[89] | 1 | /******************************************************************** |
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| 2 | * COPYRIGHT LIP6 2014 |
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| 3 | *-----------------------------------------------------------------*/ |
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| 4 | /** |
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| 5 | * @file stream_merger.v |
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| 6 | * @brief Receives time-stamped {Downscaled RAW Video, Compressed Video, Raw EXG, Compressed EXG, Compressed Audio) |
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| 7 | * and sends them to tramission Card (exptected to be via HSMC) |
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| 8 | * |
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| 9 | * This module receives three components of SmartEEG data. |
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| 10 | * 1- Time-stamped downscaled RAW (for live privew) and Compressed Video from the Video coder via AvalonST sinks. |
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| 11 | * 2- Time stamped compressed Audio via AvalonST sink |
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| 12 | * 3- Time stamped RAW and Compressed EXG data via AvalonST sinks |
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| 13 | * It transmits these data channels to transmitter card (ARM-based CycloneV FPGA SocKit board connected via HSMC) |
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| 14 | * |
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| 15 | * @author S. Z. Ahmed <syed-zahid.ahmed@lip6.fr> |
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| 16 | * @author L. Lambert <laurent.lambert@lip6.fr> |
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| 17 | * @date Fri. 28 Feb. 2014 |
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| 18 | * |
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| 19 | * Revision History |
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| 20 | * @version V1.0 Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui} |
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| 21 | * |
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| 22 | *******************************************************************/ |
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[83] | 23 | |
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| 24 | `timescale 1 ps / 1 ps |
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| 25 | module stream_merger #( |
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| 26 | parameter AUTO_CLOCK_CLOCK_RATE = "-1" |
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| 27 | ) ( |
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| 28 | input wire clk, // clock.clk |
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| 29 | input wire reset, // reset.reset |
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| 30 | input wire [7:0] avs_ctrl_address, // ctrl.address |
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| 31 | input wire avs_ctrl_read, // .read |
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| 32 | output wire [31:0] avs_ctrl_readdata, // .readdata |
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| 33 | input wire avs_ctrl_write, // .write |
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| 34 | input wire [31:0] avs_ctrl_writedata, // .writedata |
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| 35 | output wire avs_ctrl_waitrequest, // .waitrequest |
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| 36 | input wire [31:0] asi_raw_video_data, // raw_video.data |
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| 37 | output wire asi_raw_video_ready, // .ready |
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| 38 | input wire asi_raw_video_valid, // .valid |
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| 39 | input wire [31:0] asi_raw_exg_data, // raw_exg.data |
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| 40 | output wire asi_raw_exg_ready, // .ready |
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| 41 | input wire asi_raw_exg_valid, // .valid |
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| 42 | input wire [31:0] asi_comp_video_data, // comp_video.data |
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| 43 | output wire asi_comp_video_ready, // .ready |
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| 44 | input wire asi_comp_video_valid, // .valid |
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| 45 | input wire [31:0] asi_comp_exg_data, // comp_exg.data |
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| 46 | output wire asi_comp_exg_ready, // .ready |
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| 47 | input wire asi_comp_exg_valid, // .valid |
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| 48 | input wire [31:0] asi_comp_audio_data, // comp_audio.data |
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| 49 | output wire asi_comp_audio_ready, // .ready |
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| 50 | input wire asi_comp_audio_valid // .valid |
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| 51 | ); |
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| 52 | |
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| 53 | // TODO: Auto-generated HDL template |
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| 54 | |
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| 55 | assign avs_ctrl_waitrequest = 1'b0; |
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| 56 | |
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| 57 | assign avs_ctrl_readdata = 32'b00000000000000000000000000000000; |
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| 58 | |
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| 59 | assign asi_in0_ready = 1'b0; |
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| 60 | |
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| 61 | endmodule |
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