source: PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro.v @ 83

// synchro.v

// This file was auto-generated as a prototype implementation of a module
// created in component editor.  It ties off all outputs to ground and
// ignores all inputs.  It needs to be edited to make it do something
// useful.
// 
// This file will not be automatically regenerated.  You should check it in
// to your version control system if you want to keep it.

`timescale 1 ps / 1 ps
module synchro (
                input  wire [7:0]  avs_s0_address,        //           s0.address
                input  wire        avs_s0_read,           //             .read
                output wire [31:0] avs_s0_readdata,       //             .readdata
                input  wire        avs_s0_write,          //             .write
                input  wire [31:0] avs_s0_writedata,      //             .writedata
                output wire        avs_s0_waitrequest,    //             .waitrequest
                input  wire        clk,                   //        clock.clk
                input  wire        reset,                 //        reset.reset
                output wire        video_trigger,         // conduit_sync.export
                output wire        etis_sync_clock,       //             .export
                output wire        etis_sync_clock_start,  //             .export
                output wire [31:0] aso_ts_data,      // ts.data
                input  wire        aso_ts_ready,     //           .ready
                output wire        aso_ts_valid      //           .valid
        );

        // TODO: Auto-generated HDL template

        assign avs_s0_waitrequest = 1'b0;

        assign avs_s0_readdata = 32'b00000000000000000000000000000000;

        assign video_trigger = 1'b0;

        assign etis_sync_clock_start = 1'b0;

        assign etis_sync_clock = 1'b0;

endmodule