source: PROJECT_SMART_EEG/trunk/hw/sync_sys/synchro @ 87

Name Size Rev Age Author Last Change
../
synchro.v 1.6 KB ​ 84   12 years lambert Adding hierarchical subdirectory for every component
synchro_hw.tcl 5.0 KB ​ 87   12 years lambert Adding generation simulation support for verilog
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