source: PROJECT_SMART_EEG/trunk/hw/sync_sys/video_codec/video_codec_hw.tcl

Last change on this file was 87, checked in by lambert, 10 years ago

Adding generation simulation support for verilog
File size: 7.2 KB
Line 
1# TCL File Generated by Component Editor 13.1
2# Mon Mar 03 15:34:59 CET 2014
3# DO NOT MODIFY
4
5
6#
7# video_codec "video_codec" v1.0
8#  2014.03.03.15:34:59
9#
10#
11
12#
13# request TCL package from ACDS 13.1
14#
15package require -exact qsys 13.1
16
17
18#
19# module video_codec
20#
21set_module_property DESCRIPTION ""
22set_module_property NAME video_codec
23set_module_property VERSION 1.0
24set_module_property INTERNAL false
25set_module_property OPAQUE_ADDRESS_MAP true
26set_module_property GROUP smartEEG
27set_module_property AUTHOR ""
28set_module_property DISPLAY_NAME video_codec
29set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
30set_module_property EDITABLE true
31set_module_property ANALYZE_HDL AUTO
32set_module_property REPORT_TO_TALKBACK false
33set_module_property ALLOW_GREYBOX_GENERATION false
34
35
36#
37# file sets
38#
39add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
40set_fileset_property QUARTUS_SYNTH TOP_LEVEL video_codec
41set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
42add_fileset_file video_codec.v VERILOG PATH video_codec.v TOP_LEVEL_FILE
43
44add_fileset SIM_VERILOG SIM_VERILOG "" ""
45set_fileset_property SIM_VERILOG TOP_LEVEL video_codec
46set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
47add_fileset_file video_codec.v VERILOG PATH video_codec.v
48
49
50#
51# parameters
52#
53
54
55#
56# display items
57#
58
59
60#
61# connection point clock
62#
63add_interface clock clock end
64set_interface_property clock clockRate 0
65set_interface_property clock ENABLED true
66set_interface_property clock EXPORT_OF ""
67set_interface_property clock PORT_NAME_MAP ""
68set_interface_property clock CMSIS_SVD_VARIABLES ""
69set_interface_property clock SVD_ADDRESS_GROUP ""
70
71add_interface_port clock clk clk Input 1
72
73
74#
75# connection point reset
76#
77add_interface reset reset end
78set_interface_property reset associatedClock clock
79set_interface_property reset synchronousEdges DEASSERT
80set_interface_property reset ENABLED true
81set_interface_property reset EXPORT_OF ""
82set_interface_property reset PORT_NAME_MAP ""
83set_interface_property reset CMSIS_SVD_VARIABLES ""
84set_interface_property reset SVD_ADDRESS_GROUP ""
85
86add_interface_port reset reset reset Input 1
87
88
89#
90# connection point ctrl
91#
92add_interface ctrl avalon end
93set_interface_property ctrl addressUnits WORDS
94set_interface_property ctrl associatedClock clock
95set_interface_property ctrl associatedReset reset
96set_interface_property ctrl bitsPerSymbol 8
97set_interface_property ctrl burstOnBurstBoundariesOnly false
98set_interface_property ctrl burstcountUnits WORDS
99set_interface_property ctrl explicitAddressSpan 0
100set_interface_property ctrl holdTime 0
101set_interface_property ctrl linewrapBursts false
102set_interface_property ctrl maximumPendingReadTransactions 0
103set_interface_property ctrl readLatency 0
104set_interface_property ctrl readWaitTime 1
105set_interface_property ctrl setupTime 0
106set_interface_property ctrl timingUnits Cycles
107set_interface_property ctrl writeWaitTime 0
108set_interface_property ctrl ENABLED true
109set_interface_property ctrl EXPORT_OF ""
110set_interface_property ctrl PORT_NAME_MAP ""
111set_interface_property ctrl CMSIS_SVD_VARIABLES ""
112set_interface_property ctrl SVD_ADDRESS_GROUP ""
113
114add_interface_port ctrl avs_ctrl_address address Input 8
115add_interface_port ctrl avs_ctrl_read read Input 1
116add_interface_port ctrl avs_ctrl_readdata readdata Output 32
117add_interface_port ctrl avs_ctrl_write write Input 1
118add_interface_port ctrl avs_ctrl_writedata writedata Input 32
119add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1
120set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
121set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
122set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
123set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
124
125
126#
127# connection point raw_video
128#
129add_interface raw_video avalon_streaming end
130set_interface_property raw_video associatedClock clock
131set_interface_property raw_video associatedReset reset
132set_interface_property raw_video dataBitsPerSymbol 8
133set_interface_property raw_video errorDescriptor ""
134set_interface_property raw_video firstSymbolInHighOrderBits true
135set_interface_property raw_video maxChannel 0
136set_interface_property raw_video readyLatency 0
137set_interface_property raw_video ENABLED true
138set_interface_property raw_video EXPORT_OF ""
139set_interface_property raw_video PORT_NAME_MAP ""
140set_interface_property raw_video CMSIS_SVD_VARIABLES ""
141set_interface_property raw_video SVD_ADDRESS_GROUP ""
142
143add_interface_port raw_video asi_raw_video_data data Input 32
144add_interface_port raw_video asi_raw_video_ready ready Output 1
145add_interface_port raw_video asi_raw_video_valid valid Input 1
146
147
148#
149# connection point comp_video
150#
151add_interface comp_video avalon_streaming start
152set_interface_property comp_video associatedClock clock
153set_interface_property comp_video associatedReset reset
154set_interface_property comp_video dataBitsPerSymbol 8
155set_interface_property comp_video errorDescriptor ""
156set_interface_property comp_video firstSymbolInHighOrderBits true
157set_interface_property comp_video maxChannel 0
158set_interface_property comp_video readyLatency 0
159set_interface_property comp_video ENABLED true
160set_interface_property comp_video EXPORT_OF ""
161set_interface_property comp_video PORT_NAME_MAP ""
162set_interface_property comp_video CMSIS_SVD_VARIABLES ""
163set_interface_property comp_video SVD_ADDRESS_GROUP ""
164
165add_interface_port comp_video aso_comp_video_ready ready Input 1
166add_interface_port comp_video aso_comp_video_data data Output 32
167add_interface_port comp_video aso_comp_video_valid valid Output 1
168
169
170#
171# connection point raw_video_ds
172#
173add_interface raw_video_ds avalon_streaming start
174set_interface_property raw_video_ds associatedClock clock
175set_interface_property raw_video_ds associatedReset reset
176set_interface_property raw_video_ds dataBitsPerSymbol 8
177set_interface_property raw_video_ds errorDescriptor ""
178set_interface_property raw_video_ds firstSymbolInHighOrderBits true
179set_interface_property raw_video_ds maxChannel 0
180set_interface_property raw_video_ds readyLatency 0
181set_interface_property raw_video_ds ENABLED true
182set_interface_property raw_video_ds EXPORT_OF ""
183set_interface_property raw_video_ds PORT_NAME_MAP ""
184set_interface_property raw_video_ds CMSIS_SVD_VARIABLES ""
185set_interface_property raw_video_ds SVD_ADDRESS_GROUP ""
186
187add_interface_port raw_video_ds aso_raw_video_ds_ready ready Input 1
188add_interface_port raw_video_ds aso_raw_video_ds_valid valid Output 1
189add_interface_port raw_video_ds aso_raw_video_ds_data data Output 32
190
191
192#
193# connection point ts
194#
195add_interface ts avalon_streaming end
196set_interface_property ts associatedClock clock
197set_interface_property ts associatedReset reset
198set_interface_property ts dataBitsPerSymbol 8
199set_interface_property ts errorDescriptor ""
200set_interface_property ts firstSymbolInHighOrderBits true
201set_interface_property ts maxChannel 0
202set_interface_property ts readyLatency 0
203set_interface_property ts ENABLED true
204set_interface_property ts EXPORT_OF ""
205set_interface_property ts PORT_NAME_MAP ""
206set_interface_property ts CMSIS_SVD_VARIABLES ""
207set_interface_property ts SVD_ADDRESS_GROUP ""
208
209add_interface_port ts asi_ts_data data Input 32
210add_interface_port ts asi_ts_ready ready Output 1
211add_interface_port ts asi_ts_valid valid Input 1
212
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