Index: PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/wave4.do
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/wave4.do	(revision 113)
+++ PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/wave4.do	(revision 113)
@@ -0,0 +1,130 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /mpi_test/clk
+add wave -noupdate /mpi_test/reset
+add wave -noupdate /mpi_test/result
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/State
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/whole
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_in
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_out
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/ram_wr
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_rd
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_wr
+add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ram_address
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_in
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_out
+add wave -noupdate /mpi_test/clk
+add wave -noupdate /mpi_test/reset
+add wave -noupdate /mpi_test/result
+add wave -noupdate /mpi_test/clk
+add wave -noupdate /mpi_test/reset
+add wave -noupdate /mpi_test/result
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ex2_state
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ack_state
+add wave -noupdate /mpi_test/clk
+add wave -noupdate /mpi_test/reset
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/ex1_state
+add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/src_address
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_data
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_wr_en
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/dma_rd_grant
+add wave -noupdate /mpi_test/result
+add wave -noupdate /mpi_test/clk
+add wave -noupdate /mpi_test/reset
+add wave -noupdate /mpi_test/result
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_rd
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_wr
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_whole
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_done
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_BitMask
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_BitVal
+add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_address
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_in
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_out
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_rd
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_wr
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/dma_rd_request
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/dma_wr_request
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/dma_rd_grant
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/dma_wr_grant
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/ex1_state
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/Snd_Start
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/Snd_Start
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/stInit2
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/snd_start_i
+add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_data
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/n
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_wr_en
+add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/fifo_data_out
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/p_len
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/fifo_rd_en
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/fifo_empty
+add wave -noupdate /mpi_test/clk
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ex2_state
+add wave -noupdate -radix unsigned /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/P_len
+add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_data_available
+add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/dest_address
+add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/P_len
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/n
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ex2_state
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/State
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/ram_rd
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/ram_wr
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_in
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_out
+add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Inst_RAM_v/addra
+add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Inst_RAM_v/addrb
+add wave -noupdate /mpi_test/uut/PE_s(2)/S/Inst_RAM_v/dia
+add wave -noupdate /mpi_test/uut/PE_s(2)/S/Inst_RAM_v/dob
+add wave -noupdate /mpi_test/uut/PE_s(2)/S/Inst_RAM_v/wea
+add wave -noupdate /mpi_test/uut/PE_s(2)/S/Inst_RAM_v/ena
+add wave -noupdate /mpi_test/uut/PE_s(2)/S/Inst_RAM_v/enb
+add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/n
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/n_i
+add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/P_len
+add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/P_len_i
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ex2_fsm_logic/delai
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_wr_request
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_wr_grant
+add wave -noupdate /mpi_test/result
+add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/sram
+add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/Libr
+add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/RunState
+add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/ct_state
+add wave -noupdate /mpi_test/uut/PE_s(2)/S/HT_task/RunState
+add wave -noupdate /mpi_test/uut/PE_s(2)/S/HT_task/ct_state
+add wave -noupdate /mpi_test/uut/dyn_HT/PE_D(3)/D/HT_task/RunState
+add wave -noupdate /mpi_test/uut/dyn_HT/PE_D(4)/D/HT_task/RunState
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ex2_state
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ack_state
+add wave -noupdate /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/pop_state
+add wave -noupdate -radix unsigned /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/data_counter
+add wave -noupdate /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/fifo_read_signal
+add wave -noupdate /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/pipeline_latch_en
+add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/fifo_out_signal
+add wave -noupdate /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/fifo_empty_signal
+add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/data_out
+add wave -noupdate /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/data_out_pulse
+add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/fifo_data
+add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en
+TreeUpdate [SetDefaultTree]
+quietly WaveActivateNextPane
+WaveRestoreCursors {{Cursor 7} {32545000 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 179
+configure wave -valuecolwidth 155
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {32512840 ps} {32577160 ps}