Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs/cg.xmsgs
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs/cg.xmsgs	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs/cg.xmsgs	(revision 115)
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="sim" num="0" delta="new" >Generating component instance &apos;<arg fmt="%s" index="1">mem_4k8</arg>&apos; of &apos;<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>&apos; from &apos;<arg fmt="%s" index="3">C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>&apos;.
+</msg>
+
+</messages>
+
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs/pn_parser.xmsgs
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs/pn_parser.xmsgs	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs/pn_parser.xmsgs	(revision 115)
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/MPI_HCL/Test_Timer/ipcore_dir/mem_4k8.vhd&quot; into library work</arg>
+</msg>
+
+</messages>
+
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.asy
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.asy	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.asy	(revision 115)
@@ -0,0 +1,41 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 blk_mem_gen_v6_2
+RECTANGLE Normal 32 32 544 1376
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName addra[12:0]
+PINATTR Polarity IN
+LINE Wide 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName dina[7:0]
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName ena
+PINATTR Polarity IN
+LINE Wide 0 208 32 208
+PIN 0 208 LEFT 36
+PINATTR PinName wea[0:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName clka
+PINATTR Polarity IN
+LINE Wide 0 432 32 432
+PIN 0 432 LEFT 36
+PINATTR PinName addrb[12:0]
+PINATTR Polarity IN
+LINE Normal 0 496 32 496
+PIN 0 496 LEFT 36
+PINATTR PinName enb
+PINATTR Polarity IN
+LINE Normal 0 624 32 624
+PIN 0 624 LEFT 36
+PINATTR PinName clkb
+PINATTR Polarity IN
+LINE Wide 576 368 544 368
+PIN 576 368 RIGHT 36
+PINATTR PinName doutb[7:0]
+PINATTR Polarity OUT
+
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.gise
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.gise	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.gise	(revision 115)
@@ -0,0 +1,32 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="blk_mem_gen_v6_2.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="blk_mem_gen_v6_2.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VHO" xil_pn:name="blk_mem_gen_v6_2.vho" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_v6_2_readme.txt" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.ngc
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.ngc	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.ngc	(revision 115)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$33g40<,[o}e~g`n;"2*731&=$:,)<4-0384<=789:;<=>?4193456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0121?545392:86?<:HLSQQ<flmxj0<<50?37?45=AGZ^X7okds`?57<768>0=94FNQWW>DBCZH6:?7>115920?OIX\^1MIJ]B=30>58682;1EC^ZT;ufe96=87;97><5IORVP?BNI59:6=0>2:11>LHW]]0OEO2<1;2=56=4:3E^X][[:EMB867=87;87><5OTVSQQ<CGK68=7>11097>LHW]]0OE]O33;2=54=32@D[YY4KIQ@?7?69991?6D@_UU8TAD:4294:<6:5IORVP?QBJ591<3?=;58LQQVR\3ND\L2<:1<26>2=G\^[YY4KOQ@?7?69m2<x`u::cre061+4:22;=<57:HLSQQ<cagk7;7>1129;>JSSX\^1hb{{b=594;><IMNYM1>19:CG@WG;99427LJKR@>25;?<IMNYM1?=>c9B@ATF4891<374AEFQE974611JHI\N<0<;?DBCZH69255NDEPB868?3HNO^L2;>99B@ATF4<437LJKR@>5:==FLMXJ0:07;@FGVD:?611JHI\N<8<;?DBCZK6;245NDEPA846912KOH_L310<:?DBCZK6:>3l4AEFQF97429427LJKRC>27;><IMNYN1?18:CG@WD;:720MIJ]B=1=<>GCL[H78364AEFQF93902KOH_L36?:8EABUJ5=546OKDS@?<;><IMNYN1713:COH==E]ZUBBKA>;B08G@753JBNOFQCIBGMW@YSQYO?7NBD079@HN7?8?1H@F<8049@HN4_02IGG?V>8178GIM>8=1H@FO:;BNHE41<KEAJ=I<8;BNHE4B3?2IGGL?K859@HND23JF@N<;4CMI@50=DDBN:96MCKET`?FJLL_UOE[GKE49@HN@_02IGGKV>81;8GJKJA]^NH<:4CNPF[BCIM[K_EB@PIODL3>EUMH^NH<5Kc:FBPDYPAM^CSLm4D@VB[ROC\AUI:6JFA=2=3>BNI5;;2:5KI@>25;1<L@K7=?08;EKB8459?2NBM1?;>69GMD:6=7=0HDO317<4?AOF48=5;6JFA=3;:2=CAH6:5384DHC?5;1<L@K7>=08;EKB8779?2NBM1<=>69GMD:5;7=0HDO325<4?AOF4;?5;6JFA=05:2=CAH69;394DHC?6=803MCJ0?716:FJE949?2NBM1=?>89GMD:493:5;6JFA=12:3=CAH682;5KI@>7:3=CAH6>2;5KI@>5:3=CAH6<2;5KI@>;:3=CAH622;5KIC>3:2=CAK6:<394DH@?54803MCI0<<17:FJF9746>1OEO2>4?58@LD;9<4<7IGM<04=3>BNJ5;<2:5KIC>2<;1<L@H7=409;EKA84803MCI0?>17:FJF9466>1OEO2=2?58@LD;::4<7IGM<36=3>BNJ58>2:5KIC>12;1<L@H7>:08;EKA87>9?2NBN1<6>79GMG:56>1OEO2<0?;8@LD;;80;2:5KIC>05;0<L@H7?384DH@?0;0<L@H79384DH@?2;0<L@H7;384DH@?<;0<L@H75394DHRB85803MC[M1?17:FJTD:5601OE]O33;2=3>BNXH682:5KIQ@?4;1<L@ZI0<08;EKSF94912NB\O2<:1<4?AOWJ595:6J@A=2=3>BHI5;;2:5KO@>25;1<LFK7=?08;EMB8459?2NDM1?;>69GKD:6=7=0HBO317<4?AIF48=5;6J@A=3;:2=CGH6:5384DNC?5;1<LFK7>=08;EMB8779?2NDM1<=>69GKD:5;7=0HBO325<4?AIF4;?5;6J@A=05:2=CGH69;394DNC?6=803MEJ0?716:FLE949?2NDM1=?>89GKD:493:5;6J@A=12:3=CGH682;5KO@>7:3=CGH6>2;5KO@>5:3=CGH6<2;5KO@>;:3=CGH622:5KO@]QAB0<LFH7<394DN@?55803MEI0<?17:FLF9756>1OCO2>3?58@JD;9=4<7IAM<07=3>BHJ5;=2:5KOC>23;1<LFH7=508;EMA84?9>2NDN1?17:FLF9476>1OCO2=1?58@JD;:;4<7IAM<31=3>BHJ58?2:5KOC>11;1<LFH7>;08;EMA8719?2NDN1<7>69GKG:517<0HBL32?58@JD;;9427IAM<2394;1<LFH7?<09;EMA86813MEI0909;EMA80813MEI0;09;EMA82813MEI0509;EMA8<803MEIS_KH7:FLTD:76>1OC]O31?58@JVF4;427IA_A=194;1<LFZJ0>08;EMSF969?2ND\O2>>69GKUD;:730HB^M<283:2=CGYH7?3=4EOC0?@HEj2OES_][R@O\Eg=BFVXXX_OB_C78BDJTM8:0JI9:B812AF03I18;?6HKE09D7>AIL;1B<?5F139J67=N;;1B8?5F599JJLRWW9:37D@FTQ]35==NF@^[S=<7;HLJPUY7;11BBDZ__16;?LHN\YU;955FNHVS[50?3@DBX]Q?789JJLRT\H^N;6GAIU]342=NF@^T<<94IOKW[5403@DBXR><7:KMMQY7<>1BBDZP0458MKOSW9<<7D@FT^243>OIA]U;4:5FNHV\4<1<AGC_S=O8;HLJPZ6E?2CEEYQ?C69JJLRX8M=0ECG[_1G4?LHN\V:M;6GAIU]242=NF@^T=<94IOKW[4403@DBXR?<7:KMMQY6<>1BBDZP1458MKOSW8<<7D@FT^343>OIA]U:4:5FNHV\5<1<AGC_S<O8;HLJPZ7E?2CEEYQ>C69JJLRX9M=0ECG[_0G4?LHN\V;M;6GAIU]142=NF@^T><94IOKW[7403@DBXR<<7:KMMQY5<>1BBDZP2458MKOSW;<<7D@FT^043>OIA]U94:5FNHV\6<1<AGC_S?O8;HLJPZ4E?2CEEYQ=C69JJLRX:M=0ECG[_3G4?LHN\V8M;6GAIU]042=NF@^T?<94IOKW[6403@DBXR=<7:KMMQY4<>1BBDZP3458MKOSW:<<7D@FT^143>OIA]U84:5FNHV\7<1<AGC_S>O8;HLJPZ5E?2CEEYQ<C69JJLRX;M=0ECG[_2G4?LHN\V9M:6GAIU]B2>OIA]UI56GAIU]EMIC13EEJHHJ9;MM@O@B03EELENOC4:NVP62<D\^=o6CnjnpUawunggi0Ad``rWgqwlii:2D:;6@JTVMQO1=IGGO:7B64O/55|aYK<2ZJ^Yo4PHL\FPUNLQh0\D@PBTQMEHC>3YATDA[[NL48TVBHFL;0]l5]AL@22GQBZ?1YIJMJA79QABEBJ=1Y_YO;;SQWF2=U[]^R\Hk4RRV\TWOHZ@^RSLk4RRV\TWOHZ@^RSO?>;RJQABYBP]XJOYQAGBg8WMTBOVGBBR]FZD30?VOJWJEG@D]FOO]@L@ELi2YBARJJVHAF2>UH][IN46]_ASVBJ31<[[\J@RO8;RPUEIYE>2Y_MY[\4:QZJF2<\PZN9i5Z0.zppZdkcVgnaRijndpbpjt(ogke{kmmf,meqoqmVhggRcjm^efj*pfd`n%o~z}/icp[hsWk$I#@czx^flqqYj}q;:9i5Z0.zppZdkcVgnaRijndpbpjt(ogke{kmmf,meqoqmVhggRcjm^efj*pfd`n%o~z}/icp[hsWk$I#@czx^flqqYj}q8:9i5Z0.zppZdkcVgnaRijndpbpjt(ogke{kmmf,meqoqmVhggRcjm^efj*pfd`n%o~z}/icp[hsWk$I#@czx^flqqYj}q9:9i5Z0.zppZdkcVgnaRijndpbpjt(ogke{kmmf,meqoqmVhggRcjm^efj*pfd`n%o~z}/icp[hsWk$I#@czx^flqqYj}q>:9i5Z0.zppZdkcVgnaRijndpbpjt(ogke{kmmf,meqoqmVhggRcjm^efj*pfd`n%o~z}/icp[hsWk$I#@czx^flqqYj}q?:9i5Z0.zppZdkcVgnaRijndpbpjt(ogke{kmmf,meqoqmVhggRcjm^efj*pfd`n%o~z}/icp[hsWk$I#@czx^flqqYj}q<:9i5Z0.zppZdkcVgnaRijndpbpjt(ogke{kmmf,meqoqmVhggRcjm^efj*pfd`n%o~z}/icp[hsWk$I#@czx^flqqYj}q=:9i5Z0.zppZdkcVgnaRijndpbpjt(ogke{kmmf,meqoqmVhggRcjm^efj*pfd`n%o~z}/icp[hsWk$I#@czx^flqqYj}q2:945Z0.zppZdkcVgnaRijndpbpjt(ogke{kmmf,meqoqmVhggRcjm^efj*pfd`n%o~z}/icp[hsWk$I#~kc_qksa979=01^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#eo|_lw{[g(E'zogS}ge=0=1==R8&rxxRlck^ofiZabflxjxb| gocwmsceen$emygye^`ooZkbeVmnb"xnlhf-gvru'akxS`{w_c,A+vckWyc{iR?:8:W3+}usWkf`S`kb_fgmawgsg{%lblzfvd`nc+hf|`|nSobd_lgn[bci'kgei lsup,lduXe|rTn#L sdn\tlvbW;>=7X> xrv\fimXelgTkh`jr`vlv*aii}c}ioch.ocwmscXjeaTahcPgdl,rdjnl'ixx!`uu373>S7'qySobd_lgn[bcim{kc!hn`vjr`djo'djxdxj_cnh[hcjWnoe#{ocie,`wqt(g|~:=994U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.mvp773?2_;#u}{_cnh[hcjWnoeio{os-djdrn~lhfk#`nthtf[gjlWdofSjka/wcoma(d{}x$cxz<1558Q5){}Ui`fQbel]dakcui}ey#j`nthtffha)fh~bzhQmlj]nahY`mg%}magk.bqwv*ir|=;?;6[?/yqw[gjlWdofSjkaescwkw)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+sgkam$hy| otv6511<]9%syQmlj]nahY`mgoymya}/flbplpbjdm%blzfvd]ahnYjmdUlic!yamkg*fusz&e~x;?;7:W3+}usWkf`S`kb_fgmawgsg{%lblzfvd`nc+hf|`|nSobd_lgn[bci'kgei lsup,kpr09><0Y=!wsu]ahnYjmdUlick}aumq+bhf|`|nn`i!n`vjr`YedbUfi`Qheo-ueioc&jy~"|nmmmlt^6Z&{kf"!|6^llmkos&{kf#^J_.RKNTICXX[CF=5 }al:3?P6(pz~TnaePmdo\c`hbzh~d~"iaaukuagk`&gke{kPbmi\i`kXold$zlbfd/appw)uidfdc}U?]/pbi+t({?Uecd`ft/pbi*UCX'YBA]BJ_QPJI4>)zhgTec}zl`vf4=6<]9%syQmlj]nahY`mgoymya}/flbplpbjdm%blzfvd]ahnYjmdUlic!yamkg*fusz&xjaaa`pZ2^*wgj&{%x:R``iokw*wgj'ZN["^GBPMG\TWOJ91$ym`Qfnrwoeqc4=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf969=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf979=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf949=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf959=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf929=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf939=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf909=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf919=11^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPeoc6<>S7'qySobd_lgn[bcim{kc!hn`vjr`djo'djxdxj_cnh[hcjWnoe#{ocie,`wqt(zhggcb~T0\,qeh(uidUnbo99;T2,|vrXjeaTahcPgdlfvdrhz&memygyecod*kgsaoTnaePmdo\c`h(~hfbh#m|ts-qehjhgyQ:Q#|nm/p,w3Yig`dbx#|nm.QGT+UNEYFNS]\FM0:-vdk?82_;#u}{_cnh[hcjWnoeio{os-djdrn~lhfk#`nthtf[gjlWdofSjka/wcoma(d{}x$~lcconrX5X(uid$y#~8Pnnkmmq(uid%XH] \ILROAZVUAD;3"ob_hlpqigsm82;7X> xrv\fimXelgTkh`jr`vlv*aii}c}ioch.ocwmscXjeaTahcPgdl,rdjnl'ixx!}alnlku]6U'xja#| s7]mklhn|'xja"]KP/QJIUJBWYXBA<6!r`o\mkurdh~n>8j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6;28j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6:28j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6928j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6828j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6?28j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6>28j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6=28j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6<2864U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[`hf=11^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_4[)zhg%~lcPeo`42>S7'qySobd_lgn[bcim{kc!hn`vjr`djo'djxdxj_cnh[hcjWnoe#{ocie,`wqt(zhggcb~T2\,qeh(u'z<Tbbgaiu,qeh)TLY$XE@^CE^RQMH7?&{kf4=5Z0.zppZdkcVgnaRijndpbpjt(ogke{kmmf,meqoqmVhggRcjm^efj*pfd`n%o~z}/scnhjiwS;W%~lc!r.q5[kinf`~%~lc SER-WLKWDLU[^DC>8/pbiZoi{|fjxh?70:W3+}usWkf`S`kb_fgmawgsg{%lblzfvd`nc+hf|`|nSobd_lgn[bci'kgei lsup,vdkkgfzP>P }al,q+v0Xffceey }al-P@U(TADZGIR^]IL3;*wgjW`dxyao{e37g?P6(pz~TnaePmdo\c`hbzh~d~"iaaukuagk`&gke{kPbmi\i`kXold$zlbfd/appw)uidfdc}U=]/pbi+tfeVndyyl30?7g?P6(pz~TnaePmdo\c`hbzh~d~"iaaukuagk`&gke{kPbmi\i`kXold$zlbfd/appw)uidfdc}U=]/pbi+tfeVndyyl31?7g?P6(pz~TnaePmdo\c`hbzh~d~"iaaukuagk`&gke{kPbmi\i`kXold$zlbfd/appw)uidfdc}U=]/pbi+tfeVndyyl32?7g?P6(pz~TnaePmdo\c`hbzh~d~"iaaukuagk`&gke{kPbmi\i`kXold$zlbfd/appw)uidfdc}U=]/pbi+tfeVndyyl33?7g?P6(pz~TnaePmdo\c`hbzh~d~"iaaukuagk`&gke{kPbmi\i`kXold$zlbfd/appw)uidfdc}U=]/pbi+tfeVndyyl34?7g?P6(pz~TnaePmdo\c`hbzh~d~"iaaukuagk`&gke{kPbmi\i`kXold$zlbfd/appw)uidfdc}U=]/pbi+tfeVndyyl35?7g?P6(pz~TnaePmdo\c`hbzh~d~"iaaukuagk`&gke{kPbmi\i`kXold$zlbfd/appw)uidfdc}U=]/pbi+tfeVndyyl36?7g?P6(pz~TnaePmdo\c`hbzh~d~"iaaukuagk`&gke{kPbmi\i`kXold$zlbfd/appw)uidfdc}U=]/pbi+tfeVndyyl37?7;?P6(pz~TnaePmdo\c`hbzh~d~"iaaukuagk`&gke{kPbmi\i`kXold$zlbfd/appw)uidfdc}U=]/pbi+tfeVoem864U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR8V"ob.scn[`he??1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_6[)zhg%~"}9_omjjlr)zhg$_I^!SHOSH@YWZ@G:4#|nm928Q5){}Ui`fQbel]dakcui}ey#j`nthtffha)fh~bzhQmlj]nahY`mg%}magk.bqwv*tfeeed|V=R.scn*w)t>Vddecg{.scn+VBW&ZCF\AKPPSKN5=(uidUbb~{caug3<5=R8&rxxRlck^ofiZabflxjxb| gocwmsceen$emygye^`ooZkbeVmnb"xnlhf-gvru'{kf`ba[2_-vdk)z&y=Scafnhv-vdk([MZ%_DC_LD]SVLK60'xjaRgastnbp`52l2_;#u}{_cnh[hcjWnoeio{os-djdrn~lhfk#`nthtf[gjlWdofSjka/wcoma(d{}x$~lcconrX7X(uid$ym`Qkotva8582l2_;#u}{_cnh[hcjWnoeio{os-djdrn~lhfk#`nthtf[gjlWdofSjka/wcoma(d{}x$~lcconrX7X(uid$ym`Qkotva8482l2_;#u}{_cnh[hcjWnoeio{os-djdrn~lhfk#`nthtf[gjlWdofSjka/wcoma(d{}x$~lcconrX7X(uid$ym`Qkotva8782l2_;#u}{_cnh[hcjWnoeio{os-djdrn~lhfk#`nthtf[gjlWdofSjka/wcoma(d{}x$~lcconrX7X(uid$ym`Qkotva8682l2_;#u}{_cnh[hcjWnoeio{os-djdrn~lhfk#`nthtf[gjlWdofSjka/wcoma(d{}x$~lcconrX7X(uid$ym`Qkotva8182l2_;#u}{_cnh[hcjWnoeio{os-djdrn~lhfk#`nthtf[gjlWdofSjka/wcoma(d{}x$~lcconrX7X(uid$ym`Qkotva8082l2_;#u}{_cnh[hcjWnoeio{os-djdrn~lhfk#`nthtf[gjlWdofSjka/wcoma(d{}x$~lcconrX7X(uid$ym`Qkotva8382l2_;#u}{_cnh[hcjWnoeio{os-djdrn~lhfk#`nthtf[gjlWdofSjka/wcoma(d{}x$~lcconrX7X(uid$ym`Qkotva828202_;#u}{_cnh[hcjWnoeio{os-djdrn~lhfk#`nthtf[gjlWdofSjka/wcoma(d{}x$~lcconrX7X(uid$ym`Qjn`7;?P6(pz~TnaePmdo\c`hbzh~d~"iaaukuagk`&gke{kPbmi\i`kXold$zlbfd/appw)uidfdc}U<]/pbi+tfeVoenn5ZSDP\RLUNJEO27[GJW^VZT@0<_LK7<384WDC?5;0<_LK7>364WDC?7?69>2]NM1=16:UFF969>2]NN1?16:UFF94902]NN1=50?48S@D;;7h0[_G[E^DJVVRd3^XBXHQBOEG\Ef=PZ@^NS@AKE^@2`>^ND@DS!UJM 1,2$VRRJ):%=-O\CHK5?]USD@H<7U][_FLGf>^XKFXNSD@IO79[`gYNlo1SheQ_rhoUawungg;;7Ujb_LcikwPbzzcdb<>4Xeo\Ilhhz_oydaa3:Zpp6=^mz?>7RQPXMLN[ZY7WVU^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#b{{2076?ZYXPEDFSRQ>_^]V4*~t|VhggRcjm^efj`tf|fx$kco{iwgaib(ii}c}iRlck^ofiZabf&|j`dj!crvq+jss=8?>7RQPXMLN[ZY5WVU^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#b{{7076?ZYXPEDFSRQ<_^]V4*~t|VhggRcjm^efj`tf|fx$kco{iwgaib(ii}c}iRlck^ofiZabf&|j`dj!crvq+jss;820mij}a=2==>gcl{k7==06;`fgvd:697h0mij}a=31>58>3hno~l2>2?:8eabui5;546okdsc?6;><imnym1=18:cg`wg;<720mij}a=7=<>gcl{k7:364aefqe91902koho38?:8eabui53546okds`?4;?<imnyn1??>89b`ate48;5n6okds`?57<7601jhi|m<00=<>gcl{h7=364aefqf94902kohl33?:8eabuj5>546okds`?1;><imnyn1818:cg`wd;?720mij}b=:=<>gcl{h75384bhlgaf7?3kf`S`kb_fgm[bcim{chSn}{rg9ahnYjmdUlicQbuy3;?gjlWdofSjka_qpjiZqnl}bT=<64bmi\i`kXoldT|gb_vkgpmY5911i`fQbel]dakYwz`gT{dj{h^12<>dkcVgnaRijn^rqmhYpam~cS9?k;cnh[hcjWnoeS}|fm^uqeuvbzVy=S<?k;cnh[hcjWnoeS}|fm^uqeuvbzVy=S??k;cnh[hcjWnoeS}|fm^uqeuvbzVy=S>?k;cnh[hcjWnoeS}|fm^uqeuvbzVy=S9h4bmi\i`kXoldTxb~>0:`ooZkbeVmnbRx9_30`?gjlWdofSjka_w4\6)&_aecet-M@RD"Dakcui}ey,<=!35c7?gjlWdofSjka_w4\6)dkcVgnaRijn^t5[7*|kVkohoPwhfwl874$jUjhi|m_vkgpm;6;%iTmai`rhvki87+kVkseRgk_vkgpm;3$jUjtdQ|l`tf[qwm4:'oRowi^vzt`;6$jUiuykPshxf9=*dWjefab`Pcmi>4)eXllljyazPd`vb95*dWmcxmobj_vcqjZdo~Vid`a3?,b]gmvgedlU|m`Pbit\vdh`m4:'oRkcacmqeqohfVnb~0J5/LRJ[MEK']oxxRZfmdp,muehzlUoe!{mq-\gb)+kVljadbv=rrbvqgi>%iTdl}Payk\ma;7$jUcm~Qjn`?2(fYoizUnbo3>,b]kevYnfcohxh|}=1.`[mgtWdofSb{{ptv\v`atWh7; nQgar]nahYh}}z~xR|jgr]a95*dWakxS`{w_nwwtprXzlmxSl3?,b]kevYj}qUdyy~zt^pfcvYe59&hSeo|_sgdg`g:8%iTdl}Prde`ag;7$jUcm~Q}suc>4)eX`hyT~~zm=1.`[mgtWzemxhml_hlsqqYumnyTm0>#c^jbwZuhn}ohoRaztqww[wc`{Vh6<!mPiokw[cokmVdjah3ao^alaZ`ndlUgcljjd-a\mkosiV|j`0>#c^kmmqdX~hf6<!mPiovfvcgdmV~r|h3?,b]okdbXagcSkgce<2/gZkbeV~r|h3>,b]nq}YwayogeckPsucdav;7$jU{~dcPtxrf94*dW{ojhRjjpuj\e8>61;&hSknd^fftqnXj42:5?"l_sgb`Zqnl}bTm06#c^pfeaYpam~cSo37,b]qwqYwz`eyeywPa<AF(fYu{}U{~da}iu{\f8EB$jUyyQ{yqg>W\HD$jUyy|nm^c>4)eXzz~ym`Qm=1.`[vojWjeg`d}foo]`l`el5HFG nQzsd]a}qcXlk6=!mPurg\f|rbW~oi1<"l_tqf[acai|fSio{a<2/gZstmVoho0>#c^wpaZuhn}oho0>#c^ufeZqnl}b6=!mPwd`\slbs`4;'oRy}iug\``vs`Vk64<7=,b]tvlrbWmo{xeQm=93:6)eX{ciRc`dd]b9RTN\LUME_][,b]tvlrbWdeoiRl2WSKWAZ@NZZ^'oRy}iug\slbs`Vk64!mPwskwaZqnl}bTn06#c^zgasodmokfeaw2sqcqpdh1u;>0naePmdo\c`hX~?U9 obd_lgn[bciW<T>!ur159ahnYjmdUlicQy6^0\|vr6;2hggRcjm^kmtprXjeehg<:4bmi\i`kXg|~{yyQmlnah0>ekch>0oaem7:fjjd:76>1oeco31?58`lhf4;4<7igaa=1=3>bnfh6?2:5kioc?1;1<l`dj0;06;ekme91=87=0hd`n<6<;?air|k6;255kotva848?3me~xo2=>99gkpre4:437iaztc>7:==cg|~i0807;emvpg:16h1ocxzm<683:==cg|~i0:0<;dlb7>cij11eknlzimf;?rcf490;2;5xe`>3:xFGx=?=7MNw1gf9B?2=9rY>>7?lf;362?74;<;;j7<87edxj4ec281e=nk56:&2gg<6k>1v_8>51bd9500=9:9>==h526:27>U6<k09=l4?:010146a2;=3=:5\51815d<728989<>i:35;5<=c9on1<7?51zQ66?7dn3;>:7?<3433b?4008;0zY?99;295?7==hqX9?4>cg8213<6;:?:<k4=7932?!7e13;?h6X>cb81p7283;0y<;>:19~ 43028<0n<hk:181b?702<kpD<l7;%35b?7al2P857;tb;595=<?2831q)?la;3ea>"4k38;<6*:1;3eb>"6>?0:7)?95;3g4>o59j0;6)?:9;02f>h6=10;76g>d883>!7213;o46`>5983?>o6l>0;6)?:9;3g<>h6=10:76g>d783>!7213;o46`>5981?>o6m;0;6)?:9;3g<>h6=10876g>e083>!7213;o46`>5987?>o6m90;6)?:9;3g<>h6=10>76g>dg83>!7213;o46`>5985?>o6ll0;6)?:9;3g<>h6=10<76g>de83>!7213;o46`>598;?>o6lj0;6)?:9;3g<>h6=10276g>dc83>!7213;o46`>598b?>o6lh0;6)?:9;3g<>h6=10i76g>d483>!7213;o46`>598`?>o58l0;6)?:9;03`>h6=10;76g=0b83>!72138;h6`>5982?>o58k0;6)?:9;03`>h6=10976g=0`83>!72138;h6`>5980?>o5800;6)?:9;03`>h6=10?76g=0983>!72138;h6`>5986?>o58>0;6)?:9;03`>h6=10=76g=0783>!72138;h6`>5984?>o6m>0;6)?:9;3f2>h6=10;76g>e483>!7213;n:6`>5982?>o6m=0;6)?:9;3f2>h6=10976g>f183>!7213;n:6`>5980?>o6mo0;6)?:9;3f2>h6=10?76g>ed83>!7213;n:6`>5986?>o6mm0;6)?:9;3f2>h6=10=76g>eb83>!7213;n:6`>5984?>o6mk0;6)?:9;3f2>h6=10376g>e`83>!7213;n:6`>598:?>o6m00;6)?:9;3f2>h6=10j76g>e983>!7213;n:6`>598a?>o6m:0;6)?:9;3f2>h6=10h76g=0583>>o5910;66g=0483>>o5900;66a=1683>!72138::6`>5983?>i59<0;6)?:9;022>h6=10:76a=1583>!72138::6`>5981?>i59:0;6)?:9;022>h6=10876a=1383>!72138::6`>5987?>i5980;6)?:9;022>h6=10>76a=1183>!72138::6`>5985?>i58o0;6)?:9;022>h6=10<76l>c883>4<729q/=;h5f99K5f><@8h37bh8:188yg70i3:187>50z&22c<a>2B:o55G1c:8 4602;1b?l4?::k0f?6=3`?86=44o07`>5<<uk;<n7>54;294~"6>o0m:6F>c99K5g><,8:<6?5f3`83>>o4j3:17d;<:188k43d2900qo?87;293?6=8r.::k4>4g9K5f><@8h37)??7;d6?l`>2900eko50;9jbg<722cmo7>5;hdg>5<<aoo1<75`14794?=zj8==6=48:183!71n3;?j6F>c99K5g><,8:<6k;4ig;94?=nnh0;66gib;29?l`d2900ekj50;9jb`<722e:984?::a523=83=1<7>t$04e>42a3A;h46F>b99'551=n<1bj44?::kee?6=3`li6=44iga94?=nnm0;66gie;29?j72=3:17pl>7583>2<729q/=;h515d8L4e?3A;i46*>068e1>oa13:17dhn:188mcd=831bjn4?::ke`?6=3`ln6=44o076>5<<uk;<?7>57;294~"6>o0:8k5G1b:8L4d?3-;;;7h:;hd:>5<<aok1<75ffc83>>oak3:17dhk:188mcc=831d=8;50;9~f415290<6=4?{%35b?73n2B:o55G1c:8 4602o?0ek750;9jbd<722cmn7>5;hd`>5<<aon1<75ffd83>>i6=<0;66sm16394?1=83:p(<8i:06e?M7d02B:n55+1159b0=nn00;66gia;29?l`e2900ekm50;9jba<722cmi7>5;n361?6=3th:;=4?:683>5}#9?l1=9h4H0a;?M7e02.:<:4i5:ke=?6=3`lj6=44ig`94?=nnj0;66gid;29?l`b2900c<;::188yg7?;3:187>50z&22c<6<l1C=n64H0`;?!77?3;<7)?:a;3g7>oa13:17dhn:188mcd=831d=8;50;9~f4>5290?6=4?{%35b?73m2B:o55G1c:8 4602?1/=8o51e18mc?=831bjl4?::kef?6=3f;>97>5;|`2<4<72=0;6=u+17d951c<@8i37E?m8:&242<13-;>m7?k2:ke=?6=3`lj6=44ig`94?=h9<?1<75rb0:3>5<3290;w)?9f;37a>N6k11C=o64$024>0=#9<k1=i<4ig;94?=nnh0;66gib;29?j72=3:17pl>7g83>1<729q/=;h515g8L4e?3A;i46*>06823>"6=h0:h95ff883>>oai3:17dhm:188k4322900qo?8e;290?6=8r.::k4>4d9K5f><@8h37)??7;48 43f28n:7dh6:188mcg=831bjo4?::m210<722wi=:j50;694?6|,8<m6<:j;I3`<>N6j11/==956:&21d<6l81bj44?::kee?6=3`li6=44o076>5<<uk;<o7>54;294~"6>o0:8h5G1b:8L4d?3-;;;7;4$07b>4b33`l26=44igc94?=nnk0;66a>5483>>{e9hh1<7ll:183!71n3;>h6F>c99K5g><R:31ov75a;33>42=980:97?=:d8g>c<6;3i1qc;;:89m10<>3gi86=5ae483?!`52o>0(k=5f59'bc<33-;;<7:4$022>1=#998186*>0287?!77<3>0(<>::59'550=<2.:<54;;%33=?2<,8:j695+11`90>"68j0?7)??d;68 46b2=1/==h54:&255<33-;:=7:4$031>1=#989186*>1587?!76=3>0(<?9:59'541=<2.:=54;;%32=?2<,8;j695+10`90>"69j0?7)?>d;68 47b2=1/=<h54:&265<33-;9=7:4$001>1=#9;9186*>2587?!75=3>0(<<9:59'571=<2.:>54;;%31=?2<,88j695+13`90>"6:j0?7)?=d;68 44b2=1/=?h54:&275<33-;8=7:4$011>1=#9:9186*>3587?!74=3>0(<=9:59'561=<2.:?54;;%30=?2<,89j695+12`90>"6;j0?7)?<d;68 45b2=1/=>h54:&205<33-;?=7:4$061>1=#9=9186*>4587?!73=3>0(<:9:59'511=<2.:854<;%37=?5<,8>j6<;;;%356?71m2.::>4<b:&221<4j2.:::4<8:&22=<6>h1/=;l53:&22f<43-;h97?l4:&2g3<6k=1b=8k50;9j06<722cm=7>5;h355?6=3`>36=44i07e>5<<a8<;6=44ig294?=n1j0;6)?:9;;a?k7203:07d7n:18'50?=1k1e=8651:9j=<<72-;>577m;o36<?4<3`336=4+14;9=g=i9<21?65f1cg94?"6=00:ni5a14:94>=n9ki1<7*>5882fa=i9<21=65f1c`94?"6=00:ni5a14:96>=n9kk1<7*>5882fa=i9<21?65`bc83>!7213hj7c?:8;28?jd>290/=875b`9m50>=921dn:4?:%36=?df3g;>47<4;n`5>5<#9<31nl5a14:97>=hj<0;6)?:9;`b?k7203>07bl;:18'50?=jh1e=8655:9lf6<72-;>57ln;o36<?0<3fh96=4+14;9fd=i9<21;65`b083>!7213hj7c?:8;:8?jd7290/=875b`9m50>=121dmk4?:%36=?df3g;>47o4;ncf>5<#9<31nl5a14:9f>=hij0;6)?:9;`b?k7203i07bom:18'50?=jh1e=865d:9led<72-;>57ln;o36<?c<3fk26=4+14;9fd=i9<21j65`a983>!7213hj7c?:8;33?>if?3:1(<;6:cc8j43?28;07bo9:18'50?=jh1e=8651398kd3=83.:944ma:l21=<6;21dm94?:%36=?df3g;>47?;;:mb7?6=,8?26oo4n07;>43<3fi96=4+14;9fd=i9<21=;54ob394?"6=00im6`>59823>=hk90;6)?:9;`b?k7203;376amf;29 43>2kk0b<;7:0;8?jdb290/=875b`9m50>=9h10coj50;&21<<ei2d:954>b:9lff<72-;>57ln;o36<?7d32ei47>5$07:>gg<f8?36<j4;ncg>5<#9<31nl5a14:95`=<gh81<7*>588ae>h6=10:j65f1g83>!7213;n7c?:8;28?l7c290/=8751d9m50>=921b=n4?:%36=?7b3g;>47<4;h3a>5<#9<31=h5a14:97>=n:10;6)?:9;3f?k7203>07d<8:18'50?=9l1e=8655:9j63<72-;>57?j;o36<?0<3`8>6=4+14;95`=i9<21;65f2583>!7213;n7c?:8;:8?l44290/=8751d9m50>=121b>?4?:%36=?7b3g;>47o4;h02>5<#9<31=h5a14:9f>=n:90;6)?:9;3f?k7203i07d?n:18'50?=9l1e=865d:9j6`<72-;>57<k;o36<?6<3`8h6=4+14;96a=i9<21=65f2c83>!72138o7c?:8;08?l4f290/=8752e9m50>=;21b?:4?:%36=?4c3g;>47:4;h15>5<#9<31>i5a14:91>=n;<0;6)?:9;0g?k7203<07d=;:18'50?=:m1e=8657:9j76<72-;>57<k;o36<?><3`996=4+14;96a=i9<21565f3083>!72138o7c?:8;c8?l57290/=8752e9m50>=j21b>k4?:%36=?4c3g;>47m4;h0:>5<#9<31>i5a14:9`>=n190;6)?:9;:e?k7203:07d6j:18'50?=0o1e=8651:9j<f<72-;>576i;o36<?4<3`2i6=4+14;9<c=i9<21?65f8`83>!72132m7c?:8;68?l>>290/=8758g9m50>==21b454?:%36=?>a3g;>4784;h:4>5<#9<314k5a14:93>=n0?0;6)?:9;:e?k7203207d6::18'50?=0o1e=8659:9j<1<72-;>576i;o36<?g<3`286=4+14;9<c=i9<21n65f8083>!72132m7c?:8;a8?l>7290/=8758g9m50>=l21b;k4?:%36=?>a3g;>47k4;h5f>5<#9<314k5a14:9b>=n?m0;6)?:9;:e?k7203;;76g8c;29 43>21l0b<;7:038?l1e290/=8758g9m50>=9;10e:o50;&21<<?n2d:954>3:9j3<<72-;>576i;o36<?7332c<47>5$07:>=`<f8?36<;4;h;4>5<#9<314k5a14:953=<a0<1<7*>588;b>h6=10:;65f9483>!72132m7c?:8;3;?>o><3:1(<;6:9d8j43?28307d7<:18'50?=0o1e=8651`98m<4=83.:9447f:l21=<6j21b5<4?:%36=?>a3g;>47?l;:k;`?6=,8?265h4n07;>4b<3`296=4+14;9<c=i9<21=h54i6594?"6=003j6`>5982b>=hmh0;6)?:9;g:?k7203:07bk7:18'50?=m01e=8651:9la2<72-;>57k6;o36<?4<3fo=6=4+14;9a<=i9<21?65fa083>!7213k;7c?:8;28?l?a290/=875a19m50>=921b5h4?:%36=?g73g;>47<4;h;g>5<#9<31m=5a14:97>=hmo0;6)?:9;gf?k7203:07bkk:18'50?=ml1e=8651:9laf<72-;>57kj;o36<?4<3foi6=4+14;9a`=i9<21?65`de83>!7213nh7c?:8;28?jbe290/=875db9m50>=921dh44?:%36=?bd3g;>47<4;nf;>5<#9<31hn5a14:97>=hl>0;6)?:9;f`?k7203>07bj9:18'50?=lj1e=8655:9l`0<72-;>57jl;o36<?0<3fn?6=4+14;9`f=i9<21;65`d283>!7213nh7c?:8;:8?jb5290/=875db9m50>=121dh<4?:%36=?bd3g;>47o4;nf3>5<#9<31hn5a14:9f>=hkl0;6)?:9;f`?k7203i07bmk:18'50?=lj1e=865d:9lgf<72-;>57jl;o36<?c<3fii6=4+14;9`f=i9<21j65`c`83>!7213nh7c?:8;33?>id13:1(<;6:ea8j43?28;07bm7:18'50?=lj1e=8651398kf1=83.:944kc:l21=<6;21do;4?:%36=?bd3g;>47?;;:m`1?6=,8?26im4n07;>43<3fo?6=4+14;9`f=i9<21=;54od194?"6=00oo6`>59823>=hm;0;6)?:9;f`?k7203;376aj1;29 43>2mi0b<;7:0;8?jc7290/=875db9m50>=9h10cih50;&21<<ck2d:954>b:9l``<72-;>57jl;o36<?7d32eom7>5$07:>ae<f8?36<j4;nae>5<#9<31hn5a14:95`=<gj>1<7*>588gg>h6=10:j65f1b194?"6=00:o?5a14:94>=n9j;1<7*>5882g7=i9<21=65f1b294?"6=00:o?5a14:96>=n9kl1<7*>5882g7=i9<21?65f6g83>!7213<n7c?:8;28?l0c290/=8756d9m50>=921b:o4?:%36=?0b3g;>47<4;h4b>5<#9<31:h5a14:97>=n>00;6)?:9;4f?k7203>07d87:18'50?=>l1e=8655:9j22<72-;>578j;o36<?0<3`<=6=4+14;92`=i9<21;65f6483>!7213<n7c?:8;:8?l03290/=8756d9m50>=121b:>4?:%36=?0b3g;>47o4;h41>5<#9<31:h5a14:9f>=n>90;6)?:9;4f?k7203i07d;i:18'50?=>l1e=865d:9j1`<72-;>578j;o36<?c<3`?o6=4+14;92`=i9<21j65f5b83>!7213<n7c?:8;33?>o2j3:1(<;6:7g8j43?28;07d;n:18'50?=>l1e=8651398m0?=83.:9449e:l21=<6;21b954?:%36=?0b3g;>47?;;:k63?6=,8?26;k4n07;>43<3`==6=4+14;92`=i9<21=;54i6794?"6=00=i6`>59823>=n?=0;6)?:9;4f?k7203;376g83;29 43>2?o0b<;7:0;8?l15290/=8756d9m50>=9h10e:?50;&21<<1m2d:954>b:9j35<72-;>578j;o36<?7d32c=o7>5$07:>3c<f8?36<j4;h42>5<#9<31:h5a14:95`=<a<<1<7*>5885a>h6=10:j65rb0;f>5<ek3:1<v*>6g821a=O9j20D<l7;[1:>f}>2h0:<7?;:03950<6:3o1h7h5128`>xh2<330b8;59:l`7?6<fl?1<6*i2;d7?!`42o>0(kh54:&245<33-;;=7:4$021>1=#999186*>0587?!77=3>0(<>9:59'55>=<2.:<44;;%33e?2<,8:i695+11a90>"68m0?7)??e;68 46a2=1/=<>54:&254<33-;:>7:4$030>1=#98>186*>1487?!76>3>0(<?8:59'54>=<2.:=44;;%32e?2<,8;i695+10a90>"69m0?7)?>e;68 47a2=1/=?>54:&264<33-;9>7:4$000>1=#9;>186*>2487?!75>3>0(<<8:59'57>=<2.:>44;;%31e?2<,88i695+13a90>"6:m0?7)?=e;68 44a2=1/=>>54:&274<33-;8>7:4$010>1=#9:>186*>3487?!74>3>0(<=8:59'56>=<2.:?44;;%30e?2<,89i695+12a90>"6;m0?7)?<e;68 45a2=1/=9>54:&204<33-;?>7:4$060>1=#9=>186*>4487?!73>3>0(<:8:59'51>=;2.:844<;%37e?72<2.::?4>6d9'535=;k1/=;:53c9'531=;11/=;6517c8 40e2:1/=;m53:&2g0<6k=1/=n851b68m43b2900e9=50;9jb4<722c::<4?::k7<?6=3`;>j7>5;h354?6=3`l;6=44i8a94?"6=002n6`>5983?>o>i3:1(<;6:8`8j43?2810e4750;&21<<>j2d:954=;:k:<?6=,8?264l4n07;>6=<a8hn6=4+14;95gb<f8?36=54i0``>5<#9<31=oj4n07;>4=<a8hi6=4+14;95gb<f8?36?54i0`b>5<#9<31=oj4n07;>6=<gkh1<7*>588ae>h6=10;76am9;29 43>2kk0b<;7:098kg1=83.:944ma:l21=<532ei:7>5$07:>gg<f8?36>54oc794?"6=00im6`>5987?>ie<3:1(<;6:cc8j43?2<10co=50;&21<<ei2d:9549;:ma6?6=,8?26oo4n07;>2=<gk;1<7*>588ae>h6=10376am0;29 43>2kk0b<;7:898kd`=83.:944ma:l21=<f32eji7>5$07:>gg<f8?36o54o`a94?"6=00im6`>598`?>ifj3:1(<;6:cc8j43?2m10clo50;&21<<ei2d:954j;:mb=?6=,8?26oo4n07;>c=<gh21<7*>588ae>h6=10:<65`a683>!7213hj7c?:8;32?>if>3:1(<;6:cc8j43?28807bo::18'50?=jh1e=8651298kd2=83.:944ma:l21=<6<21dm>4?:%36=?df3g;>47?:;:m`6?6=,8?26oo4n07;>40<3fi:6=4+14;9fd=i9<21=:54ob294?"6=00im6`>5982<>=hjo0;6)?:9;`b?k7203;276ame;29 43>2kk0b<;7:0c8?jdc290/=875b`9m50>=9k10com50;&21<<ei2d:954>c:9lf=<72-;>57ln;o36<?7c32ejh7>5$07:>gg<f8?36<k4;nc1>5<#9<31nl5a14:95c=<a8l1<7*>5882a>h6=10;76g>d;29 43>28o0b<;7:098m4e=83.:944>e:l21=<532c:n7>5$07:>4c<f8?36>54i3:94?"6=00:i6`>5987?>o5?3:1(<;6:0g8j43?2<10e?850;&21<<6m2d:9549;:k11?6=,8?26<k4n07;>2=<a;>1<7*>5882a>h6=10376g=3;29 43>28o0b<;7:898m74=83.:944>e:l21=<f32c9=7>5$07:>4c<f8?36o54i3294?"6=00:i6`>598`?>o6i3:1(<;6:0g8j43?2m10e?k50;&21<<5l2d:954?;:k1g?6=,8?26?j4n07;>4=<a;h1<7*>5881`>h6=10976g=a;29 43>2;n0b<;7:298m61=83.:944=d:l21=<332c8:7>5$07:>7b<f8?36854i2794?"6=009h6`>5985?>o4<3:1(<;6:3f8j43?2>10e>=50;&21<<5l2d:9547;:k06?6=,8?26?j4n07;><=<a:;1<7*>5881`>h6=10j76g<0;29 43>2;n0b<;7:c98m7`=83.:944=d:l21=<d32c957>5$07:>7b<f8?36i54i8294?"6=003j6`>5983?>o?m3:1(<;6:9d8j43?2810e5m50;&21<<?n2d:954=;:k;f?6=,8?265h4n07;>6=<a1k1<7*>588;b>h6=10?76g79;29 43>21l0b<;7:498m=>=83.:9447f:l21=<132c3;7>5$07:>=`<f8?36:54i9494?"6=003j6`>598;?>o?=3:1(<;6:9d8j43?2010e5:50;&21<<?n2d:954n;:k;7?6=,8?265h4n07;>g=<a1;1<7*>588;b>h6=10h76g70;29 43>21l0b<;7:e98m2`=83.:9447f:l21=<b32c<i7>5$07:>=`<f8?36k54i6f94?"6=003j6`>59824>=n?j0;6)?:9;:e?k7203;:76g8b;29 43>21l0b<;7:008?l1f290/=8758g9m50>=9:10e:750;&21<<?n2d:954>4:9j3=<72-;>576i;o36<?7232c2;7>5$07:>=`<f8?36<84;h;5>5<#9<314k5a14:952=<a0?1<7*>588;b>h6=10:465f9583>!72132m7c?:8;3:?>o>;3:1(<;6:9d8j43?28k07d7=:18'50?=0o1e=8651c98m<7=83.:9447f:l21=<6k21b4i4?:%36=?>a3g;>47?k;:k;6?6=,8?265h4n07;>4c<3`=<6=4+14;9<c=i9<21=k54odc94?"6=00n56`>5983?>ib03:1(<;6:d;8j43?2810ch950;&21<<b12d:954=;:mf2?6=,8?26h74n07;>6=<ah;1<7*>588b4>h6=10;76g6f;29 43>2h:0b<;7:098m<c=83.:944n0:l21=<532c2h7>5$07:>d6<f8?36>54odd94?"6=00ni6`>5983?>ibl3:1(<;6:dg8j43?2810chm50;&21<<bm2d:954=;:mff?6=,8?26hk4n07;>6=<gmn1<7*>588gg>h6=10;76akb;29 43>2mi0b<;7:098ka?=83.:944kc:l21=<532eo47>5$07:>ae<f8?36>54oe594?"6=00oo6`>5987?>ic>3:1(<;6:ea8j43?2<10ci;50;&21<<ck2d:9549;:mg0?6=,8?26im4n07;>2=<gm91<7*>588gg>h6=10376ak2;29 43>2mi0b<;7:898ka7=83.:944kc:l21=<f32eo<7>5$07:>ae<f8?36o54obg94?"6=00oo6`>598`?>idl3:1(<;6:ea8j43?2m10cnm50;&21<<ck2d:954j;:m`f?6=,8?26im4n07;>c=<gjk1<7*>588gg>h6=10:<65`c883>!7213nh7c?:8;32?>id03:1(<;6:ea8j43?28807bm8:18'50?=lj1e=8651298kf0=83.:944kc:l21=<6<21do84?:%36=?bd3g;>47?:;:mf0?6=,8?26im4n07;>40<3fo86=4+14;9`f=i9<21=:54od094?"6=00oo6`>5982<>=hm80;6)?:9;f`?k7203;276aj0;29 43>2mi0b<;7:0c8?jba290/=875db9m50>=9k10cik50;&21<<ck2d:954>c:9l`d<72-;>57jl;o36<?7c32ehj7>5$07:>ae<f8?36<k4;na7>5<#9<31hn5a14:95c=<a8i86=4+14;95f4<f8?36=54i0a2>5<#9<31=n<4n07;>4=<a8i;6=4+14;95f4<f8?36?54i0`e>5<#9<31=n<4n07;>6=<a?l1<7*>5885a>h6=10;76g9d;29 43>2?o0b<;7:098m3d=83.:9449e:l21=<532c=m7>5$07:>3c<f8?36>54i7;94?"6=00=i6`>5987?>o103:1(<;6:7g8j43?2<10e;950;&21<<1m2d:9549;:k52?6=,8?26;k4n07;>2=<a??1<7*>5885a>h6=10376g94;29 43>2?o0b<;7:898m35=83.:9449e:l21=<f32c=>7>5$07:>3c<f8?36o54i7294?"6=00=i6`>598`?>o2n3:1(<;6:7g8j43?2m10e8k50;&21<<1m2d:954j;:k6`?6=,8?26;k4n07;>c=<a<i1<7*>5885a>h6=10:<65f5c83>!7213<n7c?:8;32?>o2i3:1(<;6:7g8j43?28807d;6:18'50?=>l1e=8651298m0>=83.:9449e:l21=<6<21b9:4?:%36=?0b3g;>47?:;:k42?6=,8?26;k4n07;>40<3`=>6=4+14;92`=i9<21=:54i6694?"6=00=i6`>5982<>=n?:0;6)?:9;4f?k7203;276g82;29 43>2?o0b<;7:0c8?l16290/=8756d9m50>=9k10e:>50;&21<<1m2d:954>c:9j2f<72-;>578j;o36<?7c32c==7>5$07:>3c<f8?36<k4;h75>5<#9<31:h5a14:95c=<uk;2=7>5bb83>5}#9?l1=8j4H0a;?M7e02P857mt9;c955<6<3;:6<;5138f>a<a2891o7sa558:?k32201eo>4?;og6>5=#n;0m86*i3;d7?!`a2=1/==>54:&244<33-;;>7:4$020>1=#99>186*>0487?!77>3>0(<>7:59'55?=<2.:<l4;;%33f?2<,8:h695+11f90>"68l0?7)??f;68 4772=1/=<?54:&257<33-;:?7:4$037>1=#98?186*>1787?!76?3>0(<?7:59'54?=<2.:=l4;;%32f?2<,8;h695+10f90>"69l0?7)?>f;68 4472=1/=??54:&267<33-;9?7:4$007>1=#9;?186*>2787?!75?3>0(<<7:59'57?=<2.:>l4;;%31f?2<,88h695+13f90>"6:l0?7)?=f;68 4572=1/=>?54:&277<33-;8?7:4$017>1=#9:?186*>3787?!74?3>0(<=7:59'56?=<2.:?l4;;%30f?2<,89h695+12f90>"6;l0?7)?<f;68 4272=1/=9?54:&207<33-;??7:4$067>1=#9=?186*>4787?!73?3>0(<:7:29'51?=;2.:8l4>559'534=9?o0(<8<:2`8 4032:h0(<88:2:8 40?28<j7)?9b;18 40d2:1/=n;51b68 4e128i?7d?:e;29?l242900ek?50;9j537=831b854?::k21c<722c::=4?::ke4?6=3`3h6=4+14;9=g=i9<21<65f9`83>!72133i7c?:8;38?l?>290/=8759c9m50>=:21b554?:%36=??e3g;>47=4;h3aa?6=,8?26<lk;o36<?6<3`;io7>5$07:>4dc3g;>47?4;h3af?6=,8?26<lk;o36<?4<3`;im7>5$07:>4dc3g;>47=4;n`a>5<#9<31nl5a14:94>=hj00;6)?:9;`b?k7203;07bl8:18'50?=jh1e=8652:9lf3<72-;>57ln;o36<?5<3fh>6=4+14;9fd=i9<21865`b583>!7213hj7c?:8;78?jd4290/=875b`9m50>=>21dn?4?:%36=?df3g;>4794;n`2>5<#9<31nl5a14:9<>=hj90;6)?:9;`b?k7203307boi:18'50?=jh1e=865a:9le`<72-;>57ln;o36<?d<3fkh6=4+14;9fd=i9<21o65`ac83>!7213hj7c?:8;f8?jgf290/=875b`9m50>=m21dm44?:%36=?df3g;>47h4;nc;>5<#9<31nl5a14:955=<gh=1<7*>588ae>h6=10:=65`a783>!7213hj7c?:8;31?>if=3:1(<;6:cc8j43?28907bo;:18'50?=jh1e=8651598kd5=83.:944ma:l21=<6=21do?4?:%36=?df3g;>47?9;:m`5?6=,8?26oo4n07;>41<3fi;6=4+14;9fd=i9<21=554ocd94?"6=00im6`>5982=>=hjl0;6)?:9;`b?k7203;j76amd;29 43>2kk0b<;7:0`8?jdd290/=875b`9m50>=9j10co650;&21<<ei2d:954>d:9lea<72-;>57ln;o36<?7b32ej>7>5$07:>gg<f8?36<h4;h3e>5<#9<31=h5a14:94>=n9m0;6)?:9;3f?k7203;07d?l:18'50?=9l1e=8652:9j5g<72-;>57?j;o36<?5<3`836=4+14;95`=i9<21865f2683>!7213;n7c?:8;78?l41290/=8751d9m50>=>21b>84?:%36=?7b3g;>4794;h07>5<#9<31=h5a14:9<>=n::0;6)?:9;3f?k7203307d<=:18'50?=9l1e=865a:9j64<72-;>57?j;o36<?d<3`8;6=4+14;95`=i9<21o65f1`83>!7213;n7c?:8;f8?l4b290/=8752e9m50>=821b>n4?:%36=?4c3g;>47?4;h0a>5<#9<31>i5a14:96>=n:h0;6)?:9;0g?k7203907d=8:18'50?=:m1e=8654:9j73<72-;>57<k;o36<?3<3`9>6=4+14;96a=i9<21:65f3583>!72138o7c?:8;58?l54290/=8752e9m50>=021b??4?:%36=?4c3g;>4774;h12>5<#9<31>i5a14:9e>=n;90;6)?:9;0g?k7203h07d<i:18'50?=:m1e=865c:9j6<<72-;>57<k;o36<?b<3`3;6=4+14;9<c=i9<21<65f8d83>!72132m7c?:8;38?l>d290/=8758g9m50>=:21b4o4?:%36=?>a3g;>47=4;h:b>5<#9<314k5a14:90>=n000;6)?:9;:e?k7203?07d67:18'50?=0o1e=8656:9j<2<72-;>576i;o36<?1<3`2=6=4+14;9<c=i9<21465f8483>!72132m7c?:8;;8?l>3290/=8758g9m50>=i21b4>4?:%36=?>a3g;>47l4;h:2>5<#9<314k5a14:9g>=n090;6)?:9;:e?k7203n07d9i:18'50?=0o1e=865e:9j3`<72-;>576i;o36<?`<3`=o6=4+14;9<c=i9<21==54i6a94?"6=003j6`>59825>=n?k0;6)?:9;:e?k7203;976g8a;29 43>21l0b<;7:018?l1>290/=8758g9m50>=9=10e:650;&21<<?n2d:954>5:9j=2<72-;>576i;o36<?7132c2:7>5$07:>=`<f8?36<94;h;6>5<#9<314k5a14:95==<a0>1<7*>588;b>h6=10:565f9283>!72132m7c?:8;3b?>o>:3:1(<;6:9d8j43?28h07d7>:18'50?=0o1e=8651b98m=b=83.:9447f:l21=<6l21b4?4?:%36=?>a3g;>47?j;:k43?6=,8?265h4n07;>4`<3foj6=4+14;9a<=i9<21<65`e983>!7213o27c?:8;38?jc0290/=875e89m50>=:21di;4?:%36=?c>3g;>47=4;hc2>5<#9<31m=5a14:94>=n1o0;6)?:9;c3?k7203;07d7j:18'50?=i91e=8652:9j=a<72-;>57o?;o36<?5<3fom6=4+14;9a`=i9<21<65`ee83>!7213on7c?:8;38?jcd290/=875ed9m50>=:21dio4?:%36=?cb3g;>47=4;nfg>5<#9<31hn5a14:94>=hlk0;6)?:9;f`?k7203;07bj6:18'50?=lj1e=8652:9l`=<72-;>57jl;o36<?5<3fn<6=4+14;9`f=i9<21865`d783>!7213nh7c?:8;78?jb2290/=875db9m50>=>21dh94?:%36=?bd3g;>4794;nf0>5<#9<31hn5a14:9<>=hl;0;6)?:9;f`?k7203307bj>:18'50?=lj1e=865a:9l`5<72-;>57jl;o36<?d<3fin6=4+14;9`f=i9<21o65`ce83>!7213nh7c?:8;f8?jed290/=875db9m50>=m21doo4?:%36=?bd3g;>47h4;nab>5<#9<31hn5a14:955=<gj31<7*>588gg>h6=10:=65`c983>!7213nh7c?:8;31?>id?3:1(<;6:ea8j43?28907bm9:18'50?=lj1e=8651598kf3=83.:944kc:l21=<6=21di94?:%36=?bd3g;>47?9;:mf7?6=,8?26im4n07;>41<3fo96=4+14;9`f=i9<21=554od394?"6=00oo6`>5982=>=hm90;6)?:9;f`?k7203;j76akf;29 43>2mi0b<;7:0`8?jbb290/=875db9m50>=9j10cio50;&21<<ck2d:954>d:9lgc<72-;>57jl;o36<?7b32eh87>5$07:>ae<f8?36<h4;h3`7?6=,8?26<m=;o36<?6<3`;h=7>5$07:>4e53g;>47?4;h3`4?6=,8?26<m=;o36<?4<3`;ij7>5$07:>4e53g;>47=4;h4e>5<#9<31:h5a14:94>=n>m0;6)?:9;4f?k7203;07d8m:18'50?=>l1e=8652:9j2d<72-;>578j;o36<?5<3`<26=4+14;92`=i9<21865f6983>!7213<n7c?:8;78?l00290/=8756d9m50>=>21b:;4?:%36=?0b3g;>4794;h46>5<#9<31:h5a14:9<>=n>=0;6)?:9;4f?k7203307d8<:18'50?=>l1e=865a:9j27<72-;>578j;o36<?d<3`<;6=4+14;92`=i9<21o65f5g83>!7213<n7c?:8;f8?l3b290/=8756d9m50>=m21b9i4?:%36=?0b3g;>47h4;h7`>5<#9<31:h5a14:955=<a<h1<7*>5885a>h6=10:=65f5`83>!7213<n7c?:8;31?>o213:1(<;6:7g8j43?28907d;7:18'50?=>l1e=8651598m01=83.:9449e:l21=<6=21b;;4?:%36=?0b3g;>47?9;:k41?6=,8?26;k4n07;>41<3`=?6=4+14;92`=i9<21=554i6194?"6=00=i6`>5982=>=n?;0;6)?:9;4f?k7203;j76g81;29 43>2?o0b<;7:0`8?l17290/=8756d9m50>=9j10e;m50;&21<<1m2d:954>d:9j24<72-;>578j;o36<?7b32c>:7>5$07:>3c<f8?36<h4;|`2<1<72ki1<7>t$04e>43c3A;h46F>b99Y7<<ds00j6<>515825?722881i7j5f;30>f<zf<>156`:5;;8jf5=82dn97>4$g09b1=#n:0m86*if;68 4672=1/==?54:&247<33-;;?7:4$027>1=#99?186*>0787?!7703>0(<>6:59'55g=<2.:<o4;;%33g?2<,8:o695+11g90>"68o0?7)?>0;68 4762=1/=<<54:&256<33-;:87:4$036>1=#98<186*>1687?!7603>0(<?6:59'54g=<2.:=o4;;%32g?2<,8;o695+10g90>"69o0?7)?=0;68 4462=1/=?<54:&266<33-;987:4$006>1=#9;<186*>2687?!7503>0(<<6:59'57g=<2.:>o4;;%31g?2<,88o695+13g90>"6:o0?7)?<0;68 4562=1/=><54:&276<33-;887:4$016>1=#9:<186*>3687?!7403>0(<=6:59'56g=<2.:?o4;;%30g?2<,89o695+12g90>"6;o0?7)?;0;68 4262=1/=9<54:&206<33-;?87:4$066>1=#9=<186*>4687?!730390(<:6:29'51g=9<>0(<8=:04f?!71;39i7)?94;1a?!71?3937)?98;35e>"6>k087)?9c;18 4e228i?7)?l6;3`0>o6=l0;66g;3;29?l`62900e<8>:188m1>=831b=8h50;9j536=831bj=4?::k:g?6=,8?264l4n07;>5=<a0k1<7*>588:f>h6=10:76g69;29 43>20h0b<;7:398m<>=83.:9446b:l21=<432c:nh4?:%36=?7el2d:954?;:k2ff<72-;>57?md:l21=<632c:no4?:%36=?7el2d:954=;:k2fd<72-;>57?md:l21=<432ein7>5$07:>gg<f8?36=54oc;94?"6=00im6`>5982?>ie?3:1(<;6:cc8j43?2;10co850;&21<<ei2d:954<;:ma1?6=,8?26oo4n07;>1=<gk>1<7*>588ae>h6=10>76am3;29 43>2kk0b<;7:798kg4=83.:944ma:l21=<032ei=7>5$07:>gg<f8?36554oc294?"6=00im6`>598:?>ifn3:1(<;6:cc8j43?2h10clk50;&21<<ei2d:954m;:mbg?6=,8?26oo4n07;>f=<ghh1<7*>588ae>h6=10o76ana;29 43>2kk0b<;7:d98kd?=83.:944ma:l21=<a32ej47>5$07:>gg<f8?36<>4;nc4>5<#9<31nl5a14:954=<gh<1<7*>588ae>h6=10:>65`a483>!7213hj7c?:8;30?>if<3:1(<;6:cc8j43?28>07bo<:18'50?=jh1e=8651498kf4=83.:944ma:l21=<6>21do<4?:%36=?df3g;>47?8;:m`4?6=,8?26oo4n07;>4><3fhm6=4+14;9fd=i9<21=454ocg94?"6=00im6`>5982e>=hjm0;6)?:9;`b?k7203;i76amc;29 43>2kk0b<;7:0a8?jd?290/=875b`9m50>=9m10clj50;&21<<ei2d:954>e:9le7<72-;>57ln;o36<?7a32c:j7>5$07:>4c<f8?36=54i0f94?"6=00:i6`>5982?>o6k3:1(<;6:0g8j43?2;10e<l50;&21<<6m2d:954<;:k1<?6=,8?26<k4n07;>1=<a;=1<7*>5882a>h6=10>76g=6;29 43>28o0b<;7:798m73=83.:944>e:l21=<032c987>5$07:>4c<f8?36554i3194?"6=00:i6`>598:?>o5:3:1(<;6:0g8j43?2h10e??50;&21<<6m2d:954m;:k14?6=,8?26<k4n07;>f=<a8k1<7*>5882a>h6=10o76g=e;29 43>2;n0b<;7:198m7e=83.:944=d:l21=<632c9n7>5$07:>7b<f8?36?54i3c94?"6=009h6`>5980?>o4?3:1(<;6:3f8j43?2=10e>850;&21<<5l2d:954:;:k01?6=,8?26?j4n07;>3=<a:>1<7*>5881`>h6=10<76g<3;29 43>2;n0b<;7:998m64=83.:944=d:l21=<>32c8=7>5$07:>7b<f8?36l54i2294?"6=009h6`>598a?>o5n3:1(<;6:3f8j43?2j10e?750;&21<<5l2d:954k;:k:4?6=,8?265h4n07;>5=<a1o1<7*>588;b>h6=10:76g7c;29 43>21l0b<;7:398m=d=83.:9447f:l21=<432c3m7>5$07:>=`<f8?36954i9;94?"6=003j6`>5986?>o?03:1(<;6:9d8j43?2?10e5950;&21<<?n2d:9548;:k;2?6=,8?265h4n07;>==<a1?1<7*>588;b>h6=10276g74;29 43>21l0b<;7:`98m=5=83.:9447f:l21=<e32c3=7>5$07:>=`<f8?36n54i9294?"6=003j6`>598g?>o0n3:1(<;6:9d8j43?2l10e:k50;&21<<?n2d:954i;:k4`?6=,8?265h4n07;>46<3`=h6=4+14;9<c=i9<21=<54i6`94?"6=003j6`>59826>=n?h0;6)?:9;:e?k7203;876g89;29 43>21l0b<;7:068?l1?290/=8758g9m50>=9<10e4950;&21<<?n2d:954>6:9j=3<72-;>576i;o36<?7032c297>5$07:>=`<f8?36<64;h;7>5<#9<314k5a14:95<=<a091<7*>588;b>h6=10:m65f9383>!72132m7c?:8;3a?>o>93:1(<;6:9d8j43?28i07d6k:18'50?=0o1e=8651e98m=4=83.:9447f:l21=<6m21b;:4?:%36=?>a3g;>47?i;:mfe?6=,8?26h74n07;>5=<gl21<7*>588f=>h6=10:76aj7;29 43>2l30b<;7:398k`0=83.:944j9:l21=<432cj=7>5$07:>d6<f8?36=54i8d94?"6=00j<6`>5982?>o>m3:1(<;6:`28j43?2;10e4j50;&21<<f82d:954<;:mfb?6=,8?26hk4n07;>5=<gln1<7*>588fa>h6=10:76ajc;29 43>2lo0b<;7:398k`d=83.:944je:l21=<432eoh7>5$07:>ae<f8?36=54oe`94?"6=00oo6`>5982?>ic13:1(<;6:ea8j43?2;10ci650;&21<<ck2d:954<;:mg3?6=,8?26im4n07;>1=<gm<1<7*>588gg>h6=10>76ak5;29 43>2mi0b<;7:798ka2=83.:944kc:l21=<032eo?7>5$07:>ae<f8?36554oe094?"6=00oo6`>598:?>ic93:1(<;6:ea8j43?2h10ci>50;&21<<ck2d:954m;:m`a?6=,8?26im4n07;>f=<gjn1<7*>588gg>h6=10o76alc;29 43>2mi0b<;7:d98kfd=83.:944kc:l21=<a32ehm7>5$07:>ae<f8?36<>4;na:>5<#9<31hn5a14:954=<gj21<7*>588gg>h6=10:>65`c683>!7213nh7c?:8;30?>id>3:1(<;6:ea8j43?28>07bm::18'50?=lj1e=8651498k`2=83.:944kc:l21=<6>21di>4?:%36=?bd3g;>47?8;:mf6?6=,8?26im4n07;>4><3fo:6=4+14;9`f=i9<21=454od294?"6=00oo6`>5982e>=hlo0;6)?:9;f`?k7203;i76ake;29 43>2mi0b<;7:0a8?jbf290/=875db9m50>=9m10cnh50;&21<<ck2d:954>e:9lg1<72-;>57jl;o36<?7a32c:o>4?:%36=?7d:2d:954?;:k2g4<72-;>57?l2:l21=<632c:o=4?:%36=?7d:2d:954=;:k2fc<72-;>57?l2:l21=<432c=j7>5$07:>3c<f8?36=54i7f94?"6=00=i6`>5982?>o1j3:1(<;6:7g8j43?2;10e;o50;&21<<1m2d:954<;:k5=?6=,8?26;k4n07;>1=<a?21<7*>5885a>h6=10>76g97;29 43>2?o0b<;7:798m30=83.:9449e:l21=<032c=97>5$07:>3c<f8?36554i7694?"6=00=i6`>598:?>o1;3:1(<;6:7g8j43?2h10e;<50;&21<<1m2d:954m;:k54?6=,8?26;k4n07;>f=<a<l1<7*>5885a>h6=10o76g:e;29 43>2?o0b<;7:d98m0b=83.:9449e:l21=<a32c>o7>5$07:>3c<f8?36<>4;h7a>5<#9<31:h5a14:954=<a<k1<7*>5885a>h6=10:>65f5883>!7213<n7c?:8;30?>o203:1(<;6:7g8j43?28>07d;8:18'50?=>l1e=8651498m20=83.:9449e:l21=<6>21b;84?:%36=?0b3g;>47?8;:k40?6=,8?26;k4n07;>4><3`=86=4+14;92`=i9<21=454i6094?"6=00=i6`>5982e>=n?80;6)?:9;4f?k7203;i76g80;29 43>2?o0b<;7:0a8?l0d290/=8756d9m50>=9m10e;?50;&21<<1m2d:954>e:9j13<72-;>578j;o36<?7a32wx=8<50;30=~;6k00m;63>ac815>;6ik09<63>ac82e>;6ik08<63>ac81b>;6ik09563>ac85b>;6ik0=h63>ac85f>;6ik0=m63>ac85=>;6ik0=463>ac853>;6ik0=:63>ac851>;6ik0=863>ac857>;6ik0=>63>ac854>;6ik0>j63>ac86a>;6ik0>h63>ac86g>;6ik0>n63>ac86e>;6ik0>563>ac86<>;6ik0>;63>ac842>;6ik0<963>ac8:4>;6ik03i63>ac8;g>;6ik03n63>ac8;e>;6ik03563>ac8;<>;6ik03;63>ac8;2>;6ik03963>ac8;0>;6ik03?63>ac8;5>;6ik03<63>ac84b>;6ik0<i63>ac84`>;6ik0<o63>ac84f>;6ik0<m63>ac84=>;6ik0<463>ac8:3>;6ik02:63>ac8:1>;6ik02863>ac8:7>;6ik02>63>ac8:5>;6ik03h63>ac8;6>;6ik0<;63>ac8:g>;6ik02m63>ac8:=>;6ik02463>ac8b5>;6ik02j63>ac8:a>;6ik02h63>ac82g6=:9hh1=n?4=0ca>4e734;jn7?mf:?2eg<6=l16=ll514d894ge28<;70?nb;355>;61l09=63>9d814>;61l0:m63>9d804>;61l09j63>9d81=>;61l0=j63>9d85`>;61l0=n63>9d85e>;61l0=563>9d85<>;61l0=;63>9d852>;61l0=963>9d850>;61l0=?63>9d856>;61l0=<63>9d86b>;61l0>i63>9d86`>;61l0>o63>9d86f>;61l0>m63>9d86=>;61l0>463>9d863>;61l0<:63>9d841>;61l02<63>9d8;a>;61l03o63>9d8;f>;61l03m63>9d8;=>;61l03463>9d8;3>;61l03:63>9d8;1>;61l03863>9d8;7>;61l03=63>9d8;4>;61l0<j63>9d84a>;61l0<h63>9d84g>;61l0<n63>9d84e>;61l0<563>9d84<>;61l02;63>9d8:2>;61l02963>9d8:0>;61l02?63>9d8:6>;61l02=63>9d8;`>;61l03>63>9d843>;61l02o63>9d8:e>;61l02563>9d8:<>;61l0j=63>9d8:b>;61l02i63>9d8:`>;61l0:o>5218g95f7<583n6<m?;<3:a?7en27:5h4>5d9>5<c=9<l01<7j:043?87>m3;==63>90815>;61809<63>9082e>;61808<63>9081b>;61809563>9085b>;6180=h63>9085f>;6180=m63>9085=>;6180=463>90853>;6180=:63>90851>;6180=863>90857>;6180=>63>90854>;6180>j63>9086a>;6180>h63>9086g>;6180>n63>9086e>;6180>563>9086<>;6180>;63>90842>;6180<963>908:4>;61803i63>908;g>;61803n63>908;e>;61803563>908;<>;61803;63>908;2>;61803963>908;0>;61803?63>908;5>;61803<63>9084b>;6180<i63>9084`>;6180<o63>9084f>;6180<m63>9084=>;6180<463>908:3>;61802:63>908:1>;61802863>908:7>;61802>63>908:5>;61803h63>908;6>;6180<;63>908:g>;61802m63>908:=>;61802463>908b5>;61802j63>908:a>;61802h63>9082g6=:90;1=n?4=0;2>4e734;2=7?mf:?2=4<6=l16=4?514d894?628<;70?61;355>;60=09=63>85814>;60=0:m63>85804>;60=09j63>8581=>;60=0=j63>8585`>;60=0=n63>8585e>;60=0=563>8585<>;60=0=;63>85852>;60=0=963>85850>;60=0=?63>85856>;60=0=<63>8586b>;60=0>i63>8586`>;60=0>o63>8586f>;60=0>m63>8586=>;60=0>463>85863>;60=0<:63>85841>;60=02<63>858;a>;60=03o63>858;f>;60=03m63>858;=>;60=03463>858;3>;60=03:63>858;1>;60=03863>858;7>;60=03=63>858;4>;60=0<j63>8584a>;60=0<h63>8584g>;60=0<n63>8584e>;60=0<563>8584<>;60=02;63>858:2>;60=02963>858:0>;60=02?63>858:6>;60=02=63>858;`>;60=03>63>85843>;60=02o63>858:e>;60=02563>858:<>;60=0j=63>858:b>;60=02i63>858:`>;60=0:o>5219695f7<582?6<m?;<3;0?7en27:494>5d9>5=2=9<l01<6;:043?87?<3;==6s|21d94?4|V;:m70?80;361>{t:8:1<7<t^333?87093;>96s|20394?4|V;;:70?82;361>{t:881<7<t^331?870;3;>96s|20194?4|V;;870?84;361>{t:8>1<7<t^337?870=3;>96s|20794?4|V;;>70?86;361>{t:8=1<7<t^334?870?3;>96s|20;94?1|V;;270?8a;1a?870j39i70?73;d:?87?:3l270?71;db?87?83l27p}=0483>2}Y:9?01<9n:2c8941e2:k01<om:5:894?b2=201<7>:5:894>32=20q~<>8;291~X59116=:h5f89>52c=n016=:j5f`9>52e=n01v?>;:186[47<27:mo4;3:?2=`<3;27:5<4;3:?2<1<3;2wx=h=50;7xZ4c434;jn7=>;<3:a?5634;2=7=>;<3;0?563ty:i54?:4y]5`><58ki6><4=0;f>64<583:6><4=0:7>64<uz;n57>55z\2a<=:9hh1?>5218g976=:90;1?>52196976=z{8oj6=4:{_3fe>;6ik08863>9d800>;61808863>85800>{t9lh1<7;t^0ga?87fj39>70?6e;16?87>939>70?74;16?xu6mj0;68uQ1da894ge2:<01<7j:24894?62:<01<6;:248yv7bl3:19vP>ee9>5dd=;>16=4k5369>5<7=;>16=5:5369~w4cb290>wS?je:?2eg<5i27:5h4=a:?2=4<5i27:494=a:p5``=83?pR<ki;<3bf?4e34;2i7<m;<3:5?4e34;387<m;|q2b5<72<qU=k>4=0ca>7e<583n6?m4=0;2>7e<582?6?m4}r3f0?6==rT:i9521``96`=:90o1>h5218396`=:91>1>h5rs0g6>5<1sW;n963>7`867>;60:0mn63>838ef>;6080m563>818ef>{t9l=1<78t^0g4?870j3?870?73;db?87?:3lj70?71;da?87?83lj7p}=0783>0}Y:9<01<om:44894?b2<<01<7>:44894>32<<0q~<?7;291~X58>16=ll5609>5<c=>816=4?5609>5=2=>81v?>7:186[47027:mo49c:?2=`<1k27:5<49c:?2<1<1k2wx>=750;7xZ76>34;jn79?;<3:a?1734;2=79?;<3;0?173ty9<l4?:4y]65g<58ki6:?4=0;f>27<583:6:?4=0:7>27<uz8;n7>55z\14g=:9hh1;?5218g937=:90;1;?52196937=z{;:h6=4:{_03g>;6ik0<?63>9d847>;6180<?63>85847>{t:9o1<7;t^32f?87fj3=?70?6e;57?87>93=?70?74;57?xu6l<0;68uQ1e7894ge2;801<7j:30894?62;801<6;:308yv7ci3:19vP>d`9>5dd=::16=4k5229>5<7=::16=5:5229~w4be290>wS?kb:?2eg<5<27:5h4=4:?2=4<5<27:494=4:p5ae=83?pR<jl;<3bf?4234;2i7<:;<3:5?4234;387<:;|q2`a<72<qU=ij4=0ca>70<583n6?84=0;2>70<582?6?84}r3ga?6==rT:hh521``962=:90o1>:52183962=:91>1>:5rs0fe>5<2sW;oj63>ac81<>;61l09463>9081<>;60=0946s|1d294?3|V8o;70?nb;3a?87>m3;i70?61;3a?87?<3;i7p}>e083>0}Y9l;01<om:0a894?b28i01<7>:0a894>328i0q~?j2;291~X6m;16=ll51e9>5<c=9m16=4?51e9>5=2=9m1v<j9:186[7c>27:mo4>f:?2=`<6n27:5<4>f:?2<1<6n2wx=i950;7xZ4b034;<j7hm;<34a?`e34;<h7h6;<34g?`e3ty:h44?:4y]5a?<58=m6ko4=05f>cg<58=o6kl4=05`>cg<uz8:o7>510y]64e<58ki6<lj;<3bf?7ek27:mo4>bc9>5dd=9kk01<7j:0`f?87>m3;io63>9d82fg=:90o1=oo4=0;2>4db34;2=7?mc:?2=4<6jk16=4?51cc894>328hn70?74;3ag>;60=0:no5219695gg<uz;<57>59z?23g<6=j16=:95f`9>520=nh16=:;5f`9>522=nh16=:=5f`9>524=nh16=:?5f`9>526=nh1v<97:18:870i3;>o63>768e=>;6??0m563>748e=>;6?=0m563>728e=>;6?;0m563>708e=>;6?90m56s|1c594?4|58286<;:;<3bf?`63ty:ml4?:3y>5=4=9<?01<7j:g38yv7>l3:1>v3>808210=:90;1j<5rs0;3>5<5s4;3<7?:5:?2<1<a92wx=o850;0x941a28?>70?nb;d3?xu6i00;6?u216g9503<583n6k>4}r3:g?6=:r7:;i4>549>5<7=n91v<6i:181870k3;>963>858e4>{t9ho1<7<t=053>ce<58ki6n:4}r3bb?6=:r7:;<4ic:?2eg<dn2wx=o>50;0x94152oi01<om:ec8yv7e93:1>v3>728eg>;6ik0oi6s|1c094?4|58=?6km4=0ca>a`<uz;i?7>52z?230<ak27:mo4j0:p5g2=838p1<99:ga894ge2l;0q~?m5;296~;6?>0mo63>ac8f6>{t9h;1<7<t=053>cb<583n6n:4}r3b6?6=:r7:;<4id:?2=`<dn2wx=l=50;0x94152on01<7j:ec8yv7f<3:1>v3>728e`>;61l0oi6s|1`794?4|58=?6kj4=0;f>a`<uz;j:7>52z?230<al27:5h4j0:p5d1=838p1<99:gf894?b2l;0q~?n8;296~;6?>0mh63>9d8f6>{t90>1<7<t=053>cd<583:6n:4}r3:1?6=:r7:;<4ib:?2=4<dn2wx=4850;0x94152oh01<7>:ec8yv7>?3:1>v3>728ef>;6180oi6s|18:94?4|58=?6kl4=0;2>a`<uz;257>52z?230<aj27:5<4j0:p5<g=838p1<99:g`894?62l;0q~?6b;296~;6?>0mn63>908f6>{t91=1<7<t=053>cc<582?6n:4}r3;<?6=:r7:;<4ie:?2<1<dn2wx=5750;0x94152oo01<6;:ec8yv7?i3:1>v3>728ea>;60=0oi6s|19`94?4|58=?6kk4=0:7>a`<uz;3o7>52z?230<am27:494j0:p5=b=838p1<99:gg894>32l;0q~?7e;296~;6?>0mi63>858f6>{zf:k96=4>{I3a<>{i;h91<7?tH0`;?xh4i=0;6<uG1c:8yk5f=3:1=vF>b99~j6g1290:wE?m8:m7d1=83;pD<l7;|l0e=<728qC=o64}o1b=?6=9rB:n55rn2cb>5<6sA;i46sa3``94?7|@8h37p`<ab83>4}O9k20qc=nd;295~N6j11vb>oj:182M7e02we?lh50;3xL4d?3td8n=4?:0yK5g><ug9i=7>51zJ2f==zf:h96=4>{I3a<>{i;k91<7?tH0`;?xh4j=0;6<uG1c:8yk5e=3:1=vF>b99~j6d1290:wE?m8:m7g1=83;pD<l7;|l0f=<728qC=o64}o1a=?6=9rB:n55rn2`b>5<6sA;i46sa3c`94?7|@8h37p`<bb83>4}O9k20qc=md;295~N6j11vb>lj:182M7e02we?oh50;3xL4d?3td8o=4?:0yK5g><ug9h=7>51zJ2f==zf:i96=4>{I3a<>{i;j91<7?tH0`;?xh4k=0;6<uG1c:8yk5d=3:1=vF>b99~j6e1290:wE?m8:m7f1=83;pD<l7;|l0g=<728qC=o64}o1`=?6=9rB:n55rn2ab>5<6sA;i46sa3b`94?7|@8h37p`<cb83>4}O9k20qc=ld;295~N6j11vb>mj:182M7e02we?nh50;3xL4d?3td8h=4?:0yK5g><ug9o=7>51zJ2f==zf:n96=4>{I3a<>{i;m91<7?tH0`;?xh4l=0;6<uG1c:8yk5c=3:1=vF>b99~j6b1290:wE?m8:m7a1=83;pD<l7;|l0`=<728qC=o64}o1g=?6=9rB:n55rn2fb>5<6sA;i46sa3e`94?7|@8h37p`<db83>4}O9k20qc=kd;295~N6j11vb>jj:182M7e02we?ih50;3xL4d?3td8i=4?:0yK5g><ug9n=7>51zJ2f==zf:o96=4>{I3a<>{i;l91<7?tH0`;?xh4m=0;6<uG1c:8yk5b=3:1=vF>b99~j6c1290:wE?m8:m7`1=83;pD<l7;|l0a=<728qC=o64}o1f=?6=9rB:n55rn2gb>5<6sA;i46sa3d`94?7|@8h37p`<eb83>4}O9k20qc=jd;295~N6j11vb>kj:182M7e02we?hh50;3xL4d?3td8j=4?:0yK5g><ug9m=7>51zJ2f==zf:l96=4>{I3a<>{i;o91<7?tH0`;?xh4n=0;6<uG1c:8yk5a=3:1=vF>b99~j6`1290:wE?m8:m7c1=83;pD<l7;|l0b=<728qC=o64}o1e=?6=9rB:n55rn2db>5<6sA;i46sa3g`94?7|@8h37psr}AB@1312m;8:l;>1|BCF~6zHIZpqMN
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.vhd	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.vhd	(revision 115)
@@ -0,0 +1,152 @@
+--------------------------------------------------------------------------------
+--    This file is owned and controlled by Xilinx and must be used solely     --
+--    for design, simulation, implementation and creation of design files     --
+--    limited to Xilinx devices or technologies. Use with non-Xilinx          --
+--    devices or technologies is expressly prohibited and immediately         --
+--    terminates your license.                                                --
+--                                                                            --
+--    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
+--    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
+--    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
+--    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
+--    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
+--    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
+--    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
+--    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
+--    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
+--    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
+--    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
+--    PARTICULAR PURPOSE.                                                     --
+--                                                                            --
+--    Xilinx products are not intended for use in life support appliances,    --
+--    devices, or systems.  Use in such applications are expressly            --
+--    prohibited.                                                             --
+--                                                                            --
+--    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
+--    All rights reserved.                                                    --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file blk_mem_gen_v6_2.vhd when simulating
+-- the core, blk_mem_gen_v6_2. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY blk_mem_gen_v6_2 IS
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    enb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END blk_mem_gen_v6_2;
+
+ARCHITECTURE blk_mem_gen_v6_2_a OF blk_mem_gen_v6_2 IS
+-- synthesis translate_off
+COMPONENT wrapped_blk_mem_gen_v6_2
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    enb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END COMPONENT;
+
+-- Configuration specification
+  FOR ALL : wrapped_blk_mem_gen_v6_2 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
+    GENERIC MAP (
+      c_addra_width => 13,
+      c_addrb_width => 13,
+      c_algorithm => 1,
+      c_axi_id_width => 4,
+      c_axi_slave_type => 0,
+      c_axi_type => 1,
+      c_byte_size => 8,
+      c_common_clk => 0,
+      c_default_data => "0",
+      c_disable_warn_bhv_coll => 0,
+      c_disable_warn_bhv_range => 0,
+      c_family => "spartan6",
+      c_has_axi_id => 0,
+      c_has_ena => 1,
+      c_has_enb => 1,
+      c_has_injecterr => 0,
+      c_has_mem_output_regs_a => 0,
+      c_has_mem_output_regs_b => 0,
+      c_has_mux_output_regs_a => 0,
+      c_has_mux_output_regs_b => 0,
+      c_has_regcea => 0,
+      c_has_regceb => 0,
+      c_has_rsta => 0,
+      c_has_rstb => 0,
+      c_has_softecc_input_regs_a => 0,
+      c_has_softecc_output_regs_b => 0,
+      c_init_file_name => "no_coe_file_loaded",
+      c_inita_val => "0",
+      c_initb_val => "0",
+      c_interface_type => 0,
+      c_load_init_file => 0,
+      c_mem_type => 1,
+      c_mux_pipeline_stages => 0,
+      c_prim_type => 1,
+      c_read_depth_a => 8192,
+      c_read_depth_b => 8192,
+      c_read_width_a => 8,
+      c_read_width_b => 8,
+      c_rst_priority_a => "CE",
+      c_rst_priority_b => "CE",
+      c_rst_type => "SYNC",
+      c_rstram_a => 0,
+      c_rstram_b => 0,
+      c_sim_collision_check => "ALL",
+      c_use_byte_wea => 1,
+      c_use_byte_web => 1,
+      c_use_default_data => 0,
+      c_use_ecc => 0,
+      c_use_softecc => 0,
+      c_wea_width => 1,
+      c_web_width => 1,
+      c_write_depth_a => 8192,
+      c_write_depth_b => 8192,
+      c_write_mode_a => "WRITE_FIRST",
+      c_write_mode_b => "WRITE_FIRST",
+      c_write_width_a => 8,
+      c_write_width_b => 8,
+      c_xdevicefamily => "spartan6"
+    );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_blk_mem_gen_v6_2
+  PORT MAP (
+    clka => clka,
+    ena => ena,
+    wea => wea,
+    addra => addra,
+    dina => dina,
+    clkb => clkb,
+    enb => enb,
+    addrb => addrb,
+    doutb => doutb
+  );
+-- synthesis translate_on
+
+END blk_mem_gen_v6_2_a;
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.vho
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.vho	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.vho	(revision 115)
@@ -0,0 +1,89 @@
+--------------------------------------------------------------------------------
+--    This file is owned and controlled by Xilinx and must be used solely     --
+--    for design, simulation, implementation and creation of design files     --
+--    limited to Xilinx devices or technologies. Use with non-Xilinx          --
+--    devices or technologies is expressly prohibited and immediately         --
+--    terminates your license.                                                --
+--                                                                            --
+--    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
+--    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
+--    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
+--    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
+--    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
+--    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
+--    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
+--    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
+--    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
+--    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
+--    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
+--    PARTICULAR PURPOSE.                                                     --
+--                                                                            --
+--    Xilinx products are not intended for use in life support appliances,    --
+--    devices, or systems.  Use in such applications are expressly            --
+--    prohibited.                                                             --
+--                                                                            --
+--    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
+--    All rights reserved.                                                    --
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+--    Generated from core with identifier: xilinx.com:ip:blk_mem_gen:6.2      --
+--                                                                            --
+--    The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port    --
+--    Block Memory and Single Port Block Memory LogiCOREs, but is not a       --
+--    direct drop-in replacement.  It should be used in all new Xilinx        --
+--    designs. The core supports RAM and ROM functions over a wide range of   --
+--    widths and depths. Use this core to generate block memories with        --
+--    symmetric or asymmetric read and write port widths, as well as cores    --
+--    which can perform simultaneous write operations to separate             --
+--    locations, and simultaneous read operations from the same location.     --
+--    For more information on differences in interface and feature support    --
+--    between this core and the Dual Port Block Memory and Single Port        --
+--    Block Memory LogiCOREs, please consult the data sheet.                  --
+--------------------------------------------------------------------------------
+
+-- Interfaces:
+--    AXI_SLAVE_S_AXI
+--    AXILite_SLAVE_S_AXI
+
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT blk_mem_gen_v6_2
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    enb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : blk_mem_gen_v6_2
+  PORT MAP (
+    clka => clka,
+    ena => ena,
+    wea => wea,
+    addra => addra,
+    dina => dina,
+    clkb => clkb,
+    enb => enb,
+    addrb => addrb,
+    doutb => doutb
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file blk_mem_gen_v6_2.vhd when simulating
+-- the core, blk_mem_gen_v6_2. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.xco
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.xco	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.xco	(revision 115)
@@ -0,0 +1,105 @@
+##############################################################
+#
+# Xilinx Core Generator version 13.3
+# Date: Mon Mar 03 16:17:17 2014
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:blk_mem_gen:6.2
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2
+# END Select
+# BEGIN Parameters
+CSET additional_inputs_for_power_estimation=false
+CSET algorithm=Minimum_Area
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
+CSET byte_size=8
+CSET coe_file=no_coe_file_loaded
+CSET collision_warnings=ALL
+CSET component_name=blk_mem_gen_v6_2
+CSET disable_collision_warnings=false
+CSET disable_out_of_range_warnings=false
+CSET ecc=false
+CSET ecctype=No_ECC
+CSET enable_a=Use_ENA_Pin
+CSET enable_b=Use_ENB_Pin
+CSET error_injection_type=Single_Bit_Error_Injection
+CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
+CSET load_init_file=false
+CSET memory_type=Simple_Dual_Port_RAM
+CSET operating_mode_a=WRITE_FIRST
+CSET operating_mode_b=WRITE_FIRST
+CSET output_reset_value_a=0
+CSET output_reset_value_b=0
+CSET pipeline_stages=0
+CSET port_a_clock=100
+CSET port_a_enable_rate=100
+CSET port_a_write_rate=50
+CSET port_b_clock=100
+CSET port_b_enable_rate=100
+CSET port_b_write_rate=0
+CSET primitive=8kx2
+CSET read_width_a=8
+CSET read_width_b=8
+CSET register_porta_input_of_softecc=false
+CSET register_porta_output_of_memory_core=false
+CSET register_porta_output_of_memory_primitives=false
+CSET register_portb_output_of_memory_core=false
+CSET register_portb_output_of_memory_primitives=false
+CSET register_portb_output_of_softecc=false
+CSET remaining_memory_locations=0
+CSET reset_memory_latch_a=false
+CSET reset_memory_latch_b=false
+CSET reset_priority_a=CE
+CSET reset_priority_b=CE
+CSET reset_type=SYNC
+CSET softecc=false
+CSET use_axi_id=false
+CSET use_byte_write_enable=true
+CSET use_error_injection_pins=false
+CSET use_regcea_pin=false
+CSET use_regceb_pin=false
+CSET use_rsta_pin=false
+CSET use_rstb_pin=false
+CSET write_depth_a=8192
+CSET write_width_a=8
+CSET write_width_b=8
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2011-03-11T08:24:14.000Z
+# END Extra information
+GENERATE
+# CRC: ae3bda39
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.xise
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.xise	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2.xise	(revision 115)
@@ -0,0 +1,399 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="blk_mem_gen_v6_2.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="blk_mem_gen_v6_2.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|blk_mem_gen_v6_2|blk_mem_gen_v6_2_a" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="blk_mem_gen_v6_2.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/blk_mem_gen_v6_2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="blk_mem_gen_v6_2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="blk_mem_gen_v6_2_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="blk_mem_gen_v6_2_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="blk_mem_gen_v6_2_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="blk_mem_gen_v6_2_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="blk_mem_gen_v6_2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-03-03T17:18:27" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="4C2336E0A57A47F1A3C485BD8D22E04B" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_flist.txt
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_flist.txt	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_flist.txt	(revision 115)
@@ -0,0 +1,25 @@
+# Output products list for <blk_mem_gen_v6_2>
+_xmsgs\pn_parser.xmsgs
+blk_mem_gen_ds512.pdf
+blk_mem_gen_v6_2.asy
+blk_mem_gen_v6_2.gise
+blk_mem_gen_v6_2.ngc
+blk_mem_gen_v6_2.vhd
+blk_mem_gen_v6_2.vho
+blk_mem_gen_v6_2.xco
+blk_mem_gen_v6_2.xise
+blk_mem_gen_v6_2_flist.txt
+blk_mem_gen_v6_2_readme.txt
+blk_mem_gen_v6_2_ste\example_design\blk_mem_gen_v6_2_top.ucf
+blk_mem_gen_v6_2_ste\example_design\blk_mem_gen_v6_2_top.vhd
+blk_mem_gen_v6_2_ste\example_design\blk_mem_gen_v6_2_top.xdc
+blk_mem_gen_v6_2_ste\example_design\bmg_wrapper.vhd
+blk_mem_gen_v6_2_ste\implement\implement.bat
+blk_mem_gen_v6_2_ste\implement\implement.sh
+blk_mem_gen_v6_2_ste\implement\planAhead_rdn.bat
+blk_mem_gen_v6_2_ste\implement\planAhead_rdn.sh
+blk_mem_gen_v6_2_ste\implement\planAhead_rdn.tcl
+blk_mem_gen_v6_2_ste\implement\xst.prj
+blk_mem_gen_v6_2_ste\implement\xst.scr
+blk_mem_gen_v6_2_xmdf.tcl
+summary.log
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_readme.txt
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_readme.txt	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_readme.txt	(revision 115)
@@ -0,0 +1,203 @@
+                Core name: Xilinx LogiCORE Block Memory Generator
+                Version: 6.2
+                Release Date: June 22, 2011
+
+
+================================================================================
+
+This document contains the following sections:
+
+1. Introduction
+2. New Features
+3. Supported Devices
+4. Resolved Issues
+5. Known Issues
+6. Technical Support
+7. Core Release History
+8. Legal Disclaimer
+
+================================================================================
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v6.2 
+solution. For the latest core updates, see the product page at:
+ 
+ http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
+
+
+2. NEW FEATURES
+
+  - ISE 13.2 software support
+  - Virtex-7L, Kintex-7L, Artix-7* and Zynq-7000* device support
+
+3. SUPPORTED DEVICES
+
+The following device families are supported by the core for this release.
+
+Zynq-7000*
+
+Virtex-7 
+Virtex-7 XT (7vx485t)
+Virtex-7 -2L
+
+Kintex-7
+Kintex-7 -2L 
+
+Artix-7*
+
+Virtex-6 XC CXT/LXT/SXT/HXT
+Virtex-6 XQ LXT/SXT                                                       
+Virtex-6 -1L XQ LXT/SXT 
+
+Spartan-6 XC LX/LXT 
+Spartan-6 XA 
+Spartan-6 XQ LX/LXT       
+Spartan-6 -1L XQ LX
+
+Virtex-5 XC LX/LXT/SXT/TXT/FXT
+Virtex-5 XQ LX/ LXT/SXT/FXT                                                
+
+Virtex-4 XC LX/SX/FX
+Virtex-4 XQ LX/SX/FX
+Virtex-4 XQR LX/SX/FX                                                  
+
+Spartan-3 XC
+Spartan-3 XA                                                                      
+Spartan-3A XC 3A / 3A DSP / 3AN DSP                                      
+Spartan-3A XA 3A / 3A DSP                                                    
+Spartan-3E XC                                        
+Spartan-3E XA 
+
+*To access these devices in the ISE Design Suite, contact your Xilinx FAE.
+
+4. RESOLVED ISSUES
+
+The following issues are resolved in Block Memory Generator v6.2: 
+  
+  1. Core errors in NGDBuild when the depth is too large (especially for Spartan-6 devices)
+   Version Fixed: v6.2 
+   - CR 587481
+   - AR 39718
+
+5. KNOWN ISSUES 
+
+The following are known issues for v6.2 of this core at time of release:
+
+  1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)
+    Work around: The user must review the possible scenarios that causes the collission and revise 
+     their design to avoid those situations.
+    - CR588505
+  
+    Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with 
+          Write Mode = Read First in conjunction with asynchronous clocking
+   
+  2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
+
+  3. Core does not generate for large memories. Depending on the
+     machine the ISE CORE Generator software runs on, the maximum size of the memory that
+     can be generated will vary.  For example, a Dual Pentium-4 server 
+     with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
+    - CR 415768
+    - AR 24034
+  
+The most recent information, including known issues, workarounds, and resolutions for 
+this version is provided in the IP Release Notes User Guide located at
+  
+       www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+   
+6. TECHNICAL SUPPORT 
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
+03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
+09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support
+03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue 
+12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power
+                                       Device support; Automotive Spartan 3A
+                                       DSP device support
+09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3
+06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2
+04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1
+09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8
+03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7
+10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6
+07/2007     Xilinx, Inc.  2.5          Revised to v2.5
+04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1
+02/2007     Xilinx, Inc.  2.4          Revised to v2.4
+11/2006     Xilinx, Inc.  2.3          Revised to v2.3
+09/2006     Xilinx, Inc.  2.2          Revised to v2.2
+06/2006     Xilinx, Inc.  2.1          Revised to v2.1
+01/2006     Xilinx, Inc.  1.1          Initial release
+================================================================================
+
+8. Legal Disclaimer
+
+ (c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved.
+ 
+ This file contains confidential and proprietary information
+ of Xilinx, Inc. and is protected under U.S. and
+ international copyright and other intellectual property
+ laws.
+ 
+ DISCLAIMER
+ This disclaimer is not a license and does not grant any
+ rights to the materials distributed herewith. Except as
+ otherwise provided in a valid license issued to you by
+ Xilinx, and to the maximum extent permitted by applicable
+ law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+ (2) Xilinx shall not be liable (whether in contract or tort,
+ including negligence, or under any other theory of
+ liability) for any loss or damage of any kind or nature
+ related to, arising under or in connection with these
+ materials, including for any direct, or any indirect,
+ special, incidental, or consequential loss or damage
+ (including loss of data, profits, goodwill, or any type of
+ loss or damage suffered as a result of any action brought
+ by a third party) even if such damage or loss was
+ reasonably foreseeable or Xilinx had been advised of the
+ possibility of the same.
+ 
+ CRITICAL APPLICATIONS
+ Xilinx products are not designed or intended to be fail-
+ safe, or for use in any application requiring fail-safe
+ performance, such as life-support or safety devices or
+ systems, Class III medical devices, nuclear facilities,
+ applications related to the deployment of airbags, or any
+ other applications that could lead to death, personal
+ injury, or severe property or environmental damage
+ (individually and collectively, "Critical
+ Applications"). Customer assumes the sole risk and
+ liability of any use of Xilinx products in Critical
+ Applications, subject only to applicable laws and
+ regulations governing limitations on product liability.
+ 
+ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+ PART OF THIS FILE AT ALL TIMES.
+
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.ucf
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.ucf	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.ucf	(revision 115)
@@ -0,0 +1,61 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Tx Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+NET "CLKA"  TNM_NET     = "CLKA";
+  
+NET "CLKB"  TNM_NET     = "CLKB";
+
+TIMESPEC "TS_CLKA"      = PERIOD "CLKA"  25 MHZ;
+  
+TIMESPEC "TS_CLKB"      = PERIOD "CLKB"  25 MHZ;
+
+################################################################################
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.vhd	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.vhd	(revision 115)
@@ -0,0 +1,178 @@
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v6.2 Core - Top-level core wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_wrapper.vhd
+--
+-- Description:
+--   This is the actual BMG core wrapper.
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY blk_mem_gen_v6_2_top IS
+  PORT (
+      --Inputs - Port A
+    ENA            : IN STD_LOGIC;  --opt port
+  
+    WEA            : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRA          : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+  
+    DINA           : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+  
+    CLKA       : IN STD_LOGIC;
+
+  
+      --Inputs - Port B
+    ENB            : IN STD_LOGIC;  --opt port
+    ADDRB          : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    DOUTB          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    CLKB           : IN STD_LOGIC
+
+  );
+
+END blk_mem_gen_v6_2_top;
+
+
+ARCHITECTURE xilinx OF blk_mem_gen_v6_2_top IS
+
+  COMPONENT BUFG IS
+  PORT (
+     I      : IN STD_ULOGIC;
+     O      : OUT STD_ULOGIC
+  );
+  END COMPONENT;
+
+  COMPONENT blk_mem_gen_v6_2 IS
+  PORT (
+      --Port A
+    ENA        : IN STD_LOGIC;  --opt port
+  
+    WEA        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRA      : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+  
+    DINA       : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+  
+    CLKA       : IN STD_LOGIC;
+
+  
+      --Port B
+    ENB        : IN STD_LOGIC;  --opt port
+    ADDRB      : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    DOUTB      : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    CLKB       : IN STD_LOGIC
+
+
+  );
+  END COMPONENT;
+
+  SIGNAL CLKA_buf     : STD_LOGIC;
+  SIGNAL CLKB_buf     : STD_LOGIC;
+  SIGNAL S_ACLK_buf   : STD_LOGIC;
+
+BEGIN
+
+  bufg_A : BUFG
+    PORT MAP (
+     I => CLKA,
+     O => CLKA_buf
+     );
+
+  bufg_B : BUFG
+    PORT MAP (
+     I => CLKB,
+     O => CLKB_buf
+     );
+
+
+  bmg0 : blk_mem_gen_v6_2
+    PORT MAP (
+      --Port A
+      ENA        => ENA,
+  
+      WEA        => WEA,
+      ADDRA      => ADDRA,
+  
+      DINA       => DINA,
+
+      CLKA       => CLKA_buf,
+
+  
+      --Port B
+      ENB        => ENB, 
+      ADDRB      => ADDRB,
+      DOUTB      => DOUTB,
+      CLKB       => CLKB_buf
+
+    );
+
+END xilinx;
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.xdc
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.xdc	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.xdc	(revision 115)
@@ -0,0 +1,56 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ]
+  
+create_clock -name "TS_CLKB" -period 20.0 [ get_ports CLKB ]
+################################################################################
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/bmg_wrapper.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/bmg_wrapper.vhd	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/bmg_wrapper.vhd	(revision 115)
@@ -0,0 +1,269 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v6.2 Core - Top-level wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_wrapper.vhd
+--
+-- Description:
+--   This is the top-level BMG wrapper (over BMG core).
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+-- Configured Core Parameter Values:
+-- (Refer to the SIM Parameters table in the datasheet for more information on
+-- the these parameters.)
+--    C_FAMILY                    :  spartan6 
+--    C_XDEVICEFAMILY             :  spartan6 
+--    C_INTERFACE_TYPE            :  0 
+--    C_AXI_TYPE                  :  1 
+--    C_AXI_SLAVE_TYPE            :  0 
+--    C_AXI_ID_WIDTH              :  4 
+--    C_MEM_TYPE                  :  1 
+--    C_BYTE_SIZE                 :  8 
+--    C_ALGORITHM                 :  1 
+--    C_PRIM_TYPE                 :  1 
+--    C_LOAD_INIT_FILE            :  0 
+--    C_INIT_FILE_NAME            :  no_coe_file_loaded 
+--    C_USE_DEFAULT_DATA          :  0 
+--    C_DEFAULT_DATA              :  0 
+--    C_RST_TYPE                  :  SYNC 
+--    C_HAS_RSTA                  :  0 
+--    C_RST_PRIORITY_A            :  CE 
+--    C_RSTRAM_A                  :  0 
+--    C_INITA_VAL                 :  0 
+--    C_HAS_ENA                   :  1 
+--    C_HAS_REGCEA                :  0 
+--    C_USE_BYTE_WEA              :  1 
+--    C_WEA_WIDTH                 :  1 
+--    C_WRITE_MODE_A              :  WRITE_FIRST 
+--    C_WRITE_WIDTH_A             :  8 
+--    C_READ_WIDTH_A              :  8 
+--    C_WRITE_DEPTH_A             :  8192 
+--    C_READ_DEPTH_A              :  8192 
+--    C_ADDRA_WIDTH               :  13 
+--    C_HAS_RSTB                  :  0 
+--    C_RST_PRIORITY_B            :  CE 
+--    C_RSTRAM_B                  :  0 
+--    C_INITB_VAL                 :  0 
+--    C_HAS_ENB                   :  1 
+--    C_HAS_REGCEB                :  0 
+--    C_USE_BYTE_WEB              :  1 
+--    C_WEB_WIDTH                 :  1 
+--    C_WRITE_MODE_B              :  WRITE_FIRST 
+--    C_WRITE_WIDTH_B             :  8 
+--    C_READ_WIDTH_B              :  8 
+--    C_WRITE_DEPTH_B             :  8192 
+--    C_READ_DEPTH_B              :  8192 
+--    C_ADDRB_WIDTH               :  13 
+--    C_HAS_MEM_OUTPUT_REGS_A     :  0 
+--    C_HAS_MEM_OUTPUT_REGS_B     :  0 
+--    C_HAS_MUX_OUTPUT_REGS_A     :  0 
+--    C_HAS_MUX_OUTPUT_REGS_B     :  0 
+--    C_HAS_SOFTECC_INPUT_REGS_A  :  0 
+--    C_HAS_SOFTECC_OUTPUT_REGS_B :  0 
+--    C_MUX_PIPELINE_STAGES       :  0 
+--    C_USE_ECC                   :  0 
+--    C_USE_SOFTECC               :  0 
+--    C_HAS_INJECTERR             :  0 
+--    C_SIM_COLLISION_CHECK       :  ALL 
+--    C_COMMON_CLK                :  0 
+--    C_DISABLE_WARN_BHV_COLL     :  0 
+--    C_DISABLE_WARN_BHV_RANGE    :  0 
+
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY bmg_wrapper IS
+  PORT (
+    --Port A
+    CLKA       : IN STD_LOGIC;
+    RSTA       : IN STD_LOGIC;  --opt port
+    ENA        : IN STD_LOGIC;  --optional port
+    REGCEA     : IN STD_LOGIC;  --optional port
+    WEA        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRA      : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    DINA       : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    DOUTA      : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+    --Port B
+    CLKB       : IN STD_LOGIC;
+    RSTB       : IN STD_LOGIC;  --opt port
+    ENB        : IN STD_LOGIC;  --optional port
+    REGCEB     : IN STD_LOGIC;  --optional port
+    WEB        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRB      : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    DINB       : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    DOUTB      : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+    --ECC
+    INJECTSBITERR  : IN STD_LOGIC; --optional port
+    INJECTDBITERR  : IN STD_LOGIC; --optional port
+    SBITERR        : OUT STD_LOGIC; --optional port
+    DBITERR        : OUT STD_LOGIC; --optional port
+    RDADDRECC      : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
+ -- AXI BMG Input and Output Port Declarations
+
+    -- AXI Global Signals
+    S_ACLK                         : IN  STD_LOGIC;
+    S_AXI_AWID                     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+    S_AXI_AWADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXI_AWLEN                    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXI_AWSIZE                   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
+    S_AXI_AWBURST                  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_AWVALID                  : IN  STD_LOGIC;
+    S_AXI_AWREADY                  : OUT STD_LOGIC;
+    S_AXI_WDATA                    : IN  STD_LOGIC_VECTOR(7  DOWNTO 0);
+    S_AXI_WSTRB                    : IN  STD_LOGIC_VECTOR(0  DOWNTO 0);
+    S_AXI_WLAST                    : IN  STD_LOGIC;
+    S_AXI_WVALID                   : IN  STD_LOGIC;
+    S_AXI_WREADY                   : OUT STD_LOGIC;
+    S_AXI_BID                      : OUT STD_LOGIC_VECTOR(3  DOWNTO 0):= (OTHERS => '0');
+    S_AXI_BRESP                    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_BVALID                   : OUT STD_LOGIC;
+    S_AXI_BREADY                   : IN  STD_LOGIC;
+
+    -- AXI Full/Lite Slave Read (Write side)
+    S_AXI_ARID                     : IN  STD_LOGIC_VECTOR(3  DOWNTO 0);
+    S_AXI_ARADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXI_ARLEN                    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXI_ARSIZE                   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
+    S_AXI_ARBURST                  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_ARVALID                  : IN  STD_LOGIC;
+    S_AXI_ARREADY                  : OUT STD_LOGIC;
+    S_AXI_RID                      : OUT STD_LOGIC_VECTOR(3  DOWNTO 0):= (OTHERS => '0');
+    S_AXI_RDATA                    : OUT STD_LOGIC_VECTOR(7  DOWNTO 0);
+    S_AXI_RRESP                    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_RLAST                    : OUT STD_LOGIC;
+    S_AXI_RVALID                   : OUT STD_LOGIC;
+    S_AXI_RREADY                   : IN  STD_LOGIC;
+
+    -- AXI Full/Lite Sideband Signals
+    S_AXI_INJECTSBITERR            : IN  STD_LOGIC;
+    S_AXI_INJECTDBITERR            : IN  STD_LOGIC;
+    S_AXI_SBITERR                  : OUT STD_LOGIC;
+    S_AXI_DBITERR                  : OUT STD_LOGIC;
+    S_AXI_RDADDRECC                : OUT STD_LOGIC_VECTOR(12  DOWNTO 0);
+    S_ARESETN                      : IN  STD_LOGIC
+
+
+  );
+
+END bmg_wrapper;
+
+
+ARCHITECTURE xilinx OF bmg_wrapper IS
+
+  COMPONENT blk_mem_gen_v6_2_top IS
+  PORT (
+      --Port A
+    ENA            : IN STD_LOGIC;  --opt port
+  
+    WEA            : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRA          : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+  
+    DINA           : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+  
+    CLKA       : IN STD_LOGIC;
+
+  
+      --Port B
+    ENB            : IN STD_LOGIC;  --opt port
+    ADDRB          : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    DOUTB          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    CLKB           : IN STD_LOGIC
+
+
+  );
+  END COMPONENT;
+
+BEGIN
+
+  bmg0 : blk_mem_gen_v6_2_top
+    PORT MAP (
+      --Port A
+      ENA        => ENA,
+  
+      WEA        => WEA,
+      ADDRA      => ADDRA,
+  
+      DINA       => DINA,
+
+      CLKA       => CLKA,
+  
+      --Port B
+      ENB        => ENB, 
+      ADDRB      => ADDRB,
+      DOUTB      => DOUTB,
+      CLKB       => CLKB
+
+
+      );
+END xilinx;
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/implement.bat
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/implement.bat	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/implement.bat	(revision 115)
@@ -0,0 +1,41 @@
+
+rem Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+rem Synthesize the VHDL Wrapper Files
+
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+copy blk_mem_gen_v6_2_top.ngc .\results\
+
+
+rem Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+copy ..\..\blk_mem_gen_v6_2.ngc results\
+
+
+rem  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\blk_mem_gen_v6_2_top.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc6slx45-csg324-3 blk_mem_gen_v6_2_top
+
+echo 'Running map'
+map blk_mem_gen_v6_2_top -o mapped.ncd -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level VHDL model'
+netgen -ofmt vhdl -sim -tm blk_mem_gen_v6_2_top -pcf mapped.pcf -w routed.ncd routed.vhd
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/implement.sh
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/implement.sh	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/implement.sh	(revision 115)
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+#Synthesize the Wrapper Files
+echo 'Synthesizing XST wrapper file (core_top.vhd) with XST';
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+cp blk_mem_gen_v6_2_top.ngc ./results/
+
+
+# Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+cp ../../blk_mem_gen_v6_2.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/blk_mem_gen_v6_2_top.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc6slx45-csg324-3 blk_mem_gen_v6_2_top
+
+echo 'Running map'
+map blk_mem_gen_v6_2_top -o mapped.ncd -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level VHDL model'
+netgen -ofmt vhdl -sim -tm blk_mem_gen_v6_2_top -pcf mapped.pcf -w routed.ncd routed.vhd
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.bat
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.bat	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.bat	(revision 115)
@@ -0,0 +1,55 @@
+#!/bin/sh
+rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+rem 
+rem This file contains confidential and proprietary information
+rem of Xilinx, Inc. and is protected under U.S. and
+rem international copyright and other intellectual property
+rem laws.
+rem 
+rem DISCLAIMER
+rem This disclaimer is not a license and does not grant any
+rem rights to the materials distributed herewith. Except as
+rem otherwise provided in a valid license issued to you by
+rem Xilinx, and to the maximum extent permitted by applicable
+rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+rem (2) Xilinx shall not be liable (whether in contract or tort,
+rem including negligence, or under any other theory of
+rem liability) for any loss or damage of any kind or nature
+rem related to, arising under or in connection with these
+rem materials, including for any direct, or any indirect,
+rem special, incidental, or consequential loss or damage
+rem (including loss of data, profits, goodwill, or any type of
+rem loss or damage suffered as a result of any action brought
+rem by a third party) even if such damage or loss was
+rem reasonably foreseeable or Xilinx had been advised of the
+rem possibility of the same.
+rem 
+rem CRITICAL APPLICATIONS
+rem Xilinx products are not designed or intended to be fail-
+rem safe, or for use in any application requiring fail-safe
+rem performance, such as life-support or safety devices or
+rem systems, Class III medical devices, nuclear facilities,
+rem applications related to the deployment of airbags, or any
+rem other applications that could lead to death, personal
+rem injury, or severe property or environmental damage
+rem (individually and collectively, "Critical
+rem Applications"). Customer assumes the sole risk and
+rem liability of any use of Xilinx products in Critical
+rem Applications, subject only to applicable laws and
+rem regulations governing limitations on product liability.
+rem 
+rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+rem PART OF THIS FILE AT ALL TIMES.
+
+rem -----------------------------------------------------------------------------
+rem  Script to synthesize and implement the Coregen FIFO Generator
+rem -----------------------------------------------------------------------------
+rmdir /S /Q results
+mkdir results
+cd results
+copy ..\..\..\tmp\blk_mem_gen_v6_2.edf .
+planAhead -mode batch -source ..\planAhead_rdn.tcl
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.sh
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.sh	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.sh	(revision 115)
@@ -0,0 +1,55 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+#-----------------------------------------------------------------------------
+#  Script to synthesize and implement the Coregen FIFO Generator
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+cp ../../../tmp/blk_mem_gen_v6_2.edf .
+planAhead -mode batch -source ../planAhead_rdn.tcl
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.tcl
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.tcl	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.tcl	(revision 115)
@@ -0,0 +1,68 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+set device xc6slx45csg324-3
+set projName blk_mem_gen_v6_2
+set design blk_mem_gen_v6_2
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module blk_mem_gen_v6_2_top
+add_files -norecurse {../../example_design/blk_mem_gen_v6_2_top.vhd}
+add_files -norecurse {./blk_mem_gen_v6_2.edf}
+import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/blk_mem_gen_v6_2_top.xdc}
+set_property top blk_mem_gen_v6_2_top [get_property srcset [current_run]]
+synth_design
+opt_design 
+place_design 
+route_design 
+set_param sta.dlyMediator true
+write_sdf -rename_top_module blk_mem_gen_v6_2_top -file routed.sdf 
+write_verilog -nolib -mode sim -sdf_anno false -rename_top_module blk_mem_gen_v6_2_top routed.vhd
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file routed.drc
+#write_bitstream
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/xst.prj
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/xst.prj	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/xst.prj	(revision 115)
@@ -0,0 +1,1 @@
+work ../example_design/blk_mem_gen_v6_2_top.vhd
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/xst.scr
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/xst.scr	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/xst.scr	(revision 115)
@@ -0,0 +1,13 @@
+run
+-ifmt VHDL
+-ent blk_mem_gen_v6_2_top
+-p xc6slx45-csg324-3
+-ifn xst.prj
+-write_timing_constraints No
+-iobuf YES
+-max_fanout 100
+-ofn blk_mem_gen_v6_2_top 
+-ofmt NGC
+-bus_delimiter ()
+-hierarchy_separator /
+-case Maintain
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_xmdf.tcl
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_xmdf.tcl	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_xmdf.tcl	(revision 115)
@@ -0,0 +1,123 @@
+# The package naming convention is <core_name>_xmdf
+package provide blk_mem_gen_v6_2_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::blk_mem_gen_v6_2_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::blk_mem_gen_v6_2_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name blk_mem_gen_v6_2
+}
+# ::blk_mem_gen_v6_2_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::blk_mem_gen_v6_2_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2.vho
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.xdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/example_design/bmg_wrapper.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/implement/planAhead_rdn.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/implement/planAhead_rdn.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/implement/planAhead_rdn.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module blk_mem_gen_v6_2
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/coregen.cgp
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/coregen.cgp	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/coregen.cgp	(revision 115)
@@ -0,0 +1,9 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = VHDL
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET package = csg324
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/create_mem8k8.tcl
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/create_mem8k8.tcl	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/create_mem8k8.tcl	(revision 115)
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator create command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "mem8k8" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc6slx45-3csg324 VHDL ]
+
+if { $result == 0 } {
+   puts "Core Generator create command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator create command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator create cancelled."
+}
+exit $result
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/create_mem_4k8.tcl
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/create_mem_4k8.tcl	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/create_mem_4k8.tcl	(revision 115)
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator create command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "mem_4k8" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc6slx45-3csg324 VHDL ]
+
+if { $result == 0 } {
+   puts "Core Generator create command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator create command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator create cancelled."
+}
+exit $result
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/edit_mem_4k8.tcl
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/edit_mem_4k8.tcl	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/edit_mem_4k8.tcl	(revision 115)
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator edit command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_edit "mem_4k8" xc6slx45-3csg324 VHDL ]
+
+if { $result == 0 } {
+   puts "Core Generator edit command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator edit command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator edit cancelled."
+}
+exit $result
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.asy
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.asy	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.asy	(revision 115)
@@ -0,0 +1,41 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 mem8k8
+RECTANGLE Normal 32 32 544 1376
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName addra[12:0]
+PINATTR Polarity IN
+LINE Wide 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName dina[7:0]
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName ena
+PINATTR Polarity IN
+LINE Wide 0 208 32 208
+PIN 0 208 LEFT 36
+PINATTR PinName wea[0:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName clka
+PINATTR Polarity IN
+LINE Wide 0 432 32 432
+PIN 0 432 LEFT 36
+PINATTR PinName addrb[12:0]
+PINATTR Polarity IN
+LINE Normal 0 496 32 496
+PIN 0 496 LEFT 36
+PINATTR PinName enb
+PINATTR Polarity IN
+LINE Normal 0 624 32 624
+PIN 0 624 LEFT 36
+PINATTR PinName clkb
+PINATTR Polarity IN
+LINE Wide 576 368 544 368
+PIN 576 368 RIGHT 36
+PINATTR PinName doutb[7:0]
+PINATTR Polarity OUT
+
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.gise
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.gise	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.gise	(revision 115)
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="mem8k8.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_v6_2_readme.txt" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="mem8k8.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="mem8k8.sym" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VHO" xil_pn:name="mem8k8.vho" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.ngc
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.ngc	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.ngc	(revision 115)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$0a340<,[o}e~g`n;"2*731&=$:,)<4-0;8456789:;<9>40123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?15927?OIX\^1mij}a=31>586<2;86D@_UU8b`ate4881<3?;;069MKVR\3KOH_O31283:42<9=0BB][[:@FGVG:6;3:5==5>:HLSQQ<pmh6;6=0>2:11>LHW]]0OEL2<1;2=57=4:3CE\XZ5DH@?74<76890??4@UURVP?BHI59:6=0>3:11>JSSX\^1HBL33083:47<<3CE\XZ5DHRB86<768;087GAPTV9@LVE4:0;2<>44;KMTPR=_LK7?7>11197>LHW]]0\IO2<:1<26>2=G\^[YY4KOQC?7?699;1?6B[[PTV9@JVE4:0;2h59smz71fu`;;>&?<?48;KMTPR=l`dj0:4?>018<?IR\Y__6iaztc>4>58?3HNO^L2?>89B@ATF48:556OKDSC?548>3HNO^L2>2?`8EABUI5;86=06;@FGVD:6;720MIJ]A=3=<>GCL[K7>364AEFQE95902KOH_O34?:8EABUI5?546OKDSC?2;><IMNYM1918:CG@WG;0720MIJ]A=;=<>GCL[H7<374AEFQF977601JHI\M<03==>GCL[H7=?0m;@FGVG:6;3:556OKDS@?568?3HNO^O2>>99B@ATE4;437LJKRC>0:==FLMXI0907;@FGVG:2611JHI\M<7<;?DBCZK6<255NDEPA8=8?3HNO^O26>29BHI><J\YTECH@2:AF57=D@LI@SAGLEOQF[Q_WM=1H@F>9;BNH5=613JF@>:>:;BNH6]><KEA9T<6?5:AOO<633JF@M85LLJC23>EKCH;O>:5LLJC2@11<KEAJ=I6;;BNHF0=DDBH:96MCKB36?FJLL8?0OAEKVb9@HNBQWMC]EIK:;BNHB]><KEAMT<6?9:ALIHOS\LN:86M@RD]DAKCUI]CDBRGAFN58GWCF\LNh7IO[A^UJ@QNXIj1OMYOPWHFWLZD13MCJ0=08;EKB8469?2NBM1?>>69GMD:6:7=0HDO312<4?AOF48>5;6JFA=36:2=CAH6::394DHC?52803MCJ0<617:FJE97>6?1OEL2>>69GMD:587=0HDO320<4?AOF4;85;6JFA=00:2=CAH698394DHC?60803MCJ0?817:FJE9406>1OEL2=8?58@LG;:04=7IGN<3<4?AOF4::556JFA=12>5803MCJ0>?16:FJE959>2NBM1:16:FJE939>2NBM1816:FJE919>2NBM1616:FJE9?9>2NBN1>17:FJF9776>1OEO2>1?58@LD;9;4<7IGM<01=3>BNJ5;?2:5KIC>21;1<L@H7=;08;EKA8419?2NBN1?7>69GMG:617<0HDL31?58@LD;:94<7IGM<33=3>BNJ5892:5KIC>17;1<L@H7>908;EKA8739?2NBN1<9>69GMG:5?7=0HDL329<4?AOE4;35:6JFB=0=3>BNJ59;245KIC>05?69?2NBN1=>>79GMG:46?1OEO2;>79GMG:26?1OEO29>79GMG:06?1OEO27>79GMG:>6>1OE]O30?58@LVF484<7IG_A=0==>BNXH686=08;EKSE959?2NB\O2?>69GMUD;97=0HD^M<3<:?AOWJ591<394DHRA86813MEJ0=08;EMB8469?2NDM1?>>69GKD:6:7=0HBO312<4?AIF48>5;6J@A=36:2=CGH6::394DNC?52803MEJ0<617:FLE97>6?1OCL2>>69GKD:587=0HBO320<4?AIF4;85;6J@A=00:2=CGH698394DNC?60803MEJ0?817:FLE9406>1OCL2=8?58@JG;:04=7IAN<3<4?AIF4::556J@A=12>5803MEJ0>?16:FLE959>2NDM1:16:FLE939>2NDM1816:FLE919>2NDM1616:FLE9?9?2NDMR\JG79GKG:76>1OCO2>0?58@JD;984<7IAM<00=3>BHJ5;82:5KOC>20;1<LFH7=808;EMA8409?2NDN1?8>69GKG:607=0HBL318<5?AIE484<7IAM<32=3>BHJ58:2:5KOC>16;1<LFH7>>08;EMA8729?2NDN1<:>69GKG:5>7=0HBL326<4?AIE4;25;6J@B=0::3=CGK692:5KOC>04;?<LFH7?<4?>69GKG:497<0HBL33?48@JD;<7<0HBL35?48@JD;>7<0HBL37?48@JD;07<0HBL39?58@JDXZLM<7IA_A=2=3>BHXH6:2:5KOQC?6;?<LFZJ0>4?>69GKUG;;7=0HB^M<1<4?AIWJ5;5;6J@PC>1:<=CGYH7?7>17:FLTG:46:1NBL=4EO@a?@HXZZ^YM@QNb:GM[WUSZHGTN85IAMQF5>A43NDO46GAIUR\45><AGC_\R>>8:KMMQVX8;20ECG[P^20<>OIA]ZT<964IOKWTZ6202CEEY^P07:8MKOSXV:<;6GAIU]342=NF@^T<<94IOKW[5403@DBXR><7:KMMQY7<>1BBDZP0458MKOSW9<<7D@FT^243>OIA]U;4:5FNHV\4<1<AGC_S=O8;HLJPZ6E?2CEEYQ?C69JJLRX8M=0ECG[_1G4?LHN\V:M;6GAIU]242=NF@^T=<94IOKW[4403@DBXR?<7:KMMQY6<>1BBDZP1458MKOSW8<<7D@FT^343>OIA]U:4:5FNHV\5<1<AGC_S<O8;HLJPZ7E?2CEEYQ>C69JJLRX9M=0ECG[_0G4?LHN\V;M;6GAIU]142=NF@^T><94IOKW[7403@DBXR<<7:KMMQY5<>1BBDZP2458MKOSW;<<7D@FT^043>OIA]U94:5FNHV\6<1<AGC_S?O8;HLJPZ4E?2CEEYQ=C69JJLRX:M=0ECG[_3G4?LHN\V8M;6GAIU]042=NF@^T?<94IOKW[6403@DBXR=<7:KMMQY4<>1BBDZP3458MKOSW:<<7D@FT^143>OIA]U84:5FNHV\7<1<AGC_S>O8;HLJPZ5E?2CEEYQ<C69JJLRX;M=0ECG[_2G4?LHN\V9M:6GAIU]B2>OIA]UI56GAIU]EMIC13EEJHHJ9;MM@O@B03EELENOCc:ObnjtQm{ybccm4MhllvScu{`ee>6@>7:LFPRIUC=1ECCK7;N,42}bXD=1[M_Zn;QKM[GSTAMRi7]GA_CWPJDKB>2ZXHB@Ja:PBIG71J^OY:6\JGBGB2>TBOJOI86\\T@68VVRE?2XXXYW_Ed9QWQYWZ@EYEYWPAd9QWQYWZ@EYEYWPB038WMTBOVOSX_OLT^LDG`=T@[OLS@GA_RKYA45<[@GTOBBCIRKLJZEOMJAj7^GB_EGUMFC13ZE^^NK7;RRBVQGI>>1X^[OC_@58WWPFDVH=7^ZNTTQ7?V_IK=1_U]K86:W3+}usWkf`S`kb_fgmawgsg{%lblzfvd`nc+hf|`|nSobd_lgn[bci'kgei lsup,vdkkgfzP<P }al,q+v0Xffceey }al-P@U(TADZGIR^]IL3;*wgj??1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_4[)zhg%~"}9_omjjlr)zhg$_I^!SHOSH@YWZ@G:4#|nm648Q5){}Ui`fQbel]dakcui}ey#j`nthtffha)fh~bzhQmlj]nahY`mg%}magk.bqwv*tfeeed|V<R.scn*w)t>Vddecg{.scn+VBW&ZCF\AKPPSKN5=(uid==7X> xrv\fimXelgTkh`jr`vlv*aii}c}ioch.ocwmscXjeaTahcPgdl,rdjnl'ixx!}alnlku]4U'xja#| s7]mklhn|'xja"]KP/QJIUJBWYXBA<6!r`o`?PUBZV\B_DLCE89UM@QX\PZN:6YJA=2=2>QBI5;5:6YJA=0=<>QBI591<384WDC?7;0<_LH7<384WD@?5;0<_LH7>364WD@?7?69>2]NN1=1b:UQMQCXN@XXXn5XRHVF[HICMVKh7Z\FTD]NKACXJ8n0TDBFNY/[@G&7&8*XXXL/0/3#EVENA?1S_YBFB69[WQY@FMh0TRM@RD]JJCI13QniSDji;Yfk[Utne_oydaa119[`hYJiceyZh||inl24>^ceVGbbb|Yesqjkk5<Pz~87Tk|8:cg`wg;8730mij}a=33:<=flmxj0<?1b:cg`wg;9;0;245ndepb844902koho31?:8eabui58546okdsc?7;><imnym1:18:cg`wg;=720mij}a=4=<>gcl{k7;364aefqe9>902koho39?:8eabuj5:556okds`?558>3hno~o2>1?`8eabuj5;96=06;`fgvg:6:720mij}b=3=<>gcl{h7>364aefqf95902kohl34?:8eabuj5?546okds`?2;><imnyn1918:cg`wd;0720mij}b=;=5==edbUfi`Qheo]dakcuajUhy|>8:`ooZkbeVmnbR~}il]tmaroW8;37obd_lgn[bciWyxbaRyfduj\64><jeaTahcPgdl\twojW~coxeQ<199ahnYjmdUlicQrho\slbs`V>:h6lck^ofiZabfVzye`Qxr`rsawYt>V;:h6lck^ofiZabfVzye`Qxr`rsawYt>V8:h6lck^ofiZabfVzye`Qxr`rsawYt>V9:h6lck^ofiZabfVzye`Qxr`rsawYt>V>m7obd_lgn[bciW}e{==5mlj]nahY`mgU}:R<=c:`ooZkbeVmnbRx9_3.#\ljnfq*HC_K/Gdlfvdrhz);8">?;;cnh[hcjWnoeS{8P2^zpp45<jeaTahcPiorvpZdkgja:86lck^ofiZir|ySob`cj68gimf<2iggo94dhlb85803mcem1?17:fjjd:56>1oeco33?58`lhf4=4<7igaa=7=3>bnfh6=245kioc?3?69?2nbbl28>99gkpre49437iaztc>2:==cg|~i0?07;emvpg:4611ocxzm<5<;?air|k6>255kotva838f3me~xo28:1<;?air|k6<2>5jn`18akd13dof4f6;9`9nah>l0%hggRcjm^efjZp1W;&poRokdsc\slbs`4;8 nQndepa[roc|a7:?!mPamelvlroe4;'oRowi^kg[roc|a7? nQnxh]phdpbW}s{i0>#c^c{mZr~xl7: nQmyug\wl|b50&hSnabmnl\gim:8%iThhhnumv\`drf59&hSig|acnf[rgufVhczRm`lm?3(fYcazki`hQxasl\fmpXzhdli0>#c^goegiui}cdbRjfr<F9+HVNWAIG#Yk|t^Vji`t(ayid~hQkis-wiu)Xkn%'oRhnmhnz9vvfz}ke:!mPh`q\e}oXam7; nQgar]fjd;6$jUcm~Qjnc?2(fYoizUbbgkltdpq95*dWakxS`kb_nwwtprXzlmxSl3?,b]kevYjmdUdyy~zt^pfcvYe59&hSeo|_lw{[jssx|~T~hi|_`?3(fYoizUfyuQ`uurvpZtbozUi1="l_icp[wc`klk6<!mPh`q\v`admk7; nQgar]qwqg:8%iTdl}Prrva95*dWakxS~aitda`[lhw}}Uyij}Pa<2/gZnf{Vydjyklc^mvpussW{olRl20-a\mkosWocgiR`nmd?mkZehmVlb`hQco`ff`)eXagcmRxnl<2/gZoia}hTzlb20-a\mkrbzokhiRzvpd?3(fYkghnTecg{_gkoa86+kVgnaRzvpd?2(fYj}qU{e}kciog\wqg`mz7; nQrho\p|vb58&hSknd^fftqnXi42:5<"l_sgb`Zbbx}bTn06>90.`[wcflV}bhyfPa<:/gZtbimU|eizg_c?;(fYu{}U{~da}iu{\e8EB$jUyyQrhmqmqXj4IN nQ}su]w}uc:[PDH nQ}supbiZg:8%iT~~z}al]a95*dWzcfSnaclhqjkkYd`li`1LBC,b]vw`Yeq}oT{ho20-a\qvcXjp~nSzkm=1.`[pubWmommxb{_ecwe86+kVxiRklc<2/gZstmVydjyklc<2/gZqbiV}bhyf21-a\s`dX`nd0?#c^uqmqcXllzdRo280;2(fYpz`~nSikti]a9=7>9%iT{g{e^ol``Yf5^XBXHQIISQW(fYpz`~nS`ake^`>SWOSMVLB^^Z#c^uqmqcX`ndRo28-a\swosmV}bhyfPb<:/gZ~cmchikobim{>wugu|hd=q<o4mdo;o=*edbUfi`Qheo]u2Z4+st20bjmmuhng<>qbi5:1<384wdc?4;{GHy92<6NOx0`b>C<328qX8i4>768201<6;:?:<k4=7c42k70=3;0b<99:79'525=9?l0q^:m:054>42328989<>i:35a=7=T9:i1=oj50;307077n38<n484S5`95gb=83;8?8??f;04f<1<l8hj6=4>:0yP0a<6?>0:894>32724c<5?k3:7{Z>5483>4<62::p_9j51659512=9:9>==h526`:5>"6>80:?h5Y16696~s6;o0:7x?;0;28y!73=3;87o?ma;296c<22::pD<8?;%36f?7ei2P897;t8;6951<228?1q)?82;3b4>"4?3;io6*;c;3af>"6=;0:7)?:1;34<>o6jo0;6)?;7;3aa>h6<?0;76g>7e83>!73?3;<o6`>4783?>o6?k0;6)?;7;34g>h6<?0:76g>7`83>!73?3;<o6`>4781?>o60?0;6)?;7;34g>h6<?0876g>8483>!73?3;<o6`>4787?>o60=0;6)?;7;34g>h6<?0>76g>8283>!73?3;<o6`>4785?>o60;0;6)?;7;34g>h6<?0<76g>8083>!73?3;<o6`>478;?>o6090;6)?;7;34g>h6<?0276g>7g83>!73?3;<o6`>478b?>o6?l0;6)?;7;34g>h6<?0i76g>7883>!73?3;<o6`>478`?>o6il0;6)?;7;3b`>h6<?0;76g>ab83>!73?3;jh6`>4782?>o6ik0;6)?;7;3b`>h6<?0976g>a`83>!73?3;jh6`>4780?>o6i00;6)?;7;3b`>h6<?0?76g>a983>!73?3;jh6`>4786?>o6i>0;6)?;7;3b`>h6<?0=76g>a783>!73?3;jh6`>4784?>o60k0;6)?;7;3;e>h6<?0;76g>8883>!73?3;3m6`>4782?>o6010;6)?;7;3;e>h6<?0976g>9583>!73?3;3m6`>4780?>o61:0;6)?;7;3;e>h6<?0?76g>9383>!73?3;3m6`>4786?>o6180;6)?;7;3;e>h6<?0=76g>9183>!73?3;3m6`>4784?>o60o0;6)?;7;3;e>h6<?0376g>8d83>!73?3;3m6`>478:?>o60m0;6)?;7;3;e>h6<?0j76g>8b83>!73?3;3m6`>478a?>o60>0;6)?;7;3;e>h6<?0h76g>a583>>o6j10;66g>a483>>o6j00;66a>b683>!73?3;i:6`>4783?>i6j<0;6)?;7;3a2>h6<?0:76a>b583>!73?3;i:6`>4781?>i6j:0;6)?;7;3a2>h6<?0876a>b383>!73?3;i:6`>4787?>i6j80;6)?;7;3a2>h6<?0>76a>b183>!73?3;i:6`>4785?>i6io0;6)?;7;3a2>h6<?0<76l>7083>4<729q/=8l5f19K526<@8<;7bki:188yg72k3:1nn4?:1y'50d=9=30D<9?;I354>\4=3ip:795d;32>`<6:3l1n7o5c;33><<zf=o1>6`;f;08jgb=82doj7>4$da9a`=#mm0ni6*i1;18 c4=;2.m?7=4$g697>"a=390(k853:&e3?5<,o21?6*i9;18 cg=;2.mn7=4$ga97>"al390(kk53:&eb?5<,8:;6>5+11397>"68;087)??3;18 4632:1/==;53:&243<43-;;;7=4$02;>6=#9931?6*>0`80?!77j390(<>l:29'55b=;2.:<h4<;%33b?5<,8;;6>5+10397>"69;087)?>3;18 4732:1/=<;53:&253<43-;:;7=4$03;>6=#9831?6*>1`80?!76j390(<?l:29'54b=;2.:=h4<;%32b?5<,88;6>5+13397>"6:;087)?=3;18 4432:1/=?;53:&263<43-;9;7=4$00;>6=#9;31?6*>2`80?!75j390(<<l:29'57b=;2.:>h4<;%31b?5<,89;6>5+12397>"6;;087)?<3;18 4532:1/=>;53:&273<43-;8;7=4$01;>6=#9:31>6*>3`81?!74j3;??6*>4d821d=#9=l1?;5+142973=#9<91?95+1469500<,8?<6?5+14:96>"6>m0::n5+17g953e<a8>j6=44i2g94?=nmk0;66g>4e83>>o3;3:17d?;b;29?l73k3:17dkn:188m<0=83.:8:465:l203<732c287>5$064><3<f8>=6<54i8194?"6<>0296`>4781?>o>:3:1(<:8:878j4212:10e<89:18'511=9??0b<:9:198m403290/=9951778j4212810e<8<:18'511=9??0b<:9:398m405290/=9951778j4212:10co;50;&202<e<2d:8;4?;:ma7?6=,8><6o:4n065>4=<gk;1<7*>468a0>h6<?0976am0;29 4202k>0b<:9:298kd`=83.:8:4m4:l203<332eji7>5$064>g2<f8>=6854o`f94?"6<>0i86`>4785?>ifk3:1(<:8:c68j4212>10cll50;&202<e<2d:8;47;:mbe?6=,8><6o:4n065><=<gh31<7*>468a0>h6<?0j76an8;29 4202k>0b<:9:c98kd0=83.:8:4m4:l203<d32ej97>5$064>g2<f8>=6i54o`694?"6<>0i86`>478f?>if;3:1(<:8:c68j4212o10cl<50;&202<e<2d:8;4>0:9le4<72-;?;7l;;o372?7632ej<7>5$064>g2<f8>=6<<4;n;e>5<#9==1n95a154956=<g0o1<7*>468a0>h6<?0:865`9e83>!73?3h?7c?;6;36?>iek3:1(<:8:c68j42128<07blm:18'511=j=1e=9851698kgg=83.:8:4m4:l203<6021dn44?:%373?d33g;?:7?6;:ma<?6=,8><6o:4n065>4g<3fh<6=4+1559f1=i9=<1=o54oc494?"6<>0i86`>4782g>=hj;0;6)?;7;`7?k73>3;o76an7;29 4202k>0b<:9:0g8?j?d290/=995b59m510=9o10e<l50;&202<6i2d:8;4?;:k2=?6=,8><6<o4n065>4=<a821<7*>4682e>h6<?0976g>7;29 42028k0b<:9:298m72=83.:8:4>a:l203<332c9?7>5$064>4g<f8>=6854i3094?"6<>0:m6`>4785?>o593:1(<:8:0c8j4212>10e?>50;&202<6i2d:8;47;:k2b?6=,8><6<o4n065><=<a8o1<7*>4682e>h6<?0j76g>d;29 42028k0b<:9:c98m4e=83.:8:4>a:l203<d32c::7>5$064>4g<f8>=6i54i3c94?"6<>0956`>4783?>o503:1(<:8:3;8j4212810e?950;&202<512d:8;4=;:k12?6=,8><6?74n065>6=<a:91<7*>4681=>h6<?0?76g<2;29 4202;30b<:9:498m67=83.:8:4=9:l203<132c8<7>5$064>7?<f8>=6:54i3d94?"6<>0956`>478;?>o5m3:1(<:8:3;8j4212010e?j50;&202<512d:8;4n;:k1g?6=,8><6?74n065>g=<a;h1<7*>4681=>h6<?0h76g=5;29 4202;30b<:9:e98m=g=83.:8:479:l203<732c347>5$064>=?<f8>=6<54i9494?"6<>0356`>4781?>o?=3:1(<:8:9;8j4212:10e5:50;&202<?12d:8;4;;:k;7?6=,8><6574n065>0=<a181<7*>468;=>h6<?0=76g71;29 4202130b<:9:698m=6=83.:8:479:l203<?32c<j7>5$064>=?<f8>=6454i6g94?"6<>0356`>478b?>o0l3:1(<:8:9;8j4212k10e:l50;&202<?12d:8;4l;:k4e?6=,8><6574n065>a=<a>31<7*>468;=>h6<?0n76g88;29 4202130b<:9:g98m21=83.:8:479:l203<6821b;;4?:%373?>>3g;?:7?>;:k41?6=,8><6574n065>44<3`=?6=4+1559<<=i9=<1=>54i6194?"6<>0356`>47820>=n?;0;6)?;7;::?k73>3;>76g61;29 4202130b<:9:048?l?7290/=995889m510=9>10e5h50;&202<?12d:8;4>8:9j<`<72-;?;766;o372?7>32c3h7>5$064>=?<f8>=6<o4;h:`>5<#9==1445a15495g=<a1h1<7*>468;=>h6<?0:o65f8683>!73?3227c?;6;3g?>o0k3:1(<:8:9;8j42128o07d9>:18'511=001e=9851g98k`2=83.:8:4j3:l203<732en>7>5$064>`5<f8>=6<54od394?"6<>0n?6`>4781?>ib83:1(<:8:d18j4212:10e4l50;&202<>i2d:8;4?;:k:=?6=,8><64o4n065>4=<a021<7*>468:e>h6<?0976g67;29 42020k0b<:9:298k`?=83.:8:4j8:l203<732en;7>5$064>`><f8>=6<54od494?"6<>0n46`>4781?>ib=3:1(<:8:d:8j4212:10ci950;&202<c>2d:8;4?;:mg1?6=,8><6i84n065>4=<gm91<7*>468g2>h6<?0976ak2;29 4202m<0b<:9:298ka7=83.:8:4k6:l203<332eo<7>5$064>a0<f8>=6854obd94?"6<>0o:6`>4785?>idm3:1(<:8:e48j4212>10cnj50;&202<c>2d:8;47;:m`g?6=,8><6i84n065><=<gjh1<7*>468g2>h6<?0j76ala;29 4202m<0b<:9:c98kf>=83.:8:4k6:l203<d32eh;7>5$064>a0<f8>=6i54ob494?"6<>0o:6`>478f?>id=3:1(<:8:e48j4212o10cn:50;&202<c>2d:8;4>0:9lg6<72-;?;7j9;o372?7632eh>7>5$064>a0<f8>=6<<4;na2>5<#9==1h;5a154956=<gj:1<7*>468g2>h6<?0:865`bg83>!73?3n=7c?;6;36?>icm3:1(<:8:e48j42128<07bjk:18'511=l?1e=9851698kae=83.:8:4k6:l203<6021dho4?:%373?b13g;?:7?6;:mge?6=,8><6i84n065>4g<3fn26=4+1559`3=i9=<1=o54oe:94?"6<>0o:6`>4782g>=hl=0;6)?;7;f5?k73>3;o76al9;29 4202m<0b<:9:0g8?jdb290/=995d79m510=9o10e<8m:18'511=9?k0b<:9:198m40>290/=99517c8j4212810e<87:18'511=9?k0b<:9:398m400290/=99517c8j4212:10e;750;&202<102d:8;4?;:k53?6=,8><6;64n065>4=<a??1<7*>4685<>h6<?0976g94;29 4202?20b<:9:298m35=83.:8:498:l203<332c=>7>5$064>3><f8>=6854i7394?"6<>0=46`>4785?>o183:1(<:8:7:8j4212>10e8h50;&202<102d:8;47;:k6a?6=,8><6;64n065><=<a<n1<7*>4685<>h6<?0j76g:c;29 4202?20b<:9:c98m0g=83.:8:498:l203<d32c>57>5$064>3><f8>=6i54i4:94?"6<>0=46`>478f?>o2?3:1(<:8:7:8j4212o10e8850;&202<102d:8;4>0:9j10<72-;?;787;o372?7632c>87>5$064>3><f8>=6<<4;h70>5<#9==1:55a154956=<a<81<7*>4685<>h6<?0:865f5083>!73?3<37c?;6;36?>o083:1(<:8:7:8j42128<07d8i:18'511=>11e=9851698m3c=83.:8:498:l203<6021b:i4?:%373?0?3g;?:7?6;:k5g?6=,8><6;64n065>4g<3`<i6=4+15592==i9=<1=o54i7c94?"6<>0=46`>4782g>=n>?0;6)?;7;4;?k73>3;o76g:b;29 4202?20b<:9:0g8?l37290/=995699m510=9o10qo?:d;29ff<729q/=8l515;8L4173A;=<6T<5;ax2?1=l3;:6h4>2;d9f?g=k3;;644rn5g96>h3n380boj50:lgb?6<,li1ih5+ee8fa>"a9390(k<53:&e7?5<,o>1?6*i5;18 c0=;2.m;7=4$g:97>"a1390(ko53:&ef?5<,oi1?6*id;18 cc=;2.mj7=4$023>6=#99;1?6*>0380?!77;390(<>;:29'553=;2.:<;4<;%333?5<,8:36>5+11;97>"68h087)??b;18 46d2:1/==j53:&24`<43-;;j7=4$033>6=#98;1?6*>1380?!76;390(<?;:29'543=;2.:=;4<;%323?5<,8;36>5+10;97>"69h087)?>b;18 47d2:1/=<j53:&25`<43-;:j7=4$003>6=#9;;1?6*>2380?!75;390(<<;:29'573=;2.:>;4<;%313?5<,8836>5+13;97>"6:h087)?=b;18 44d2:1/=?j53:&26`<43-;9j7=4$013>6=#9:;1?6*>3380?!74;390(<=;:29'563=;2.:?;4<;%303?5<,8936>5+12;96>"6;h097)?<b;377>"6<l0:9l5+15d973=#9<:1?;5+141971=#9<>1=884$074>7=#9<21>6*>6e822f=#9?o1=;m4i06b>5<<a:o1<75fec83>>o6<m0;66g;3;29?l73j3:17d?;c;29?lcf2900e4850;&202<>=2d:8;4?;:k:0?6=,8><64;4n065>4=<a091<7*>468:1>h6<?0976g62;29 42020?0b<:9:298m401290/=9951778j4212910e<8;:18'511=9??0b<:9:098m404290/=9951778j4212;10e<8=:18'511=9??0b<:9:298kg3=83.:8:4m4:l203<732ei?7>5$064>g2<f8>=6<54oc394?"6<>0i86`>4781?>ie83:1(<:8:c68j4212:10clh50;&202<e<2d:8;4;;:mba?6=,8><6o:4n065>0=<ghn1<7*>468a0>h6<?0=76anc;29 4202k>0b<:9:698kdd=83.:8:4m4:l203<?32ejm7>5$064>g2<f8>=6454o`;94?"6<>0i86`>478b?>if03:1(<:8:c68j4212k10cl850;&202<e<2d:8;4l;:mb1?6=,8><6o:4n065>a=<gh>1<7*>468a0>h6<?0n76an3;29 4202k>0b<:9:g98kd4=83.:8:4m4:l203<6821dm<4?:%373?d33g;?:7?>;:mb4?6=,8><6o:4n065>44<3f3m6=4+1559f1=i9=<1=>54o8g94?"6<>0i86`>47820>=h1m0;6)?;7;`7?k73>3;>76amc;29 4202k>0b<:9:048?jde290/=995b59m510=9>10coo50;&202<e<2d:8;4>8:9lf<<72-;?;7l;;o372?7>32ei47>5$064>g2<f8>=6<o4;n`4>5<#9==1n95a15495g=<gk<1<7*>468a0>h6<?0:o65`b383>!73?3h?7c?;6;3g?>if?3:1(<:8:c68j42128o07b7l:18'511=j=1e=9851g98m4d=83.:8:4>a:l203<732c:57>5$064>4g<f8>=6<54i0:94?"6<>0:m6`>4781?>o6?3:1(<:8:0c8j4212:10e?:50;&202<6i2d:8;4;;:k17?6=,8><6<o4n065>0=<a;81<7*>4682e>h6<?0=76g=1;29 42028k0b<:9:698m76=83.:8:4>a:l203<?32c:j7>5$064>4g<f8>=6454i0g94?"6<>0:m6`>478b?>o6l3:1(<:8:0c8j4212k10e<m50;&202<6i2d:8;4l;:k22?6=,8><6<o4n065>a=<a;k1<7*>4681=>h6<?0;76g=8;29 4202;30b<:9:098m71=83.:8:4=9:l203<532c9:7>5$064>7?<f8>=6>54i2194?"6<>0956`>4787?>o4:3:1(<:8:3;8j4212<10e>?50;&202<512d:8;49;:k04?6=,8><6?74n065>2=<a;l1<7*>4681=>h6<?0376g=e;29 4202;30b<:9:898m7b=83.:8:4=9:l203<f32c9o7>5$064>7?<f8>=6o54i3`94?"6<>0956`>478`?>o5=3:1(<:8:3;8j4212m10e5o50;&202<?12d:8;4?;:k;<?6=,8><6574n065>4=<a1<1<7*>468;=>h6<?0976g75;29 4202130b<:9:298m=2=83.:8:479:l203<332c3?7>5$064>=?<f8>=6854i9094?"6<>0356`>4785?>o?93:1(<:8:9;8j4212>10e5>50;&202<?12d:8;47;:k4b?6=,8><6574n065><=<a>o1<7*>468;=>h6<?0j76g8d;29 4202130b<:9:c98m2d=83.:8:479:l203<d32c<m7>5$064>=?<f8>=6i54i6;94?"6<>0356`>478f?>o003:1(<:8:9;8j4212o10e:950;&202<?12d:8;4>0:9j33<72-;?;766;o372?7632c<97>5$064>=?<f8>=6<<4;h57>5<#9==1445a154956=<a>91<7*>468;=>h6<?0:865f7383>!73?3227c?;6;36?>o>93:1(<:8:9;8j42128<07d7?:18'511=001e=9851698m=`=83.:8:479:l203<6021b4h4?:%373?>>3g;?:7?6;:k;`?6=,8><6574n065>4g<3`2h6=4+1559<<=i9=<1=o54i9`94?"6<>0356`>4782g>=n0>0;6)?;7;::?k73>3;o76g8c;29 4202130b<:9:0g8?l16290/=995889m510=9o10ch:50;&202<b;2d:8;4?;:mf6?6=,8><6h=4n065>4=<gl;1<7*>468f7>h6<?0976aj0;29 4202l90b<:9:298m<d=83.:8:46a:l203<732c257>5$064><g<f8>=6<54i8:94?"6<>02m6`>4781?>o>?3:1(<:8:8c8j4212:10ch750;&202<b02d:8;4?;:mf3?6=,8><6h64n065>4=<gl<1<7*>468f<>h6<?0976aj5;29 4202l20b<:9:298ka1=83.:8:4k6:l203<732eo97>5$064>a0<f8>=6<54oe194?"6<>0o:6`>4781?>ic:3:1(<:8:e48j4212:10ci?50;&202<c>2d:8;4;;:mg4?6=,8><6i84n065>0=<gjl1<7*>468g2>h6<?0=76ale;29 4202m<0b<:9:698kfb=83.:8:4k6:l203<?32eho7>5$064>a0<f8>=6454ob`94?"6<>0o:6`>478b?>idi3:1(<:8:e48j4212k10cn650;&202<c>2d:8;4l;:m`3?6=,8><6i84n065>a=<gj<1<7*>468g2>h6<?0n76al5;29 4202m<0b<:9:g98kf2=83.:8:4k6:l203<6821do>4?:%373?b13g;?:7?>;:m`6?6=,8><6i84n065>44<3fi:6=4+1559`3=i9=<1=>54ob294?"6<>0o:6`>47820>=hjo0;6)?;7;f5?k73>3;>76ake;29 4202m<0b<:9:048?jbc290/=995d79m510=9>10cim50;&202<c>2d:8;4>8:9l`g<72-;?;7j9;o372?7>32eom7>5$064>a0<f8>=6<o4;nf:>5<#9==1h;5a15495g=<gm21<7*>468g2>h6<?0:o65`d583>!73?3n=7c?;6;3g?>id13:1(<:8:e48j42128o07blj:18'511=l?1e=9851g98m40e290/=99517c8j4212910e<86:18'511=9?k0b<:9:098m40?290/=99517c8j4212;10e<88:18'511=9?k0b<:9:298m3?=83.:8:498:l203<732c=;7>5$064>3><f8>=6<54i7794?"6<>0=46`>4781?>o1<3:1(<:8:7:8j4212:10e;=50;&202<102d:8;4;;:k56?6=,8><6;64n065>0=<a?;1<7*>4685<>h6<?0=76g90;29 4202?20b<:9:698m0`=83.:8:498:l203<?32c>i7>5$064>3><f8>=6454i4f94?"6<>0=46`>478b?>o2k3:1(<:8:7:8j4212k10e8o50;&202<102d:8;4l;:k6=?6=,8><6;64n065>a=<a<21<7*>4685<>h6<?0n76g:7;29 4202?20b<:9:g98m00=83.:8:498:l203<6821b984?:%373?0?3g;?:7?>;:k60?6=,8><6;64n065>44<3`?86=4+15592==i9=<1=>54i4094?"6<>0=46`>47820>=n=80;6)?;7;4;?k73>3;>76g80;29 4202?20b<:9:048?l0a290/=995699m510=9>10e;k50;&202<102d:8;4>8:9j2a<72-;?;787;o372?7>32c=o7>5$064>3><f8>=6<o4;h4a>5<#9==1:55a15495g=<a?k1<7*>4685<>h6<?0:o65f6783>!73?3<37c?;6;3g?>o2j3:1(<:8:7:8j42128o07d;?:18'511=>11e=9851g98yg72m3:1nn4?:1y'50d=9=30D<9?;I354>\4=3ip:795d;32>`<6:3l1n7o5c;33><<zf=o1>6`;f;08jgb=82doj7>4$da9a`=#mm0ni6*i1;18 c4=;2.m?7=4$g697>"a=390(k853:&e3?5<,o21?6*i9;18 cg=;2.mn7=4$ga97>"al390(kk53:&eb?5<,8:;6>5+11397>"68;087)??3;18 4632:1/==;53:&243<43-;;;7=4$02;>6=#9931?6*>0`80?!77j390(<>l:29'55b=;2.:<h4<;%33b?5<,8;;6>5+10397>"69;087)?>3;18 4732:1/=<;53:&253<43-;:;7=4$03;>6=#9831?6*>1`80?!76j390(<?l:29'54b=;2.:=h4<;%32b?5<,88;6>5+13397>"6:;087)?=3;18 4432:1/=?;53:&263<43-;9;7=4$00;>6=#9;31?6*>2`80?!75j390(<<l:29'57b=;2.:>h4<;%31b?5<,89;6>5+12397>"6;;087)?<3;18 4532:1/=>;53:&273<43-;8;7=4$01;>6=#9:31>6*>3`81?!74j3;??6*>4d821d=#9=l1?;5+142973=#9<91?95+1469500<,8?<6?5+14:96>"6>m0::n5+17g953e<a8>j6=44i2g94?=nmk0;66g>4e83>>o3;3:17d?;b;29?l73k3:17dkn:188m<0=83.:8:465:l203<732c287>5$064><3<f8>=6<54i8194?"6<>0296`>4781?>o>:3:1(<:8:878j4212:10e<89:18'511=9??0b<:9:198m403290/=9951778j4212810e<8<:18'511=9??0b<:9:398m405290/=9951778j4212:10co;50;&202<e<2d:8;4?;:ma7?6=,8><6o:4n065>4=<gk;1<7*>468a0>h6<?0976am0;29 4202k>0b<:9:298kd`=83.:8:4m4:l203<332eji7>5$064>g2<f8>=6854o`f94?"6<>0i86`>4785?>ifk3:1(<:8:c68j4212>10cll50;&202<e<2d:8;47;:mbe?6=,8><6o:4n065><=<gh31<7*>468a0>h6<?0j76an8;29 4202k>0b<:9:c98kd0=83.:8:4m4:l203<d32ej97>5$064>g2<f8>=6i54o`694?"6<>0i86`>478f?>if;3:1(<:8:c68j4212o10cl<50;&202<e<2d:8;4>0:9le4<72-;?;7l;;o372?7632ej<7>5$064>g2<f8>=6<<4;n;e>5<#9==1n95a154956=<g0o1<7*>468a0>h6<?0:865`9e83>!73?3h?7c?;6;36?>iek3:1(<:8:c68j42128<07blm:18'511=j=1e=9851698kgg=83.:8:4m4:l203<6021dn44?:%373?d33g;?:7?6;:ma<?6=,8><6o:4n065>4g<3fh<6=4+1559f1=i9=<1=o54oc494?"6<>0i86`>4782g>=hj;0;6)?;7;`7?k73>3;o76an7;29 4202k>0b<:9:0g8?j?d290/=995b59m510=9o10e<l50;&202<6i2d:8;4?;:k2=?6=,8><6<o4n065>4=<a821<7*>4682e>h6<?0976g>7;29 42028k0b<:9:298m72=83.:8:4>a:l203<332c9?7>5$064>4g<f8>=6854i3094?"6<>0:m6`>4785?>o593:1(<:8:0c8j4212>10e?>50;&202<6i2d:8;47;:k2b?6=,8><6<o4n065><=<a8o1<7*>4682e>h6<?0j76g>d;29 42028k0b<:9:c98m4e=83.:8:4>a:l203<d32c::7>5$064>4g<f8>=6i54i3c94?"6<>0956`>4783?>o503:1(<:8:3;8j4212810e?950;&202<512d:8;4=;:k12?6=,8><6?74n065>6=<a:91<7*>4681=>h6<?0?76g<2;29 4202;30b<:9:498m67=83.:8:4=9:l203<132c8<7>5$064>7?<f8>=6:54i3d94?"6<>0956`>478;?>o5m3:1(<:8:3;8j4212010e?j50;&202<512d:8;4n;:k1g?6=,8><6?74n065>g=<a;h1<7*>4681=>h6<?0h76g=5;29 4202;30b<:9:e98m=g=83.:8:479:l203<732c347>5$064>=?<f8>=6<54i9494?"6<>0356`>4781?>o?=3:1(<:8:9;8j4212:10e5:50;&202<?12d:8;4;;:k;7?6=,8><6574n065>0=<a181<7*>468;=>h6<?0=76g71;29 4202130b<:9:698m=6=83.:8:479:l203<?32c<j7>5$064>=?<f8>=6454i6g94?"6<>0356`>478b?>o0l3:1(<:8:9;8j4212k10e:l50;&202<?12d:8;4l;:k4e?6=,8><6574n065>a=<a>31<7*>468;=>h6<?0n76g88;29 4202130b<:9:g98m21=83.:8:479:l203<6821b;;4?:%373?>>3g;?:7?>;:k41?6=,8><6574n065>44<3`=?6=4+1559<<=i9=<1=>54i6194?"6<>0356`>47820>=n?;0;6)?;7;::?k73>3;>76g61;29 4202130b<:9:048?l?7290/=995889m510=9>10e5h50;&202<?12d:8;4>8:9j<`<72-;?;766;o372?7>32c3h7>5$064>=?<f8>=6<o4;h:`>5<#9==1445a15495g=<a1h1<7*>468;=>h6<?0:o65f8683>!73?3227c?;6;3g?>o0k3:1(<:8:9;8j42128o07d9>:18'511=001e=9851g98k`2=83.:8:4j3:l203<732en>7>5$064>`5<f8>=6<54od394?"6<>0n?6`>4781?>ib83:1(<:8:d18j4212:10e4l50;&202<>i2d:8;4?;:k:=?6=,8><64o4n065>4=<a021<7*>468:e>h6<?0976g67;29 42020k0b<:9:298k`?=83.:8:4j8:l203<732en;7>5$064>`><f8>=6<54od494?"6<>0n46`>4781?>ib=3:1(<:8:d:8j4212:10ci950;&202<c>2d:8;4?;:mg1?6=,8><6i84n065>4=<gm91<7*>468g2>h6<?0976ak2;29 4202m<0b<:9:298ka7=83.:8:4k6:l203<332eo<7>5$064>a0<f8>=6854obd94?"6<>0o:6`>4785?>idm3:1(<:8:e48j4212>10cnj50;&202<c>2d:8;47;:m`g?6=,8><6i84n065><=<gjh1<7*>468g2>h6<?0j76ala;29 4202m<0b<:9:c98kf>=83.:8:4k6:l203<d32eh;7>5$064>a0<f8>=6i54ob494?"6<>0o:6`>478f?>id=3:1(<:8:e48j4212o10cn:50;&202<c>2d:8;4>0:9lg6<72-;?;7j9;o372?7632eh>7>5$064>a0<f8>=6<<4;na2>5<#9==1h;5a154956=<gj:1<7*>468g2>h6<?0:865`bg83>!73?3n=7c?;6;36?>icm3:1(<:8:e48j42128<07bjk:18'511=l?1e=9851698kae=83.:8:4k6:l203<6021dho4?:%373?b13g;?:7?6;:mge?6=,8><6i84n065>4g<3fn26=4+1559`3=i9=<1=o54oe:94?"6<>0o:6`>4782g>=hl=0;6)?;7;f5?k73>3;o76al9;29 4202m<0b<:9:0g8?jdb290/=995d79m510=9o10e<8m:18'511=9?k0b<:9:198m40>290/=99517c8j4212810e<87:18'511=9?k0b<:9:398m400290/=99517c8j4212:10e;750;&202<102d:8;4?;:k53?6=,8><6;64n065>4=<a??1<7*>4685<>h6<?0976g94;29 4202?20b<:9:298m35=83.:8:498:l203<332c=>7>5$064>3><f8>=6854i7394?"6<>0=46`>4785?>o183:1(<:8:7:8j4212>10e8h50;&202<102d:8;47;:k6a?6=,8><6;64n065><=<a<n1<7*>4685<>h6<?0j76g:c;29 4202?20b<:9:c98m0g=83.:8:498:l203<d32c>57>5$064>3><f8>=6i54i4:94?"6<>0=46`>478f?>o2?3:1(<:8:7:8j4212o10e8850;&202<102d:8;4>0:9j10<72-;?;787;o372?7632c>87>5$064>3><f8>=6<<4;h70>5<#9==1:55a154956=<a<81<7*>4685<>h6<?0:865f5083>!73?3<37c?;6;36?>o083:1(<:8:7:8j42128<07d8i:18'511=>11e=9851698m3c=83.:8:498:l203<6021b:i4?:%373?0?3g;?:7?6;:k5g?6=,8><6;64n065>4g<3`<i6=4+15592==i9=<1=o54i7c94?"6<>0=46`>4782g>=n>?0;6)?;7;4;?k73>3;o76g:b;29 4202?20b<:9:0g8?l37290/=995699m510=9o10qo?:f;29ff<729q/=8l515;8L4173A;=<6T<5;ax2?1=l3;:6h4>2;d9f?g=k3;;644rn5g96>h3n380boj50:lgb?6<,li1ih5+ee8fa>"a9390(k<53:&e7?5<,o>1?6*i5;18 c0=;2.m;7=4$g:97>"a1390(ko53:&ef?5<,oi1?6*id;18 cc=;2.mj7=4$023>6=#99;1?6*>0380?!77;390(<>;:29'553=;2.:<;4<;%333?5<,8:36>5+11;97>"68h087)??b;18 46d2:1/==j53:&24`<43-;;j7=4$033>6=#98;1?6*>1380?!76;390(<?;:29'543=;2.:=;4<;%323?5<,8;36>5+10;97>"69h087)?>b;18 47d2:1/=<j53:&25`<43-;:j7=4$003>6=#9;;1?6*>2380?!75;390(<<;:29'573=;2.:>;4<;%313?5<,8836>5+13;97>"6:h087)?=b;18 44d2:1/=?j53:&26`<43-;9j7=4$013>6=#9:;1?6*>3380?!74;390(<=;:29'563=;2.:?;4<;%303?5<,8936>5+12;96>"6;h097)?<b;377>"6<l0:9l5+15d973=#9<:1?;5+141971=#9<>1=884$074>7=#9<21>6*>6e822f=#9?o1=;m4i06b>5<<a:o1<75fec83>>o6<m0;66g;3;29?l73j3:17d?;c;29?lcf2900e4850;&202<>=2d:8;4?;:k:0?6=,8><64;4n065>4=<a091<7*>468:1>h6<?0976g62;29 42020?0b<:9:298m401290/=9951778j4212910e<8;:18'511=9??0b<:9:098m404290/=9951778j4212;10e<8=:18'511=9??0b<:9:298kg3=83.:8:4m4:l203<732ei?7>5$064>g2<f8>=6<54oc394?"6<>0i86`>4781?>ie83:1(<:8:c68j4212:10clh50;&202<e<2d:8;4;;:mba?6=,8><6o:4n065>0=<ghn1<7*>468a0>h6<?0=76anc;29 4202k>0b<:9:698kdd=83.:8:4m4:l203<?32ejm7>5$064>g2<f8>=6454o`;94?"6<>0i86`>478b?>if03:1(<:8:c68j4212k10cl850;&202<e<2d:8;4l;:mb1?6=,8><6o:4n065>a=<gh>1<7*>468a0>h6<?0n76an3;29 4202k>0b<:9:g98kd4=83.:8:4m4:l203<6821dm<4?:%373?d33g;?:7?>;:mb4?6=,8><6o:4n065>44<3f3m6=4+1559f1=i9=<1=>54o8g94?"6<>0i86`>47820>=h1m0;6)?;7;`7?k73>3;>76amc;29 4202k>0b<:9:048?jde290/=995b59m510=9>10coo50;&202<e<2d:8;4>8:9lf<<72-;?;7l;;o372?7>32ei47>5$064>g2<f8>=6<o4;n`4>5<#9==1n95a15495g=<gk<1<7*>468a0>h6<?0:o65`b383>!73?3h?7c?;6;3g?>if?3:1(<:8:c68j42128o07b7l:18'511=j=1e=9851g98m4d=83.:8:4>a:l203<732c:57>5$064>4g<f8>=6<54i0:94?"6<>0:m6`>4781?>o6?3:1(<:8:0c8j4212:10e?:50;&202<6i2d:8;4;;:k17?6=,8><6<o4n065>0=<a;81<7*>4682e>h6<?0=76g=1;29 42028k0b<:9:698m76=83.:8:4>a:l203<?32c:j7>5$064>4g<f8>=6454i0g94?"6<>0:m6`>478b?>o6l3:1(<:8:0c8j4212k10e<m50;&202<6i2d:8;4l;:k22?6=,8><6<o4n065>a=<a;k1<7*>4681=>h6<?0;76g=8;29 4202;30b<:9:098m71=83.:8:4=9:l203<532c9:7>5$064>7?<f8>=6>54i2194?"6<>0956`>4787?>o4:3:1(<:8:3;8j4212<10e>?50;&202<512d:8;49;:k04?6=,8><6?74n065>2=<a;l1<7*>4681=>h6<?0376g=e;29 4202;30b<:9:898m7b=83.:8:4=9:l203<f32c9o7>5$064>7?<f8>=6o54i3`94?"6<>0956`>478`?>o5=3:1(<:8:3;8j4212m10e5o50;&202<?12d:8;4?;:k;<?6=,8><6574n065>4=<a1<1<7*>468;=>h6<?0976g75;29 4202130b<:9:298m=2=83.:8:479:l203<332c3?7>5$064>=?<f8>=6854i9094?"6<>0356`>4785?>o?93:1(<:8:9;8j4212>10e5>50;&202<?12d:8;47;:k4b?6=,8><6574n065><=<a>o1<7*>468;=>h6<?0j76g8d;29 4202130b<:9:c98m2d=83.:8:479:l203<d32c<m7>5$064>=?<f8>=6i54i6;94?"6<>0356`>478f?>o003:1(<:8:9;8j4212o10e:950;&202<?12d:8;4>0:9j33<72-;?;766;o372?7632c<97>5$064>=?<f8>=6<<4;h57>5<#9==1445a154956=<a>91<7*>468;=>h6<?0:865f7383>!73?3227c?;6;36?>o>93:1(<:8:9;8j42128<07d7?:18'511=001e=9851698m=`=83.:8:479:l203<6021b4h4?:%373?>>3g;?:7?6;:k;`?6=,8><6574n065>4g<3`2h6=4+1559<<=i9=<1=o54i9`94?"6<>0356`>4782g>=n0>0;6)?;7;::?k73>3;o76g8c;29 4202130b<:9:0g8?l16290/=995889m510=9o10ch:50;&202<b;2d:8;4?;:mf6?6=,8><6h=4n065>4=<gl;1<7*>468f7>h6<?0976aj0;29 4202l90b<:9:298m<d=83.:8:46a:l203<732c257>5$064><g<f8>=6<54i8:94?"6<>02m6`>4781?>o>?3:1(<:8:8c8j4212:10ch750;&202<b02d:8;4?;:mf3?6=,8><6h64n065>4=<gl<1<7*>468f<>h6<?0976aj5;29 4202l20b<:9:298ka1=83.:8:4k6:l203<732eo97>5$064>a0<f8>=6<54oe194?"6<>0o:6`>4781?>ic:3:1(<:8:e48j4212:10ci?50;&202<c>2d:8;4;;:mg4?6=,8><6i84n065>0=<gjl1<7*>468g2>h6<?0=76ale;29 4202m<0b<:9:698kfb=83.:8:4k6:l203<?32eho7>5$064>a0<f8>=6454ob`94?"6<>0o:6`>478b?>idi3:1(<:8:e48j4212k10cn650;&202<c>2d:8;4l;:m`3?6=,8><6i84n065>a=<gj<1<7*>468g2>h6<?0n76al5;29 4202m<0b<:9:g98kf2=83.:8:4k6:l203<6821do>4?:%373?b13g;?:7?>;:m`6?6=,8><6i84n065>44<3fi:6=4+1559`3=i9=<1=>54ob294?"6<>0o:6`>47820>=hjo0;6)?;7;f5?k73>3;>76ake;29 4202m<0b<:9:048?jbc290/=995d79m510=9>10cim50;&202<c>2d:8;4>8:9l`g<72-;?;7j9;o372?7>32eom7>5$064>a0<f8>=6<o4;nf:>5<#9==1h;5a15495g=<gm21<7*>468g2>h6<?0:o65`d583>!73?3n=7c?;6;3g?>id13:1(<:8:e48j42128o07blj:18'511=l?1e=9851g98m40e290/=99517c8j4212910e<86:18'511=9?k0b<:9:098m40?290/=99517c8j4212;10e<88:18'511=9?k0b<:9:298m3?=83.:8:498:l203<732c=;7>5$064>3><f8>=6<54i7794?"6<>0=46`>4781?>o1<3:1(<:8:7:8j4212:10e;=50;&202<102d:8;4;;:k56?6=,8><6;64n065>0=<a?;1<7*>4685<>h6<?0=76g90;29 4202?20b<:9:698m0`=83.:8:498:l203<?32c>i7>5$064>3><f8>=6454i4f94?"6<>0=46`>478b?>o2k3:1(<:8:7:8j4212k10e8o50;&202<102d:8;4l;:k6=?6=,8><6;64n065>a=<a<21<7*>4685<>h6<?0n76g:7;29 4202?20b<:9:g98m00=83.:8:498:l203<6821b984?:%373?0?3g;?:7?>;:k60?6=,8><6;64n065>44<3`?86=4+15592==i9=<1=>54i4094?"6<>0=46`>47820>=n=80;6)?;7;4;?k73>3;>76g80;29 4202?20b<:9:048?l0a290/=995699m510=9>10e;k50;&202<102d:8;4>8:9j2a<72-;?;787;o372?7>32c=o7>5$064>3><f8>=6<o4;h4a>5<#9==1:55a15495g=<a?k1<7*>4685<>h6<?0:o65f6783>!73?3<37c?;6;3g?>o2j3:1(<:8:7:8j42128o07d;?:18'511=>11e=9851g98yv7393:1=9?t=052>``<58?h6<84=07`>73<58?h6;74=07`>31<58?h6;;4=07`>32<58?h6;=4=07`>34<58?h6;?4=07`>36<58?h68h4=07`>0c<58?h68j4=07`>0e<58?h68o4=07`>0?<58?h6864=07`>01<58?h6884=07`>03<58?h68:4=07`>05<58?h68<4=07`>07<58?h6:>4=07`>3`<58?h6;k4=07`>3b<58?h6;m4=07`>3d<58?h6;o4=07`>30<58?h65o4=07`>=><58?h6584=07`>=3<58?h65:4=07`>=5<58?h65<4=07`>=7<58?h65>4=07`>2`<58?h6:k4=07`>2b<58?h6:l4=07`>2g<58?h6:74=07`>2><58?h6:94=07`>20<58?h6:;4=07`>22<58?h6:=4=07`>24<58?h64?4=07`><6<58?h65h4=07`>=c<58?h65j4=07`>=e<58?h65l4=07`>=1<58?h6:m4=07`>27<58?h6484=07`><2<58?h64=4=07`><4<58?h64l4=07`><?<58?h6464=07`><1<58?h6<8m;<36g?71127:9n4>699>50e=9?=01<;l:06b?872k3;?n63>5b820f=:9<i1=9j4=07g>40<58?o6?;4=07g>3?<58?o6;94=07g>33<58?o6;:4=07g>35<58?o6;<4=07g>37<58?o6;>4=07g>0`<58?o68k4=07g>0b<58?o68m4=07g>0g<58?o6874=07g>0><58?o6894=07g>00<58?o68;4=07g>02<58?o68=4=07g>04<58?o68?4=07g>26<58?o6;h4=07g>3c<58?o6;j4=07g>3e<58?o6;l4=07g>3g<58?o6;84=07g>=g<58?o6564=07g>=0<58?o65;4=07g>=2<58?o65=4=07g>=4<58?o65?4=07g>=6<58?o6:h4=07g>2c<58?o6:j4=07g>2d<58?o6:o4=07g>2?<58?o6:64=07g>21<58?o6:84=07g>23<58?o6::4=07g>25<58?o6:<4=07g><7<58?o64>4=07g>=`<58?o65k4=07g>=b<58?o65m4=07g>=d<58?o6594=07g>2e<58?o6:?4=07g><0<58?o64:4=07g><5<58?o64<4=07g><d<58?o6474=07g><><58?o6494=07g>40e34;>h7?99:?21a<6>116=8j51758943c28>j70?:d;37f>;6=m0:8n5214f951b<58?n6<84=07f>73<58?n6;74=07f>31<58?n6;;4=07f>32<58?n6;=4=07f>34<58?n6;?4=07f>36<58?n68h4=07f>0c<58?n68j4=07f>0e<58?n68o4=07f>0?<58?n6864=07f>01<58?n6884=07f>03<58?n68:4=07f>05<58?n68<4=07f>07<58?n6:>4=07f>3`<58?n6;k4=07f>3b<58?n6;m4=07f>3d<58?n6;o4=07f>30<58?n65o4=07f>=><58?n6584=07f>=3<58?n65:4=07f>=5<58?n65<4=07f>=7<58?n65>4=07f>2`<58?n6:k4=07f>2b<58?n6:l4=07f>2g<58?n6:74=07f>2><58?n6:94=07f>20<58?n6:;4=07f>22<58?n6:=4=07f>24<58?n64?4=07f><6<58?n65h4=07f>=c<58?n65j4=07f>=e<58?n65l4=07f>=1<58?n6:m4=07f>27<58?n6484=07f><2<58?n64=4=07f><4<58?n64l4=07f><?<58?n6464=07f><1<58?n6<8m;<36a?71127:9h4>699>50c=9?=01<;j:06b?872m3;?n63>5d820f=:9<o1=9j4=07e>40<58?m6?;4=07e>3?<58?m6;94=07e>33<58?m6;:4=07e>35<58?m6;<4=07e>37<58?m6;>4=07e>0`<58?m68k4=07e>0b<58?m68m4=07e>0g<58?m6874=07e>0><58?m6894=07e>00<58?m68;4=07e>02<58?m68=4=07e>04<58?m68?4=07e>26<58?m6;h4=07e>3c<58?m6;j4=07e>3e<58?m6;l4=07e>3g<58?m6;84=07e>=g<58?m6564=07e>=0<58?m65;4=07e>=2<58?m65=4=07e>=4<58?m65?4=07e>=6<58?m6:h4=07e>2c<58?m6:j4=07e>2d<58?m6:o4=07e>2?<58?m6:64=07e>21<58?m6:84=07e>23<58?m6::4=07e>25<58?m6:<4=07e><7<58?m64>4=07e>=`<58?m65k4=07e>=b<58?m65m4=07e>=d<58?m6594=07e>2e<58?m6:?4=07e><0<58?m64:4=07e><5<58?m64<4=07e><d<58?m6474=07e><><58?m6494=07e>40e34;>j7?99:?21c<6>116=8h51758943a28>j70?:f;37f>;6=o0:8n5214d951b<uz;jj7>52z\2ec=:9<i1nh5rs0`3>5<5sW;i<63>5b8`=>{t9k;1<7<t^0`2?872l3hn7p}>b383>7}Y9k801<;k:b;8yv7e;3:1>vP>b29>50c=jl1v<l;:181[7e<27:9h4l9:p5g3=838pR<l:;<36b?db3ty:n:4?:3y]5g1<58?m6n74}r3a=?6==rT:n45214a9ag=:9<n1io5214g9ag=:9<l1io5rs0c6>5<2sW;j963>5b877>;6=m0??63>5d877>;6=o0??6s|1c:94?3|V8h370?:c;gb?872l3oj70?:e;gb?872n3oj7p}>a583>0}Y9h>01<;l:2g8943c2:o01<;j:2g8943a2:o0q~?77;291~X60>16=8m52c9>50b=:k16=8k52c9>50`=:k1v<6l:186[7?k27:9n4=c:?21a<5k27:9h4=c:?21c<5k2wx=5j50;7xZ4>c34;>o7<k;<36`?4c34;>i7<k;<36b?4c3ty:4h4?:4y]5=c<58?h6?k4=07g>7c<58?n6?k4=07e>7c<uz;3j7>55z\2<c=:9<i1>k5214f96c=:9<o1>k5214d96c=z{83;6=4:{_3:4>;6=j08<63>5e804>;6=l08<63>5g804>{t90;1<7;t^0;2?872k39:70?:d;12?872m39:70?:f;12?xu61;0;68uQ1808943d2:801<;k:208943b2:801<;i:208yv7>;3:19vP>929>50e=;:16=8j5329>50c=;:16=8h5329~w4?3290>wS?64:?21f<5>27:9i4=6:?21`<5>27:9k4=6:p5=>=83?pR<67;<36g?4034;>h7<8;<36a?4034;>j7<8;|q2<<<72<qU=574=07`>7><58?o6?64=07f>7><58?m6?64}r3;f?6==rT:4o5214a96d=:9<n1>l5214g96d=:9<l1>l5rs0c5>5<5sW;j:63>5b864>{t9h=1<7<t^0c4?872k3?i7p}>a983>7}Y9h201<;k:428yv7f13:1>vP>a89>50b==k1v<on:181[7fi27:9h4:0:p5dd=838pR<om;<36a?3e3ty:mn4?:3y]5de<58?m68>4}r3ba?6=:rT:mh5214d91g=z{8=26=4:{_34=>;6=j0:o63>5e82g>;6=l0:o63>5g82g>{t9>o1<7;t^05f?872k3;o70?:d;3g?872m3;o70?:f;3g?xu6?o0;68uQ16d8943d28o01<;k:0g8943b28o01<;i:0g8yv7?83:19vP>819>50e=9o16=8j51g9>50c=9o16=8h51g9~w4>6290>wS?71:?21f<5827:9i4=0:?21`<5827:9k4=0:p5=4=83?pR<6=;<36g?4634;>h7<>;<36a?4634;>j7<>;|q2<6<72<qU=5=4=07`>74<58?o6?<4=07f>74<58?m6?<4}r3;0?6==rT:495214a966=:9<n1>>5214g966=:9<l1>>5rs0:6>5<2sW;3963>5b810>;6=m09863>5d810>;6=o0986s|19494?3|V82=70?:c;34?872l3;<70?:e;34?872n3;<7p}>7`83>0}Y9>k01<;l:0:8943c28201<;j:0:8943a2820q~?8b;291~X6?k16=8m5189>50b=9016=8k5189>50`=901v<9k:186[70l27:9n4>b:?21a<6j27:9h4>b:?21c<6j2wx=oh50;32[7en27:9n4>679>50e=9?>01<;l:040?872k3;=>63>5e8223=:9<n1=;:4=07g>40434;>h7?92:?21`<6>?16=8k51768943b28<870?:e;356>;6=o0::;5214d9532<58?m6<8<;<36b?71:2wvb>=?:182M7182we?>?50;3xL4073td8??4?:0yK536<ug98?7>51zJ225=zf:9?6=4>{I354>{i;:?1<7?tH043?xh4;?0;6<uG1728yk54?3:1=vF>619~j65?290:wE?90:m76?=83;pD<8?;|l07d<728qC=;>4}o10f?6=9rB::=5rn21`>5<6sA;=<6sa32f94?7|@8<;7p`<3d83>4}O9?:0qc=<f;295~N6>91vb>:?:182M7182we?9?50;3xL4073td88?4?:0yK536<ug9??7>51zJ225=zf:>?6=4>{I354>{i;=?1<7?tH043?xh4<?0;6<uG1728yk53?3:1=vF>619~j62?290:wE?90:m71?=83;pD<8?;|l00d<728qC=;>4}o17f?6=9rB::=5rn26`>5<6sA;=<6sa35f94?7|@8<;7p`<4d83>4}O9?:0qc=;f;295~N6>91vb>;?:182M7182we?8?50;3xL4073td89?4?:0yK536<ug9>?7>51zJ225=zf:??6=4>{I354>{i;<?1<7?tH043?xh4=?0;6<uG1728yk52?3:1=vF>619~j63?290:wE?90:m70?=83;pD<8?;|l01d<728qC=;>4}o16f?6=9rB::=5rn27`>5<6sA;=<6sa34f94?7|@8<;7p`<5d83>4}O9?:0qc=:f;295~N6>91vqpsO@By0=5<c;8>=9h<r@A@x4xFGXrwKL
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.sym
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.sym	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.sym	(revision 115)
@@ -0,0 +1,36 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="mem8k8">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2014-3-3T16:27:16</timestamp>
+    <pin polarity="Input" x="0" y="80" name="addra[12:0]" />
+    <pin polarity="Input" x="0" y="112" name="dina[7:0]" />
+    <pin polarity="Input" x="0" y="144" name="ena" />
+    <pin polarity="Input" x="0" y="208" name="wea[0:0]" />
+    <pin polarity="Input" x="0" y="272" name="clka" />
+    <pin polarity="Input" x="0" y="432" name="addrb[12:0]" />
+    <pin polarity="Input" x="0" y="496" name="enb" />
+    <pin polarity="Input" x="0" y="624" name="clkb" />
+    <pin polarity="Output" x="576" y="368" name="doutb[7:0]" />
+    <graph>
+        <text style="fontsize:40;fontname:Arial" x="32" y="32">mem8k8</text>
+        <rect width="512" x="32" y="32" height="1344" />
+        <line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[12:0]" />
+        <line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin dina[7:0]" />
+        <line x2="32" y1="144" y2="144" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin ena" />
+        <line x2="32" y1="208" y2="208" style="linewidth:W" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin wea[0:0]" />
+        <line x2="32" y1="272" y2="272" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
+        <line x2="32" y1="432" y2="432" style="linewidth:W" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin addrb[12:0]" />
+        <line x2="32" y1="496" y2="496" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="496" type="pin enb" />
+        <line x2="32" y1="624" y2="624" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="624" type="pin clkb" />
+        <line x2="544" y1="368" y2="368" style="linewidth:W" x1="576" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin doutb[7:0]" />
+    </graph>
+</symbol>
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.vhd	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.vhd	(revision 115)
@@ -0,0 +1,152 @@
+--------------------------------------------------------------------------------
+--    This file is owned and controlled by Xilinx and must be used solely     --
+--    for design, simulation, implementation and creation of design files     --
+--    limited to Xilinx devices or technologies. Use with non-Xilinx          --
+--    devices or technologies is expressly prohibited and immediately         --
+--    terminates your license.                                                --
+--                                                                            --
+--    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
+--    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
+--    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
+--    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
+--    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
+--    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
+--    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
+--    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
+--    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
+--    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
+--    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
+--    PARTICULAR PURPOSE.                                                     --
+--                                                                            --
+--    Xilinx products are not intended for use in life support appliances,    --
+--    devices, or systems.  Use in such applications are expressly            --
+--    prohibited.                                                             --
+--                                                                            --
+--    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
+--    All rights reserved.                                                    --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file mem8k8.vhd when simulating
+-- the core, mem8k8. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY mem8k8 IS
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    enb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END mem8k8;
+
+ARCHITECTURE mem8k8_a OF mem8k8 IS
+-- synthesis translate_off
+COMPONENT wrapped_mem8k8
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    enb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END COMPONENT;
+
+-- Configuration specification
+  FOR ALL : wrapped_mem8k8 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
+    GENERIC MAP (
+      c_addra_width => 13,
+      c_addrb_width => 13,
+      c_algorithm => 1,
+      c_axi_id_width => 4,
+      c_axi_slave_type => 0,
+      c_axi_type => 1,
+      c_byte_size => 9,
+      c_common_clk => 0,
+      c_default_data => "0",
+      c_disable_warn_bhv_coll => 0,
+      c_disable_warn_bhv_range => 0,
+      c_family => "spartan6",
+      c_has_axi_id => 0,
+      c_has_ena => 1,
+      c_has_enb => 1,
+      c_has_injecterr => 0,
+      c_has_mem_output_regs_a => 0,
+      c_has_mem_output_regs_b => 0,
+      c_has_mux_output_regs_a => 0,
+      c_has_mux_output_regs_b => 0,
+      c_has_regcea => 0,
+      c_has_regceb => 0,
+      c_has_rsta => 0,
+      c_has_rstb => 0,
+      c_has_softecc_input_regs_a => 0,
+      c_has_softecc_output_regs_b => 0,
+      c_init_file_name => "no_coe_file_loaded",
+      c_inita_val => "0",
+      c_initb_val => "0",
+      c_interface_type => 0,
+      c_load_init_file => 0,
+      c_mem_type => 1,
+      c_mux_pipeline_stages => 0,
+      c_prim_type => 1,
+      c_read_depth_a => 8191,
+      c_read_depth_b => 8191,
+      c_read_width_a => 8,
+      c_read_width_b => 8,
+      c_rst_priority_a => "CE",
+      c_rst_priority_b => "CE",
+      c_rst_type => "SYNC",
+      c_rstram_a => 0,
+      c_rstram_b => 0,
+      c_sim_collision_check => "ALL",
+      c_use_byte_wea => 0,
+      c_use_byte_web => 0,
+      c_use_default_data => 0,
+      c_use_ecc => 0,
+      c_use_softecc => 0,
+      c_wea_width => 1,
+      c_web_width => 1,
+      c_write_depth_a => 8191,
+      c_write_depth_b => 8191,
+      c_write_mode_a => "WRITE_FIRST",
+      c_write_mode_b => "WRITE_FIRST",
+      c_write_width_a => 8,
+      c_write_width_b => 8,
+      c_xdevicefamily => "spartan6"
+    );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_mem8k8
+  PORT MAP (
+    clka => clka,
+    ena => ena,
+    wea => wea,
+    addra => addra,
+    dina => dina,
+    clkb => clkb,
+    enb => enb,
+    addrb => addrb,
+    doutb => doutb
+  );
+-- synthesis translate_on
+
+END mem8k8_a;
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.vho
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.vho	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.vho	(revision 115)
@@ -0,0 +1,89 @@
+--------------------------------------------------------------------------------
+--    This file is owned and controlled by Xilinx and must be used solely     --
+--    for design, simulation, implementation and creation of design files     --
+--    limited to Xilinx devices or technologies. Use with non-Xilinx          --
+--    devices or technologies is expressly prohibited and immediately         --
+--    terminates your license.                                                --
+--                                                                            --
+--    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
+--    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
+--    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
+--    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
+--    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
+--    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
+--    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
+--    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
+--    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
+--    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
+--    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
+--    PARTICULAR PURPOSE.                                                     --
+--                                                                            --
+--    Xilinx products are not intended for use in life support appliances,    --
+--    devices, or systems.  Use in such applications are expressly            --
+--    prohibited.                                                             --
+--                                                                            --
+--    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
+--    All rights reserved.                                                    --
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+--    Generated from core with identifier: xilinx.com:ip:blk_mem_gen:6.2      --
+--                                                                            --
+--    The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port    --
+--    Block Memory and Single Port Block Memory LogiCOREs, but is not a       --
+--    direct drop-in replacement.  It should be used in all new Xilinx        --
+--    designs. The core supports RAM and ROM functions over a wide range of   --
+--    widths and depths. Use this core to generate block memories with        --
+--    symmetric or asymmetric read and write port widths, as well as cores    --
+--    which can perform simultaneous write operations to separate             --
+--    locations, and simultaneous read operations from the same location.     --
+--    For more information on differences in interface and feature support    --
+--    between this core and the Dual Port Block Memory and Single Port        --
+--    Block Memory LogiCOREs, please consult the data sheet.                  --
+--------------------------------------------------------------------------------
+
+-- Interfaces:
+--    AXI_SLAVE_S_AXI
+--    AXILite_SLAVE_S_AXI
+
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT mem8k8
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    enb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : mem8k8
+  PORT MAP (
+    clka => clka,
+    ena => ena,
+    wea => wea,
+    addra => addra,
+    dina => dina,
+    clkb => clkb,
+    enb => enb,
+    addrb => addrb,
+    doutb => doutb
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file mem8k8.vhd when simulating
+-- the core, mem8k8. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.xco
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.xco	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.xco	(revision 115)
@@ -0,0 +1,105 @@
+##############################################################
+#
+# Xilinx Core Generator version 13.3
+# Date: Mon Mar 03 16:26:23 2014
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:blk_mem_gen:6.2
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2
+# END Select
+# BEGIN Parameters
+CSET additional_inputs_for_power_estimation=false
+CSET algorithm=Minimum_Area
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
+CSET byte_size=9
+CSET coe_file=no_coe_file_loaded
+CSET collision_warnings=ALL
+CSET component_name=mem8k8
+CSET disable_collision_warnings=false
+CSET disable_out_of_range_warnings=false
+CSET ecc=false
+CSET ecctype=No_ECC
+CSET enable_a=Use_ENA_Pin
+CSET enable_b=Use_ENB_Pin
+CSET error_injection_type=Single_Bit_Error_Injection
+CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
+CSET load_init_file=false
+CSET memory_type=Simple_Dual_Port_RAM
+CSET operating_mode_a=WRITE_FIRST
+CSET operating_mode_b=WRITE_FIRST
+CSET output_reset_value_a=0
+CSET output_reset_value_b=0
+CSET pipeline_stages=0
+CSET port_a_clock=100
+CSET port_a_enable_rate=100
+CSET port_a_write_rate=50
+CSET port_b_clock=100
+CSET port_b_enable_rate=100
+CSET port_b_write_rate=0
+CSET primitive=8kx2
+CSET read_width_a=8
+CSET read_width_b=8
+CSET register_porta_input_of_softecc=false
+CSET register_porta_output_of_memory_core=false
+CSET register_porta_output_of_memory_primitives=false
+CSET register_portb_output_of_memory_core=false
+CSET register_portb_output_of_memory_primitives=false
+CSET register_portb_output_of_softecc=false
+CSET remaining_memory_locations=0
+CSET reset_memory_latch_a=false
+CSET reset_memory_latch_b=false
+CSET reset_priority_a=CE
+CSET reset_priority_b=CE
+CSET reset_type=SYNC
+CSET softecc=false
+CSET use_axi_id=false
+CSET use_byte_write_enable=false
+CSET use_error_injection_pins=false
+CSET use_regcea_pin=false
+CSET use_regceb_pin=false
+CSET use_rsta_pin=false
+CSET use_rstb_pin=false
+CSET write_depth_a=8191
+CSET write_width_a=8
+CSET write_width_b=8
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2011-03-11T08:24:14.000Z
+# END Extra information
+GENERATE
+# CRC: c197a96c
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.xise
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.xise	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.xise	(revision 115)
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="mem8k8.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+    </file>
+    <file xil_pn:name="mem8k8.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|mem8k8|mem8k8_a" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="mem8k8.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mem8k8" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="mem8k8" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-03-03T17:27:19" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3A940284CDED41488E19E27EE9472069" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_flist.txt
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_flist.txt	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_flist.txt	(revision 115)
@@ -0,0 +1,26 @@
+# Output products list for <mem8k8>
+_xmsgs\pn_parser.xmsgs
+blk_mem_gen_ds512.pdf
+blk_mem_gen_v6_2_readme.txt
+mem8k8.asy
+mem8k8.gise
+mem8k8.ngc
+mem8k8.sym
+mem8k8.vhd
+mem8k8.vho
+mem8k8.xco
+mem8k8.xise
+mem8k8_flist.txt
+mem8k8_ste\example_design\bmg_wrapper.vhd
+mem8k8_ste\example_design\mem8k8_top.ucf
+mem8k8_ste\example_design\mem8k8_top.vhd
+mem8k8_ste\example_design\mem8k8_top.xdc
+mem8k8_ste\implement\implement.bat
+mem8k8_ste\implement\implement.sh
+mem8k8_ste\implement\planAhead_rdn.bat
+mem8k8_ste\implement\planAhead_rdn.sh
+mem8k8_ste\implement\planAhead_rdn.tcl
+mem8k8_ste\implement\xst.prj
+mem8k8_ste\implement\xst.scr
+mem8k8_xmdf.tcl
+summary.log
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/example_design/bmg_wrapper.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/example_design/bmg_wrapper.vhd	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/example_design/bmg_wrapper.vhd	(revision 115)
@@ -0,0 +1,269 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v6.2 Core - Top-level wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_wrapper.vhd
+--
+-- Description:
+--   This is the top-level BMG wrapper (over BMG core).
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+-- Configured Core Parameter Values:
+-- (Refer to the SIM Parameters table in the datasheet for more information on
+-- the these parameters.)
+--    C_FAMILY                    :  spartan6 
+--    C_XDEVICEFAMILY             :  spartan6 
+--    C_INTERFACE_TYPE            :  0 
+--    C_AXI_TYPE                  :  1 
+--    C_AXI_SLAVE_TYPE            :  0 
+--    C_AXI_ID_WIDTH              :  4 
+--    C_MEM_TYPE                  :  1 
+--    C_BYTE_SIZE                 :  9 
+--    C_ALGORITHM                 :  1 
+--    C_PRIM_TYPE                 :  1 
+--    C_LOAD_INIT_FILE            :  0 
+--    C_INIT_FILE_NAME            :  no_coe_file_loaded 
+--    C_USE_DEFAULT_DATA          :  0 
+--    C_DEFAULT_DATA              :  0 
+--    C_RST_TYPE                  :  SYNC 
+--    C_HAS_RSTA                  :  0 
+--    C_RST_PRIORITY_A            :  CE 
+--    C_RSTRAM_A                  :  0 
+--    C_INITA_VAL                 :  0 
+--    C_HAS_ENA                   :  1 
+--    C_HAS_REGCEA                :  0 
+--    C_USE_BYTE_WEA              :  0 
+--    C_WEA_WIDTH                 :  1 
+--    C_WRITE_MODE_A              :  WRITE_FIRST 
+--    C_WRITE_WIDTH_A             :  8 
+--    C_READ_WIDTH_A              :  8 
+--    C_WRITE_DEPTH_A             :  8191 
+--    C_READ_DEPTH_A              :  8191 
+--    C_ADDRA_WIDTH               :  13 
+--    C_HAS_RSTB                  :  0 
+--    C_RST_PRIORITY_B            :  CE 
+--    C_RSTRAM_B                  :  0 
+--    C_INITB_VAL                 :  0 
+--    C_HAS_ENB                   :  1 
+--    C_HAS_REGCEB                :  0 
+--    C_USE_BYTE_WEB              :  0 
+--    C_WEB_WIDTH                 :  1 
+--    C_WRITE_MODE_B              :  WRITE_FIRST 
+--    C_WRITE_WIDTH_B             :  8 
+--    C_READ_WIDTH_B              :  8 
+--    C_WRITE_DEPTH_B             :  8191 
+--    C_READ_DEPTH_B              :  8191 
+--    C_ADDRB_WIDTH               :  13 
+--    C_HAS_MEM_OUTPUT_REGS_A     :  0 
+--    C_HAS_MEM_OUTPUT_REGS_B     :  0 
+--    C_HAS_MUX_OUTPUT_REGS_A     :  0 
+--    C_HAS_MUX_OUTPUT_REGS_B     :  0 
+--    C_HAS_SOFTECC_INPUT_REGS_A  :  0 
+--    C_HAS_SOFTECC_OUTPUT_REGS_B :  0 
+--    C_MUX_PIPELINE_STAGES       :  0 
+--    C_USE_ECC                   :  0 
+--    C_USE_SOFTECC               :  0 
+--    C_HAS_INJECTERR             :  0 
+--    C_SIM_COLLISION_CHECK       :  ALL 
+--    C_COMMON_CLK                :  0 
+--    C_DISABLE_WARN_BHV_COLL     :  0 
+--    C_DISABLE_WARN_BHV_RANGE    :  0 
+
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY bmg_wrapper IS
+  PORT (
+    --Port A
+    CLKA       : IN STD_LOGIC;
+    RSTA       : IN STD_LOGIC;  --opt port
+    ENA        : IN STD_LOGIC;  --optional port
+    REGCEA     : IN STD_LOGIC;  --optional port
+    WEA        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRA      : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    DINA       : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    DOUTA      : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+    --Port B
+    CLKB       : IN STD_LOGIC;
+    RSTB       : IN STD_LOGIC;  --opt port
+    ENB        : IN STD_LOGIC;  --optional port
+    REGCEB     : IN STD_LOGIC;  --optional port
+    WEB        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRB      : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    DINB       : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    DOUTB      : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+    --ECC
+    INJECTSBITERR  : IN STD_LOGIC; --optional port
+    INJECTDBITERR  : IN STD_LOGIC; --optional port
+    SBITERR        : OUT STD_LOGIC; --optional port
+    DBITERR        : OUT STD_LOGIC; --optional port
+    RDADDRECC      : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
+ -- AXI BMG Input and Output Port Declarations
+
+    -- AXI Global Signals
+    S_ACLK                         : IN  STD_LOGIC;
+    S_AXI_AWID                     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+    S_AXI_AWADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXI_AWLEN                    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXI_AWSIZE                   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
+    S_AXI_AWBURST                  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_AWVALID                  : IN  STD_LOGIC;
+    S_AXI_AWREADY                  : OUT STD_LOGIC;
+    S_AXI_WDATA                    : IN  STD_LOGIC_VECTOR(7  DOWNTO 0);
+    S_AXI_WSTRB                    : IN  STD_LOGIC_VECTOR(0  DOWNTO 0);
+    S_AXI_WLAST                    : IN  STD_LOGIC;
+    S_AXI_WVALID                   : IN  STD_LOGIC;
+    S_AXI_WREADY                   : OUT STD_LOGIC;
+    S_AXI_BID                      : OUT STD_LOGIC_VECTOR(3  DOWNTO 0):= (OTHERS => '0');
+    S_AXI_BRESP                    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_BVALID                   : OUT STD_LOGIC;
+    S_AXI_BREADY                   : IN  STD_LOGIC;
+
+    -- AXI Full/Lite Slave Read (Write side)
+    S_AXI_ARID                     : IN  STD_LOGIC_VECTOR(3  DOWNTO 0);
+    S_AXI_ARADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXI_ARLEN                    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXI_ARSIZE                   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
+    S_AXI_ARBURST                  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_ARVALID                  : IN  STD_LOGIC;
+    S_AXI_ARREADY                  : OUT STD_LOGIC;
+    S_AXI_RID                      : OUT STD_LOGIC_VECTOR(3  DOWNTO 0):= (OTHERS => '0');
+    S_AXI_RDATA                    : OUT STD_LOGIC_VECTOR(7  DOWNTO 0);
+    S_AXI_RRESP                    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_RLAST                    : OUT STD_LOGIC;
+    S_AXI_RVALID                   : OUT STD_LOGIC;
+    S_AXI_RREADY                   : IN  STD_LOGIC;
+
+    -- AXI Full/Lite Sideband Signals
+    S_AXI_INJECTSBITERR            : IN  STD_LOGIC;
+    S_AXI_INJECTDBITERR            : IN  STD_LOGIC;
+    S_AXI_SBITERR                  : OUT STD_LOGIC;
+    S_AXI_DBITERR                  : OUT STD_LOGIC;
+    S_AXI_RDADDRECC                : OUT STD_LOGIC_VECTOR(12  DOWNTO 0);
+    S_ARESETN                      : IN  STD_LOGIC
+
+
+  );
+
+END bmg_wrapper;
+
+
+ARCHITECTURE xilinx OF bmg_wrapper IS
+
+  COMPONENT mem8k8_top IS
+  PORT (
+      --Port A
+    ENA            : IN STD_LOGIC;  --opt port
+  
+    WEA            : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRA          : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+  
+    DINA           : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+  
+    CLKA       : IN STD_LOGIC;
+
+  
+      --Port B
+    ENB            : IN STD_LOGIC;  --opt port
+    ADDRB          : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    DOUTB          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    CLKB           : IN STD_LOGIC
+
+
+  );
+  END COMPONENT;
+
+BEGIN
+
+  bmg0 : mem8k8_top
+    PORT MAP (
+      --Port A
+      ENA        => ENA,
+  
+      WEA        => WEA,
+      ADDRA      => ADDRA,
+  
+      DINA       => DINA,
+
+      CLKA       => CLKA,
+  
+      --Port B
+      ENB        => ENB, 
+      ADDRB      => ADDRB,
+      DOUTB      => DOUTB,
+      CLKB       => CLKB
+
+
+      );
+END xilinx;
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.ucf
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.ucf	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.ucf	(revision 115)
@@ -0,0 +1,61 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Tx Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+NET "CLKA"  TNM_NET     = "CLKA";
+  
+NET "CLKB"  TNM_NET     = "CLKB";
+
+TIMESPEC "TS_CLKA"      = PERIOD "CLKA"  25 MHZ;
+  
+TIMESPEC "TS_CLKB"      = PERIOD "CLKB"  25 MHZ;
+
+################################################################################
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.vhd	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.vhd	(revision 115)
@@ -0,0 +1,178 @@
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v6.2 Core - Top-level core wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_wrapper.vhd
+--
+-- Description:
+--   This is the actual BMG core wrapper.
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY mem8k8_top IS
+  PORT (
+      --Inputs - Port A
+    ENA            : IN STD_LOGIC;  --opt port
+  
+    WEA            : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRA          : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+  
+    DINA           : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+  
+    CLKA       : IN STD_LOGIC;
+
+  
+      --Inputs - Port B
+    ENB            : IN STD_LOGIC;  --opt port
+    ADDRB          : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    DOUTB          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    CLKB           : IN STD_LOGIC
+
+  );
+
+END mem8k8_top;
+
+
+ARCHITECTURE xilinx OF mem8k8_top IS
+
+  COMPONENT BUFG IS
+  PORT (
+     I      : IN STD_ULOGIC;
+     O      : OUT STD_ULOGIC
+  );
+  END COMPONENT;
+
+  COMPONENT mem8k8 IS
+  PORT (
+      --Port A
+    ENA        : IN STD_LOGIC;  --opt port
+  
+    WEA        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRA      : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+  
+    DINA       : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+  
+    CLKA       : IN STD_LOGIC;
+
+  
+      --Port B
+    ENB        : IN STD_LOGIC;  --opt port
+    ADDRB      : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    DOUTB      : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    CLKB       : IN STD_LOGIC
+
+
+  );
+  END COMPONENT;
+
+  SIGNAL CLKA_buf     : STD_LOGIC;
+  SIGNAL CLKB_buf     : STD_LOGIC;
+  SIGNAL S_ACLK_buf   : STD_LOGIC;
+
+BEGIN
+
+  bufg_A : BUFG
+    PORT MAP (
+     I => CLKA,
+     O => CLKA_buf
+     );
+
+  bufg_B : BUFG
+    PORT MAP (
+     I => CLKB,
+     O => CLKB_buf
+     );
+
+
+  bmg0 : mem8k8
+    PORT MAP (
+      --Port A
+      ENA        => ENA,
+  
+      WEA        => WEA,
+      ADDRA      => ADDRA,
+  
+      DINA       => DINA,
+
+      CLKA       => CLKA_buf,
+
+  
+      --Port B
+      ENB        => ENB, 
+      ADDRB      => ADDRB,
+      DOUTB      => DOUTB,
+      CLKB       => CLKB_buf
+
+    );
+
+END xilinx;
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.xdc
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.xdc	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.xdc	(revision 115)
@@ -0,0 +1,56 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ]
+  
+create_clock -name "TS_CLKB" -period 20.0 [ get_ports CLKB ]
+################################################################################
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/implement.bat
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/implement.bat	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/implement.bat	(revision 115)
@@ -0,0 +1,41 @@
+
+rem Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+rem Synthesize the VHDL Wrapper Files
+
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+copy mem8k8_top.ngc .\results\
+
+
+rem Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+copy ..\..\mem8k8.ngc results\
+
+
+rem  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\mem8k8_top.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc6slx45-csg324-3 mem8k8_top
+
+echo 'Running map'
+map mem8k8_top -o mapped.ncd -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level VHDL model'
+netgen -ofmt vhdl -sim -tm mem8k8_top -pcf mapped.pcf -w routed.ncd routed.vhd
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/implement.sh
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/implement.sh	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/implement.sh	(revision 115)
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+#Synthesize the Wrapper Files
+echo 'Synthesizing XST wrapper file (core_top.vhd) with XST';
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+cp mem8k8_top.ngc ./results/
+
+
+# Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+cp ../../mem8k8.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/mem8k8_top.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc6slx45-csg324-3 mem8k8_top
+
+echo 'Running map'
+map mem8k8_top -o mapped.ncd -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level VHDL model'
+netgen -ofmt vhdl -sim -tm mem8k8_top -pcf mapped.pcf -w routed.ncd routed.vhd
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.bat
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.bat	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.bat	(revision 115)
@@ -0,0 +1,55 @@
+#!/bin/sh
+rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+rem 
+rem This file contains confidential and proprietary information
+rem of Xilinx, Inc. and is protected under U.S. and
+rem international copyright and other intellectual property
+rem laws.
+rem 
+rem DISCLAIMER
+rem This disclaimer is not a license and does not grant any
+rem rights to the materials distributed herewith. Except as
+rem otherwise provided in a valid license issued to you by
+rem Xilinx, and to the maximum extent permitted by applicable
+rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+rem (2) Xilinx shall not be liable (whether in contract or tort,
+rem including negligence, or under any other theory of
+rem liability) for any loss or damage of any kind or nature
+rem related to, arising under or in connection with these
+rem materials, including for any direct, or any indirect,
+rem special, incidental, or consequential loss or damage
+rem (including loss of data, profits, goodwill, or any type of
+rem loss or damage suffered as a result of any action brought
+rem by a third party) even if such damage or loss was
+rem reasonably foreseeable or Xilinx had been advised of the
+rem possibility of the same.
+rem 
+rem CRITICAL APPLICATIONS
+rem Xilinx products are not designed or intended to be fail-
+rem safe, or for use in any application requiring fail-safe
+rem performance, such as life-support or safety devices or
+rem systems, Class III medical devices, nuclear facilities,
+rem applications related to the deployment of airbags, or any
+rem other applications that could lead to death, personal
+rem injury, or severe property or environmental damage
+rem (individually and collectively, "Critical
+rem Applications"). Customer assumes the sole risk and
+rem liability of any use of Xilinx products in Critical
+rem Applications, subject only to applicable laws and
+rem regulations governing limitations on product liability.
+rem 
+rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+rem PART OF THIS FILE AT ALL TIMES.
+
+rem -----------------------------------------------------------------------------
+rem  Script to synthesize and implement the Coregen FIFO Generator
+rem -----------------------------------------------------------------------------
+rmdir /S /Q results
+mkdir results
+cd results
+copy ..\..\..\tmp\mem8k8.edf .
+planAhead -mode batch -source ..\planAhead_rdn.tcl
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.sh
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.sh	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.sh	(revision 115)
@@ -0,0 +1,55 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+#-----------------------------------------------------------------------------
+#  Script to synthesize and implement the Coregen FIFO Generator
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+cp ../../../tmp/mem8k8.edf .
+planAhead -mode batch -source ../planAhead_rdn.tcl
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.tcl
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.tcl	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.tcl	(revision 115)
@@ -0,0 +1,68 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+set device xc6slx45csg324-3
+set projName mem8k8
+set design mem8k8
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module mem8k8_top
+add_files -norecurse {../../example_design/mem8k8_top.vhd}
+add_files -norecurse {./mem8k8.edf}
+import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/mem8k8_top.xdc}
+set_property top mem8k8_top [get_property srcset [current_run]]
+synth_design
+opt_design 
+place_design 
+route_design 
+set_param sta.dlyMediator true
+write_sdf -rename_top_module mem8k8_top -file routed.sdf 
+write_verilog -nolib -mode sim -sdf_anno false -rename_top_module mem8k8_top routed.vhd
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file routed.drc
+#write_bitstream
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/xst.prj
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/xst.prj	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/xst.prj	(revision 115)
@@ -0,0 +1,1 @@
+work ../example_design/mem8k8_top.vhd
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/xst.scr
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/xst.scr	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_ste/implement/xst.scr	(revision 115)
@@ -0,0 +1,13 @@
+run
+-ifmt VHDL
+-ent mem8k8_top
+-p xc6slx45-csg324-3
+-ifn xst.prj
+-write_timing_constraints No
+-iobuf YES
+-max_fanout 100
+-ofn mem8k8_top 
+-ofmt NGC
+-bus_delimiter ()
+-hierarchy_separator /
+-case Maintain
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_xmdf.tcl
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_xmdf.tcl	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8_xmdf.tcl	(revision 115)
@@ -0,0 +1,127 @@
+# The package naming convention is <core_name>_xmdf
+package provide mem8k8_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::mem8k8_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::mem8k8_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name mem8k8
+}
+# ::mem8k8_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::mem8k8_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8.sym
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8.vho
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8_ste/example_design/bmg_wrapper.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8_ste/example_design/mem8k8_top.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8_ste/example_design/mem8k8_top.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8_ste/example_design/mem8k8_top.xdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8_ste/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8_ste/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8_ste/implement/planAhead_rdn.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8_ste/implement/planAhead_rdn.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8_ste/implement/planAhead_rdn.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8_ste/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8_ste/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem8k8_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module mem8k8
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.asy
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.asy	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.asy	(revision 115)
@@ -0,0 +1,41 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 mem_4k8
+RECTANGLE Normal 32 32 544 1376
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName addra[11:0]
+PINATTR Polarity IN
+LINE Wide 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName dina[7:0]
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName ena
+PINATTR Polarity IN
+LINE Wide 0 208 32 208
+PIN 0 208 LEFT 36
+PINATTR PinName wea[0:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName clka
+PINATTR Polarity IN
+LINE Wide 0 432 32 432
+PIN 0 432 LEFT 36
+PINATTR PinName addrb[11:0]
+PINATTR Polarity IN
+LINE Normal 0 496 32 496
+PIN 0 496 LEFT 36
+PINATTR PinName enb
+PINATTR Polarity IN
+LINE Normal 0 624 32 624
+PIN 0 624 LEFT 36
+PINATTR PinName clkb
+PINATTR Polarity IN
+LINE Wide 576 368 544 368
+PIN 576 368 RIGHT 36
+PINATTR PinName doutb[7:0]
+PINATTR Polarity OUT
+
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.gise
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.gise	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.gise	(revision 115)
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="mem_4k8.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_v6_2_readme.txt" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="mem_4k8.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="mem_4k8.sym" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VHO" xil_pn:name="mem_4k8.vho" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.ngc
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.ngc	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.ngc	(revision 115)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$0d540<,[o}e~g`n;"2*731&=$:,)<4-0384<=789:;<=>?4193456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?01220>752@D[YY4ndepb847=87;?7<<5IORVP?gcl{h7=<4?>06851<NFY__6LJKR@>27?699=1:87GAPTV9EABUJ5;86=0>0:39MKVR\3}nm1>50?38644<;;0BB][[:EKB867=87;97><5IORVP?BNJ59:6=0>3:11>JSSX\^1HBO33083:45<;;0DYY^ZT;FLF956294:=6:5IORVP?BNXH686=0>1:69MKVR\3NB\O2<:1<24>2=AGZ^X7YJA=194;773=0BB][[:VGA86<7688087AZTQWW>AIWI591<3?=;58LQQVR\3ND\O2<:1<f?3ukp=?hj==4,12?=76310BB][[:ekme91=87;8754@UURVP?bh}}h7;7>18:CG@WG;8730MIJ]A=33:<=FLMXJ0<?19:CG@WG;9;4i7LJKR@>27?6912KOH_O312<;?DBCZH6:255NDEPB878?3HNO^L2<>99B@ATF4=437LJKR@>6:==FLMXJ0;07;@FGVD:0611JHI\N<9<;?DBCZH62255NDEPA858>3HNO^O2>0?;8EABUJ5;:245NDEPA8449j2KOH_L31283:<=FLMXI0<=18:CG@WD;9720MIJ]B=0=<>GCL[H7?364AEFQF92902KOH_L35?:8EABUJ5<546OKDS@?3;><IMNYN1618:CG@WD;1790MAB7;CWP[LHAG81H>6MJ139@L@ELWECHIC]J_U[SA1=DDB:=7NBD1925?FJL:>:>7NBD2Y:8GIM5P82;96MCK827?FJLI<1H@FO>7:AOOD7C:>1H@FO>D558GIMF9M2?7NBDB49@HND6=2IGGN?:;BNH@43<KEAOZn5LLJFU[AOQAMO>7NBDFY:8GIMAP82;56M@MLKWP@B6<2ID^HQHEOGQEQOHFVCEJB94CSGBP@B63Mi0HLZN_VKGPMYFk2NJXLQXIEVK[G0<L@K7<394DHC?55803MCJ0<?17:FJE9756>1OEL2>3?58@LG;9=4<7IGN<07=3>BNI5;=2:5KI@>23;1<L@K7=508;EKB84?9>2NBM1?17:FJE9476>1OEL2=1?58@LG;:;4<7IGN<31=3>BNI58?2:5KI@>11;1<L@K7>;08;EKB8719?2NBM1<7>69GMD:517<0HDO32?58@LG;;9427IGN<2394;1<L@K7?<09;EKB86813MCJ0909;EKB80813MCJ0;09;EKB82813MCJ0509;EKB8<813MCI0=08;EKA8469?2NBN1?>>69GMG:6:7=0HDL312<4?AOE48>5;6JFB=36:2=CAK6::394DH@?52803MCI0<617:FJF97>6?1OEO2>>69GMG:587=0HDL320<4?AOE4;85;6JFB=00:2=CAK698394DH@?60803MCI0?817:FJF9406>1OEO2=8?58@LD;:04=7IGM<3<4?AOE4::556JFB=12>5803MCI0>?16:FJF959>2NBN1:16:FJF939>2NBN1816:FJF919>2NBN1616:FJF9?9?2NB\L2?>69GMUG;97=0HD^N<3<:?AOWI591<394DHRB86803MC[N1>17:FJTG:66>1OE]L32?;8@LVE4:0;2:5KIQ@?7;0<LFK7<394DNC?55803MEJ0<?17:FLE9756>1OCL2>3?58@JG;9=4<7IAN<07=3>BHI5;=2:5KO@>23;1<LFK7=508;EMB84?9>2NDM1?17:FLE9476>1OCL2=1?58@JG;:;4<7IAN<31=3>BHI58?2:5KO@>11;1<LFK7>;08;EMB8719?2NDM1<7>69GKD:517<0HBO32?58@JG;;9427IAN<2394;1<LFK7?<09;EMB86813MEJ0909;EMB80813MEJ0;09;EMB82813MEJ0509;EMB8<803MEJS_KH6:FLF969?2NDN1??>69GKG:697=0HBL313<4?AIE4895;6J@B=37:2=CGK6:9394DN@?53803MEI0<917:FLF97?6>1OCO2>9?48@JD;97=0HBL321<4?AIE4;;5;6J@B=01:2=CGK69?394DN@?61803MEI0?;17:FLF9416>1OCO2=7?58@JD;:14<7IAM<3;=2>BHJ585;6J@B=13:<=CGK68=7>17:FLF9566?1OCO2<>79GKG:36?1OCO2:>79GKG:16?1OCO28>79GKG:?6?1OCO26>69GKGYUMN=0HB^N<1<4?AIWI5;5;6J@P@>1:<=CGYK7?7>17:FLTD:46>1OC]L30?58@JVE484<7IA_B=0==>BHXK686=08;EMSF959:2O??6KAA29FJGd<MGUY_Y\NM^Ca?@HXZZ^YM@QM5:DBHVC43ONN=6I<;FLG6>O7:2C:>6G=8:KMMQVX8920ECG[P^22<>OIA]ZT<?64IOKWTZ6402CEEY^P05:8MKOSXV:>46GAIUR\43><AGC_\R>89:KMMQUSI]O<7D@FT^233>OIA]U;=:5FNHV\471<AGC_S==8;HLJPZ63?2CEEYQ?569JJLRX8?=0ECG[_154?LHN\V:3;6GAIU]3=2=NF@^T<L94IOKW[5D03@DBXR>L7:KMMQY7L>1BBDZP0D58MKOSW9L<7D@FT^333>OIA]U:=:5FNHV\571<AGC_S<=8;HLJPZ73?2CEEYQ>569JJLRX9?=0ECG[_054?LHN\V;3;6GAIU]2=2=NF@^T=L94IOKW[4D03@DBXR?L7:KMMQY6L>1BBDZP1D58MKOSW8L<7D@FT^033>OIA]U9=:5FNHV\671<AGC_S?=8;HLJPZ43?2CEEYQ=569JJLRX:?=0ECG[_354?LHN\V83;6GAIU]1=2=NF@^T>L94IOKW[7D03@DBXR<L7:KMMQY5L>1BBDZP2D58MKOSW;L<7D@FT^133>OIA]U8=:5FNHV\771<AGC_S>=8;HLJPZ53?2CEEYQ<569JJLRX;?=0ECG[_254?LHN\V93;6GAIU]0=2=NF@^T?L94IOKW[6D03@DBXR=L7:KMMQY4L>1BBDZP3D58MKOSW:L=7D@FT^C5?LHN\VH27D@FT^DJH@0<DFKOII84LNAHAA1<DFMBOLB;;MWW61=K]]9h7@oeosTfvvohfj1Feca}Vdppmjh53G;<7CK[WNPH0>HHFL;0C55@.64{`ZJ33YKYXl5_IO]AQVOCPk1[ECQMURLBI@?<XBUC@XZAM79SWAIIM81Zm6\NMC35FRCU>2XNKNKN6:PFCFCE<2XXXL:4RRVA3>TT\]S[Ih5]SU]SVLIUA]STMh5]SU]SVLIUA]STN<?4SIPFCZC_\[KHXR@HCd9PLWC@WDCES^GUE018WLKXKFFGE^G@N^AKAFMf3ZCFSIKYIBG5?VIRZJO37^^NRUCM22=TZ_KGSL94SSTBHZD13Z^JXX];;R[MG1=SQYO>h6[?/yqw[gjlWdofSjkaescwkw)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+sgkam$hy| h`q\ip~Xj'H$A`{w_emvpZkrp8;>h6[?/yqw[gjlWdofSjkaescwkw)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+sgkam$hy| h`q\ip~Xj'H$A`{w_emvpZkrp;;>h6[?/yqw[gjlWdofSjkaescwkw)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+sgkam$hy| h`q\ip~Xj'H$A`{w_emvpZkrp:;>h6[?/yqw[gjlWdofSjkaescwkw)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+sgkam$hy| h`q\ip~Xj'H$A`{w_emvpZkrp=;>h6[?/yqw[gjlWdofSjkaescwkw)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+sgkam$hy| h`q\ip~Xj'H$A`{w_emvpZkrp<;>h6[?/yqw[gjlWdofSjkaescwkw)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+sgkam$hy| h`q\ip~Xj'H$A`{w_emvpZkrp?;>h6[?/yqw[gjlWdofSjkaescwkw)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+sgkam$hy| h`q\ip~Xj'H$A`{w_emvpZkrp>;>h6[?/yqw[gjlWdofSjkaescwkw)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+sgkam$hy| h`q\ip~Xj'H$A`{w_emvpZkrp1;>56[?/yqw[gjlWdofSjkaescwkw)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+sgkam$hy| h`q\ip~Xj'H$hbPphrf848202_;#u}{_cnh[hcjWnoeio{os-djdrn~lhfk#`nthtf[gjlWdofSjka/wcoma(d{}x$dl}Pmtz\f+D({lfT|d~j_065?P6(pz~TnaePmdo\c`hbzh~d~"iaaukuagk`&gke{kPbmi\i`kXold$zlbfd/appw)h}};?;6[?/yqw[gjlWdofSjkaescwkw)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+sgkam$hy| otv2511<]9%syQmlj]nahY`mgoymya}/flbplpbjdm%blzfvd]ahnYjmdUlic!yamkg*fusz&e~x??;7:W3+}usWkf`S`kb_fgmawgsg{%lblzfvd`nc+hf|`|nSobd_lgn[bci'kgei lsup,kpr49><0Y=!wsu]ahnYjmdUlick}aumq+bhf|`|nn`i!n`vjr`YedbUfi`Qheo-ueioc&jy~"|nmmmlt^6Z&{kf"!|6^llmkos&{kf#^J_.RKNTICXX[CF=5 }al:3?P6(pz~TnaePmdo\c`hbzh~d~"iaaukuagk`&gke{kPbmi\i`kXold$zlbfd/appw)uidfdc}U?]/pbi+t({?Uecd`ft/pbi*UCX'YBA]BJ_QPJI4>)zhgTec}zl`vf4=6<]9%syQmlj]nahY`mgoymya}/flbplpbjdm%blzfvd]ahnYjmdUlic!yamkg*fusz&xjaaa`pZ2^*wgj&{%x:R``iokw*wgj'ZN["^GBPMG\TWOJ91$ym`Qfnrwoeqc6=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf969=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf979=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf949=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf959=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf929=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf939=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf909=m1^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPdnwwf919=11^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_5[)zhg%~lcPeoc6<>S7'qySobd_lgn[bcim{kc!hn`vjr`djo'djxdxj_cnh[hcjWnoe#{ocie,`wqt(zhggcb~T0\,qeh(uidUnbo99;T2,|vrXjeaTahcPgdlfvdrhz&memygyecod*kgsaoTnaePmdo\c`h(~hfbh#m|ts-qehjhgyQ:Q#|nm/p,w3Yig`dbx#|nm.QGT+UNEYFNS]\FM0:-vdk?82_;#u}{_cnh[hcjWnoeio{os-djdrn~lhfk#`nthtf[gjlWdofSjka/wcoma(d{}x$~lcconrX5X(uid$y#~8Pnnkmmq(uid%XH] \ILROAZVUAD;3"ob_hlpqigsm92;7X> xrv\fimXelgTkh`jr`vlv*aii}c}ioch.ocwmscXjeaTahcPgdl,rdjnl'ixx!}alnlku]6U'xja#| s7]mklhn|'xja"]KP/QJIUJBWYXBA<6!r`o\mkurdh~n=8j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6;28j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6:28j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6928j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6828j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6?28j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6>28j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6=28j4U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[air|k6<2864U1-{wqYedbUfi`Qheogqeqiu'ndjxdxjble-jdrn~lUi`fQbel]dak)qieco"n}{r.pbiiihxR;V"ob.scn[`hf=11^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#oblnms_4[)zhg%~lcPeo``?PUBZV\B_DLCE89UM@QX\PZN:6YJA=2=2>QBI5;5:6YJA=0=<>QBI591<384WDC?7;0<_LH7<384WD@?5;0<_LH7>364WD@?7?69>2]NN1=1b:UQMQCXN@XXXn5XRHVF[HICMVKh7Z\FTD]NKACXJ8n0TDBFNY/[@G&7&8*XXXL/0/3#EVENA?1S_YBFB69[WQY@FMh0TRM@RD]JJCI13QniSDji;Yfk[Utne_oydaa119[`hYJiceyZh||inl24>^ceVGbbb|Yesqjkk5<Pz~87Tk|549\[Z^KFDUTS=QP_T2,|vrXjeaTahcPgdlfvdrhz&memygyecod*kgsaoTnaePmdo\c`h(~hfbh#m|ts-lqq56=<1TSRVCNL]\[4YXW\:$t~zPbmi\i`kXoldn~lz`r.emeqoqmkgl"co{iwg\fimXelgTkh` v`nj`+et|{%dyy?>6c9\[Z^KFDUTS?QP_T2,|vrXjeaTahcPgdlfvdrhz&memygyecod*kgsaoTnaePmdo\c`h(~hfbh#m|ts-kevYj}qUi"O!Bmtz\`jssWds;<8m;^]\\IHJWVU8SRQZ0.zppZdkcVgnaRijndpbpjt(ogke{kmmf,meqoqmVhggRcjm^efj*pfd`n%o~z}/icp[hsWk$I#@czx^flqqYj}q?::o5P_^ZOJHYXW=UTSX> xrv\fimXelgTkh`jr`vlv*aii}c}ioch.ocwmscXjeaTahcPgdl,rdjnl'ixx!gar]nq}Ye&K%FaxvPdnww[hs;8<i7RQPXMLN[ZY2WVU^<"v|t^`ooZkbeVmnbh|ntnp,ckgsaoiaj aaukuaZdkcVgnaRijn.tbhlb)kz~y#eo|_lw{[g(E'Dg~tRj`uu]nq}7602koho30?;8eabui5;;2o5ndepb847=8730mij}a=32:==flmxj0<07;`fgvd:5611jhi|n<2<;?dbczh6?255ndepb808?3hno~l29>99b`atf4>437ljkr`>;:==flmxj0407;`fgvg:7601jhi|m<02=f>gcl{h7=<4?>89b`ate48;546okds`?5;><imnyn1<18:cg`wd;;720mij}b=6=<>gcl{h79364aefqf90902kohl37?:8eabuj52546okds`?=;0<j`doin?7;cnh[hcjWnoeSjkaesk`[fuszo1i`fQbel]dakYj}q;37obd_lgn[bciWyxbaRyfduj\54><jeaTahcPgdl\twojW~coxeQ=1e9ahnYjmdUlicQrho\swgwxlxT;Q>1e9ahnYjmdUlicQrho\swgwxlxT;Q=f:`ooZkbeVmnbRz`p028fimXelgTkh`Pv7]16f=edbUfi`Qheo]u2Z4+(Qcgecv/CNPF$Bcim{kc.>3/120>dkcVgnaRijn^t5[7Y{};87obd_lgn[lhw}}Ui`bmd159ahnYjmdUdyy~zt^`okfm33jf`m95llj`4?aoii5:5;6jfn`>2:2=cagk7>394dhlb86803mcem1:17:fjjd:26>1oeco36?;8`lhf4>0;2:5kioc?3;><lfn1>18:flqqd;9720hb{{b=0=<>bh}}h7?364dnwwf92902ndyyl35?:8`jssj5<5m6j`uu`?3?6902ndyyl37?18akg43ldi;6cjm^6h<1?e3dofS9e7,cnh[hcjWnoeS{8P2-y`[dbczhU|eizg=00/gZgcl{hT{dj{h<31(fYfdneyeyfb=0.`[d~nW`nT{dj{h<6/gZgaVygm{kPtxrf95*dWhrbSywe<3/gZd~|lUxewk28-a\gjkjggUh`f3?,b]gacgrd}Uomyo20-a\`lufjeoT{l|a_cju[fikd4:'oRjfs``oaZqfzgUid{Q}aoef95*dWlfjnb|nthmm[aou5M0$A]GPHBN,P`usW]cfi!fpbmqaZbnz&~f|"Qlg..`[cgjaes6}o}t`l5(fYoizUjtdQfd<2/gZnf{Voem0?#c^jbwZcij4;'oRfns^kmn`esm{x6<!mPh`q\i`kXg|~{yyQ}efq\e86+kVbjRcjm^mvpussW{olRl20-a\lduXe|rTcxzuu]qabuXi4:'oRfns^ov|Zir|ySkhs^`>4)eX`hyT~hile`?3(fYoizUyijmjb<2/gZnf{Vxxxl3?,b]kevYu{}h6<!mPh`q\wj`smjiTec~zt^pfcvYf59&hSeo|_rmep`edWf|xzPrdep[g;7$jUbbdzPfhnf[kgjm4ddSnaj_gkoaZjhimoo nQfnhvb[sgk59&hSd`ftc]uei;7$jUbbyk}f`af[qwm4:'oRb`ae]jjlrXn`fn1="l_lgn[qwm4;'oRczx^rjt`jnflUxxlijs<2/gZvuadUu}k21-a\v`gcWmo{xeQn=52:2)eXzlkoSikti]a916>>%iT~hok_vkgpmYf51&hSknd^uj`qnXj42'oR||t^rqmjtn|pUj1NK#c^pppZvuafxbxtQm=BG/gZtt|V~r|h3\YOA/gZtt|{kfSl3?,b]qwqtfeVh6<!mPsho\gjjkazcdbRmgebi>EIJ+kVxiRlvtd]tad;6$jU~hQmyug\s`d:9%iTy~kPdddbqirXlh~j1="l_tqf[`ed59&hSx}j_rmep`ed59&hSzkn_vkgpm;6$jU|ioQxievk94*dW~xbxhQkeqvk[d;380<'oRy}iug\``vs`Vh68=79,b]tvlrbWdeoiRo2WSKWAZ@NZZ^'oRy}iug\ijbbWk7\^DZJ_GKQWQ*dW~xbxhQxievk[d;?$jU|~dzj_vkgpmYe51&hSujjvhafbdkndp7x|l|{ao4~5g=jmdU?g5"mlj]nahY`mgU}:R<#{|:8jbee}`fo46yja=294;0<lk7<3sO@q043>FGp8l;6K4;:0yP14<6ik0:9?4>32724c<69>o9wc?n9;38j4gf2?1/=l951`18yV2a28ki6<;=:010146a28;<io5\15595c5=83;8?8??f;32<41<[=l1=k=50;307077n3;:4<o4d0d3>5<628qX9<4>ac8217<6;:?:<k4>16g:?sR6><0;6<4>:51xW07=9hh1=8<5121655`=98=n56*>94820<=Q9h21>v{>4b82?p73l3:0q)?:3;36?g7a83:1>i4>0;60M7><2.::o4>f19Y7=<2s00>6<956;3;>x"6i?0:h;5+3c82b7=#=90:j<5+17095>"6>80:mn5f1g794?"6=<0:j95a14694>=n9k<1<7*>5482f0=i9<>1<65f1c694?"6=<0:n85a14695>=n9kl1<7*>5482f0=i9<>1>65f1cg94?"6=<0:n85a14697>=n9kn1<7*>5482f0=i9<>1865f1ca94?"6=<0:n85a14691>=n9kh1<7*>5482f0=i9<>1:65f1cc94?"6=<0:n85a14693>=n9k31<7*>5482f0=i9<>1465f1c:94?"6=<0:n85a1469=>=n9k=1<7*>5482f0=i9<>1m65f1c194?"6=<0:n85a1469f>=n9l>1<7*>5482a6=i9<>1<65f1d094?"6=<0:i>5a14695>=n9l;1<7*>5482a6=i9<>1>65f1d294?"6=<0:i>5a14697>=n9ml1<7*>5482a6=i9<>1865f1eg94?"6=<0:i>5a14691>=n9mn1<7*>5482a6=i9<>1:65f1ea94?"6=<0:i>5a14693>=n9j91<7*>5482g7=i9<>1<65f1b394?"6=<0:o?5a14695>=n9ji1<7*>5482g7=i9<>1>65f1b`94?"6=<0:o?5a14697>=n9jk1<7*>5482g7=i9<>1865f1b;94?"6=<0:o?5a14691>=n9j21<7*>5482g7=i9<>1:65f1b594?"6=<0:o?5a14693>=n9j<1<7*>5482g7=i9<>1465f1b794?"6=<0:o?5a1469=>=n9j>1<7*>5482g7=i9<>1m65f1b294?"6=<0:o?5a1469f>=n9mk1<75f1dg94?=n9mh1<75f1dd94?=h9ln1<7*>5482af=i9<>1<65`1d`94?"6=<0:in5a14695>=h9lk1<7*>5482af=i9<>1>65`1d;94?"6=<0:in5a14697>=h9l21<7*>5482af=i9<>1865`1d594?"6=<0:in5a14691>=h9l<1<7*>5482af=i9<>1:65`1d794?"6=<0:in5a14693>=e9h?1<7?50;2x 40e2o=0D<o;;I3:0>ia>3:17pl>7483>1<729q/=;l5f49K5d2<@83?7)??3;08m6?=831b?l4?::k66?6=3f;>47>5;|`22f<72=0;6=u+17`951d<@8k?7E?64:&246<bn2.:9;4>b39jb=<722cm57>5;hdb>5<<g8?:6=44}c35`?6=<3:1<v*>6c820g=O9h>0D<7;;%337?ca3-;>:7?m2:ke<?6=3`l26=44igc94?=h9<;1<75rb04f>5<3290;w)?9b;37f>N6i=1C=4:4$020>``<,8?=6<l>;hd;>5<<ao31<75ff`83>>i6=80;66sm17d94?2=83:p(<8m:06a?M7f<2B:595+1119ac=#9<<1=o?4ig:94?=nn00;66gia;29?j7293:17pl>7183>1<729q/=;l515`8L4g33A;286*>028fb>"6=?0:n=5ff983>>oa13:17dhn:188k4362900qo?81;290?6=8r.::o4>4c9K5d2<@83?7)??3;ge?!72>3;i<6gi8;29?l`>2900eko50;9l507=831vn<9=:187>5<7s-;=n7?;b:J2e1=O90>0(<><:dd8 43128km7dh7:188mc?=831bjl4?::m214<722wi=:=50;694?6|,8<i6<:m;I3b0>N61=1/===5eg9'500=9hl0ek650;9jb<<722cmm7>5;n365?6=3th:;44?:283>5}#9?h1=9o4H0c7?M7><2.:<>4>6:&213<6im1bj54?::ke=?6=3f;>=7>5;|`23=<72:0;6=u+17`951g<@8k?7E?64:&246<f3-;>:7?nd:ke<?6=3`l26=44o072>5<<uk;<;7>53;294~"6>k0:8l5G1`68L4?33-;;?7?9;%362?7fm2cm47>5;hd:>5<<g8?:6=44}c342?6=;3:1<v*>6c820d=O9h>0D<7;;%337?g<,8?=6<oj;hd;>5<<ao31<75`14394?=zj82<6=4mc;294~"6>k0:945G1`68L4?33S936nu8:98e>45=990:87?>:e8`>`<6:3h1qc;<:89m11<>3gi96=5ae583?!`52o>0(k=5f59'bg<33-lh695+fe87?!`b2=1/jk4;;%334?2<,8::695+11090>"68=0?7)??5;68 4612=1/==954:&24=<33-;;57:4$02b>1=#99h186*>0b87?!77l3>0(<>j:59'55`=<2.:==4;;%325?2<,8;9695+10190>"69=0?7)?>5;68 4712=1/=<954:&25=<33-;:57:4$03b>1=#98h186*>1b87?!76l3>0(<?j:59'54`=<2.:>=4;;%315?2<,889695+13190>"6:=0?7)?=5;68 4412=1/=?954:&26=<33-;957:4$00b>1=#9;h186*>2b87?!75l3>0(<<j:59'57`=<2.:?=4;;%305?2<,899695+12190>"6;=0?7)?<5;68 4512=1/=>954:&27=<33-;857:4$01b>1=#9:h186*>3b87?!74l3>0(<=j:59'56`=<2.:8=4;;%375?2<,8>9695+15190>"6<=087)?;5;18 42128?;7)?:e;35e>"6=o08m6*>6180e>"6>:08;6*>658223=#9?=1?6*>6980?!7f93;j<6*>a382e5=n9<k1<75f4383>>oa93:17d?:d;29?l202900e<;m:188m43d2900ek>50;9j=g<72-;>977n;o360?6<3`326=4+1479=d=i9<>1=65f9983>!72=33j7c?:4;08?l?0290/=8;59`9m502=;21b=4o50;&210<6101e=8:50:9j5<>=83.:984>989m502=921b=4950;&210<6101e=8:52:9j5<0=83.:984>989m502=;21dnl4?:%361?d>3g;>87>4;n`;>5<#9<?1n45a14695>=hj?0;6)?:5;`:?k72<3807bl::18'503=j01e=8:53:9lf1<72-;>97l6;o360?2<3fh86=4+1479f<=i9<>1965`b383>!72=3h27c?:4;48?jd6290/=8;5b89m502=?21dn=4?:%361?d>3g;>8764;nce>5<#9<?1n45a1469=>=hil0;6)?:5;`:?k72<3k07bok:18'503=j01e=8:5b:9leg<72-;>97l6;o360?e<3fkj6=4+1479f<=i9<>1h65`a883>!72=3h27c?:4;g8?jg?290/=8;5b89m502=n21dm:4?:%361?d>3g;>87??;:mb2?6=,8?>6o74n077>47<3fk>6=4+1479f<=i9<>1=?54o`694?"6=<0i56`>55827>=hi:0;6)?:5;`:?k72<3;?76an2;29 4322k30b<;;:078?je6290/=8;5b89m502=9?10cn>50;&210<e12d:994>7:9lfc<72-;>97l6;o360?7?32eii7>5$076>g?<f8??6<74;n`g>5<#9<?1n45a14695d=<gki1<7*>548a=>h6==0:n65`bc83>!72=3h27c?:4;3`?>ie?3:1(<;::c;8j43328n07bol:18'503=j01e=8:51d98kd7=83.:984m9:l211<6n21b=h4?:%361?7c3g;>87>4;h3`>5<#9<?1=i5a14695>=n9k0;6)?:5;3g?k72<3807d?n:18'503=9m1e=8:53:9j62<72-;>97?k;o360?2<3`8=6=4+14795a=i9<>1965f2483>!72=3;o7c?:4;48?l43290/=8;51e9m502=?21b>>4?:%361?7c3g;>8764;h01>5<#9<?1=i5a1469=>=n:80;6)?:5;3g?k72<3k07d<?:18'503=9m1e=8:5b:9j5c<72-;>97?k;o360?e<3`;26=4+14795a=i9<>1h65f2e83>!72=38h7c?:4;28?l4e290/=8;52b9m502=921b>l4?:%361?4d3g;>87<4;h0:>5<#9<?1>n5a14697>=n;?0;6)?:5;0`?k72<3>07d=::18'503=:j1e=8:55:9j71<72-;>97<l;o360?0<3`986=4+14796f=i9<>1;65f3383>!72=38h7c?:4;:8?l56290/=8;52b9m502=121b?=4?:%361?4d3g;>87o4;h0e>5<#9<?1>n5a1469f>=n:l0;6)?:5;0`?k72<3i07d<7:18'503=:j1e=8:5d:9j<c<72-;>976j;o360?6<3`2o6=4+1479<`=i9<>1=65f8c83>!72=32n7c?:4;08?l>f290/=8;58d9m502=;21b444?:%361?>b3g;>87:4;h:;>5<#9<?14h5a14691>=n0>0;6)?:5;:f?k72<3<07d69:18'503=0l1e=8:57:9j<0<72-;>976j;o360?><3`2?6=4+1479<`=i9<>1565f8283>!72=32n7c?:4;c8?l>5290/=8;58d9m502=j21b4=4?:%361?>b3g;>87m4;h5e>5<#9<?14h5a1469`>=n?l0;6)?:5;:f?k72<3o07d9k:18'503=0l1e=8:5f:9j3f<72-;>976j;o360?7732c<n7>5$076>=c<f8??6<?4;h5b>5<#9<?14h5a146957=<a>31<7*>548;a>h6==0:?65f7983>!72=32n7c?:4;37?>o0?3:1(<;::9g8j43328?07d79:18'503=0l1e=8:51798m<3=83.:9847e:l211<6?21b594?:%361?>b3g;>87?7;:k:7?6=,8?>65k4n077>4?<3`396=4+1479<`=i9<>1=l54i8394?"6=<03i6`>5582f>=n190;6)?:5;:f?k72<3;h76g7c;29 43221o0b<;;:0f8?l>6290/=8;58d9m502=9l10e:850;&210<?m2d:994>f:9la<<72-;>97k7;o360?6<3fo<6=4+1479a==i9<>1=65`e783>!72=3o37c?:4;08?jc2290/=8;5e99m502=;21bm=4?:%361??a3g;>87>4;h;f>5<#9<?15k5a14695>=n1m0;6)?:5;;e?k72<3807d7l:18'503=1o1e=8:53:9la`<72-;>97kk;o360?6<3foh6=4+1479aa=i9<>1=65`ec83>!72=3oo7c?:4;08?jcf290/=8;5ee9m502=;21dhn4?:%361?be3g;>87>4;nfb>5<#9<?1ho5a14695>=hl10;6)?:5;fa?k72<3807bj8:18'503=lk1e=8:53:9l`3<72-;>97jm;o360?2<3fn>6=4+1479`g=i9<>1965`d583>!72=3ni7c?:4;48?jb4290/=8;5dc9m502=?21dh?4?:%361?be3g;>8764;nf2>5<#9<?1ho5a1469=>=hl90;6)?:5;fa?k72<3k07bmi:18'503=lk1e=8:5b:9lga<72-;>97jm;o360?e<3fih6=4+1479`g=i9<>1h65`cc83>!72=3ni7c?:4;g8?jef290/=8;5dc9m502=n21do44?:%361?be3g;>87??;:m`<?6=,8?>6il4n077>47<3fi<6=4+1479`g=i9<>1=?54ob494?"6=<0on6`>55827>=hk<0;6)?:5;fa?k72<3;?76al4;29 4322mh0b<;;:078?jc4290/=8;5dc9m502=9?10ch<50;&210<cj2d:994>7:9la4<72-;>97jm;o360?7?32en<7>5$076>ad<f8??6<74;nfe>5<#9<?1ho5a14695d=<gmo1<7*>548gf>h6==0:n65`de83>!72=3ni7c?:4;3`?>ic13:1(<;::e`8j43328n07bmj:18'503=lk1e=8:51d98kf5=83.:984kb:l211<6n21b=4h50;&210<61l1e=8:50:9j5<b=83.:984>9d9m502=921b=4m50;&210<61l1e=8:52:9j5<d=83.:984>9d9m502=;21b:h4?:%361?0c3g;>87>4;h4`>5<#9<?1:i5a14695>=n>h0;6)?:5;4g?k72<3807d86:18'503=>m1e=8:53:9j2=<72-;>978k;o360?2<3`<<6=4+14792a=i9<>1965f6783>!72=3<o7c?:4;48?l02290/=8;56e9m502=?21b:94?:%361?0c3g;>8764;h40>5<#9<?1:i5a1469=>=n>;0;6)?:5;4g?k72<3k07d8>:18'503=>m1e=8:5b:9j1c<72-;>978k;o360?e<3`?n6=4+14792a=i9<>1h65f5e83>!72=3<o7c?:4;g8?l3d290/=8;56e9m502=n21b9o4?:%361?0c3g;>87??;:k6e?6=,8?>6;j4n077>47<3`?26=4+14792a=i9<>1=?54i4:94?"6=<0=h6`>55827>=n=>0;6)?:5;4g?k72<3;?76g:6;29 4322?n0b<;;:078?l12290/=8;56e9m502=9?10e::50;&210<1l2d:994>7:9j36<72-;>978k;o360?7?32c<>7>5$076>3b<f8??6<74;h52>5<#9<?1:i5a14695d=<a>:1<7*>5485`>h6==0:n65f6g83>!72=3<o7c?:4;3`?>o1j3:1(<;::7f8j43328n07d8?:18'503=>m1e=8:51d98m03=83.:9849d:l211<6n21vn<9n:18ag?6=8r.::o4>589K5d2<@83?7W=7:by4>=<a2891==4>4;32>a<d2l0:>7l5}o70><=i==027cm=:19ma1<73-l96k:4$g19b1=#nk0?7)hl:59'ba<33-ln695+fg87?!7783>0(<>>:59'554=<2.:<94;;%331?2<,8:=695+11590>"6810?7)??9;68 46f2=1/==l54:&24f<33-;;h7:4$02f>1=#99l186*>1187?!7693>0(<?=:59'545=<2.:=94;;%321?2<,8;=695+10590>"6910?7)?>9;68 47f2=1/=<l54:&25f<33-;:h7:4$03f>1=#98l186*>2187?!7593>0(<<=:59'575=<2.:>94;;%311?2<,88=695+13590>"6:10?7)?=9;68 44f2=1/=?l54:&26f<33-;9h7:4$00f>1=#9;l186*>3187?!7493>0(<==:59'565=<2.:?94;;%301?2<,89=695+12590>"6;10?7)?<9;68 45f2=1/=>l54:&27f<33-;8h7:4$01f>1=#9:l186*>4187?!7393>0(<:=:59'515=<2.:894<;%371?5<,8>=6<;?;%36a?71i2.:9k4<a:&225<4i2.::>4<7:&221<6>?1/=;953:&22=<43-;j=7?n0:&2e7<6i91b=8o50;9j07<722cm=7>5;h36`?6=3`><6=44i07a>5<<a8?h6=44ig294?=n1k0;6)?:5;;b?k72<3:07d76:18'503=1h1e=8:51:9j==<72-;>977n;o360?4<3`3<6=4+1479=d=i9<>1?65f18c94?"6=<0:545a14694>=n9021<7*>5482=<=i9<>1=65f18594?"6=<0:545a14696>=n90<1<7*>5482=<=i9<>1?65`b`83>!72=3h27c?:4;28?jd?290/=8;5b89m502=921dn;4?:%361?d>3g;>87<4;n`6>5<#9<?1n45a14697>=hj=0;6)?:5;`:?k72<3>07bl<:18'503=j01e=8:55:9lf7<72-;>97l6;o360?0<3fh:6=4+1479f<=i9<>1;65`b183>!72=3h27c?:4;:8?jga290/=8;5b89m502=121dmh4?:%361?d>3g;>87o4;ncg>5<#9<?1n45a1469f>=hik0;6)?:5;`:?k72<3i07bon:18'503=j01e=8:5d:9le<<72-;>97l6;o360?c<3fk36=4+1479f<=i9<>1j65`a683>!72=3h27c?:4;33?>if>3:1(<;::c;8j43328;07bo::18'503=j01e=8:51398kd2=83.:984m9:l211<6;21dm>4?:%361?d>3g;>87?;;:mb6?6=,8?>6o74n077>43<3fi:6=4+1479f<=i9<>1=;54ob294?"6=<0i56`>55823>=hjo0;6)?:5;`:?k72<3;376ame;29 4322k30b<;;:0;8?jdc290/=8;5b89m502=9h10com50;&210<e12d:994>b:9lfg<72-;>97l6;o360?7d32ei;7>5$076>g?<f8??6<j4;nc`>5<#9<?1n45a14695`=<gh;1<7*>548a=>h6==0:j65f1d83>!72=3;o7c?:4;28?l7d290/=8;51e9m502=921b=o4?:%361?7c3g;>87<4;h3b>5<#9<?1=i5a14697>=n:>0;6)?:5;3g?k72<3>07d<9:18'503=9m1e=8:55:9j60<72-;>97?k;o360?0<3`8?6=4+14795a=i9<>1;65f2283>!72=3;o7c?:4;:8?l45290/=8;51e9m502=121b><4?:%361?7c3g;>87o4;h03>5<#9<?1=i5a1469f>=n9o0;6)?:5;3g?k72<3i07d?6:18'503=9m1e=8:5d:9j6a<72-;>97<l;o360?6<3`8i6=4+14796f=i9<>1=65f2`83>!72=38h7c?:4;08?l4>290/=8;52b9m502=;21b?;4?:%361?4d3g;>87:4;h16>5<#9<?1>n5a14691>=n;=0;6)?:5;0`?k72<3<07d=<:18'503=:j1e=8:57:9j77<72-;>97<l;o360?><3`9:6=4+14796f=i9<>1565f3183>!72=38h7c?:4;c8?l4a290/=8;52b9m502=j21b>h4?:%361?4d3g;>87m4;h0;>5<#9<?1>n5a1469`>=n0o0;6)?:5;:f?k72<3:07d6k:18'503=0l1e=8:51:9j<g<72-;>976j;o360?4<3`2j6=4+1479<`=i9<>1?65f8883>!72=32n7c?:4;68?l>?290/=8;58d9m502==21b4:4?:%361?>b3g;>8784;h:5>5<#9<?14h5a14693>=n0<0;6)?:5;:f?k72<3207d6;:18'503=0l1e=8:59:9j<6<72-;>976j;o360?g<3`296=4+1479<`=i9<>1n65f8183>!72=32n7c?:4;a8?l1a290/=8;58d9m502=l21b;h4?:%361?>b3g;>87k4;h5g>5<#9<?14h5a1469b>=n?j0;6)?:5;:f?k72<3;;76g8b;29 43221o0b<;;:038?l1f290/=8;58d9m502=9;10e:750;&210<?m2d:994>3:9j3=<72-;>976j;o360?7332c<;7>5$076>=c<f8??6<;4;h;5>5<#9<?14h5a146953=<a0?1<7*>548;a>h6==0:;65f9583>!72=32n7c?:4;3;?>o>;3:1(<;::9g8j43328307d7=:18'503=0l1e=8:51`98m<7=83.:9847e:l211<6j21b5=4?:%361?>b3g;>87?l;:k;g?6=,8?>65k4n077>4b<3`2:6=4+1479<`=i9<>1=h54i6494?"6=<03i6`>5582b>=hm00;6)?:5;g;?k72<3:07bk8:18'503=m11e=8:51:9la3<72-;>97k7;o360?4<3fo>6=4+1479a==i9<>1?65fa183>!72=33m7c?:4;28?l?b290/=8;59g9m502=921b5i4?:%361??a3g;>87<4;h;`>5<#9<?15k5a14697>=hml0;6)?:5;gg?k72<3:07bkl:18'503=mm1e=8:51:9lag<72-;>97kk;o360?4<3foj6=4+1479aa=i9<>1?65`db83>!72=3ni7c?:4;28?jbf290/=8;5dc9m502=921dh54?:%361?be3g;>87<4;nf4>5<#9<?1ho5a14697>=hl?0;6)?:5;fa?k72<3>07bj::18'503=lk1e=8:55:9l`1<72-;>97jm;o360?0<3fn86=4+1479`g=i9<>1;65`d383>!72=3ni7c?:4;:8?jb6290/=8;5dc9m502=121dh=4?:%361?be3g;>87o4;nae>5<#9<?1ho5a1469f>=hkm0;6)?:5;fa?k72<3i07bml:18'503=lk1e=8:5d:9lgg<72-;>97jm;o360?c<3fij6=4+1479`g=i9<>1j65`c883>!72=3ni7c?:4;33?>id03:1(<;::e`8j43328;07bm8:18'503=lk1e=8:51398kf0=83.:984kb:l211<6;21do84?:%361?be3g;>87?;;:m`0?6=,8?>6il4n077>43<3fo86=4+1479`g=i9<>1=;54od094?"6=<0on6`>55823>=hm80;6)?:5;fa?k72<3;376aj0;29 4322mh0b<;;:0;8?jba290/=8;5dc9m502=9h10cik50;&210<cj2d:994>b:9l`a<72-;>97jm;o360?7d32eo57>5$076>ad<f8??6<j4;naf>5<#9<?1ho5a14695`=<gj91<7*>548gf>h6==0:j65f18d94?"6=<0:5h5a14694>=n90n1<7*>5482=`=i9<>1=65f18a94?"6=<0:5h5a14696>=n90h1<7*>5482=`=i9<>1?65f6d83>!72=3<o7c?:4;28?l0d290/=8;56e9m502=921b:l4?:%361?0c3g;>87<4;h4:>5<#9<?1:i5a14697>=n>10;6)?:5;4g?k72<3>07d88:18'503=>m1e=8:55:9j23<72-;>978k;o360?0<3`<>6=4+14792a=i9<>1;65f6583>!72=3<o7c?:4;:8?l04290/=8;56e9m502=121b:?4?:%361?0c3g;>87o4;h42>5<#9<?1:i5a1469f>=n=o0;6)?:5;4g?k72<3i07d;j:18'503=>m1e=8:5d:9j1a<72-;>978k;o360?c<3`?h6=4+14792a=i9<>1j65f5c83>!72=3<o7c?:4;33?>o2i3:1(<;::7f8j43328;07d;6:18'503=>m1e=8:51398m0>=83.:9849d:l211<6;21b9:4?:%361?0c3g;>87?;;:k62?6=,8?>6;j4n077>43<3`=>6=4+14792a=i9<>1=;54i6694?"6=<0=h6`>55823>=n?:0;6)?:5;4g?k72<3;376g82;29 4322?n0b<;;:0;8?l16290/=8;56e9m502=9h10e:>50;&210<1l2d:994>b:9j2c<72-;>978k;o360?7d32c=n7>5$076>3b<f8??6<j4;h43>5<#9<?1:i5a14695`=<a<?1<7*>5485`>h6==0:j65rs06f>5<>lr7:m84i6:?2<2<5827:4:4>f:?2<2<6127:4:4=f:?2<2<5m27:4:4=8:?2<2<1m27:4:49c:?2<2<1i27:4:499:?2<2<1027:4:497:?2<2<1>27:4:495:?2<2<1<27:4:493:?2<2<1:27:4:491:?2<2<2n27:4:4:e:?2<2<2l27:4:4:c:?2<2<2j27:4:4:a:?2<2<2127:4:4:8:?2<2<2?27:4:4:6:?2<2<0=27:4:484:?2<2<?n27:4:47d:?2<2<?j27:4:47a:?2<2<?127:4:478:?2<2<??27:4:476:?2<2<?=27:4:474:?2<2<?;27:4:472:?2<2<?827:4:48f:?2<2<0m27:4:48d:?2<2<0k27:4:48b:?2<2<0i27:4:489:?2<2<0027:4:487:?2<2<>>27:4:465:?2<2<><27:4:463:?2<2<>:27:4:461:?2<2<>827:4:47c:?2<2<?927:4:486:?2<2<>j27:4:469:?2<2<>027:4:467:?2<2<f827:4:46e:?2<2<>l27:4:46c:?2<2<61o16=59518f894>0283h70?77;3:f>;60>0:9l52195950d<582<6<;l;<3;3?72l27:;l4=0:?23d<6n27:;l4>9:?23d<5n27:;l4=e:?23d<5027:;l49e:?23d<1k27:;l49a:?23d<1127:;l498:?23d<1?27:;l496:?23d<1=27:;l494:?23d<1;27:;l492:?23d<1927:;l4:f:?23d<2m27:;l4:d:?23d<2k27:;l4:b:?23d<2i27:;l4:9:?23d<2027:;l4:7:?23d<2>27:;l485:?23d<0<27:;l47f:?23d<?l27:;l47b:?23d<?i27:;l479:?23d<?027:;l477:?23d<?>27:;l475:?23d<?<27:;l473:?23d<?:27:;l470:?23d<0n27:;l48e:?23d<0l27:;l48c:?23d<0j27:;l48a:?23d<0127:;l488:?23d<0?27:;l466:?23d<>=27:;l464:?23d<>;27:;l462:?23d<>927:;l460:?23d<?k27:;l471:?23d<0>27:;l46b:?23d<>127:;l468:?23d<>?27:;l4n0:?23d<>m27:;l46d:?23d<>k27:;l4>9g9>52g=90n01<9n:0;`?870i3;2n63>7`821d=:9>k1=8l4=05b>43d34;<m7?:d:p5`3=838pR<k:;<35g?7292wx=h850;0xZ4c134;=h7?:1:p5`1=838pR<k8;<35a?7292wx=h650;0xZ4c?34;=j7?:1:p5`?=838pR<k6;<344?7292wx=ho50;0xZ4cf34;<=7?:1:p5`d=838pR<km;<346?7292wx=hj50;0xZ4cc34;<?7?:1:p5``=83>pR<ki;<341?5f34;<57h7;<34<?`?3ty:ho4?:5y]5ad<58=>6>74=0:4>11<58=j6994}r3fa?6=;rT:ih521659b==:9><1j55rs0fb>5<4sW;om63>86876>;6?h0?>6s|1b294?5|V8i;70?77;13?870i39;7p}>c583>6}Y9j>01<68:238941f2:;0q~?l5;297~X6k<16=595339>52g=;;1v<m9:180[7d>27:4:4<3:?23d<4;2wx=n950;1xZ4e034;3;7=;;<34e?533ty:o54?:2y]5f><582<6>;4=05b>63<uz;h57>53z\2g<=:91=1?;5216c973=z{8ij6=4<{_3`e>;60>09563>7`81=>{t9jh1<7=t^0aa?87??38j70?8a;0b?xu6kj0;6>uQ1ba894>02;h01<9n:3`8yv7d93:1?vP>c09>5=1=:m16=:o52e9~w4e4290?wS?l3:?230<2:27:;44i9:?23=<a12wx=im50;1xZ4bd34;3;7;:;<34e?323ty:hi4?:2y]5ab<582<6;>4=05b>36<uz;oi7>53z\2``=:91=1:o5216c92g=z{8nm6=4<{_3gb>;60>0=j63>7`85b>{t9l:1<7=t^0g3?87??3=;70?8a;53?xu6m80;6>uQ1d3894>02>;01<9n:638yv7b:3:1?vP>e39>5=1=?;16=:o5739~w4c32908wS?j4:?2<2<0;27:;l483:p5g5=839pR<l<;<3;3?4634;<m7<>;|q2f2<72:qU=o94=0:4>74<58=j6?<4}r3a<?6=;rT:n552195966=:9>k1>>5rs0`:>5<4sW;i563>86810>;6?h0986s|1cc94?5|V8hj70?77;06?870i38>7p}>bc83>6}Y9kh01<68:348941f2;<0q~?mc;297~X6jj16=595269>52g=:>1v<lk:180[7el27:4:4>a:?23d<6i2wx=ok50;1xZ4db34;3;7?m;<34e?7e3ty:nk4?:2y]5g`<582<6<m4=05b>4e<uz;i87>53z\2f1=:91=1=h5216c95`=z{8h=6=4<{_3a2>;6?>0m563>778e=>{t9o?1<77t^0d6?87??3;2m63>8682===:91=1=494=0:4>4?134;<m7?6a:?23d<61116=:o51858941f283=7p}>7583><}:9>?1=864=04`>c><58<o6k64=04f>c><58<m6k64=053>c><58=:6k64=051>c><58=86k64}r3:7?6=:r7:;44>509>5=1=n81v<69:18187003;>=63>7`8e5>{t9081<7<t=054>43634;3;7h?;|q2<0<72;q6=:851438941f2o:0q~?7a;296~;6>j0mm63>868`7>{t91h1<7<t=04g>cg<582<6nk4}r3;g?6=:r7::h4ia:?2<2<c12wx=5j50;0x940a2ok01<68:ef8yv7?m3:1>v3>718ee>;60>0oi6s|19d94?4|58=:6ko4=0:4>a`<uz;2<7>52z?237<ai27:4:4j0:p5<7=838p1<9<:gc894>02l;0q~?8d;296~;6>j0m563>7`8`7>{t9>o1<7<t=04g>c?<58=j6nk4}r34b?6=:r7::h4i9:?23d<c12wx=5>50;0x940a2o301<9n:ef8yv7?93:1>v3>718e=>;6?h0oi6s|19094?4|58=:6k74=05b>a`<uz;3?7>52z?237<a127:;l4j0:p5=2=838p1<9<:g;8941f2l;0qp`>f083>4}O90>0qc?i2;295~N61=1vb<h<:182M7><2we=k:50;3xL4?33td:j84?:0yK5<2<ug;m:7>51zJ2=1=zf8l<6=4>{I3:0>{i9o21<7?tH0;7?xh6n00;6<uG1868yk7ai3:1=vF>959~j4`e290:wE?64:m5ce=83;pD<7;;|l2ba<728qC=4:4}o3ea?6=9rB:595rn0de>5<6sA;286sa21294?7|@83?7p`=0083>4}O90>0qc<?2;295~N61=1vb?><:182M7><2we>=:50;3xL4?33td9<84?:0yK5<2<ug8;:7>51zJ2=1=zf;:<6=4>{I3:0>{i:921<7?tH0;7?xh5800;6<uG1868yk47i3:1=vF>959~j76e290:wE?64:m65e=83;pD<7;;|l14a<728qC=4:4}o03a?6=9rB:595rn32e>5<6sA;286sa20294?7|@83?7p`=1083>4}O90>0qc<>2;295~N61=1vb??<:182M7><2we><:50;3xL4?33td9=84?:0yK5<2<ug8::7>51zJ2=1=zf;;<6=4>{I3:0>{i:821<7?tH0;7?xh5900;6<uG1868yk46i3:1=vF>959~j77e290:wE?64:m64e=83;pD<7;;|l15a<728qC=4:4}o02a?6=9rB:595rn33e>5<6sA;286sa23294?7|@83?7p`=2083>4}O90>0qc<=2;295~N61=1vb?<<:182M7><2we>?:50;3xL4?33td9>84?:0yK5<2<ug89:7>51zJ2=1=zf;8<6=4>{I3:0>{i:;21<7?tH0;7?xh5:00;6<uG1868yk45i3:1=vF>959~j74e290:wE?64:m67e=83;pD<7;;|l16a<728qC=4:4}o01a?6=9rB:595rn30e>5<6sA;286sa22294?7|@83?7p`=3083>4}O90>0qc<<2;295~N61=1vb?=<:182M7><2wvqpNOCz043?bb=m8ho=sO@Cy3yEFWstJK
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.sym
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.sym	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.sym	(revision 115)
@@ -0,0 +1,36 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="mem_4k8">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2014-3-3T7:17:14</timestamp>
+    <pin polarity="Input" x="0" y="80" name="addra[11:0]" />
+    <pin polarity="Input" x="0" y="112" name="dina[7:0]" />
+    <pin polarity="Input" x="0" y="144" name="ena" />
+    <pin polarity="Input" x="0" y="208" name="wea[0:0]" />
+    <pin polarity="Input" x="0" y="272" name="clka" />
+    <pin polarity="Input" x="0" y="432" name="addrb[11:0]" />
+    <pin polarity="Input" x="0" y="496" name="enb" />
+    <pin polarity="Input" x="0" y="624" name="clkb" />
+    <pin polarity="Output" x="576" y="368" name="doutb[7:0]" />
+    <graph>
+        <text style="fontsize:40;fontname:Arial" x="32" y="32">mem_4k8</text>
+        <rect width="512" x="32" y="32" height="1344" />
+        <line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[11:0]" />
+        <line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin dina[7:0]" />
+        <line x2="32" y1="144" y2="144" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin ena" />
+        <line x2="32" y1="208" y2="208" style="linewidth:W" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin wea[0:0]" />
+        <line x2="32" y1="272" y2="272" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
+        <line x2="32" y1="432" y2="432" style="linewidth:W" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin addrb[11:0]" />
+        <line x2="32" y1="496" y2="496" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="496" type="pin enb" />
+        <line x2="32" y1="624" y2="624" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="624" type="pin clkb" />
+        <line x2="544" y1="368" y2="368" style="linewidth:W" x1="576" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin doutb[7:0]" />
+    </graph>
+</symbol>
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.vhd	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.vhd	(revision 115)
@@ -0,0 +1,152 @@
+--------------------------------------------------------------------------------
+--    This file is owned and controlled by Xilinx and must be used solely     --
+--    for design, simulation, implementation and creation of design files     --
+--    limited to Xilinx devices or technologies. Use with non-Xilinx          --
+--    devices or technologies is expressly prohibited and immediately         --
+--    terminates your license.                                                --
+--                                                                            --
+--    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
+--    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
+--    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
+--    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
+--    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
+--    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
+--    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
+--    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
+--    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
+--    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
+--    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
+--    PARTICULAR PURPOSE.                                                     --
+--                                                                            --
+--    Xilinx products are not intended for use in life support appliances,    --
+--    devices, or systems.  Use in such applications are expressly            --
+--    prohibited.                                                             --
+--                                                                            --
+--    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
+--    All rights reserved.                                                    --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file mem_4k8.vhd when simulating
+-- the core, mem_4k8. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY mem_4k8 IS
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    enb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END mem_4k8;
+
+ARCHITECTURE mem_4k8_a OF mem_4k8 IS
+-- synthesis translate_off
+COMPONENT wrapped_mem_4k8
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    enb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END COMPONENT;
+
+-- Configuration specification
+  FOR ALL : wrapped_mem_4k8 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral)
+    GENERIC MAP (
+      c_addra_width => 12,
+      c_addrb_width => 12,
+      c_algorithm => 1,
+      c_axi_id_width => 4,
+      c_axi_slave_type => 0,
+      c_axi_type => 1,
+      c_byte_size => 8,
+      c_common_clk => 0,
+      c_default_data => "0",
+      c_disable_warn_bhv_coll => 0,
+      c_disable_warn_bhv_range => 0,
+      c_family => "spartan6",
+      c_has_axi_id => 0,
+      c_has_ena => 1,
+      c_has_enb => 1,
+      c_has_injecterr => 0,
+      c_has_mem_output_regs_a => 0,
+      c_has_mem_output_regs_b => 0,
+      c_has_mux_output_regs_a => 0,
+      c_has_mux_output_regs_b => 0,
+      c_has_regcea => 0,
+      c_has_regceb => 0,
+      c_has_rsta => 0,
+      c_has_rstb => 0,
+      c_has_softecc_input_regs_a => 0,
+      c_has_softecc_output_regs_b => 0,
+      c_init_file_name => "no_coe_file_loaded",
+      c_inita_val => "0",
+      c_initb_val => "0",
+      c_interface_type => 0,
+      c_load_init_file => 0,
+      c_mem_type => 1,
+      c_mux_pipeline_stages => 0,
+      c_prim_type => 1,
+      c_read_depth_a => 4096,
+      c_read_depth_b => 4096,
+      c_read_width_a => 8,
+      c_read_width_b => 8,
+      c_rst_priority_a => "CE",
+      c_rst_priority_b => "CE",
+      c_rst_type => "SYNC",
+      c_rstram_a => 0,
+      c_rstram_b => 0,
+      c_sim_collision_check => "ALL",
+      c_use_byte_wea => 1,
+      c_use_byte_web => 1,
+      c_use_default_data => 0,
+      c_use_ecc => 0,
+      c_use_softecc => 0,
+      c_wea_width => 1,
+      c_web_width => 1,
+      c_write_depth_a => 4096,
+      c_write_depth_b => 4096,
+      c_write_mode_a => "WRITE_FIRST",
+      c_write_mode_b => "WRITE_FIRST",
+      c_write_width_a => 8,
+      c_write_width_b => 8,
+      c_xdevicefamily => "spartan6"
+    );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_mem_4k8
+  PORT MAP (
+    clka => clka,
+    ena => ena,
+    wea => wea,
+    addra => addra,
+    dina => dina,
+    clkb => clkb,
+    enb => enb,
+    addrb => addrb,
+    doutb => doutb
+  );
+-- synthesis translate_on
+
+END mem_4k8_a;
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.vho
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.vho	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.vho	(revision 115)
@@ -0,0 +1,89 @@
+--------------------------------------------------------------------------------
+--    This file is owned and controlled by Xilinx and must be used solely     --
+--    for design, simulation, implementation and creation of design files     --
+--    limited to Xilinx devices or technologies. Use with non-Xilinx          --
+--    devices or technologies is expressly prohibited and immediately         --
+--    terminates your license.                                                --
+--                                                                            --
+--    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
+--    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
+--    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
+--    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
+--    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
+--    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
+--    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
+--    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
+--    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
+--    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
+--    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
+--    PARTICULAR PURPOSE.                                                     --
+--                                                                            --
+--    Xilinx products are not intended for use in life support appliances,    --
+--    devices, or systems.  Use in such applications are expressly            --
+--    prohibited.                                                             --
+--                                                                            --
+--    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
+--    All rights reserved.                                                    --
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+--    Generated from core with identifier: xilinx.com:ip:blk_mem_gen:6.2      --
+--                                                                            --
+--    The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port    --
+--    Block Memory and Single Port Block Memory LogiCOREs, but is not a       --
+--    direct drop-in replacement.  It should be used in all new Xilinx        --
+--    designs. The core supports RAM and ROM functions over a wide range of   --
+--    widths and depths. Use this core to generate block memories with        --
+--    symmetric or asymmetric read and write port widths, as well as cores    --
+--    which can perform simultaneous write operations to separate             --
+--    locations, and simultaneous read operations from the same location.     --
+--    For more information on differences in interface and feature support    --
+--    between this core and the Dual Port Block Memory and Single Port        --
+--    Block Memory LogiCOREs, please consult the data sheet.                  --
+--------------------------------------------------------------------------------
+
+-- Interfaces:
+--    AXI_SLAVE_S_AXI
+--    AXILite_SLAVE_S_AXI
+
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT mem_4k8
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    enb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : mem_4k8
+  PORT MAP (
+    clka => clka,
+    ena => ena,
+    wea => wea,
+    addra => addra,
+    dina => dina,
+    clkb => clkb,
+    enb => enb,
+    addrb => addrb,
+    doutb => doutb
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file mem_4k8.vhd when simulating
+-- the core, mem_4k8. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.xco
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.xco	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.xco	(revision 115)
@@ -0,0 +1,105 @@
+##############################################################
+#
+# Xilinx Core Generator version 13.3
+# Date: Mon Mar 03 07:15:50 2014
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:blk_mem_gen:6.2
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2
+# END Select
+# BEGIN Parameters
+CSET additional_inputs_for_power_estimation=false
+CSET algorithm=Minimum_Area
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
+CSET byte_size=8
+CSET coe_file=no_coe_file_loaded
+CSET collision_warnings=ALL
+CSET component_name=mem_4k8
+CSET disable_collision_warnings=false
+CSET disable_out_of_range_warnings=false
+CSET ecc=false
+CSET ecctype=No_ECC
+CSET enable_a=Use_ENA_Pin
+CSET enable_b=Use_ENB_Pin
+CSET error_injection_type=Single_Bit_Error_Injection
+CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
+CSET load_init_file=false
+CSET memory_type=Simple_Dual_Port_RAM
+CSET operating_mode_a=WRITE_FIRST
+CSET operating_mode_b=WRITE_FIRST
+CSET output_reset_value_a=0
+CSET output_reset_value_b=0
+CSET pipeline_stages=0
+CSET port_a_clock=100
+CSET port_a_enable_rate=100
+CSET port_a_write_rate=50
+CSET port_b_clock=100
+CSET port_b_enable_rate=100
+CSET port_b_write_rate=0
+CSET primitive=8kx2
+CSET read_width_a=8
+CSET read_width_b=8
+CSET register_porta_input_of_softecc=false
+CSET register_porta_output_of_memory_core=false
+CSET register_porta_output_of_memory_primitives=false
+CSET register_portb_output_of_memory_core=false
+CSET register_portb_output_of_memory_primitives=false
+CSET register_portb_output_of_softecc=false
+CSET remaining_memory_locations=0
+CSET reset_memory_latch_a=false
+CSET reset_memory_latch_b=false
+CSET reset_priority_a=CE
+CSET reset_priority_b=CE
+CSET reset_type=SYNC
+CSET softecc=false
+CSET use_axi_id=false
+CSET use_byte_write_enable=true
+CSET use_error_injection_pins=false
+CSET use_regcea_pin=false
+CSET use_regceb_pin=false
+CSET use_rsta_pin=false
+CSET use_rstb_pin=false
+CSET write_depth_a=4096
+CSET write_width_a=8
+CSET write_width_b=8
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2011-03-11T08:24:14.000Z
+# END Extra information
+GENERATE
+# CRC: 7d184c03
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.xise
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.xise	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.xise	(revision 115)
@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="mem_4k8.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="mem_4k8.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|mem_4k8|mem_4k8_a" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="mem_4k8.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mem_4k8" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="mem_4k8" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-03-03T08:17:20" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C0D96C8DEC5F479F8D5451528E624BEE" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_flist.txt
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_flist.txt	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_flist.txt	(revision 115)
@@ -0,0 +1,25 @@
+# Output products list for <mem_4k8>
+blk_mem_gen_ds512.pdf
+blk_mem_gen_v6_2_readme.txt
+mem_4k8.asy
+mem_4k8.gise
+mem_4k8.ngc
+mem_4k8.sym
+mem_4k8.vhd
+mem_4k8.vho
+mem_4k8.xco
+mem_4k8.xise
+mem_4k8_flist.txt
+mem_4k8_ste\example_design\bmg_wrapper.vhd
+mem_4k8_ste\example_design\mem_4k8_top.ucf
+mem_4k8_ste\example_design\mem_4k8_top.vhd
+mem_4k8_ste\example_design\mem_4k8_top.xdc
+mem_4k8_ste\implement\implement.bat
+mem_4k8_ste\implement\implement.sh
+mem_4k8_ste\implement\planAhead_rdn.bat
+mem_4k8_ste\implement\planAhead_rdn.sh
+mem_4k8_ste\implement\planAhead_rdn.tcl
+mem_4k8_ste\implement\xst.prj
+mem_4k8_ste\implement\xst.scr
+mem_4k8_xmdf.tcl
+summary.log
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/bmg_wrapper.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/bmg_wrapper.vhd	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/bmg_wrapper.vhd	(revision 115)
@@ -0,0 +1,269 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v6.2 Core - Top-level wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_wrapper.vhd
+--
+-- Description:
+--   This is the top-level BMG wrapper (over BMG core).
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+-- Configured Core Parameter Values:
+-- (Refer to the SIM Parameters table in the datasheet for more information on
+-- the these parameters.)
+--    C_FAMILY                    :  spartan6 
+--    C_XDEVICEFAMILY             :  spartan6 
+--    C_INTERFACE_TYPE            :  0 
+--    C_AXI_TYPE                  :  1 
+--    C_AXI_SLAVE_TYPE            :  0 
+--    C_AXI_ID_WIDTH              :  4 
+--    C_MEM_TYPE                  :  1 
+--    C_BYTE_SIZE                 :  8 
+--    C_ALGORITHM                 :  1 
+--    C_PRIM_TYPE                 :  1 
+--    C_LOAD_INIT_FILE            :  0 
+--    C_INIT_FILE_NAME            :  no_coe_file_loaded 
+--    C_USE_DEFAULT_DATA          :  0 
+--    C_DEFAULT_DATA              :  0 
+--    C_RST_TYPE                  :  SYNC 
+--    C_HAS_RSTA                  :  0 
+--    C_RST_PRIORITY_A            :  CE 
+--    C_RSTRAM_A                  :  0 
+--    C_INITA_VAL                 :  0 
+--    C_HAS_ENA                   :  1 
+--    C_HAS_REGCEA                :  0 
+--    C_USE_BYTE_WEA              :  1 
+--    C_WEA_WIDTH                 :  1 
+--    C_WRITE_MODE_A              :  WRITE_FIRST 
+--    C_WRITE_WIDTH_A             :  8 
+--    C_READ_WIDTH_A              :  8 
+--    C_WRITE_DEPTH_A             :  4096 
+--    C_READ_DEPTH_A              :  4096 
+--    C_ADDRA_WIDTH               :  12 
+--    C_HAS_RSTB                  :  0 
+--    C_RST_PRIORITY_B            :  CE 
+--    C_RSTRAM_B                  :  0 
+--    C_INITB_VAL                 :  0 
+--    C_HAS_ENB                   :  1 
+--    C_HAS_REGCEB                :  0 
+--    C_USE_BYTE_WEB              :  1 
+--    C_WEB_WIDTH                 :  1 
+--    C_WRITE_MODE_B              :  WRITE_FIRST 
+--    C_WRITE_WIDTH_B             :  8 
+--    C_READ_WIDTH_B              :  8 
+--    C_WRITE_DEPTH_B             :  4096 
+--    C_READ_DEPTH_B              :  4096 
+--    C_ADDRB_WIDTH               :  12 
+--    C_HAS_MEM_OUTPUT_REGS_A     :  0 
+--    C_HAS_MEM_OUTPUT_REGS_B     :  0 
+--    C_HAS_MUX_OUTPUT_REGS_A     :  0 
+--    C_HAS_MUX_OUTPUT_REGS_B     :  0 
+--    C_HAS_SOFTECC_INPUT_REGS_A  :  0 
+--    C_HAS_SOFTECC_OUTPUT_REGS_B :  0 
+--    C_MUX_PIPELINE_STAGES       :  0 
+--    C_USE_ECC                   :  0 
+--    C_USE_SOFTECC               :  0 
+--    C_HAS_INJECTERR             :  0 
+--    C_SIM_COLLISION_CHECK       :  ALL 
+--    C_COMMON_CLK                :  0 
+--    C_DISABLE_WARN_BHV_COLL     :  0 
+--    C_DISABLE_WARN_BHV_RANGE    :  0 
+
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY bmg_wrapper IS
+  PORT (
+    --Port A
+    CLKA       : IN STD_LOGIC;
+    RSTA       : IN STD_LOGIC;  --opt port
+    ENA        : IN STD_LOGIC;  --optional port
+    REGCEA     : IN STD_LOGIC;  --optional port
+    WEA        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRA      : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    DINA       : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    DOUTA      : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+    --Port B
+    CLKB       : IN STD_LOGIC;
+    RSTB       : IN STD_LOGIC;  --opt port
+    ENB        : IN STD_LOGIC;  --optional port
+    REGCEB     : IN STD_LOGIC;  --optional port
+    WEB        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRB      : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    DINB       : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    DOUTB      : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+    --ECC
+    INJECTSBITERR  : IN STD_LOGIC; --optional port
+    INJECTDBITERR  : IN STD_LOGIC; --optional port
+    SBITERR        : OUT STD_LOGIC; --optional port
+    DBITERR        : OUT STD_LOGIC; --optional port
+    RDADDRECC      : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --optional port
+ -- AXI BMG Input and Output Port Declarations
+
+    -- AXI Global Signals
+    S_ACLK                         : IN  STD_LOGIC;
+    S_AXI_AWID                     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+    S_AXI_AWADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXI_AWLEN                    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXI_AWSIZE                   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
+    S_AXI_AWBURST                  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_AWVALID                  : IN  STD_LOGIC;
+    S_AXI_AWREADY                  : OUT STD_LOGIC;
+    S_AXI_WDATA                    : IN  STD_LOGIC_VECTOR(7  DOWNTO 0);
+    S_AXI_WSTRB                    : IN  STD_LOGIC_VECTOR(0  DOWNTO 0);
+    S_AXI_WLAST                    : IN  STD_LOGIC;
+    S_AXI_WVALID                   : IN  STD_LOGIC;
+    S_AXI_WREADY                   : OUT STD_LOGIC;
+    S_AXI_BID                      : OUT STD_LOGIC_VECTOR(3  DOWNTO 0):= (OTHERS => '0');
+    S_AXI_BRESP                    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_BVALID                   : OUT STD_LOGIC;
+    S_AXI_BREADY                   : IN  STD_LOGIC;
+
+    -- AXI Full/Lite Slave Read (Write side)
+    S_AXI_ARID                     : IN  STD_LOGIC_VECTOR(3  DOWNTO 0);
+    S_AXI_ARADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXI_ARLEN                    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXI_ARSIZE                   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
+    S_AXI_ARBURST                  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_ARVALID                  : IN  STD_LOGIC;
+    S_AXI_ARREADY                  : OUT STD_LOGIC;
+    S_AXI_RID                      : OUT STD_LOGIC_VECTOR(3  DOWNTO 0):= (OTHERS => '0');
+    S_AXI_RDATA                    : OUT STD_LOGIC_VECTOR(7  DOWNTO 0);
+    S_AXI_RRESP                    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_RLAST                    : OUT STD_LOGIC;
+    S_AXI_RVALID                   : OUT STD_LOGIC;
+    S_AXI_RREADY                   : IN  STD_LOGIC;
+
+    -- AXI Full/Lite Sideband Signals
+    S_AXI_INJECTSBITERR            : IN  STD_LOGIC;
+    S_AXI_INJECTDBITERR            : IN  STD_LOGIC;
+    S_AXI_SBITERR                  : OUT STD_LOGIC;
+    S_AXI_DBITERR                  : OUT STD_LOGIC;
+    S_AXI_RDADDRECC                : OUT STD_LOGIC_VECTOR(11  DOWNTO 0);
+    S_ARESETN                      : IN  STD_LOGIC
+
+
+  );
+
+END bmg_wrapper;
+
+
+ARCHITECTURE xilinx OF bmg_wrapper IS
+
+  COMPONENT mem_4k8_top IS
+  PORT (
+      --Port A
+    ENA            : IN STD_LOGIC;  --opt port
+  
+    WEA            : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRA          : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+  
+    DINA           : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+  
+    CLKA       : IN STD_LOGIC;
+
+  
+      --Port B
+    ENB            : IN STD_LOGIC;  --opt port
+    ADDRB          : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    DOUTB          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    CLKB           : IN STD_LOGIC
+
+
+  );
+  END COMPONENT;
+
+BEGIN
+
+  bmg0 : mem_4k8_top
+    PORT MAP (
+      --Port A
+      ENA        => ENA,
+  
+      WEA        => WEA,
+      ADDRA      => ADDRA,
+  
+      DINA       => DINA,
+
+      CLKA       => CLKA,
+  
+      --Port B
+      ENB        => ENB, 
+      ADDRB      => ADDRB,
+      DOUTB      => DOUTB,
+      CLKB       => CLKB
+
+
+      );
+END xilinx;
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.ucf
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.ucf	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.ucf	(revision 115)
@@ -0,0 +1,61 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Tx Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+NET "CLKA"  TNM_NET     = "CLKA";
+  
+NET "CLKB"  TNM_NET     = "CLKB";
+
+TIMESPEC "TS_CLKA"      = PERIOD "CLKA"  25 MHZ;
+  
+TIMESPEC "TS_CLKB"      = PERIOD "CLKB"  25 MHZ;
+
+################################################################################
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.vhd	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.vhd	(revision 115)
@@ -0,0 +1,178 @@
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v6.2 Core - Top-level core wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_wrapper.vhd
+--
+-- Description:
+--   This is the actual BMG core wrapper.
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY mem_4k8_top IS
+  PORT (
+      --Inputs - Port A
+    ENA            : IN STD_LOGIC;  --opt port
+  
+    WEA            : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRA          : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+  
+    DINA           : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+  
+    CLKA       : IN STD_LOGIC;
+
+  
+      --Inputs - Port B
+    ENB            : IN STD_LOGIC;  --opt port
+    ADDRB          : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    DOUTB          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    CLKB           : IN STD_LOGIC
+
+  );
+
+END mem_4k8_top;
+
+
+ARCHITECTURE xilinx OF mem_4k8_top IS
+
+  COMPONENT BUFG IS
+  PORT (
+     I      : IN STD_ULOGIC;
+     O      : OUT STD_ULOGIC
+  );
+  END COMPONENT;
+
+  COMPONENT mem_4k8 IS
+  PORT (
+      --Port A
+    ENA        : IN STD_LOGIC;  --opt port
+  
+    WEA        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    ADDRA      : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+  
+    DINA       : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+  
+    CLKA       : IN STD_LOGIC;
+
+  
+      --Port B
+    ENB        : IN STD_LOGIC;  --opt port
+    ADDRB      : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+    DOUTB      : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    CLKB       : IN STD_LOGIC
+
+
+  );
+  END COMPONENT;
+
+  SIGNAL CLKA_buf     : STD_LOGIC;
+  SIGNAL CLKB_buf     : STD_LOGIC;
+  SIGNAL S_ACLK_buf   : STD_LOGIC;
+
+BEGIN
+
+  bufg_A : BUFG
+    PORT MAP (
+     I => CLKA,
+     O => CLKA_buf
+     );
+
+  bufg_B : BUFG
+    PORT MAP (
+     I => CLKB,
+     O => CLKB_buf
+     );
+
+
+  bmg0 : mem_4k8
+    PORT MAP (
+      --Port A
+      ENA        => ENA,
+  
+      WEA        => WEA,
+      ADDRA      => ADDRA,
+  
+      DINA       => DINA,
+
+      CLKA       => CLKA_buf,
+
+  
+      --Port B
+      ENB        => ENB, 
+      ADDRB      => ADDRB,
+      DOUTB      => DOUTB,
+      CLKB       => CLKB_buf
+
+    );
+
+END xilinx;
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.xdc
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.xdc	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.xdc	(revision 115)
@@ -0,0 +1,56 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ]
+  
+create_clock -name "TS_CLKB" -period 20.0 [ get_ports CLKB ]
+################################################################################
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/implement.bat
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/implement.bat	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/implement.bat	(revision 115)
@@ -0,0 +1,41 @@
+
+rem Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+rem Synthesize the VHDL Wrapper Files
+
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+copy mem_4k8_top.ngc .\results\
+
+
+rem Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+copy ..\..\mem_4k8.ngc results\
+
+
+rem  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\mem_4k8_top.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc6slx45-csg324-3 mem_4k8_top
+
+echo 'Running map'
+map mem_4k8_top -o mapped.ncd -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level VHDL model'
+netgen -ofmt vhdl -sim -tm mem_4k8_top -pcf mapped.pcf -w routed.ncd routed.vhd
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/implement.sh
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/implement.sh	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/implement.sh	(revision 115)
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+#Synthesize the Wrapper Files
+echo 'Synthesizing XST wrapper file (core_top.vhd) with XST';
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+cp mem_4k8_top.ngc ./results/
+
+
+# Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+cp ../../mem_4k8.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/mem_4k8_top.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc6slx45-csg324-3 mem_4k8_top
+
+echo 'Running map'
+map mem_4k8_top -o mapped.ncd -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level VHDL model'
+netgen -ofmt vhdl -sim -tm mem_4k8_top -pcf mapped.pcf -w routed.ncd routed.vhd
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.bat
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.bat	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.bat	(revision 115)
@@ -0,0 +1,55 @@
+#!/bin/sh
+rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+rem 
+rem This file contains confidential and proprietary information
+rem of Xilinx, Inc. and is protected under U.S. and
+rem international copyright and other intellectual property
+rem laws.
+rem 
+rem DISCLAIMER
+rem This disclaimer is not a license and does not grant any
+rem rights to the materials distributed herewith. Except as
+rem otherwise provided in a valid license issued to you by
+rem Xilinx, and to the maximum extent permitted by applicable
+rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+rem (2) Xilinx shall not be liable (whether in contract or tort,
+rem including negligence, or under any other theory of
+rem liability) for any loss or damage of any kind or nature
+rem related to, arising under or in connection with these
+rem materials, including for any direct, or any indirect,
+rem special, incidental, or consequential loss or damage
+rem (including loss of data, profits, goodwill, or any type of
+rem loss or damage suffered as a result of any action brought
+rem by a third party) even if such damage or loss was
+rem reasonably foreseeable or Xilinx had been advised of the
+rem possibility of the same.
+rem 
+rem CRITICAL APPLICATIONS
+rem Xilinx products are not designed or intended to be fail-
+rem safe, or for use in any application requiring fail-safe
+rem performance, such as life-support or safety devices or
+rem systems, Class III medical devices, nuclear facilities,
+rem applications related to the deployment of airbags, or any
+rem other applications that could lead to death, personal
+rem injury, or severe property or environmental damage
+rem (individually and collectively, "Critical
+rem Applications"). Customer assumes the sole risk and
+rem liability of any use of Xilinx products in Critical
+rem Applications, subject only to applicable laws and
+rem regulations governing limitations on product liability.
+rem 
+rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+rem PART OF THIS FILE AT ALL TIMES.
+
+rem -----------------------------------------------------------------------------
+rem  Script to synthesize and implement the Coregen FIFO Generator
+rem -----------------------------------------------------------------------------
+rmdir /S /Q results
+mkdir results
+cd results
+copy ..\..\..\tmp\mem_4k8.edf .
+planAhead -mode batch -source ..\planAhead_rdn.tcl
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.sh
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.sh	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.sh	(revision 115)
@@ -0,0 +1,55 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+#-----------------------------------------------------------------------------
+#  Script to synthesize and implement the Coregen FIFO Generator
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+cp ../../../tmp/mem_4k8.edf .
+planAhead -mode batch -source ../planAhead_rdn.tcl
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.tcl
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.tcl	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.tcl	(revision 115)
@@ -0,0 +1,68 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+set device xc6slx45csg324-3
+set projName mem_4k8
+set design mem_4k8
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module mem_4k8_top
+add_files -norecurse {../../example_design/mem_4k8_top.vhd}
+add_files -norecurse {./mem_4k8.edf}
+import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/mem_4k8_top.xdc}
+set_property top mem_4k8_top [get_property srcset [current_run]]
+synth_design
+opt_design 
+place_design 
+route_design 
+set_param sta.dlyMediator true
+write_sdf -rename_top_module mem_4k8_top -file routed.sdf 
+write_verilog -nolib -mode sim -sdf_anno false -rename_top_module mem_4k8_top routed.vhd
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file routed.drc
+#write_bitstream
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/xst.prj
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/xst.prj	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/xst.prj	(revision 115)
@@ -0,0 +1,1 @@
+work ../example_design/mem_4k8_top.vhd
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/xst.scr
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/xst.scr	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/xst.scr	(revision 115)
@@ -0,0 +1,13 @@
+run
+-ifmt VHDL
+-ent mem_4k8_top
+-p xc6slx45-csg324-3
+-ifn xst.prj
+-write_timing_constraints No
+-iobuf YES
+-max_fanout 100
+-ofn mem_4k8_top 
+-ofmt NGC
+-bus_delimiter ()
+-hierarchy_separator /
+-case Maintain
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_xmdf.tcl
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_xmdf.tcl	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_xmdf.tcl	(revision 115)
@@ -0,0 +1,127 @@
+# The package naming convention is <core_name>_xmdf
+package provide mem_4k8_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::mem_4k8_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::mem_4k8_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name mem_4k8
+}
+# ::mem_4k8_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::mem_4k8_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8.sym
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8.vho
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8_ste/example_design/bmg_wrapper.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8_ste/example_design/mem_4k8_top.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8_ste/example_design/mem_4k8_top.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8_ste/example_design/mem_4k8_top.xdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8_ste/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8_ste/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8_ste/implement/planAhead_rdn.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8_ste/implement/planAhead_rdn.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8_ste/implement/planAhead_rdn.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8_ste/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8_ste/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path mem_4k8_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module mem_4k8
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_coregen.cgc
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_coregen.cgc	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_coregen.cgc	(revision 115)
@@ -0,0 +1,444 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" >
+   <spirit:vendor>xilinx.com</spirit:vendor>
+   <spirit:library>CoreGen</spirit:library>
+   <spirit:name>mem_coregen</spirit:name>
+   <spirit:version>1.0</spirit:version>
+   <spirit:componentInstances>
+      <spirit:componentInstance>
+         <spirit:instanceName>blk_mem_gen_v6_2</spirit:instanceName>
+         <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="6.2" />
+         <spirit:configurableElementValues>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">blk_mem_gen_v6_2</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_TYPE">AXI4_Full</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_SLAVE_TYPE">Memory_Slave</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_AXI_ID">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_WIDTH">4</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEMORY_TYPE">Simple_Dual_Port_RAM</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECCTYPE">No_ECC</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SOFTECC">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_ERROR_INJECTION_PINS">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ERROR_INJECTION_TYPE">Single_Bit_Error_Injection</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BYTE_WRITE_ENABLE">true</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BYTE_SIZE">8</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALGORITHM">Minimum_Area</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">8kx2</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSUME_SYNCHRONOUS_CLK">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_WIDTH_A">8</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DEPTH_A">4096</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WIDTH_A">8</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPERATING_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_A">Use_ENA_Pin</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_WIDTH_B">8</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WIDTH_B">8</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPERATING_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_B">Use_ENB_Pin</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTA_OUTPUT_OF_MEMORY_PRIMITIVES">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTA_OUTPUT_OF_MEMORY_CORE">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_REGCEA_PIN">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTB_OUTPUT_OF_MEMORY_PRIMITIVES">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTB_OUTPUT_OF_MEMORY_CORE">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_REGCEB_PIN">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTA_INPUT_OF_SOFTECC">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTB_OUTPUT_OF_SOFTECC">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIPELINE_STAGES">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOAD_INIT_FILE">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COE_FILE">no_coe_file_loaded</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FILL_REMAINING_MEMORY_LOCATIONS">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REMAINING_MEMORY_LOCATIONS">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RSTA_PIN">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_MEMORY_LATCH_A">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PRIORITY_A">CE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_RESET_VALUE_A">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RSTB_PIN">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_MEMORY_LATCH_B">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PRIORITY_B">CE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_RESET_VALUE_B">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">SYNC</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDITIONAL_INPUTS_FOR_POWER_ESTIMATION">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_A_CLOCK">100</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_A_WRITE_RATE">50</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_B_CLOCK">100</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_B_WRITE_RATE">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_A_ENABLE_RATE">100</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_B_ENABLE_RATE">100</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COLLISION_WARNINGS">ALL</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_COLLISION_WARNINGS">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_OUT_OF_RANGE_WARNINGS">false</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">spartan6</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">spartan6</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/_cg/</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">8</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_TYPE">SYNC</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">8</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">8</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">4096</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">4096</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">12</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">8</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">8</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">4096</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">4096</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">12</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
+            <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
+         </spirit:configurableElementValues>
+         <spirit:vendorExtensions>
+            <xilinx:instanceProperties>
+               <xilinx:projectOptions>
+                  <xilinx:projectName>mem_coregen</xilinx:projectName>
+                  <xilinx:outputDirectory>./</xilinx:outputDirectory>
+                  <xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
+                  <xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
+               </xilinx:projectOptions>
+               <xilinx:part>
+                  <xilinx:device>xc6slx45</xilinx:device>
+                  <xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
+                  <xilinx:package>csg324</xilinx:package>
+                  <xilinx:speedGrade>-3</xilinx:speedGrade>
+               </xilinx:part>
+               <xilinx:flowOptions>
+                  <xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
+                  <xilinx:designEntry>VHDL</xilinx:designEntry>
+                  <xilinx:asySymbol>true</xilinx:asySymbol>
+                  <xilinx:flowVendor>Other</xilinx:flowVendor>
+                  <xilinx:addPads>false</xilinx:addPads>
+                  <xilinx:removeRPMs>false</xilinx:removeRPMs>
+                  <xilinx:createNDF>false</xilinx:createNDF>
+                  <xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
+                  <xilinx:formalVerification>false</xilinx:formalVerification>
+               </xilinx:flowOptions>
+               <xilinx:simulationOptions>
+                  <xilinx:simulationModel>Behavioral</xilinx:simulationModel>
+                  <xilinx:simulationLanguage>VHDL</xilinx:simulationLanguage>
+                  <xilinx:foundationSym>false</xilinx:foundationSym>
+               </xilinx:simulationOptions>
+               <xilinx:packageInfo>
+                  <xilinx:sourceCoreCreationDate>2011-03-11T08:24:14.000Z</xilinx:sourceCoreCreationDate>
+               </xilinx:packageInfo>
+            </xilinx:instanceProperties>
+            <xilinx:generationHistory>
+               <xilinx:fileSet>
+                  <xilinx:name>apply_current_project_options_generator</xilinx:name>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>customization_generator</xilinx:name>
+                  <xilinx:file>
+                     <xilinx:name>./summary.log</xilinx:name>
+                     <xilinx:userFileType>unknown</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:01:21 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x4F489DB4</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>model_parameter_resolution_generator</xilinx:name>
+                  <xilinx:file>
+                     <xilinx:name>./summary.log</xilinx:name>
+                     <xilinx:userFileType>unknown</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:01:29 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x4F489DB4</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>ip_xco_generator</xilinx:name>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2.xco</xilinx:name>
+                     <xilinx:userFileType>xco</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:01:30 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0xF014F97C</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>associated_files_generator</xilinx:name>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_ds512.pdf</xilinx:name>
+                     <xilinx:userFileType>pdf</xilinx:userFileType>
+                     <xilinx:timeStamp>Tue Oct 04 23:21:26 GMT 2011</xilinx:timeStamp>
+                     <xilinx:checkSum>0xA43B8952</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2_readme.txt</xilinx:name>
+                     <xilinx:userFileType>txt</xilinx:userFileType>
+                     <xilinx:timeStamp>Tue Oct 04 23:21:26 GMT 2011</xilinx:timeStamp>
+                     <xilinx:checkSum>0x399E1D72</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>ejava_generator</xilinx:name>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.ucf</xilinx:name>
+                     <xilinx:userFileType>ignore</xilinx:userFileType>
+                     <xilinx:userFileType>ucf</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:01:32 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x8915DFA1</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.vhd</xilinx:name>
+                     <xilinx:userFileType>ignore</xilinx:userFileType>
+                     <xilinx:userFileType>vhdl</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:01:32 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x39D6EEDA</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.xdc</xilinx:name>
+                     <xilinx:userFileType>ignore</xilinx:userFileType>
+                     <xilinx:userFileType>xdc</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:01:32 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x78E2D49A</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2_ste/example_design/bmg_wrapper.vhd</xilinx:name>
+                     <xilinx:userFileType>ignore</xilinx:userFileType>
+                     <xilinx:userFileType>vhdl</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:01:32 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x5C3F6B98</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2_ste/implement/implement.bat</xilinx:name>
+                     <xilinx:userFileType>ignore</xilinx:userFileType>
+                     <xilinx:userFileType>unknown</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:01:32 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0xE86DEA05</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2_ste/implement/implement.sh</xilinx:name>
+                     <xilinx:userFileType>ignore</xilinx:userFileType>
+                     <xilinx:userFileType>unknown</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:01:32 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0xBF76F109</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2_ste/implement/planAhead_rdn.bat</xilinx:name>
+                     <xilinx:userFileType>ignore</xilinx:userFileType>
+                     <xilinx:userFileType>unknown</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:01:32 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x86FAE7F8</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2_ste/implement/planAhead_rdn.sh</xilinx:name>
+                     <xilinx:userFileType>ignore</xilinx:userFileType>
+                     <xilinx:userFileType>unknown</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:01:32 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0xD25129D7</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2_ste/implement/planAhead_rdn.tcl</xilinx:name>
+                     <xilinx:userFileType>ignore</xilinx:userFileType>
+                     <xilinx:userFileType>tcl</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:01:32 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x30DC827D</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2_ste/implement/xst.prj</xilinx:name>
+                     <xilinx:userFileType>ignore</xilinx:userFileType>
+                     <xilinx:userFileType>unknown</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:01:32 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x263C68FF</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2_ste/implement/xst.scr</xilinx:name>
+                     <xilinx:userFileType>ignore</xilinx:userFileType>
+                     <xilinx:userFileType>unknown</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:01:32 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0xF4B7D6CF</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>ngc_netlist_generator</xilinx:name>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2.ngc</xilinx:name>
+                     <xilinx:userFileType>ngc</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:03:01 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0xB393819B</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>obfuscate_netlist_generator</xilinx:name>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>padded_implementation_netlist_generator</xilinx:name>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>instantiation_template_generator</xilinx:name>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2.vho</xilinx:name>
+                     <xilinx:userFileType>vho</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:03:02 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0xC2F71940</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>structural_simulation_model_generator</xilinx:name>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2.vhd</xilinx:name>
+                     <xilinx:userFileType>vhdl</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:03:03 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x509FA329</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>asy_generator</xilinx:name>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2.asy</xilinx:name>
+                     <xilinx:userFileType>asy</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:03:09 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x6178BCD9</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+                  <xilinx:file>
+                     <xilinx:name>./summary.log</xilinx:name>
+                     <xilinx:userFileType>unknown</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:03:09 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x4F489DB4</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>xmdf_generator</xilinx:name>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2_xmdf.tcl</xilinx:name>
+                     <xilinx:userFileType>tclXmdf</xilinx:userFileType>
+                     <xilinx:userFileType>tcl</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:03:09 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x9F2E33B8</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>ise_generator</xilinx:name>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2.gise</xilinx:name>
+                     <xilinx:userFileType>ignore</xilinx:userFileType>
+                     <xilinx:userFileType>gise</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:03:22 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x94E343F5</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2.xise</xilinx:name>
+                     <xilinx:userFileType>ignore</xilinx:userFileType>
+                     <xilinx:userFileType>xise</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:03:22 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0x69700327</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>deliver_readme_generator</xilinx:name>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>flist_generator</xilinx:name>
+                  <xilinx:file>
+                     <xilinx:name>./blk_mem_gen_v6_2_flist.txt</xilinx:name>
+                     <xilinx:userFileType>ignore</xilinx:userFileType>
+                     <xilinx:userFileType>txtFlist</xilinx:userFileType>
+                     <xilinx:userFileType>txt</xilinx:userFileType>
+                     <xilinx:timeStamp>Mon Mar 03 07:03:23 GMT 2014</xilinx:timeStamp>
+                     <xilinx:checkSum>0xF86013AF</xilinx:checkSum>
+                     <xilinx:generationId>generationid_4243181522</xilinx:generationId>
+                  </xilinx:file>
+               </xilinx:fileSet>
+               <xilinx:fileSet>
+                  <xilinx:name>view_readme_generator</xilinx:name>
+               </xilinx:fileSet>
+            </xilinx:generationHistory>
+         </spirit:vendorExtensions>
+      </spirit:componentInstance>
+   </spirit:componentInstances>
+   <spirit:vendorExtensions>
+      <xilinx:instanceProperties>
+         <xilinx:projectOptions>
+            <xilinx:projectName>mem_coregen</xilinx:projectName>
+            <xilinx:outputDirectory>./</xilinx:outputDirectory>
+            <xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
+            <xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
+         </xilinx:projectOptions>
+         <xilinx:part>
+            <xilinx:device>xc6slx45</xilinx:device>
+            <xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
+            <xilinx:package>csg324</xilinx:package>
+            <xilinx:speedGrade>-3</xilinx:speedGrade>
+         </xilinx:part>
+         <xilinx:flowOptions>
+            <xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
+            <xilinx:designEntry>VHDL</xilinx:designEntry>
+            <xilinx:asySymbol>true</xilinx:asySymbol>
+            <xilinx:flowVendor>Other</xilinx:flowVendor>
+            <xilinx:addPads>false</xilinx:addPads>
+            <xilinx:removeRPMs>false</xilinx:removeRPMs>
+            <xilinx:createNDF>false</xilinx:createNDF>
+            <xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
+            <xilinx:formalVerification>false</xilinx:formalVerification>
+         </xilinx:flowOptions>
+         <xilinx:simulationOptions>
+            <xilinx:simulationModel>Behavioral</xilinx:simulationModel>
+            <xilinx:simulationLanguage>VHDL</xilinx:simulationLanguage>
+            <xilinx:foundationSym>false</xilinx:foundationSym>
+         </xilinx:simulationOptions>
+      </xilinx:instanceProperties>
+   </spirit:vendorExtensions>
+</spirit:design>
+
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_coregen.cgp
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_coregen.cgp	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_coregen.cgp	(revision 115)
@@ -0,0 +1,22 @@
+# Date: Sun Mar 02 19:33:45 2014
+
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
+SET workingdirectory = .\tmp\
+
+# CRC: 1242dfe7
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/summary.log
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/summary.log	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/summary.log	(revision 115)
@@ -0,0 +1,19 @@
+
+User Configuration
+-------------------------------------
+Algorithm				:	Minimum_Area
+Memory Type				:	Simple_Dual_Port_RAM
+Port A Write Width		:	8
+Port B Read Width		:	8
+Memory Depth			:	8191
+--------------------------------------------------------------
+
+Block RAM resource(s) (9K BRAMs)		: 0
+Block RAM resource(s) (18K BRAMs)		: 4
+--------------------------------------------------------------
+Clock A Frequency		:  100
+Port A Enable Rate		:  100
+Port A Write Rate		:  50
+----------------------------------------------------------
+Estimated Power for IP : 9.683365 mW
+----------------------------------------------------------
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_cg/_dbg/xil_444.in
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_cg/_dbg/xil_444.in	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_cg/_dbg/xil_444.in	(revision 115)
@@ -0,0 +1,92 @@
+SET_FLAG DEBUG FALSE
+SET_FLAG MODE INTERACTIVE
+SET_FLAG STANDALONE_MODE FALSE
+SET_PREFERENCE devicefamily spartan6
+SET_PREFERENCE device xc6slx45
+SET_PREFERENCE speedgrade -3
+SET_PREFERENCE package csg324
+SET_PREFERENCE verilogsim false
+SET_PREFERENCE vhdlsim true
+SET_PREFERENCE simulationfiles Behavioral
+SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
+SET_PREFERENCE outputdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/
+SET_PREFERENCE workingdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/
+SET_PREFERENCE subworkingdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/_cg/
+SET_PREFERENCE transientdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/_cg/_dbg/
+SET_PREFERENCE designentry VHDL
+SET_PREFERENCE flowvendor Other
+SET_PREFERENCE addpads false
+SET_PREFERENCE projectname coregen
+SET_PREFERENCE formalverification false
+SET_PREFERENCE asysymbol false
+SET_PREFERENCE implementationfiletype Ngc
+SET_PREFERENCE foundationsym false
+SET_PREFERENCE createndf false
+SET_PREFERENCE removerpms false
+SET_PARAMETER Component_Name mem_4k8
+SET_PARAMETER Interface_Type Native
+SET_PARAMETER AXI_Type AXI4_Full
+SET_PARAMETER AXI_Slave_Type Memory_Slave
+SET_PARAMETER Use_AXI_ID false
+SET_PARAMETER AXI_ID_Width 4
+SET_PARAMETER Memory_Type Simple_Dual_Port_RAM
+SET_PARAMETER ecctype No_ECC
+SET_PARAMETER ECC false
+SET_PARAMETER softecc false
+SET_PARAMETER Use_Error_Injection_Pins false
+SET_PARAMETER Error_Injection_Type Single_Bit_Error_Injection
+SET_PARAMETER Use_Byte_Write_Enable true
+SET_PARAMETER Byte_Size 8
+SET_PARAMETER Algorithm Minimum_Area
+SET_PARAMETER Primitive 8kx2
+SET_PARAMETER Assume_Synchronous_Clk false
+SET_PARAMETER Write_Width_A 8
+SET_PARAMETER Write_Depth_A 4096
+SET_PARAMETER Read_Width_A 8
+SET_PARAMETER Operating_Mode_A WRITE_FIRST
+SET_PARAMETER Enable_A Use_ENA_Pin
+SET_PARAMETER Write_Width_B 8
+SET_PARAMETER Read_Width_B 8
+SET_PARAMETER Operating_Mode_B WRITE_FIRST
+SET_PARAMETER Enable_B Use_ENB_Pin
+SET_PARAMETER Register_PortA_Output_of_Memory_Primitives false
+SET_PARAMETER Register_PortA_Output_of_Memory_Core false
+SET_PARAMETER Use_REGCEA_Pin false
+SET_PARAMETER Register_PortB_Output_of_Memory_Primitives false
+SET_PARAMETER Register_PortB_Output_of_Memory_Core false
+SET_PARAMETER Use_REGCEB_Pin false
+SET_PARAMETER register_porta_input_of_softecc false
+SET_PARAMETER register_portb_output_of_softecc false
+SET_PARAMETER Pipeline_Stages 0
+SET_PARAMETER Load_Init_File false
+SET_PARAMETER Coe_File no_coe_file_loaded
+SET_PARAMETER Fill_Remaining_Memory_Locations false
+SET_PARAMETER Remaining_Memory_Locations 0
+SET_PARAMETER Use_RSTA_Pin false
+SET_PARAMETER Reset_Memory_Latch_A false
+SET_PARAMETER Reset_Priority_A CE
+SET_PARAMETER Output_Reset_Value_A 0
+SET_PARAMETER Use_RSTB_Pin false
+SET_PARAMETER Reset_Memory_Latch_B false
+SET_PARAMETER Reset_Priority_B CE
+SET_PARAMETER Output_Reset_Value_B 0
+SET_PARAMETER Reset_Type SYNC
+SET_PARAMETER Additional_Inputs_for_Power_Estimation false
+SET_PARAMETER Port_A_Clock 100
+SET_PARAMETER Port_A_Write_Rate 50
+SET_PARAMETER Port_B_Clock 100
+SET_PARAMETER Port_B_Write_Rate 0
+SET_PARAMETER Port_A_Enable_Rate 100
+SET_PARAMETER Port_B_Enable_Rate 100
+SET_PARAMETER Collision_Warnings ALL
+SET_PARAMETER Disable_Collision_Warnings false
+SET_PARAMETER Disable_Out_of_Range_Warnings false
+SET_CORE_NAME Block Memory Generator
+SET_CORE_VERSION 6.2
+SET_CORE_VLNV xilinx.com:ip:blk_mem_gen:6.2
+SET_CORE_CLASS com.xilinx.ip.blk_mem_gen_v6_2.blk_mem_gen_v6_2
+SET_CORE_PATH C:/Xilinx/13.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2
+SET_CORE_GUIPATH C:/Xilinx/13.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2/gui/blk_mem_gen_v6_2.tcl
+SET_CORE_DATASHEET C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_ds512.pdf
+ADD_CORE_DOCUMENT <C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_ds512.pdf><blk_mem_gen_ds512.pdf>
+ADD_CORE_DOCUMENT <C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_v6_2_vinfo.html><blk_mem_gen_v6_2_vinfo.html>
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_cg/_dbg/xil_444.out
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_cg/_dbg/xil_444.out	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_cg/_dbg/xil_444.out	(revision 115)
@@ -0,0 +1,61 @@
+SET_PARAMETER use_rstb_pin false
+SET_PARAMETER pipeline_stages 0
+SET_PARAMETER assume_synchronous_clk false
+SET_PARAMETER use_regcea_pin false
+SET_PARAMETER axi_id_width 4
+SET_PARAMETER softecc false
+SET_PARAMETER load_init_file false
+SET_PARAMETER port_a_write_rate 50
+SET_PARAMETER disable_collision_warnings false
+SET_PARAMETER use_byte_write_enable true
+SET_PARAMETER ecc false
+SET_PARAMETER primitive 8kx2
+SET_PARAMETER port_b_clock 100
+SET_PARAMETER remaining_memory_locations 0
+SET_PARAMETER memory_type Simple_Dual_Port_RAM
+SET_PARAMETER register_porta_input_of_softecc false
+SET_PARAMETER port_a_clock 100
+SET_PARAMETER read_width_a 8
+SET_PARAMETER disable_out_of_range_warnings false
+SET_PARAMETER read_width_b 8
+SET_PARAMETER register_portb_output_of_softecc false
+SET_PARAMETER byte_size 8
+SET_PARAMETER register_portb_output_of_memory_core false
+SET_PARAMETER use_regceb_pin false
+SET_PARAMETER register_porta_output_of_memory_core false
+SET_PARAMETER reset_memory_latch_a false
+SET_PARAMETER reset_memory_latch_b false
+SET_PARAMETER register_porta_output_of_memory_primitives false
+SET_PARAMETER use_error_injection_pins false
+SET_PARAMETER enable_a Use_ENA_Pin
+SET_PARAMETER enable_b Use_ENB_Pin
+SET_PARAMETER port_a_enable_rate 100
+SET_PARAMETER use_axi_id false
+SET_PARAMETER write_depth_a 4096
+SET_PARAMETER algorithm Minimum_Area
+SET_PARAMETER output_reset_value_a 0
+SET_PARAMETER output_reset_value_b 0
+SET_PARAMETER error_injection_type Single_Bit_Error_Injection
+SET_PARAMETER port_b_write_rate 0
+SET_PARAMETER ecctype No_ECC
+SET_PARAMETER write_width_a 8
+SET_PARAMETER write_width_b 8
+SET_PARAMETER component_name mem_4k8
+SET_PARAMETER reset_priority_a CE
+SET_PARAMETER reset_priority_b CE
+SET_PARAMETER operating_mode_a WRITE_FIRST
+SET_PARAMETER additional_inputs_for_power_estimation false
+SET_PARAMETER operating_mode_b WRITE_FIRST
+SET_PARAMETER interface_type Native
+SET_PARAMETER reset_type SYNC
+SET_PARAMETER register_portb_output_of_memory_primitives false
+SET_PARAMETER use_rsta_pin false
+SET_PARAMETER port_b_enable_rate 100
+SET_PARAMETER coe_file no_coe_file_loaded
+SET_PARAMETER fill_remaining_memory_locations false
+SET_PARAMETER axi_slave_type Memory_Slave
+SET_PARAMETER axi_type AXI4_Full
+SET_PARAMETER collision_warnings ALL
+SET_ERROR_CODE 2
+SET_ERROR_MSG  CANCEL: Customization cancelled.
+SET_ERROR_TEXT Finished initializing IP model.	
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_cg/summary.log
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_cg/summary.log	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_cg/summary.log	(revision 115)
@@ -0,0 +1,19 @@
+
+User Configuration
+-------------------------------------
+Algorithm				:	Minimum_Area
+Memory Type				:	Simple_Dual_Port_RAM
+Port A Write Width		:	8
+Port B Read Width		:	8
+Memory Depth			:	4096
+--------------------------------------------------------------
+
+Block RAM resource(s) (9K BRAMs)		: 0
+Block RAM resource(s) (18K BRAMs)		: 2
+--------------------------------------------------------------
+Clock A Frequency		:  100
+Port A Enable Rate		:  100
+Port A Write Rate		:  50
+----------------------------------------------------------
+Estimated Power for IP : 3.303411 mW
+----------------------------------------------------------
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs	(revision 115)
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+</messages>
+
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs	(revision 115)
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/_cg/blk_mem_gen_v6_2.vhd&quot; into library work</arg>
+</msg>
+
+</messages>
+
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_xmsgs/xst.xmsgs
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_xmsgs/xst.xmsgs	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/_xmsgs/xst.xmsgs	(revision 115)
@@ -0,0 +1,411 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="UtilitiesC" num="159" delta="old" >Message file &quot;<arg fmt="%s" index="1">usenglish/ip.msg</arg>&quot; wasn&apos;t found.
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg> 	u:<arg fmt="%d" index="6">2</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">2</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg> 	u:<arg fmt="%d" index="6">2</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">2</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg> 	u:<arg fmt="%d" index="6">2</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">3</arg>: (<arg fmt="%d" index="2">6</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg> 	u:<arg fmt="%d" index="6">2</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg> 	u:<arg fmt="%d" index="6">2</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">2</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg> 	u:<arg fmt="%d" index="6">2</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">2</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg> 	u:<arg fmt="%d" index="6">2</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">3</arg>: (<arg fmt="%d" index="2">6</arg>,<arg fmt="%d" index="3">0</arg>) 	: <arg fmt="%d" index="4">2</arg>x<arg fmt="%d" index="5">8192</arg> 	u:<arg fmt="%d" index="6">2</arg>
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="old" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_input_block.vhd" Line 691: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="old" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_input_block.vhd" Line 707: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="746" delta="old" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 977: Range is empty (null range)
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="220" delta="old" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 977: Assignment ignored
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="746" delta="old" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 978: Range is empty (null range)
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="220" delta="old" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 978: Assignment ignored
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="634" delta="new" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_wrapper_s6.vhd" Line 490: Net &lt;<arg fmt="%s" index="1">douta_i[1]</arg>&gt; does not have a driver.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="old" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_generic_cstr.vhd" Line 1544: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="321" delta="old" >"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_generic_cstr.vhd" Line 1557: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">douta</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdata</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_awready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_wready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_arready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rlast</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWID&lt;3:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWADDR&lt;31:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWLEN&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWSIZE&lt;2:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWBURST&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_WDATA&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_WSTRB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARID&lt;3:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARADDR&lt;31:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARLEN&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARSIZE&lt;2:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARBURST&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AClk</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_ARESETN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWVALID</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_WLAST</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_WVALID</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_BREADY</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARVALID</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_RREADY</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="old" >Signal &apos;<arg fmt="%s" index="1">S_AXI_BID</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_v6_2_xst</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_BRESP</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="old" >Signal &apos;<arg fmt="%s" index="1">S_AXI_RID</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_v6_2_xst</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RDATA</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RRESP</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_AWREADY</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_WREADY</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_BVALID</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_ARREADY</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RLAST</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RVALID</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DINB&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RSTA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RSTB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">INJECTDBITERR_I</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">INJECTSBITERR_I</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">REGCEA&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">REGCEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[0].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[0].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[1].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[1].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[2].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[2].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[3].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[3].ram.r</arg>&gt; is unconnected or connected to loadless signal.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DINB&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">douta_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_1</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DINB&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">douta_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_2</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DINB&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">douta_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_3</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DINB&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">douta_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_4</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">00</arg>).
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DOUTA_I&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RDADDRECC_I&lt;12:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">CLKB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">SBITERR_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DBITERR_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
+</msg>
+
+<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
+</msg>
+
+</messages>
+
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/blk_mem_gen_v6_2.lso
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/blk_mem_gen_v6_2.lso	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/blk_mem_gen_v6_2.lso	(revision 115)
@@ -0,0 +1,1 @@
+work
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/mem8k8.lso
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/mem8k8.lso	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/mem8k8.lso	(revision 115)
@@ -0,0 +1,1 @@
+work
Index: /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/mem_4k8.lso
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/mem_4k8.lso	(revision 115)
+++ /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/tmp/mem_4k8.lso	(revision 115)
@@ -0,0 +1,1 @@
+work
