Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_flist.txt
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_flist.txt	(revision 117)
+++ 	(revision )
@@ -1,25 +1,0 @@
-# Output products list for <blk_mem_gen_v6_2>
-_xmsgs\pn_parser.xmsgs
-blk_mem_gen_ds512.pdf
-blk_mem_gen_v6_2.asy
-blk_mem_gen_v6_2.gise
-blk_mem_gen_v6_2.ngc
-blk_mem_gen_v6_2.vhd
-blk_mem_gen_v6_2.vho
-blk_mem_gen_v6_2.xco
-blk_mem_gen_v6_2.xise
-blk_mem_gen_v6_2_flist.txt
-blk_mem_gen_v6_2_readme.txt
-blk_mem_gen_v6_2_ste\example_design\blk_mem_gen_v6_2_top.ucf
-blk_mem_gen_v6_2_ste\example_design\blk_mem_gen_v6_2_top.vhd
-blk_mem_gen_v6_2_ste\example_design\blk_mem_gen_v6_2_top.xdc
-blk_mem_gen_v6_2_ste\example_design\bmg_wrapper.vhd
-blk_mem_gen_v6_2_ste\implement\implement.bat
-blk_mem_gen_v6_2_ste\implement\implement.sh
-blk_mem_gen_v6_2_ste\implement\planAhead_rdn.bat
-blk_mem_gen_v6_2_ste\implement\planAhead_rdn.sh
-blk_mem_gen_v6_2_ste\implement\planAhead_rdn.tcl
-blk_mem_gen_v6_2_ste\implement\xst.prj
-blk_mem_gen_v6_2_ste\implement\xst.scr
-blk_mem_gen_v6_2_xmdf.tcl
-summary.log
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_readme.txt
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_readme.txt	(revision 117)
+++ 	(revision )
@@ -1,203 +1,0 @@
-                Core name: Xilinx LogiCORE Block Memory Generator
-                Version: 6.2
-                Release Date: June 22, 2011
-
-
-================================================================================
-
-This document contains the following sections:
-
-1. Introduction
-2. New Features
-3. Supported Devices
-4. Resolved Issues
-5. Known Issues
-6. Technical Support
-7. Core Release History
-8. Legal Disclaimer
-
-================================================================================
-
-
-1. INTRODUCTION
-
-For installation instructions for this release, please go to:
-
-  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
-
-For system requirements:
-
-   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
-
-This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v6.2 
-solution. For the latest core updates, see the product page at:
- 
- http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
-
-
-2. NEW FEATURES
-
-  - ISE 13.2 software support
-  - Virtex-7L, Kintex-7L, Artix-7* and Zynq-7000* device support
-
-3. SUPPORTED DEVICES
-
-The following device families are supported by the core for this release.
-
-Zynq-7000*
-
-Virtex-7 
-Virtex-7 XT (7vx485t)
-Virtex-7 -2L
-
-Kintex-7
-Kintex-7 -2L 
-
-Artix-7*
-
-Virtex-6 XC CXT/LXT/SXT/HXT
-Virtex-6 XQ LXT/SXT                                                       
-Virtex-6 -1L XQ LXT/SXT 
-
-Spartan-6 XC LX/LXT 
-Spartan-6 XA 
-Spartan-6 XQ LX/LXT       
-Spartan-6 -1L XQ LX
-
-Virtex-5 XC LX/LXT/SXT/TXT/FXT
-Virtex-5 XQ LX/ LXT/SXT/FXT                                                
-
-Virtex-4 XC LX/SX/FX
-Virtex-4 XQ LX/SX/FX
-Virtex-4 XQR LX/SX/FX                                                  
-
-Spartan-3 XC
-Spartan-3 XA                                                                      
-Spartan-3A XC 3A / 3A DSP / 3AN DSP                                      
-Spartan-3A XA 3A / 3A DSP                                                    
-Spartan-3E XC                                        
-Spartan-3E XA 
-
-*To access these devices in the ISE Design Suite, contact your Xilinx FAE.
-
-4. RESOLVED ISSUES
-
-The following issues are resolved in Block Memory Generator v6.2: 
-  
-  1. Core errors in NGDBuild when the depth is too large (especially for Spartan-6 devices)
-   Version Fixed: v6.2 
-   - CR 587481
-   - AR 39718
-
-5. KNOWN ISSUES 
-
-The following are known issues for v6.2 of this core at time of release:
-
-  1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)
-    Work around: The user must review the possible scenarios that causes the collission and revise 
-     their design to avoid those situations.
-    - CR588505
-  
-    Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with 
-          Write Mode = Read First in conjunction with asynchronous clocking
-   
-  2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
-
-  3. Core does not generate for large memories. Depending on the
-     machine the ISE CORE Generator software runs on, the maximum size of the memory that
-     can be generated will vary.  For example, a Dual Pentium-4 server 
-     with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
-    - CR 415768
-    - AR 24034
-  
-The most recent information, including known issues, workarounds, and resolutions for 
-this version is provided in the IP Release Notes User Guide located at
-  
-       www.xilinx.com/support/documentation/user_guides/xtp025.pdf
-   
-6. TECHNICAL SUPPORT 
-
-To obtain technical support, create a WebCase at www.xilinx.com/support.
-Questions are routed to a team with expertise using this product.
-
-Xilinx provides technical support for use of this product when used
-according to the guidelines described in the core documentation, and
-cannot guarantee timing, functionality, or support of this product for
-designs that do not follow specified guidelines.
-
-7. CORE RELEASE HISTORY 
-
-Date        By            Version      Description
-================================================================================
-06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
-03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
-09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support
-07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support
-04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support
-03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue 
-12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power
-                                       Device support; Automotive Spartan 3A
-                                       DSP device support
-09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3
-06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2
-04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1
-09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8
-03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7
-10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6
-07/2007     Xilinx, Inc.  2.5          Revised to v2.5
-04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1
-02/2007     Xilinx, Inc.  2.4          Revised to v2.4
-11/2006     Xilinx, Inc.  2.3          Revised to v2.3
-09/2006     Xilinx, Inc.  2.2          Revised to v2.2
-06/2006     Xilinx, Inc.  2.1          Revised to v2.1
-01/2006     Xilinx, Inc.  1.1          Initial release
-================================================================================
-
-8. Legal Disclaimer
-
- (c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved.
- 
- This file contains confidential and proprietary information
- of Xilinx, Inc. and is protected under U.S. and
- international copyright and other intellectual property
- laws.
- 
- DISCLAIMER
- This disclaimer is not a license and does not grant any
- rights to the materials distributed herewith. Except as
- otherwise provided in a valid license issued to you by
- Xilinx, and to the maximum extent permitted by applicable
- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
- (2) Xilinx shall not be liable (whether in contract or tort,
- including negligence, or under any other theory of
- liability) for any loss or damage of any kind or nature
- related to, arising under or in connection with these
- materials, including for any direct, or any indirect,
- special, incidental, or consequential loss or damage
- (including loss of data, profits, goodwill, or any type of
- loss or damage suffered as a result of any action brought
- by a third party) even if such damage or loss was
- reasonably foreseeable or Xilinx had been advised of the
- possibility of the same.
- 
- CRITICAL APPLICATIONS
- Xilinx products are not designed or intended to be fail-
- safe, or for use in any application requiring fail-safe
- performance, such as life-support or safety devices or
- systems, Class III medical devices, nuclear facilities,
- applications related to the deployment of airbags, or any
- other applications that could lead to death, personal
- injury, or severe property or environmental damage
- (individually and collectively, "Critical
- Applications"). Customer assumes the sole risk and
- liability of any use of Xilinx products in Critical
- Applications, subject only to applicable laws and
- regulations governing limitations on product liability.
- 
- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
- PART OF THIS FILE AT ALL TIMES.
-
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_xmdf.tcl
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_xmdf.tcl	(revision 117)
+++ 	(revision )
@@ -1,123 +1,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide blk_mem_gen_v6_2_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::blk_mem_gen_v6_2_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::blk_mem_gen_v6_2_xmdf::xmdfInit { instance } {
-# Variable containing name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name blk_mem_gen_v6_2
-}
-# ::blk_mem_gen_v6_2_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::blk_mem_gen_v6_2_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2.asy
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2.vho
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_readme.txt
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.ucf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.xdc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/example_design/bmg_wrapper.vhd
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/implement/implement.bat
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/implement/implement.sh
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/implement/planAhead_rdn.bat
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/implement/planAhead_rdn.sh
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/implement/planAhead_rdn.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/implement/xst.prj
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_ste/implement/xst.scr
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module blk_mem_gen_v6_2
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/coregen.cgp
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/coregen.cgp	(revision 117)
+++ 	(revision )
@@ -1,9 +1,0 @@
-SET busformat = BusFormatAngleBracketNotRipped
-SET designentry = VHDL
-SET device = xc6slx45
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET package = csg324
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/create_mem8k8.tcl
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/create_mem8k8.tcl	(revision 117)
+++ 	(revision )
@@ -1,37 +1,0 @@
-##
-## Core Generator Run Script, generator for Project Navigator create command
-##
-
-proc findRtfPath { relativePath } {
-   set xilenv ""
-   if { [info exists ::env(XILINX) ] } {
-      if { [info exists ::env(MYXILINX)] } {
-         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
-      } else {
-         set xilenv $::env(XILINX)
-      }
-   }
-   foreach path [ split $xilenv $::xilinx::path_sep ] {
-      set fullPath [ file join $path $relativePath ]
-      if { [ file exists $fullPath ] } {
-         return $fullPath
-      }
-   }
-   return ""
-}
-
-source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
-
-set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "mem8k8" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc6slx45-3csg324 VHDL ]
-
-if { $result == 0 } {
-   puts "Core Generator create command completed successfully."
-} elseif { $result == 1 } {
-   puts "Core Generator create command failed."
-} elseif { $result == 3 || $result == 4 } {
-   # convert 'version check' result to real return range, bypassing any messages.
-   set result [ expr $result - 3 ]
-} else {
-   puts "Core Generator create cancelled."
-}
-exit $result
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/create_mem_4k8.tcl
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/create_mem_4k8.tcl	(revision 117)
+++ 	(revision )
@@ -1,37 +1,0 @@
-##
-## Core Generator Run Script, generator for Project Navigator create command
-##
-
-proc findRtfPath { relativePath } {
-   set xilenv ""
-   if { [info exists ::env(XILINX) ] } {
-      if { [info exists ::env(MYXILINX)] } {
-         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
-      } else {
-         set xilenv $::env(XILINX)
-      }
-   }
-   foreach path [ split $xilenv $::xilinx::path_sep ] {
-      set fullPath [ file join $path $relativePath ]
-      if { [ file exists $fullPath ] } {
-         return $fullPath
-      }
-   }
-   return ""
-}
-
-source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
-
-set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "mem_4k8" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc6slx45-3csg324 VHDL ]
-
-if { $result == 0 } {
-   puts "Core Generator create command completed successfully."
-} elseif { $result == 1 } {
-   puts "Core Generator create command failed."
-} elseif { $result == 3 || $result == 4 } {
-   # convert 'version check' result to real return range, bypassing any messages.
-   set result [ expr $result - 3 ]
-} else {
-   puts "Core Generator create cancelled."
-}
-exit $result
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/edit_mem_4k8.tcl
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/edit_mem_4k8.tcl	(revision 117)
+++ 	(revision )
@@ -1,37 +1,0 @@
-##
-## Core Generator Run Script, generator for Project Navigator edit command
-##
-
-proc findRtfPath { relativePath } {
-   set xilenv ""
-   if { [info exists ::env(XILINX) ] } {
-      if { [info exists ::env(MYXILINX)] } {
-         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
-      } else {
-         set xilenv $::env(XILINX)
-      }
-   }
-   foreach path [ split $xilenv $::xilinx::path_sep ] {
-      set fullPath [ file join $path $relativePath ]
-      if { [ file exists $fullPath ] } {
-         return $fullPath
-      }
-   }
-   return ""
-}
-
-source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
-
-set result [ run_cg_edit "mem_4k8" xc6slx45-3csg324 VHDL ]
-
-if { $result == 0 } {
-   puts "Core Generator edit command completed successfully."
-} elseif { $result == 1 } {
-   puts "Core Generator edit command failed."
-} elseif { $result == 3 || $result == 4 } {
-   # convert 'version check' result to real return range, bypassing any messages.
-   set result [ expr $result - 3 ]
-} else {
-   puts "Core Generator edit cancelled."
-}
-exit $result
Index: OJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.asy
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8.asy	(revision 117)
+++ 	(revision )
@@ -1,41 +1,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 mem_4k8
-RECTANGLE Normal 32 32 544 1376
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName addra[11:0]
-PINATTR Polarity IN
-LINE Wide 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName dina[7:0]
-PINATTR Polarity IN
-LINE Normal 0 144 32 144
-PIN 0 144 LEFT 36
-PINATTR PinName ena
-PINATTR Polarity IN
-LINE Wide 0 208 32 208
-PIN 0 208 LEFT 36
-PINATTR PinName wea[0:0]
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName clka
-PINATTR Polarity IN
-LINE Wide 0 432 32 432
-PIN 0 432 LEFT 36
-PINATTR PinName addrb[11:0]
-PINATTR Polarity IN
-LINE Normal 0 496 32 496
-PIN 0 496 LEFT 36
-PINATTR PinName enb
-PINATTR Polarity IN
-LINE Normal 0 624 32 624
-PIN 0 624 LEFT 36
-PINATTR PinName clkb
-PINATTR Polarity IN
-LINE Wide 576 368 544 368
-PIN 576 368 RIGHT 36
-PINATTR PinName doutb[7:0]
-PINATTR Polarity OUT
-