Changeset 128 for PROJECT_CORE_MPI/MPI_HCL
- Timestamp:
- Mar 19, 2014, 7:50:14 PM (11 years ago)
- Location:
- PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/Test_Timer.gise
r110 r128 27 27 <file xil_pn:fileType="FILE_NCD" xil_pn:name="EX4_FSM_guide.ncd" xil_pn:origination="imported"/> 28 28 <file xil_pn:fileType="FILE_NCD" xil_pn:name="IP_Timer_guide.ncd" xil_pn:origination="imported"/> 29 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="MultiMPITest.bld"/> 30 <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="MultiMPITest.cmd_log"/> 31 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="MultiMPITest.lso"/> 32 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest.ncd" xil_pn:subbranch="Par"/> 33 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="MultiMPITest.ngc"/> 34 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="MultiMPITest.ngd"/> 35 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="MultiMPITest.ngr"/> 36 <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="MultiMPITest.pad"/> 37 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="MultiMPITest.par" xil_pn:subbranch="Par"/> 38 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="MultiMPITest.pcf" xil_pn:subbranch="Map"/> 39 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="MultiMPITest.prj"/> 40 <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="MultiMPITest.ptwx"/> 41 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="MultiMPITest.stx"/> 42 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="MultiMPITest.syr"/> 43 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="MultiMPITest.twr" xil_pn:subbranch="Par"/> 44 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="MultiMPITest.twx" xil_pn:subbranch="Par"/> 45 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="MultiMPITest.unroutes" xil_pn:subbranch="Par"/> 46 <file xil_pn:fileType="FILE_XPI" xil_pn:name="MultiMPITest.xpi"/> 47 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="MultiMPITest.xst"/> 29 48 <file xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest_guide.ncd" xil_pn:origination="imported"/> 49 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="MultiMPITest_map.map" xil_pn:subbranch="Map"/> 50 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="MultiMPITest_map.mrp" xil_pn:subbranch="Map"/> 51 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest_map.ncd" xil_pn:subbranch="Map"/> 52 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="MultiMPITest_map.ngm" xil_pn:subbranch="Map"/> 53 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_map.xrpt"/> 54 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_ngdbuild.xrpt"/> 55 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="MultiMPITest_pad.csv" xil_pn:subbranch="Par"/> 56 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="MultiMPITest_pad.txt" xil_pn:subbranch="Par"/> 57 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_par.xrpt"/> 58 <file xil_pn:fileType="FILE_HTML" xil_pn:name="MultiMPITest_summary.html"/> 59 <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="MultiMPITest_summary.xml"/> 60 <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="MultiMPITest_usage.xml"/> 61 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MultiMPITest_xst.xrpt"/> 30 62 <file xil_pn:fileType="FILE_NCD" xil_pn:name="RAM_v_guide.ncd" xil_pn:origination="imported"/> 63 <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/> 64 <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/> 65 <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> 66 <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/> 67 <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/> 68 <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/> 69 <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="mpi_test.fdo"/> 70 <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/> 71 <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/> 72 <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/> 31 73 </files> 32 74 33 75 <transforms xmlns="http://www.xilinx.com/XMLSchema"> 76 <transform xil_pn:end_ts="1395253035" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1395253035"> 77 <status xil_pn:value="SuccessfullyRun"/> 78 <status xil_pn:value="ReadyToRun"/> 79 </transform> 80 <transform xil_pn:end_ts="1395253035" xil_pn:in_ck="6933023978948769501" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1395253035"> 81 <status xil_pn:value="SuccessfullyRun"/> 82 <status xil_pn:value="ReadyToRun"/> 83 <outfile xil_pn:name="../Core_MPI/CORE_MPI.vhd"/> 84 <outfile xil_pn:name="../Core_MPI/DEMUX1.vhd"/> 85 <outfile xil_pn:name="../Core_MPI/DMA_ARBITER.vhd"/> 86 <outfile xil_pn:name="../Core_MPI/EX1_FSM.vhd"/> 87 <outfile xil_pn:name="../Core_MPI/EX2_FSM.vhd"/> 88 <outfile xil_pn:name="../Core_MPI/EX3_FSM.vhd"/> 89 <outfile xil_pn:name="../Core_MPI/EX4_FSM.vhd"/> 90 <outfile xil_pn:name="../Core_MPI/Ex0_Fsm.vhd"/> 91 <outfile xil_pn:name="../Core_MPI/Ex5_FSM.vhd"/> 92 <outfile xil_pn:name="../Core_MPI/FIFO_64_FWFT.vhd"/> 93 <outfile xil_pn:name="../Core_MPI/FIfo_mem.vhd"/> 94 <outfile xil_pn:name="../Core_MPI/FIfo_proc.vhd"/> 95 <outfile xil_pn:name="../Core_MPI/MPICORETEST.vhd"/> 96 <outfile xil_pn:name="../Core_MPI/MPI_CORE_SCHEDULER.vhd"/> 97 <outfile xil_pn:name="../Core_MPI/MPI_NOC.vhd"/> 98 <outfile xil_pn:name="../Core_MPI/MPI_PKG.vhd"/> 99 <outfile xil_pn:name="../Core_MPI/MPI_RMA.vhd"/> 100 <outfile xil_pn:name="../Core_MPI/MUX1.vhd"/> 101 <outfile xil_pn:name="../Core_MPI/MUX8.vhd"/> 102 <outfile xil_pn:name="../Core_MPI/MultiMPITest.vhd"/> 103 <outfile xil_pn:name="../Core_MPI/Packet_type.vhd"/> 104 <outfile xil_pn:name="../Core_MPI/RAM_32_32.vhd"/> 105 <outfile xil_pn:name="../Core_MPI/RAM_64.vhd"/> 106 <outfile xil_pn:name="../Core_MPI/RAM_MUX.vhd"/> 107 <outfile xil_pn:name="../Core_MPI/SetBit.vhd"/> 108 <outfile xil_pn:name="../Core_MPI/image_pkg.vhd"/> 109 <outfile xil_pn:name="../Core_MPI/load_instr.vhd"/> 110 <outfile xil_pn:name="../Core_MPI/round_robbin_machine.vhd"/> 111 <outfile xil_pn:name="../Core_MPI/test_DMA.vhd"/> 112 <outfile xil_pn:name="../HCL_Arch_conf.vhd"/> 113 <outfile xil_pn:name="../HT_process.vhd"/> 114 <outfile xil_pn:name="../Hold_FSM.vhd"/> 115 <outfile xil_pn:name="../IP_Timer.vhd"/> 116 <outfile xil_pn:name="../NoC/Arbiter.vhd"/> 117 <outfile xil_pn:name="../NoC/CoreTypes.vhd"/> 118 <outfile xil_pn:name="../NoC/Crossbar.vhd"/> 119 <outfile xil_pn:name="../NoC/Crossbit.vhd"/> 120 <outfile xil_pn:name="../NoC/FIFO_256_FWFT.vhd"/> 121 <outfile xil_pn:name="../NoC/FIFO_DP.vhd"/> 122 <outfile xil_pn:name="../NoC/INPUT_PORT_MODULE.vhd"/> 123 <outfile xil_pn:name="../NoC/OUTPUT_PORT_MODULE.vhd"/> 124 <outfile xil_pn:name="../NoC/PortRam.vhd"/> 125 <outfile xil_pn:name="../NoC/Proto_receiv.vhd"/> 126 <outfile xil_pn:name="../NoC/RAM_256.vhd"/> 127 <outfile xil_pn:name="../NoC/SCHEDULER10_10.VHD"/> 128 <outfile xil_pn:name="../NoC/SCHEDULER11_11.VHD"/> 129 <outfile xil_pn:name="../NoC/SCHEDULER12_12.VHD"/> 130 <outfile xil_pn:name="../NoC/SCHEDULER13_13.VHD"/> 131 <outfile xil_pn:name="../NoC/SCHEDULER14_14.VHD"/> 132 <outfile xil_pn:name="../NoC/SCHEDULER15_15.VHD"/> 133 <outfile xil_pn:name="../NoC/SCHEDULER16_16.VHD"/> 134 <outfile xil_pn:name="../NoC/SCHEDULER2_2.VHD"/> 135 <outfile xil_pn:name="../NoC/SCHEDULER3_3.VHD"/> 136 <outfile xil_pn:name="../NoC/SCHEDULER4_4.VHD"/> 137 <outfile xil_pn:name="../NoC/SCHEDULER5_5.VHD"/> 138 <outfile xil_pn:name="../NoC/SCHEDULER6_6.VHD"/> 139 <outfile xil_pn:name="../NoC/SCHEDULER7_7.VHD"/> 140 <outfile xil_pn:name="../NoC/SCHEDULER8_8.VHD"/> 141 <outfile xil_pn:name="../NoC/SCHEDULER9_9.VHD"/> 142 <outfile xil_pn:name="../NoC/SWITCH_GEN.vhd"/> 143 <outfile xil_pn:name="../NoC/SWITCH_GENERIQUE.vhd"/> 144 <outfile xil_pn:name="../NoC/Scheduler.vhd"/> 145 <outfile xil_pn:name="../NoC/conv.vhd"/> 146 <outfile xil_pn:name="../NoC/proto_send.vhd"/> 147 <outfile xil_pn:name="../NoC/stimuli1.vhd"/> 148 <outfile xil_pn:name="../NoC/test_xbar_8x8.vhd"/> 149 <outfile xil_pn:name="../PE.vhd"/> 150 <outfile xil_pn:name="../mpi_test.vhd"/> 151 </transform> 152 <transform xil_pn:end_ts="1395253035" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8801908244967488165" xil_pn:start_ts="1395253035"> 153 <status xil_pn:value="SuccessfullyRun"/> 154 <status xil_pn:value="ReadyToRun"/> 155 </transform> 156 <transform xil_pn:end_ts="1395253035" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="3275490455063375833" xil_pn:start_ts="1395253035"> 157 <status xil_pn:value="SuccessfullyRun"/> 158 <status xil_pn:value="ReadyToRun"/> 159 </transform> 160 <transform xil_pn:end_ts="1395253035" xil_pn:in_ck="-4721685615919775683" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="2807353887341256342" xil_pn:start_ts="1395253035"> 161 <status xil_pn:value="SuccessfullyRun"/> 162 <status xil_pn:value="ReadyToRun"/> 163 <outfile xil_pn:name="ipcore_dir/mem8k8.ngc"/> 164 <outfile xil_pn:name="ipcore_dir/mem8k8.vhd"/> 165 </transform> 166 <transform xil_pn:end_ts="1395253035" xil_pn:in_ck="6976421074370935990" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1395253035"> 167 <status xil_pn:value="SuccessfullyRun"/> 168 <status xil_pn:value="ReadyToRun"/> 169 <outfile xil_pn:name="../Core_MPI/CORE_MPI.vhd"/> 170 <outfile xil_pn:name="../Core_MPI/DEMUX1.vhd"/> 171 <outfile xil_pn:name="../Core_MPI/DMA_ARBITER.vhd"/> 172 <outfile xil_pn:name="../Core_MPI/EX1_FSM.vhd"/> 173 <outfile xil_pn:name="../Core_MPI/EX2_FSM.vhd"/> 174 <outfile xil_pn:name="../Core_MPI/EX3_FSM.vhd"/> 175 <outfile xil_pn:name="../Core_MPI/EX4_FSM.vhd"/> 176 <outfile xil_pn:name="../Core_MPI/Ex0_Fsm.vhd"/> 177 <outfile xil_pn:name="../Core_MPI/Ex5_FSM.vhd"/> 178 <outfile xil_pn:name="../Core_MPI/FIFO_64_FWFT.vhd"/> 179 <outfile xil_pn:name="../Core_MPI/FIfo_mem.vhd"/> 180 <outfile xil_pn:name="../Core_MPI/FIfo_proc.vhd"/> 181 <outfile xil_pn:name="../Core_MPI/MPICORETEST.vhd"/> 182 <outfile xil_pn:name="../Core_MPI/MPI_CORE_SCHEDULER.vhd"/> 183 <outfile xil_pn:name="../Core_MPI/MPI_NOC.vhd"/> 184 <outfile xil_pn:name="../Core_MPI/MPI_PKG.vhd"/> 185 <outfile xil_pn:name="../Core_MPI/MPI_RMA.vhd"/> 186 <outfile xil_pn:name="../Core_MPI/MUX1.vhd"/> 187 <outfile xil_pn:name="../Core_MPI/MUX8.vhd"/> 188 <outfile xil_pn:name="../Core_MPI/MultiMPITest.vhd"/> 189 <outfile xil_pn:name="../Core_MPI/Packet_type.vhd"/> 190 <outfile xil_pn:name="../Core_MPI/RAM_32_32.vhd"/> 191 <outfile xil_pn:name="../Core_MPI/RAM_64.vhd"/> 192 <outfile xil_pn:name="../Core_MPI/RAM_MUX.vhd"/> 193 <outfile xil_pn:name="../Core_MPI/SetBit.vhd"/> 194 <outfile xil_pn:name="../Core_MPI/image_pkg.vhd"/> 195 <outfile xil_pn:name="../Core_MPI/load_instr.vhd"/> 196 <outfile xil_pn:name="../Core_MPI/round_robbin_machine.vhd"/> 197 <outfile xil_pn:name="../Core_MPI/test_DMA.vhd"/> 198 <outfile xil_pn:name="../HCL_Arch_conf.vhd"/> 199 <outfile xil_pn:name="../HT_process.vhd"/> 200 <outfile xil_pn:name="../Hold_FSM.vhd"/> 201 <outfile xil_pn:name="../IP_Timer.vhd"/> 202 <outfile xil_pn:name="../NoC/Arbiter.vhd"/> 203 <outfile xil_pn:name="../NoC/CoreTypes.vhd"/> 204 <outfile xil_pn:name="../NoC/Crossbar.vhd"/> 205 <outfile xil_pn:name="../NoC/Crossbit.vhd"/> 206 <outfile xil_pn:name="../NoC/FIFO_256_FWFT.vhd"/> 207 <outfile xil_pn:name="../NoC/FIFO_DP.vhd"/> 208 <outfile xil_pn:name="../NoC/INPUT_PORT_MODULE.vhd"/> 209 <outfile xil_pn:name="../NoC/OUTPUT_PORT_MODULE.vhd"/> 210 <outfile xil_pn:name="../NoC/PortRam.vhd"/> 211 <outfile xil_pn:name="../NoC/Proto_receiv.vhd"/> 212 <outfile xil_pn:name="../NoC/RAM_256.vhd"/> 213 <outfile xil_pn:name="../NoC/SCHEDULER10_10.VHD"/> 214 <outfile xil_pn:name="../NoC/SCHEDULER11_11.VHD"/> 215 <outfile xil_pn:name="../NoC/SCHEDULER12_12.VHD"/> 216 <outfile xil_pn:name="../NoC/SCHEDULER13_13.VHD"/> 217 <outfile xil_pn:name="../NoC/SCHEDULER14_14.VHD"/> 218 <outfile xil_pn:name="../NoC/SCHEDULER15_15.VHD"/> 219 <outfile xil_pn:name="../NoC/SCHEDULER16_16.VHD"/> 220 <outfile xil_pn:name="../NoC/SCHEDULER2_2.VHD"/> 221 <outfile xil_pn:name="../NoC/SCHEDULER3_3.VHD"/> 222 <outfile xil_pn:name="../NoC/SCHEDULER4_4.VHD"/> 223 <outfile xil_pn:name="../NoC/SCHEDULER5_5.VHD"/> 224 <outfile xil_pn:name="../NoC/SCHEDULER6_6.VHD"/> 225 <outfile xil_pn:name="../NoC/SCHEDULER7_7.VHD"/> 226 <outfile xil_pn:name="../NoC/SCHEDULER8_8.VHD"/> 227 <outfile xil_pn:name="../NoC/SCHEDULER9_9.VHD"/> 228 <outfile xil_pn:name="../NoC/SWITCH_GEN.vhd"/> 229 <outfile xil_pn:name="../NoC/SWITCH_GENERIQUE.vhd"/> 230 <outfile xil_pn:name="../NoC/Scheduler.vhd"/> 231 <outfile xil_pn:name="../NoC/conv.vhd"/> 232 <outfile xil_pn:name="../NoC/proto_send.vhd"/> 233 <outfile xil_pn:name="../NoC/stimuli1.vhd"/> 234 <outfile xil_pn:name="../NoC/test_xbar_8x8.vhd"/> 235 <outfile xil_pn:name="../PE.vhd"/> 236 <outfile xil_pn:name="../mpi_test.vhd"/> 237 <outfile xil_pn:name="ipcore_dir/mem8k8.vhd"/> 238 </transform> 239 <transform xil_pn:end_ts="1395253100" xil_pn:in_ck="8499758427208669482" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="-9125186505467785876" xil_pn:start_ts="1395253035"> 240 <status xil_pn:value="SuccessfullyRun"/> 241 <status xil_pn:value="ReadyToRun"/> 242 <outfile xil_pn:name="mpi_test.fdo"/> 243 </transform> 244 <transform xil_pn:end_ts="1395253902" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1395253902"> 245 <status xil_pn:value="SuccessfullyRun"/> 246 <status xil_pn:value="ReadyToRun"/> 247 </transform> 248 <transform xil_pn:end_ts="1395253902" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1582102620978348987" xil_pn:start_ts="1395253902"> 249 <status xil_pn:value="SuccessfullyRun"/> 250 <status xil_pn:value="ReadyToRun"/> 251 </transform> 252 <transform xil_pn:end_ts="1395253903" xil_pn:in_ck="-4721685615919775683" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="2807353887341256342" xil_pn:start_ts="1395253902"> 253 <status xil_pn:value="SuccessfullyRun"/> 254 <status xil_pn:value="ReadyToRun"/> 255 <outfile xil_pn:name="ipcore_dir/mem8k8.ngc"/> 256 <outfile xil_pn:name="ipcore_dir/mem8k8.vhd"/> 257 </transform> 34 258 <transform xil_pn:end_ts="1393949142" xil_pn:in_ck="2234850181043412427" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1393949142"> 35 259 <status xil_pn:value="SuccessfullyRun"/> 36 260 <status xil_pn:value="ReadyToRun"/> 37 261 </transform> 262 <transform xil_pn:end_ts="1395253903" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8804766714685316537" xil_pn:start_ts="1395253903"> 263 <status xil_pn:value="SuccessfullyRun"/> 264 <status xil_pn:value="ReadyToRun"/> 265 </transform> 266 <transform xil_pn:end_ts="1395253903" xil_pn:in_ck="-1335772100541163525" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1395253903"> 267 <status xil_pn:value="SuccessfullyRun"/> 268 <status xil_pn:value="ReadyToRun"/> 269 </transform> 270 <transform xil_pn:end_ts="1395253903" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4624523187203829856" xil_pn:start_ts="1395253903"> 271 <status xil_pn:value="SuccessfullyRun"/> 272 <status xil_pn:value="ReadyToRun"/> 273 </transform> 274 <transform xil_pn:end_ts="1395254070" xil_pn:in_ck="8499758427208669482" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3604278402045306212" xil_pn:start_ts="1395253903"> 275 <status xil_pn:value="SuccessfullyRun"/> 276 <status xil_pn:value="WarningsGenerated"/> 277 <status xil_pn:value="ReadyToRun"/> 278 <status xil_pn:value="OutOfDateForOutputs"/> 279 <status xil_pn:value="OutputChanged"/> 280 <outfile xil_pn:name="MultiMPITest.lso"/> 281 <outfile xil_pn:name="MultiMPITest.ngc"/> 282 <outfile xil_pn:name="MultiMPITest.ngr"/> 283 <outfile xil_pn:name="MultiMPITest.prj"/> 284 <outfile xil_pn:name="MultiMPITest.stx"/> 285 <outfile xil_pn:name="MultiMPITest.syr"/> 286 <outfile xil_pn:name="MultiMPITest.xst"/> 287 <outfile xil_pn:name="MultiMPITest_xst.xrpt"/> 288 <outfile xil_pn:name="_xmsgs/xst.xmsgs"/> 289 <outfile xil_pn:name="webtalk_pn.xml"/> 290 <outfile xil_pn:name="xst"/> 291 </transform> 292 <transform xil_pn:end_ts="1395254071" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4542759591300251492" xil_pn:start_ts="1395254070"> 293 <status xil_pn:value="SuccessfullyRun"/> 294 <status xil_pn:value="ReadyToRun"/> 295 </transform> 296 <transform xil_pn:end_ts="1395254085" xil_pn:in_ck="-8086002020225495248" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-5155457213437603231" xil_pn:start_ts="1395254071"> 297 <status xil_pn:value="SuccessfullyRun"/> 298 <status xil_pn:value="ReadyToRun"/> 299 <outfile xil_pn:name="MultiMPITest.bld"/> 300 <outfile xil_pn:name="MultiMPITest.ngd"/> 301 <outfile xil_pn:name="MultiMPITest_ngdbuild.xrpt"/> 302 <outfile xil_pn:name="_ngo"/> 303 <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> 304 </transform> 305 <transform xil_pn:end_ts="1395254373" xil_pn:in_ck="2034496922163271928" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7937066311386137899" xil_pn:start_ts="1395254085"> 306 <status xil_pn:value="SuccessfullyRun"/> 307 <status xil_pn:value="ReadyToRun"/> 308 <outfile xil_pn:name="MultiMPITest.pcf"/> 309 <outfile xil_pn:name="MultiMPITest_map.map"/> 310 <outfile xil_pn:name="MultiMPITest_map.mrp"/> 311 <outfile xil_pn:name="MultiMPITest_map.ncd"/> 312 <outfile xil_pn:name="MultiMPITest_map.ngm"/> 313 <outfile xil_pn:name="MultiMPITest_map.xrpt"/> 314 <outfile xil_pn:name="MultiMPITest_summary.xml"/> 315 <outfile xil_pn:name="MultiMPITest_usage.xml"/> 316 <outfile xil_pn:name="_xmsgs/map.xmsgs"/> 317 </transform> 318 <transform xil_pn:end_ts="1395254509" xil_pn:in_ck="-7713434038111607791" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1395254373"> 319 <status xil_pn:value="SuccessfullyRun"/> 320 <status xil_pn:value="WarningsGenerated"/> 321 <status xil_pn:value="ReadyToRun"/> 322 <outfile xil_pn:name="MultiMPITest.ncd"/> 323 <outfile xil_pn:name="MultiMPITest.pad"/> 324 <outfile xil_pn:name="MultiMPITest.par"/> 325 <outfile xil_pn:name="MultiMPITest.ptwx"/> 326 <outfile xil_pn:name="MultiMPITest.unroutes"/> 327 <outfile xil_pn:name="MultiMPITest.xpi"/> 328 <outfile xil_pn:name="MultiMPITest_pad.csv"/> 329 <outfile xil_pn:name="MultiMPITest_pad.txt"/> 330 <outfile xil_pn:name="MultiMPITest_par.xrpt"/> 331 <outfile xil_pn:name="_xmsgs/par.xmsgs"/> 332 </transform> 333 <transform xil_pn:end_ts="1395254509" xil_pn:in_ck="2034496922163271796" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1395254482"> 334 <status xil_pn:value="SuccessfullyRun"/> 335 <status xil_pn:value="ReadyToRun"/> 336 <outfile xil_pn:name="MultiMPITest.twr"/> 337 <outfile xil_pn:name="MultiMPITest.twx"/> 338 <outfile xil_pn:name="_xmsgs/trce.xmsgs"/> 339 </transform> 38 340 </transforms> 39 341 -
PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/Test_Timer.xise
r111 r128 622 622 <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> 623 623 <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> 624 <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/mpi_test " xil_pn:valueState="non-default"/>625 <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work. mpi_test" xil_pn:valueState="non-default"/>624 <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/mpi_test/uut" xil_pn:valueState="non-default"/> 625 <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.MultiMPITest" xil_pn:valueState="non-default"/> 626 626 <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> 627 627 <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> … … 646 646 <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> 647 647 <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/> 648 <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work. mpi_test" xil_pn:valueState="default"/>648 <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.MultiMPITest" xil_pn:valueState="default"/> 649 649 <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> 650 650 <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
Note: See TracChangeset
for help on using the changeset viewer.