Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/CORE_MPI.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/CORE_MPI.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/CORE_MPI.vhd (revision 138) @@ -0,0 +1,997 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM NGOUNOU +-- +-- Create Date: 05:52:25 06/21/2011 +-- Design Name: +-- Module Name: CORE_MPI - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +Library NocLib; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity CORE_MPI is + Port ( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + clkout : out std_logic; + instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + instruction_en : in STD_LOGIC; --valide l'instruction + instruction_fifo_full : out STD_LOGIC; + ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + barrier_completed : out STD_LOGIC; + packet_received : out STD_LOGIC; + packet_ack : in std_logic; + PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); --le resultat de l'exécution + ram_we : out STD_LOGIC; + ram_en : out STD_LOGIC; + ram_address_rd : out STD_LOGIC_VECTOR (15 downto 0); + ram_address_wr : out STD_LOGIC_VECTOR (15 downto 0); + ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + switch_port_in_cmd_en : out std_logic; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_in_wr_en : out STD_LOGIC; + switch_port_in_full : in STD_LOGIC; + switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_out_rd_en : out STD_LOGIC; + switch_port_in_empty : in STD_LOGIC; + switch_port_out_data_vailaible : in STD_LOGIC + ); + +end CORE_MPI; + +architecture Structural of CORE_MPI is +--déclaration des types +type Type_Noc is +record + port_in_cmd_en : std_logic; + port_out_data : STD_LOGIC_VECTOR (Word-1 downto 0); + port_in_wr_en : STD_LOGIC; + port_in_empty : STD_LOGIC; + port_in_full : STD_LOGIC; + port_in_data : STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_rd_en : STD_LOGIC; + port_out_data_available : STD_LOGIC; +end record; +-- déclaration des composants MPI + +COMPONENT FIFO_64_FWFT + PORT( + clk : IN std_logic; + din : IN std_logic_vector(Word-1 downto 0); + rd_en : IN std_logic; + srst : IN std_logic; + wr_en : IN std_logic; + dout : OUT std_logic_vector(Word-1 downto 0); + empty : OUT std_logic; + full : OUT std_logic + ); +END COMPONENT; +COMPONENT load_instr + Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + instruction_ack : out STD_LOGIC; + fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_wr :out std_logic; + fifo_full : in STD_LOGIC; + copying : out std_logic; + Ram_rd_en : out STD_LOGIC; + ram_address_rd : buffer STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0)); +end component; +COMPONENT DMA_ARBITER + PORT( + + clk : IN std_logic; + reset : IN std_logic; + dma_rd_request : IN std_logic_vector(3 downto 0); + data_wr_in : IN std_logic_vector(Word-1 downto 0); + data_rd_out : out std_logic_vector(Word-1 downto 0); + address_rd : IN std_logic_vector(15 downto 0); + address_wr : IN std_logic_vector(15 downto 0); + + dma_wr_request : IN std_logic_vector(3 downto 0); + address_out_rd : OUT std_logic_vector(15 downto 0); + address_out_wr : OUT std_logic_vector(15 downto 0); + ram_en : OUT std_logic; + ram_we : OUT std_logic; + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + data_wr_mem : OUT std_logic_vector(Word-1 downto 0); + data_rd_mem : IN std_logic_vector(Word-1 downto 0); + dma_wr_grant : OUT std_logic_vector(3 downto 0); + dma_rd_grant : OUT std_logic_vector(3 downto 0) + ); +END COMPONENT; + +COMPONENT EX1_FSM + PORT( + clk : IN std_logic; + reset : IN std_logic; + + pid : in std_logic_vector (3 downto 0); --port id + nprocs : in std_logic_vector (3 downto 0); -- la taille du Noc + instruction : in std_logic_vector(Word-1 downto 0); + instruction_en : in std_logic; + fifo_empty : IN std_logic; + fifo_data_out : IN std_logic_vector(Word-1 downto 0); + fifo_rd_en : OUT std_logic; + fifo_src : IN STD_LOGIC; + ram_data_in : IN std_logic_vector(Word-1 downto 0); + ram_data_out : out std_logic_vector(Word-1 downto 0); + dma_rd_grant : IN std_logic; + dma_wr_grant : IN std_logic; + dma_wr_request : OUT std_logic; + dma_rd_request : OUT std_logic; + ram_address : OUT std_logic_vector(15 downto 0); + ram_rd,ram_wr : out std_logic; + Snd_Data : IN Typ_PortIO(0 to 3); + Snd_Start : IN std_logic; + Snd_Ack : OUT std_logic; + priority_rotation : OUT std_logic; + + switch_port_in_data : OUT std_logic_vector(Word-1 downto 0); + switch_port_in_wr_en : OUT std_logic; + switch_port_in_full : IN std_logic; + Result :out std_logic_vector(Word-1 downto 0); + Ready : out std_logic; + AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic -- état de la Lib + ); + END COMPONENT; + +COMPONENT EX2_FSM + PORT( + clk : IN std_logic; + reset : IN std_logic; + + instruction_en: in std_logic; + Initialized : in std_logic; + + switch_port_out_rd_en : OUT std_logic ; + switch_data_available : IN std_logic; + switch_port_out_data : IN std_logic_vector(Word-1 downto 0); + AppRank : in STD_LOGIC_VECTOR; + AppSize : in STD_LOGIC_VECTOR; + dma_wr_grant : IN std_logic; + dma_wr_request : OUT std_logic; + dma_rd_grant : IN std_logic; + dma_rd_request : OUT std_logic; + ram_address : OUT std_logic_vector(15 downto 0); + ram_rd,ram_wr : out std_logic; + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_full : IN std_logic; + Rec_Rdy : OUT std_logic; + Rec_Data : buffer Typ_PortIO(0 to 3); + Rec_Ack : IN std_logic; + fifo_data : OUT std_logic_vector(Word-1 downto 0); + fifo_wr_en : OUT std_logic; + --fifo_out : out std_logic_vector; + Result : out STD_LOGIC_VECTOR (Word-1 downto 0); + packet_received : OUT std_logic; + packet_ack : IN std_logic; + barrier_completed : OUT std_logic; + Ready : Out std_logic; + AppInitAck : in std_logic; + AppInitReq : out std_logic + ); + END COMPONENT; + + + COMPONENT EX3_FSM + PORT( + instruction : IN std_logic_vector(Word-1 downto 0); + clk : IN std_logic; + reset : IN std_logic; + Ismain :in std_logic; + ResOut : OUT std_logic_vector(Word-1 downto 0) + + ); + END COMPONENT; + + COMPONENT EX4_FSM + PORT( + Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); --permet de lire le FIFO + Instruction_En : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + ResultOut : out STD_LOGIC_VECTOR (Word-1 downto 0); + Result_En : out STD_LOGIC; + Ready : out STD_LOGIC; + NocSize : out STD_LOGIC_VECTOR; + AppRank : out STD_LOGIC_VECTOR; + AppSize : out STD_LOGIC_VECTOR; + IsMain : out STD_LOGIC; + I_fifo_full :in STD_LOGIC; + Snd_Ack : IN std_logic; + Rec_Rdy : IN std_logic; + Rec_Data : IN Typ_PortIO(0 to 3); + Snd_data : OUT Typ_PortIO(0 to 3); + Snd_Start : buffer std_logic; + Rec_Ack : OUT std_logic; + I_fifo_wr_en: out STD_LOGIC; + I_fifo_data_in :out STD_LOGIC_vector(Word-1 downto 0); + Initialized : out STD_LOGIC; + dma_wr_request : out std_logic; + dma_rd_request : out std_logic; + dma_wr_grant : in std_logic; + dma_rd_grant : in std_logic; + Ram_address : out STD_LOGIC_VECTOR (15 downto 0); --accès au stockage + Ram_wr : out STD_LOGIC; --activation de l'écriture en RAM + Ram_Data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);--données des ports + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + AppAck : in STD_LOGIC; + AppReq : in STD_LOGIC; + PortId : out STD_LOGIC_VECTOR(3 downto 0); + port_in_cmd_en : out STD_LOGIC; + port_in_wr_en : out STD_LOGIC; + port_in_empty : in STD_LOGIC; + port_in_full : in STD_LOGIC; + port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_rd_en : out STD_LOGIC; + port_out_data_available : in STD_LOGIC); + END COMPONENT; + + COMPONENT EX0_FSM + PORT( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + + Initialized : in STD_LOGIC; + Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + instruction_en: in STD_LOGIC; + + ClkRate : in STD_LOGIC_VECTOR ; + uTimeResult : out STD_LOGIC_VECTOR; + TickResult : out STD_LOGIC_VECTOR + ); + END COMPONENT; + + +COMPONENT MPI_CORE_SCHEDULER + PORT( + clk : IN std_logic; + reset : IN std_logic; + priority_rotation : IN std_logic; + instruction_fifo_empty : IN std_logic; + instruction_fifo_rd_en : OUT std_logic; + instruction_fifo_data : IN std_logic_vector(Word-1 downto 0); + instruction_available : OUT std_logic; + + get_request_fifo_empty : IN std_logic; + get_request_fifo_rd_en : OUT std_logic; + get_request_fifo_data : IN std_logic_vector(Word-1 downto 0); + + fifo_rd_en : IN std_logic; + fifo_empty : OUT std_logic; + fifo_selected : OUT std_logic; + + data_out : OUT std_logic_vector(Word-1 downto 0) + + + ); + END COMPONENT; + +-- declaration des signaux d'interconnexion entre les modules du coresignal fifo_sel: std_logic; -- indique l'un des deux fifos d'instructions qui sont prêts +signal fifo_instr : std_logic; -- une instruction est prête dans les fifos d'instruction + + +signal scheduler_fifo_empty : std_logic; +signal scheduler_data_out : std_logic_vector(Word-1 downto 0); +signal dma_arbiter_data_rd_out : std_logic_vector(Word-1 downto 0); + +signal scheduler_priority_rotation : std_logic; +signal scheduler_rd_en : std_logic; + +signal dma_data_rd,dma_data_wr : std_logic_vector(Word-1 downto 0); -- bus à 3 états +signal dma_rd_address,dma_rd_address1,dma_rd_address2 : std_logic_vector(15 downto 0); -- ces bus doivent être gérés en logique 3 états! +signal dma_rd_address3 : std_logic_vector(15 downto 0); +signal dma_wr_address1,dma_wr_address3 : std_logic_vector(15 downto 0); +signal dma_wr_address2,dma_wr_address4 : std_logic_vector(15 downto 0); +signal dma_wr_address : std_logic_vector(15 downto 0); +signal switch_port_in_data_signal : std_logic_vector(Word-1 downto 0); +signal ram_data_out_signal : std_logic_vector(Word-1 downto 0); +signal weram,rdram,ram_wev,ram_env :std_logic:='0'; + +signal i_fifo2_signal : std_logic_vector(Word-1 downto 0); +signal Ex_EN : std_logic_vector(4 downto 1):=(others=>'0'); --active les sous MAE permettant de décoder les instructions MPI +signal Res4_en:std_logic;--acquittement du réusltat du module n°4 +signal Ex4_en,Ex1_RDY,Ex2_RDY,EX3_RDY,EX4_RDY : std_logic:='0'; -- indique la fin de l'exécution de la MAE +signal ex1_ram_rd,ex2_ram_rd,ex4_ram_rd ,Exi_ram_rd: std_logic:='0' ; -- validation lecture des données en RAM +signal ex1_ram_wr,ex2_ram_wr,ex4_ram_wr,Exi_ram_wr : std_logic :='0'; -- validation écriture des données en RAM +signal Exi_busy : std_logic:='0'; +signal Ex1_Result,Ex2_Result,Ex4_result : std_logic_vector(Word-1 downto 0); +signal Instr_in : STD_LOGIC_VECTOR (Word-1 downto 0); +--================interface DMA avec les modules ====================================== +signal dma_data_in,Dma_data_in1,dma_data_in2,dma_data_in4 : std_logic_vector(Word-1 downto 0); +signal dma_data_out : std_logic_vector(Word-1 downto 0); +signal dma_rd_request :std_logic_vector(4 downto 1):=(others=>'0'); +signal dma_wr_request :std_logic_vector(4 downto 1):=(others=>'0'); +signal dma_wr_grant,dma_rd_grant:std_logic_vector(4 downto 1); +-- +--====================================================================================== +--connexion au switch + +signal Noc1,NOC2,NOC3 : Type_Noc; -- regroupement des signaux qui vont au Noc + +--================================================================ +--déclaration des signaux d'état du Core +signal IsMain,SizeSet,RankSet,Initialized,AppReq,AppAck:std_logic; +signal InitReq,InitReq1,InitReq2 :std_logic:='0'; -- demande d'initialisation +signal InitAck,IAck,Ilatch : std_logic:='0'; +signal MPISize,MyRank : std_logic_vector(3 downto 0); +signal LibState: std_logic_vector(Word-1 downto 0):=(others=>'0'); --ready,receiving,sending,spawning,rwaiting,swaiting,... +signal NocSize :std_logic_vector(3 downto 0):=(others=>'0'); +Signal PortId : std_logic_vector(3 downto 0); +Signal uClkRate : std_logic_vector(Word-1 downto 0):="00011010"; --50 Mhz +signal uTimeCount :std_logic_vector(31 downto 0):=(others=>'0'); +signal TickCount : std_logic_vector(31 downto 0):=(others=>'0'); +signal RankSize: std_logic_vector(Word-1 downto 0):=(others=>'0'); +--======================================================== +--déclaration des signaux permettant d'activer le module +signal AdrSelect : std_logic_vector(ADRLEN-1 downto 0); +--======================================================== +--signal PushOut_d,RankSize,TickUsOut:std_logic_vector; --résultat de l'execution des commandes mpi +--======================================================== +--connexion avec les FIFO instructions +signal fifo1_wr : std_logic; +signal fifo1_din : std_logic_vector (Word-1 downto 0); +signal fifo_sel : std_logic; --permet d'arbitrer la priorité de lecture entre les deux fifos +signal i_fifo1_rd_en : std_logic; +signal fifo1_full : std_logic; +signal i_fifo1_empty : std_logic; +signal i_fifo1_data_out : std_logic_vector(Word-1 downto 0); +signal i_fifo2_rd_en : std_logic; +signal i_fifo2_data_out : std_logic_vector(Word-1 downto 0); +signal i_fifo2_data_in : std_logic_vector(Word-1 downto 0); +signal i_fifo2_wr_en : std_logic; +signal i_fifo2_empty : std_logic; +signal i_fifo2_full : std_logic; +signal Ex2_i_fifo2_data_in : std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal Ex2_i_fifo2_wr_en : std_logic:='0'; +--signaux pour les données entre modules +signal Snd_Ack :std_logic; +signal Rec_Rdy : std_logic; +signal Rec_Data : Typ_PortIO(0 to 3); +signal Snd_data : Typ_PortIO(0 to 3); +signal Snd_Start : std_logic; +signal Rec_Ack : std_logic; +--signal i_fifo2_empty : std_logic; +--signal i_fifo2_full : std_logic; +signal Ex4_i_fifo2_data_in : std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal Ex4_i_fifo2_wr_en : std_logic:='0'; +--signal i_fifo2_empty : std_logic; +--signal i_fifo2_full : std_logic; +-- signaux pour la gestion des MAE +signal n,n_i :natural range 0 to 7:=0; +signal St_Ex1,St_Ex2,St_Ex4:natural range 0 to 7:=0; +signal Next_St_Ex1,Next_St_Ex2,Next_St_Ex4:natural range 0 to 7:=0; +--=========================================================== + +begin +--switch_port_in_data_signal <= ; +--switch_port_out_data_signal <= ; +-- istanciation des composants du core MPI +Instruction_Fifo1: FIFO_64_FWFT PORT MAP( + clk =>clk, + din =>fifo1_din, + rd_en => i_fifo1_rd_en, + srst => reset, + wr_en => fifo1_wr, + dout =>i_fifo1_data_out, + empty => i_fifo1_empty, + full => fifo1_full + ); + +Instruction_Fifo2: FIFO_64_FWFT PORT MAP( + clk =>clk, + din => i_fifo2_data_in , + rd_en =>i_fifo2_rd_en, + srst =>reset, + wr_en =>i_fifo2_wr_en, + dout =>i_fifo2_data_out, + empty =>i_fifo2_empty, + full => i_fifo2_full + ); +LD_instr:load_instr PORT MAP ( + + Instruction =>Instruction, + Instruction_en =>Instruction_en, + clk =>clk, + reset =>reset, + dma_rd_grant =>dma_rd_grant(3), + dma_rd_request =>dma_rd_request(3), + copying=> Exi_busy, + instruction_ack =>iack, --indique la fin de la copie d'une instruction dans le FIFO + fifo_din => fifo1_din, + fifo_wr => fifo1_wr, + fifo_full =>fifo1_full, + Ram_rd_en=> Exi_ram_rd, + ram_address_rd => dma_rd_address3, + ram_data =>dma_data_out --sortie DMA +); + +pushout(0)<=ILatch; +pushout(1)<=IsMain; +pushout(2)<=SizeSet; +pushout(3)<=Ex4_result(6); --Spawn in progress on main +pushout(4)<=Initialized; +pushout(5)<=Ex1_result(1); -- +pushout(6)<=LibState(3); --Spawned child +pushout(7)<=Ex4_result(7); --Spawn complete +MPI_CORE_EX0_FSM: EX0_FSM PORT MAP( + instruction => i_fifo1_data_out, + instruction_en=> '1', + uTimeResult => uTimeCount, + TickResult => TickCount, + Initialized => Initialized, -- indique si la l'appel à init a été concluant + ClkRate => uClkRate, + clk =>clk , + reset => reset + ); +MPI_CORE_EX1_FSM: EX1_FSM PORT MAP( + clk =>clk , + reset =>reset, + pid => MyRank, --port Id + nprocs=>MPISize, -- à revoir dans certains cas ou tous les PEs ne sont pas connectés + fifo_empty => scheduler_fifo_empty , + fifo_data_out =>scheduler_data_out, + fifo_rd_en =>scheduler_rd_en, + fifo_src =>fifo_sel, + priority_rotation => scheduler_priority_rotation, + + instruction_en=>Ex_en(1), --active le module + Instruction => Instruction, + switch_port_in_full =>Noc1.port_in_full, --ces signaux doivent être contrôlés en 3 state logic + switch_port_in_data =>Noc1.port_in_data, + switch_port_in_wr_en =>Noc1.Port_in_wr_en , + + Snd_Data =>Snd_Data, + Snd_Start =>Snd_start, + Snd_Ack =>Snd_ack, + Ram_rd => ex1_ram_rd, + Ram_wr =>ex1_ram_wr, + ram_data_in =>dma_data_out, + Ram_data_out =>dma_data_in1, + ram_address=>dma_wr_address1, + --ram_address =>dma_rd_address2, --la même adresse sert pour la lecture ou l'écriture + dma_rd_request =>dma_rd_request(1), + dma_wr_request =>dma_wr_request(1), + dma_rd_grant =>dma_rd_grant(1) , + dma_wr_grant =>dma_wr_grant(1) , + + AppInitReq => InitReq1, -- requête d'initialisation de l'application + AppInitAck =>Res4_En , -- Acquitement d'initialisation + Initialized=>Initialized, -- état de la Lib + Result => Ex1_Result, -- le résultat de l'exécution + Ready=> Ex1_Rdy + ); +instruction_fifo_full<=fifo1_full; +dma_rd_address1<=dma_wr_address1; --la même adresse sert pour la lecture ou l'écriture en RAM +Exi_sync :process(reset,clk) + +begin + if rising_edge(clk) then + if reset='1' then + St_Ex2<=0; + St_Ex1<=0; + St_Ex4<=0; + Ilatch<='0'; + n<=0; + else + St_Ex2<=Next_St_Ex2; + St_Ex1<=Next_St_Ex1; + St_Ex4<=Next_St_Ex4; + ILatch<=Iack; + n<=n_i; + end if; +end if; +End process Exi_sync; +-- détermination de l'activation des module +--scheduler_priority_rotation<=not(Ex1_rdy); +Ex1_Act:process(ST_Ex1,Initialized,fifo_instr,n,InitReq,Ex4_rdy,Ex1_rdy,Ex2_rdy)--A qoui sert encore ce processus (26/10/12) ???? +variable c_cyl:natural range 0 to 15:=0; +begin + if reset='1' then + Next_St_ex1<=0; + c_cyl:=0; +else -- cette machie à état permet de distinguer les activations de Ex4 et Ex1 + case St_ex1 is + when 0 => if InitReq='1' and Initialized='0' then + Next_St_ex1<=1; + elsif Initialized='1' then + Next_St_ex1 <=2; + elsif fifo_instr='1' then --cas d'une instruction directe qui est présente + --if fifo_sel='0' then + Next_St_ex1 <=2; + --end if; + end if; + + when 1 => if Ex4_Rdy='1' then + Next_St_ex1<=4; + end if; + when 2 => if Ex1_rdy='0' then --ex1 est libre et actif + Next_St_ex1<=3; + end if; + + when 3 => if Ex1_rdy='1' and Initialized='0'then --ex1 est occupé et actif + Next_St_ex1<=0; + elsif Ex1_rdy='1' and Initialized='1' then + Next_St_ex1<=2; + end if; + + when 4 => if Ex2_rdy='0' then --s'il y a un message du réseau + --compter quelques cycles d'horloges pour attendre initreq2 + if n=4 then + Next_St_ex1<=0; + n_i<=0; + else + n_i<=n+1; + end if; + else + Next_St_ex1<=0; + end if; + + when others => + Next_St_ex1<=0; + end case; +end if; +end process ex1_Act; + +ex1_v:process(St_Ex1) + begin + case St_Ex1 is + when 0 => + Ex_en(1)<='0'; + when 1 => + Ex_en(1)<='0'; + when 2|3 => + Ex_en(1)<='1'; + when others => + Ex_en(1)<='0'; + end case; + +end process ex1_v; + +Ex2_nextState:Process(reset,st_Ex2, Ex4_rdy,Initialized,Ex2_Result,Ex2_rdy) --active la réception lorsqu' Put ou un Get ou un Init a été effectué +begin +Next_St_Ex2<=st_Ex2; +Case st_Ex2 is + +when 0 => + if Initialized='1' and Ex4_rdy='1' then --- Ex1_result(0)='1' or Ex1_result(1)='1' or Ex1_result(2)='1' then + Next_St_Ex2<=1; --active la réception des mesages sur le noeud. + + else + Next_St_Ex2<=0; + end if; +When 1 => + if Ex2_rdy='0' then + Next_St_Ex2<=2; + end if; +When 2 => + if Ex2_rdy='1' then + Next_St_Ex2<=0; + end if; +when others => + Next_St_Ex2<=0; + end case; +end process; +Ex2_val:Process(st_Ex2,Ex4_result) -- + +begin +Case st_Ex2 is + +when 0 => +Ex_en(2)<='0'; +--LibState(3)<='0'; +when 1|2 => + Ex_en(2) <='1'; +when 3|4|5|6|7 => + Ex_en(2)<='0'; +when others=> + Ex_en(2)<='0'; +end case; + if rising_edge(Ex4_result(1)) then + LibState(3)<='1'; --spawn a été détecté. + end if; +end process; + +Ex_en_proc:process (clk,reset) +begin + if rising_edge(clk) then + if reset='1' then + Ex4_en<='0'; + else + + if Ex_en(4)='1' then + Ex4_en<='1'; --synchro + else + Ex4_en<='0'; --synchro + end if; + end if; + end if; +end process; +Ex4_Active:process (St_Ex4,initreq1,initreq2,Ex1_rdy,Initialized,Res4_en) +begin + +case St_Ex4 is + when 0 => + if (InitReq1='1') then + Next_St_Ex4<=1; + elsif InitReq2='1' then --le module 1 n'est pas actif + Next_St_Ex4<=2; + else + Next_St_Ex4<=0; + end if; + when 1 => + If Res4_en='1' then --fin de l'exécution du module + Next_St_Ex4<=3; + end if; + when 2 => + if Res4_en='1' then --Ex2_result(0)='1' + Next_St_Ex4<=4; + end if; + when 3 => + if initreq1='0' then + Next_St_Ex4<=5; + end if; + when 4 => + if initreq2='0' then + Next_St_Ex4<=5; + end if; + when 5 => + Next_St_Ex4<=0; + when others => + Next_St_Ex4<=0; + end case; + +end process Ex4_active; + +Ex4_active_val:process (st_Ex4) +begin + case St_Ex4 is + when 0 => + AppReq<='0'; + InitReq<='0';Ex_en(4)<='0'; + AppAck<='0'; + when 1 => + AppReq<='1'; + InitReq<='1'; + Ex_en(4)<='1'; + AppAck<='0'; + when 2 => + AppReq<='1'; + InitReq<='1'; + Ex_en(4)<='1'; + AppAck<='0'; + when 3 => + AppReq<='0'; + InitReq<='0'; + Ex_en(4)<='0'; + AppAck<='1'; + when 4 => + AppReq<='0'; + InitReq<='0'; + Ex_en(4)<='0'; + AppAck<='1'; + when 5 => + AppReq<='0'; + InitReq<='0';Ex_en(4)<='0'; + AppAck<='1'; + when others => + AppReq<='0'; + InitReq<='0'; + AppAck<='0'; + Ex_en(4)<='0'; + end case ; +-- Appreq<=Ex_en(4); --signal d'activation de la MAE Init +--InitReq<=(not(Initialized) and InitReq1) or InitReq2; -- deux cas permettent d'activer l'initialisation +--AppAck<=Ex1_result(0) or Ex2_result(0); -- signal init completed +end process Ex4_active_val; +--Ex_en(2)<=Initialized; --- Me pose des soucis en ce moment ??? +Ex_en(3)<='0'; +--Ex_en(4)<= '1' when InitReq='1' else '0'; + +-- soit une requête du PE soit une requête du Core + + +MPI_CORE_EX2_FSM: EX2_FSM PORT MAP( + + clk =>clk, + reset =>reset, + instruction_en=>Ex_en(2), + Ready =>Ex2_rdy, --signale que le module est disponible + fifo_full =>i_fifo2_full, + + fifo_wr_en => Ex2_i_fifo2_wr_en, + fifo_data => Ex2_i_fifo2_data_in, + + switch_port_out_rd_en => Noc2.port_out_rd_en, + switch_data_available =>Noc2.port_out_data_available, + switch_port_out_data =>Noc2.port_out_data , + + Rec_Rdy => Rec_Rdy, + Rec_Data =>Rec_Data, + Rec_Ack =>Rec_Ack, + -- il manque un signal pour valider l'accès à la RAM + dma_wr_request =>dma_wr_request(2), + dma_wr_grant =>dma_wr_grant(2), + dma_rd_request =>dma_rd_request(2), + dma_rd_grant =>dma_rd_grant(2), + ram_address =>dma_wr_address2, + Ram_rd => ex2_ram_rd, + Ram_wr =>ex2_ram_wr, + Ram_data_out=> Dma_data_out, + Ram_data_in => Dma_data_in2, + packet_received =>packet_received, + packet_ack => packet_ack, + barrier_completed =>barrier_completed, + AppRank =>MyRank, + AppSize =>MPISize, + AppInitReq => InitReq2, -- requête d'initialisation de l'application + AppInitAck =>Res4_En , -- Acquitement d'initialisation + Initialized=>Initialized, + Result => Ex2_Result -- le résultat de l'exécution + ); +Dma_rd_address2<=Dma_wr_address2; +ICI_MPI_CORE_EX3_FSM: EX3_FSM PORT MAP( + instruction => x"00", --pas utiliser + ResOut => RankSize, + clk =>clk , + IsMain=>IsMain, + reset => reset + ); +MPI_CORE_EX4_FSM :EX4_FSM PORT MAP ( + Instruction => Instr_in, --STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_En =>Ex4_en, -- ='1' lorsque ce module est sollicité + clk =>clk, + reset =>reset, + ResultOut =>Ex4_Result, --STD_LOGIC_VECTOR (Word-1 downto 0); + Result_En =>Res4_En, -- ='1' lorsque fin de l'exécution du module + Ready => Ex4_Rdy, + NocSize =>NocSize, + AppRank =>MyRank, + AppSize =>MPISize, + IsMain =>IsMain, + Rec_Rdy => Rec_Rdy, + Rec_Data =>Rec_Data, + Rec_Ack =>Rec_Ack, + Snd_Ack =>Snd_ack, + Snd_data =>Snd_data, + Snd_Start =>Snd_Start, + + I_fifo_full =>i_fifo2_full, + + I_fifo_wr_en => Ex4_i_fifo2_wr_en, + I_fifo_data_in => Ex4_i_fifo2_data_in, + Initialized =>Initialized, + Ram_data_out => Dma_data_out, + Ram_address =>dma_wr_Address4, --accès au stockage + Ram_wr =>Ex4_Ram_wr, --activation de l'écriture en RAM + Ram_data_in =>Dma_data_in4, --données à écrire en RAM + DMA_rd_Request => dma_rd_request(4), + DMA_rd_grant => dma_rd_grant(4), + DMA_wr_Request => dma_wr_request(4), + DMA_wr_grant => dma_wr_grant(4), + AppAck =>AppAck, + AppReq =>InitReq, + PortId=>PortId, + port_in_cmd_en => Noc3.port_in_cmd_en, + port_in_wr_en =>Noc3.port_in_wr_en, + port_in_empty =>Noc3.port_in_empty, + port_in_full =>Noc3.port_in_full, + port_in_data =>Noc3.port_in_data, + port_out_data =>Noc3.port_out_data, + port_out_rd_en =>Noc3.port_out_rd_en, + port_out_data_available =>Noc3.port_out_data_available + + +); +--=============Mux des signaux d'accès à la RAM========= +ram_we<='1' when (weram='1' and ram_wev ='1') else '0'; -- le contrôleur DMA contrôle directement +Ram_en<= '1' when (rdram ='1' or weram='1') else '0'; -- les signaux qui vont vers la RAM + + --dma_data_in <=dma_data_in1 or dma_data_in2; + --dma_data_out <=dma_data_out1 or dma_data_out2; + mux_ad_ram_rd:process (dma_rd_grant,dma_rd_address1,dma_rd_address2,dma_rd_address3, + ex1_ram_rd, Ex2_ram_rd, Exi_ram_rd ) +begin + case dma_rd_grant is + when "0001" => dma_rd_address <= dma_rd_address1; + rdram<= ex1_ram_rd; + when "0010" => dma_rd_address <= dma_rd_address2; + rdram<= ex2_ram_rd; + when "0100" => dma_rd_address <= dma_rd_address3; + rdram<= exi_ram_rd; +-- when "1000" => dma_rd_address <= ; + when others => dma_rd_address <= (others =>'0'); + rdram<='0'; + end case; +end process; + mux_ad_ram_wr:process (dma_wr_grant,dma_wr_address1,dma_wr_address2,dma_wr_address4,Dma_data_in1,Dma_data_in2,Dma_data_in4, + ex1_ram_wr,ex2_ram_wr,ex4_ram_wr) +begin + case dma_wr_grant is + + when "0001" => dma_wr_address <= dma_wr_address1; + weram<=ex1_ram_wr ; + Dma_data_in<=Dma_data_in1; + when "0010" => dma_wr_address <= dma_wr_address2; + weram<=ex2_ram_wr ; + Dma_data_in<=Dma_data_in2; + when "1000" => dma_wr_address <= dma_wr_address4; + weram<=ex4_ram_wr; + Dma_data_in<=Dma_data_in4; + when others => dma_wr_address <= (others =>'0'); + weram<='0'; + end case; +end process; +--====================================================== + +--=================Mux des signaux qui vont au switch============ + clkout<=clk; -- permettra le lien avec le module du switch + + NOC1.port_out_data<=switch_port_out_data; + NOC1.port_out_data_available<=switch_port_out_data_vailaible; + NOC1.port_in_empty<=switch_port_in_empty; + NOC1.port_in_full<=switch_port_in_full; + + NOC2.port_out_data<=switch_port_out_data; + NOC2.port_out_data_available<=switch_port_out_data_vailaible; + NOC2.port_in_empty<=switch_port_in_empty; + NOC2.port_in_full<=switch_port_in_full; + + NOC3.port_out_data<=switch_port_out_data; + NOC3.port_out_data_available<=switch_port_out_data_vailaible; + NOC3.port_in_empty<=switch_port_in_empty; + NOC3.port_in_full<=switch_port_in_full; + mux_Noc:process (Ex_en,Noc1,Noc2,Noc3,switch_port_out_data_vailaible,Initialized,Initreq2, + ex2_i_fifo2_wr_en,ex2_i_fifo2_data_in,ex4_i_fifo2_data_in,ex4_i_fifo2_wr_en, + instruction,ex2_result) + +begin + case Ex_en is + + when"0001" => + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC2.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + when "0010"|"0011" => + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC2.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + i_fifo2_wr_en<=ex2_i_fifo2_wr_en; + i_fifo2_data_in<=ex2_i_fifo2_data_in; + when"1011" => --ce cas pose problème car on ne sait ce qui se passe !!! + if initreq2='1' then + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + else + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC2.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + end if; + i_fifo2_wr_en<=ex2_i_fifo2_wr_en; + i_fifo2_data_in<=ex2_i_fifo2_data_in; + when "1001" => --ca où un appel à init est effectué + if initialized='0' then + switch_port_in_data <=Noc3.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC3.port_in_wr_en; + switch_port_in_cmd_en <=NOC3.port_in_cmd_en; + else + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + end if; + i_fifo2_wr_en<=ex4_i_fifo2_wr_en; + i_fifo2_data_in<=ex4_i_fifo2_data_in; + when "1010" => --ca où un appel à init est effectué + --switch_port_in_data <=Noc3.port_in_data; +-- switch_port_out_rd_en<=NOC3.port_out_rd_en; +-- switch_port_in_wr_en <=NOC3.port_in_wr_en; +-- switch_port_in_cmd_en <=NOC3.port_in_cmd_en; + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + i_fifo2_wr_en<=ex4_i_fifo2_wr_en; + i_fifo2_data_in<=ex4_i_fifo2_data_in; + when others => --permet de gérer le cas où un spawn arrive par le réseau + switch_port_in_data <=Noc3.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC3.port_in_wr_en; + switch_port_in_cmd_en <=NOC3.port_in_cmd_en; + + i_fifo2_wr_en<=ex4_i_fifo2_wr_en; + i_fifo2_data_in<=ex4_i_fifo2_data_in; + end case; + Instr_in <=Instruction ; + if initreq2='1' and Ex_en(4)='1' then + Instr_in <=Ex2_Result ; + else + Instr_in <=Instruction ; + end if; + i_fifo2_wr_en<=ex2_i_fifo2_wr_en; + i_fifo2_data_in<=ex2_i_fifo2_data_in; + end process; + + +--=============================================================== +MPI_CORE_DMA_ARBITER: DMA_ARBITER PORT MAP( + clk =>clk, + reset =>reset, + + data_wr_mem => ram_data_in, --vers RAM + + data_rd_mem => Ram_data_out, --- Vers RAM + address_rd =>dma_rd_address, + address_wr =>dma_wr_address, + address_out_rd =>ram_address_rd, + address_out_wr =>ram_address_wr, + ram_en => ram_env, --validation lecture + ram_we =>ram_wev, --validation écriture + hold_req=>hold_req,--demande de bus à l'application + hold_ack=>hold_ack, -- libération du bus RAM par l'application + + data_rd_out => Dma_data_out, --vers périphérique + data_wr_in =>Dma_data_in, --vers périphérique + dma_wr_grant =>dma_wr_grant, + dma_rd_request => dma_rd_request, + dma_rd_grant => dma_rd_grant, + dma_wr_request => dma_wr_request + ); + + +CORE_SCHEDULER: MPI_CORE_SCHEDULER PORT MAP( -- permet de sélectionner la source de l'instruction + -- qui sera exécutée par la MAE EX1 + clk => clk, + reset => reset, + priority_rotation =>scheduler_priority_rotation, + instruction_fifo_empty =>i_fifo1_empty, + get_request_fifo_empty => i_fifo2_empty, + instruction_fifo_rd_en =>i_fifo1_rd_en, + get_request_fifo_rd_en =>i_fifo2_rd_en , + instruction_fifo_data =>i_fifo1_data_out, + get_request_fifo_data =>i_fifo2_data_out, + fifo_selected =>fifo_sel, + instruction_available => fifo_instr, + fifo_empty => scheduler_fifo_empty, + fifo_rd_en =>scheduler_rd_en, + data_out => scheduler_data_out + ); + +end structural; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/DEMUX1.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/DEMUX1.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/DEMUX1.vhd (revision 138) @@ -0,0 +1,54 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:35:09 06/13/2011 +-- Design Name: +-- Module Name: DEMUX1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity CDEMUX1 is + Port ( di : in STD_LOGIC; + sel : in STD_LOGIC; + do1 : out STD_LOGIC; + do2 : out STD_LOGIC); +end CDEMUX1; + +architecture Behavioral of CDEMUX1 is + +begin + +demux_process : process(di, sel) +begin + if sel = '0' then + do1 <= di; + do2 <= '0'; + else + do2 <= di; + do1 <='0'; + end if; +end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/DMA_ARBITER.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/DMA_ARBITER.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/DMA_ARBITER.vhd (revision 138) @@ -0,0 +1,463 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL +-- GAMOM ROLAND CHRISTIAN +-- +-- Create Date: 04:39:43 05/21/2011 +-- Design Name: +-- Module Name: DMA_ARBITER - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- gestionnaire DMA pour le port secodaire de la RAM true dual port des mémoire +-- privée de chaque noeud +-- Dependencies: +-- +-- Revision: 09/07/2012 +-- Revision 1.01 - File Created +-- Revision 1.2 - 19/03/2013 +-- Correction de bugs et optimisation du nombre de cycles +-- Création d'un testbench +-- Additional Comments: Ce module pourra être optimisé pour générer les adresses automatiquement +-- par le controleur DMA lorsqu'il est sollicité par la périphérie +-- +---------------------------------------------------------------------------------- +library IEEE; +library NocLib; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.numeric_std.all; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity DMA_ARBITER is + Port ( dma_rd_request : in STD_LOGIC_VEctor (3 downto 0):=(others=>'0'); + data_wr_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + data_rd_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + address_rd : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); --adresse pour lecture + address_wr : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); -- adresse pour écriture + address_out_wr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); -- adresse de sortie du DMA Arbiter + address_out_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_en : out STD_LOGIC; -- + ram_we : out STD_LOGIC; + data_wr_mem : out STD_LOGIC_VECTOR (Word-1 downto 0); -- donnée en sortie écriture + data_rd_mem : in STD_LOGIC_VECTOR (Word-1 downto 0); -- données en sortie lecture + dma_wr_grant : out STD_LOGIC_vector(3 downto 0):=(others=>'0'); -- autorisation d'écriture + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + clk : in std_logic; + reset : in std_logic; + dma_rd_grant : out STD_LOGIC_vector(3 downto 0):=(others=>'0'); -- autorisation de lecture + dma_wr_request : in STD_LOGIC_vector(3 downto 0):=(others=>'0')); -- demande de lecture +end DMA_ARBITER; + +architecture Behavioral of DMA_ARBITER is +type fsm_states is (idle,wait_ack,arbiter_ack, writing,ReadWrite,reading);-- definition du type etat pour le codage des etats des fsm +signal dmac_state : fsm_states; + +signal prio_rd,prio_wr:std_logic_vector(3 downto 0);--vecteur de bits de priorité +signal pri_rd,pri_wr : natural range 0 to 3; -- stocke le numéro du module qui a la priorité +signal dma_rd_logic : std_logic_vector(3 downto 0):=(others=>'0'); +signal dma_wr_logic : std_logic_vector(3 downto 0):=(others=>'0'); +signal dma_rd_latch,dma_wr_latch: std_logic_vector(3 downto 0):=(others=>'0'); +signal dma_req_wr, dma_req_rd : std_logic; +signal last_grant_rd,last_grant_wr : STD_LOGIC_vector(3 downto 0):=(others=>'0'); +signal tmp :std_logic_vector(3 downto 0):="0000"; + +begin +--========================================================================== +---le MUX qui contrôle les adresses est géré à l'extérieur du contrôleur DMA +dma_sync: process (clk,data_rd_mem,data_wr_in,address_rd,address_wr) +begin +data_rd_out<=data_rd_mem ; +data_wr_mem <= data_wr_in; +address_out_rd <= address_rd; +address_out_wr <= address_wr; + +end process; +--dma_rd_grant<= dma_rd_logic; +--dma_wr_grant<= dma_wr_logic; +dma_rd_grant<= dma_rd_latch; +dma_wr_grant<= dma_wr_latch; +--========================================================================== + +--Déterminer si une requête HOLD doit être émise vers l'application pour la libération du +--bus mémoire +tmp<=(others =>'0'); + +--for i in 0 to 3 loop +--dma_req_wr<=dma_req_wr or dma_wr_request(i); +--loop; + +--for i in 0 to 3 loop +-- dma_req_rd<=dma_req_rd or dma_rd_request(i); -- construire le signal request vers l'extérieur +--loop; +hold_req<='1' when dma_req_rd='1' or dma_req_wr='1' else '0'; --envoyer un Hold vers l'application + + +-- machine à etat du DMAC +dmac_process : process(clk,reset) +--variable tmp : natural range 0 to 15; +variable tmp_rd,tmp_wr: std_logic_vector(3 downto 0); +variable req_rd,req_wr : std_logic:='0' ; + +begin + if rising_edge(clk) then + if reset = '1' then + dmac_state<= idle; + + prio_rd <="0001"; -- au debut priorité lecture au premier module + prio_wr <="0010"; -- au debut priorité ecriture au deuxième module + pri_rd<=0;--index de la priorité + pri_wr<=1; + req_rd:='0'; + req_wr:='0'; + else + if req_wr='0' then --tant que le Ctrl DMA est libre alors faire bouger la priorité en écriture + case dma_wr_request is + when "0001" => pri_wr<=0; + prio_wr<="0001"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="0001"; + when "0010" => pri_wr<=1; + prio_wr<="0010"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="0010"; + when "0100" => pri_wr<=2; + prio_wr<="0100"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="0100"; + when "1000" => pri_wr<=3; + prio_wr<="1000"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="1000"; + + when others => + if req_rd='1' then --demande simultané de lecture et d'écriture + + if dma_rd_request(pri_rd)='1' then + pri_wr<=pri_rd; + req_wr:='1'; + for i in 0 to 3 loop + if i=pri_rd then + prio_wr(i)<='1'; + dma_wr_logic(i)<='1'; + else + prio_wr(i)<='0'; + dma_wr_logic(i)<='0'; + end if; + end loop; + + + end if; + + else --on affecte l'accè à la mémoire suivant le round robbin + tmp_wr:= (dma_wr_request and prio_wr) ; + dma_wr_logic <=tmp_wr; + + req_wr:= not(All_zeros(tmp_wr)); + dma_req_wr<= not(All_zeros(tmp_wr)); + end if; + -- la priorité est circulaire et décale à chaque coup d'horloge + if req_wr='0' then + prio_wr<=rol_vec(prio_wr); + if pri_wr=3 then + pri_wr<=0; + Prio_wr<="0001"; + else + pri_wr<=pri_wr+1; + end if; + end if; + end case; + else --req_wr='1' + + --demande simultané de lecture et d'écriture + + if dma_rd_request(pri_wr)='1' then + pri_rd<=pri_wr; + req_rd:='1'; + prio_rd<=prio_wr; +-- for i in 0 to 3 loop +-- if i=pri_rd then +-- prio_wr(i)<='1'; +-- dma_wr_logic(i)<='1'; +-- else +-- prio_wr(i)<='0'; +-- dma_wr_logic(i)<='0'; +-- end if; +-- end loop; + + end if; + + end if; + + if req_rd='0' then --tant que le Ctrl DMA est libre alors faire bouger la priorité + case dma_rd_request is + when "0001" => pri_rd<=0; + prio_rd<="0001"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="0001"; + when "0010" => pri_rd<=1; + prio_rd<="0010"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="0010"; + + when "0100" => pri_rd<=2; + prio_rd<="0100"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="0100"; + + when "1000" => pri_rd<=3; + prio_rd<="1000"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="1000"; + + when others => + --si une demande survient de la part d'un composant déjà acquitté alors celui-ci est prioritaire + if req_wr='1' then + + if dma_rd_request(pri_wr)='1' then + pri_rd<=pri_wr; + req_rd:='1'; + for i in 0 to 3 loop + if i=pri_wr then + prio_rd(i)<='1'; + dma_rd_logic(i)<='1'; + else + prio_rd(i)<='0'; + dma_rd_logic(i)<='0'; + end if; + end loop; + + + end if; + + else + tmp_rd:= (dma_rd_request and prio_rd) ; + dma_rd_logic<=tmp_rd; + dma_req_rd<= not (All_Zeros(tmp_rd)); + req_rd:= not (All_Zeros(tmp_rd)); + end if; + -- la priorité est circulaire et décale à chaque coup d'horloge + if req_rd='0' then + prio_rd<=rol_vec(prio_rd); + if pri_rd =3 then + pri_rd<=0; + prio_rd<="0001"; + else + + pri_rd<=pri_rd+1; + end if; + end if; + end case; + + end if; + + case dmac_state is + when idle => if req_rd='1' or req_wr='1' then + dmac_state<=wait_ack; + else -- initialiser la priorité + + + req_rd:='0'; + dma_req_rd<= '0'; + + + + req_wr:='0'; + dma_req_wr<= '0'; + + dma_wr_logic <="0000"; --aucun accès mémoire n'est accrédité + dma_rd_logic <="0000"; + + end if; + + when wait_ack => -- l'application doit autoriser l'utilisation de la RAM par le Core + if dma_wr_request(pri_wr) ='1' or dma_rd_request(pri_rd) ='1' then + if hold_ack='1' then + --dmac_state<=arbiter_ack; + if dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='1' then -- + dmac_state <= Readwrite; + elsif dma_wr_request(pri_wr) ='0' and dma_rd_request(pri_rd) ='1' then + dmac_state <= Reading; + elsif dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='0' then + dmac_state <= Writing; + else + dmac_state<=Idle; + end if; + end if; + else + + if dma_wr_request(pri_wr) ='0' then + req_wr:='0';-- forcer une nouvelle recherche de priorité + end if; + + if dma_rd_request(pri_rd) ='0' then + req_rd:='0'; + end if; + dmac_state<=Idle; + end if; + + + when arbiter_ack => +-- if dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='1' then -- +-- dmac_state <= Readwrite; +-- elsif dma_wr_request(pri_wr) ='0' and dma_rd_request(pri_rd) ='1' then +-- dmac_state <= Reading; +-- elsif dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='0' then +-- dmac_state <= Writing; +-- else + dmac_state<=Idle; +-- end if; + -- cet état a été combiné au précédent pour gagner un cycle + when Writing => if dma_wr_request(pri_wr) ='1' then + if hold_ack='1' then + -- on reste dans cet état + if dma_rd_request(pri_rd)='1' then + dmac_state<=ReadWrite; + else + req_rd:='0'; + end if; + else + dmac_state<=wait_ack; + end if; + elsif dma_rd_request(pri_rd) ='1' then + dmac_state <= Reading; + req_wr:='0'; + else + dmac_state <= idle; + req_wr:='0'; + end if; + + + when ReadWrite => if hold_ack='1' then + if dma_wr_request(pri_wr)='1' and dma_rd_request(pri_rd)='1' then + dmac_state <= ReadWrite; + elsif dma_wr_request(pri_wr)='1' and dma_rd_request(pri_rd)='0' then + dmac_state <= Writing; + req_rd:='0'; + elsif dma_wr_request(pri_wr)='0' and dma_rd_request(pri_rd)='1' then + dmac_state <= Reading; + req_wr:='0'; + else + dmac_state <= Idle; + req_rd:='0';req_wr:='0'; + end if; + else + if (dma_wr_request(pri_wr)='1') or (dma_rd_request(pri_rd)='1') then + dmac_state <= Wait_ack; + else + dmac_state <= Idle; + end if; + end if; + when Reading => + if dma_rd_request(pri_rd) ='1' then + if hold_ack='1' then + -- on reste dans cet état + if dma_wr_request(pri_wr)='1' then + dmac_state<=ReadWrite; + else + req_wr:='0'; + end if; + else + dmac_state<=wait_ack; + end if; + elsif dma_wr_request(pri_wr) ='1' then + dmac_state<=writing; + req_rd:='0'; + else + dmac_state <= idle; + req_rd:='0'; + end if; + when others => dmac_state <= idle; + end case; + end if; + end if; +end process; +-- action_asociées +ol: process(dmac_state, address_rd, address_wr,pri_wr,pri_rd,prio_wr,prio_rd,dma_wr_request,dma_rd_request) + +begin +--tester les requêtes DMA en lecture ou en écriture + +case dmac_state is + when idle => + ram_en <='0'; + ram_we <='0'; + dma_wr_latch <=(others=>'0'); + dma_rd_latch <=(others=>'0'); + --address_out_rd <= address_rd; + --hold_req<='0'; + when wait_ack => + ram_en <='0'; + ram_we <='0'; + dma_wr_latch<=(others=>'0'); + dma_rd_latch<=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= (others=>'Z'); + --hold_req<='1'; + when arbiter_ack => --à optimiser pour gagner un cycle + ram_en <='0'; + ram_we <='0'; + dma_wr_latch<=(others=>'0'); + dma_rd_latch<=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= (others=>'Z'); + when writing => -- ecriture dans la ram + ram_en <='1'; + ram_we <='1'; + dma_wr_latch<=(others=>'0'); + dma_wr_latch(pri_wr) <='1'; + dma_rd_latch <=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= address_wr; + --hold_req<='1'; + + when ReadWrite => -- Lecture et écriture simultannée dans la Dual Port RAM + ram_en <='1'; + ram_we <='1'; + dma_wr_latch<=(others=>'0'); + dma_wr_latch(pri_wr) <='1'; + dma_rd_latch<=(others=>'0'); + dma_rd_latch(pri_rd)<='1'; + + --address_out_rd <= address_rd; + --address_out_wr <= address_wr; + --hold_req<='1'; + when Reading => -- lecture dans la ram + ram_en <='1'; + ram_we <='0'; + dma_wr_latch<=(others=>'0'); + dma_rd_latch<=(others=>'0'); + dma_rd_latch(pri_rd)<='1'; + + --address_out_rd <= address_rd; + --address_out_wr <= (others=>'Z'); + --hold_req<='1'; + when others => + ram_en <='0'; + ram_we <='0'; + dma_wr_latch <=(others=>'0'); + dma_rd_latch <=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= (others=>'Z'); + --hold_req<='0'; + end case; +end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX1_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX1_FSM.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX1_FSM.vhd (revision 138) @@ -0,0 +1,1319 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer:GAMOM /KIEGAING +-- +-- Create Date: 08:12:29 06/16/2011 +-- Design Name: +-- Module Name: EX1_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Ce module est chargé de recevoir les instructions du programme MPI et +-- de les exécuter (PUT) il coopère avec EX2 qui reçoit les instructions venant du NoC +-- (GET) +-- +-- Dependencies: +-- +-- Revision: 09/07/2012 +-- Revision 0.03 - File updated +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library NocLib ; +use Work.Packet_type.ALL; +USE ieee.numeric_std.ALL; + + +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX1_FSM is + -- parametres generiques du module : + + + Port ( + --instruction_available : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + instruction : in std_logic_vector(Word-1 downto 0); + instruction_en : in std_logic:='0'; -- active le module instruction + pid : in std_logic_vector(3 downto 0) ; -- id du processeur + nprocs : in std_logic_vector(3 downto 0);-- nombre de processeur du MPSOC - 1 + Result : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module + Ready : out std_logic; --indique la fin de l'éxécution d'une instruction + AppInitReq :out STD_LOGIC:='0'; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic ; -- état de la Lib + -- Accès au Fifo d'instructions + priority_rotation : out STD_LOGIC:='0'; + fifo_rd_en : out STD_LOGIC:='0'; + fifo_empty : in STD_LOGIC; + fifo_data_out : in STD_LOGIC_VECTOR (7 downto 0); + fifo_src : in STD_LOGIC; --permet de désigner le fifo qui est en service + + + Snd_Data : IN Typ_PortIO(0 to 3); + Snd_Start : IN std_logic; + Snd_Ack : OUT std_logic; + + -- Accès au réseau sur puce + switch_port_in_full : in std_logic; + switch_port_in_data : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); + switch_port_in_wr_en : out STD_LOGIC:='0'; + -- Accès à la mémoire RAM du PE + ram_data_in : in std_logic_vector(7 downto 0); + ram_data_out : out std_logic_vector(7 downto 0):=(others=>'0'); + ram_rd,ram_wr : out std_logic:='0'; + ram_address : out std_logic_vector(15 downto 0):=(others=>'0'); + + dma_wr_request : OUT std_logic:='0'; + dma_rd_request : OUT std_logic:='0'; + dma_wr_grant : in STD_LOGIC; + dma_rd_grant : in STD_LOGIC); +end EX1_FSM; + +architecture Behavioral of EX1_FSM is + +component proto_send is +generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée + fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie + fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie + fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée + fifo_in_data_out : in std_logic_vector(Word-1 downto 0); + fifo_out_data_in : out std_logic_vector(Word-1 downto 0); + packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet + copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo + snd_start : in std_logic; --début de la réception + snd_ack :in std_logic; -- acquittement de la réception + snd_comp : out std_logic; -- fin de la réception + mem :in memory(0 to sizemem-1)); --données à copier vers le fifo + + +end component proto_send; +-- definition du type etat pour le codage des etats des fsm +type fsm_states is (fifo_select, fetch_packet_type, decode_packet_type, fetch_addresses, + decode_packet_type2, read_status1,read_status2,ex1_barrier1, ex1_barrier2, ex1_barrier3, ex1_barrier4, + ex1_get1, ex1_get2,ex1_get3,ex1_get4, ex1_put1, ex1_put2, ex1_put3, ex1_put4,ex1_put5, + ex1_init1,ex1_init_run,ex1_init2,ex1_init3,ex1_spawn,ex1_ready,ex1_send_ack,ex1_Wsync); +-- machine a etat du module +signal ex1_state,Next_Ex1_state : fsm_states; + +-- les variables utilisées dans la fsm +signal snd_start1,snd_start_sync,snd_comp,snd_ack1,push:std_logic:='0'; +signal mem,mem_i : memory(0 to 3); +signal data_to_send,data_to_send_i,result_i,result1,noc_fifo_in : std_logic_vector(Word-1 downto 0); +signal packet_type,packet_type_i : std_logic_vector(3 downto 0); +--signal dpid : std_logic_vector(3 downto 0); +signal pid_counter,pid_counter_i : std_logic_vector(3 downto 0); +signal p_len,p_len_i: std_logic_vector(Word-1 downto 0); +signal src_address,src_address_i : std_logic_vector(ADRLEN-1 downto 0); +signal dma_rd,dma_wr,Wr_ok,rd_ok:std_logic:='0'; +--signal res_address : std_logic_vector(15 downto 0); +signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0); +signal n,n_i : natural range 0 to 15; +signal len,len_i : natural range 0 to 255; +signal fifo_rd,fifo_wr,fifo_copy:std_logic:='0'; +signal fifo_sel:std_logic:='0'; +signal run_init,run_init_i:std_logic:='0'; +begin +-- connection des signaux avec les ports +ram_address <= src_address; +result<=Result1; +sw_send: proto_send generic map (sizemem=>4) + port map ( + clk=>clk, + reset=>reset, + fifo_in_empty=>fifo_empty, + fifo_in_full=>'0',--pas utilisé + fifo_out_empty=>'0', + packet_len=>p_len, + copy_mode=>fifo_copy, + fifo_out_full => switch_port_in_full, + fifo_in_rd_en=>fifo_rd, + fifo_in_data_out=>fifo_data_out, +fifo_out_wr_en =>fifo_wr, + + fifo_out_data_in =>noc_fifo_in, + snd_start =>snd_start_sync, + snd_ack =>snd_ack1, + snd_comp=>snd_comp, + mem =>mem + ); +ex1_fsm_sync:process(clk) + + begin + if rising_edge(clk) then + if reset = '1' then + ex1_state <= fifo_select; + n<=0; + len<=0; + p_len<=(others=>'0'); + snd_ack<='0'; + src_address<=(others=>'0'); + dest_address<=(others=>'0'); + run_init<='0'; + else + ex1_state<=next_ex1_state; + n<=n_i; + len<=len_i; + p_len<=p_len_i; + dest_address<=dest_address_i; + Packet_type<=Packet_type_i; + Pid_counter<=Pid_counter_i; + Data_to_send<=Data_to_send_i; + Result1<=Result_i; + run_init<=Run_init_i; + for i in 0 to 3 loop + mem(i)<=mem_i(i); + end loop; + src_address <= src_address_i; + snd_ack<=snd_ack1; --acquittement de l'envoie des données pour EX4 + snd_start_sync<=snd_start1; + end if; + end if; + end process ex1_fsm_sync; +-- processus de transistion entre les etats +fsm_nst_logic : process(ex1_state,n,instruction_en,fifo_empty,fifo_data_out, switch_port_in_full,pid, + pid_counter,len,p_len,snd_start,snd_comp, ram_data_in,dma_rd_grant,dma_wr_grant,AppInitAck,src_address, + fifo_src,dest_address,packet_type,mem,snd_data,run_init,data_to_send) +variable tempval : std_logic_vector(Word-1 downto 0); +variable onepop,fifo_vide : std_logic:='0'; --indique que le fifo a été dépilé +begin + snd_ack1<='0'; + fifo_copy<='0'; + snd_start1<='0'; + n_i<=n; --valeur par défaut + Next_ex1_state <=Ex1_state; + Src_address_i<=src_address; + dest_address_i<=dest_address; + P_len_i<=P_len; + Packet_type_i<=Packet_type; + Pid_counter_i<=Pid_counter; + run_init_i<=Run_init; + Len_i<=Len; + Data_to_send_i<=Data_to_send; + dma_rd<='0'; --attention ceci peut changer le code + dma_wr<='0'; --il faut donc le vérifier + for i in 0 to 3 loop + mem_i(i)<=mem(i); + end loop; + case ex1_state is + when fifo_select => if instruction_en='1' and fifo_empty ='0' then + Next_ex1_state <= fetch_packet_type; + else + Next_ex1_state <= fifo_select; + end if; + rd_ok<='0'; + wr_ok<='0'; + if instruction_en='1' and snd_start='1' then + run_init_i<='1'; + Next_ex1_state<=ex1_init_run; + else + run_init_i<='0'; + end if; + --lecture du registre status de la mib MPI + when read_status1 => if dma_rd_grant = '1' then -- fin du mpi_put + Next_ex1_state <= read_status2; + else + Next_ex1_state <= read_status1; + end if; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16)); + when read_status2 => + Next_ex1_state <= fifo_select; + when fetch_packet_type => rd_ok<='0'; + if fifo_empty ='1' then + Next_ex1_state <= fifo_select; + else + packet_type_i <= fifo_data_out(7 downto 4); + data_to_send_i <= fifo_data_out; + Next_ex1_state <= decode_packet_type; + rd_ok<='1'; + end if; + when decode_packet_type => rd_ok<='0'; + if fifo_empty='0' then + if packet_type = MPI_PUT then + p_len_i <= fifo_data_out + 4; + n_i <= 0;rd_ok<='1'; + Next_ex1_state <= fetch_addresses; + elsif packet_type = MPI_GET then + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i <= fifo_data_out; + n_i <= 0; rd_ok<='1'; + Next_ex1_state <= fetch_addresses; + elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then + p_len_i <= "00000011"; -- = 3 + pid_counter_i <= "0000"; + rd_ok<='1'; + Next_ex1_state <= ex1_barrier1; + elsif packet_type = MPI_INIT then + Next_ex1_state<=ex1_init1; + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + n_i<=0;rd_ok<='1'; + elsif packet_type = MPI_ACK then + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + n_i <= 0; rd_ok<='0'; + Next_ex1_state <= ex1_send_Ack; + elsif packet_type = MPI_WIN_SYNC then + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + n_i <= 0; rd_ok<='0'; + Next_ex1_state <= ex1_WSynC; + elsif packet_type = MPI_SPAWN then + Next_ex1_state<=ex1_SPAWN; + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + onepop:='1';--il y a une donnée lue + src_address_i<=std_logic_vector(to_unsigned(Core_spawn_adr+1,16)); + rd_ok<='0'; + else -- packet non reconnu + --synthesis translate_off + report "Ex1 : ATTENTION paquet non reconnu !!!!!!!!!" ; + --synthesis translate_on + if fifo_empty = '1' then + Next_ex1_state <= fifo_select; + + else + rd_ok<='1'; + packet_type_i <= fifo_data_out(7 downto 4); --lire le prochain paquet + data_to_send_i <= fifo_data_out; + Next_ex1_state <= decode_packet_type;-- pas necessaire mais plus sure + end if; + end if; + end if; + when fetch_addresses => n_i<=n;rd_ok<='1'; + if fifo_empty = '0' and n = 0 then + src_address_i(15 downto 8) <= fifo_data_out; + n_i <= n + 1; + Next_ex1_state <= fetch_addresses; + elsif fifo_empty = '0' and n = 1 then + src_address_i(7 downto 0) <= fifo_data_out; + n_i <= n + 1; + Next_ex1_state <= fetch_addresses; + elsif fifo_empty = '0' and n = 2 then + dest_address_i(15 downto 8) <= fifo_data_out; + n_i <= n + 1; + Next_ex1_state <= fetch_addresses; + elsif fifo_empty = '0' and n = 3 then + dest_address_i(7 downto 0) <= fifo_data_out; + n_i <= n+1; + elsif n=4 then + rd_ok<='0'; + n_i<=0; + Next_ex1_state <= decode_packet_type2; + elsif fifo_empty='1' then + rd_ok<='0'; + Next_ex1_state <= fetch_addresses; --attendre les données manquantes + else + Next_ex1_state <= fifo_select; + end if; + when decode_packet_type2 => if packet_type = MPI_PUT then + Next_ex1_state <= ex1_put1; + elsif packet_type = MPI_GET then + Next_ex1_state <= ex1_get1; + end if; + -- execution du mpi put + when ex1_put1 => if dma_rd_grant = '1' then + Next_ex1_state <= ex1_put2; + else + Next_ex1_state <= ex1_put1; + end if; + Wr_ok<='0'; + when ex1_put2 =>Wr_ok<='0'; + if switch_port_in_full = '0' and n = 0 then + --envoie du code MPI_PUT + n_i<= n + 1; + wr_ok<='0'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 1 then + data_to_send_i <= p_len; + n_i<= n + 1; + wr_ok<='1'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 2 then + data_to_send_i <= dest_address(15 downto 8); + n_i<= n + 1; + wr_ok<='1'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 3 then + data_to_send_i <= dest_address(7 downto 0); + n_i<= n +1; + wr_ok<='1'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 4 then + p_len_i <= p_len - 4; + -- Next_ex1_state <= ex1_put3; + Wr_ok<='0'; + n_i<=n+1; + elsif n=5 and dma_rd_grant='1' then + Next_ex1_state <= ex1_put3; + n_i<=0; + Wr_ok<='1'; + else + Next_ex1_state <= ex1_put2; + end if; + when ex1_put3 => wr_ok<='0'; + if unsigned(p_len)>0 then + --if n=0 then +-- n_i<=1; --cycle d'attente pour la RAM +-- Wr_ok<='0'; +-- elsif n=1 then + if switch_port_in_full = '0' then + if n=1 then --creer un délai sur ces signaux par rapport à src_adress + p_len_i <= p_len - 1; + Wr_Ok<='1'; + end if; + n_i<=1; + src_address_i <= src_address+1; + Next_ex1_state <= ex1_put3; + + + else + Wr_Ok<='0'; + src_address_i <= src_address; + n_i<=0; + end if; + --elsif n=2 then +-- n_i<=0; --cycle d'attente pour la RAM +-- Wr_ok<='0'; +-- src_address_i <= src_address ; --prochaine lecture +-- +-- end if; + else + Wr_Ok<='0'; + Next_ex1_state <= ex1_put4; + end if; + when ex1_put4 =>rd_ok<='1'; + wr_ok<='0'; + if dma_rd_grant = '1' then -- fin du mpi_put + Next_ex1_state <= ex1_put5; + rd_ok<='0'; + n_i<=0; + data_to_send_i<="00000001"; + else + Next_ex1_state <= ex1_put4; + end if; + + if fifo_src='0' then --détection Put ou Get + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + else + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + end if; + when ex1_put5 => if n >0 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + rd_ok<='0';wr_ok<='0'; + if n=0 then + + n_i<=n+1; + elsif n=1 then + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + dma_wr<='1'; + dma_rd<='1'; + elsif n=2 then + if dma_rd_grant='1' then + n_i<=n+1; + dma_wr<='1'; + tempval:=Ram_data_in; + data_to_send_i<=ram_data_in; + end if; + rd_ok<='1'; + wr_ok<='0'; + + dma_rd<='1'; + elsif n=3 then + dma_rd<='1'; + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_in; + data_to_send_i<=ram_data_in; + --src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + tempval(5):='1'; -- SET du bit DSENT + data_to_send_i(5)<='1'; + if fifo_src='0' then -- c'est un put qui est exécuté + tempval(5):='1'; -- SET du bit DSENT + --data_to_send_i<=ram_data_in or "00100000"; + else -- c'est un Get qui est exécuté + --tempval(2):='1'; -- ne pas annuler le sending après un GET + --data_to_send_i<=ram_data_in or "00000100"; + end if; + --data_to_send_i<=tempval; --A tester + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + dma_rd<='0'; --libérer le bus et revenir en arrière + dma_wr<='0'; + n_i<=0; + end if; + elsif n=3 then + if dma_wr_grant = '1' and dma_rd_grant='1' then + n_i<=n+1; + + --src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + end if; + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='1'; + elsif n=4 then + if dma_wr_grant = '1' and dma_rd_grant='1' then + n_i<=n+1; + + src_address_i<=std_logic_vector(to_unsigned(core_put_adr+6,16)); + data_to_send_i<="00000001"; + end if; + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='1'; + elsif n=5 then + if dma_wr_grant = '1' then + n_i<=n+1; + + -- SET du bit DSENT + data_to_send_i<="00000001"; + end if; + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='0'; + elsif n=6 then + n_i<=0; + Next_ex1_state <= fifo_select; + rd_ok<='0'; + wr_ok<='0'; + dma_wr<='0'; + dma_rd<='0'; + end if; + + + when ex1_get1 => wr_ok<='0'; + if switch_port_in_full = '0' and n = 0 then -- execution du mpi get + --écrire l'entête de la fonction + n_i<= n + 1; + Wr_ok<='0'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 1 then -- execution du mpi get + data_to_send_i <= "00001000"; -- longueur du paquet sur le réseau ? + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 2 then + data_to_send_i <= "0000"&pid; -- Rang source + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 3 then + data_to_send_i <= p_len; + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 4 then + data_to_send_i <= src_address(15 downto 8); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 5 then + data_to_send_i <= src_address(7 downto 0); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 6 then + data_to_send_i <= dest_address(15 downto 8); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 7 then + data_to_send_i <= dest_address(7 downto 0); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 8 then + Next_ex1_state <= ex1_get2; + n_i<=0; + Wr_ok<='1'; + else + Next_ex1_state <= ex1_get1; + end if; + when ex1_get2 => if dma_wr_grant = '1' then + Next_ex1_state <= ex1_get3; + src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16)); + data_to_send_i<="00000001"; + else + Next_ex1_state <= ex1_get2; + end if; + dma_wr<='1'; + when ex1_send_ack |ex1_Wsync=> rd_ok<='0'; + if n = 0 then -- execution du mpi ack /ou Mpi_Win_sync + if switch_port_in_full = '0' then + + wr_Ok<='0'; --envoie de la première donnée(code ack) + n_i<= n + 1; + onepop:='0'; + + end if; + elsif n = 1 then + if fifo_empty='0' and onepop='0' then + data_to_send_i <=p_len ; + + rd_Ok<='1'; --passe la longueur + onepop:=not onepop; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok<='0'; + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:=not onepop; + n_i<= n + 1; + wr_ok<='1'; + elsif (switch_port_in_full = '1') then + wr_Ok<='0'; + + end if; + + elsif (n= 2) then + if fifo_empty='0' and onepop='0' then + + data_to_send_i <=fifo_data_out; + rd_Ok<='1'; + onepop:=not onepop; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok<='0'; + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:=not onepop; + n_i<= n + 1; + wr_ok<='1'; + else + wr_Ok<='0'; + + end if; + elsif (n= 3) then + if fifo_empty='0' and onepop='0' then + + data_to_send_i <=fifo_data_out; + rd_Ok<='1'; + onepop:=not onepop; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok<='0'; + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:=not onepop; + n_i<= n + 1; + wr_ok<='1'; + + else + wr_Ok<='0'; + + end if; + elsif n = 4 then + n_i<=0; + Wr_Ok<='1'; + rd_ok<='0';--vider le tampon + Next_ex1_state <= fifo_select; + + end if; + + when ex1_get3 =>if n<2 then --ecriture de la fin d'envoie + if dma_wr_grant = '1' then -- fin du post de mpi_get + + n_i<=n+1; + data_to_send_i<="00000001"; + wr_ok<='1'; + rd_ok<='0'; + end if; + + elsif n=2 then + n_i<=0; + Next_ex1_state <= ex1_get4; + end if; + src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16)); + when ex1_get4 => wr_ok<='0'; + rd_ok<='0'; + dma_wr<='1'; + dma_rd<='1'; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + + if n=0 then + + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=1 then + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=2 then + if dma_rd_grant='1' then + n_i<=n+1; + rd_ok<='1'; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + else + n_i<=1; + end if; + + elsif n=3 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_in; + data_to_send_i<=Ram_data_in; + rd_ok<='1'; + wr_ok<='0'; + dma_wr<='1'; + dma_rd<='1'; + else + dma_wr<='0'; + dma_rd<='0'; + n_i<=n-1; + end if; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + elsif n=4 then + if dma_wr_grant = '1' and dma_rd_grant='1' then + n_i<=n+1; + rd_ok<='0'; + wr_ok<='1'; + tempval(6):='1'; --SET du bit Windows Busy --car réception Get + tempval(1):='1'; -- SET du bit DReceiving + data_to_send_i(6)<='1'; + data_to_send_i(1)<='1'; + --data_to_send_i<=tempval; -- à tester absolument !!! + else + rd_ok<='0'; + wr_ok<='1'; + n_i<=1; + end if; + dma_wr<='1'; + dma_rd<='1'; + elsif n=5 then + wr_ok<='1'; + if dma_wr_grant = '1' then + n_i<=n+1; + end if; + elsif n=6 then + n_i<=0; + Next_ex1_state <= fifo_select; + dma_wr<='0'; + dma_rd<='0'; + end if; + + when ex1_spawn => rd_ok<='0'; + if n = 0 then -- execution du mpi spawn + if switch_port_in_full = '0' then + + wr_Ok<='0'; + n_i<= n + 1; + onepop:='0'; + --data_to_send_i<=len; + end if; + elsif n = 1 then + if fifo_empty='0' and onepop='0' then + data_to_send_i <=p_len ; + + rd_Ok<='1'; + onepop:='1'; --une donnée lue il faut arrêter de dépiler + + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:='0'; + n_i<= n + 1; + wr_ok<='1'; + else + wr_Ok<='0'; + + end if; + + elsif (n= 2) or (n=3) then + if fifo_empty='0' and onepop='0' then + + data_to_send_i <=fifo_data_out; + rd_Ok<='1'; + onepop:='1'; --une donnée lue il faut arrêter de dépiler + + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:='0'; + n_i<= n + 1; + wr_ok<='1'; + else + wr_Ok<='0'; + + end if; + elsif n=4 then + n_i<=0; + Wr_Ok<='1'; + rd_ok<='0'; + Next_ex1_state <= fifo_select; + end if; + -- execution du barrier + when ex1_barrier1 => if switch_port_in_full = '0' then + Next_ex1_state <= ex1_barrier2; + else + Next_ex1_state <= ex1_barrier1; + end if; + when ex1_barrier2 => if switch_port_in_full = '0' then + Next_ex1_state <= ex1_barrier3; + else + Next_ex1_state <= ex1_barrier2; + end if; + when ex1_barrier3 => if switch_port_in_full = '0' then + Next_ex1_state <= ex1_barrier4; + else + Next_ex1_state <= ex1_barrier3; + end if; + when ex1_barrier4 => if packet_type = MPI_BARRIER_COMPLETED and pid_counter < nprocs then + pid_counter_i <= pid_counter + 1; + Next_ex1_state <= ex1_barrier1; + else + Next_ex1_state <= fifo_select; + end if; + when ex1_init1 => rd_ok<='0'; + if n=0 then + n_i<=n+1; + Len_i<=len-2; --deux données a été dépilée + elsif n=1 then --vider le fifo instruction + if len>0 then + if fifo_empty='0' then + rd_ok<='1'; + Len_i<=len-1; + + else + rd_ok<='0'; + Len_i<=Len; + end if; + else + n_i<=n+1; + end if; + elsif n=2 then -- + n_i<=0; + rd_ok<='0'; + Next_ex1_state<=ex1_init_run; + + end if; + + when ex1_init_run=> if n=0 then + if snd_start='1' then --le module ex4 veut envoyer des données + + n_i<=n+1; + + for i in 0 to 3 loop + mem_i(i)<=snd_data(i); + end loop; + if snd_data(0)(7 downto 4)=MPI_INIT or + snd_data(0)(7 downto 4)=MPI_SPAWN or + snd_data(0)(7 downto 4)=MPI_ACK then + + else + report "Ex1 : Une instruction inconnue a été envoyé par Ex4 sur le réseau !"; + end if; + P_len_i<=x"04"; + fifo_copy<='0'; + snd_ack1<='0'; + + end if; + if AppInitAck='1' then + Next_ex1_state<=ex1_init2; + end if; + elsif n=1 then + fifo_sel<='0';--pas de rotation du fifo instruction + snd_start1<='1'; + P_len_i<=x"04"; + fifo_copy<='0'; + snd_ack1<='0'; + + n_i<=n+1; + elsif n=2 then + snd_start1<='1'; + if snd_comp='1' then + snd_ack1<='1'; + + snd_start1<='0'; + n_i<=n+1; + end if; + elsif n=3 then + snd_start1<='0'; + snd_ack1<='1'; + fifo_sel<='0'; + if snd_start='0' then --attente l'annulation de l'envoie + n_i<=0; + snd_ack1<='0'; + if run_init='1' then + Next_EX1_state<=fifo_select; + --run_init<='0'; + end if; + end if; + end if; + + + when ex1_init2 => -- écriture dans le registre status reg. + src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16)); + if n=0 then --envoie du message Spawn Ack sur le réseau + if instruction(6)='1' then --Spawned=1 ? + n_i<=1; --envoie du message Spawn à main lib + data_to_send_i<="01010000"; --init+spawn + else + n_i<=4; --écrire le résultat de la fn + data_to_send_i<="00010000"; --init seul + end if; + + elsif n=1 then + n_i<=n+1; + mem_i(0)<=MPI_INIT & x"0"; --répondre au premier + mem_i(1)<=x"04"; + mem_i(2)<=x"00"; + mem_i(3)<=INIT_SPAWN & pid;-- indiquer qui répond au + elsif n=2 then + snd_start1<='1'; + n_i<=n+1; + fifo_copy<='0'; + elsif n=3 then + fifo_copy<='0'; + snd_start1<='1'; + if snd_comp='1' then + snd_ack1<='1'; + snd_start1<='0'; + n_i<=n+1; + end if; + elsif n=4 then --écriture du registre status + dma_wr<='1'; + wr_ok<='1'; + if dma_wr_grant = '1' then -- fin du mpi_init + n_i<=n+1; + end if; + elsif n=5 then + wr_ok<='1'; + dma_wr<='1'; + if dma_wr_grant = '1' then -- fin du mpi_init + n_i<=n+1; + end if; + elsif n=6 then + Next_ex1_state <= ex1_init3; + n_i<=0; + wr_ok<='0'; + end if; + + + when ex1_init3 =>--if AppInitAck='1' then + Next_ex1_state <= fifo_select; + --end if; + when ex1_ready => Next_ex1_state <= fifo_select; + when others => Next_ex1_state <= fifo_select; + end case; + + end process; + + -- sortie de la machine à etat + ex1_fsm_action : process(ex1_state, fifo_empty, switch_port_in_full, p_len,pid, + pid_counter, dma_rd,dma_wr,ram_data_in,AppInitAck,fifo_wr,noc_fifo_in,data_to_send, packet_type, wr_ok,rd_ok, + fifo_rd) + variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0'); + begin +-- code fonctionnel + Result_i<=Result1; + case ex1_state is + when fifo_select => priority_rotation <='1'; -- on peut changer la priorité + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result_i <=(others=>'0'); + Ready<='1'; + when read_status1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result_i <=(others=>'0'); + Ready<='0'; + when read_status2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + status_reg:=Ram_data_in; + Result_i <=(others=>'0'); + Ready<='0'; + when fetch_packet_type => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= (others =>'0'); + AppInitReq<='0'; + switch_port_in_wr_en <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + + when decode_packet_type => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= Data_To_Send; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when fetch_addresses => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when decode_packet_type2 =>priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= packet_type & pid_counter; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= p_len; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= "0000" & pid; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= "0000" & pid; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_get1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= Wr_ok; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + when ex1_get2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <='0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= dma_Wr; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_get3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others=>'0');---??? + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; -- le résultat de l'exécution + Ready<='0'; -- fin du module + Result_i <=(2=>'1',others=>'0');--Get completed + when ex1_get4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; --"00000001"; + Result_i <=(2=>'1',others=>'0'); --get completed + Ready<='0'; -- fin du module + when ex1_put1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_put2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + Ram_rd<='1'; + Ram_wr<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_put3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_data_in; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_put4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_data_in;---??? + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= rd_ok; + dma_wr_request <= wr_ok; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution + --result(1)<='1'; + Result_i <=(1=>'1',others=>'0');--put completed + Ready<='0'; -- fin du module + when ex1_put5 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; --"00000001"; + Result_i <=(1=>'1',others=>'0'); --put completed + Ready<='0'; -- fin du module + when ex1_init1 => priority_rotation <='0'; + if fifo_empty='0' then + fifo_rd_en <= rd_ok; + else + fifo_rd_en<='0'; + end if; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= wr_ok; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='1'; + Result_i <=(others=>'0'); + Ready<='0'; + when ex1_init_run => priority_rotation <='0'; + + fifo_rd_en <= fifo_rd; + + switch_port_in_data <= noc_fifo_in; + switch_port_in_wr_en <= fifo_wr; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='1'; + Result_i <=(others=>'0'); + Ready<='0'; + + when ex1_init2=> priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= noc_fifo_in; + switch_port_in_wr_en <= fifo_wr; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<=wr_ok; + Ram_data_out<=Data_to_send; -- le résultat de l'exécution + Ready<='0'; -- dans le registre status + Result_i <=(others=>'0');-- + when ex1_init3=> priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<='1'; + Ram_data_out<="00010000"; + Ready<='0'; -- fin du module + Result_i<=(0=>'1',others=>'0'); --le résultat de l'initialisation est écrit + + when ex1_spawn => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= Data_to_send; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when ex1_send_ack|ex1_Wsync => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= Data_to_send; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when ex1_ready => + Ready<='1'; -- fin du module + priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Ready<='0'; + + when others => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result_i <=(others=>'0'); + Ready<='0'; + end case; + + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX1_FSM.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX1_FSM.vhd.bak (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX1_FSM.vhd.bak (revision 138) @@ -0,0 +1,1319 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer:GAMOM /KIEGAING +-- +-- Create Date: 08:12:29 06/16/2011 +-- Design Name: +-- Module Name: EX1_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Ce module est chargé de recevoir les instructions du programme MPI et +-- de les exécuter (PUT) il coopère avec EX2 qui reçoit les instructions venant du NoC +-- (GET) +-- +-- Dependencies: +-- +-- Revision: 09/07/2012 +-- Revision 0.03 - File updated +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library NocLib ; +use Work.Packet_type.ALL; +USE ieee.numeric_std.ALL; + + +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX1_FSM is + -- parametres generiques du module : + + + Port ( + --instruction_available : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + instruction : in std_logic_vector(Word-1 downto 0); + instruction_en : in std_logic:='0'; -- active le module instruction + pid : in std_logic_vector(3 downto 0) ; -- id du processeur + nprocs : in std_logic_vector(3 downto 0);-- nombre de processeur du MPSOC - 1 + Result : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module + Ready : out std_logic; --indique la fin de l'éxécution d'une instruction + AppInitReq :out STD_LOGIC:='0'; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic ; -- état de la Lib + -- Accès au Fifo d'instructions + priority_rotation : out STD_LOGIC:='0'; + fifo_rd_en : out STD_LOGIC:='0'; + fifo_empty : in STD_LOGIC; + fifo_data_out : in STD_LOGIC_VECTOR (7 downto 0); + fifo_src : in STD_LOGIC; --permet de désigner le fifo qui est en service + + + Snd_Data : IN Typ_PortIO(0 to 3); + Snd_Start : IN std_logic; + Snd_Ack : OUT std_logic; + + -- Accès au réseau sur puce + switch_port_in_full : in std_logic; + switch_port_in_data : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); + switch_port_in_wr_en : out STD_LOGIC:='0'; + -- Accès à la mémoire RAM du PE + ram_data_in : in std_logic_vector(7 downto 0); + ram_data_out : out std_logic_vector(7 downto 0):=(others=>'0'); + ram_rd,ram_wr : out std_logic:='0'; + ram_address : out std_logic_vector(15 downto 0):=(others=>'0'); + + dma_wr_request : OUT std_logic:='0'; + dma_rd_request : OUT std_logic:='0'; + dma_wr_grant : in STD_LOGIC; + dma_rd_grant : in STD_LOGIC); +end EX1_FSM; + +architecture Behavioral of EX1_FSM is + +component proto_send is +generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée + fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie + fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie + fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée + fifo_in_data_out : in std_logic_vector(Word-1 downto 0); + fifo_out_data_in : out std_logic_vector(Word-1 downto 0); + packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet + copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo + snd_start : in std_logic; --début de la réception + snd_ack :in std_logic; -- acquittement de la réception + snd_comp : out std_logic; -- fin de la réception + mem :in memory(0 to sizemem-1)); --données à copier vers le fifo + + +end component proto_send; +-- definition du type etat pour le codage des etats des fsm +type fsm_states is (fifo_select, fetch_packet_type, decode_packet_type, fetch_addresses, + decode_packet_type2, read_status1,read_status2,ex1_barrier1, ex1_barrier2, ex1_barrier3, ex1_barrier4, + ex1_get1, ex1_get2,ex1_get3,ex1_get4, ex1_put1, ex1_put2, ex1_put3, ex1_put4,ex1_put5, + ex1_init1,ex1_init_run,ex1_init2,ex1_init3,ex1_spawn,ex1_ready,ex1_send_ack,ex1_Wsync); +-- machine a etat du module +signal ex1_state,Next_Ex1_state : fsm_states; + +-- les variables utilisées dans la fsm +signal snd_start1,snd_start_sync,snd_comp,snd_ack1,push:std_logic:='0'; +signal mem,mem_i : memory(0 to 3); +signal data_to_send,data_to_send_i,result_i,result1,noc_fifo_in : std_logic_vector(Word-1 downto 0); +signal packet_type,packet_type_i : std_logic_vector(3 downto 0); +--signal dpid : std_logic_vector(3 downto 0); +signal pid_counter,pid_counter_i : std_logic_vector(3 downto 0); +signal p_len,p_len_i: std_logic_vector(Word-1 downto 0); +signal src_address,src_address_i : std_logic_vector(ADRLEN-1 downto 0); +signal dma_rd,dma_wr,Wr_ok,rd_ok:std_logic:='0'; +--signal res_address : std_logic_vector(15 downto 0); +signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0); +signal n,n_i : natural range 0 to 15; +signal len,len_i : natural range 0 to 255; +signal fifo_rd,fifo_wr,fifo_copy:std_logic:='0'; +signal fifo_sel:std_logic:='0'; +signal run_init,run_init_i:std_logic:='0'; +begin +-- connection des signaux avec les ports +ram_address <= src_address; +result<=Result1; +sw_send: proto_send generic map (sizemem=>4) + port map ( + clk=>clk, + reset=>reset, + fifo_in_empty=>fifo_empty, + fifo_in_full=>'0',--pas utilisé + fifo_out_empty=>'0', + packet_len=>p_len, + copy_mode=>fifo_copy, + fifo_out_full => switch_port_in_full, + fifo_in_rd_en=>fifo_rd, + fifo_in_data_out=>fifo_data_out, +fifo_out_wr_en =>fifo_wr, + + fifo_out_data_in =>noc_fifo_in, + snd_start =>snd_start_sync, + snd_ack =>snd_ack1, + snd_comp=>snd_comp, + mem =>mem + ); +ex1_fsm_sync:process(clk) + + begin + if rising_edge(clk) then + if reset = '1' then + ex1_state <= fifo_select; + n<=0; + len<=0; + p_len<=(others=>'0'); + snd_ack<='0'; + src_address<=(others=>'0'); + dest_address<=(others=>'0'); + run_init<='0'; + else + ex1_state<=next_ex1_state; + n<=n_i; + len<=len_i; + p_len<=p_len_i; + dest_address<=dest_address_i; + Packet_type<=Packet_type_i; + Pid_counter<=Pid_counter_i; + Data_to_send<=Data_to_send_i; + Result1<=Result_i; + run_init<=Run_init_i; + for i in 0 to 3 loop + mem(i)<=mem_i(i); + end loop; + src_address <= src_address_i; + snd_ack<=snd_ack1; --acquittement de l'envoie des données pour EX4 + snd_start_sync<=snd_start1; + end if; + end if; + end process ex1_fsm_sync; +-- processus de transistion entre les etats +fsm_nst_logic : process(ex1_state,n,instruction_en,fifo_empty,fifo_data_out, switch_port_in_full,pid, + pid_counter,len,p_len,snd_start,snd_comp, ram_data_in,dma_rd_grant,dma_wr_grant,AppInitAck,src_address, + fifo_src,dest_address,packet_type,mem,snd_data,run_init,data_to_send) +variable tempval : std_logic_vector(Word-1 downto 0); +variable onepop,fifo_vide : std_logic:='0'; --indique que le fifo a été dépilé +begin + snd_ack1<='0'; + fifo_copy<='0'; + snd_start1<='0'; + n_i<=n; --valeur par défaut + Next_ex1_state <=Ex1_state; + Src_address_i<=src_address; + dest_address_i<=dest_address; + P_len_i<=P_len; + Packet_type_i<=Packet_type; + Pid_counter_i<=Pid_counter; + run_init_i<=Run_init; + Len_i<=Len; + Data_to_send_i<=Data_to_send; + dma_rd<='0'; --attention ceci peut changer le code + dma_wr<='0'; --il faut donc le vérifier + for i in 0 to 3 loop + mem_i(i)<=mem(i); + end loop; + case ex1_state is + when fifo_select => if instruction_en='1' and fifo_empty ='0' then + Next_ex1_state <= fetch_packet_type; + else + Next_ex1_state <= fifo_select; + end if; + rd_ok<='0'; + wr_ok<='0'; + if instruction_en='1' and snd_start='1' then + run_init_i<='1'; + Next_ex1_state<=ex1_init_run; + else + run_init_i<='0'; + end if; + --lecture du registre status de la mib MPI + when read_status1 => if dma_rd_grant = '1' then -- fin du mpi_put + Next_ex1_state <= read_status2; + else + Next_ex1_state <= read_status1; + end if; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16)); + when read_status2 => + Next_ex1_state <= fifo_select; + when fetch_packet_type => rd_ok<='0'; + if fifo_empty ='1' then + Next_ex1_state <= fifo_select; + else + packet_type_i <= fifo_data_out(7 downto 4); + data_to_send_i <= fifo_data_out; + Next_ex1_state <= decode_packet_type; + rd_ok<='1'; + end if; + when decode_packet_type => rd_ok<='0'; + if fifo_empty='0' then + if packet_type = MPI_PUT then + p_len_i <= fifo_data_out + 4; + n_i <= 0;rd_ok<='1'; + Next_ex1_state <= fetch_addresses; + elsif packet_type = MPI_GET then + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i <= fifo_data_out; + n_i <= 0; rd_ok<='1'; + Next_ex1_state <= fetch_addresses; + elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then + p_len_i <= "00000011"; -- = 3 + pid_counter_i <= "0000"; + rd_ok<='1'; + Next_ex1_state <= ex1_barrier1; + elsif packet_type = MPI_INIT then + Next_ex1_state<=ex1_init1; + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + n_i<=0;rd_ok<='1'; + elsif packet_type = MPI_ACK then + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + n_i <= 0; rd_ok<='0'; + Next_ex1_state <= ex1_send_Ack; + elsif packet_type = MPI_WIN_SYNC then + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + n_i <= 0; rd_ok<='0'; + Next_ex1_state <= ex1_WSynC; + elsif packet_type = MPI_SPAWN then + Next_ex1_state<=ex1_SPAWN; + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + onepop:='1';--il y a une donnée lue + src_address_i<=std_logic_vector(to_unsigned(Core_spawn_adr+1,16)); + rd_ok<='0'; + else -- packet non reconnu + --synthesis translate_off + report "Ex1 : ATTENTION paquet non reconnu !!!!!!!!!" ; + --synthesis translate_on + if fifo_empty = '1' then + Next_ex1_state <= fifo_select; + + else + rd_ok<='1'; + packet_type_i <= fifo_data_out(7 downto 4); --lire le prochain paquet + data_to_send_i <= fifo_data_out; + Next_ex1_state <= decode_packet_type;-- pas necessaire mais plus sure + end if; + end if; + end if; + when fetch_addresses => n_i<=n;rd_ok<='1'; + if fifo_empty = '0' and n = 0 then + src_address_i(15 downto 8) <= fifo_data_out; + n_i <= n + 1; + Next_ex1_state <= fetch_addresses; + elsif fifo_empty = '0' and n = 1 then + src_address_i(7 downto 0) <= fifo_data_out; + n_i <= n + 1; + Next_ex1_state <= fetch_addresses; + elsif fifo_empty = '0' and n = 2 then + dest_address_i(15 downto 8) <= fifo_data_out; + n_i <= n + 1; + Next_ex1_state <= fetch_addresses; + elsif fifo_empty = '0' and n = 3 then + dest_address_i(7 downto 0) <= fifo_data_out; + n_i <= n+1; + elsif n=4 then + rd_ok<='0'; + n_i<=0; + Next_ex1_state <= decode_packet_type2; + elsif fifo_empty='1' then + rd_ok<='0'; + Next_ex1_state <= fetch_addresses; --attendre les données manquantes + else + Next_ex1_state <= fifo_select; + end if; + when decode_packet_type2 => if packet_type = MPI_PUT then + Next_ex1_state <= ex1_put1; + elsif packet_type = MPI_GET then + Next_ex1_state <= ex1_get1; + end if; + -- execution du mpi put + when ex1_put1 => if dma_rd_grant = '1' then + Next_ex1_state <= ex1_put2; + else + Next_ex1_state <= ex1_put1; + end if; + Wr_ok<='0'; + when ex1_put2 =>Wr_ok<='0'; + if switch_port_in_full = '0' and n = 0 then + --envoie du code MPI_PUT + n_i<= n + 1; + wr_ok<='0'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 1 then + data_to_send_i <= p_len; + n_i<= n + 1; + wr_ok<='1'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 2 then + data_to_send_i <= dest_address(15 downto 8); + n_i<= n + 1; + wr_ok<='1'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 3 then + data_to_send_i <= dest_address(7 downto 0); + n_i<= n +1; + wr_ok<='1'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 4 then + p_len_i <= p_len - 4; + -- Next_ex1_state <= ex1_put3; + Wr_ok<='0'; + n_i<=n+1; + elsif n=5 and dma_rd_grant='1' then + Next_ex1_state <= ex1_put3; + n_i<=0; + Wr_ok<='1'; + else + Next_ex1_state <= ex1_put2; + end if; + when ex1_put3 => wr_ok<='0'; + if unsigned(p_len)>0 then + --if n=0 then +-- n_i<=1; --cycle d'attente pour la RAM +-- Wr_ok<='0'; +-- elsif n=1 then + if switch_port_in_full = '0' then + if n=1 then --creer un délai sur ces signaux par rapport à src_adress + p_len_i <= p_len - 1; + Wr_Ok<='1'; + end if; + n_i<=1; + src_address_i <= src_address+1; + Next_ex1_state <= ex1_put3; + + + else + Wr_Ok<='0'; + src_address_i <= src_address; + n_i<=0; + end if; + --elsif n=2 then +-- n_i<=0; --cycle d'attente pour la RAM +-- Wr_ok<='0'; +-- src_address_i <= src_address ; --prochaine lecture +-- +-- end if; + else + Wr_Ok<='0'; + Next_ex1_state <= ex1_put4; + end if; + when ex1_put4 =>rd_ok<='1'; + wr_ok<='0'; + if dma_rd_grant = '1' then -- fin du mpi_put + Next_ex1_state <= ex1_put5; + rd_ok<='0'; + n_i<=0; + data_to_send_i<="00000001"; + else + Next_ex1_state <= ex1_put4; + end if; + + if fifo_src='0' then --détection Put ou Get + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + else + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + end if; + when ex1_put5 => if n >0 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + rd_ok<='0';wr_ok<='0'; + if n=0 then + + n_i<=n+1; + elsif n=1 then + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + dma_wr<='1'; + dma_rd<='1'; + elsif n=2 then + if dma_rd_grant='1' then + n_i<=n+1; + dma_wr<='1'; + tempval:=Ram_data_in; + data_to_send_i<=ram_data_in; + end if; + rd_ok<='1'; + wr_ok<='0'; + + dma_rd<='1'; + elsif n=3 then + dma_rd<='1'; + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_in; + data_to_send_i<=ram_data_in; + --src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + tempval(5):='1'; -- SET du bit DSENT + data_to_send_i(5)<='1'; + if fifo_src='0' then -- c'est un put qui est exécuté + tempval(5):='1'; -- SET du bit DSENT + --data_to_send_i<=ram_data_in or "00100000"; + else -- c'est un Get qui est exécuté + --tempval(2):='1'; -- ne pas annuler le sending après un GET + --data_to_send_i<=ram_data_in or "00000100"; + end if; + --data_to_send_i<=tempval; --A tester + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + dma_rd<='0'; --libérer le bus et revenir en arrière + dma_wr<='0'; + n_i<=0; + end if; + elsif n=3 then + if dma_wr_grant = '1' and dma_rd_grant='1' then + n_i<=n+1; + + --src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + end if; + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='1'; + elsif n=4 then + if dma_wr_grant = '1' and dma_rd_grant='1' then + n_i<=n+1; + + src_address_i<=std_logic_vector(to_unsigned(core_put_adr+6,16)); + + end if; + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='1'; + elsif n=5 then + if dma_wr_grant = '1' then + n_i<=n+1; + + -- SET du bit DSENT + data_to_send_i<="00000001"; + end if; + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='0'; + elsif n=6 then + n_i<=0; + Next_ex1_state <= fifo_select; + rd_ok<='0'; + wr_ok<='0'; + dma_wr<='0'; + dma_rd<='0'; + end if; + + + when ex1_get1 => wr_ok<='0'; + if switch_port_in_full = '0' and n = 0 then -- execution du mpi get + --écrire l'entête de la fonction + n_i<= n + 1; + Wr_ok<='0'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 1 then -- execution du mpi get + data_to_send_i <= "00001000"; -- longueur du paquet sur le réseau ? + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 2 then + data_to_send_i <= "0000"&pid; -- Rang source + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 3 then + data_to_send_i <= p_len; + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 4 then + data_to_send_i <= src_address(15 downto 8); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 5 then + data_to_send_i <= src_address(7 downto 0); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 6 then + data_to_send_i <= dest_address(15 downto 8); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 7 then + data_to_send_i <= dest_address(7 downto 0); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 8 then + Next_ex1_state <= ex1_get2; + n_i<=0; + Wr_ok<='1'; + else + Next_ex1_state <= ex1_get1; + end if; + when ex1_get2 => if dma_wr_grant = '1' then + Next_ex1_state <= ex1_get3; + src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16)); + data_to_send_i<="00000001"; + else + Next_ex1_state <= ex1_get2; + end if; + dma_wr<='1'; + when ex1_send_ack |ex1_Wsync=> rd_ok<='0'; + if n = 0 then -- execution du mpi ack /ou Mpi_Win_sync + if switch_port_in_full = '0' then + + wr_Ok<='0'; --envoie de la première donnée(code ack) + n_i<= n + 1; + onepop:='0'; + + end if; + elsif n = 1 then + if fifo_empty='0' and onepop='0' then + data_to_send_i <=p_len ; + + rd_Ok<='1'; --passe la longueur + onepop:=not onepop; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok<='0'; + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:=not onepop; + n_i<= n + 1; + wr_ok<='1'; + elsif (switch_port_in_full = '1') then + wr_Ok<='0'; + + end if; + + elsif (n= 2) then + if fifo_empty='0' and onepop='0' then + + data_to_send_i <=fifo_data_out; + rd_Ok<='1'; + onepop:=not onepop; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok<='0'; + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:=not onepop; + n_i<= n + 1; + wr_ok<='1'; + else + wr_Ok<='0'; + + end if; + elsif (n= 3) then + if fifo_empty='0' and onepop='0' then + + data_to_send_i <=fifo_data_out; + rd_Ok<='1'; + onepop:=not onepop; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok<='0'; + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:=not onepop; + n_i<= n + 1; + wr_ok<='1'; + + else + wr_Ok<='0'; + + end if; + elsif n = 4 then + n_i<=0; + Wr_Ok<='1'; + rd_ok<='0';--vider le tampon + Next_ex1_state <= fifo_select; + + end if; + + when ex1_get3 =>if n<2 then --ecriture de la fin d'envoie + if dma_wr_grant = '1' then -- fin du post de mpi_get + + n_i<=n+1; + data_to_send_i<="00000001"; + wr_ok<='1'; + rd_ok<='0'; + end if; + + elsif n=2 then + n_i<=0; + Next_ex1_state <= ex1_get4; + end if; + src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16)); + when ex1_get4 => wr_ok<='0'; + rd_ok<='0'; + dma_wr<='1'; + dma_rd<='1'; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + + if n=0 then + + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=1 then + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=2 then + if dma_rd_grant='1' then + n_i<=n+1; + rd_ok<='1'; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + else + n_i<=1; + end if; + + elsif n=3 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_in; + data_to_send_i<=Ram_data_in; + rd_ok<='1'; + wr_ok<='0'; + dma_wr<='1'; + dma_rd<='1'; + else + dma_wr<='0'; + dma_rd<='0'; + n_i<=n-1; + end if; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + elsif n=4 then + if dma_wr_grant = '1' and dma_rd_grant='1' then + n_i<=n+1; + rd_ok<='0'; + wr_ok<='1'; + tempval(6):='1'; --SET du bit Windows Busy --car réception Get + tempval(1):='1'; -- SET du bit DReceiving + data_to_send_i(6)<='1'; + data_to_send_i(1)<='1'; + --data_to_send_i<=tempval; -- à tester absolument !!! + else + rd_ok<='0'; + wr_ok<='1'; + n_i<=1; + end if; + dma_wr<='1'; + dma_rd<='1'; + elsif n=5 then + wr_ok<='1'; + if dma_wr_grant = '1' then + n_i<=n+1; + end if; + elsif n=6 then + n_i<=0; + Next_ex1_state <= fifo_select; + dma_wr<='0'; + dma_rd<='0'; + end if; + + when ex1_spawn => rd_ok<='0'; + if n = 0 then -- execution du mpi spawn + if switch_port_in_full = '0' then + + wr_Ok<='0'; + n_i<= n + 1; + onepop:='0'; + --data_to_send_i<=len; + end if; + elsif n = 1 then + if fifo_empty='0' and onepop='0' then + data_to_send_i <=p_len ; + + rd_Ok<='1'; + onepop:='1'; --une donnée lue il faut arrêter de dépiler + + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:='0'; + n_i<= n + 1; + wr_ok<='1'; + else + wr_Ok<='0'; + + end if; + + elsif (n= 2) or (n=3) then + if fifo_empty='0' and onepop='0' then + + data_to_send_i <=fifo_data_out; + rd_Ok<='1'; + onepop:='1'; --une donnée lue il faut arrêter de dépiler + + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:='0'; + n_i<= n + 1; + wr_ok<='1'; + else + wr_Ok<='0'; + + end if; + elsif n=4 then + n_i<=0; + Wr_Ok<='1'; + rd_ok<='0'; + Next_ex1_state <= fifo_select; + end if; + -- execution du barrier + when ex1_barrier1 => if switch_port_in_full = '0' then + Next_ex1_state <= ex1_barrier2; + else + Next_ex1_state <= ex1_barrier1; + end if; + when ex1_barrier2 => if switch_port_in_full = '0' then + Next_ex1_state <= ex1_barrier3; + else + Next_ex1_state <= ex1_barrier2; + end if; + when ex1_barrier3 => if switch_port_in_full = '0' then + Next_ex1_state <= ex1_barrier4; + else + Next_ex1_state <= ex1_barrier3; + end if; + when ex1_barrier4 => if packet_type = MPI_BARRIER_COMPLETED and pid_counter < nprocs then + pid_counter_i <= pid_counter + 1; + Next_ex1_state <= ex1_barrier1; + else + Next_ex1_state <= fifo_select; + end if; + when ex1_init1 => rd_ok<='0'; + if n=0 then + n_i<=n+1; + Len_i<=len-2; --deux données a été dépilée + elsif n=1 then --vider le fifo instruction + if len>0 then + if fifo_empty='0' then + rd_ok<='1'; + Len_i<=len-1; + + else + rd_ok<='0'; + Len_i<=Len; + end if; + else + n_i<=n+1; + end if; + elsif n=2 then -- + n_i<=0; + rd_ok<='0'; + Next_ex1_state<=ex1_init_run; + + end if; + + when ex1_init_run=> if n=0 then + if snd_start='1' then --le module ex4 veut envoyer des données + + n_i<=n+1; + + for i in 0 to 3 loop + mem_i(i)<=snd_data(i); + end loop; + if snd_data(0)(7 downto 4)=MPI_INIT or + snd_data(0)(7 downto 4)=MPI_SPAWN or + snd_data(0)(7 downto 4)=MPI_ACK then + + else + report "Ex1 : Une instruction inconnue a été envoyé par Ex4 sur le réseau !"; + end if; + P_len_i<=x"04"; + fifo_copy<='0'; + snd_ack1<='0'; + + end if; + if AppInitAck='1' then + Next_ex1_state<=ex1_init2; + end if; + elsif n=1 then + fifo_sel<='0';--pas de rotation du fifo instruction + snd_start1<='1'; + P_len_i<=x"04"; + fifo_copy<='0'; + snd_ack1<='0'; + + n_i<=n+1; + elsif n=2 then + snd_start1<='1'; + if snd_comp='1' then + snd_ack1<='1'; + + snd_start1<='0'; + n_i<=n+1; + end if; + elsif n=3 then + snd_start1<='0'; + snd_ack1<='1'; + fifo_sel<='0'; + if snd_start='0' then --attente l'annulation de l'envoie + n_i<=0; + snd_ack1<='0'; + if run_init='1' then + Next_EX1_state<=fifo_select; + --run_init<='0'; + end if; + end if; + end if; + + + when ex1_init2 => -- écriture dans le registre status reg. + src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16)); + if n=0 then --envoie du message Spawn Ack sur le réseau + if instruction(6)='1' then --Spawned=1 ? + n_i<=1; --envoie du message Spawn à main lib + data_to_send_i<="01010000"; --init+spawn + else + n_i<=4; --écrire le résultat de la fn + data_to_send_i<="00010000"; --init seul + end if; + + elsif n=1 then + n_i<=n+1; + mem_i(0)<=MPI_INIT & x"0"; --répondre au premier + mem_i(1)<=x"04"; + mem_i(2)<=x"00"; + mem_i(3)<=INIT_SPAWN & pid;-- indiquer qui répond au + elsif n=2 then + snd_start1<='1'; + n_i<=n+1; + fifo_copy<='0'; + elsif n=3 then + fifo_copy<='0'; + snd_start1<='1'; + if snd_comp='1' then + snd_ack1<='1'; + snd_start1<='0'; + n_i<=n+1; + end if; + elsif n=4 then --écriture du registre status + dma_wr<='1'; + wr_ok<='1'; + if dma_wr_grant = '1' then -- fin du mpi_init + n_i<=n+1; + end if; + elsif n=5 then + wr_ok<='1'; + dma_wr<='1'; + if dma_wr_grant = '1' then -- fin du mpi_init + n_i<=n+1; + end if; + elsif n=6 then + Next_ex1_state <= ex1_init3; + n_i<=0; + wr_ok<='0'; + end if; + + + when ex1_init3 =>--if AppInitAck='1' then + Next_ex1_state <= fifo_select; + --end if; + when ex1_ready => Next_ex1_state <= fifo_select; + when others => Next_ex1_state <= fifo_select; + end case; + + end process; + + -- sortie de la machine à etat + ex1_fsm_action : process(ex1_state, fifo_empty, switch_port_in_full, p_len,pid, + pid_counter, dma_rd,dma_wr,ram_data_in,AppInitAck,fifo_wr,noc_fifo_in,data_to_send, packet_type, wr_ok,rd_ok, + fifo_rd) + variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0'); + begin +-- code fonctionnel + Result_i<=Result1; + case ex1_state is + when fifo_select => priority_rotation <='1'; -- on peut changer la priorité + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result_i <=(others=>'0'); + Ready<='1'; + when read_status1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result_i <=(others=>'0'); + Ready<='0'; + when read_status2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + status_reg:=Ram_data_in; + Result_i <=(others=>'0'); + Ready<='0'; + when fetch_packet_type => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= (others =>'0'); + AppInitReq<='0'; + switch_port_in_wr_en <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + + when decode_packet_type => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= Data_To_Send; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when fetch_addresses => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when decode_packet_type2 =>priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= packet_type & pid_counter; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= p_len; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= "0000" & pid; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= "0000" & pid; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_get1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= Wr_ok; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + when ex1_get2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <='0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= dma_Wr; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_get3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others=>'0');---??? + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; -- le résultat de l'exécution + Ready<='0'; -- fin du module + Result_i <=(2=>'1',others=>'0');--Get completed + when ex1_get4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; --"00000001"; + Result_i <=(2=>'1',others=>'0'); --get completed + Ready<='0'; -- fin du module + when ex1_put1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_put2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + Ram_rd<='1'; + Ram_wr<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_put3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_data_in; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_put4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_data_in;---??? + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= rd_ok; + dma_wr_request <= wr_ok; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution + --result(1)<='1'; + Result_i <=(1=>'1',others=>'0');--put completed + Ready<='0'; -- fin du module + when ex1_put5 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; --"00000001"; + Result_i <=(1=>'1',others=>'0'); --put completed + Ready<='0'; -- fin du module + when ex1_init1 => priority_rotation <='0'; + if fifo_empty='0' then + fifo_rd_en <= rd_ok; + else + fifo_rd_en<='0'; + end if; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= wr_ok; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='1'; + Result_i <=(others=>'0'); + Ready<='0'; + when ex1_init_run => priority_rotation <='0'; + + fifo_rd_en <= fifo_rd; + + switch_port_in_data <= noc_fifo_in; + switch_port_in_wr_en <= fifo_wr; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='1'; + Result_i <=(others=>'0'); + Ready<='0'; + + when ex1_init2=> priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= noc_fifo_in; + switch_port_in_wr_en <= fifo_wr; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<=wr_ok; + Ram_data_out<=Data_to_send; -- le résultat de l'exécution + Ready<='0'; -- dans le registre status + Result_i <=(others=>'0');-- + when ex1_init3=> priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<='1'; + Ram_data_out<="00010000"; + Ready<='0'; -- fin du module + Result_i<=(0=>'1',others=>'0'); --le résultat de l'initialisation est écrit + + when ex1_spawn => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= Data_to_send; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when ex1_send_ack|ex1_Wsync => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= Data_to_send; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when ex1_ready => + Ready<='1'; -- fin du module + priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Ready<='0'; + + when others => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result_i <=(others=>'0'); + Ready<='0'; + end case; + + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX2_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX2_FSM.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX2_FSM.vhd (revision 138) @@ -0,0 +1,1722 @@ +---------------------------------------------------------------------------------- +-- Company: GRIIA - ETIS - LIP6 +-- Engineer: GAMOM, KIEGAING +-- +-- Create Date: 01:02:10 06/17/2011 +-- Design Name: +-- Module Name: EX2_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- machine a etat qui execute la reception des packet dans le core mpi +-- Dependencies: +--ss +-- Revision: 26/01/2012 +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +library NocLib ; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.Numeric_std.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use Work.Packet_type.ALL; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX2_FSM is + + generic ( + pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur + nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1 + ); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + + Instruction_en : in std_logic; + + dma_wr_grant : in STD_LOGIC; + dma_wr_request : out STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + ram_rd : out std_logic; + ram_wr : out std_logic; + ram_address : out std_logic_vector(ADRLEN-1 downto 0); + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + + fifo_data : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_wr_en : out STD_LOGIC; + fifo_full : in STD_LOGIC; + Rec_Rdy : OUT std_logic; + Rec_Data : buffer Typ_PortIO(0 to 3); + Rec_Ack : IN std_logic; + AppRank : in STD_LOGIC_VECTOR(3 downto 0); + AppSize : in STD_LOGIC_VECTOR(3 downto 0); + packet_received : out STD_LOGIC; + packet_ack : in STD_LOGIC; + barrier_completed : out STD_LOGIC; + Ready : Out std_logic; + AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic ; -- état de la Lib + Result : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module + switch_data_available : in STD_LOGIC; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_out_rd_en : out STD_LOGIC + + + + ); +end EX2_FSM; + +architecture Behavioral of EX2_FSM is +--module pour la lecture des données sur le réseau +CONSTANT MSIZE : natural :=4; --taille de la mémoire tampon pour les messages reçu +component Proto_receiv is + generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_empty,fifo_full : in std_logic; + rcv_start : in std_logic; --début de la réception + rcv_ack :in std_logic; -- acquittement de la réception + rcv_comp : out std_logic; -- fin de la réception + pop : out std_logic:='0'; + fifo_out : in std_logic_vector(Word-1 downto 0); + mem :out memory(0 to sizemem-1)); +end component Proto_receiv; + +COMPONENT SetBit + PORT( + clk : IN std_logic; + reset : IN std_logic; + BitMask : IN std_logic_vector(7 downto 0); + BitVal : IN std_logic; + start : in std_logic; + whole : in std_logic; + done : out std_logic; + dma_wr_grant : IN std_logic; + dma_rd_grant : IN std_logic; + Ram_data_in : out std_logic_vector(7 downto 0); + dma_wr_request : OUT std_logic; + dma_rd_request : OUT std_logic; + ram_rd : OUT std_logic; + ram_wr : OUT std_logic; + ram_address : IN std_logic_vector(15 downto 0); + Ram_data_out : in std_logic_vector(7 downto 0) + ); + End component SetBit; +--constante +constant Max_stack : integer:=7;--Le nombre de GET qui peuvent être empilés +-- définition du type etat de la machine à etat +type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2, +fetch_addresses,ex2_spawn1,ex2_spawn2,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4, +ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack1,ex2_ack2,ex2_ack3, + Ex2_WSync,Ex2_WComp,ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4, + ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2,Ex2_Set_Busy); +type fsm_ack is(ack0,ack_readwait,ack_checkwait,ack1,ack2,ack3,ack4,ack5,ack6); +type mem32 is array (natural range <>) of std_logic_vector (31 downto 0); +signal Next_Ex2_state,ex2_state :fsm_states; +signal ack_state,next_ack_state : fsm_ack; +-- +signal mode_get,match_get:std_logic:='0'; +signal mode_get_i,match_get_i:std_logic:='0'; +-- machine a etat du module +signal packet_type, packet_type_i : std_logic_vector(3 downto 0); +signal P_len_i,P_len : std_logic_vector(Word-1 downto 0); +signal barrier_counter,barrier_counter_i : std_logic_vector(3 downto 0); +signal pading_data,data_to_ram,Data_to_ram_i : std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal n,n_i : natural range 0 to 15; +signal dest_address,dest_address_i,ack_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0'); +signal data_to_write_fifo,data_to_write_fifo_i : std_logic_vector(Word-1 downto 0); +--******************************************* +--signaux pour la fonction SetBit +signal sb_BitMask : std_logic_vector(7 downto 0):=(others=>'0'); +signal sb_BitVal,sb_start,sb_done : std_logic:='0'; +signal sb_whole : std_logic:='0'; --écrire le mot entier +signal sb_Ram_data_in : std_logic_vector(7 downto 0); +signal sb_dma_wr_request : std_logic; +signal sb_dma_rd_request : std_logic; +signal sb_ram_rd : std_logic; +signal sb_ram_wr : std_logic; +signal sb_ram_address : std_logic_vector(15 downto 0):=(others=>'0'); +signal sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0'); +-- deuxième module pour set busy bit +signal Set_Wbusy : std_logic:='0'; --choix du Mux +signal GPost_Set,Gpost_Set_i : std_logic:='0'; --indique l'arrivée de Win_Compl + +--********************************************* +signal Ex2_on : std_logic:='0'; +signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; +signal sent_ack, sent_ack_i,wr_ack,instr_ack,Instr_ack_i:std_logic:='0'; --signaux pour la gesion de l'acquittement +signal dest_ack,dest_ack_i:std_logic_vector(3 downto 0) :=(others=>'0'); +signal to_fifo_ack :std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal Result_i,result1 : STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); +--signaux pour l'untilisation du composant de réception +signal rfifo_empty,rfifo_full:std_logic; +signal rcv_start,rcv_comp,rcv_ack:std_logic; +signal rpop:std_logic; +signal initreq,initreq_i:std_logic:='0'; --Requete d'initialisation +--signal mem:memory(0 to Msize-1)); +--jusqu'à 16 Get peuvent être attendus! +signal Wcomp : std_logic:='0'; --indique que tous les transferts sont terminés +signal WStart,WPost,WBUSY, WBUSY_i,RGET,RGET_i: std_logic:='0'; -- +signal Rec_WPost,Rec_WPost_i,GComp,GComp_i, GPost_i,GPost: std_logic_vector(Max_Stack downto 0):=(others=>'0'); +signal Waited_Get,Waited_Get_i : mem32(0 to Max_stack); +Signal Rec_Data_i : Typ_PortIO(0 to 3); +signal Get_Instr,Get_instr_i,Put_instr,Put_instr_i :memory(0 to 8); +signal Put_Id : std_logic_vector(31 downto 0):=(others=>'0'); +signal P_G,P_G_i: natural range 0 to 3:=0; --Msg Ack : 1 -> Put, 2-->Get +signal Ptr_Get,Ptr_Get_i : natural range 0 to Max_stack:=0; +signal Received_get,Received_get_i : std_logic_vector(Max_stack downto 0):=(others=>'0');--sera remis à 0 lorsque Wstart/WPost est reçu +begin + +ram_address <= ack_address when instr_ack='1' else dest_address; +--fifo_data <= data_to_write_fifo; +Result<=Result1; +p_instr_fifo:process(ack_state,data_to_write_fifo_i,wr_ack,to_fifo_ack,instr_ack) +begin + if instr_ack='1' then + fifo_data<=to_fifo_ack; +else + fifo_data<=data_to_write_fifo_i; +end if; +end process p_instr_fifo; + + + +R0:proto_receiv generic map (sizemem =>4) + port map ( + clk=>clk, + reset=>reset, + rcv_start=>rcv_start, + rcv_comp=>rcv_comp, + rcv_ack=>rcv_ack, + fifo_empty=>rfifo_empty, + fifo_full=>rfifo_full, + fifo_out=>switch_port_out_data, + pop=>rpop, + mem=>open + + ); +--envoie de l'acquittement +setbit1:SetBit + PORT MAP ( + clk =>clk, + reset =>reset, + BitMask =>sb_bitMask, + BitVal =>sb_bitval, + dma_wr_grant =>dma_wr_grant, + dma_rd_grant =>dma_rd_grant, + Ram_data_in => sb_Ram_data_in, + dma_wr_request =>sb_dma_wr_request, + dma_rd_request =>sb_dma_rd_request, + ram_rd =>sb_ram_rd, + ram_wr =>sb_ram_wr, + ram_address =>dest_address, + Ram_data_out =>sb_ram_data_out, + Start =>sb_start, + whole=>sb_whole, + done =>sb_done + ); + +-- processus de transistion entre les etats +ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized, + switch_data_available,switch_port_out_data,sb_ram_data_in,Data_to_Ram,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len, + sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy,Ptr_Get,Get_Instr,P_G,Waited_get,Received_get,rget,GPost,GPost_Set,packet_type,barrier_counter, + dest_ack,rec_wpost,Gcomp,rec_data,mode_get,match_get,Instr_ack,result1,data_to_write_fifo) +variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée +variable tempval : std_logic_vector(Word-1 downto 0); +variable n_e,i:natural range 0 to 15 :=0; + +--=================================================================- +procedure read_nocdat_fsm(sdata_avail: std_logic; +signal rd,wr:out std_logic; +signal Plen_i : in std_logic_vector(Word-1 downto 0); +signal Plen_o : out std_logic_vector(Word-1 downto 0); +variable n:out natural range 0 to 15;signal n_e:in natural range 0 to 15) is +--lit la suite des données qui sont dans le NoC et identifie le paramètre important +begin +if n_e<3 then + wr<='0'; + if sdata_avail='1' then + n:=n_e+1; + rd<='1'; + plen_o <=plen_i-1; + else + rd<='0'; + end if; + --result_i<=(others=>'0'); + elsif n_e=3 then + if sdata_avail='1' then + n:=n_e+1; + rd<='0'; + --P_len <=P_len_i -1; + --data_to_ram<=sportdout; + --Result_i<=sport_out_data; + else + rd<='0'; + end if; + end if; +end procedure; + +begin + + Next_Ex2_state <= Ex2_state; + Ex2_on<='0'; + sb_whole<='0'; + sb_start<='0'; --valeur par défaut + sb_bitmask<=x"FF"; + sb_bitval<='1'; + dma_rd<='0'; + dma_wr<='0'; + rd_ok<='0'; + wr_ok<='0'; + barrier_counter_i <= barrier_counter; + GPost_Set_i<=GPost_Set; + Rec_WPost_i<=Rec_WPost; + GPost_i<=GPost; + P_G_i<=P_G; + RGET_i<=RGET; + WBUSY_i<=WBUSY; + Result_i<=Result1; + Ptr_get_i<=Ptr_get; + mode_get_i<=mode_get; + data_to_write_fifo_i<=data_to_write_fifo; + match_get_i<=match_get; + GComp_i<=GComp; + Instr_ack_i<=Instr_ack; + received_get_i<=received_get; + mode_get_i<=mode_get; + InitReq_i<=InitReq; + match_get_i<=match_get; + Data_to_ram_i<=Data_to_ram; + dest_address_i<=dest_address; + for i in 0 to Max_stack loop + Waited_get_i(i)<=Waited_get(i); + end loop; + For i in 0 to 7 loop + Get_Instr_i(i)<=Get_instr(i); + end loop; + Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non + n_i<=n; --valeur par défaut de n_i + P_len_i<=P_len; + for i in 0 to 3 loop + Rec_Data_i(i)<=Rec_Data(i); + Packet_type_i<=Packet_type; + dest_ack_i<=dest_ack; + end loop; + case ex2_state is + when Ex2_ready => if Instruction_en='1' and switch_data_available='1' then + Next_Ex2_state <= fetch_packet_type; + end if; + rd_ok<='0';wr_ok<='0'; + when fetch_packet_type => if switch_data_available ='1' and Instruction_en='1' then --and initialized ='1' + Next_Ex2_state <= decode_packet_type; + packet_type_i<=switch_port_out_data(7 downto 4); + Dest_ack_i<=switch_port_out_data(3 downto 0); + Rec_Data_i(0)<=switch_port_out_data; --récupérer la première donnée reçue ! + rd_ok<='1'; + else + --Next_Ex2_state <= Ex2_Ready; + rd_ok<='0'; + end if; + n_i<=0; + when decode_packet_type => rd_ok<='0'; + if switch_data_available ='0' then + Next_Ex2_state <= decode_packet_type; + else + rd_ok<='1'; + Rec_Data_i(1)<=switch_port_out_data-2; + if packet_type = MPI_PUT then + P_len_i <= switch_port_out_data - 2; + n_i<=0; + + Next_Ex2_state <= decode_packet_type2; + elsif packet_type = MPI_GET then + P_len_i <=switch_port_out_data-2; + Next_Ex2_state <= decode_packet_type2; + elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then + P_len_i <= switch_port_out_data; + n_i<=0; + Next_Ex2_state <= ex2_barrier1; + elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then + n_i<=0; + wr_ok<='0'; + --rd_ok<='1'; + P_len_i <= switch_port_out_data-2; + Rec_Data_i(1)<=switch_port_out_data; + Next_Ex2_state <= ex2_init1; + elsif packet_type = MPI_ACK then + n_i<=0; + wr_ok<='0'; + rd_ok<='0'; + P_len_i <= switch_port_out_data-2; + Next_Ex2_state <= ex2_ack1; + elsif packet_type = MPI_WIN_SYNC then + n_i<=0; + wr_ok<='0'; + rd_ok<='0'; + P_len_i <= switch_port_out_data-2; + Next_Ex2_state <= ex2_Wsync; + elsif packet_type = MPI_SPAWN then + Next_Ex2_state <= ex2_spawn1; + wr_ok<='0'; + rd_ok<='0'; + else + Next_Ex2_state <= decode_packet_type; + rd_ok<='0'; + end if; + end if; + when decode_packet_type2 => if packet_type = MPI_PUT then + Next_Ex2_state <= fetch_addresses; + else + Next_Ex2_state <= ex2_get1; + end if; + when fetch_addresses => if n=0 then + if switch_data_available = '1' then + dest_address_i(15 downto 8) <= switch_port_out_data; + Rec_data_i(2)<=switch_port_out_data; + n_i <= n + 1; + rd_ok<='1'; + else + rd_ok<='0'; + end if; + elsif n=1 then + if switch_data_available = '1' then + dest_address_i(Word-1 downto 0) <= switch_port_out_data; + Rec_data_i(3)<=switch_port_out_data; + P_len_i <= P_len - 2; + Next_Ex2_state <= ex2_put1; + n_i<=0; + rd_ok<='1'; + else + rd_ok<='0'; + Next_Ex2_state <= fetch_addresses; + end if; + end if; + when ex2_ack1 => rd_ok<='0'; + if n<2 then --réception de l'acquittement. + n_e:=n; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); + n_i<=n_e; + elsif n=2 then + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + + data_to_ram_i<=switch_port_out_data; + Result_i<=switch_port_out_data; + end if; + + elsif n=3 then + n_i<=n+1;P_G_i<=0; + if data_to_ram(7 downto 4)=MPI_PUT then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr,16)); + wr_ok<='1'; + P_G_i<=1; --put ou get + P_len_i<=x"06"; --longueur de l'entête à parcourir + elsif data_to_ram(7 downto 4)=MPI_GET then + Result_i<=data_to_ram; + wr_ok<='1'; -- + P_G_i<=2; --put get + P_len_i<=x"06";--taille de l'instruction en mémoire + dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr,16)); + elsif data_to_ram(7 downto 4)=MPI_SPAWN then + Result_i<=data_to_ram; + wr_ok<='1'; -- + dest_address_i<=std_logic_vector(to_unsigned(Core_Spawn_adr+7,16)); + elsif data_to_ram(7 downto 4)=MPI_INIT then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Core_Init_adr+7,16)); + wr_ok<='1'; -- + -- + else + Result_i<="00000000"; + wr_ok<='0'; -- + n_i<=n; --code inconnu ! + end if; + elsif n=4 then + if P_G=1 or P_G=2 then + Next_ex2_state<=ex2_ack2; + else + Next_ex2_state<=ex2_ack3; + end if; + n_i<=0; + end if; + + when Ex2_ack2 =>if unsigned(p_len)>0 then + If Dma_rd_grant='1' then + if n=0 then + n_i<=n+1; --cycle d'attente pour la RAM + elsif n=1 then + dest_address_i <= dest_address+1; + n_i<=2; + elsif n>=2 then + + --creer un délai sur ces signaux par rapport à src_adress + + n_i<=n+1; + rd_ok<='1'; +-- if n>1 then + dest_address_i <= dest_address+1; + p_len_i <= p_len - 1; + --end if; + Get_Instr_i(n-2)<=Ram_data_out; --deux cycles de retard + Next_ex2_state <= ex2_ack2; + end if; + end if; + dma_rd<='1'; + rd_ok<='1'; + else + if P_G=1 then + dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16)); + else + dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16)); + Waited_get_i(ptr_get)(7 downto 0)<=Get_instr(0); --id + Waited_get_i(ptr_get)(15 downto 8)<=Get_instr(1); --longueur + Waited_get_i(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas + Waited_get_i(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut + RGET_i<='1'; + + Ptr_Get_i<=Ptr_Get+1; --prochain Get à traiter + end if; + Next_ex2_state <= ex2_ack3; + n_i<=0; --suite du process ack + rd_ok<='0'; + dma_rd<='0'; + end if; + +when ex2_ack3 => if n=0 then --set acknowlege bit of the instruction + sb_start<='1'; + sb_bitMask<=x"20";--cinquième bit à un + sb_bitval<='1'; + sb_whole<='0';--Modifier un seul bit ! + if sb_done='1' then + n_i<=1; + sb_start<='0'; + sb_bitval<='0'; + dest_address_i<=dest_address+1; + end if; + + elsif n=1 then + sb_start<='1'; + sb_bitMask<=Rec_Data(2); + sb_bitval<='1'; + sb_whole<='1'; + if sb_done='1' then + n_i<=n+1; + sb_start<='0'; + sb_bitval<='0'; + sb_whole<='0'; + end if; + + elsif n=2 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + end if; + + when ex2_Wsync => rd_ok<='0'; + if n<2 then --réception de la synchronisation. + n_e:=n; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); + n_i<=n_e; + elsif n=2 then + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + + data_to_ram_i<=switch_port_out_data; + Result_i<=switch_port_out_data; + end if; + + elsif n=3 then + n_i<=n+1;P_G_i<=0; + if data_to_ram(7 downto 4)=SYNC_WSTART then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); + wr_ok<='1'; + P_G_i<=1; --put ou get + P_len_i<=x"06"; --longueur de l'entête à parcourir + elsif data_to_ram(7 downto 4)=SYNC_WPOST then + Result_i<=data_to_ram; + wr_ok<='1'; -- + P_G_i<=2; --put get + P_len_i<=x"06";--taille de l'instruction en mémoire + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); + elsif data_to_ram(7 downto 4)=SYNC_WWAIT then + Result_i<=data_to_ram; + wr_ok<='1'; -- + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+7,16)); + elsif data_to_ram(7 downto 4)=SYNC_WCOMP then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); + wr_ok<='1'; -- + Next_Ex2_State<=Ex2_WCOMP; + n_i<=0; + else + Result_i<="00000000"; + wr_ok<='0'; -- + n_i<=n; --code inconnu ! + end if; + + end if; + when Ex2_Wcomp => dma_rd<='1'; + rd_ok<='1'; + + if n=0 then + n_i<=n+1; --cycle d'attente pour la RAM + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + GComp_i(i)<='1'; + elsif n=1 then + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); + If Dma_rd_grant='1' then + n_i<=2; + end if; + elsif n=2 then + If Dma_rd_grant='1' then + --creer un délai sur ces signaux par rapport à dest_adress + n_i<=n+1; + rd_ok<='1'; + dest_address_i <= dest_address+1; + GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard + + else + n_i<=1; + end if; + elsif n=3 then + If Dma_rd_grant='1' then + --GPost_i(15 downto 8)<=Ram_data_out; --Uncomment if needed + n_i<=n+1; + rd_ok<='1'; + dma_rd<='1'; + end if; + elsif n=4 then + --GPost_i(15 downto 8)<=Ram_data_out; --Uncomment if needed + + rd_ok<='1'; + dma_rd<='1'; + n_i<=n+1; + elsif n=5 then + rd_ok<='0'; + dma_rd<='0'; + n_i<=0; + If GPost=GComp then --le même nombre de post que de COmpleted ? + GPost_Set_i<='1'; + end if; + + Next_ex2_state <= ex2_set_busy; + end if; + + + when ex2_init1 => if n<2 then -- execution du mpi Init + wr_ok<='0'; + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + P_len_i <=P_len-1; + Rec_Data_i(n+2)<=switch_port_out_data; + data_to_ram_i<=switch_port_out_data; + Result_i<=switch_port_out_data; + else + rd_ok<='0'; + n_i<=n; + end if; + result_i<=(others=>'0'); + elsif n=2 then + n_i<=n+1; + rd_ok<='0'; + + elsif n=3 then + rd_ok<='0'; -- normalement plus rien à lire + n_i<=n+1; + if Initialized='1' then + if data_to_ram(7 downto 4)=INIT_SEEKMAIN then + Result_i<=data_to_ram; + InitReq_i<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=INIT_STAT then + Result_i<=data_to_ram; + InitReq_i<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=INIT_REGISTER then + Result_i<=data_to_ram; + InitReq_i<='0'; --permet d'activer Init de Ex_4 + report "Mise à jour des données d'initialisation"; + Next_Ex2_state<=ex2_ready; + n_i<=0; + elsif data_to_ram(7 downto 4)=INIT_SPAWN then + Result_i<=data_to_ram; + InitReq_i<='1'; --permet d'activer Init de Ex_4 + -- il faut mettre à jour l'état de Spawn + else + Result_i<="00000000"; + InitReq_i<='0'; --permet d'activer Init de Ex_4 + end if; + end if; + elsif n=4 then + n_i<=n+1; + elsif n=5 then + if p_len=0 then + Next_Ex2_state<=ex2_init2; + rd_ok<='0'; + else + p_len_i <=p_len -1; + rd_ok<='1'; --vider le tampon de lecture pour ce paquet ! + end if; + + end if; + when ex2_init2=> if n=5 then + if AppInitAck='1' then + n_i<=n+1; + InitReq_i<='0'; + Result_i<="00000001"; -- cette valeur permet d'acquitter la fonction Init + end if; + elsif n=6 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + InitReq_i<='0'; + end if; + + when ex2_put1 => rd_ok<='0'; --ne pas autoriser la lecture du switch + wr_ok<='0'; + dma_rd<='1'; + if n=0 then + if RGET='1' then + Lp: for i in 1 to Max_stack loop -- to Ptr_get normalement + if i<=Ptr_Get then + if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and + waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and + waited_get(i-1)(23 downto 16)=rec_data(2) and + waited_get(i-1)(31 downto 24)=rec_data(3) then + if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then + + match_get_i<='1'; + end if; + else + + end if; + end if; + exit Lp when i= Ptr_get; + end loop Lp; + end if; + + n_i<=1; + elsif n=1 then + if match_get='1' then + n_i<=3; --ne pas envoyer ack dans ce cas + report "GET Détecté ACK pas envoyé dans Ex2 du HCL n°" & image(pid); + else + n_i<=2; + end if; + elsif n=2 then + instr_ack_i<='1'; --activer l'envoie de l'accusé de réception + data_to_write_fifo_i<=to_fifo_ack; + wr_ok<=wr_ack; + if sent_ack='1' then + n_i<=3; + instr_ack_i<='0'; + dma_wr<='1'; + end if; + + elsif n=3 then + dma_wr<='1'; + if dma_wr_grant = '1' then + Next_Ex2_state <= ex2_put2; + data_to_ram_i<=switch_port_out_data; + rd_ok<='0'; + n_i<=0; + delai:=0; + else + Next_Ex2_state <= ex2_put1; + end if; + end if; + when ex2_put2 => rd_ok<='0'; + n_i<=1; + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + --Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + if unsigned( P_len) > 0 then + + if switch_data_available = '1' and delai=0 then + delai:=1; --une donné lue + P_len_i <= P_len - 1; + Next_Ex2_state <= ex2_put2; + rd_ok<='1'; + data_to_ram_i<=switch_port_out_data; + end if; + if dma_wr_grant='1' and delai=1 then + -- if n=1 then + wr_ok<='1'; + dest_address_i <= dest_address + 1; + delai:=0;--une donnée écrite + -- else + -- dest_address_i <= dest_address ; + -- end if; + --if delai=1 then + --data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch + --end if; + + else + dest_address_i<=dest_address; + wr_ok<='0'; + n_i<=0; + end if; + + Next_Ex2_state <= ex2_put2; + + else + rd_ok<='0'; + + + if dma_wr_grant='1' and n=1 then + + Next_Ex2_state <= ex2_put3; + Wr_ok<='0'; + n_i<=0; + end if; + end if; + + when ex2_put3 => if dma_rd_grant='1' then + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + Next_Ex2_state <= ex2_put4; + n_i<=0; + rd_ok<='1'; + wr_ok<='0'; + end if; + + when ex2_put4 => if n>0 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + if n=0 then + if RGET='1' then + L1: for i in 1 to Max_stack loop -- to Ptr_get normalement + if i<=Ptr_Get then + if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and + waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and + waited_get(i-1)(23 downto 16)=rec_data(2) and + waited_get(i-1)(31 downto 24)=rec_data(3) then + if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then + received_get_i(i-1)<='1'; + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + mode_get_i<='1'; + match_get_i<='1'; + end if; + else + + end if; + end if; + exit L1 when i= Ptr_get; + end loop L1; + end if; + + n_i<=n+1; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=1 then + if match_get='0' then + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + end if; + if dma_rd_grant='1' then + if RGET='1' then --si on est en mode attente d'un Get + RGET_i<='0'; --Supposons tous les Gets reçus ! + test_wcomp:for i in 1 to Max_stack loop --Tous les Get reçus ? + if Ptr_get>=i then + if received_get(i-1)='0' then + RGET_i<='1'; --Non ! + end if; + end if; + exit test_wcomp when i=Ptr_get; + end loop test_wcomp; + + end if; + n_i<=n+1; + rd_ok<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + end if; + elsif n=2 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + tempval(4):='1'; --SET du bit DReceived + if Mode_Get='1' then --si get ack est détecté + tempval(6):=RGET; -- Bit 6 Busy=0 si dernier get reçu !! + mode_get_i<='1'; + end if; + data_to_ram_i<=tempval; + rd_ok<='0'; + wr_ok<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + n_i<=0; + end if; + elsif n=3 then + if dma_wr_grant='1' then + rd_ok<='0'; + wr_ok<='1'; + n_i<=n+1; + end if; + elsif n=4 then + if dma_wr_grant='1' then + rd_ok<='0'; + wr_ok<='1'; + + n_i<=5; + end if; + elsif n=5 then + Next_Ex2_state <= ex2_set_busy; + n_i<=0; + rd_ok<='0'; + wr_ok<='0'; + mode_get_i<='0'; + match_get_i<='0'; + end if; + + + + -- dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction + when ex2_put5 => + Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put + + when ex2_spawn1 => + + if n<2 then + n_e:=n; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); + n_i<=n_e; + Rec_Data_i(2)<=Switch_port_out_data; + elsif n=2 then + Rec_Data_i(3)<=Switch_port_out_data; + Result_i<=Switch_port_out_data; + Data_to_ram_i<=Switch_port_out_data; + n_i<=n+1; + rd_ok<='1'; + elsif n=3 then + if data_to_ram(7 downto 4)=SPAWN_LOAD then + Result_i<=data_to_ram; + wr_ok<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=SPAWN_COMP then + Result_i<=data_to_ram; + wr_ok<='0'; --permet d'activer Init de Ex_4 + + elsif data_to_ram(7 downto 4)=SPAWN_ERR then + Result_i<=data_to_ram; + wr_ok<='0'; --permet d'activer Init de Ex_4 + else + Result_i<=(others=>'0'); + + end if; + n_i<=n+1; + rd_ok<='0'; + elsif n=4 then + wr_ok<='1'; + if AppInitAck='1' then + wr_ok<='0'; + rd_ok<='0'; + n_i<=n+1; + end if; + elsif n=5 then + wr_ok<='0'; + rd_ok<='0'; + n_i<=0; + Next_Ex2_state <=Ex2_Ready; + end if; + when Ex2_Spawn2=> + Next_Ex2_state <=Ex2_Ready; + when ex2_get1 => rd_ok<='0'; --ne pas autoriser la lecture du switch + --ack_state<=next_ack_state; --MAE d'envoie de AR + dma_rd<='1'; + if n=0 then + instr_ack_i<='1'; --activer l'envoie de l'accusé de réception + data_to_write_fifo_i<=to_fifo_ack; + wr_ok<=wr_ack; + if sent_ack='1' then + n_i<=1; + instr_ack_i<='0'; + wr_ok<='0'; + --if switch_data_available='1' then + rd_ok<='0';-- + --P_len<=P_len-1; + --end if; + end if; + + elsif n=1 then + if switch_data_available='1' then + if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo + data_to_write_fifo_i <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put + wr_ok<='1'; + rd_ok<='1'; --autoriser la lecture du crossbar + P_len_i<=P_len-1; + n_i<=n+1; + else + Wr_ok<='0'; + Rd_ok<='0'; + end if; + else + Wr_ok<='0'; + rd_ok<='0'; + end if; + elsif n=2 then + if switch_data_available='1' then + if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo + --data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put + --P_len_i <= P_len-1;--le nombre d'octet qui restent à copier + Next_Ex2_state <= ex2_get2; + wr_ok<='0'; + rd_ok<='0'; --autoriser la lecture du crossbar + n_i<=0; + else + rd_ok<='0'; + wr_ok<='0'; + end if; + else + rd_ok<='0'; + wr_ok<='0'; + end if; + end if; + when ex2_get2 => if P_len>0 then + if fifo_full = '0' and switch_data_available ='1' then + data_to_write_fifo_i <= switch_port_out_data;--la longueur initiale du GET + p_len_i <= P_len - 1; + Next_Ex2_state <= ex2_get2; + wr_ok<='1'; + Rd_ok<='1'; + elsE + + wr_ok<='0'; + Rd_ok<='0'; + END IF; + else + if n=0 then + if fifo_full='0' then + wr_ok<='0';--une impulsion en plus + n_i<=n+1; + Next_Ex2_state <= ex2_get2; + else + wr_ok<='0'; + end if; + + else + Next_Ex2_state <= ex2_get3; + n_i<=0; + wr_ok<='0'; + end if; + rd_ok<='0'; + end if; + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + + --préparer en avance l'adresse de lecture/écriture + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_get3 => wr_ok<='0'; + if dma_rd_grant='1' then -- fin du mpi_get + Next_Ex2_state <= ex2_get4; + n_i<=0; + --activer le bit sending du registre de transfert + else + Next_Ex2_state <= ex2_get3; + end if; + + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_get4 => if n <4 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + if n=0 then + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + elsif n=1 then + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + data_to_ram_i<=Ram_data_out; + elsif n=2 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + --tempval(2):='1'; --mise à 1 du Bit DSending + --tempval(5):='0'; --Mise à 0 du Bit Sent + data_to_ram_i(2)<='1'; --mise à 1 du Bit DSending + data_to_ram_i(5)<='0'; --Mise à 0 du Bit Sent + + data_to_ram_i<=tempval; + rd_ok<='1'; + wr_ok<='0'; + else + rd_ok<='1'; + wr_ok<='0'; + n_i<=0; + end if; + + + elsif n=3 then + if dma_wr_grant = '1' then + n_i<=n+1; + rd_ok<='0'; + wr_ok<='1'; + end if; + elsif n=4 then + if dma_wr_grant = '1' then + n_i<=0; + Next_Ex2_state <= Ex2_Ready; -- fin du mpi_get + else + rd_ok<='0'; + wr_ok<='1'; + --n<=n-1; + end if; + end if; + + + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_Set_Busy => if n=0 then --set busy bit of the instruction + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + n_i<=1; + if Gpost_Set='1' then + if (rec_wpost=gpost) and RGET='0' then + Wbusy_i<='0'; + Gpost_Set_i<='0'; + GComp_i<=(others=>'0'); + rec_wpost_i<=(others=>'0');--reset des messages reçu + else + Wbusy_i<='1'; + end if; + else + + n_i<=2; + end if; + if RGET='1' then + WBusy_i<='1'; + end if; + elsif n=1 then + sb_start<='1'; + sb_bitMask<=x"40";--6e bit à 1 + sb_bitval<=WBusy; + if sb_done='1' then + n_i<=2; + sb_start<='0'; + sb_bitval<='0'; + end if; + elsif n=2 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + end if; + -- execution du barrier + when ex2_barrier1 => if switch_data_available = '1' then + pading_data <= switch_port_out_data; + Next_Ex2_state <= ex2_barrier2; + else + Next_Ex2_state <= ex2_barrier1; + end if; + when ex2_barrier2 => if packet_type = MPI_BARRIER_REACHED then + barrier_counter_i <= barrier_counter + 1; + Next_Ex2_state <= ex2_barrier4; + else + Next_Ex2_state <= ex2_barrier3; + end if; + when ex2_barrier3 => if n < 10 then + n_i<= n + 1; + Next_Ex2_state <= ex2_barrier3; + else + Next_Ex2_state <= Ex2_Ready; + end if; + when ex2_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED + data_to_write_fifo_i <= MPI_BARRIER_COMPLETED & "0000"; + Next_Ex2_state <= ex2_barrier5; + else + Next_Ex2_state <= Ex2_Ready; + end if; + when ex2_barrier5 => if fifo_full = '0' then -- taille du packet MPI_BARRIER_COMPLETED + data_to_write_fifo_i <= "00000011"; + Next_Ex2_state <= ex2_barrier6; + else + Next_Ex2_state <= ex2_barrier5; + end if; + when ex2_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED + data_to_write_fifo_i <= "00000000"; + Next_Ex2_state <= ex2_barrier7; + else + Next_Ex2_state <= ex2_barrier6; + end if; + when ex2_barrier7 => if fifo_full = '0' then + barrier_counter_i <= "0000"; + Next_Ex2_state <= Ex2_Ready; + else + Next_Ex2_state <= ex2_barrier7; + end if; + + when others => Next_Ex2_state <= Ex2_Ready; + end case; + + end process; + + -- sortie de la machine à etat +-- + ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram,Dma_rd,Dma_wr, + switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request, + appInitAck,n,InitReq) + variable transact : std_logic_vector(Word-1 downto 0); + begin +-- code fonctionnel + sb_ram_data_out<=Ram_data_out; --presque toujours cette valeur + case Ex2_state is + when Ex2_Ready => fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='1'; + AppInitReq<='0'; + when fetch_packet_type => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='0'; + AppInitReq<='0'; + + + when decode_packet_type => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when decode_packet_type2 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + when fetch_addresses => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + when ex2_ack1 |ex2_Wsync => + Ready<='0'; + switch_port_out_rd_en<=rd_ok; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when ex2_ack2|Ex2_WCOMP => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= dma_rd; + dma_wr_request <= '0'; + Ram_rd<=rd_ok; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + when ex2_ack3 => + Ready<='0'; + switch_port_out_rd_en<=rd_ok; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when ex2_put1 => fifo_wr_en <= wr_ok; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= dma_wr; + dma_rd_request <= dma_rd; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_put2 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <=rd_ok; + + if rd_ok = '1' then + + Ram_data_in<=switch_port_out_data; + else + Ram_data_in<=data_to_ram; + end if; + Ram_wr<=wr_ok; + Ram_rd<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + when ex2_put3 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + --ne pas corrompre le contenu de la RAM + --Ram_data_in<=data_to_ram; + Ram_wr<='0'; + Ram_rd<='1'; + packet_received <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + + when ex2_put4 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <= '0'; + packet_received <= '1'; + dma_rd_request <= dma_rd; + dma_wr_request <=dma_wr; + Ram_wr<=wr_ok; + Ram_rd<=rd_ok; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_in<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution + + when ex2_put5 => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_in<=data_to_ram; + --Result <=(1=>'1',others=>'0'); --put completed + + when ex2_get1=> fifo_wr_en <= wr_ok; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= dma_rd; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_get2 => + switch_port_out_rd_en <=rd_ok; + fifo_wr_en <= Wr_ok; + Ready<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + + when ex2_get3 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <= '0'; + packet_received <= '1'; + dma_rd_request <= '1'; + dma_wr_request <='0'; + Ram_wr<='0'; + Ram_rd<='1'; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + --Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending + + when ex2_get4 => + Ready<='0'; + barrier_completed <= '0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '1'; + AppInitReq<='0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_in<=data_to_ram; --activer le bit DSending + + + when ex2_barrier1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + Ready<='0'; + AppInitReq<='0'; + + when ex2_barrier2 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + + when ex2_barrier3 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + Ready<='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '1'; + AppInitReq<='0'; + + when ex2_barrier4 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + + when ex2_barrier5 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_barrier6 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_barrier7 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_spawn1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok;--switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ready<='0'; + Ram_data_in<=(others =>'0'); + AppInitReq<=wr_ok; + when ex2_Spawn2 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + + Ram_data_in<=data_to_ram; + + Ram_wr<=wr_ok; + Ram_rd<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + when ex2_init1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok;--switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ready<='0'; + Ram_data_in<=(others =>'0'); + AppInitReq<=InitReq; + + + when ex2_init2 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ram_data_in<=(others =>'0'); + AppInitReq<= not(AppInitAck); + Ready<='0'; + + + when ex2_Set_Busy => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when others => Ready<='1'; -- le module est à nouveau libre + fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='1'; + AppInitReq<='0'; + end case; + + end process; + + ex2_fsm_sync:process(clk,reset) + + begin + + if reset = '1' then + ex2_state <= Ex2_Ready; + ack_state<=ack0; --MAE d'envoie de AR + n<=0; + P_len<=(others=>'0'); + GPost<=(others =>'0'); + else + if rising_edge(clk) then + ex2_state<=next_ex2_state; + ack_state<=next_ack_state; --MAE d'envoie de AR + n<=n_i; + P_len<=P_len_i; + Packet_type<=packet_type_i; + P_G<=P_G_i; + Result1<=Result_i; --juste une copie + dest_address <= dest_address_i; + data_to_write_fifo<=data_to_write_fifo_i; + WBUSY<=WBUSY_i; + RGET<=RGET_i; + InitReq<=InitReq_i; + mode_get<=mode_get_i; + match_get<=match_get_i; + Sent_ack<=sent_ack_i; + Instr_ack<=Instr_ack_i; + Ptr_Get<=Ptr_Get_i; + Rec_Wpost<=Rec_WPost_i; + dest_ack<=dest_ack_i; + barrier_counter<=barrier_counter_i; + GPost<=GPost_i; + GComp<=GComp_i; + Received_get<=Received_get_i; + GPost_set<=GPost_Set_i; + data_to_ram<=data_to_ram_i; + For i in 0 to Max_stack loop + Waited_get(i)<=Waited_get_i(i); + end loop; + For i in 0 to 7 loop + Get_Instr(i)<=Get_instr_i(i); + end loop; + for i in 0 to 3 loop + Rec_Data(i)<=Rec_Data_i(i); + end loop; + end if; + end if; + end process ex2_fsm_sync; +snd_ack:process (ack_state,reset,fifo_full,instr_ack,Dest_Ack,apprank,Packet_type,ram_data_out,dma_rd_grant) +--ce processus est chargé d'emettre l'accusé de réception pour chaque instruction reçu +begin +-- if rising_edge(clk) then + Sent_ack_i<='0'; --pas besoin de le mémoriser + wr_ack<='0'; --valeur par défaut + ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); + if reset='1' then + next_ack_state<=ack0; + to_fifo_ack<=(others=>'1'); + else + next_ack_state<=ack_state; + + case ack_state is + when ack0 =>to_fifo_ack<=(others=>'0'); + Wr_ack<='0'; + if instr_ack='1' then + next_ack_state<=ack_readwait; + to_fifo_ack <= MPI_ACK & Dest_ack; + wr_ack<='0'; + end if; + + sent_ack_i<='0'; + when ack_readwait => to_fifo_ack <= MPI_ACK & Dest_ack; + ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); + --vérifier WinPost attend bien une action de cette source + if dma_rd_grant='1' then + next_ack_state<=ack_checkwait; + end if; + when ack_checkwait => to_fifo_ack <= MPI_ACK & Dest_ack; + ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); + if dma_rd_grant='1' and ram_data_out(conv_integer(dest_ack))='1' then + next_ack_state<=ack1; + elsif dma_rd_grant='0' then + next_ack_state<=ack_readwait; + else + next_ack_state<=ack6; --pas d'acknowledge à envoyer + assert true report "Packet non attendu de cette source !" + severity failure; + end if; + when ack1 => if fifo_full = '0' then -- conversion envoie lack à l'emetteur + -- en empilement dans le fifo + to_fifo_ack <= MPI_ACK & Dest_ack; + next_ack_state <= ack2; + wr_ack<='1'; + else + wr_ack<='0'; + end if; + sent_ack_i<='0'; + to_fifo_ack <= MPI_ACK & Dest_ack; + when ack2 => if fifo_full = '0' then + to_fifo_ack <= "00000100";--la longueur + + next_ack_state <= ack3; + wr_ack<='1'; + else -- + next_ack_state <= ack2; + wr_ack<='0'; + + end if; + to_fifo_ack <= "00000100"; + sent_ack_i<='0'; + when ack3 => if fifo_full = '0' then + to_fifo_ack <= "00000000";-- + next_ack_state <= ack4; + wr_ack<='1'; + else -- + next_ack_state <= ack3; + wr_ack<='0'; + + end if; + to_fifo_ack <= "00000000"; + sent_ack_i<='0'; + when ack4 => if fifo_full = '0' then + to_fifo_ack <=packet_type & apprank ;--l'instruction et le rang de lacquitteur + next_ack_state <= ack5; + wr_ack<='1'; + sent_ack_i<='0'; + else -- + next_ack_state <= ack4; + wr_ack<='0'; + sent_ack_i<='0'; + end if; + to_fifo_ack <=packet_type & apprank ; + when ack5 => if Instr_ack='0' then --dernier pulse + next_ack_state <= ack0; + else + next_ack_state <= ack6; + end if; + wr_ack<='0'; + sent_ack_i<='1'; + to_fifo_ack<=(others=>'1'); + when ack6 => if Instr_ack='0' then + next_ack_state <= ack0; + + end if; + wr_ack<='0'; + sent_ack_i<='1'; + to_fifo_ack<=(others=>'1'); +end case; +end if; +--end if; +end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX2_FSM.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX2_FSM.vhd.bak (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX2_FSM.vhd.bak (revision 138) @@ -0,0 +1,1722 @@ +---------------------------------------------------------------------------------- +-- Company: GRIIA - ETIS - LIP6 +-- Engineer: GAMOM, KIEGAING +-- +-- Create Date: 01:02:10 06/17/2011 +-- Design Name: +-- Module Name: EX2_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- machine a etat qui execute la reception des packet dans le core mpi +-- Dependencies: +--ss +-- Revision: 26/01/2012 +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +library NocLib ; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.Numeric_std.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use Work.Packet_type.ALL; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX2_FSM is + + generic ( + pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur + nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1 + ); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + + Instruction_en : in std_logic; + + dma_wr_grant : in STD_LOGIC; + dma_wr_request : out STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + ram_rd : out std_logic; + ram_wr : out std_logic; + ram_address : out std_logic_vector(ADRLEN-1 downto 0); + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + + fifo_data : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_wr_en : out STD_LOGIC; + fifo_full : in STD_LOGIC; + Rec_Rdy : OUT std_logic; + Rec_Data : buffer Typ_PortIO(0 to 3); + Rec_Ack : IN std_logic; + AppRank : in STD_LOGIC_VECTOR(3 downto 0); + AppSize : in STD_LOGIC_VECTOR(3 downto 0); + packet_received : out STD_LOGIC; + packet_ack : in STD_LOGIC; + barrier_completed : out STD_LOGIC; + Ready : Out std_logic; + AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic ; -- état de la Lib + Result : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module + switch_data_available : in STD_LOGIC; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_out_rd_en : out STD_LOGIC + + + + ); +end EX2_FSM; + +architecture Behavioral of EX2_FSM is +--module pour la lecture des données sur le réseau +CONSTANT MSIZE : natural :=4; --taille de la mémoire tampon pour les messages reçu +component Proto_receiv is + generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_empty,fifo_full : in std_logic; + rcv_start : in std_logic; --début de la réception + rcv_ack :in std_logic; -- acquittement de la réception + rcv_comp : out std_logic; -- fin de la réception + pop : out std_logic:='0'; + fifo_out : in std_logic_vector(Word-1 downto 0); + mem :out memory(0 to sizemem-1)); +end component Proto_receiv; + +COMPONENT SetBit + PORT( + clk : IN std_logic; + reset : IN std_logic; + BitMask : IN std_logic_vector(7 downto 0); + BitVal : IN std_logic; + start : in std_logic; + whole : in std_logic; + done : out std_logic; + dma_wr_grant : IN std_logic; + dma_rd_grant : IN std_logic; + Ram_data_in : out std_logic_vector(7 downto 0); + dma_wr_request : OUT std_logic; + dma_rd_request : OUT std_logic; + ram_rd : OUT std_logic; + ram_wr : OUT std_logic; + ram_address : IN std_logic_vector(15 downto 0); + Ram_data_out : in std_logic_vector(7 downto 0) + ); + End component SetBit; +--constante +constant Max_stack : integer:=7;--Le nombre de GET qui peuvent être empilés +-- définition du type etat de la machine à etat +type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2, +fetch_addresses,ex2_spawn1,ex2_spawn2,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4, +ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack1,ex2_ack2,ex2_ack3, + Ex2_WSync,Ex2_WComp,ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4, + ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2,Ex2_Set_Busy); +type fsm_ack is(ack0,ack_readwait,ack_checkwait,ack1,ack2,ack3,ack4,ack5,ack6); +type mem32 is array (natural range <>) of std_logic_vector (31 downto 0); +signal Next_Ex2_state,ex2_state :fsm_states; +signal ack_state,next_ack_state : fsm_ack; +-- +signal mode_get,match_get:std_logic:='0'; +signal mode_get_i,match_get_i:std_logic:='0'; +-- machine a etat du module +signal packet_type, packet_type_i : std_logic_vector(3 downto 0); +signal P_len_i,P_len : std_logic_vector(Word-1 downto 0); +signal barrier_counter,barrier_counter_i : std_logic_vector(3 downto 0); +signal pading_data,data_to_ram,Data_to_ram_i : std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal n,n_i : natural range 0 to 15; +signal dest_address,dest_address_i,ack_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0'); +signal data_to_write_fifo,data_to_write_fifo_i : std_logic_vector(Word-1 downto 0); +--******************************************* +--signaux pour la fonction SetBit +signal sb_BitMask : std_logic_vector(7 downto 0):=(others=>'0'); +signal sb_BitVal,sb_start,sb_done : std_logic:='0'; +signal sb_whole : std_logic:='0'; --écrire le mot entier +signal sb_Ram_data_in : std_logic_vector(7 downto 0); +signal sb_dma_wr_request : std_logic; +signal sb_dma_rd_request : std_logic; +signal sb_ram_rd : std_logic; +signal sb_ram_wr : std_logic; +signal sb_ram_address : std_logic_vector(15 downto 0):=(others=>'0'); +signal sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0'); +-- deuxième module pour set busy bit +signal Set_Wbusy : std_logic:='0'; --choix du Mux +signal GPost_Set,Gpost_Set_i : std_logic:='0'; --indique l'arrivée de Win_Compl + +--********************************************* +signal Ex2_on : std_logic:='0'; +signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; +signal sent_ack, sent_ack_i,wr_ack,instr_ack,Instr_ack_i:std_logic:='0'; --signaux pour la gesion de l'acquittement +signal dest_ack,dest_ack_i:std_logic_vector(3 downto 0) :=(others=>'0'); +signal to_fifo_ack :std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal Result_i,result1 : STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); +--signaux pour l'untilisation du composant de réception +signal rfifo_empty,rfifo_full:std_logic; +signal rcv_start,rcv_comp,rcv_ack:std_logic; +signal rpop:std_logic; +signal initreq,initreq_i:std_logic:='0'; --Requete d'initialisation +--signal mem:memory(0 to Msize-1)); +--jusqu'à 16 Get peuvent être attendus! +signal Wcomp : std_logic:='0'; --indique que tous les transferts sont terminés +signal WStart,WPost,WBUSY, WBUSY_i,RGET,RGET_i: std_logic:='0'; -- +signal Rec_WPost,Rec_WPost_i,GComp,GComp_i, GPost_i,GPost: std_logic_vector(Max_Stack downto 0):=(others=>'0'); +signal Waited_Get,Waited_Get_i : mem32(0 to Max_stack); +Signal Rec_Data_i : Typ_PortIO(0 to 3); +signal Get_Instr,Get_instr_i,Put_instr,Put_instr_i :memory(0 to 8); +signal Put_Id : std_logic_vector(31 downto 0):=(others=>'0'); +signal P_G,P_G_i: natural range 0 to 3:=0; --Msg Ack : 1 -> Put, 2-->Get +signal Ptr_Get,Ptr_Get_i : natural range 0 to Max_stack:=0; +signal Received_get,Received_get_i : std_logic_vector(Max_stack downto 0):=(others=>'0');--sera remis à 0 lorsque Wstart/WPost est reçu +begin + +ram_address <= ack_address when instr_ack='1' else dest_address; +--fifo_data <= data_to_write_fifo; +Result<=Result1; +p_instr_fifo:process(ack_state,data_to_write_fifo_i,wr_ack,to_fifo_ack,instr_ack) +begin + if instr_ack='1' then + fifo_data<=to_fifo_ack; +else + fifo_data<=data_to_write_fifo_i; +end if; +end process p_instr_fifo; + + + +R0:proto_receiv generic map (sizemem =>4) + port map ( + clk=>clk, + reset=>reset, + rcv_start=>rcv_start, + rcv_comp=>rcv_comp, + rcv_ack=>rcv_ack, + fifo_empty=>rfifo_empty, + fifo_full=>rfifo_full, + fifo_out=>switch_port_out_data, + pop=>rpop, + mem=>open + + ); +--envoie de l'acquittement +setbit1:SetBit + PORT MAP ( + clk =>clk, + reset =>reset, + BitMask =>sb_bitMask, + BitVal =>sb_bitval, + dma_wr_grant =>dma_wr_grant, + dma_rd_grant =>dma_rd_grant, + Ram_data_in => sb_Ram_data_in, + dma_wr_request =>sb_dma_wr_request, + dma_rd_request =>sb_dma_rd_request, + ram_rd =>sb_ram_rd, + ram_wr =>sb_ram_wr, + ram_address =>dest_address, + Ram_data_out =>sb_ram_data_out, + Start =>sb_start, + whole=>sb_whole, + done =>sb_done + ); + +-- processus de transistion entre les etats +ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized, + switch_data_available,switch_port_out_data,sb_ram_data_in,Data_to_Ram,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len, + sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy,Ptr_Get,Get_Instr,P_G,Waited_get,Received_get,rget,GPost,GPost_Set,packet_type,barrier_counter, + dest_ack,rec_wpost,Gcomp,rec_data,mode_get,match_get,Instr_ack,result1,data_to_write_fifo) +variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée +variable tempval : std_logic_vector(Word-1 downto 0); +variable n_e,i:natural range 0 to 15 :=0; + +--=================================================================- +procedure read_nocdat_fsm(sdata_avail: std_logic; +signal rd,wr:out std_logic; +signal Plen_i : in std_logic_vector(Word-1 downto 0); +signal Plen_o : out std_logic_vector(Word-1 downto 0); +variable n:out natural range 0 to 15;signal n_e:in natural range 0 to 15) is +--lit la suite des données qui sont dans le NoC et identifie le paramètre important +begin +if n_e<3 then + wr<='0'; + if sdata_avail='1' then + n:=n_e+1; + rd<='1'; + plen_o <=plen_i-1; + else + rd<='0'; + end if; + --result_i<=(others=>'0'); + elsif n_e=3 then + if sdata_avail='1' then + n:=n_e+1; + rd<='0'; + --P_len <=P_len_i -1; + --data_to_ram<=sportdout; + --Result_i<=sport_out_data; + else + rd<='0'; + end if; + end if; +end procedure; + +begin + + Next_Ex2_state <= Ex2_state; + Ex2_on<='0'; + sb_whole<='0'; + sb_start<='0'; --valeur par défaut + sb_bitmask<=x"FF"; + sb_bitval<='1'; + dma_rd<='0'; + dma_wr<='0'; + rd_ok<='0'; + wr_ok<='0'; + barrier_counter_i <= barrier_counter; + GPost_Set_i<=GPost_Set; + Rec_WPost_i<=Rec_WPost; + GPost_i<=GPost; + P_G_i<=P_G; + RGET_i<=RGET; + WBUSY_i<=WBUSY; + Result_i<=Result1; + Ptr_get_i<=Ptr_get; + mode_get_i<=mode_get; + data_to_write_fifo_i<=data_to_write_fifo; + match_get_i<=match_get; + GComp_i<=GComp; + Instr_ack_i<=Instr_ack; + received_get_i<=received_get; + mode_get_i<=mode_get; + InitReq_i<=InitReq; + match_get_i<=match_get; + Data_to_ram_i<=Data_to_ram; + dest_address_i<=dest_address; + for i in 0 to Max_stack loop + Waited_get_i(i)<=Waited_get(i); + end loop; + For i in 0 to 7 loop + Get_Instr_i(i)<=Get_instr(i); + end loop; + Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non + n_i<=n; --valeur par défaut de n_i + P_len_i<=P_len; + for i in 0 to 3 loop + Rec_Data_i(i)<=Rec_Data(i); + Packet_type_i<=Packet_type; + dest_ack_i<=dest_ack; + end loop; + case ex2_state is + when Ex2_ready => if Instruction_en='1' and switch_data_available='1' then + Next_Ex2_state <= fetch_packet_type; + end if; + rd_ok<='0';wr_ok<='0'; + when fetch_packet_type => if switch_data_available ='1' and Instruction_en='1' then --and initialized ='1' + Next_Ex2_state <= decode_packet_type; + packet_type_i<=switch_port_out_data(7 downto 4); + Dest_ack_i<=switch_port_out_data(3 downto 0); + Rec_Data_i(0)<=switch_port_out_data; --récupérer la première donnée reçue ! + rd_ok<='1'; + else + --Next_Ex2_state <= Ex2_Ready; + rd_ok<='0'; + end if; + n_i<=0; + when decode_packet_type => rd_ok<='0'; + if switch_data_available ='0' then + Next_Ex2_state <= decode_packet_type; + else + rd_ok<='1'; + Rec_Data_i(1)<=switch_port_out_data-2; + if packet_type = MPI_PUT then + P_len_i <= switch_port_out_data - 2; + n_i<=0; + + Next_Ex2_state <= decode_packet_type2; + elsif packet_type = MPI_GET then + P_len_i <=switch_port_out_data-2; + Next_Ex2_state <= decode_packet_type2; + elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then + P_len_i <= switch_port_out_data; + n_i<=0; + Next_Ex2_state <= ex2_barrier1; + elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then + n_i<=0; + wr_ok<='0'; + --rd_ok<='1'; + P_len_i <= switch_port_out_data-2; + Rec_Data_i(1)<=switch_port_out_data; + Next_Ex2_state <= ex2_init1; + elsif packet_type = MPI_ACK then + n_i<=0; + wr_ok<='0'; + rd_ok<='0'; + P_len_i <= switch_port_out_data-2; + Next_Ex2_state <= ex2_ack1; + elsif packet_type = MPI_WIN_SYNC then + n_i<=0; + wr_ok<='0'; + rd_ok<='0'; + P_len_i <= switch_port_out_data-2; + Next_Ex2_state <= ex2_Wsync; + elsif packet_type = MPI_SPAWN then + Next_Ex2_state <= ex2_spawn1; + wr_ok<='0'; + rd_ok<='0'; + else + Next_Ex2_state <= decode_packet_type; + rd_ok<='0'; + end if; + end if; + when decode_packet_type2 => if packet_type = MPI_PUT then + Next_Ex2_state <= fetch_addresses; + else + Next_Ex2_state <= ex2_get1; + end if; + when fetch_addresses => if n=0 then + if switch_data_available = '1' then + dest_address_i(15 downto 8) <= switch_port_out_data; + Rec_data_i(2)<=switch_port_out_data; + n_i <= n + 1; + rd_ok<='1'; + else + rd_ok<='0'; + end if; + elsif n=1 then + if switch_data_available = '1' then + dest_address_i(Word-1 downto 0) <= switch_port_out_data; + Rec_data_i(3)<=switch_port_out_data; + P_len_i <= P_len - 2; + Next_Ex2_state <= ex2_put1; + n_i<=0; + rd_ok<='1'; + else + rd_ok<='0'; + Next_Ex2_state <= fetch_addresses; + end if; + end if; + when ex2_ack1 => rd_ok<='0'; + if n<2 then --réception de l'acquittement. + n_e:=n; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); + n_i<=n_e; + elsif n=2 then + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + + data_to_ram_i<=switch_port_out_data; + Result_i<=switch_port_out_data; + end if; + + elsif n=3 then + n_i<=n+1;P_G_i<=0; + if data_to_ram(7 downto 4)=MPI_PUT then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr,16)); + wr_ok<='1'; + P_G_i<=1; --put ou get + P_len_i<=x"06"; --longueur de l'entête à parcourir + elsif data_to_ram(7 downto 4)=MPI_GET then + Result_i<=data_to_ram; + wr_ok<='1'; -- + P_G_i<=2; --put get + P_len_i<=x"06";--taille de l'instruction en mémoire + dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr,16)); + elsif data_to_ram(7 downto 4)=MPI_SPAWN then + Result_i<=data_to_ram; + wr_ok<='1'; -- + dest_address_i<=std_logic_vector(to_unsigned(Core_Spawn_adr+7,16)); + elsif data_to_ram(7 downto 4)=MPI_INIT then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Core_Init_adr+7,16)); + wr_ok<='1'; -- + -- + else + Result_i<="00000000"; + wr_ok<='0'; -- + n_i<=n; --code inconnu ! + end if; + elsif n=4 then + if P_G=1 or P_G=2 then + Next_ex2_state<=ex2_ack2; + else + Next_ex2_state<=ex2_ack3; + end if; + n_i<=0; + end if; + + when Ex2_ack2 =>if unsigned(p_len)>0 then + If Dma_rd_grant='1' then + if n=0 then + n_i<=n+1; --cycle d'attente pour la RAM + elsif n=1 then + dest_address_i <= dest_address+1; + n_i<=2; + elsif n>=2 then + + --creer un délai sur ces signaux par rapport à src_adress + + n_i<=n+1; + rd_ok<='1'; +-- if n>1 then + dest_address_i <= dest_address+1; + p_len_i <= p_len - 1; + --end if; + Get_Instr_i(n-2)<=Ram_data_out; --deux cycles de retard + Next_ex2_state <= ex2_ack2; + end if; + end if; + dma_rd<='1'; + rd_ok<='1'; + else + if P_G=1 then + dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16)); + else + dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16)); + Waited_get_i(ptr_get)(7 downto 0)<=Get_instr(0); --id + Waited_get_i(ptr_get)(15 downto 8)<=Get_instr(1); --longueur + Waited_get_i(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas + Waited_get_i(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut + RGET_i<='1'; + + Ptr_Get_i<=Ptr_Get+1; --prochain Get à traiter + end if; + Next_ex2_state <= ex2_ack3; + n_i<=0; --suite du process ack + rd_ok<='0'; + dma_rd<='0'; + end if; + +when ex2_ack3 => if n=0 then --set acknowlege bit of the instruction + sb_start<='1'; + sb_bitMask<=x"20";--cinquième bit à un + sb_bitval<='1'; + sb_whole<='0';--Modifier un seul bit ! + if sb_done='1' then + n_i<=1; + sb_start<='0'; + sb_bitval<='0'; + dest_address_i<=dest_address+1; + end if; + + elsif n=1 then + sb_start<='1'; + sb_bitMask<=Rec_Data(2); + sb_bitval<='1'; + sb_whole<='1'; + if sb_done='1' then + n_i<=n+1; + sb_start<='0'; + sb_bitval<='0'; + sb_whole<='0'; + end if; + + elsif n=2 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + end if; + + when ex2_Wsync => rd_ok<='0'; + if n<2 then --réception de la synchronisation. + n_e:=n; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); + n_i<=n_e; + elsif n=2 then + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + + data_to_ram_i<=switch_port_out_data; + Result_i<=switch_port_out_data; + end if; + + elsif n=3 then + n_i<=n+1;P_G_i<=0; + if data_to_ram(7 downto 4)=SYNC_WSTART then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); + wr_ok<='1'; + P_G_i<=1; --put ou get + P_len_i<=x"06"; --longueur de l'entête à parcourir + elsif data_to_ram(7 downto 4)=SYNC_WPOST then + Result_i<=data_to_ram; + wr_ok<='1'; -- + P_G_i<=2; --put get + P_len_i<=x"06";--taille de l'instruction en mémoire + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); + elsif data_to_ram(7 downto 4)=SYNC_WWAIT then + Result_i<=data_to_ram; + wr_ok<='1'; -- + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+7,16)); + elsif data_to_ram(7 downto 4)=SYNC_WCOMP then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); + wr_ok<='1'; -- + Next_Ex2_State<=Ex2_WCOMP; + n_i<=0; + else + Result_i<="00000000"; + wr_ok<='0'; -- + n_i<=n; --code inconnu ! + end if; + + end if; + when Ex2_Wcomp => dma_rd<='1'; + rd_ok<='1'; + + if n=0 then + n_i<=n+1; --cycle d'attente pour la RAM + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + GComp_i(i)<='1'; + elsif n=1 then + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); + If Dma_rd_grant='1' then + n_i<=2; + end if; + elsif n=2 then + If Dma_rd_grant='1' then + --creer un délai sur ces signaux par rapport à dest_adress + n_i<=n+1; + rd_ok<='1'; + dest_address_i <= dest_address+1; + GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard + + else + n_i<=1; + end if; + elsif n=3 then + If Dma_rd_grant='1' then + --GPost_i(15 downto 8)<=Ram_data_out; --Uncomment if needed + n_i<=n+1; + rd_ok<='1'; + dma_rd<='1'; + end if; + elsif n=4 then + --GPost_i(15 downto 8)<=Ram_data_out; --Uncomment if needed + + rd_ok<='1'; + dma_rd<='1'; + n_i<=n+1; + elsif n=5 then + rd_ok<='0'; + dma_rd<='0'; + n_i<=0; + If GPost=GComp then --le même nombre de post que de COmpleted ? + GPost_Set_i<='1'; + end if; + + Next_ex2_state <= ex2_set_busy; + end if; + + + when ex2_init1 => if n<2 then -- execution du mpi Init + wr_ok<='0'; + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + P_len_i <=P_len-1; + Rec_Data_i(n+2)<=switch_port_out_data; + data_to_ram_i<=switch_port_out_data; + Result_i<=switch_port_out_data; + else + rd_ok<='0'; + n_i<=n; + end if; + result_i<=(others=>'0'); + elsif n=2 then + n_i<=n+1; + rd_ok<='0'; + + elsif n=3 then + rd_ok<='0'; -- normalement plus rien à lire + n_i<=n+1; + if Initialized='1' then + if data_to_ram(7 downto 4)=INIT_SEEKMAIN then + Result_i<=data_to_ram; + InitReq_i<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=INIT_STAT then + Result_i<=data_to_ram; + InitReq_i<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=INIT_REGISTER then + Result_i<=data_to_ram; + InitReq_i<='0'; --permet d'activer Init de Ex_4 + report "Mise à jour des données d'initialisation"; + Next_Ex2_state<=ex2_ready; + n_i<=0; + elsif data_to_ram(7 downto 4)=INIT_SPAWN then + Result_i<=data_to_ram; + InitReq_i<='1'; --permet d'activer Init de Ex_4 + -- il faut mettre à jour l'état de Spawn + else + Result_i<="00000000"; + InitReq_i<='0'; --permet d'activer Init de Ex_4 + end if; + end if; + elsif n=4 then + n_i<=n+1; + elsif n=5 then + if p_len=0 then + Next_Ex2_state<=ex2_init2; + rd_ok<='0'; + else + p_len_i <=p_len -1; + rd_ok<='1'; --vider le tampon de lecture pour ce paquet ! + end if; + + end if; + when ex2_init2=> if n=5 then + if AppInitAck='1' then + n_i<=n+1; + InitReq_i<='0'; + Result_i<="00000001"; -- cette valeur permet d'acquitter la fonction Init + end if; + elsif n=6 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + InitReq_i<='0'; + end if; + + when ex2_put1 => rd_ok<='0'; --ne pas autoriser la lecture du switch + wr_ok<='0'; + dma_rd<='1'; + if n=0 then + if RGET='1' then + Lp: for i in 1 to Max_stack loop -- to Ptr_get normalement + if i<=Ptr_Get then + if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and + waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and + waited_get(i-1)(23 downto 16)=rec_data(2) and + waited_get(i-1)(31 downto 24)=rec_data(3) then + if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then + + match_get_i<='1'; + end if; + else + + end if; + end if; + exit Lp when i= Ptr_get; + end loop Lp; + end if; + + n_i<=1; + elsif n=1 then + if match_get='1' then + n_i<=3; --ne pas envoyer ack dans ce cas + report "GET Détecté ACK pas envoyé dans Ex2 du HCL n°" & image(pid); + else + n_i<=2; + end if; + elsif n=2 then + instr_ack_i<='1'; --activer l'envoie de l'accusé de réception + data_to_write_fifo_i<=to_fifo_ack; + wr_ok<=wr_ack; + if sent_ack='1' then + n_i<=2; + instr_ack_i<='0'; + dma_wr<='1'; + end if; + + elsif n=3 then + dma_wr<='1'; + if dma_wr_grant = '1' then + Next_Ex2_state <= ex2_put2; + data_to_ram_i<=switch_port_out_data; + rd_ok<='0'; + n_i<=0; + delai:=0; + else + Next_Ex2_state <= ex2_put1; + end if; + end if; + when ex2_put2 => rd_ok<='0'; + n_i<=1; + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + --Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + if unsigned( P_len) > 0 then + + if switch_data_available = '1' and delai=0 then + delai:=1; --une donné lue + P_len_i <= P_len - 1; + Next_Ex2_state <= ex2_put2; + rd_ok<='1'; + data_to_ram_i<=switch_port_out_data; + end if; + if dma_wr_grant='1' and delai=1 then + -- if n=1 then + wr_ok<='1'; + dest_address_i <= dest_address + 1; + delai:=0;--une donnée écrite + -- else + -- dest_address_i <= dest_address ; + -- end if; + --if delai=1 then + --data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch + --end if; + + else + dest_address_i<=dest_address; + wr_ok<='0'; + n_i<=0; + end if; + + Next_Ex2_state <= ex2_put2; + + else + rd_ok<='0'; + + + if dma_wr_grant='1' and n=1 then + + Next_Ex2_state <= ex2_put3; + Wr_ok<='0'; + n_i<=0; + end if; + end if; + + when ex2_put3 => if dma_rd_grant='1' then + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + Next_Ex2_state <= ex2_put4; + n_i<=0; + rd_ok<='1'; + wr_ok<='0'; + end if; + + when ex2_put4 => if n>0 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + if n=0 then + if RGET='1' then + L1: for i in 1 to Max_stack loop -- to Ptr_get normalement + if i<=Ptr_Get then + if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and + waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and + waited_get(i-1)(23 downto 16)=rec_data(2) and + waited_get(i-1)(31 downto 24)=rec_data(3) then + if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then + received_get_i(i-1)<='1'; + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + mode_get_i<='1'; + match_get_i<='1'; + end if; + else + + end if; + end if; + exit L1 when i= Ptr_get; + end loop L1; + end if; + + n_i<=n+1; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=1 then + if match_get='0' then + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + end if; + if dma_rd_grant='1' then + if RGET='1' then --si on est en mode attente d'un Get + RGET_i<='0'; --Supposons tous les Gets reçus ! + test_wcomp:for i in 1 to Max_stack loop --Tous les Get reçus ? + if Ptr_get>=i then + if received_get(i-1)='0' then + RGET_i<='1'; --Non ! + end if; + end if; + exit test_wcomp when i=Ptr_get; + end loop test_wcomp; + + end if; + n_i<=n+1; + rd_ok<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + end if; + elsif n=2 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + tempval(4):='1'; --SET du bit DReceived + if Mode_Get='1' then --si get ack est détecté + tempval(6):=RGET; -- Bit 6 Busy=0 si dernier get reçu !! + mode_get_i<='1'; + end if; + data_to_ram_i<=tempval; + rd_ok<='0'; + wr_ok<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + n_i<=0; + end if; + elsif n=3 then + if dma_wr_grant='1' then + rd_ok<='0'; + wr_ok<='1'; + n_i<=n+1; + end if; + elsif n=4 then + if dma_wr_grant='1' then + rd_ok<='0'; + wr_ok<='1'; + + n_i<=5; + end if; + elsif n=5 then + Next_Ex2_state <= ex2_set_busy; + n_i<=0; + rd_ok<='0'; + wr_ok<='0'; + mode_get_i<='0'; + match_get_i<='0'; + end if; + + + + -- dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction + when ex2_put5 => + Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put + + when ex2_spawn1 => + + if n<2 then + n_e:=n; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); + n_i<=n_e; + Rec_Data_i(2)<=Switch_port_out_data; + elsif n=2 then + Rec_Data_i(3)<=Switch_port_out_data; + Result_i<=Switch_port_out_data; + Data_to_ram_i<=Switch_port_out_data; + n_i<=n+1; + rd_ok<='1'; + elsif n=3 then + if data_to_ram(7 downto 4)=SPAWN_LOAD then + Result_i<=data_to_ram; + wr_ok<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=SPAWN_COMP then + Result_i<=data_to_ram; + wr_ok<='0'; --permet d'activer Init de Ex_4 + + elsif data_to_ram(7 downto 4)=SPAWN_ERR then + Result_i<=data_to_ram; + wr_ok<='0'; --permet d'activer Init de Ex_4 + else + Result_i<=(others=>'0'); + + end if; + n_i<=n+1; + rd_ok<='0'; + elsif n=4 then + wr_ok<='1'; + if AppInitAck='1' then + wr_ok<='0'; + rd_ok<='0'; + n_i<=n+1; + end if; + elsif n=5 then + wr_ok<='0'; + rd_ok<='0'; + n_i<=0; + Next_Ex2_state <=Ex2_Ready; + end if; + when Ex2_Spawn2=> + Next_Ex2_state <=Ex2_Ready; + when ex2_get1 => rd_ok<='0'; --ne pas autoriser la lecture du switch + --ack_state<=next_ack_state; --MAE d'envoie de AR + dma_rd<='1'; + if n=0 then + instr_ack_i<='1'; --activer l'envoie de l'accusé de réception + data_to_write_fifo_i<=to_fifo_ack; + wr_ok<=wr_ack; + if sent_ack='1' then + n_i<=1; + instr_ack_i<='0'; + wr_ok<='0'; + --if switch_data_available='1' then + rd_ok<='0';-- + --P_len<=P_len-1; + --end if; + end if; + + elsif n=1 then + if switch_data_available='1' then + if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo + data_to_write_fifo_i <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put + wr_ok<='1'; + rd_ok<='1'; --autoriser la lecture du crossbar + P_len_i<=P_len-1; + n_i<=n+1; + else + Wr_ok<='0'; + Rd_ok<='0'; + end if; + else + Wr_ok<='0'; + rd_ok<='0'; + end if; + elsif n=2 then + if switch_data_available='1' then + if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo + --data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put + --P_len_i <= P_len-1;--le nombre d'octet qui restent à copier + Next_Ex2_state <= ex2_get2; + wr_ok<='0'; + rd_ok<='0'; --autoriser la lecture du crossbar + n_i<=0; + else + rd_ok<='0'; + wr_ok<='0'; + end if; + else + rd_ok<='0'; + wr_ok<='0'; + end if; + end if; + when ex2_get2 => if P_len>0 then + if fifo_full = '0' and switch_data_available ='1' then + data_to_write_fifo_i <= switch_port_out_data;--la longueur initiale du GET + p_len_i <= P_len - 1; + Next_Ex2_state <= ex2_get2; + wr_ok<='1'; + Rd_ok<='1'; + elsE + + wr_ok<='0'; + Rd_ok<='0'; + END IF; + else + if n=0 then + if fifo_full='0' then + wr_ok<='0';--une impulsion en plus + n_i<=n+1; + Next_Ex2_state <= ex2_get2; + else + wr_ok<='0'; + end if; + + else + Next_Ex2_state <= ex2_get3; + n_i<=0; + wr_ok<='0'; + end if; + rd_ok<='0'; + end if; + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + + --préparer en avance l'adresse de lecture/écriture + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_get3 => wr_ok<='0'; + if dma_rd_grant='1' then -- fin du mpi_get + Next_Ex2_state <= ex2_get4; + n_i<=0; + --activer le bit sending du registre de transfert + else + Next_Ex2_state <= ex2_get3; + end if; + + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_get4 => if n <4 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + if n=0 then + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + elsif n=1 then + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + data_to_ram_i<=Ram_data_out; + elsif n=2 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + --tempval(2):='1'; --mise à 1 du Bit DSending + --tempval(5):='0'; --Mise à 0 du Bit Sent + data_to_ram_i(2)<='1'; --mise à 1 du Bit DSending + data_to_ram_i(5)<='0'; --Mise à 0 du Bit Sent + + data_to_ram_i<=tempval; + rd_ok<='1'; + wr_ok<='0'; + else + rd_ok<='1'; + wr_ok<='0'; + n_i<=0; + end if; + + + elsif n=3 then + if dma_wr_grant = '1' then + n_i<=n+1; + rd_ok<='0'; + wr_ok<='1'; + end if; + elsif n=4 then + if dma_wr_grant = '1' then + n_i<=0; + Next_Ex2_state <= Ex2_Ready; -- fin du mpi_get + else + rd_ok<='0'; + wr_ok<='1'; + --n<=n-1; + end if; + end if; + + + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_Set_Busy => if n=0 then --set busy bit of the instruction + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + n_i<=1; + if Gpost_Set='1' then + if (rec_wpost=gpost) and RGET='0' then + Wbusy_i<='0'; + Gpost_Set_i<='0'; + GComp_i<=(others=>'0'); + rec_wpost_i<=(others=>'0');--reset des messages reçu + else + Wbusy_i<='1'; + end if; + else + + n_i<=2; + end if; + if RGET='1' then + WBusy_i<='1'; + end if; + elsif n=1 then + sb_start<='1'; + sb_bitMask<=x"40";--6e bit à 1 + sb_bitval<=WBusy; + if sb_done='1' then + n_i<=2; + sb_start<='0'; + sb_bitval<='0'; + end if; + elsif n=2 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + end if; + -- execution du barrier + when ex2_barrier1 => if switch_data_available = '1' then + pading_data <= switch_port_out_data; + Next_Ex2_state <= ex2_barrier2; + else + Next_Ex2_state <= ex2_barrier1; + end if; + when ex2_barrier2 => if packet_type = MPI_BARRIER_REACHED then + barrier_counter_i <= barrier_counter + 1; + Next_Ex2_state <= ex2_barrier4; + else + Next_Ex2_state <= ex2_barrier3; + end if; + when ex2_barrier3 => if n < 10 then + n_i<= n + 1; + Next_Ex2_state <= ex2_barrier3; + else + Next_Ex2_state <= Ex2_Ready; + end if; + when ex2_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED + data_to_write_fifo_i <= MPI_BARRIER_COMPLETED & "0000"; + Next_Ex2_state <= ex2_barrier5; + else + Next_Ex2_state <= Ex2_Ready; + end if; + when ex2_barrier5 => if fifo_full = '0' then -- taille du packet MPI_BARRIER_COMPLETED + data_to_write_fifo_i <= "00000011"; + Next_Ex2_state <= ex2_barrier6; + else + Next_Ex2_state <= ex2_barrier5; + end if; + when ex2_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED + data_to_write_fifo_i <= "00000000"; + Next_Ex2_state <= ex2_barrier7; + else + Next_Ex2_state <= ex2_barrier6; + end if; + when ex2_barrier7 => if fifo_full = '0' then + barrier_counter_i <= "0000"; + Next_Ex2_state <= Ex2_Ready; + else + Next_Ex2_state <= ex2_barrier7; + end if; + + when others => Next_Ex2_state <= Ex2_Ready; + end case; + + end process; + + -- sortie de la machine à etat +-- + ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram,Dma_rd,Dma_wr, + switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request, + appInitAck,n,InitReq) + variable transact : std_logic_vector(Word-1 downto 0); + begin +-- code fonctionnel + sb_ram_data_out<=Ram_data_out; --presque toujours cette valeur + case Ex2_state is + when Ex2_Ready => fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='1'; + AppInitReq<='0'; + when fetch_packet_type => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='0'; + AppInitReq<='0'; + + + when decode_packet_type => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when decode_packet_type2 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + when fetch_addresses => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + when ex2_ack1 |ex2_Wsync => + Ready<='0'; + switch_port_out_rd_en<=rd_ok; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when ex2_ack2|Ex2_WCOMP => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= dma_rd; + dma_wr_request <= '0'; + Ram_rd<=rd_ok; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + when ex2_ack3 => + Ready<='0'; + switch_port_out_rd_en<=rd_ok; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when ex2_put1 => fifo_wr_en <= wr_ok; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= dma_wr; + dma_rd_request <= dma_rd; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_put2 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <=rd_ok; + + if rd_ok = '1' then + + Ram_data_in<=switch_port_out_data; + else + Ram_data_in<=data_to_ram; + end if; + Ram_wr<=wr_ok; + Ram_rd<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + when ex2_put3 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + --ne pas corrompre le contenu de la RAM + --Ram_data_in<=data_to_ram; + Ram_wr<='0'; + Ram_rd<='1'; + packet_received <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + + when ex2_put4 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <= '0'; + packet_received <= '1'; + dma_rd_request <= dma_rd; + dma_wr_request <=dma_wr; + Ram_wr<=wr_ok; + Ram_rd<=rd_ok; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_in<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution + + when ex2_put5 => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_in<=data_to_ram; + --Result <=(1=>'1',others=>'0'); --put completed + + when ex2_get1=> fifo_wr_en <= wr_ok; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= dma_rd; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_get2 => + switch_port_out_rd_en <=rd_ok; + fifo_wr_en <= Wr_ok; + Ready<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + + when ex2_get3 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <= '0'; + packet_received <= '1'; + dma_rd_request <= '1'; + dma_wr_request <='0'; + Ram_wr<='0'; + Ram_rd<='1'; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + --Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending + + when ex2_get4 => + Ready<='0'; + barrier_completed <= '0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '1'; + AppInitReq<='0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_in<=data_to_ram; --activer le bit DSending + + + when ex2_barrier1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + Ready<='0'; + AppInitReq<='0'; + + when ex2_barrier2 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + + when ex2_barrier3 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + Ready<='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '1'; + AppInitReq<='0'; + + when ex2_barrier4 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + + when ex2_barrier5 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_barrier6 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_barrier7 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_spawn1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok;--switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ready<='0'; + Ram_data_in<=(others =>'0'); + AppInitReq<=wr_ok; + when ex2_Spawn2 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + + Ram_data_in<=data_to_ram; + + Ram_wr<=wr_ok; + Ram_rd<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + when ex2_init1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok;--switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ready<='0'; + Ram_data_in<=(others =>'0'); + AppInitReq<=InitReq; + + + when ex2_init2 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ram_data_in<=(others =>'0'); + AppInitReq<= not(AppInitAck); + Ready<='0'; + + + when ex2_Set_Busy => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when others => Ready<='1'; -- le module est à nouveau libre + fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='1'; + AppInitReq<='0'; + end case; + + end process; + + ex2_fsm_sync:process(clk,reset) + + begin + + if reset = '1' then + ex2_state <= Ex2_Ready; + ack_state<=ack0; --MAE d'envoie de AR + n<=0; + P_len<=(others=>'0'); + GPost<=(others =>'0'); + else + if rising_edge(clk) then + ex2_state<=next_ex2_state; + ack_state<=next_ack_state; --MAE d'envoie de AR + n<=n_i; + P_len<=P_len_i; + Packet_type<=packet_type_i; + P_G<=P_G_i; + Result1<=Result_i; --juste une copie + dest_address <= dest_address_i; + data_to_write_fifo<=data_to_write_fifo_i; + WBUSY<=WBUSY_i; + RGET<=RGET_i; + InitReq<=InitReq_i; + mode_get<=mode_get_i; + match_get<=match_get_i; + Sent_ack<=sent_ack_i; + Instr_ack<=Instr_ack_i; + Ptr_Get<=Ptr_Get_i; + Rec_Wpost<=Rec_WPost_i; + dest_ack<=dest_ack_i; + barrier_counter<=barrier_counter_i; + GPost<=GPost_i; + GComp<=GComp_i; + Received_get<=Received_get_i; + GPost_set<=GPost_Set_i; + data_to_ram<=data_to_ram_i; + For i in 0 to Max_stack loop + Waited_get(i)<=Waited_get_i(i); + end loop; + For i in 0 to 7 loop + Get_Instr(i)<=Get_instr_i(i); + end loop; + for i in 0 to 3 loop + Rec_Data(i)<=Rec_Data_i(i); + end loop; + end if; + end if; + end process ex2_fsm_sync; +snd_ack:process (ack_state,reset,fifo_full,instr_ack,Dest_Ack,apprank,Packet_type,ram_data_out,dma_rd_grant) +--ce processus est chargé d'emettre l'accusé de réception pour chaque instruction reçu +begin +-- if rising_edge(clk) then + Sent_ack_i<='0'; --pas besoin de le mémoriser + wr_ack<='0'; --valeur par défaut + ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); + if reset='1' then + next_ack_state<=ack0; + to_fifo_ack<=(others=>'1'); + else + next_ack_state<=ack_state; + + case ack_state is + when ack0 =>to_fifo_ack<=(others=>'0'); + Wr_ack<='0'; + if instr_ack='1' then + next_ack_state<=ack_readwait; + to_fifo_ack <= MPI_ACK & Dest_ack; + wr_ack<='0'; + end if; + + sent_ack_i<='0'; + when ack_readwait => to_fifo_ack <= MPI_ACK & Dest_ack; + ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); + --vérifier WinPost attend bien une action de cette source + if dma_rd_grant='1' then + next_ack_state<=ack_checkwait; + end if; + when ack_checkwait => to_fifo_ack <= MPI_ACK & Dest_ack; + ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); + if dma_rd_grant='1' and ram_data_out(conv_integer(dest_ack))='1' then + next_ack_state<=ack1; + elsif dma_rd_grant='0' then + next_ack_state<=ack_readwait; + else + next_ack_state<=ack6; --pas d'acknowledge à envoyer + assert true report "Packet non attendu de cette source !" + severity failure; + end if; + when ack1 => if fifo_full = '0' then -- conversion envoie lack à l'emetteur + -- en empilement dans le fifo + to_fifo_ack <= MPI_ACK & Dest_ack; + next_ack_state <= ack2; + wr_ack<='1'; + else + wr_ack<='0'; + end if; + sent_ack_i<='0'; + to_fifo_ack <= MPI_ACK & Dest_ack; + when ack2 => if fifo_full = '0' then + to_fifo_ack <= "00000100";--la longueur + + next_ack_state <= ack3; + wr_ack<='1'; + else -- + next_ack_state <= ack2; + wr_ack<='0'; + + end if; + to_fifo_ack <= "00000100"; + sent_ack_i<='0'; + when ack3 => if fifo_full = '0' then + to_fifo_ack <= "00000000";-- + next_ack_state <= ack4; + wr_ack<='1'; + else -- + next_ack_state <= ack3; + wr_ack<='0'; + + end if; + to_fifo_ack <= "00000000"; + sent_ack_i<='0'; + when ack4 => if fifo_full = '0' then + to_fifo_ack <=packet_type & apprank ;--l'instruction et le rang de lacquitteur + next_ack_state <= ack5; + wr_ack<='1'; + sent_ack_i<='0'; + else -- + next_ack_state <= ack4; + wr_ack<='0'; + sent_ack_i<='0'; + end if; + to_fifo_ack <=packet_type & apprank ; + when ack5 => if Instr_ack='0' then --dernier pulse + next_ack_state <= ack0; + else + next_ack_state <= ack6; + end if; + wr_ack<='0'; + sent_ack_i<='1'; + to_fifo_ack<=(others=>'1'); + when ack6 => if Instr_ack='0' then + next_ack_state <= ack0; + + end if; + wr_ack<='0'; + sent_ack_i<='1'; + to_fifo_ack<=(others=>'1'); +end case; +end if; +--end if; +end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX2_FSM_1.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX2_FSM_1.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX2_FSM_1.vhd (revision 138) @@ -0,0 +1,1604 @@ +---------------------------------------------------------------------------------- +-- Company: GRIIA - ETIS - LIP6 +-- Engineer: GAMOM, KIEGAING +-- +-- Create Date: 01:02:10 06/17/2011 +-- Design Name: +-- Module Name: EX2_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- machine a etat qui execute la reception des packet dans le core mpi +-- Dependencies: +--ss +-- Revision: 26/01/2012 +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +library NocLib ; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.Numeric_std.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use Work.Packet_type.ALL; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX2_FSM is + + generic ( + pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur + nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1 + ); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + + Instruction_en : in std_logic; + + dma_wr_grant : in STD_LOGIC; + dma_wr_request : out STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + ram_rd : out std_logic; + ram_wr : out std_logic; + ram_address : out std_logic_vector(ADRLEN-1 downto 0); + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + + fifo_data : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_wr_en : out STD_LOGIC; + fifo_full : in STD_LOGIC; + Rec_Rdy : OUT std_logic; + Rec_Data : buffer Typ_PortIO(0 to 3); + Rec_Ack : IN std_logic; + AppRank : in STD_LOGIC_VECTOR(3 downto 0); + AppSize : in STD_LOGIC_VECTOR(3 downto 0); + packet_received : out STD_LOGIC; + packet_ack : in STD_LOGIC; + barrier_completed : out STD_LOGIC; + Ready : Out std_logic; + AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic ; -- état de la Lib + Result : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module + switch_data_available : in STD_LOGIC; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_out_rd_en : out STD_LOGIC + + + + ); +end EX2_FSM; + +architecture Behavioral of EX2_FSM is +--module pour la lecture des données sur le réseau +CONSTANT MSIZE : natural :=4; --taille de la mémoire tampon pour les messages reçu +component Proto_receiv is + generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_empty,fifo_full : in std_logic; + rcv_start : in std_logic; --début de la réception + rcv_ack :in std_logic; -- acquittement de la réception + rcv_comp : out std_logic; -- fin de la réception + pop : out std_logic:='0'; + fifo_out : in std_logic_vector(Word-1 downto 0); + mem :out memory(0 to sizemem-1)); +end component Proto_receiv; + +COMPONENT SetBit + PORT( + clk : IN std_logic; + reset : IN std_logic; + BitMask : IN std_logic_vector(7 downto 0); + BitVal : IN std_logic; + start : in std_logic; + whole : in std_logic; + done : out std_logic; + dma_wr_grant : IN std_logic; + dma_rd_grant : IN std_logic; + Ram_data_in : out std_logic_vector(7 downto 0); + dma_wr_request : OUT std_logic; + dma_rd_request : OUT std_logic; + ram_rd : OUT std_logic; + ram_wr : OUT std_logic; + ram_address : IN std_logic_vector(15 downto 0); + Ram_data_out : in std_logic_vector(7 downto 0) + ); + End component SetBit; +-- définition du type etat de la machine à etat +type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2, +fetch_addresses,ex2_spawn1,ex2_spawn2,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4, +ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack1,ex2_ack2,ex2_ack3, + Ex2_WSync,Ex2_WComp,ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4, + ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2,Ex2_Set_Busy); +type fsm_ack is(ack0,ack1,ack2,ack3,ack4,ack5,ack6); +type mem32 is array (natural range <>) of std_logic_vector (31 downto 0); +signal Next_Ex2_state,ex2_state :fsm_states; +signal ack_state,next_ack_state : fsm_ack; +-- machine a etat du module +signal packet_type : std_logic_vector(3 downto 0); +signal P_len_i,P_len : std_logic_vector(Word-1 downto 0); +signal barrier_counter : std_logic_vector(3 downto 0); +signal pading_data,data_to_ram : std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal n,n_i : natural range 0 to 15; +signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0'); +signal data_to_write_fifo : std_logic_vector(Word-1 downto 0); +--******************************************* +--signaux pour la fonction SetBit +signal sb_BitMask : std_logic_vector(7 downto 0):=(others=>'0'); +signal sb_BitVal,sb_start,sb_done : std_logic:='0'; +signal sb_whole : std_logic:='0'; --écrire le mot entier +signal sb_Ram_data_in : std_logic_vector(7 downto 0); +signal sb_dma_wr_request : std_logic; +signal sb_dma_rd_request : std_logic; +signal sb_ram_rd : std_logic; +signal sb_ram_wr : std_logic; +signal sb_ram_address : std_logic_vector(15 downto 0):=(others=>'0'); +signal sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0'); +-- deuxième module pour set busy bit +signal Set_Wbusy : std_logic:='0'; --choix du Mux +signal GPost_Set,Gpost_Set_i : std_logic:='0'; --indique l'arrivée de Win_Compl + +--********************************************* +signal Ex2_on : std_logic:='0'; +signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; +signal sent_ack, sent_ack_i,wr_ack,instr_ack,Instr_ack_i:std_logic:='0'; --signaux pour la gesion de l'acquittement +signal dest_ack:std_logic_vector(3 downto 0) :=(others=>'0'); +signal to_fifo_ack :std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal Result_i : STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); +--signaux pour l'untilisation du composant de réception +signal rfifo_empty,rfifo_full:std_logic; +signal rcv_start,rcv_comp,rcv_ack:std_logic; +signal rpop:std_logic; +--signal mem:memory(0 to Msize-1)); +--jusqu'à 16 Get peuvent être attendus! +signal Wcomp : std_logic:='0'; --indique que tous les transferts sont terminés +signal WStart,WPost,WBUSY ,RGET: std_logic:='0'; -- +signal Rec_WPost,Rec_WPost_i,GComp,GComp_i, GPost_i,GPost: std_logic_vector(15 downto 0):=(others=>'0'); +signal Waited_Get,Waited_Get_i : mem32(0 to 15); +Signal Rec_Data_i : Typ_PortIO(0 to 3); +signal Get_Instr,Put_instr :memory(0 to 8); +signal Put_Id : std_logic_vector(31 downto 0):=(others=>'0'); +signal P_G: natural range 0 to 3:=0; --Msg Ack : 1 -> Put, 2-->Get +signal Ptr_Get,Ptr_Get_i : natural range 0 to 15:=0; +signal Received_get : std_logic_vector(15 downto 0):=(others=>'0');--sera remis à 0 lorsque Wstart/WPost est reçu +begin +ram_address <= dest_address; +--fifo_data <= data_to_write_fifo; +Result<=Result_i; +p_instr_fifo:process(ack_state,data_to_write_fifo,wr_ack,to_fifo_ack,instr_ack) +begin + if instr_ack='1' then + fifo_data<=to_fifo_ack; +else + fifo_data<=data_to_write_fifo; +end if; +end process p_instr_fifo; + + + +R0:proto_receiv generic map (sizemem =>4) + port map ( + clk=>clk, + reset=>reset, + rcv_start=>rcv_start, + rcv_comp=>rcv_comp, + rcv_ack=>rcv_ack, + fifo_empty=>rfifo_empty, + fifo_full=>rfifo_full, + fifo_out=>switch_port_out_data, + pop=>rpop, + mem=>open + + ); +--envoie de l'acquittement +setbit1:SetBit + PORT MAP ( + clk =>clk, + reset =>reset, + BitMask =>sb_bitMask, + BitVal =>sb_bitval, + dma_wr_grant =>dma_wr_grant, + dma_rd_grant =>dma_rd_grant, + Ram_data_in => sb_Ram_data_in, + dma_wr_request =>sb_dma_wr_request, + dma_rd_request =>sb_dma_rd_request, + ram_rd =>sb_ram_rd, + ram_wr =>sb_ram_wr, + ram_address =>dest_address, + Ram_data_out =>sb_ram_data_out, + Start =>sb_start, + whole=>sb_whole, + done =>sb_done + ); + +-- processus de transistion entre les etats +ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized, + switch_data_available,switch_port_out_data,sb_ram_data_in,Data_to_Ram,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len, + sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy,Ptr_Get,Get_Instr,P_G,Waited_get,Received_get,rget,GPost,GPost_Set,packet_type,barrier_counter, + dest_ack,rec_wpost,Gcomp,rec_data) +variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée +variable tempval : std_logic_vector(Word-1 downto 0); +variable n_e,i:natural range 0 to 15 :=0; +variable mode_get,match_get:std_logic:='0'; +--=================================================================- +procedure read_nocdat_fsm(sdata_avail: std_logic; +signal rd,wr:out std_logic; +signal Plen : inout std_logic_vector(Word-1 downto 0); +variable n:out natural range 0 to 15;signal n_e:in natural range 0 to 15) is +--lit la suite des données qui sont dans le NoC et identifie le paramètre important +begin +if n_e<3 then + wr<='0'; + if sdata_avail='1' then + n:=n_e+1; + rd<='1'; + plen <=plen-1; + else + rd<='0'; + end if; + --result_i<=(others=>'0'); + elsif n_e=3 then + if sdata_avail='1' then + n:=n_e+1; + rd<='0'; + --P_len <=P_len_i -1; + --data_to_ram<=sportdout; + --Result_i<=sport_out_data; + else + rd<='0'; + end if; + end if; +end procedure; + +begin + + Next_Ex2_state <= Ex2_state; + Ex2_on<='0'; + barrier_counter <= "0000"; + GPost_Set_i<=GPost_Set; + Rec_WPost_i<=Rec_WPost; + GPost_i<=GPost; + GComp_i<=GComp; + dest_address_i<=dest_address; + for i in 0 to 15 loop + Waited_get_i(i)<=Waited_get(i); + end loop; + + Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non + n_i<=n; --valeur par défaut de n_i + P_len_i<=P_len; + for i in 0 to 3 loop + Rec_Data_i(i)<=Rec_Data(i); + end loop; + case ex2_state is + when Ex2_ready => if Instruction_en='1' and switch_data_available='1' then + Next_Ex2_state <= fetch_packet_type; + end if; + rd_ok<='0';wr_ok<='0'; + when fetch_packet_type => if switch_data_available ='1' and Instruction_en='1' then --and initialized ='1' + Next_Ex2_state <= decode_packet_type; + packet_type<=switch_port_out_data(7 downto 4); + Dest_ack<=switch_port_out_data(3 downto 0); + Rec_Data_i(0)<=switch_port_out_data; --récupérer la première donnée reçue ! + rd_ok<='1'; + else + --Next_Ex2_state <= Ex2_Ready; + rd_ok<='0'; + end if; + n_i<=0; + when decode_packet_type => rd_ok<='0'; + if switch_data_available ='0' then + Next_Ex2_state <= decode_packet_type; + else + rd_ok<='1'; + Rec_Data_i(1)<=switch_port_out_data-2; + if packet_type = MPI_PUT then + P_len_i <= switch_port_out_data - 2; + n_i<=0; + + Next_Ex2_state <= decode_packet_type2; + elsif packet_type = MPI_GET then + P_len_i <=switch_port_out_data-2; + Next_Ex2_state <= decode_packet_type2; + elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then + P_len_i <= switch_port_out_data; + n_i<=0; + Next_Ex2_state <= ex2_barrier1; + elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then + n_i<=0; + wr_ok<='0'; + --rd_ok<='1'; + P_len_i <= switch_port_out_data-2; + Rec_Data_i(1)<=switch_port_out_data; + Next_Ex2_state <= ex2_init1; + elsif packet_type = MPI_ACK then + n_i<=0; + wr_ok<='0'; + rd_ok<='0'; + P_len_i <= switch_port_out_data-2; + Next_Ex2_state <= ex2_ack1; + elsif packet_type = MPI_WIN_SYNC then + n_i<=0; + wr_ok<='0'; + rd_ok<='0'; + P_len_i <= switch_port_out_data-2; + Next_Ex2_state <= ex2_Wsync; + elsif packet_type = MPI_SPAWN then + Next_Ex2_state <= ex2_spawn1; + wr_ok<='0'; + rd_ok<='0'; + else + Next_Ex2_state <= decode_packet_type; + rd_ok<='0'; + end if; + end if; + when decode_packet_type2 => if packet_type = MPI_PUT then + Next_Ex2_state <= fetch_addresses; + else + Next_Ex2_state <= ex2_get1; + end if; + when fetch_addresses => if n=0 then + if switch_data_available = '1' then + dest_address_i(15 downto 8) <= switch_port_out_data; + Rec_data_i(2)<=switch_port_out_data; + n_i <= n + 1; + rd_ok<='1'; + else + rd_ok<='0'; + end if; + elsif n=1 then + if switch_data_available = '1' then + dest_address_i(Word-1 downto 0) <= switch_port_out_data; + Rec_data_i(3)<=switch_port_out_data; + P_len_i <= P_len - 2; + Next_Ex2_state <= ex2_put1; + n_i<=0; + rd_ok<='1'; + else + rd_ok<='0'; + Next_Ex2_state <= fetch_addresses; + end if; + end if; + when Ex2_ack2 =>if unsigned(p_len)>0 then + If Dma_rd_grant='1' then + if n=0 then + n_i<=n+1; --cycle d'attente pour la RAM + elsif n=1 then + dest_address_i <= dest_address+1; + n_i<=2; + elsif n>=2 then + + --creer un délai sur ces signaux par rapport à src_adress + + n_i<=n+1; + rd_ok<='1'; +-- if n>1 then + dest_address_i <= dest_address+1; + p_len_i <= p_len - 1; + --end if; + Get_Instr(n-2)<=Ram_data_out; --deux cycles de retard + Next_ex2_state <= ex2_ack2; + end if; + end if; + dma_rd<='1'; + rd_ok<='1'; + else + if P_G=1 then + dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16)); + else + dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16)); + Waited_get_i(ptr_get)(7 downto 0)<=Get_instr(0); --id + Waited_get_i(ptr_get)(15 downto 8)<=Get_instr(1); --longueur + Waited_get_i(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas + Waited_get_i(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut + RGET<='1'; + + Ptr_Get_i<=Ptr_Get+1; --prochain Get à traiter + end if; + Next_ex2_state <= ex2_ack3; + n_i<=0; --suite du process ack + rd_ok<='0'; + dma_rd<='0'; + end if; + when ex2_ack1 => rd_ok<='0'; + if n<2 then --réception de l'acquittement. + n_e:=n_i; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n); + n_i<=n_e; + elsif n=2 then + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + + data_to_ram<=switch_port_out_data; + Result_i<=switch_port_out_data; + end if; + + elsif n=3 then + n_i<=n+1;P_G<=0; + if data_to_ram(7 downto 4)=MPI_PUT then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr,16)); + wr_ok<='1'; + P_G<=1; --put ou get + P_len_i<=x"06"; --longueur de l'entête à parcourir + elsif data_to_ram(7 downto 4)=MPI_GET then + Result_i<=data_to_ram; + wr_ok<='1'; -- + P_G<=2; --put get + P_len_i<=x"06";--taille de l'instruction en mémoire + dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr,16)); + elsif data_to_ram(7 downto 4)=MPI_SPAWN then + Result_i<=data_to_ram; + wr_ok<='1'; -- + dest_address_i<=std_logic_vector(to_unsigned(Core_Spawn_adr+7,16)); + elsif data_to_ram(7 downto 4)=MPI_INIT then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Core_Init_adr+7,16)); + wr_ok<='1'; -- + -- + else + Result_i<="00000000"; + wr_ok<='0'; -- + n_i<=n; --code inconnu ! + end if; + elsif n=4 then + if P_G=1 or P_G=2 then + Next_ex2_state<=ex2_ack2; + else + Next_ex2_state<=ex2_ack3; + end if; + n_i<=0; + end if; + +when ex2_ack3 => if n=0 then --set acknowlege bit of the instruction + sb_start<='1'; + sb_bitMask<=x"20";--cinquième bit à un + sb_bitval<='1'; + sb_whole<='0';--Modifier un seul bit ! + if sb_done='1' then + n_i<=1; + sb_start<='0'; + sb_bitval<='0'; + dest_address_i<=dest_address+1; + end if; + + elsif n=1 then + sb_start<='1'; + sb_bitMask<=Rec_Data(2); + sb_bitval<='1'; + sb_whole<='1'; + if sb_done='1' then + n_i<=n+1; + sb_start<='0'; + sb_bitval<='0'; + sb_whole<='0'; + end if; + + elsif n=2 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + end if; + + when ex2_Wsync => rd_ok<='0'; + if n<2 then --réception de la synchronisation. + n_e:=n; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n); + n_i<=n_e; + elsif n=2 then + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + + data_to_ram<=switch_port_out_data; + Result_i<=switch_port_out_data; + end if; + + elsif n=3 then + n_i<=n+1;P_G<=0; + if data_to_ram(7 downto 4)=SYNC_WSTART then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); + wr_ok<='1'; + P_G<=1; --put ou get + P_len_i<=x"06"; --longueur de l'entête à parcourir + elsif data_to_ram(7 downto 4)=SYNC_WPOST then + Result_i<=data_to_ram; + wr_ok<='1'; -- + P_G<=2; --put get + P_len_i<=x"06";--taille de l'instruction en mémoire + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); + elsif data_to_ram(7 downto 4)=SYNC_WWAIT then + Result_i<=data_to_ram; + wr_ok<='1'; -- + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+7,16)); + elsif data_to_ram(7 downto 4)=SYNC_WCOMP then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); + wr_ok<='1'; -- + Next_Ex2_State<=Ex2_WCOMP; + n_i<=0; + else + Result_i<="00000000"; + wr_ok<='0'; -- + n_i<=n; --code inconnu ! + end if; + + end if; + when Ex2_Wcomp => dma_rd<='1'; + rd_ok<='1'; + + if n=0 then + n_i<=n+1; --cycle d'attente pour la RAM + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + GComp_i(i)<='1'; + elsif n=1 then + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); + If Dma_rd_grant='1' then + n_i<=2; + end if; + elsif n=2 then + If Dma_rd_grant='1' then + --creer un délai sur ces signaux par rapport à dest_adress + n_i<=n+1; + rd_ok<='1'; + dest_address_i <= dest_address+1; + GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard + + else + n_i<=1; + end if; + elsif n=3 then + If Dma_rd_grant='1' then + GPost_i(15 downto 8)<=Ram_data_out; + n_i<=n+1; + rd_ok<='1'; + dma_rd<='1'; + end if; + elsif n=4 then + GPost_i(15 downto 8)<=Ram_data_out; + rd_ok<='1'; + dma_rd<='1'; + n_i<=n+1; + elsif n=5 then + rd_ok<='0'; + dma_rd<='0'; + n_i<=0; + If GPost=GComp then --le même nombre de post que de COmpleted ? + GPost_Set_i<='1'; + end if; + + Next_ex2_state <= ex2_set_busy; + end if; + + + when ex2_init1 => if n<2 then -- execution du mpi Init + wr_ok<='0'; + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + P_len_i <=P_len-1; + Rec_Data_i(n+2)<=switch_port_out_data; + data_to_ram<=switch_port_out_data; + Result_i<=switch_port_out_data; + else + rd_ok<='0'; + n_i<=n; + end if; + result_i<=(others=>'0'); + elsif n=2 then + n_i<=n+1; + rd_ok<='0'; + + elsif n=3 then + rd_ok<='0'; -- normalement plus rien à lire + n_i<=n+1; + if Initialized='1' then + if data_to_ram(7 downto 4)=INIT_SEEKMAIN then + Result_i<=data_to_ram; + wr_ok<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=INIT_STAT then + Result_i<=data_to_ram; + wr_ok<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=INIT_REGISTER then + Result_i<=data_to_ram; + wr_ok<='0'; --permet d'activer Init de Ex_4 + report "Mise à jour des données d'initialisation"; + Next_Ex2_state<=ex2_ready; + n_i<=0; + elsif data_to_ram(7 downto 4)=INIT_SPAWN then + Result_i<=data_to_ram; + wr_ok<='1'; --permet d'activer Init de Ex_4 + -- il faut mettre à jour l'état de Spawn + else + Result_i<="00000000"; + wr_ok<='0'; --permet d'activer Init de Ex_4 + end if; + end if; + elsif n=4 then + n_i<=n+1; + elsif n=5 then + if p_len=0 then + Next_Ex2_state<=ex2_init2; + rd_ok<='0'; + else + p_len_i <=p_len -1; + rd_ok<='1'; --vider le tampon de lecture pour ce paquet ! + end if; + + end if; + when ex2_init2=> if n=5 then + if AppInitAck='1' then + n_i<=n+1; + Result_i<="00000001"; -- cette valeur permet d'acquitter la fonction Init + end if; + elsif n=6 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + end if; + + when ex2_put1 => rd_ok<='0'; --ne pas autoriser la lecture du switch + wr_ok<='0'; + if n=0 then + instr_ack_i<='1'; --activer l'envoie de l'accusé de réception + data_to_write_fifo<=to_fifo_ack; + wr_ok<=wr_ack; + if sent_ack='1' then + n_i<=1; + instr_ack_i<='0'; + end if; + + elsif n=1 then + if dma_wr_grant = '1' then + Next_Ex2_state <= ex2_put2; + data_to_ram<=switch_port_out_data; + rd_ok<='0'; + n_i<=0; + delai:=0; + else + Next_Ex2_state <= ex2_put1; + end if; + end if; + when ex2_put2 => rd_ok<='0'; + n_i<=1; + i:=to_integer(unsigned(Rec_Data_i(0)(3 downto 0))); + --Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + if unsigned( P_len) > 0 then + + if switch_data_available = '1' and delai=0 then + delai:=1; --une donné lue + P_len_i <= P_len - 1; + Next_Ex2_state <= ex2_put2; + rd_ok<='1'; + data_to_ram<=switch_port_out_data; + end if; + if dma_wr_grant='1' and delai=1 then + -- if n=1 then + wr_ok<='1'; + dest_address_i <= dest_address + 1; + delai:=0;--une donnée écrite + -- else + -- dest_address_i <= dest_address ; + -- end if; + --if delai=1 then + --data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch + --end if; + + else + dest_address_i<=dest_address; + wr_ok<='0'; + n_i<=0; + end if; + + Next_Ex2_state <= ex2_put2; + + else + rd_ok<='0'; + + + if dma_wr_grant='1' and n=1 then + + Next_Ex2_state <= ex2_put3; + Wr_ok<='0'; + n_i<=0; + end if; + end if; + + when ex2_put3 => if dma_rd_grant='1' then + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + Next_Ex2_state <= ex2_put4; + n_i<=0; + rd_ok<='1'; + wr_ok<='0'; + end if; + + when ex2_put4 => if n<=4 and n>0 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + if n=0 then + if RGET='1' then + L1: for i in 1 to 15 loop -- to Ptr_get normalement + if i<=Ptr_Get then + if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and + waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and + waited_get(i-1)(23 downto 16)=rec_data(2) and + waited_get(i-1)(31 downto 24)=rec_data(3) then + if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then + received_get(i-1)<='1'; + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + mode_get:='1'; + match_get:='1'; + end if; + else + + end if; + end if; + exit L1 when i= Ptr_get; + end loop L1; + end if; + + n_i<=n+1; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=1 then + if match_get='0' then + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + end if; + if dma_rd_grant='1' then + if RGET='1' then --si on est en mode attente d'un Get + RGET<='0'; --Supposons tous les Gets reçus ! + test_wcomp:for i in 1 to 15 loop --Tous les Get reçus ? + if Ptr_get>=i then + if received_get(i-1)='0' then + RGET<='1'; --Non ! + end if; + end if; + exit test_wcomp when i=Ptr_get; + end loop test_wcomp; + + end if; + n_i<=n+1; + else + rd_ok<='1'; + wr_ok<='0'; + end if; + elsif n=2 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + tempval(4):='1'; --SET du bit DReceived + if Mode_Get='1' then --si get ack est détecté + tempval(6):=RGET; -- Bit 6 Busy=0 si dernier get reçu !! + mode_get:='1'; + end if; + data_to_ram<=tempval; + rd_ok<='0'; + wr_ok<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + n_i<=0; + end if; + elsif n=3 then + if dma_wr_grant='1' then + rd_ok<='0'; + wr_ok<='1'; + n_i<=n+1; + end if; + elsif n=4 then + if dma_wr_grant='1' then + rd_ok<='0'; + wr_ok<='1'; + + n_i<=5; + end if; + elsif n=5 then + Next_Ex2_state <= ex2_set_busy; + n_i<=0; + rd_ok<='0'; + wr_ok<='0'; + mode_get:='0'; + match_get:='0'; + end if; + + + + -- dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction + when ex2_put5 => + Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put + + when ex2_spawn1 => + + if n<2 then + n_e:=n; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n); + n_i<=n_e; + Rec_Data_i(2)<=Switch_port_out_data; + elsif n=2 then + Rec_Data_i(3)<=Switch_port_out_data; + Result_i<=Switch_port_out_data; + Data_to_ram<=Switch_port_out_data; + n_i<=n+1; + rd_ok<='1'; + elsif n=3 then + if data_to_ram(7 downto 4)=SPAWN_LOAD then + Result_i<=data_to_ram; + wr_ok<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=SPAWN_COMP then + Result_i<=data_to_ram; + wr_ok<='0'; --permet d'activer Init de Ex_4 + + elsif data_to_ram(7 downto 4)=SPAWN_ERR then + Result_i<=data_to_ram; + wr_ok<='0'; --permet d'activer Init de Ex_4 + else + Result_i<=(others=>'0'); + + end if; + n_i<=n+1; + rd_ok<='0'; + elsif n=4 then + wr_ok<='1'; + if AppInitAck='1' then + wr_ok<='0'; + rd_ok<='0'; + n_i<=n+1; + end if; + elsif n=5 then + wr_ok<='0'; + rd_ok<='0'; + n_i<=0; + Next_Ex2_state <=Ex2_Ready; + end if; + when Ex2_Spawn2=> + Next_Ex2_state <=Ex2_Ready; + when ex2_get1 => rd_ok<='0'; --ne pas autoriser la lecture du switch + --ack_state<=next_ack_state; --MAE d'envoie de AR + if n=0 then + instr_ack_i<='1'; --activer l'envoie de l'accusé de réception + data_to_write_fifo<=to_fifo_ack; + wr_ok<=wr_ack; + if sent_ack='1' then + n_i<=1; + instr_ack_i<='0'; + wr_ok<='0'; + --if switch_data_available='1' then + rd_ok<='0';-- + --P_len<=P_len-1; + --end if; + end if; + + elsif n=1 then + if switch_data_available='1' then + if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo + data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put + wr_ok<='1'; + rd_ok<='1'; --autoriser la lecture du crossbar + P_len_i<=P_len-1; + n_i<=n+1; + else + Wr_ok<='0'; + Rd_ok<='0'; + end if; + else + Wr_ok<='0'; + rd_ok<='0'; + end if; + elsif n=2 then + if switch_data_available='1' then + if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo + --data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put + --P_len_i <= P_len-1;--le nombre d'octet qui restent à copier + Next_Ex2_state <= ex2_get2; + wr_ok<='0'; + rd_ok<='0'; --autoriser la lecture du crossbar + n_i<=0; + else + rd_ok<='0'; + wr_ok<='0'; + end if; + else + rd_ok<='0'; + wr_ok<='0'; + end if; + end if; + when ex2_get2 => if P_len>0 then + if fifo_full = '0' and switch_data_available ='1' then + data_to_write_fifo <= switch_port_out_data;--la longueur initiale du GET + p_len_i <= P_len - 1; + Next_Ex2_state <= ex2_get2; + wr_ok<='1'; + Rd_ok<='1'; + elsE + + wr_ok<='0'; + Rd_ok<='0'; + END IF; + else + if n=0 then + if fifo_full='0' then + wr_ok<='0';--une impulsion en plus + n_i<=n+1; + Next_Ex2_state <= ex2_get2; + else + wr_ok<='0'; + end if; + + else + Next_Ex2_state <= ex2_get3; + n_i<=0; + wr_ok<='0'; + end if; + rd_ok<='0'; + end if; + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + + --préparer en avance l'adresse de lecture/écriture + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_get3 => wr_ok<='0'; + if dma_rd_grant='1' then -- fin du mpi_get + Next_Ex2_state <= ex2_get4; + n_i<=0; + --activer le bit sending du registre de transfert + else + Next_Ex2_state <= ex2_get3; + end if; + + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_get4 => if n <4 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + if n=0 then + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + elsif n=1 then + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=2 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + tempval(2):='1'; --mise à 1 du Bit DSending + --tempval(5):='0'; --Mise à 0 du Bit Sent + data_to_ram<=tempval; + rd_ok<='1'; + wr_ok<='0'; + else + rd_ok<='1'; + wr_ok<='0'; + n_i<=0; + end if; + + elsif n=3 then + if dma_wr_grant = '1' then + n_i<=n+1; + rd_ok<='0'; + wr_ok<='1'; + end if; + elsif n=4 then + if dma_wr_grant = '1' then + n_i<=0; + Next_Ex2_state <= Ex2_Ready; -- fin du mpi_get + else + rd_ok<='0'; + wr_ok<='1'; + --n<=n-1; + end if; + end if; + + + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_Set_Busy => if n=0 then --set busy bit of the instruction + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + n_i<=1; + if Gpost_Set='1' then + if (rec_wpost=gpost) and RGET='0' then + Wbusy<='0'; + Gpost_Set_i<='0'; + GComp_i<=(others=>'0'); + rec_wpost_i<=(others=>'0');--reset des messages reçu + else + Wbusy<='1'; + end if; + else + + n_i<=2; + end if; + if RGET='1' then + WBusy<='1'; + end if; + elsif n=1 then + sb_start<='1'; + sb_bitMask<=x"40";--6e bit à 1 + sb_bitval<=WBusy; + if sb_done='1' then + n_i<=2; + sb_start<='0'; + sb_bitval<='0'; + end if; + elsif n=2 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + end if; + -- execution du barrier + when ex2_barrier1 => if switch_data_available = '1' then + pading_data <= switch_port_out_data; + Next_Ex2_state <= ex2_barrier2; + else + Next_Ex2_state <= ex2_barrier1; + end if; + when ex2_barrier2 => if packet_type = MPI_BARRIER_REACHED then + barrier_counter <= barrier_counter + 1; + Next_Ex2_state <= ex2_barrier4; + else + Next_Ex2_state <= ex2_barrier3; + end if; + when ex2_barrier3 => if n < 10 then + n_i<= n + 1; + Next_Ex2_state <= ex2_barrier3; + else + Next_Ex2_state <= Ex2_Ready; + end if; + when ex2_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED + data_to_write_fifo <= MPI_BARRIER_COMPLETED & "0000"; + Next_Ex2_state <= ex2_barrier5; + else + Next_Ex2_state <= Ex2_Ready; + end if; + when ex2_barrier5 => if fifo_full = '0' then -- taille du packet MPI_BARRIER_COMPLETED + data_to_write_fifo <= "00000011"; + Next_Ex2_state <= ex2_barrier6; + else + Next_Ex2_state <= ex2_barrier5; + end if; + when ex2_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED + data_to_write_fifo <= "00000000"; + Next_Ex2_state <= ex2_barrier7; + else + Next_Ex2_state <= ex2_barrier6; + end if; + when ex2_barrier7 => if fifo_full = '0' then + barrier_counter <= "0000"; + Next_Ex2_state <= Ex2_Ready; + else + Next_Ex2_state <= ex2_barrier7; + end if; + + when others => Next_Ex2_state <= Ex2_Ready; + end case; + + end process; + + -- sortie de la machine à etat +-- + ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram,Dma_rd,Dma_wr, + switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request, + appInitAck,n) + variable transact : std_logic_vector(Word-1 downto 0); + begin +-- code fonctionnel + case Ex2_state is + when Ex2_Ready => fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='1'; + AppInitReq<='0'; + when fetch_packet_type => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='0'; + AppInitReq<='0'; + + + when decode_packet_type => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when decode_packet_type2 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + when fetch_addresses => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + when ex2_ack1 |ex2_Wsync => + Ready<='0'; + switch_port_out_rd_en<=rd_ok; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when ex2_ack2|Ex2_WCOMP => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= dma_rd; + dma_wr_request <= '0'; + Ram_rd<=rd_ok; + Ram_wr<='0'; + when ex2_ack3 => + Ready<='0'; + switch_port_out_rd_en<=rd_ok; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when ex2_put1 => fifo_wr_en <= wr_ok; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '1'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_put2 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <=rd_ok; + + if rd_ok = '1' then + + Ram_data_in<=switch_port_out_data; + else + Ram_data_in<=data_to_ram; + end if; + Ram_wr<=wr_ok; + Ram_rd<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + when ex2_put3 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + --ne pas corrompre le contenu de la RAM + --Ram_data_in<=data_to_ram; + Ram_wr<='0'; + Ram_rd<='1'; + packet_received <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + + + when ex2_put4 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <= '0'; + packet_received <= '1'; + dma_rd_request <= dma_rd; + dma_wr_request <=dma_wr; + Ram_wr<=wr_ok; + Ram_rd<=rd_ok; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_in<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution + + when ex2_put5 => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_in<=data_to_ram; + --Result <=(1=>'1',others=>'0'); --put completed + + when ex2_get1=> fifo_wr_en <= wr_ok; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_get2 => + switch_port_out_rd_en <=rd_ok; + fifo_wr_en <= Wr_ok; + Ready<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + + when ex2_get3 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <= '0'; + packet_received <= '1'; + dma_rd_request <= '1'; + dma_wr_request <='0'; + Ram_wr<='0'; + Ram_rd<='1'; + AppInitReq<='0'; + barrier_completed <= '0'; + --Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending + + when ex2_get4 => + Ready<='0'; + barrier_completed <= '0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '1'; + AppInitReq<='0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_in<=data_to_ram; --activer le bit DSending + + + when ex2_barrier1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + Ready<='0'; + AppInitReq<='0'; + + when ex2_barrier2 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + + when ex2_barrier3 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + Ready<='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '1'; + AppInitReq<='0'; + + when ex2_barrier4 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + + when ex2_barrier5 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_barrier6 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_barrier7 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_spawn1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok;--switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ready<='0'; + Ram_data_in<=(others =>'0'); + AppInitReq<=wr_ok; + when ex2_Spawn2 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + + Ram_data_in<=data_to_ram; + + Ram_wr<=wr_ok; + Ram_rd<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + when ex2_init1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok;--switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ready<='0'; + Ram_data_in<=(others =>'0'); + AppInitReq<=wr_ok; + + + when ex2_init2 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ram_data_in<=(others =>'0'); + AppInitReq<= not(AppInitAck); + Ready<='0'; + + + when ex2_Set_Busy => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when others => Ready<='1'; -- le module est à nouveau libre + fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='1'; + AppInitReq<='0'; + end case; + + end process; + + ex2_fsm_sync:process(clk,reset) + + begin + + if reset = '1' then + ex2_state <= Ex2_Ready; + ack_state<=ack0; --MAE d'envoie de AR + n<=0; + P_len<=(others=>'0'); + GPost<=(others =>'0'); + else + if rising_edge(clk) then + ex2_state<=next_ex2_state; + ack_state<=next_ack_state; --MAE d'envoie de AR + n<=n_i; + P_len<=P_len_i; + dest_address <= dest_address_i; + Sent_ack<=sent_ack_i; + Instr_ack<=Instr_ack_i; + Ptr_Get<=Ptr_Get_i; + Rec_Wpost<=Rec_WPost_i; + GPost<=GPost_i; + GComp<=GComp_i; + GPost_set<=GPost_Set_i; + For i in 0 to 15 loop + Waited_get(i)<=Waited_get_i(i); + end loop; + for i in 0 to 3 loop + Rec_Data(i)<=Rec_Data_i(i); + end loop; + end if; + end if; + end process ex2_fsm_sync; +snd_ack:process (ack_state,reset,fifo_full,instr_ack,Dest_Ack,Packet_type) +--ce processus est chargé d'emettre l'accusé de réception pour chaque instruction reçu +begin +-- if rising_edge(clk) then + + if reset='1' then + next_ack_state<=ack0; + else + next_ack_state<=ack_state; + case ack_state is + when ack0 =>to_fifo_ack<=(others=>'0'); + Wr_ack<='0'; + if instr_ack='1' then + next_ack_state<=ack1; + to_fifo_ack <= MPI_ACK & Dest_ack; + wr_ack<='0'; + end if; + + sent_ack_i<='0'; + + when ack1 => if fifo_full = '0' then -- conversion envoie lack à l'emetteur + -- en empilement dans le fifo + to_fifo_ack <= MPI_ACK & Dest_ack; + next_ack_state <= ack2; + wr_ack<='1'; + else + wr_ack<='0'; + end if; + sent_ack_i<='0'; + when ack2 => if fifo_full = '0' then + to_fifo_ack <= "00000100";--la longueur + + next_ack_state <= ack3; + wr_ack<='1'; + else -- + next_ack_state <= ack2; + wr_ack<='0'; + + end if; + sent_ack_i<='0'; + when ack3 => if fifo_full = '0' then + to_fifo_ack <= "00000000";-- + next_ack_state <= ack4; + wr_ack<='1'; + else -- + next_ack_state <= ack3; + wr_ack<='0'; + + end if; + sent_ack_i<='0'; + when ack4 => if fifo_full = '0' then + to_fifo_ack <=packet_type & apprank ;--l'instruction et le rang de lacquitteur + next_ack_state <= ack5; + wr_ack<='1'; + sent_ack_i<='0'; + else -- + next_ack_state <= ack4; + wr_ack<='0'; + sent_ack_i<='0'; + end if; + when ack5 => if Instr_ack='0' then --dernier pulse + next_ack_state <= ack0; + else + next_ack_state <= ack6; + end if; + wr_ack<='0'; + sent_ack_i<='1'; + to_fifo_ack<=(others=>'1'); + when ack6 => if Instr_ack='0' then + next_ack_state <= ack0; + + end if; + wr_ack<='0'; + sent_ack_i<='1'; + to_fifo_ack<=(others=>'1'); +end case; +end if; +--end if; +end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX3_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX3_FSM.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX3_FSM.vhd (revision 138) @@ -0,0 +1,75 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM / KIEGAING +-- +-- Create Date: 09:22:58 05/20/2011 +-- Design Name: +-- Module Name: EX3_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- module du core mpi chargé d'exécuter les fonctions mpi_get_size et mpi_get_rank +-- Dependencies: +-- +-- Revision: 23/02/2012 +-- Revision 0.02 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +--package Packet_type +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use Work.Packet_type.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX3_FSM is + generic ( + pid : unsigned(Word-1 downto 0) := "00000001"; -- id du processeur + nprocs : unsigned(Word-1 downto 0):="00000011"-- nombre de processeur du MPSOC + ); + Port ( instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + ResOut : out STD_LOGIC_VECTOR (Word-1 downto 0); + pid_nprocs: out STD_LOGIC_VECTOR (Word-1 downto 0); + clk : in STD_LOGIC; + IsMain: in STD_LOGIC; + reset : in STD_LOGIC); +end EX3_FSM; + + +architecture Behavioral of EX3_FSM is + +signal instruction_signal : std_logic_vector(3 downto 0); +signal rank : unsigned(Word-1 downto 0) := pid; +signal size : unsigned(Word-1 downto 0) := nprocs; +begin +instruction_signal <= instruction(7 downto 4); +ex3_fsm_process : process(clk) +begin + + +if rising_edge(clk) then + if reset ='1' then + ResOut <= (others=>'0'); + else + if instruction_signal = MPI_GET_RANK then + ResOut <= std_logic_vector(rank); + elsif instruction_signal = MPI_GET_SIZE then + ResOut <= std_logic_vector(size); + elsif instruction_signal=MPI_INIT then + if IsMain='1' then --master est associé à la bibliothèque de rang 0 + rank<=rank+1; -- elle est responsable d'affecter de nouveaux rangs + end if; + end if; + end if; +end if; +end process; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX4_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX4_FSM.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX4_FSM.vhd (revision 138) @@ -0,0 +1,1950 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM +-- +-- Create Date: 14:44:36 03/07/2012 +-- Design Name: +-- Module Name: EX4_FSM - Behavioral +-- Project Name: MPI_CORE_COMPONENTS +-- Target Devices: SPARTAN 3E xc3s1200e +-- Tool versions: +-- Description: Ce module renferme les fonctions permettant d'initialiser la +-- bibliothèque matériel MPI +-- Dependencies: +-- +-- Revision: 25/juin/2012 au 24/Octobre/2012 +-- Revision 0.03 - File updated +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; + +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; +Library NocLib; +use NoCLib.CoreTypes.all; +use work.packet_type.all; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX4_FSM is + Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_En : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + ResultOut : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); + Result_En : out STD_LOGIC:='0'; + Ready : out STD_LOGIC; --indique que le module est disponible + NocSize : out STD_LOGIC_VECTOR(3 downto 0); + PortId : out STD_LOGIC_VECTOR(3 downto 0):=(others=>'0'); + AppRank : out STD_LOGIC_VECTOR(3 downto 0):=(others=>'0'); + AppSize : out STD_LOGIC_VECTOR(3 downto 0):=(others=>'0'); + IsMain : out STD_LOGIC; + I_fifo_full :in STD_LOGIC; --instruction fifo + I_fifo_wr_en: out STD_LOGIC;--instruction fifo Write enable + I_fifo_data_in :out STD_LOGIC_vector(Word-1 downto 0); --instruction fifo data + Initialized : out STD_LOGIC; + Snd_Ack : IN std_logic; + Rec_Rdy : IN std_logic; + Rec_Data : IN Typ_PortIO(0 to 3); + Snd_data : OUT Typ_PortIO(0 to 3); + Snd_Start : buffer std_logic; + Rec_Ack : OUT std_logic; + dma_wr_grant : in STD_LOGIC; + dma_wr_request : out STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + ram_rd : out std_logic; + ram_wr : out std_logic; + ram_address : out std_logic_vector(ADRLEN-1 downto 0);--accès au stockage + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + + AppAck : in STD_LOGIC; + AppReq : in STD_LOGIC; + port_in_cmd_en : out STD_LOGIC:='0'; + port_in_wr_en : out STD_LOGIC:='0'; + port_in_empty : in STD_LOGIC; + port_in_full : in STD_LOGIC; + port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'-'); + port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_rd_en : out STD_LOGIC:='0'; + port_out_data_available : in STD_LOGIC); +end EX4_FSM; + +architecture Behavioral of EX4_FSM is + +COMPONENT SetBit + PORT( + clk : IN std_logic; + reset : IN std_logic; + BitNum : IN std_logic_vector(0 to 2); + BitVal : IN std_logic; + dma_wr_grant : IN std_logic; + dma_rd_grant : IN std_logic; + Ram_data_in : IN std_logic_vector(7 downto 0); + + dma_wr_request : OUT std_logic; + dma_rd_request : OUT std_logic; + ram_rd : OUT std_logic; + ram_wr : OUT std_logic; + ram_address : OUT std_logic_vector(15 downto 0); + Ram_data_out : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; +Type Ar_MPIPort_In is array (positive range <>) of Typ_MPIPort_in; +Type Ar_MPIPort_out is array (positive range <>) of Typ_MPIPort_out; + + --MAE pour emission de init + --type init1_type is (init,NocSize,InitToNoc,NextPort,EndBCast); + -- MAE pour affectation des rangs aux différentes librairies MPI + type init2_type is (init,GetPortNum,DecodeData,IsPortZero,SeekMain1,SeekMain2,StoreMain,SetMainFlag,ReadNoc,GetMainReq,StoreRank,NewRank,SendRank,RegRank,SendPeerStat,AskPeerStat,GetPeerStat,SendApp,SpawnApp,SpawnLoad,ErrSpawn,EndInit); + -- MAE pour réception de init depuis le réseau; + type init3_type is (init,GetNocSize,ReadInitHead,StorePort,EndInit); + type typ_send is (s_init,s_head,s_len,s_len2,s_data,s_end); + type typ_receiv is (r_wait,r_dlen,r_drop,r_glen,r_data,r_pulse,r_end); + type typ_cmd is (cmdstart,cmdpost,cmdpostidle,cmdread,cmdlen,cmdglen,cmddata,cmdend,cmdtimeout); + type typ_mem16 is array(natural range <>) of std_logic_vector(15 downto 0);-- + signal etsnd : typ_send; + signal etrec:typ_receiv; --pour la machine à état de réception + signal etcmd :typ_cmd; --pour la machine à état de commande +signal IS_state,next_Is_state : natural range 0 to 3:=0; + +-- signal stInit1, next_stInit1 : init1_type; + signal stInit2, next_stInit2 : init2_type; + --signal stInit3, next_stInit3 : init3_type; + --signaux pour l'interface avec les ports + signal cport_in_wr_en,sport_in_wr_en:std_logic; + signal cport_out_rd_en,rport_out_rd_en:std_logic; + signal rdy:std_logic:='0'; --signal busy/ready + signal tosend,tosend4 :std_logic_vector(Word-1 downto 0); + signal PeerStat,PeerStat_i : std_logic_vector(15 downto 0):=(others=>'0'); --état des autres Lib initialisées + signal SpawnReq,SpawnReq_Q : std_logic_vector(15 downto 0):=(others=>'0'); --état des autres HT qui ont appelés le Spawn + signal Spawn_grp,Spawn_grp_Q :typ_mem16(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); --un max de quatre groupes de fils est prévu + signal Grp_id,grp_id_i :natural range 0 to 3:=0; --id du groupe des HT fils + signal selector : std_logic_vector (2 downto 0); -- pour le MUX des signaux vers le port + --signaux pour les états des MAE + signal NocSizeOk,PortCountFlag : std_logic; + signal PortNumFlag,PortNumFlag_i,EquFlag,EquFlag_i,MainResp: std_logic:='0'; + signal StatAsked,RankAsked,RankSent:std_logic; + signal nextr,nextr_i : natural :=0; + signal RTS_cmd,RTS_dat,RTS_I,CTR,BCast,Send_Ack,DS_Ack,CM_Ack:std_logic:='0'; + signal I_Send_Ack,I_Send_Rdy:std_logic:='0'; + signal Rcv_On,Snd_On,Cmd_On : std_logic:='0'; --status des MAE d'envoie et de réception + signal SpawnOn,SpawnInit :std_logic:='0'; --indique que le Spawn est activé + signal SpawnNbReq,SpawnNbAck,SpawnNBAck_i : natural range 0 to 15 :=0; --compte le nombre de requêtes et le nombre d'acquitement + signal SpawnNbReq_Q : natural range 0 to 15 :=0; --compte le nombre de requêtes et le nombre d'acquitement + signal SpawnCmd0,SpawnCmd1, SpawnCmd2 :std_logic_vector(Word-1 downto 0):=(others=>'0'); + signal SpawnCmd0_Q,SpawnCmd1_Q, SpawnCmd2_Q :std_logic_vector(Word-1 downto 0):=(others=>'0'); + signal SpawnDest :std_logic_vector(3 downto 0); + Signal Ht_Start,Ht_Start_i : natural range 0 to 15:=0; + Signal vPeerStat,vPeerStat_i : std_logic_vector(15 downto 0):=(others=>'0'); + signal IsMain_i,IsMain1,Initialized_i,HCL_init,HCL_Init_i: std_logic:='0'; + signal DS_RDY ,BCast_Rdy,Send_RDY,CM_RDY:std_logic:='0'; + signal ExecTime_out:std_logic; + --signaux de gestion de la RAM + signal Ram_Next_Address : std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_BASE_ADR+CORE_Rank2port_BASE,16)); + signal Ram_NExt_Address_i :std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_BASE_ADR+CORE_Rank2port_BASE,16)); + signal n,n_i:natural range 0 to 15 :=0; + signal n0,n0_i:natural range 0 to 7:=0; + signal DataToRam : std_logic_vector(Word-1 downto 0) ; + signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; + --Signaux des résultats et de l'état + signal PortNum_i,PortNum,MyPort : std_logic_vector(3 downto 0); -- + signal NocMax ,NocMax_i: std_logic_vector(3 downto 0):=(others=>'0'); -- Nombre de ports du réseau -1 ? + signal MyRank : std_logic_vector(3 downto 0) ; --rang du PE + signal AppSize_i,AppSize1:std_logic_vector(3 downto 0) ;--taille de l'application + signal Spawn_done,Spawn_done_i:std_logic:='0'; --indique que le Spawn a été effectué + signal MainPort,MainPort_i : std_logic_vector(3 downto 0) ; --Port de la lib main + signal NextRank,NextRank_i : std_logic_vector(3 downto 0):=(others=>'0'); --utiliser pour gérer les affectations de rangs MPI + signal Data_To_Send,Data_to_send_i : Typ_PortIo(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); -- permet d'empiler les données à envoyer + signal RankToPort :Typ_PortIo(0 to 15);--permet d'associer un port réseau à chaque rang + signal CmdReceived : Typ_PortIO(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); + signal DataReceived : Typ_PortIO(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); + signal Datalen,DataLen_i : natural range 0 to 7:=0; --indique la longueur des données + --other outputs + signal StatAsked_i,RankAsked_i,MainResp_i,RankSent_i,Result_i:std_logic:='0'; + signal snd_start_i:std_logic:='0';--version interne des signaux de sortie + --signal BCast_Rdy_i : std_logic; + signal cdlen,dcount : natural range 0 to 255:=0; --longueur du paquet reçu par le process pcmd + signal timeout,timeout_i : natural range 0 to 4095:=0; + signal PortStat,PortStat_i : std_logic_vector(3 downto 0):=(others=>'0'); + signal PeerPort,PeerPort_i : natural range 0 to 15:=0; -- désigne le port qui emet une requête + signal PeerRTS,PeerRTS_i,PeerCTR:std_logic:='0'; + signal cpt,cpt_peer : natural range 0 to 31:=0; --compteur pour le nombre de HT initialisés + signal clk_cyl,clk_cyl_i : natural range 0 to 15:=0; +begin +--======================================================================================= +--fonctions du module +--======================================================================================= +--======================================================================================= + +-- Inst_SetBit: SetBit PORT MAP( +-- clk => clk, +-- reset => reset , +-- ce => cmd, +-- BitNum => , +-- BitVal => '1', +-- dma_wr_grant => dma_wr_grant , +-- dma_wr_request => dma_wr_request, +-- dma_rd_grant => dma_rd_grant, +-- dma_rd_request => dma_rd_request, +-- ram_rd => ram_rd, +-- ram_wr => ram_wr, +-- ram_address => , +-- Ram_data_in => Ram_data_in, +-- Ram_data_out => Ram_data_out +-- ); + + + -- Gestion de l'initialisation du Core MPI + sync_Init2 : process (clk,reset) + begin + if reset='1' then + stinit2<=init; + StatAsked<='0'; + MyPort<=(others=>'0'); + NextRank<=(others =>'0'); + elsif rising_edge(clk) then + stinit2<=next_stinit2; + IS_State<=Next_IS_State; + n0<=n0_i; + --ajout des autres affectations ici + Ram_Next_Address<=Ram_Next_Address_i; + PortNumFlag<=PortNumFlag_i; + RankAsked<=RankAsked_i; + RankSent<=RankSent_i; + AppRank<=MyRank; + timeout<=timeout_i; + cpt<=cpt_peer; + clk_cyl<=clk_cyl_i; + NextRank<=NextRank_i; + StatAsked<=StatAsked_i; + MainResp<=MainResp_i; + AppSize1<=AppSize_i; + n<=n_i; + Ht_Start<=Ht_Start_i; + Grp_Id<=Grp_Id_i; + vPeerStat<=vPeerStat_i; + SpawnNbAck<=SpawnNbAck_i; + PortStat<=PortStat_i; + EquFlag<=EquFlag_i; + --IsMain1<=IsMain_i; + if ismain_i='1' then + IsMain1<='1'; + + else + IsMain1<=IsMain1; + end if; + if stInit2=DecodeData then + MyPort<=Cmdreceived(2)(3 downto 0); + end if; + + if stInit2=StoreRank and ExecTime_Out='1' then + MyRank<=MyPort; + elsif stInit2=StoreRank then + MyRank<=DataReceived(2)(3 downto 0); + elsif stInit2=SetMainFlag then + MyRank<=MyPort; + end if; + Ready<=Rdy; + snd_start<=snd_start_i; + SpawnNbReq_q<=SpawnNbReq; + SpawnReq_Q<=SpawnReq; + SpawnCmd0_Q<=SpawnCmd0; + SpawnCmd1_Q<=SpawnCmd1; + SpawnCmd2_Q<=SpawnCmd2; + Spawn_grp_q<=Spawn_grp; + PeerRTS<=PeerRTS_i; + PortNum<=PortNum_i; + Spawn_done<=Spawn_done_i; + HCL_init<=Hcl_init_i; + PeerStat<=PeerStat_i; + DataLen<=DataLen_i; + MainPort<=MainPort_i; + Nextr<=NextR_i; + NocMax<=NoCMax_i; + PeerPort<=PeerPort_i; + grp_id<=grp_id_i; + for i in 0 to 3 loop + data_to_send(i)<=data_to_send_i(i); + end loop; + end if; +end process; + +AppSize<=AppSize1; + + Init2_DECODE: process (stinit2,n, CmdReceived, EquFlag, MyPort, DS_RDY, MainResp, DataReceived, + SpawnOn,Ram_Next_Address,PeerRTS,PortSTAT,dma_rd,dma_wr,Send_rdy,I_Send_rdy,rd_ok,wr_ok,Instruction, + MainPort,PeerStat,SpawnCmd0,SpawnCmd1,SpawnCmd2,SpawnInit,BCast_rdy) + variable nextadr : natural :=0;--to_integer(unsigned(Ram_Next_Address)); + variable nport : natural range 0 to 15:=0; + begin + for i in 0 to 3 loop + data_to_send_i(i)<=data_to_send(i); + end loop; + PortNum_i<=PortNum; + PortNumFlag_i<=PortNumFlag; + PortID<=MyPort; + PeerPort_i<=PeerPort; + NocMax_i<=NoCMax; + NextRank_i<=NextRank; + MainPort_i<=MainPort; + PeerStat_i<=PeerStat; + EquFlag_i<=EquFlag; + RankAsked_i<=RankAsked; + NextR_i<=NextR; + Ram_Next_Address_i<=Ram_Next_Address; + Ram_address<=(others=>'1'); + Ram_data_in<=(others=>'1'); + dma_rd_request<='0'; + dma_wr_request<='0'; + Initialized_i<='0'; + rdy<='0'; + ram_rd<='0'; + ram_wr<='0'; + I_Send_ack<='0'; + IsMain_i<='0'; + send_ack<='0'; + DataLen_i<=0; + Case stInit2 is + When Init => + RTS_cmd<='0'; + --RTS_dat<='0'; + RTS_I<='0'; + BCast<='0'; + Result_En<='0'; + Initialized_i<='0'; + CM_Ack <='0'; + CTR<='0' ; + DS_ACK<='0'; + Send_Ack<='0'; + ram_wr<='0'; + rdy<='1';--le module est disponible + ResultOut<=(others=>'0'); + if PortNumFlag='1' and IsMain1='1' then + PortNum_i<=Instruction(3 downto 0); + else + PortNum_i<=(others=>'-'); + end if; + EquFlag_i<='0'; + RankAsked_i<='0'; + dma_wr_request<='0'; + dma_rd_request<='0'; + When GetPortNum => + RTS_cmd<='1'; + RTS_I<='0'; + + Result_En<='0'; + Initialized_i<='0'; + BCast<='0'; --réalise un envoie non collectif + CM_Ack<='0'; -- les données sont maintenant attendues + CTR<='0' ; + data_to_send_i(0)<=X"0" & GETPORTID; + DS_ACK<='0'; + Send_Ack<='0'; + ram_wr<='0'; + rdy<='0'; + IsMain_i<='0'; + ResultOut<=(others=>'0'); + PortNum_i<=(others=>'-'); + RankAsked_i<='0'; + dma_wr_request<='0'; + When DecodeData => + EquFlag_i<=(All_zeros(Cmdreceived(2)(3 downto 0))); + RTS_cmd<='0'; + RTS_I<='0'; + BCast<='0'; + + Result_En<='0'; + + CM_Ack <='1'; --les données ont été reçues + --MyPort<=Cmdreceived(2)(3 downto 0); + PortNum_i<=Cmdreceived(2)(3 downto 0); --récupère les valeurs de port + PeerPort_i<=To_integer(unsigned(Cmdreceived(2)(3 downto 0))); + NocMax_i<=Cmdreceived(2)(7 downto 4); -- et la taille du réseau + PortNumFlag_i<='1'; -- le numéro du port est maintenant connu + CTR<='0' ; + DS_ACK<='0'; + Send_Ack<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + When IsPortZero => --Ce port est-il le n° 0 du NoC ? + BCast<='0'; + Result_En<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + NextRank_i<="0001"; -- le prochain rang à affecter sera le n° 1 + nextr_i<=1; + IsMain_i<=EquFlag; + --MyRank<="0000"; + MainPort_i<="0000"; + --MainAdr<="0000"; -- le port 0 est le main Lib par défaut; + CTR<='0' ; + DS_ACK<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + When SeekMain1 => -- recherche de la lib main + RTS_cmd<='0'; + --RTS_DAT<='1'; + RTS_I<='1'; + CTR<='1' ; -- prêt à recevoir les données Clear To Receive + DS_ACK<='0'; --les données sont attendus + Send_Ack<=BCast_rdy; + I_Send_Ack<=BCAst_rdy; + data_to_send_i(0)<=MPI_INIT & MyPort ; + data_to_send_i(1)<="00000100"; -- la longueur du packet =4 + data_to_send_i(2)<="0000" & MyPort; --propose sa propre adresse + data_to_send_i(3)<=INIT_SEEKMAIN & MyPort ; + DataLen_i<=4; + BCast<='1'; + + Result_En<='0'; + Initialized_i<='0'; + ram_wr<='0'; + rdy<='0'; + ResultOut<=(others=>'0'); + RankAsked_i<='0'; + dma_wr_request<='0'; + When SeekMain2 => -- recherche de la lib main + RTS_cmd<='0'; + RTS_I<='0'; + CTR<='1' ; -- prêt à recevoir les données Clear To Receive + DS_ACK<= DS_RDY; --les données sont acquittées aussitôt reçues + Send_Ack<=BCast_rdy; +-- data_to_send_i(0)<=INIT_SEEKMAIN & MyPort ; +-- data_to_send_i(1)<="00000011"; -- la longueur du packet =3 +-- data_to_send_i(2)<="0000" & MyPort; --propose sa propre adresse +-- DataLen<=3; + BCast<='0'; + Result_En<='0'; + Initialized_i<='0'; + ram_wr<='0'; + rdy<='0'; + ResultOut<=(others=>'0'); + EquFlag_i<='0'; + RankAsked_i<='0'; + dma_wr_request<='0'; + When StoreMain => -- la Main Lib est une autre + BCAST<='0'; + Result_En<='0'; + IsMain_i<='0'; + Initialized_i<='0'; + DS_ACK<=DS_RDY; + Send_Ack<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<=not(MainResp); -- essayer de recevoir tant que le main n'a pas répondu + ram_wr<='1'; + rdy<='0'; + ResultOut<=(others=>'0'); + RankAsked_i<='0'; + EquFlag_i<='0'; + MainPort_i<=DataReceived(0)(3 downto 0); + ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16)); + ram_data_in<=DataReceived(0)(3 downto 0)& DataReceived(2)(3 downto 0); --MainPort & MyRank + dma_wr_request<= '0'; ---pas très sûr + + When AskPeerStat => -- Interroge les données d'initialisation + RTS_cmd<='0'; + if n=0 then + --RTS_DAT<='0'; --on peut envoyer les données + RTS_I<='1'; + else + --RTS_DAT<='0'; --on désactive l'envoie des données + RTS_I<='0'; + end if; + CTR<='0' ; -- prêt à recevoir les données Clear To Receive + DS_ACK<='0'; --les données sont attendus + I_Send_Ack<=I_Send_rdy; + Send_Ack<=Send_rdy; + data_to_send_i(0)<=MPI_INIT & MainPort ; + data_to_send_i(1)<="00000100"; -- la longueur du packet =4 + data_to_send_i(2)<="0000" & MyPort; --indique sa propre adresse + data_to_send_i(3)<=INIT_STAT & MyPort ; + DataLen_i<=4; + BCast<='0'; + Result_En<='0'; + ram_wr<='0'; + rdy<='0'; + ResultOut<=(others=>'0'); + EquFlag_i<='0'; + RankAsked_i<='0'; + dma_wr_request<='0'; + When SetMainFlag => -- Cette Lib est la Main Lib + if (Datareceived(3)(7 downto 4) = INIT_SEEKMAIN) then + RankAsked_i<='1'; + else + RankAsked_i<='0'; + end if; + RTS_cmd<='0'; + Initialized_i<='0'; + RTS_I<='0'; + BCast<='0'; + IsMain_i<='1'; + Result_En<='0'; + --MyRank<="0000"; + MainPort_i<="0000"; + PeerStat_i(0)<='1'; --la main lib est initialisée + CTR<='1'; + DS_ACK<='0'; + ram_wr<='1'; + rdy<='0'; + ResultOut<=(others=>'0'); + EquFlag_i<='0'; + ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16)); + ram_data_in<=(others =>'0'); -- le port vaut 0 et la mainlib est aussi à 0 + dma_wr_request<='1'; + When ReadNoc => + if (Datareceived(3)(7 downto 4) = INIT_SEEKMAIN) then + RankAsked_i<='1' ; + else + RankAsked_i<='0'; + end if; + ram_wr<='0'; -- pas d'écriture en RAM + rdy<='0'; + BCast<='0'; + DS_ACK<='0'; + --IsMain<='0'; + Result_En<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<='1'; + ResultOut<=(others=>'0'); + PortNum_i<=DataReceived(2)(3 downto 0); -- le port qui demande un rang; + PeerPort_i<= To_integer(unsigned(DataReceived(2)(3 downto 0))); + --EquFlag<='1'; + dma_wr_request<='0'; + When GetMainReq => + --RankAsked_i<='1'; + ram_wr<='0'; -- pas + BCast<='0'; + DS_ACK<='1'; + Result_En<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<='1'; + ResultOut<=(others=>'0'); + PortNum_i<=DataReceived(0)(3 downto 0); -- le port qui demande un rang; + EquFlag_i<='1'; + dma_wr_request<='0'; + When GetPeerStat => + --RankAsked_i<='1'; + ram_wr<='0'; -- pas + BCast<='0'; + DS_ACK<=DS_RDY; + Result_En<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<=not MainResp; + ResultOut<=(others=>'0'); + PortNum_i<=DataReceived(0)(3 downto 0); --adresse du Main Port + PeerStat_i(7 downto 0)<=DataReceived(2); -- état des initialisations + EquFlag_i<='0'; + dma_wr_request<=dma_wr; + ram_wr<=wr_ok; + rdy<='0'; + ram_rd<=rd_ok; + Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_Init_Adr+2,ADRLEN)); --incr_vec(Ram_Next_Address,'1'); + ram_address<=Ram_Next_Address; -- + ram_data_in<=DataReceived(2); --enregistrer les ports actifs + + When NewRank => + nport:=to_integer(Unsigned(PortNum)); --port ayant sollicité le rang + nextr_i<=to_integer(unsigned(nextrank)); + if PeerStat(nport)='0' then -- si le rang n'a pas encore été affecté à ce port + nextrank_i<=incr_vec(nextrank,'1'); + RankToPort(to_integer(unsigned(nextrank)))<="0000" & PortNum; + NextAdr:=NextAdr+1; + end if; + data_to_send_i(0)<=MPI_INIT & PortNum ; + data_to_send_i(1)<="00000100"; + data_to_send_i(2)<="0000" & NextRank; --ici c'est la valeur avant incrémentation ! + data_to_send_i(3)<=INIT_SETRANK & PortNum ; + PeerStat_i(nport)<='1'; -- mise à jour du status + DataLen_i<=4; + BCast<='0'; + DS_ACK<='0'; + Result_En<='0'; + EquFlag_i<='1'; + RTS_cmd<='0'; + RTS_I<='1'; + CTR<='0' ; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='1'; + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + + When SendRank => + BCast<='0'; + Result_En<='0'; + EquFlag_i<='1'; + + RTS_I<='1'; + DataLen_i<=4; + RTS_cmd<='0'; + DS_ACK<='0'; + Send_Ack<='0'; + CTR<='0' ; + ram_wr<='0'; + Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_RANK_ADR+Nextr-1,16)); + ResultOut<=(others=>'0'); + RankAsked_i<='1'; + dma_wr_request<='0'; + When RegRank => + RankAsked_i<='0'; + + CTR<='1' ; -- continuer à recevoir les données du NoC + Result_En<='0'; + RTS_cmd<='0'; + DS_ACK<='0'; + Send_Ack<=Send_RDY; + I_Send_ack<=i_send_rdy; + Rts_I<='0'; + BCast<='0'; + EquFlag_i<='1'; + ram_wr<='1'; + + Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_RANK_ADR+Nextr-1,16)); --incr_vec(Ram_Next_Address,'1'); + ram_address<=Ram_Next_Address; -- le rang qui a été envoyé; + -- "le motif 0001 indique juste que le port est bien activé + ram_data_in<="0001" & PortNum; --enregistrer le port qui a fait la demande en RAM + ResultOut<=(others=>'0'); + dma_wr_request<='1'; + When SendPeerStat => + BCast<='0'; + Result_En<='0'; + EquFlag_i<='0'; + RTS_I<=PeerRTS; + RTS_cmd<='0'; + DS_ACK<='0'; + data_to_send_i(0)<=MPI_INIT & PortStat ; + data_to_send_i(1)<="00000100"; + data_to_send_i(2)<=PeerStat(7 downto 0); + data_to_send_i(3)<=INIT_REGISTER & MyPort ; + Send_Ack<=Send_Rdy; + I_Send_Ack<=I_Send_Rdy; + CTR<='0' ; + ram_wr<='0'; + rdy<='0'; + ResultOut<=(others=>'0'); + RankAsked_i<='1'; + dma_wr_request<='0'; + Initialized_i<='1'; + When StoreRank => --le processus qui écoute le Port et qui + --stoke les adresses des autres bib va gérer le stockage du rang + BCAST<='0'; + DS_ACK<='1'; + Send_Ack<='0'; + RTS_cmd<='0'; + EquFlag_i<='0'; + RTS_I<='0'; + CTR<='0'; + Result_En<='0'; + + if ExecTime_out='1' then + MainPort_i<="0000"; + --MyRank<=MyPort; + initialized_i<='0'; + else + MainPort_i<=DataReceived(0)(3 downto 0); + --MyRank<=DataReceived(2)(3 downto 0); + Initialized_i<='1'; + end if; + ram_wr<='1'; + --ram_address<=DataReceived(2); -- le rang qui a été envoyé; + ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16)); + ram_data_in<=DataReceived(0)(3 downto 0)& DataReceived(2)(3 downto 0); --MainPort & MyRank + ResultOut<=(others=>'0'); + RankAsked_i<='0'; + dma_wr_request<='1'; + When SendApp => --ajouter du code pour recevoir l'adr du reg status + Initialized_i<='1'; + ResultOut<="00000001"; -- Init Ok + Result_En<='1'; + PortId<=MyPort; + BCAST<='0'; + DS_ACK<='1'; + Send_Ack<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + dma_wr_request<='0'; + When SpawnApp => + RTS_cmd<='0'; + RTS_I<='0'; + Result_En<='0'; + DS_ACK<=DS_RDY; + BCAST<='0'; + CTR<='0'; --cette mise à 1 permet de ctrler la fin de réception + rdy<='0'; + ram_wr<=wr_ok; + ram_rd<=rd_ok; + Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_BASE_ADR,ADRLEN)); --incr_vec(Ram_Next_Address,'1'); + ram_address<=Ram_Next_Address; -- le rang qui a été envoyé; + -- "le motif 0001 indique juste que le port est bien activé + ram_data_in<=DataToRam; --enregistrer le port qui a fait la demande en RAM + dma_rd_request <= dma_rd; + dma_wr_request <=dma_wr; + RankAsked_i<='0'; + if n>=3 then + ResultOut<=("00000010");--spawn completed + else + ResultOut<=("00000000");--spawn message received + end if; + + When SpawnLoad => + RTS_cmd<='0'; + --RTS_DAT<='1'; --à tester + RTS_I<=PeerRTS; -- pour le timing + Result_En<='0'; + DS_ACK<='0'; + BCAST<='0'; + CTR<='0'; + rdy<='0'; + ram_wr<=wr_ok; + ram_rd<=rd_ok; + data_to_send_i(0)<=SpawnCmd0; + data_to_send_i(1)<="00000100"; + data_to_send_i(2)<=SpawnCmd1; + data_to_send_i(3)<=SpawnCmd2; -- SPAWN_LOAD & MyPort ; + Send_Ack<=Send_Rdy; + I_Send_Ack<=I_Send_rdy; + RankAsked_i<='0'; + if SpawnInit='1' then + ResultOut<=("10000000"); --spawn completed + else + ResultOut<=("01000000");--spawn in progress + end if; + When ErrSpawn => + RTS_cmd<='0'; + RTS_I<='0'; + Result_En<='1'; + DS_ACK<='0'; + Send_Ack<='0'; + BCAST<='0'; + CTR<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + dma_rd_request<='0'; + When EndInit => + RTS_cmd<='0'; + RTS_I<='0'; + Result_En<='0'; + DS_ACK<='0'; + Send_Ack<='0'; + BCAST<='0'; + CTR<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + dma_rd_request<='0'; + end case; + end process; + +result_proc:process (ISMain_i,Initialized_i,stInit2,reset) +begin +if reset='1' then + --IsMain1<='0'; + Initialized<='0'; + HCL_Init_i<='0'; + +Else + HCL_init_i<=HCl_init; + Initialized<=Hcl_init; +-- if ismain_i='1' then +-- IsMain1<='1'; +-- end if; + + if Initialized_i='1' and stInit2=EndInit then + Initialized<='1'; + HCL_Init_i<='1'; + elsif stInit2=SendApp then + HCL_Init_i<='1'; + end if; +end if; +end process result_proc; + --================ + --Traitement du Spawn + --=================== + + --================== + NEXT_STInit2_DECODE: process (stInit2,AppReq,Instruction_en, AppAck,PortNumFlag,EquFlag,MainResp,StatAsked,RankAsked,RankSent,CM_RDY, CmdReceived, + BCast_Rdy, DS_RDY, DataReceived,Ht_Start,vPeerStat, Send_RDY, I_Send_RDY,TimeOut,Dma_rd_grant,Dma_wr_grant,cpt,n,clk_cyl,IsMain1,SpawnOn, + Instruction,Hcl_Init,Spawn_done,mainport,PeerStat,PeerRTS,Rec_Data,SpawnInit,grp_id,SpawnNbReq,Ram_data_out,Spawn_grp,MyPort) + variable InitTimeOut :natural:=0; + variable LastPort,Ht_hole : std_logic:='0'; + variable i,nbSpawn,htloc,Ht_Id : natural range 0 to 15:=0; + --variable vPeerStat : std_logic_vector(15 downto 0); + variable vPortStat,nulvect : std_logic_vector(3 downto 0):="0000"; + variable tempval : std_logic_vector(Word-1 downto 0); + begin + --declare default state for next_state to avoid latches + next_stInit2 <= stInit2; --default is to stay in current state + --insert statements to decode next_state + --below is a simple example + vPeerStat_i<=vPeerStat; + SpawnNbReq<=SpawnNbReq_q; + StatAsked_i<=StatAsked; + MainResp_i<=MainResp; + AppSize_i<=AppSize1; + PortStat_i<=PortStat; + grp_id_i<=grp_id; + PeerRTS_i<=PeerRTS; + --PortNumFlag_i<=PortNumFlag; + SpawnReq<=SpawnReq_q; + Spawn_done_i<=Spawn_done; + Ht_Start_i<=Ht_Start; + SpawnCmd0<=SpawnCmd0_Q; + SpawnCmd1<=SpawnCmd1_Q; + SpawnCmd2<=SpawnCmd2_Q; + Timeout_i<=Timeout; + clk_cyl_i<=clk_cyl; + n_i<=n; + Cpt_peer<=cpt; + DataToRam<=(others=>'0');--A revoir + dma_rd<='0'; + dma_wr<='0'; + rd_ok<='0'; + wr_ok<='0'; + for i in 0 to 3 loop + Spawn_grp(i)<=Spawn_grp_q(i); + end loop; + case (stInit2) is + + + When Init =>If Instruction_en='1' and AppReq='1' then + If PortNumFlag='1' and IsMain1='1' then + if instruction(7 downto 4)=INIT_SEEKMAIN and (instruction(3 downto 0)/=MyRank) then + Next_stInit2 <=NewRank;--affecter un rang au demandeur. + elsif instruction(7 downto 4)=INIT_STAT then + StatASked_i<='1'; + Next_stInit2 <=SendPeerStat; --envoyer des stat au demandeur + elsif instruction(7 downto 4)=SPAWN_LOAD then + SpawnInit<='0'; -- indique le debut du Spawn + Next_stInit2 <=SpawnLoad; + elsif instruction(7 downto 4)=INIT_SPAWN then + SpawnInit<='1'; -- indique la fin du + Next_stInit2 <=SpawnLoad; --dans ce cas il s'agit de terminer le spawn + else --ignorer ce message + Next_stInit2 <=SendApp; + end if; + elsif HCL_Init='1' and IsMain1='0' then + Next_stInit2 <=SendApp; --ignorer ce message simplement + else + Next_stInit2 <=GetPortNum; -- initialiser la bibliothèque normalement + end if; + TimeOut_i<=0;PeerRTS_i<='0'; + + elsif SpawnOn='1' and Spawn_done='0' then + Next_stInit2 <=SpawnApp; + TimeOut_i<=0; + end if; + cpt_peer<=0;LastPort:='0';n_i<=0; + When GetPortNum => -- récupérer le numéro du port + + if CM_RDY='1' then + Next_stInit2 <=DecodeData; + end if; + + When DecodeData => -- cet état permet de lire les données reçues du port + --if CM_RDY='1' then + if ((Cmdreceived(2)(3 downto 0) or nulvect)=nulvect) then -- teste si le n° du port est zero + --EquFlag<='1'; + else + --EquFlag<='0'; + end if; + + Next_stInit2 <=IsPortZero; + --end if; + When IsPortZero => + if PortNumFlag='1' then + + End if; + if EquFlag='0' then --tester le numéro de port obtenu + Next_stInit2 <=SeekMain1; -- chercher le numéro de port sur le réseau + else + Next_stInit2<=SetMainFlag; -- enregistrer le numéro de port + End If; + TimeOut_i<=0; + + When SeekMain1 =>If BCast_RDY='1' then -- si tous les envois ont été postés + Next_stInit2<=SeekMain2; + End if; + When SeekMain2 => + If DS_RDY='1' then -- Si un jeu de données a été reçu + if (Datareceived(3)(7 downto 4) = INIT_SETRANK) then + MainResp_i<='1'; + Next_stInit2 <=StoreMain; -- de la librairie pricipale + else + MainResp_i<='0'; + Timeout_i<=0; + end if; + + elsif (ExecTime_Out='1') then + + -- le Noc ne répond pas + -- affecter un numéro en raport avec le port + Next_stInit2 <=SeekMain2; + elsif TimeOut=800 then + --essayer de redemander l'initialisation + assert true report "Ex4:seekmain ->redemander l'initialisation" + severity failure; + Timeout_i<=0; + Next_stInit2 <=SeekMain1; + else + Timeout_i<=TimeOut+1; + End if; + + + + When StoreMain => + if DataReceived(3)(7 downto 4)= INIT_SETRANK then + -- enregistrer le Main Adresse et les adresses des autres processus + -- dans la variable prévue à cet effet + Next_stInit2 <=StoreRank; + + elsif Datareceived(3)(7 downto 4) = INIT_SEEKMAIN then + -- ignorer ce message + Next_stInit2 <=StoreMain; --essayer de recevoir le rang + + + end if; + + When StoreRank => + --il faut prévoir du code pour s'assurer que la RAM a bien enregistrer + -- la donnée ... + if dma_wr_grant = '1' then + if clk_cyl=2 then --prévoir deux cycle d'horloge pour lire en RAM + Next_stInit2 <=AskPeerStat; + TimeOut_i<=0; + clk_cyl_i<=0; + else + clk_cyl_i<=clk_cyl+1; + end if; + else + Next_stInit2 <=StoreRank; + TimeOut_i<=0; + clk_cyl_i<=0; + end if; + When AskPeerStat =>if n=0 then + If I_SEND_RDY='1' then -- si tous les envois ont été postés + n_i<=1; + StatAsked_i<='0'; + End if; + elsif n=1 then + If I_SEND_RDY='0' then -- si tous les envois ont été postés + Next_stInit2<=GetPeerStat; + StatAsked_i<='1'; + MainResp_i<='0'; + n_i<=0; + End if; + end if; + When GetPeerStat => + if n=0 then + If DS_RDY='1' then -- Si un jeu de données a été reçu + if (Datareceived(3) = INIT_REGISTER & MainPort ) then + MainResp_i<='1'; + n_i<=n+1; + + else + MainResp_i<='0'; + Timeout_i<=0; + n_i<=n; + end if; + + elsif TimeOut=1800 then + --essayer de redemander les statistiques + assert true report "Ex4:GetPeerStat timeout ->Les statistiques n'ont pas été reçu" + severity failure; + Timeout_i<=0; + If StatAsked='1' then + Next_stInit2 <=AskPeerStat; -- ceci n'est pas sûr + else + Next_stInit2 <=GetPeerStat; + end if; + else + Timeout_i<=TimeOut+1; + End if; + elsif n=1 then --écrire le résultat de l'initialisation + dma_wr<='1'; + if dma_wr_grant='1' then + n_i<=n+1; + wr_ok<='1'; + end if; + elsif n=2 then + n_i<=n+1; --écriture dans la RAM + elsif n=3 then + n_i<=0; + dma_wr<='0'; + Next_stInit2 <=SendApp; -- de la librairie pricipale + end if; + When SetMainFlag => + if dma_wr_grant='1' then + TimeOut_i<=0; + Next_stInit2 <=ReadNoc; + elsif Timeout=800 then + assert true report "Ex4:SetMainFlag timeout ->La mémoire n'est pas dispo dma_wr_grant=0" + severity failure; + Next_stInit2 <=SendApp; + else + TimeOut_i<=TimeOut+1; +-- end if; -- il est envisagée de terminer le programme à ce point + end if; + when ReadNoc => if DS_RDY='1' then + if (Datareceived(3)(7 downto 4) = INIT_STAT) then + StatAsked_i<='1' ; + Next_stInit2 <=SendPeerStat; + LastPort:='0'; + else + StatAsked_i<='0'; + Next_stInit2 <=GetMainReq; + end if; + + Timeout_i<=0; + elsif Timeout=400 then + assert true report "Ex4:ReadNoc timeout pas de données lues sur le NoC après 200 cycles" + severity failure; + Timeout_i<=0; + --if StatAsked = '1' then + --Next_stInit2 <=ErrSpawn; --il y a eu une erreur + Next_stInit2 <=SendApp; + -- else + -- Next_stInit2 <=SendPeerStat; + -- end if; + else + TimeOut_i<=TimeOut+1; + end if; + + When GetMainReq => if RankAsked='1' and PeerStat(PeerPort)='0' then + Next_stInit2 <=NewRank; -- un nouveau rang est demandé + else + Next_stInit2 <=ReadNoC; -- sinon essayer encore de lire un jeu de données. + end if; + When NewRank => + Next_stInit2 <=SendRank; + When SendRank => + if I_Send_RDY='1' then --RankSent + Next_stInit2 <=RegRank; + RankSent_i<='1'; -- le rang a été envoyé + TimeOut_i<=0; -- prépare le traitement de la prochaine requête + -- d'attente des ports + elsif Timeout=800 then + assert true report "Impossible d'envoyer le rang" + severity failure; + timeout_i<=0; + else + TimeOut_i<=TimeOut+1; + end if; + When RegRank => + --il faut prévoir du code pour s'assurer que la RAM a bien enregistrer + -- la donnée ... + if dma_wr_grant = '1' then +-- if DS_RDY='1' then + RankSent_i<='0'; + if DS_RDY='0' then + + Next_stInit2 <=ReadNoc; + end if; + elsif Timeout=800 then + Next_stInit2 <=SendApp; + assert true report "Ex4:RegRank Timeout dma_wr_grant=0 " + severity failure; + else + TimeOut_i<=TimeOut+1; +-- end if; -- il est envisagée + end if; + --calcul de la taille de l'appli + HtLoc:=0; + for i in 0 to 7 loop + if peerStat(i)='1' then --trouve le prochai rang libre + HtLoc:=HtLoc+1; + end if; + end loop; + AppSize_i<=std_logic_vector(to_unsigned(HtLoc,4)); + + When SendPeerStat => + + if cpt<=unsigned(NoCMax)and LastPort='0' then + if peerRts='0' then -- pas encore envoyer les données alors les préparer + if StatAsked='1' then + + PortStat_i<=PortNum; + vPortStat:=std_logic_vector(to_unsigned(PeerPort,4)); + else + PortStat_i<=std_logic_vector(to_unsigned(cpt,4));--Port à contacter + vPortStat:=std_logic_vector(to_unsigned(cpt,4)); + end if; + + if StatAsked='1' then + LastPort:='1'; -- on traite u seul port celui qui en a fait la demande + if PeerStat(PeerPort)='1' then + PeerRts_i<='1'; + end if; + else + if (PeerStat(cpt)='1') and not(vPortStat=MyPort) then + PeerRts_i<='1'; + end if; + if cpt Impossible d'envoyer sur le NoC" + severity failure; + else + TimeOut_i<=TimeOut+1; + end if; + end if; + elsif PeerRTS='1' then -- le dernier port est il activé ? + if I_Send_RDY='1' then + RankSent_i<='1'; -- les stat ont été envoyé + TimeOut_i<=0; -- prépare le traitement de la prochaine requête + PeerRts_i<='0'; + if statAsked='1' then + -- Next_stInit2<=ReadNoc; + + Next_stInit2<=SendApp; --terminer l'application + end if; + + elsif TimeOut=100 then + Next_stInit2 <=EndInit; + assert true report "Ex4:SendPeerStat Timeout -> Impossible d'envoyer sur le NoC" + severity failure; + else + TimeOut_i<=TimeOut+1; + end if; + else + Next_stInit2<=SendApp; + end if; + When SendApp => -- envoyer au programme un signal + -- et attendre un acquittement et l'adresse de base + If AppAck='1' then + Next_stInit2 <=EndInit; + end if; + + When SpawnLoad => + + if n=0 then + ht_id:=to_integer(unsigned(rec_data(0)(3 downto 0))); + vPeerStat_i<=PeerStat; --récupérer la situation actuelle des tâches créées + if IsMain1='1' and SpawnInit='0' then + SpawnNbReq<=to_integer(unsigned(Instruction(3 downto 0))); -- sauver le nombre de HT à créer + + n_i<=1; + SpawnReq(ht_id)<='1'; --Note l'id de HT qui a appelé le Spawn + elsif IsMain1='1' and SpawnInit='1' then -- il faut envoyer les acquittements + ht_id:=to_integer(unsigned(rec_data(0)(3 downto 0))); + Spawn_grp(grp_id)(ht_id)<='1'; --noter le port du Fils Spawné dans ce groupe + Ht_start_i<=0; --compte le nombre de tâches chargées + n_i<=6; + + else + if SpawnOn='1' then --if IsMain_i='0' then -- il faut juste charger puis activer la tâche + n_i<=7; + end if; + assert true + Report "SpawnLoad : Cas non prévu !" + severity failure; + end if; + elsif n=1 then + if PeerStat=SpawnReq then --tous les Hts ont appelés Spawn ? + ht_hole:='0'; + L1: for i in 0 to 15 loop + if vPeerStat(i)='0' then + SpawnDest<=std_logic_vector(to_unsigned(i,4)); -- le port à activer + SpawnCmd0<=MPI_SPAWN & std_logic_vector(to_unsigned(i,4)); + vPeerStat_i(i)<='1'; + Ht_Start_i<=Ht_Start+1; + Ht_Hole:='1'; -- une place a été trouvé + else + Ht_hole:='0'; -- pas de place trouvé + end if; + exit L1 when ht_hole='1'; + end loop L1; + if Ht_hole='0' then -- toutes les tâches n'ont pas été créés + -- aller à la fin ! en signalant une erreur! + SpawnCMd2<=Spawn_Err & "0001"; --erreur pas assez de ports sur le NoC + n_i<=9; + else + n_i<=n+1; + SpawnCmd1<=PeerStat(7 downto 0); + SpawnCmd2<=SPAWN_START & MyPort; + end if; + else --Tous les Hts n'ont pas appelé Spawn encore + Next_stInit2<=SendApp; --on termine normalement + n_i<=0; + end if; + elsif n=2 then + PeerRTS_i<='1'; -- envoyer les données du Spawn + n_i<=n+1; + elsif n=3 then + if I_Send_RDy='1' then + n_i<=n+1; + PeerRts_i<='0'; + end if; + elsif n=4 then + if SpawnInit='0' then + if Ht_Start>=SpawnNbReq then + n_i<=n+1; + else + n_i<=1; -- passer à la création du HT suivant + end if; + else + n_i<=7; -- passer au contact du HT suivant + end if; + elsif n=5 then + -- Aller à la fin le résultat du Spawn + + n_i<=10; + elsif n=6 then + nbSpawn:=0; + for i in 0 to 15 loop + if Spawn_grp(grp_id)(i)='1' then + nbSpawn:=nbSpawn+1; + end if; + end loop; + if nbSpawn=SpawnNbReq then + n_i<=n+1; --aller renvoyer les réponses + else + n_i<=10; --fin du Spawn + + end if; + elsif n=7 then + Ht_hole:='0'; +L2: for i in 0 to 7 loop --for i in Ht_start to 7 loop + if i>=Ht_start then + if vPeerStat(i)='1' and Spawn_grp(grp_id)(i)='0' then --on avertit les membres du groupe parent + --mais pas ceux du groupe Fils ! + SpawnDest<=std_logic_vector(to_unsigned(i,4)); -- le port à avertir + SpawnCmd0<=MPI_ACK & std_logic_vector(to_unsigned(i,4)); + vPeerStat_i(i)<='0'; + Ht_Start_i<=i+1; -- le prochain Ht à prévenir + Ht_Hole:='1'; -- Une tâche doit être avertie + else + Ht_hole:='0'; -- + end if; + end if; + exit L2 when ht_hole='1'; + end loop L2; + n_i<=n+1; + elsif n=8 then + if Ht_hole='1' then -- + -- un HT existant à prévenir ! + SpawnCmd1<=Spawn_grp(grp_id)(7 downto 0); + SpawnCMd2<=MPI_SPAWN & MyRank; -- fin du Spawn + n_i<=2; --envoyer la donnée sur le réseau + elsif vpeerstat /=spawn_grp(grp_id) then --il ne reste plus de membres à prévenir ? + n_i<=7; --on est sorti mais ce n'est pas la fin + + else -- fin du Spawn car tous ont été averti + n_i<=10; + SpawnNbReq<=0; + SpawnReq<=(others=>'0'); + vPeerStat_i<=(others=>'0'); + grp_id_i<=grp_id+1; --incrementer le compteur de groupes************ + end if; + elsif n=9 then + assert true report "error in Spawn command" + severity failure; + elsif n=10 then + n_i<=0; + Next_stInit2<=SendApp; + end if; + + When SpawnApp=> + --Mise à jour du bit 6 du registre status du COre. + if n>=0 and n <4 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + + if n=0 then + if DS_RDY='1' then --- + if Datareceived(3)(7 downto 4)=SPAWN_START then + n_i<=n+1; + else + Next_stInit2<=ErrSpawn; + n_i<=0; --erreur instruction incorrecte + end if; + + rd_ok<='1'; + wr_ok<='0'; + end if; + elsif n=1 or n=2 then + if dma_rd_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + end if; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=3 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + tempval(6):='1'; + + dataToram<=tempval; + rd_ok<='0'; + wr_ok<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + end if; + elsif n=4 then + if spawninit='0' then + Spawn_done_i<='1'; + end if; + rd_ok<='0'; + wr_ok<='0'; + n_i<=0; + Next_stInit2<=EndInit; + end if; + + When ErrSpawn => + assert true + report "Ex4/stInit2/SpawnApp:Erreur lors de Spawn" + severity failure; + Next_stInit2<=Init; + When EndInit=> + + StatAsked_i<='0'; --reset de ces variables + Next_stInit2<=Init; + end case; + end process; + +--================================================ +--sauvegarde du rang et du main port à l'adresse de retour de la fonction Init +--================================================== + +--==================================================== +--envoie des données sur le port +--=================================================== +selector<=(Rcv_on,Cmd_on,Snd_on); + +process (selector,Rport_out_rd_en,cport_out_rd_en,sPort_in_wr_en ,cPort_in_wr_en, + tosend ,tosend4) +begin + case selector is + + when "000" => port_in_data<=(others=>'-'); + Port_in_wr_en<='0'; + Port_out_rd_en<='0'; + + when "001" => port_in_data<=tosend; --envoie de données + Port_in_wr_en<=sPort_in_wr_en ; + Port_out_rd_en<='0'; + when "101" => port_in_data<=tosend; --envoie de données + Port_in_wr_en<=sPort_in_wr_en ; + Port_out_rd_en<=Rport_out_rd_en ; + when "010" | "110" | "011" | "111" => + port_in_data<=tosend4; --envoie de commande GetPort + Port_in_wr_en<=cPort_in_wr_en; + Port_out_rd_en<=cport_out_rd_en; + + when "100" => port_in_data<=(others=>'-'); -- réception de données + Port_in_wr_en<='0'; + Port_out_rd_en<=Rport_out_rd_en ; + + when others => port_in_data<=(others=>'-'); + Port_in_wr_en<='0'; + Port_out_rd_en<='0'; + end case; +end process; + +--================================================== + + --=============================================================== + --processus d'accès au réseau + --=============================================================== + + + + + + preceiv:process(clk,reset) + + variable origport,destport : natural range 0 to 15; + variable dcount,dlen ,rtimeout:natural range 0 to 1023; + variable ptype : std_logic_vector(3 downto 0); + variable bad_paquet :std_logic:='0'; + begin +-- + + if reset='1' then + etrec<=r_wait; + destport:=1; + rtimeout:=0; + bad_paquet:='0'; + else + if rising_edge(clk) then + case etrec is + when r_wait => + + rtimeout:=0; + bad_paquet:='0'; + --modifier le 01-08-pour gérer le Spawn + if Port_out_data_available='1' and Cmd_on='0' then + ptype:=port_out_data(7 downto 4); + origport:=to_integer(unsigned(port_out_data(3 downto 0))); + + if ptype=MPI_SPAWN and not(portnumflag='1') then + etrec<=r_dlen; --identification de la signature d'en tête valide + Datareceived(0)<=Port_out_data; --stocker l'entête + bad_paquet:='0'; + SpawnOn<='1'; --le spawn est actif + elsif Instruction_en='0' and CTR='0' and Hcl_init= '0' then + --il faut éliminer ce paquet qui est inoportun ! + Bad_paquet:='1'; + etrec<=r_dlen; --il faut ignorer cette donnée et quitter + dcount:=1; + elsif CTR='1' then + if ptype=MPI_INIT or ptype=INIT_SETRANK or ptype=INIT_SEEKMAIN or ptype=INIT_REGISTER then + etrec<=r_dlen; --identification de la signature d'en tête valide + Datareceived(0)<=Port_out_data; --stocker l'entête + bad_paquet:='0'; + else + --une donnée non attendue est présente sur le port + etrec<=r_dlen; --il faut ignorer cette donnée et quitter + dcount:=1; + bad_paquet:='1'; + Datareceived(0)<=(others=>'0'); + end if; + end if; + --elsif Port_out_data_available='1' and CTR='0' then + -- etrec<=r_drop; + else + + etrec<=r_wait; + end if; + DS_RDY<='0'; + When r_drop => -- ignorer les messages qui arrivent à ce noeud tant que + --l'application n'a pas été initialisée + if port_out_data_available='0' then + etrec<=r_end; + dcount:=0; + + end if; + + + + --Rport_out_rd_en<='1'; --lire les données qui sont dans le tampon de sortie + DS_RDY<='0'; + when r_Dlen => --positionnement du mot de longueur des données + if Port_out_data_available ='1' then + + --Rport_out_rd_en<='1'; + etrec<=r_glen; + rtimeout:=0; + else + rtimeout:=rtimeout+1; + if rtimeout>=30 then + assert true report "Ex4:etrec r_glen Timeout -> Impossible de recevoir du NoC" + severity failure; + Exectime_out<='0'; --read Noc time out + etrec<=r_end; -- données pas prêtes + end if; + + + end if; + DS_RDY<='0'; + -- + when r_glen => --lecture effective de la longueur des données + if port_out_data_available='1' then + dlen:=to_integer(unsigned(port_out_data(Word-1 downto 0))); + Datareceived(1)<=Port_out_data; + --RPort_out_rd_en<='0'; + etrec<=r_data; + dcount:=2; -- initialisation du compteur de reception (il y a + -- déjà deux mots reçues + else + rtimeout:=rtimeout+1; + if rtimeout>=30 then + assert true report "Ex4:etrec Timeout -> Impossible de recevoir sur le NoC" + severity failure; + ExecTime_out<='0'; + etrec<=r_end; -- données pas prêtes + end if; + + end if; + DS_RDY<='0'; + when r_data => -- lecture des données + if port_out_data_available='1' then + + --Rport_out_rd_en<='1'; --autoriser la lecture + if bad_paquet='0' then + DataReceived(dcount)<=Port_out_data; --récupération des données + else + DataReceived(2)<=(others=>'0'); + --ignorer ces données + end if; + --assert true report "Donnée lue :"; --& string(unsigned(port4_out(Word-1 downto 0))) + DS_RDY<='0'; + dcount:=dcount+1; + --severity note; + if dlen <=dcount then -- ce doit être égale ici et non <= ??? + etrec<=r_end; + DS_RDY<= not bad_paquet; -- jeu de données disponibles + elsif dcount=255 then --dépassement de la capacité + DS_RDY<='0'; + etrec<=r_end; + end if; + else + rtimeout:=rtimeout+1; + if rtimeout>=30 then + ExecTime_out<='0'; + etrec<=r_end; -- données pas prêtes + end if; + DS_RDY<='0'; + + end if; + when r_pulse => + etrec<=r_end; + DS_RDY<=not bad_paquet; + when r_end => + + --rPort_out_rd_en <='0'; + + if DS_ACK='1' or rtimeout> 30 or (CTR='0' and SpawnOn='0') or bad_paquet='1' then + DS_RDY<='0'; + SpawnOn<='0'; + etrec<=r_wait; + else + DS_RDY<=DS_RDY; + end if; + end case; + end if;--reset='1' + end if; + end process preceiv; + + val_preceiv: process (etrec) + begin + case etrec is + when r_wait => +-- DS_RDY<='0'; + rcv_on<='0'; + Rport_out_rd_en <='0'; + when r_dlen => +-- DS_RDY<='0'; + Rport_out_rd_en <='1'; + rcv_On<='1'; + when r_drop => +-- DS_RDY<='0'; + Rport_out_rd_en <='1'; + rcv_On<='1'; + when r_glen => + Rport_out_rd_en <='1'; +-- DS_RDY<='0'; + rcv_On<='1'; + when r_data => + Rport_out_rd_en <='1'; +-- DS_RDY<='0'; + rcv_On<='1'; + when r_pulse => + Rport_out_rd_en <='0'; + rcv_On<='1'; +-- DS_RDY<='1'; + when r_end => + Rport_out_rd_en <='0'; +-- DS_RDY<='0'; + rcv_On<='0'; + when others => + Rport_out_rd_en <='0'; +-- DS_RDY<='0'; + rcv_On<='0'; + end case; + end process; + + psend:process(clk,reset) + --génération des paquets à partir du port courant + variable pactype :natural range 0 to 15; + variable destport : natural range 0 to 15:=0; + variable realdlen, i,i_pair : natural range 0 to 255; + variable MaxPort : natural :=4; -- en fait ne doit pas être 0 + + + begin + if rising_edge(clk) then + if reset='1' then + etsnd<=s_init; + + + + else -- le process s'exécute sur chaque front + -- montant de l'horloge + case etsnd is + when s_init => tosend<=(others=>'-'); + MaxPort :=to_integer(unsigned(NOCMAX)); + sPort_in_wr_en<='0'; + if port_in_full='0' and Rts_dat='1' then --on peut aussi tester si le port est vide + BCast_RDY<='0'; -- pas la fin de du Broadcasting + Send_RDY<='0'; + Snd_on<='1'; + if Bcast='1' then -- envoyer à tous les ports le même message ? + DestPort :=0; + else + DestPort:=to_integer(unsigned(data_to_send(0)(3 downto 0))); + end if; + etsnd<=s_head; + end if; + when s_head => -- construction et envoie de l'en-tête + Send_RDY<='0'; --l'envoi commence + BCast_RDY<='0'; + Snd_on<='1'; + --pactype:=to_integer(MPI_INIT);-- + pactype:=to_integer(unsigned(data_to_send(0)(7 downto 4))); + --realdlen:=to_integer(unsigned(Datalen)); + --? destport:=MAXPORT; -- le port de destination + + tosend <=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4)); + sPort_in_wr_en<='1'; -- + + i:=1; + etsnd<=s_len2; -- passer à l'état suivant + + when s_len => + BCast_RDY<='0'; + Send_RDY<='0'; + Snd_on<='1'; + --tosend<=(STD_LOGIC_VECTOR(to_unsigned(Realdlen,8))); + tosend<=data_to_send(1); + sPort_in_wr_en <='1'; + + + --port1_in<=tosend1; --copie directe sur le port + etsnd<=s_len2; + when s_len2 => + --tosend<=(STD_LOGIC_VECTOR(to_unsigned(realdlen,8))); + sPort_in_wr_en<='1'; + tosend<=data_to_send(1); + + --port1_in<=tosend1; --copie directe sur le port + etsnd<=s_data; + BCast_RDY<='0'; + Send_RDY<='0'; + Snd_on<='1'; + i:=i+1; + when s_data => + Snd_on<='1'; + if Port_in_full='0' and RTS_dat='1' then + sPort_in_wr_en<='1'; + + --envoie des données sur le port + tosend<=data_to_send(i); + + + if i+1>=datalen then + etsnd<=s_end; + Send_RDY<='1'; --l'envoi est terminé + if BCast='1' and destport=MAXPort then + BCAST_RDY<='1'; --l'envoi collectif aussi + else + BCast_RDY<='0'; + + end if; + else + BCast_RDY<='0'; + Send_RDY<='0'; + i:=i+1; + end if; + elsif port_in_full='1' then + sPort_in_wr_en<='0'; + else + sPort_in_wr_en<='0'; + BCast_RDY<='0'; + Send_RDY<='0'; + end if; + when s_end => + tosend<=(others=>'-'); + + sPort_in_wr_en<='0'; + if Bcast='1' then + if destPort + if Port_in_empty='1' and RTS_Cmd='1' then + etcmd<=cmdpost; + + end if; + destport:=0; + ctimeout:=0; + origport:=1; + when cmdpost => + if Port_in_empty='1' then + etcmd<=cmdread; + end if; + + when cmdpostidle => --permet juste la prise en compte de la commande + etcmd<=cmdread; + dcount<=0;-- initialisation du compteur de reception + when cmdread => + + + ctimeout:=0; + + if Port_out_data_available='1' then + mport:=to_integer(unsigned(port_out_data(7 downto 4))); + pid:=to_integer(unsigned(port_out_data(3 downto 0)))+1; + CmdReceived(dcount)<=port_out_data; + --cdata_out_en(origport)<='1'; +-- if pid=origport then --le port a été bien identifié + etcmd<=cmdglen; -- + dcount<=dcount+1; +-- else +-- etcmd<=cmdtimeout; +-- end if; + else + + etcmd<=cmdread; + end if; + + + when cmdlen => --positionnement du mot de longueur des données + if Port_out_data_available='1' then + + etcmd<=cmdglen; + ctimeout:=0; + else + ctimeout:=ctimeout+1; + if ctimeout>=30 then + assert true report "Ex4:etcmd Timeout -> impossible de recevoir du le NoC" + severity failure; + etcmd<=cmdtimeout; -- données pas prêtes + end if; + + + end if; + when cmdglen => --lecture effective de la longueur des données + if Port_out_data_available='1' then + cdlen<=to_integer(unsigned(port_out_data(Word-1 downto 0))); + CmdReceived(dcount)<=port_out_data; + etcmd<=cmddata; + dcount<=dcount+1; + else + ctimeout:=ctimeout+1; + if ctimeout>=30 then + --time_out(destport)<='1'; + assert true report "Ex4:etcmd Timeout -> impossible de recevoir du le NoC" + severity failure; + etcmd<=cmdtimeout; -- données pas prêtes + end if; + + end if; + + when cmddata => + if (port_out_data_available='1' and ctimeout<30) then + + --cdata_out_en(origport)<='1'; + mport:=to_integer(unsigned(port_out_data(7 downto 4))); + --attention les ports sont numérotés à partir de 0 + pid:=to_integer(unsigned(port_out_data(3 downto 0)))+1; + CmdReceived(dcount)<=port_out_data; + if (dcount>=cdlen-1 ) then--attention le compteur de données commence à 0 + etcmd<=cmdend; + --CM_RDY<='1'; + else + dcount<=dcount+1; + end if; + Else + + if ctimeout>=30 then + --time_out(destport)<='1'; + etcmd<=cmdtimeout; -- données pas prêtes + assert true report "Ex4:etcmd. cmddata Timeout -> impossible de recevoir du le NoC" + severity failure; + else + ctimeout:=ctimeout+1; + etcmd<=cmdend; + end if; + end if; + when cmdend => + + etcmd<=cmdstart; + + when cmdtimeout => + + etcmd<=cmdstart; + end case; + --sorigport<=origport; + end if; --reset='1' + end if; + end process pcmd; + +majetcmd: process (etcmd,data_to_send, port_out_data_available, dcount,port_out_data) +variable origport : natural; +variable i:natural:=0; + begin + case etcmd is + when cmdstart => + i:=0; + Port_in_cmd_en<='0'; + tosend4<=(others=>'-'); + cport_out_rd_en<='0'; + cport_in_wr_en<='0'; + CM_RDY<='0'; + Cmd_on<='0'; + when cmdpost | cmdpostidle => + cport_in_wr_en<='1'; + tosend4<=data_to_send(0); ---code pour getportid + Port_in_cmd_en<='1'; + cport_out_rd_en<='0'; + CM_RDY<='0'; + Cmd_on<='1'; + when cmdread => + tosend4<=(others=>'-'); + cPort_in_wr_en<='0'; + cport_out_rd_en<=port_out_data_available; + --CmdReceived(dcount)<=port_out_data; --mettre les données dans le tampon + Port_in_cmd_en<='1'; + CM_RDY<='0'; + Cmd_on<='1'; + when cmdlen |cmdglen => --positionnement du mot de longueur des données + tosend4<=(others=>'-'); + cport_in_wr_en<='0'; + cport_out_rd_en<=port_out_data_available; + Port_in_cmd_en<='1'; + --CmdReceived(dcount)<= port_out_data; + CM_RDY<='0'; + Cmd_on<='1'; + when cmddata => + tosend4<=(others=>'-'); + cport_in_wr_en<='0'; + cport_out_rd_en<=Port_out_data_available; + Port_in_cmd_en<='1'; + --CmdReceived(dcount)<=port_out_data; --mettre les données dans le tampon + i:=i+1; + CM_RDY<='0'; + Cmd_on<='1'; + when cmdend => + tosend4<=(others=>'-'); + cport_in_wr_en<='0'; + cport_out_rd_en<='0'; + --CmdReceived(dcount)<=port_out_data; + Port_in_cmd_en<='0'; + CM_RDY<='1'; + Cmd_on<='0'; + when cmdtimeout => + tosend4<=(others=>'-'); + cport_in_wr_en<='0'; + cport_out_rd_en<='0'; + Port_in_cmd_en<='0'; + Cmd_on<='1'; + cm_rdy<='0'; + end case; + +end process majetcmd ; + +i_send_val:process(HCL_Init,Send_RDY,RTS_I,Snd_Ack,I_send_ack,data_to_send,Bcast_rdy,Bcast) +begin +snd_start_i<=snd_start; +RTS_DAT<='0'; + +if HCL_Init='1' then + if RTS_I='1' and snd_ack='0' then + snd_start_i<='1'; + elsif i_send_ack='1' then + + snd_start_i<='0'; + else + snd_start_i<='0'; + end if; + i_send_rdy<=snd_ack; + + Snd_data<=data_to_send; +else + if RTS_I='1' and i_send_ack='0' then + RTS_DAT<='1'; + elsif i_send_ack='1' then + + RTS_DAT<='0'; + end if; + i_send_rdy<=send_rdy; + for i in 0 to 3 loop + Snd_data(i)<=(others=>'0'); + end loop; +end if; +end process; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX4_FSM.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX4_FSM.vhd.bak (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/EX4_FSM.vhd.bak (revision 138) @@ -0,0 +1,1948 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM +-- +-- Create Date: 14:44:36 03/07/2012 +-- Design Name: +-- Module Name: EX4_FSM - Behavioral +-- Project Name: MPI_CORE_COMPONENTS +-- Target Devices: SPARTAN 3E xc3s1200e +-- Tool versions: +-- Description: Ce module renferme les fonctions permettant d'initialiser la +-- bibliothèque matériel MPI +-- Dependencies: +-- +-- Revision: 25/juin/2012 au 24/Octobre/2012 +-- Revision 0.03 - File updated +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; + +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; +Library NocLib; +use NoCLib.CoreTypes.all; +use work.packet_type.all; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX4_FSM is + Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_En : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + ResultOut : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); + Result_En : out STD_LOGIC:='0'; + Ready : out STD_LOGIC; --indique que le module est disponible + NocSize : out STD_LOGIC_VECTOR(3 downto 0); + PortId : out STD_LOGIC_VECTOR(3 downto 0):=(others=>'0'); + AppRank : out STD_LOGIC_VECTOR(3 downto 0):=(others=>'0'); + AppSize : out STD_LOGIC_VECTOR(3 downto 0):=(others=>'0'); + IsMain : out STD_LOGIC; + I_fifo_full :in STD_LOGIC; --instruction fifo + I_fifo_wr_en: out STD_LOGIC;--instruction fifo Write enable + I_fifo_data_in :out STD_LOGIC_vector(Word-1 downto 0); --instruction fifo data + Initialized : out STD_LOGIC; + Snd_Ack : IN std_logic; + Rec_Rdy : IN std_logic; + Rec_Data : IN Typ_PortIO(0 to 3); + Snd_data : OUT Typ_PortIO(0 to 3); + Snd_Start : buffer std_logic; + Rec_Ack : OUT std_logic; + dma_wr_grant : in STD_LOGIC; + dma_wr_request : out STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + ram_rd : out std_logic; + ram_wr : out std_logic; + ram_address : out std_logic_vector(ADRLEN-1 downto 0);--accès au stockage + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + + AppAck : in STD_LOGIC; + AppReq : in STD_LOGIC; + port_in_cmd_en : out STD_LOGIC:='0'; + port_in_wr_en : out STD_LOGIC:='0'; + port_in_empty : in STD_LOGIC; + port_in_full : in STD_LOGIC; + port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'-'); + port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_rd_en : out STD_LOGIC:='0'; + port_out_data_available : in STD_LOGIC); +end EX4_FSM; + +architecture Behavioral of EX4_FSM is + +COMPONENT SetBit + PORT( + clk : IN std_logic; + reset : IN std_logic; + BitNum : IN std_logic_vector(0 to 2); + BitVal : IN std_logic; + dma_wr_grant : IN std_logic; + dma_rd_grant : IN std_logic; + Ram_data_in : IN std_logic_vector(7 downto 0); + + dma_wr_request : OUT std_logic; + dma_rd_request : OUT std_logic; + ram_rd : OUT std_logic; + ram_wr : OUT std_logic; + ram_address : OUT std_logic_vector(15 downto 0); + Ram_data_out : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; +Type Ar_MPIPort_In is array (positive range <>) of Typ_MPIPort_in; +Type Ar_MPIPort_out is array (positive range <>) of Typ_MPIPort_out; + + --MAE pour emission de init + --type init1_type is (init,NocSize,InitToNoc,NextPort,EndBCast); + -- MAE pour affectation des rangs aux différentes librairies MPI + type init2_type is (init,GetPortNum,DecodeData,IsPortZero,SeekMain1,SeekMain2,StoreMain,SetMainFlag,ReadNoc,GetMainReq,StoreRank,NewRank,SendRank,RegRank,SendPeerStat,AskPeerStat,GetPeerStat,SendApp,SpawnApp,SpawnLoad,ErrSpawn,EndInit); + -- MAE pour réception de init depuis le réseau; + type init3_type is (init,GetNocSize,ReadInitHead,StorePort,EndInit); + type typ_send is (s_init,s_head,s_len,s_len2,s_data,s_end); + type typ_receiv is (r_wait,r_dlen,r_drop,r_glen,r_data,r_pulse,r_end); + type typ_cmd is (cmdstart,cmdpost,cmdpostidle,cmdread,cmdlen,cmdglen,cmddata,cmdend,cmdtimeout); + type typ_mem16 is array(natural range <>) of std_logic_vector(15 downto 0);-- + signal etsnd : typ_send; + signal etrec:typ_receiv; --pour la machine à état de réception + signal etcmd :typ_cmd; --pour la machine à état de commande +signal IS_state,next_Is_state : natural range 0 to 3:=0; + +-- signal stInit1, next_stInit1 : init1_type; + signal stInit2, next_stInit2 : init2_type; + --signal stInit3, next_stInit3 : init3_type; + --signaux pour l'interface avec les ports + signal cport_in_wr_en,sport_in_wr_en:std_logic; + signal cport_out_rd_en,rport_out_rd_en:std_logic; + signal rdy:std_logic:='0'; --signal busy/ready + signal tosend,tosend4 :std_logic_vector(Word-1 downto 0); + signal PeerStat,PeerStat_i : std_logic_vector(15 downto 0):=(others=>'0'); --état des autres Lib initialisées + signal SpawnReq,SpawnReq_Q : std_logic_vector(15 downto 0):=(others=>'0'); --état des autres HT qui ont appelés le Spawn + signal Spawn_grp,Spawn_grp_Q :typ_mem16(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); --un max de quatre groupes de fils est prévu + signal Grp_id,grp_id_i :natural range 0 to 3:=0; --id du groupe des HT fils + signal selector : std_logic_vector (2 downto 0); -- pour le MUX des signaux vers le port + --signaux pour les états des MAE + signal NocSizeOk,PortCountFlag : std_logic; + signal PortNumFlag,PortNumFlag_i,EquFlag,EquFlag_i,MainResp: std_logic:='0'; + signal StatAsked,RankAsked,RankSent:std_logic; + signal nextr,nextr_i : natural :=0; + signal RTS_cmd,RTS_dat,RTS_I,CTR,BCast,Send_Ack,DS_Ack,CM_Ack:std_logic:='0'; + signal I_Send_Ack,I_Send_Rdy:std_logic:='0'; + signal Rcv_On,Snd_On,Cmd_On : std_logic:='0'; --status des MAE d'envoie et de réception + signal SpawnOn,SpawnInit :std_logic:='0'; --indique que le Spawn est activé + signal SpawnNbReq,SpawnNbAck,SpawnNBAck_i : natural range 0 to 15 :=0; --compte le nombre de requêtes et le nombre d'acquitement + signal SpawnNbReq_Q : natural range 0 to 15 :=0; --compte le nombre de requêtes et le nombre d'acquitement + signal SpawnCmd0,SpawnCmd1, SpawnCmd2 :std_logic_vector(Word-1 downto 0):=(others=>'0'); + signal SpawnCmd0_Q,SpawnCmd1_Q, SpawnCmd2_Q :std_logic_vector(Word-1 downto 0):=(others=>'0'); + signal SpawnDest :std_logic_vector(3 downto 0); + Signal Ht_Start,Ht_Start_i : natural range 0 to 15:=0; + Signal vPeerStat,vPeerStat_i : std_logic_vector(15 downto 0):=(others=>'0'); + signal IsMain_i,IsMain1,Initialized_i,HCL_init,HCL_Init_i: std_logic:='0'; + signal DS_RDY ,BCast_Rdy,Send_RDY,CM_RDY:std_logic:='0'; + signal ExecTime_out:std_logic; + --signaux de gestion de la RAM + signal Ram_Next_Address : std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_BASE_ADR+CORE_Rank2port_BASE,16)); + signal Ram_NExt_Address_i :std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_BASE_ADR+CORE_Rank2port_BASE,16)); + signal n,n_i:natural range 0 to 15 :=0; + signal n0,n0_i:natural range 0 to 7:=0; + signal DataToRam : std_logic_vector(Word-1 downto 0) ; + signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; + --Signaux des résultats et de l'état + signal PortNum_i,PortNum,MyPort : std_logic_vector(3 downto 0); -- + signal NocMax ,NocMax_i: std_logic_vector(3 downto 0):=(others=>'0'); -- Nombre de ports du réseau -1 ? + signal MyRank : std_logic_vector(3 downto 0) ; --rang du PE + signal AppSize_i,AppSize1:std_logic_vector(3 downto 0) ;--taille de l'application + signal Spawn_done,Spawn_done_i:std_logic:='0'; --indique que le Spawn a été effectué + signal MainPort,MainPort_i : std_logic_vector(3 downto 0) ; --Port de la lib main + signal NextRank,NextRank_i : std_logic_vector(3 downto 0):=(others=>'0'); --utiliser pour gérer les affectations de rangs MPI + signal Data_To_Send,Data_to_send_i : Typ_PortIo(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); -- permet d'empiler les données à envoyer + signal RankToPort :Typ_PortIo(0 to 15);--permet d'associer un port réseau à chaque rang + signal CmdReceived : Typ_PortIO(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); + signal DataReceived : Typ_PortIO(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); + signal Datalen,DataLen_i : natural range 0 to 7:=0; --indique la longueur des données + --other outputs + signal StatAsked_i,RankAsked_i,MainResp_i,RankSent_i,Result_i:std_logic:='0'; + signal snd_start_i:std_logic:='0';--version interne des signaux de sortie + --signal BCast_Rdy_i : std_logic; + signal cdlen,dcount : natural range 0 to 255:=0; --longueur du paquet reçu par le process pcmd + signal timeout,timeout_i : natural range 0 to 4095:=0; + signal PortStat,PortStat_i : std_logic_vector(3 downto 0):=(others=>'0'); + signal PeerPort,PeerPort_i : natural range 0 to 15:=0; -- désigne le port qui emet une requête + signal PeerRTS,PeerRTS_i,PeerCTR:std_logic:='0'; + signal cpt,cpt_peer : natural range 0 to 31:=0; --compteur pour le nombre de HT initialisés + signal clk_cyl,clk_cyl_i : natural range 0 to 15:=0; +begin +--======================================================================================= +--fonctions du module +--======================================================================================= +--======================================================================================= + +-- Inst_SetBit: SetBit PORT MAP( +-- clk => clk, +-- reset => reset , +-- ce => cmd, +-- BitNum => , +-- BitVal => '1', +-- dma_wr_grant => dma_wr_grant , +-- dma_wr_request => dma_wr_request, +-- dma_rd_grant => dma_rd_grant, +-- dma_rd_request => dma_rd_request, +-- ram_rd => ram_rd, +-- ram_wr => ram_wr, +-- ram_address => , +-- Ram_data_in => Ram_data_in, +-- Ram_data_out => Ram_data_out +-- ); + + + -- Gestion de l'initialisation du Core MPI + sync_Init2 : process (clk,reset) + begin + if reset='1' then + stinit2<=init; + StatAsked<='0'; + MyPort<=(others=>'0'); + NextRank<=(others =>'0'); + elsif rising_edge(clk) then + stinit2<=next_stinit2; + IS_State<=Next_IS_State; + n0<=n0_i; + --ajout des autres affectations ici + Ram_Next_Address<=Ram_Next_Address_i; + PortNumFlag<=PortNumFlag_i; + RankAsked<=RankAsked_i; + RankSent<=RankSent_i; + AppRank<=MyRank; + timeout<=timeout_i; + cpt<=cpt_peer; + clk_cyl<=clk_cyl_i; + NextRank<=NextRank_i; + StatAsked<=StatAsked_i; + MainResp<=MainResp_i; + AppSize1<=AppSize_i; + n<=n_i; + Ht_Start<=Ht_Start_i; + Grp_Id<=Grp_Id_i; + vPeerStat<=vPeerStat_i; + SpawnNbAck<=SpawnNbAck_i; + PortStat<=PortStat_i; + EquFlag<=EquFlag_i; + --IsMain1<=IsMain_i; + if ismain_i='1' then + IsMain1<='1'; + + else + IsMain1<=IsMain1; + end if; + if stInit2=DecodeData then + MyPort<=Cmdreceived(2)(3 downto 0); + end if; + + if stInit2=StoreRank and ExecTime_Out='1' then + MyRank<=MyPort; + elsif stInit2=StoreRank then + MyRank<=DataReceived(2)(3 downto 0); + elsif stInit2=SetMainFlag then + MyRank<=MyPort; + end if; + Ready<=Rdy; + snd_start<=snd_start_i; + SpawnNbReq_q<=SpawnNbReq; + SpawnReq_Q<=SpawnReq; + SpawnCmd0_Q<=SpawnCmd0; + SpawnCmd1_Q<=SpawnCmd1; + SpawnCmd2_Q<=SpawnCmd2; + Spawn_grp_q<=Spawn_grp; + PeerRTS<=PeerRTS_i; + PortNum<=PortNum_i; + Spawn_done<=Spawn_done_i; + HCL_init<=Hcl_init_i; + PeerStat<=PeerStat_i; + DataLen<=DataLen_i; + MainPort<=MainPort_i; + Nextr<=NextR_i; + NocMax<=NoCMax_i; + PeerPort<=PeerPort_i; + grp_id<=grp_id_i; + for i in 0 to 3 loop + data_to_send(i)<=data_to_send_i(i); + end loop; + end if; +end process; + +AppSize<=AppSize1; + + Init2_DECODE: process (stinit2,n, CmdReceived, EquFlag, MyPort, DS_RDY, MainResp, DataReceived, + SpawnOn,Ram_Next_Address,PeerRTS,PortSTAT,dma_rd,dma_wr,Send_rdy,I_Send_rdy,rd_ok,wr_ok,Instruction, + MainPort,PeerStat,SpawnCmd0,SpawnCmd1,SpawnCmd2,SpawnInit,BCast_rdy) + variable nextadr : natural :=0;--to_integer(unsigned(Ram_Next_Address)); + variable nport : natural range 0 to 15:=0; + begin + for i in 0 to 3 loop + data_to_send_i(i)<=data_to_send(i); + end loop; + PortNum_i<=PortNum; + PortNumFlag_i<=PortNumFlag; + PortID<=MyPort; + PeerPort_i<=PeerPort; + NocMax_i<=NoCMax; + NextRank_i<=NextRank; + MainPort_i<=MainPort; + PeerStat_i<=PeerStat; + EquFlag_i<=EquFlag; + RankAsked_i<=RankAsked; + NextR_i<=NextR; + Ram_Next_Address_i<=Ram_Next_Address; + Ram_address<=(others=>'1'); + Ram_data_in<=(others=>'1'); + dma_rd_request<='0'; + dma_wr_request<='0'; + Initialized_i<='0'; + rdy<='0'; + ram_rd<='0'; + ram_wr<='0'; + I_Send_ack<='0'; + IsMain_i<='0'; + send_ack<='0'; + DataLen_i<=0; + Case stInit2 is + When Init => + RTS_cmd<='0'; + --RTS_dat<='0'; + RTS_I<='0'; + BCast<='0'; + Result_En<='0'; + Initialized_i<='0'; + CM_Ack <='0'; + CTR<='0' ; + DS_ACK<='0'; + Send_Ack<='0'; + ram_wr<='0'; + rdy<='1';--le module est disponible + ResultOut<=(others=>'0'); + if PortNumFlag='1' and IsMain1='1' then + PortNum_i<=Instruction(3 downto 0); + else + PortNum_i<=(others=>'-'); + end if; + EquFlag_i<='0'; + RankAsked_i<='0'; + dma_wr_request<='0'; + dma_rd_request<='0'; + When GetPortNum => + RTS_cmd<='1'; + RTS_I<='0'; + + Result_En<='0'; + Initialized_i<='0'; + BCast<='0'; --réalise un envoie non collectif + CM_Ack<='0'; -- les données sont maintenant attendues + CTR<='0' ; + data_to_send_i(0)<=X"0" & GETPORTID; + DS_ACK<='0'; + Send_Ack<='0'; + ram_wr<='0'; + rdy<='0'; + IsMain_i<='0'; + ResultOut<=(others=>'0'); + PortNum_i<=(others=>'-'); + RankAsked_i<='0'; + dma_wr_request<='0'; + When DecodeData => + EquFlag_i<=(All_zeros(Cmdreceived(2)(3 downto 0))); + RTS_cmd<='0'; + RTS_I<='0'; + BCast<='0'; + + Result_En<='0'; + + CM_Ack <='1'; --les données ont été reçues + --MyPort<=Cmdreceived(2)(3 downto 0); + PortNum_i<=Cmdreceived(2)(3 downto 0); --récupère les valeurs de port + PeerPort_i<=To_integer(unsigned(Cmdreceived(2)(3 downto 0))); + NocMax_i<=Cmdreceived(2)(7 downto 4); -- et la taille du réseau + PortNumFlag_i<='1'; -- le numéro du port est maintenant connu + CTR<='0' ; + DS_ACK<='0'; + Send_Ack<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + When IsPortZero => --Ce port est-il le n° 0 du NoC ? + BCast<='0'; + Result_En<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + NextRank_i<="0001"; -- le prochain rang à affecter sera le n° 1 + nextr_i<=1; + IsMain_i<=EquFlag; + --MyRank<="0000"; + MainPort_i<="0000"; + --MainAdr<="0000"; -- le port 0 est le main Lib par défaut; + CTR<='0' ; + DS_ACK<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + When SeekMain1 => -- recherche de la lib main + RTS_cmd<='0'; + --RTS_DAT<='1'; + RTS_I<='1'; + CTR<='1' ; -- prêt à recevoir les données Clear To Receive + DS_ACK<='0'; --les données sont attendus + Send_Ack<=BCast_rdy; + I_Send_Ack<=BCAst_rdy; + data_to_send_i(0)<=MPI_INIT & MyPort ; + data_to_send_i(1)<="00000100"; -- la longueur du packet =4 + data_to_send_i(2)<="0000" & MyPort; --propose sa propre adresse + data_to_send_i(3)<=INIT_SEEKMAIN & MyPort ; + DataLen_i<=4; + BCast<='1'; + + Result_En<='0'; + Initialized_i<='0'; + ram_wr<='0'; + rdy<='0'; + ResultOut<=(others=>'0'); + RankAsked_i<='0'; + dma_wr_request<='0'; + When SeekMain2 => -- recherche de la lib main + RTS_cmd<='0'; + RTS_I<='0'; + CTR<='1' ; -- prêt à recevoir les données Clear To Receive + DS_ACK<= DS_RDY; --les données sont acquittées aussitôt reçues + Send_Ack<=BCast_rdy; +-- data_to_send_i(0)<=INIT_SEEKMAIN & MyPort ; +-- data_to_send_i(1)<="00000011"; -- la longueur du packet =3 +-- data_to_send_i(2)<="0000" & MyPort; --propose sa propre adresse +-- DataLen<=3; + BCast<='0'; + Result_En<='0'; + Initialized_i<='0'; + ram_wr<='0'; + rdy<='0'; + ResultOut<=(others=>'0'); + EquFlag_i<='0'; + RankAsked_i<='0'; + dma_wr_request<='0'; + When StoreMain => -- la Main Lib est une autre + BCAST<='0'; + Result_En<='0'; + IsMain_i<='0'; + Initialized_i<='0'; + DS_ACK<=DS_RDY; + Send_Ack<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<=not(MainResp); -- essayer de recevoir tant que le main n'a pas répondu + ram_wr<='1'; + rdy<='0'; + ResultOut<=(others=>'0'); + RankAsked_i<='0'; + EquFlag_i<='0'; + MainPort_i<=DataReceived(0)(3 downto 0); + ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16)); + ram_data_in<=DataReceived(0)(3 downto 0)& DataReceived(2)(3 downto 0); --MainPort & MyRank + dma_wr_request<= '0'; ---pas très sûr + + When AskPeerStat => -- Interroge les données d'initialisation + RTS_cmd<='0'; + if n=0 then + --RTS_DAT<='0'; --on peut envoyer les données + RTS_I<='1'; + else + --RTS_DAT<='0'; --on désactive l'envoie des données + RTS_I<='0'; + end if; + CTR<='0' ; -- prêt à recevoir les données Clear To Receive + DS_ACK<='0'; --les données sont attendus + I_Send_Ack<=I_Send_rdy; + Send_Ack<=Send_rdy; + data_to_send_i(0)<=MPI_INIT & MainPort ; + data_to_send_i(1)<="00000100"; -- la longueur du packet =4 + data_to_send_i(2)<="0000" & MyPort; --indique sa propre adresse + data_to_send_i(3)<=INIT_STAT & MyPort ; + DataLen_i<=4; + BCast<='0'; + Result_En<='0'; + ram_wr<='0'; + rdy<='0'; + ResultOut<=(others=>'0'); + EquFlag_i<='0'; + RankAsked_i<='0'; + dma_wr_request<='0'; + When SetMainFlag => -- Cette Lib est la Main Lib + if (Datareceived(3)(7 downto 4) = INIT_SEEKMAIN) then + RankAsked_i<='1'; + else + RankAsked_i<='0'; + end if; + RTS_cmd<='0'; + Initialized_i<='0'; + RTS_I<='0'; + BCast<='0'; + IsMain_i<='1'; + Result_En<='0'; + --MyRank<="0000"; + MainPort_i<="0000"; + PeerStat_i(0)<='1'; --la main lib est initialisée + CTR<='1'; + DS_ACK<='0'; + ram_wr<='1'; + rdy<='0'; + ResultOut<=(others=>'0'); + EquFlag_i<='0'; + ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16)); + ram_data_in<=(others =>'0'); -- le port vaut 0 et la mainlib est aussi à 0 + dma_wr_request<='1'; + When ReadNoc => + if (Datareceived(3)(7 downto 4) = INIT_SEEKMAIN) then + RankAsked_i<='1' ; + else + RankAsked_i<='0'; + end if; + ram_wr<='0'; -- pas d'écriture en RAM + rdy<='0'; + BCast<='0'; + DS_ACK<='0'; + --IsMain<='0'; + Result_En<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<='1'; + ResultOut<=(others=>'0'); + PortNum_i<=DataReceived(2)(3 downto 0); -- le port qui demande un rang; + PeerPort_i<= To_integer(unsigned(DataReceived(2)(3 downto 0))); + --EquFlag<='1'; + dma_wr_request<='0'; + When GetMainReq => + --RankAsked_i<='1'; + ram_wr<='0'; -- pas + BCast<='0'; + DS_ACK<='1'; + Result_En<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<='1'; + ResultOut<=(others=>'0'); + PortNum_i<=DataReceived(0)(3 downto 0); -- le port qui demande un rang; + EquFlag_i<='1'; + dma_wr_request<='0'; + When GetPeerStat => + --RankAsked_i<='1'; + ram_wr<='0'; -- pas + BCast<='0'; + DS_ACK<=DS_RDY; + Result_En<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<=not MainResp; + ResultOut<=(others=>'0'); + PortNum_i<=DataReceived(0)(3 downto 0); --adresse du Main Port + PeerStat_i(7 downto 0)<=DataReceived(2); -- état des initialisations + EquFlag_i<='0'; + dma_wr_request<=dma_wr; + ram_wr<=wr_ok; + rdy<='0'; + ram_rd<=rd_ok; + Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_Init_Adr+2,ADRLEN)); --incr_vec(Ram_Next_Address,'1'); + ram_address<=Ram_Next_Address; -- + ram_data_in<=DataReceived(2); --enregistrer les ports actifs + + When NewRank => + nport:=to_integer(Unsigned(PortNum)); --port ayant sollicité le rang + nextr_i<=to_integer(unsigned(nextrank)); + if PeerStat(nport)='0' then -- si le rang n'a pas encore été affecté à ce port + nextrank_i<=incr_vec(nextrank,'1'); + RankToPort(to_integer(unsigned(nextrank)))<="0000" & PortNum; + NextAdr:=NextAdr+1; + end if; + data_to_send_i(0)<=MPI_INIT & PortNum ; + data_to_send_i(1)<="00000100"; + data_to_send_i(2)<="0000" & NextRank; --ici c'est la valeur avant incrémentation ! + data_to_send_i(3)<=INIT_SETRANK & PortNum ; + PeerStat_i(nport)<='1'; -- mise à jour du status + DataLen_i<=4; + BCast<='0'; + DS_ACK<='0'; + Result_En<='0'; + EquFlag_i<='1'; + RTS_cmd<='0'; + RTS_I<='1'; + CTR<='0' ; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='1'; + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + + When SendRank => + BCast<='0'; + Result_En<='0'; + EquFlag_i<='1'; + + RTS_I<='1'; + DataLen_i<=4; + RTS_cmd<='0'; + DS_ACK<='0'; + Send_Ack<='0'; + CTR<='0' ; + ram_wr<='0'; + Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_RANK_ADR+Nextr-1,16)); + ResultOut<=(others=>'0'); + RankAsked_i<='1'; + dma_wr_request<='0'; + When RegRank => + RankAsked_i<='0'; + + CTR<='1' ; -- continuer à recevoir les données du NoC + Result_En<='0'; + RTS_cmd<='0'; + DS_ACK<='0'; + Send_Ack<=Send_RDY; + I_Send_ack<=i_send_rdy; + Rts_I<='0'; + BCast<='0'; + EquFlag_i<='1'; + ram_wr<='1'; + + Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_RANK_ADR+Nextr-1,16)); --incr_vec(Ram_Next_Address,'1'); + ram_address<=Ram_Next_Address; -- le rang qui a été envoyé; + -- "le motif 0001 indique juste que le port est bien activé + ram_data_in<="0001" & PortNum; --enregistrer le port qui a fait la demande en RAM + ResultOut<=(others=>'0'); + dma_wr_request<='1'; + When SendPeerStat => + BCast<='0'; + Result_En<='0'; + EquFlag_i<='0'; + RTS_I<=PeerRTS; + RTS_cmd<='0'; + DS_ACK<='0'; + data_to_send_i(0)<=MPI_INIT & PortStat ; + data_to_send_i(1)<="00000100"; + data_to_send_i(2)<=PeerStat(7 downto 0); + data_to_send_i(3)<=INIT_REGISTER & MyPort ; + Send_Ack<=Send_Rdy; + I_Send_Ack<=I_Send_Rdy; + CTR<='0' ; + ram_wr<='0'; + rdy<='0'; + ResultOut<=(others=>'0'); + RankAsked_i<='1'; + dma_wr_request<='0'; + Initialized_i<='1'; + When StoreRank => --le processus qui écoute le Port et qui + --stoke les adresses des autres bib va gérer le stockage du rang + BCAST<='0'; + DS_ACK<='1'; + Send_Ack<='0'; + RTS_cmd<='0'; + EquFlag_i<='0'; + RTS_I<='0'; + CTR<='0'; + Result_En<='0'; + + if ExecTime_out='1' then + MainPort_i<="0000"; + --MyRank<=MyPort; + initialized_i<='0'; + else + MainPort_i<=DataReceived(0)(3 downto 0); + --MyRank<=DataReceived(2)(3 downto 0); + Initialized_i<='1'; + end if; + ram_wr<='1'; + --ram_address<=DataReceived(2); -- le rang qui a été envoyé; + ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16)); + ram_data_in<=DataReceived(0)(3 downto 0)& DataReceived(2)(3 downto 0); --MainPort & MyRank + ResultOut<=(others=>'0'); + RankAsked_i<='0'; + dma_wr_request<='1'; + When SendApp => --ajouter du code pour recevoir l'adr du reg status + Initialized_i<='1'; + ResultOut<="00000001"; -- Init Ok + Result_En<='1'; + PortId<=MyPort; + BCAST<='0'; + DS_ACK<='1'; + Send_Ack<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + dma_wr_request<='0'; + When SpawnApp => + RTS_cmd<='0'; + RTS_I<='0'; + Result_En<='0'; + DS_ACK<=DS_RDY; + BCAST<='0'; + CTR<='0'; --cette mise à 1 permet de ctrler la fin de réception + rdy<='0'; + ram_wr<=wr_ok; + ram_rd<=rd_ok; + Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_BASE_ADR,ADRLEN)); --incr_vec(Ram_Next_Address,'1'); + ram_address<=Ram_Next_Address; -- le rang qui a été envoyé; + -- "le motif 0001 indique juste que le port est bien activé + ram_data_in<=DataToRam; --enregistrer le port qui a fait la demande en RAM + dma_rd_request <= dma_rd; + dma_wr_request <=dma_wr; + RankAsked_i<='0'; + if n>=3 then + ResultOut<=("00000010");--spawn completed + else + ResultOut<=("00000000");--spawn message received + end if; + + When SpawnLoad => + RTS_cmd<='0'; + --RTS_DAT<='1'; --à tester + RTS_I<=PeerRTS; -- pour le timing + Result_En<='0'; + DS_ACK<='0'; + BCAST<='0'; + CTR<='0'; + rdy<='0'; + ram_wr<=wr_ok; + ram_rd<=rd_ok; + data_to_send_i(0)<=SpawnCmd0; + data_to_send_i(1)<="00000100"; + data_to_send_i(2)<=SpawnCmd1; + data_to_send_i(3)<=SpawnCmd2; -- SPAWN_LOAD & MyPort ; + Send_Ack<=Send_Rdy; + I_Send_Ack<=I_Send_rdy; + RankAsked_i<='0'; + if SpawnInit='1' then + ResultOut<=("10000000"); --spawn completed + else + ResultOut<=("01000000");--spawn in progress + end if; + When ErrSpawn => + RTS_cmd<='0'; + RTS_I<='0'; + Result_En<='1'; + DS_ACK<='0'; + Send_Ack<='0'; + BCAST<='0'; + CTR<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + dma_rd_request<='0'; + When EndInit => + RTS_cmd<='0'; + RTS_I<='0'; + Result_En<='0'; + DS_ACK<='0'; + Send_Ack<='0'; + BCAST<='0'; + CTR<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + dma_rd_request<='0'; + end case; + end process; + +result_proc:process (ISMain_i,Initialized_i,stInit2,reset) +begin +if reset='1' then + --IsMain1<='0'; + Initialized<='0'; + HCL_Init_i<='0'; + +Else + HCL_init_i<=HCl_init; + Initialized<=Hcl_init; +-- if ismain_i='1' then +-- IsMain1<='1'; +-- end if; + + if Initialized_i='1' and stInit2=EndInit then + Initialized<='1'; + HCL_Init_i<='1'; + elsif stInit2=SendApp then + HCL_Init_i<='1'; + end if; +end if; +end process result_proc; + --================ + --Traitement du Spawn + --=================== + + --================== + NEXT_STInit2_DECODE: process (stInit2,AppReq,Instruction_en, AppAck,PortNumFlag,EquFlag,MainResp,StatAsked,RankAsked,RankSent,CM_RDY, CmdReceived, + BCast_Rdy, DS_RDY, DataReceived,Ht_Start,vPeerStat, Send_RDY, I_Send_RDY,TimeOut,Dma_rd_grant,Dma_wr_grant,cpt,n,clk_cyl,IsMain1,SpawnOn, + Instruction,Hcl_Init,Spawn_done,mainport,PeerStat,PeerRTS,Rec_Data,SpawnInit,grp_id,SpawnNbReq,Ram_data_out,Spawn_grp,MyPort) + variable InitTimeOut :natural:=0; + variable LastPort,Ht_hole : std_logic:='0'; + variable i,nbSpawn,htloc,Ht_Id : natural range 0 to 15:=0; + --variable vPeerStat : std_logic_vector(15 downto 0); + variable vPortStat,nulvect : std_logic_vector(3 downto 0):="0000"; + variable tempval : std_logic_vector(Word-1 downto 0); + begin + --declare default state for next_state to avoid latches + next_stInit2 <= stInit2; --default is to stay in current state + --insert statements to decode next_state + --below is a simple example + vPeerStat_i<=vPeerStat; + SpawnNbReq<=SpawnNbReq_q; + StatAsked_i<=StatAsked; + MainResp_i<=MainResp; + AppSize_i<=AppSize1; + PortStat_i<=PortStat; + grp_id_i<=grp_id; + PeerRTS_i<=PeerRTS; + --PortNumFlag_i<=PortNumFlag; + SpawnReq<=SpawnReq_q; + Spawn_done_i<=Spawn_done; + Ht_Start_i<=Ht_Start; + SpawnCmd0<=SpawnCmd0_Q; + SpawnCmd1<=SpawnCmd1_Q; + SpawnCmd2<=SpawnCmd2_Q; + Timeout_i<=Timeout; + clk_cyl_i<=clk_cyl; + n_i<=n; + Cpt_peer<=cpt; + DataToRam<=(others=>'0');--A revoir + dma_rd<='0'; + dma_wr<='0'; + rd_ok<='0'; + wr_ok<='0'; + for i in 0 to 3 loop + Spawn_grp(i)<=Spawn_grp_q(i); + end loop; + case (stInit2) is + + + When Init =>If Instruction_en='1' and AppReq='1' then + If PortNumFlag='1' and IsMain1='1' then + if instruction(7 downto 4)=INIT_SEEKMAIN and (instruction(3 downto 0)/=MyRank) then + Next_stInit2 <=NewRank;--affecter un rang au demandeur. + elsif instruction(7 downto 4)=INIT_STAT then + StatASked_i<='1'; + Next_stInit2 <=SendPeerStat; --envoyer des stat au demandeur + elsif instruction(7 downto 4)=SPAWN_LOAD then + SpawnInit<='0'; -- indique le debut du Spawn + Next_stInit2 <=SpawnLoad; + elsif instruction(7 downto 4)=INIT_SPAWN then + SpawnInit<='1'; -- indique la fin du + Next_stInit2 <=SpawnLoad; --dans ce cas il s'agit de terminer le spawn + else --ignorer ce message + Next_stInit2 <=SendApp; + end if; + elsif HCL_Init='1' and IsMain1='0' then + Next_stInit2 <=SendApp; --ignorer ce message simplement + else + Next_stInit2 <=GetPortNum; -- initialiser la bibliothèque normalement + end if; + TimeOut_i<=0;PeerRTS_i<='0'; + + elsif SpawnOn='1' and Spawn_done='0' then + Next_stInit2 <=SpawnApp; + TimeOut_i<=0; + end if; + cpt_peer<=0;LastPort:='0';n_i<=0; + When GetPortNum => -- récupérer le numéro du port + + if CM_RDY='1' then + Next_stInit2 <=DecodeData; + end if; + + When DecodeData => -- cet état permet de lire les données reçues du port + --if CM_RDY='1' then + if ((Cmdreceived(2)(3 downto 0) or nulvect)=nulvect) then -- teste si le n° du port est zero + --EquFlag<='1'; + else + --EquFlag<='0'; + end if; + + Next_stInit2 <=IsPortZero; + --end if; + When IsPortZero => + if PortNumFlag='1' then + + End if; + if EquFlag='0' then --tester le numéro de port obtenu + Next_stInit2 <=SeekMain1; -- chercher le numéro de port sur le réseau + else + Next_stInit2<=SetMainFlag; -- enregistrer le numéro de port + End If; + TimeOut_i<=0; + + When SeekMain1 =>If BCast_RDY='1' then -- si tous les envois ont été postés + Next_stInit2<=SeekMain2; + End if; + When SeekMain2 => + If DS_RDY='1' then -- Si un jeu de données a été reçu + if (Datareceived(3)(7 downto 4) = INIT_SETRANK) then + MainResp_i<='1'; + Next_stInit2 <=StoreMain; -- de la librairie pricipale + else + MainResp_i<='0'; + Timeout_i<=0; + end if; + + elsif (ExecTime_Out='1') then + + -- le Noc ne répond pas + -- affecter un numéro en raport avec le port + Next_stInit2 <=SeekMain2; + elsif TimeOut=800 then + --essayer de redemander l'initialisation + assert true report "Ex4:seekmain ->redemander l'initialisation" + severity failure; + Timeout_i<=0; + Next_stInit2 <=SeekMain1; + else + Timeout_i<=TimeOut+1; + End if; + + + + When StoreMain => + if DataReceived(3)(7 downto 4)= INIT_SETRANK then + -- enregistrer le Main Adresse et les adresses des autres processus + -- dans la variable prévue à cet effet + Next_stInit2 <=StoreRank; + + elsif Datareceived(3)(7 downto 4) = INIT_SEEKMAIN then + -- ignorer ce message + Next_stInit2 <=StoreMain; --essayer de recevoir le rang + + + end if; + + When StoreRank => + --il faut prévoir du code pour s'assurer que la RAM a bien enregistrer + -- la donnée ... + if dma_wr_grant = '1' then + if clk_cyl=2 then --prévoir deux cycle d'horloge pour lire en RAM + Next_stInit2 <=AskPeerStat; + TimeOut_i<=0; + clk_cyl_i<=0; + else + clk_cyl_i<=clk_cyl+1; + end if; + else + Next_stInit2 <=StoreRank; + TimeOut_i<=0; + clk_cyl_i<=0; + end if; + When AskPeerStat =>if n=0 then + If I_SEND_RDY='1' then -- si tous les envois ont été postés + n_i<=1; + StatAsked_i<='0'; + End if; + elsif n=1 then + If I_SEND_RDY='0' then -- si tous les envois ont été postés + Next_stInit2<=GetPeerStat; + StatAsked_i<='1'; + MainResp_i<='0'; + n_i<=0; + End if; + end if; + When GetPeerStat => + if n=0 then + If DS_RDY='1' then -- Si un jeu de données a été reçu + if (Datareceived(3) = INIT_REGISTER & MainPort ) then + MainResp_i<='1'; + n_i<=n+1; + + else + MainResp_i<='0'; + Timeout_i<=0; + n_i<=n; + end if; + + elsif TimeOut=1800 then + --essayer de redemander les statistiques + assert true report "Ex4:GetPeerStat timeout ->Les statistiques n'ont pas été reçu" + severity failure; + Timeout_i<=0; + If StatAsked='1' then + Next_stInit2 <=AskPeerStat; -- ceci n'est pas sûr + else + Next_stInit2 <=GetPeerStat; + end if; + else + Timeout_i<=TimeOut+1; + End if; + elsif n=1 then --écrire le résultat de l'initialisation + dma_wr<='1'; + if dma_wr_grant='1' then + n_i<=n+1; + wr_ok<='1'; + end if; + elsif n=2 then + n_i<=n+1; --écriture dans la RAM + elsif n=3 then + n_i<=0; + dma_wr<='0'; + Next_stInit2 <=SendApp; -- de la librairie pricipale + end if; + When SetMainFlag => + if dma_wr_grant='1' then + TimeOut_i<=0; + Next_stInit2 <=ReadNoc; + elsif Timeout=800 then + assert true report "Ex4:SetMainFlag timeout ->La mémoire n'est pas dispo dma_wr_grant=0" + severity failure; + Next_stInit2 <=SendApp; + else + TimeOut_i<=TimeOut+1; +-- end if; -- il est envisagée de terminer le programme à ce point + end if; + when ReadNoc => if DS_RDY='1' then + if (Datareceived(3)(7 downto 4) = INIT_STAT) then + StatAsked_i<='1' ; + Next_stInit2 <=SendPeerStat; + LastPort:='0'; + else + StatAsked_i<='0'; + Next_stInit2 <=GetMainReq; + end if; + + Timeout_i<=0; + elsif Timeout=400 then + assert true report "Ex4:ReadNoc timeout pas de données lues sur le NoC après 200 cycles" + severity failure; + Timeout_i<=0; + --if StatAsked = '1' then + --Next_stInit2 <=ErrSpawn; --il y a eu une erreur + Next_stInit2 <=SendApp; + -- else + -- Next_stInit2 <=SendPeerStat; + -- end if; + else + TimeOut_i<=TimeOut+1; + end if; + + When GetMainReq => if RankAsked='1' and PeerStat(PeerPort)='0' then + Next_stInit2 <=NewRank; -- un nouveau rang est demandé + else + Next_stInit2 <=ReadNoC; -- sinon essayer encore de lire un jeu de données. + end if; + When NewRank => + Next_stInit2 <=SendRank; + When SendRank => + if I_Send_RDY='1' then --RankSent + Next_stInit2 <=RegRank; + RankSent_i<='1'; -- le rang a été envoyé + TimeOut_i<=0; -- prépare le traitement de la prochaine requête + -- d'attente des ports + elsif Timeout=800 then + assert true report "Impossible d'envoyer le rang" + severity failure; + timeout_i<=0; + else + TimeOut_i<=TimeOut+1; + end if; + When RegRank => + --il faut prévoir du code pour s'assurer que la RAM a bien enregistrer + -- la donnée ... + if dma_wr_grant = '1' then +-- if DS_RDY='1' then + RankSent_i<='0'; + if DS_RDY='0' then + + Next_stInit2 <=ReadNoc; + end if; + elsif Timeout=800 then + Next_stInit2 <=SendApp; + assert true report "Ex4:RegRank Timeout dma_wr_grant=0 " + severity failure; + else + TimeOut_i<=TimeOut+1; +-- end if; -- il est envisagée + end if; + --calcul de la taille de l'appli + HtLoc:=0; + for i in 0 to 7 loop + if peerStat(i)='1' then --trouve le prochai rang libre + HtLoc:=HtLoc+1; + end if; + end loop; + AppSize_i<=std_logic_vector(to_unsigned(HtLoc,4)); + + When SendPeerStat => + + if cpt<=unsigned(NoCMax)and LastPort='0' then + if peerRts='0' then -- pas encore envoyer les données alors les préparer + if StatAsked='1' then + + PortStat_i<=PortNum; + vPortStat:=std_logic_vector(to_unsigned(PeerPort,4)); + else + PortStat_i<=std_logic_vector(to_unsigned(cpt,4));--Port à contacter + vPortStat:=std_logic_vector(to_unsigned(cpt,4)); + end if; + + if StatAsked='1' then + LastPort:='1'; -- on traite u seul port celui qui en a fait la demande + if PeerStat(PeerPort)='1' then + PeerRts_i<='1'; + end if; + else + if (PeerStat(cpt)='1') and not(vPortStat=MyPort) then + PeerRts_i<='1'; + end if; + if cpt Impossible d'envoyer sur le NoC" + severity failure; + else + TimeOut_i<=TimeOut+1; + end if; + end if; + elsif PeerRTS='1' then -- le dernier port est il activé ? + if I_Send_RDY='1' then + RankSent_i<='1'; -- les stat ont été envoyé + TimeOut_i<=0; -- prépare le traitement de la prochaine requête + PeerRts_i<='0'; + if statAsked='1' then + -- Next_stInit2<=ReadNoc; + + Next_stInit2<=SendApp; --terminer l'application + end if; + + elsif TimeOut=100 then + Next_stInit2 <=EndInit; + assert true report "Ex4:SendPeerStat Timeout -> Impossible d'envoyer sur le NoC" + severity failure; + else + TimeOut_i<=TimeOut+1; + end if; + else + Next_stInit2<=SendApp; + end if; + When SendApp => -- envoyer au programme un signal + -- et attendre un acquittement et l'adresse de base + If AppAck='1' then + Next_stInit2 <=EndInit; + end if; + + When SpawnLoad => + + if n=0 then + ht_id:=to_integer(unsigned(rec_data(0)(3 downto 0))); + vPeerStat_i<=PeerStat; --récupérer la situation actuelle des tâches créées + if IsMain1='1' and SpawnInit='0' then + SpawnNbReq<=to_integer(unsigned(Instruction(3 downto 0))); -- sauver le nombre de HT à créer + + n_i<=1; + SpawnReq(ht_id)<='1'; --Note l'id de HT qui a appelé le Spawn + elsif IsMain1='1' and SpawnInit='1' then -- il faut envoyer les acquittements + ht_id:=to_integer(unsigned(rec_data(0)(3 downto 0))); + Spawn_grp(grp_id)(ht_id)<='1'; --noter le port du Fils Spawné dans ce groupe + Ht_start_i<=0; --compte le nombre de tâches chargées + n_i<=6; + + else + if SpawnOn='1' then --if IsMain_i='0' then -- il faut juste charger puis activer la tâche + n_i<=7; + end if; + assert true + Report "SpawnLoad : Cas non prévu !" + severity failure; + end if; + elsif n=1 then + if PeerStat=SpawnReq then --tous les Hts ont appelés Spawn ? + ht_hole:='0'; + L1: for i in 0 to 15 loop + if vPeerStat(i)='0' then + SpawnDest<=std_logic_vector(to_unsigned(i,4)); -- le port à activer + SpawnCmd0<=MPI_SPAWN & std_logic_vector(to_unsigned(i,4)); + vPeerStat_i(i)<='1'; + Ht_Start_i<=Ht_Start+1; + Ht_Hole:='1'; -- une place a été trouvé + else + Ht_hole:='0'; -- pas de place trouvé + end if; + exit L1 when ht_hole='1'; + end loop L1; + if Ht_hole='0' then -- toutes les tâches n'ont pas été créés + -- aller à la fin ! en signalant une erreur! + SpawnCMd2<=Spawn_Err & "0001"; --erreur pas assez de ports sur le NoC + n_i<=9; + else + n_i<=n+1; + SpawnCmd1<=PeerStat(7 downto 0); + SpawnCmd2<=SPAWN_START & MyPort; + end if; + else --Tous les Hts n'ont pas appelé Spawn encore + Next_stInit2<=SendApp; --on termine normalement + n_i<=0; + end if; + elsif n=2 then + PeerRTS_i<='1'; -- envoyer les données du Spawn + n_i<=n+1; + elsif n=3 then + if I_Send_RDy='1' then + n_i<=n+1; + PeerRts_i<='0'; + end if; + elsif n=4 then + if SpawnInit='0' then + if Ht_Start>=SpawnNbReq then + n_i<=n+1; + else + n_i<=1; -- passer à la création du HT suivant + end if; + else + n_i<=7; -- passer au contact du HT suivant + end if; + elsif n=5 then + -- Aller à la fin le résultat du Spawn + + n_i<=10; + elsif n=6 then + nbSpawn:=0; + for i in 0 to 15 loop + if Spawn_grp(grp_id)(i)='1' then + nbSpawn:=nbSpawn+1; + end if; + end loop; + if nbSpawn=SpawnNbReq then + n_i<=n+1; --aller renvoyer les réponses + else + n_i<=10; --fin du Spawn + + end if; + elsif n=7 then + Ht_hole:='0'; +L2: for i in 0 to 7 loop --for i in Ht_start to 7 loop + if i>=Ht_start then + if vPeerStat(i)='1' and Spawn_grp(grp_id)(i)='0' then --on avertit les membres du groupe parent + --mais pas ceux du groupe Fils ! + SpawnDest<=std_logic_vector(to_unsigned(i,4)); -- le port à avertir + SpawnCmd0<=MPI_ACK & std_logic_vector(to_unsigned(i,4)); + vPeerStat_i(i)<='0'; + Ht_Start_i<=i+1; -- le prochain Ht à prévenir + Ht_Hole:='1'; -- Une tâche doit être avertie + else + Ht_hole:='0'; -- + end if; + end if; + exit L2 when ht_hole='1'; + end loop L2; + n_i<=n+1; + elsif n=8 then + if Ht_hole='1' then -- + -- un HT existant à prévenir ! + SpawnCmd1<=Spawn_grp(grp_id)(7 downto 0); + SpawnCMd2<=MPI_SPAWN & MyRank; -- fin du Spawn + n_i<=2; --envoyer la donnée sur le réseau + elsif vpeerstat /=spawn_grp(grp_id) then --il ne reste plus de membres à prévenir ? + n_i<=7; --on est sorti mais ce n'est pas la fin + + else -- fin du Spawn car tous ont été averti + n_i<=10; + SpawnNbReq<=0; + SpawnReq<=(others=>'0'); + vPeerStat_i<=(others=>'0'); + grp_id_i<=grp_id+1; --incrementer le compteur de groupes************ + end if; + elsif n=9 then + assert true report "error in Spawn command" + severity failure; + elsif n=10 then + n_i<=0; + Next_stInit2<=SendApp; + end if; + + When SpawnApp=> + --Mise à jour du bit 6 du registre status du COre. + if n>=0 and n <4 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + + if n=0 then + if DS_RDY='1' then --- + if Datareceived(3)(7 downto 4)=SPAWN_START then + n_i<=n+1; + else + Next_stInit2<=ErrSpawn; + n_i<=0; --erreur instruction incorrecte + end if; + + rd_ok<='1'; + wr_ok<='0'; + end if; + elsif n=1 or n=2 then + if dma_rd_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + end if; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=3 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + tempval(6):='1'; + + dataToram<=tempval; + rd_ok<='0'; + wr_ok<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + end if; + elsif n=4 then + if spawninit='0' then + Spawn_done_i<='1'; + end if; + rd_ok<='0'; + wr_ok<='0'; + n_i<=0; + Next_stInit2<=EndInit; + end if; + + When ErrSpawn => + assert true + report "Ex4/stInit2/SpawnApp:Erreur lors de Spawn" + severity failure; + Next_stInit2<=Init; + When EndInit=> + + StatAsked_i<='0'; --reset de ces variables + Next_stInit2<=Init; + end case; + end process; + +--================================================ +--sauvegarde du rang et du main port à l'adresse de retour de la fonction Init +--================================================== + +--==================================================== +--envoie des données sur le port +--=================================================== +selector<=(Rcv_on,Cmd_on,Snd_on); + +process (selector,Rport_out_rd_en,cport_out_rd_en,sPort_in_wr_en ,cPort_in_wr_en, + tosend ,tosend4) +begin + case selector is + + when "000" => port_in_data<=(others=>'-'); + Port_in_wr_en<='0'; + Port_out_rd_en<='0'; + + when "001" => port_in_data<=tosend; --envoie de données + Port_in_wr_en<=sPort_in_wr_en ; + Port_out_rd_en<='0'; + when "101" => port_in_data<=tosend; --envoie de données + Port_in_wr_en<=sPort_in_wr_en ; + Port_out_rd_en<=Rport_out_rd_en ; + when "010" | "110" | "011" | "111" => + port_in_data<=tosend4; --envoie de commande GetPort + Port_in_wr_en<=cPort_in_wr_en; + Port_out_rd_en<=cport_out_rd_en; + + when "100" => port_in_data<=(others=>'-'); -- réception de données + Port_in_wr_en<='0'; + Port_out_rd_en<=Rport_out_rd_en ; + + when others => port_in_data<=(others=>'-'); + Port_in_wr_en<='0'; + Port_out_rd_en<='0'; + end case; +end process; + +--================================================== + + --=============================================================== + --processus d'accès au réseau + --=============================================================== + + + + + + preceiv:process(clk,reset) + + variable origport,destport : natural range 0 to 15; + variable dcount,dlen ,rtimeout:natural range 0 to 1023; + variable ptype : std_logic_vector(3 downto 0); + variable bad_paquet :std_logic:='0'; + begin +-- + + if reset='1' then + etrec<=r_wait; + destport:=1; + rtimeout:=0; + bad_paquet:='0'; + else + if rising_edge(clk) then + case etrec is + when r_wait => + + rtimeout:=0; + bad_paquet:='0'; + --modifier le 01-08-pour gérer le Spawn + if Port_out_data_available='1' and Cmd_on='0' then + ptype:=port_out_data(7 downto 4); + origport:=to_integer(unsigned(port_out_data(3 downto 0))); + + if ptype=MPI_SPAWN and not(portnumflag='1') then + etrec<=r_dlen; --identification de la signature d'en tête valide + Datareceived(0)<=Port_out_data; --stocker l'entête + bad_paquet:='0'; + SpawnOn<='1'; --le spawn est actif + elsif Instruction_en='0' and CTR='0' and Hcl_init= '0' then + --il faut éliminer ce paquet qui est inoportun ! + Bad_paquet:='1'; + etrec<=r_dlen; --il faut ignorer cette donnée et quitter + dcount:=1; + elsif CTR='1' then + if ptype=MPI_INIT or ptype=INIT_SETRANK or ptype=INIT_SEEKMAIN or ptype=INIT_REGISTER then + etrec<=r_dlen; --identification de la signature d'en tête valide + Datareceived(0)<=Port_out_data; --stocker l'entête + bad_paquet:='0'; + else + --une donnée non attendue est présente sur le port + etrec<=r_dlen; --il faut ignorer cette donnée et quitter + dcount:=1; + bad_paquet:='1'; + Datareceived(0)<=(others=>'0'); + end if; + end if; + --elsif Port_out_data_available='1' and CTR='0' then + -- etrec<=r_drop; + else + + etrec<=r_wait; + end if; + DS_RDY<='0'; + When r_drop => -- ignorer les messages qui arrivent à ce noeud tant que + --l'application n'a pas été initialisée + if port_out_data_available='0' then + etrec<=r_end; + dcount:=0; + + end if; + + + + --Rport_out_rd_en<='1'; --lire les données qui sont dans le tampon de sortie + DS_RDY<='0'; + when r_Dlen => --positionnement du mot de longueur des données + if Port_out_data_available ='1' then + + --Rport_out_rd_en<='1'; + etrec<=r_glen; + rtimeout:=0; + else + rtimeout:=rtimeout+1; + if rtimeout>=30 then + assert true report "Ex4:etrec r_glen Timeout -> Impossible de recevoir du NoC" + severity failure; + Exectime_out<='0'; --read Noc time out + etrec<=r_end; -- données pas prêtes + end if; + + + end if; + DS_RDY<='0'; + -- + when r_glen => --lecture effective de la longueur des données + if port_out_data_available='1' then + dlen:=to_integer(unsigned(port_out_data(Word-1 downto 0))); + Datareceived(1)<=Port_out_data; + --RPort_out_rd_en<='0'; + etrec<=r_data; + dcount:=2; -- initialisation du compteur de reception (il y a + -- déjà deux mots reçues + else + rtimeout:=rtimeout+1; + if rtimeout>=30 then + assert true report "Ex4:etrec Timeout -> Impossible de recevoir sur le NoC" + severity failure; + ExecTime_out<='0'; + etrec<=r_end; -- données pas prêtes + end if; + + end if; + DS_RDY<='0'; + when r_data => -- lecture des données + if port_out_data_available='1' then + + --Rport_out_rd_en<='1'; --autoriser la lecture + if bad_paquet='0' then + DataReceived(dcount)<=Port_out_data; --récupération des données + else + DataReceived(2)<=(others=>'0'); + --ignorer ces données + end if; + --assert true report "Donnée lue :"; --& string(unsigned(port4_out(Word-1 downto 0))) + DS_RDY<='0'; + dcount:=dcount+1; + --severity note; + if dlen <=dcount then -- ce doit être égale ici et non <= ??? + etrec<=r_end; + DS_RDY<= not bad_paquet; -- jeu de données disponibles + elsif dcount=255 then --dépassement de la capacité + DS_RDY<='0'; + etrec<=r_end; + end if; + else + rtimeout:=rtimeout+1; + if rtimeout>=30 then + ExecTime_out<='0'; + etrec<=r_end; -- données pas prêtes + end if; + DS_RDY<='0'; + + end if; + when r_pulse => + etrec<=r_end; + DS_RDY<=not bad_paquet; + when r_end => + + --rPort_out_rd_en <='0'; + + if DS_ACK='1' or rtimeout> 30 or (CTR='0' and SpawnOn='0') or bad_paquet='1' then + DS_RDY<='0'; + SpawnOn<='0'; + etrec<=r_wait; + else + DS_RDY<=DS_RDY; + end if; + end case; + end if;--reset='1' + end if; + end process preceiv; + + val_preceiv: process (etrec) + begin + case etrec is + when r_wait => +-- DS_RDY<='0'; + rcv_on<='0'; + Rport_out_rd_en <='0'; + when r_dlen => +-- DS_RDY<='0'; + Rport_out_rd_en <='1'; + rcv_On<='1'; + when r_drop => +-- DS_RDY<='0'; + Rport_out_rd_en <='1'; + rcv_On<='1'; + when r_glen => + Rport_out_rd_en <='1'; +-- DS_RDY<='0'; + rcv_On<='1'; + when r_data => + Rport_out_rd_en <='1'; +-- DS_RDY<='0'; + rcv_On<='1'; + when r_pulse => + Rport_out_rd_en <='0'; + rcv_On<='1'; +-- DS_RDY<='1'; + when r_end => + Rport_out_rd_en <='0'; +-- DS_RDY<='0'; + rcv_On<='0'; + when others => + Rport_out_rd_en <='0'; +-- DS_RDY<='0'; + rcv_On<='0'; + end case; + end process; + + psend:process(clk,reset) + --génération des paquets à partir du port courant + variable pactype :natural range 0 to 15; + variable destport : natural range 0 to 15:=0; + variable realdlen, i,i_pair : natural range 0 to 255; + variable MaxPort : natural :=4; -- en fait ne doit pas être 0 + + + begin + if rising_edge(clk) then + if reset='1' then + etsnd<=s_init; + + + + else -- le process s'exécute sur chaque front + -- montant de l'horloge + case etsnd is + when s_init => tosend<=(others=>'-'); + MaxPort :=to_integer(unsigned(NOCMAX)); + sPort_in_wr_en<='0'; + if port_in_full='0' and Rts_dat='1' then --on peut aussi tester si le port est vide + BCast_RDY<='0'; -- pas la fin de du Broadcasting + Send_RDY<='0'; + Snd_on<='1'; + if Bcast='1' then -- envoyer à tous les ports le même message ? + DestPort :=0; + else + DestPort:=to_integer(unsigned(data_to_send(0)(3 downto 0))); + end if; + etsnd<=s_head; + end if; + when s_head => -- construction et envoie de l'en-tête + Send_RDY<='0'; --l'envoi commence + BCast_RDY<='0'; + Snd_on<='1'; + --pactype:=to_integer(MPI_INIT);-- + pactype:=to_integer(unsigned(data_to_send(0)(7 downto 4))); + --realdlen:=to_integer(unsigned(Datalen)); + --? destport:=MAXPORT; -- le port de destination + + tosend <=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4)); + sPort_in_wr_en<='1'; -- + + i:=1; + etsnd<=s_len2; -- passer à l'état suivant + + when s_len => + BCast_RDY<='0'; + Send_RDY<='0'; + Snd_on<='1'; + --tosend<=(STD_LOGIC_VECTOR(to_unsigned(Realdlen,8))); + tosend<=data_to_send(1); + sPort_in_wr_en <='1'; + + + --port1_in<=tosend1; --copie directe sur le port + etsnd<=s_len2; + when s_len2 => + --tosend<=(STD_LOGIC_VECTOR(to_unsigned(realdlen,8))); + sPort_in_wr_en<='1'; + tosend<=data_to_send(1); + + --port1_in<=tosend1; --copie directe sur le port + etsnd<=s_data; + BCast_RDY<='0'; + Send_RDY<='0'; + Snd_on<='1'; + i:=i+1; + when s_data => + Snd_on<='1'; + if Port_in_full='0' and RTS_dat='1' then + sPort_in_wr_en<='1'; + + --envoie des données sur le port + tosend<=data_to_send(i); + + + if i+1>=datalen then + etsnd<=s_end; + Send_RDY<='1'; --l'envoi est terminé + if BCast='1' and destport=MAXPort then + BCAST_RDY<='1'; --l'envoi collectif aussi + else + BCast_RDY<='0'; + + end if; + else + BCast_RDY<='0'; + Send_RDY<='0'; + i:=i+1; + end if; + elsif port_in_full='1' then + sPort_in_wr_en<='0'; + else + sPort_in_wr_en<='0'; + BCast_RDY<='0'; + Send_RDY<='0'; + end if; + when s_end => + tosend<=(others=>'-'); + + sPort_in_wr_en<='0'; + if Bcast='1' then + if destPort + if Port_in_empty='1' and RTS_Cmd='1' then + etcmd<=cmdpost; + + end if; + destport:=0; + ctimeout:=0; + origport:=1; + when cmdpost => + if Port_in_empty='1' then + etcmd<=cmdread; + end if; + + when cmdpostidle => --permet juste la prise en compte de la commande + etcmd<=cmdread; + dcount<=0;-- initialisation du compteur de reception + when cmdread => + + + ctimeout:=0; + + if Port_out_data_available='1' then + mport:=to_integer(unsigned(port_out_data(7 downto 4))); + pid:=to_integer(unsigned(port_out_data(3 downto 0)))+1; + CmdReceived(dcount)<=port_out_data; + --cdata_out_en(origport)<='1'; +-- if pid=origport then --le port a été bien identifié + etcmd<=cmdglen; -- + dcount<=dcount+1; +-- else +-- etcmd<=cmdtimeout; +-- end if; + else + + etcmd<=cmdread; + end if; + + + when cmdlen => --positionnement du mot de longueur des données + if Port_out_data_available='1' then + + etcmd<=cmdglen; + ctimeout:=0; + else + ctimeout:=ctimeout+1; + if ctimeout>=30 then + assert true report "Ex4:etcmd Timeout -> impossible de recevoir du le NoC" + severity failure; + etcmd<=cmdtimeout; -- données pas prêtes + end if; + + + end if; + when cmdglen => --lecture effective de la longueur des données + if Port_out_data_available='1' then + cdlen<=to_integer(unsigned(port_out_data(Word-1 downto 0))); + CmdReceived(dcount)<=port_out_data; + etcmd<=cmddata; + dcount<=dcount+1; + else + ctimeout:=ctimeout+1; + if ctimeout>=30 then + --time_out(destport)<='1'; + assert true report "Ex4:etcmd Timeout -> impossible de recevoir du le NoC" + severity failure; + etcmd<=cmdtimeout; -- données pas prêtes + end if; + + end if; + + when cmddata => + if (port_out_data_available='1' and ctimeout<30) then + + --cdata_out_en(origport)<='1'; + mport:=to_integer(unsigned(port_out_data(7 downto 4))); + --attention les ports sont numérotés à partir de 0 + pid:=to_integer(unsigned(port_out_data(3 downto 0)))+1; + CmdReceived(dcount)<=port_out_data; + if (dcount>=cdlen-1 ) then--attention le compteur de données commence à 0 + etcmd<=cmdend; + --CM_RDY<='1'; + else + dcount<=dcount+1; + end if; + Else + + if ctimeout>=30 then + --time_out(destport)<='1'; + etcmd<=cmdtimeout; -- données pas prêtes + assert true report "Ex4:etcmd. cmddata Timeout -> impossible de recevoir du le NoC" + severity failure; + else + ctimeout:=ctimeout+1; + etcmd<=cmdend; + end if; + end if; + when cmdend => + + etcmd<=cmdstart; + + when cmdtimeout => + + etcmd<=cmdstart; + end case; + --sorigport<=origport; + end if; --reset='1' + end if; + end process pcmd; + +majetcmd: process (etcmd,data_to_send, port_out_data_available, dcount,port_out_data) +variable origport : natural; +variable i:natural:=0; + begin + case etcmd is + when cmdstart => + i:=0; + Port_in_cmd_en<='0'; + tosend4<=(others=>'-'); + cport_out_rd_en<='0'; + cport_in_wr_en<='0'; + CM_RDY<='0'; + Cmd_on<='0'; + when cmdpost | cmdpostidle => + cport_in_wr_en<='1'; + tosend4<=data_to_send(0); ---code pour getportid + Port_in_cmd_en<='1'; + cport_out_rd_en<='0'; + CM_RDY<='0'; + Cmd_on<='1'; + when cmdread => + tosend4<=(others=>'-'); + cPort_in_wr_en<='0'; + cport_out_rd_en<=port_out_data_available; + --CmdReceived(dcount)<=port_out_data; --mettre les données dans le tampon + Port_in_cmd_en<='1'; + CM_RDY<='0'; + Cmd_on<='1'; + when cmdlen |cmdglen => --positionnement du mot de longueur des données + tosend4<=(others=>'-'); + cport_in_wr_en<='0'; + cport_out_rd_en<=port_out_data_available; + Port_in_cmd_en<='1'; + --CmdReceived(dcount)<= port_out_data; + CM_RDY<='0'; + Cmd_on<='1'; + when cmddata => + tosend4<=(others=>'-'); + cport_in_wr_en<='0'; + cport_out_rd_en<=Port_out_data_available; + Port_in_cmd_en<='1'; + --CmdReceived(dcount)<=port_out_data; --mettre les données dans le tampon + i:=i+1; + CM_RDY<='0'; + Cmd_on<='1'; + when cmdend => + tosend4<=(others=>'-'); + cport_in_wr_en<='0'; + cport_out_rd_en<='0'; + --CmdReceived(dcount)<=port_out_data; + Port_in_cmd_en<='0'; + CM_RDY<='1'; + Cmd_on<='0'; + when cmdtimeout => + tosend4<=(others=>'-'); + cport_in_wr_en<='0'; + cport_out_rd_en<='0'; + Port_in_cmd_en<='0'; + Cmd_on<='1'; + cm_rdy<='0'; + end case; + +end process majetcmd ; + +i_send_val:process(HCL_Init,Send_RDY,RTS_I,Snd_Ack,I_send_ack,data_to_send,Bcast_rdy,Bcast) +begin +snd_start_i<=snd_start; +RTS_DAT<='0'; + +if HCL_Init='1' then + if RTS_I='1' and snd_ack='0' then + snd_start_i<='1'; + elsif i_send_ack='1' then + + snd_start_i<='0'; + end if; + i_send_rdy<=snd_ack; + + Snd_data<=data_to_send; +else + if RTS_I='1' and i_send_ack='0' then + RTS_DAT<='1'; + elsif i_send_ack='1' then + + RTS_DAT<='0'; + end if; + i_send_rdy<=send_rdy; + for i in 0 to 3 loop + Snd_data(i)<=(others=>'0'); + end loop; +end if; +end process; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/Ex0_Fsm.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/Ex0_Fsm.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/Ex0_Fsm.vhd (revision 138) @@ -0,0 +1,206 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM +-- +-- Create Date: 05:37:34 03/06/2012 +-- Design Name: +-- Module Name: Ex0_Fsm - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Fournit le temps en µs depuis l'initialisation de la bibliothèque +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library NocLib ; + +--use NocLib.CoreTypes.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Ex0_Fsm is + Port ( Initialized : in STD_LOGIC; + + Instruction : in STD_LOGIC_VECTOR (7 downto 0); + instruction_en: in STD_LOGIC; --ceci n'est pas nécessaire dans ce module + -- car le module fonctionne en permanence. + clk : in STD_LOGIC; + reset : in STD_LOGIC; + ClkRate : in STD_LOGIC_VECTOR; --la fréquence de l'horloge en Mhz + uTimeResult : out STD_LOGIC_VECTOR; + TickResult : out STD_LOGIC_VECTOR; + OvFus : out STD_Logic:='0' + ); +end Ex0_Fsm; + +architecture Behavioral of Ex0_Fsm is + + --Use descriptive names for the states, like st1_reset, st2_search + type state_type is (Init,COunt,UsOut,OverFlow); + signal state, next_state : state_type; + --Declare internal signals for all outputs of the state-machine + signal Tick_Count: std_logic_vector(31 downto 0):=(others=>'0'); + signal Time_Ucount :std_logic_vector(31 downto 0):=(others=>'0'); + signal OvF,Ovf_us,ovF_i,zero :std_logic; -- overflow flag + signal ClkR_Count : std_logic_vector(ClkRate'high downto ClkRate'low):=(others=>'0'); + signal en : std_logic:='1'; + --other outputs +begin +utime_PROC: process (clk) + begin + if (rising_edge(clk)) then + if (reset = '1') or Initialized='0' then + state <= init; + -- Time_UCount<= (others=>'0'); + -- Tick_Count <=(others=>'0'); + else + state <= next_state; + TickResult<= Tick_Count; + uTimeResult <=Time_ucount; + OvF<=OvF_i; + OvfUs<=Ovf_us; + -- <= _i; + -- assign other outputs to internal signals + end if; + end if; + end process; + + --MOORE State-Machine - Outputs based on state only + OUTPUT_DECODE: process (state) + FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is + --this function increments a std_logic_vector type by '1' + VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE tb : std_logic_vector(s1'high downto s1'low); + BEGIN + tb(s1'low) := en; + V := s1; + for i in (V'low + 1) to V'high loop + tb(i) := V(i - 1) and tb(i -1); + end loop; + for i in V'low to V'high loop + if(tb(i) = '1') then + V(i) := not(V(i)); + end if; + end loop; + return V; + end incr_vec; -- end function + + +FUNCTION dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is + --this function decrements a std_logic_vector type by '1' + VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE tb : std_logic_vector(s1'high downto s1'low); + BEGIN + tb(s1'low) := not(en); + V := s1; + for i in (V'low + 1) to V'high loop + tb(i) := V(i - 1) or tb(i -1); + end loop; + for i in V'low to V'high loop + if(tb(i) = '0') then + V(i) := not(V(i)); + end if; + end loop; + return V; + end dcr_vec; -- end function +FUNCTION all_ones(s1:std_logic_vector) return std_logic is + --this function tells if all bits of a vector are '1' + --return value Z is '1', then vector has all 1 bits + --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE Z : std_logic; + BEGIN + Z := s1(s1'low); + FOR i IN (s1'low+1) to s1'high LOOP + Z := Z AND s1(i); + END LOOP; + RETURN Z; + END all_ones; -- end function +FUNCTION all_zeros(s1:std_logic_vector) return std_logic is + --this function tells if all bits of a vector are '0' + --return value Z if '1', then vector has all 0 bits + --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE Z : std_logic; + BEGIN + Z := '0'; + FOR i IN (s1'low) to s1'high LOOP + Z := Z OR s1(i); + END LOOP; + RETURN not(Z); + END all_zeros; -- end function + + begin + --insert statements to decode internal output signals + --below is simple example + case state is + When Init => + Clkr_Count<=ClkRate; --initialiser le décompte + Time_uCount<=( others =>'0'); -- mettre à 0 le compteur des µS + Tick_Count<=(others =>'0'); --mettre à 0 les ticks + When Count => + Tick_count<=incr_vec(Tick_Count,en); + ClkR_Count<=dcr_vec(Clkr_Count,en); --compteur de µs + zero<=all_zeros(ClkR_Count); -- + OvF_i<=All_ones(Tick_count); -- + when UsOut => + Time_Ucount<=incr_vec(time_ucount,en); + Clkr_Count<=ClkRate; + Tick_count<=incr_vec(Tick_Count,en); + OvF_i<=All_ones(Tick_count); + zero<='0'; + OvF_us<=All_ones(Time_Ucount); + when OverFlow => + Tick_count<=incr_vec(Tick_Count,en); --compteur de tick + ClkR_Count<=dcr_vec(Clkr_Count,en); + OvF_us<=All_ones(Time_Ucount); + OvF_i<=All_ones(Tick_count); + end case; + end process; + + NEXT_STATE_DECODE: process (state, Initialized, zero, OvF) + begin + --declare default state for next_state to avoid latches + next_state <= state; --default is to stay in current state + --insert statements to decode next_state + --below is a simple example + case (state) is + when Init => + if Initialized = '1' then + + next_state <= count; + end if; + when Count => + if Zero = '0' then + next_state <= Count; + elsif Zero = '1' then + next_state <=Usout; + + end if; + when UsOut => + If OvF='0' then + next_state <= count; + elsif OvF='1' then + next_state <= OverFlow; + end if; + When OverFlow => + next_state<=Count; +-- when others => +-- next_state <= Init; + end case; + end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/Ex5_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/Ex5_FSM.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/Ex5_FSM.vhd (revision 138) @@ -0,0 +1,141 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 14:00:24 08/01/2013 +-- Design Name: +-- Module Name: Ex5_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Ex5_FSM is + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + + SpawnOn : in STD_LOGIC; + NocPortFree : in STD_LOGIC; + InterCSet : in STD_LOGIC; + TaskLoaded : in STD_LOGIC; + TaskInit : in STD_LOGIC; + TaskOn : in STD_LOGIC; + TimeOut : out STD_LOGIC; + DataReceived : in STD_LOGIC_VECTOR (7 downto 0); + DataToSend : out STD_LOGIC_VECTOR (7 downto 0)); +end Ex5_FSM; + +architecture Behavioral of Ex5_FSM is +type Spawn_type is (Init,CheckFree,LoadTask,CountTask,StartTask,WaitTaskInit,SetGroup,SetInterCom,RetInterCom,ErrSpawn,EndSpawn); + signal spawn_st, next_spawn : spawn_type; +begin +--Insert the following in the architecture after the begin keyword + SYNC_spawn: process (clk) + begin + if (clk'event and clk = '1') then + if (reset = '1') then + spawn_st <= init; + + else + spawn_st <= next_spawn; + -- <= _i; + -- assign other outputs to internal signals + end if; + end if; + end process; + + --MOORE State-Machine - Outputs based on state only + OUTPUT_DECODE: process (Spawn_st) + begin + --insert statements to decode internal output signals + --below is simple example + case (spawn_st) is + when init => + + when CheckFree => + + when LoadTask => + + when StartTask => + + when CountTask => + + when WaitAllTaskInit => + + when SetGroup => + + when SetInterCom => + + when RetInterCom => + + when EndSpawn => + + when others => + + end case; + end process; + + NEXT_STATE_DECODE: process (spawn_st, spawnOn,Datareceived) + begin + --declare default state for next_state to avoid latches + next_spawn <= spawn_st; --default is to stay in current state + --insert statements to decode next_state + --below is a simple example + case (spawn_st) is + when init => + if spawnOn = '1' then + next_spawn <= Checkfree; + end if; + when CheckFree => + if NoCPortFree = '1' then + next_spawn<= LoadTask; + end if; + when LoadTask => + next_spawn <= CountTask; + when StartTask => + if TaskInit = '1' then + next_spawn <= WaitAllTaskInit; + end if; + when WaitAllTaskInit => + if InterComSet = '1' then + next_spawn <= SetGroup; + end if; + when SetGroup => + if InterComSet = '1' then + next_spawn <= SetInterCom ; + end if; + when SetInterCom => + if InterComSet = '1' then + next_spawn <= RetInterCom ; + end if; + when RetInterCom => + if AppAck = '1' then + next_spawn <= EndSpawn; + end if; + when others => + next_spawn <= init; + end case; + end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/FIFO_64_FWFT.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/FIFO_64_FWFT.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/FIFO_64_FWFT.vhd (revision 138) @@ -0,0 +1,223 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL/GAMOM +-- +-- Create Date: 19:51:54 04/19/2011 +-- Design Name: +-- Module Name: FIFO_64 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +--FIFO 64 Octets utisé pour les modules d'entrée +-- ce fifo est de type fwft first word falls throught ce qui +-- signifie que l'on a toujours la donnée au sommet de la pile en +-- sortie du fifo. +-- Dependencies: RAM_64.vhd +-- +-- Revision: 08-11-2012 +-- Revision 0.01 - File Created +-- Additional Comments: suppression du signal counter_en dans les expressions +-- 08/11/12 : prise en compte du retard de propagation des infos dans la FIFO. +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FIFO_64_FWFT is + Port ( clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR (Word-1 downto 0); + rd_en : in STD_LOGIC; + srst : in STD_LOGIC; + wr_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR (Word-1 downto 0); + empty : out STD_LOGIC; + full : out STD_LOGIC); +end FIFO_64_FWFT; + +architecture Behavioral of FIFO_64_FWFT is +-- declaration de la ram 64 octets +COMPONENT RAM_64 + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector(5 downto 0); + addrb : IN std_logic_vector(5 downto 0); + dia : IN std_logic_vector(Word-1 downto 0); + --doa : OUT std_logic_vector(Word-1 downto 0); + dob : OUT std_logic_vector(Word-1 downto 0) + ); + END COMPONENT; +type fsm_states is (state0, state1, state2);-- definition du type etat pour le codage des etats des fsm +signal fwft_fsm_state : fsm_states; +type ram_type is array (63 downto 0) of std_logic_vector (Word-1 downto 0); + signal RAM: ram_type; +-- declaration des signeaux des compteurs +signal push_address_counter : std_logic_vector(5 downto 0); +signal pop_address_counter : std_logic_vector(5 downto 0); +signal fifo_counter : std_logic_vector(5 downto 0):=(others=>'0'); +--autre signaux +signal rd_ready : std_logic:='0'; +signal empty_signal : std_logic; +signal full_signal : std_logic; +signal wr_en_signal : std_logic; +signal rd_en_signal : std_logic; +signal clk_signal : std_logic; +signal dob_signal : std_logic_vector(Word-1 downto 0); +signal dout_signal : std_logic_vector(Word-1 downto 0); +signal doa_signal : std_logic_vector(Word-1 downto 0); +signal counter_en : std_logic; + +begin + +-- ram instantiation de la ram 64 octets du FIFO +--fifo_RAM_64: RAM_64 PORT MAP( +-- clka => clk_signal, +-- clkb => clk_signal, +-- wea => wr_en_signal, +-- ena => wr_en_signal, +-- enb => rd_en_signal, +-- addra => push_address_counter, +-- addrb => pop_address_counter, +-- dia => din, +-- --doa => doa_signal, +-- dob => dob_signal +-- ); +-- circuiterie des signaux de validation et d'etat du fifo +wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein +rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide +full_signal <= '1' when fifo_counter = "111111" else + '0'; +empty_signal <= '1' when rd_ready='0' or unsigned(fifo_counter) = 0 else + '0'; +clk_signal <= clk; +full <= full_signal; +empty <= empty_signal; + +-- sortie du fifo fwft +dout <= dout_signal; + +-- le processus des transistion +fwft_fsm_nsl : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + fwft_fsm_state <= state0; + else + case fwft_fsm_state is + when state0 => if wr_en_signal = '1' then --tampon vide seule l'écriture est possible + fwft_fsm_state <= state1; + end if; + + + when state1 => --if rd_en_signal = '1' and wr_en_signal='1' then --écriture seule dans le tampon + + fwft_fsm_state <= state2; + --end if; + + when state2 => if rd_en_signal = '1' and wr_en_signal='1' then + fwft_fsm_state <= state2; + elsif rd_en_signal='1' and wr_en_signal='0' and unsigned(fifo_counter) = 1 then --lecture avec écriture + fwft_fsm_state <= state0; + elsif unsigned(fifo_counter) = 0 then + fwft_fsm_state <= state0; + end if; + + when others => fwft_fsm_state <= state0; + end case; + end if; + end if; + end process; + -- actions associées à la fsm + -- mux qui oriente les sortie doa et dob vers out + val_fwft:process (fwft_fsm_state,dob_signal) + + begin + case fwft_fsm_state is + when state0 => + + dout_signal <= dob_signal; + counter_en <= '0'; + rd_ready <='0'; + when state1 => + + dout_signal <= dob_signal; + counter_en <= '1'; + rd_ready <='0'; + when state2 => + + dout_signal <= dob_signal; + counter_en <= '1'; + rd_ready <='1'; + when others => + dout_signal <= dob_signal; + counter_en <= '0'; + rd_ready <='0'; + end case; +end process; +doa_latch_process : process(clk) +begin + if rising_edge(clk) then + if wr_en_signal ='1' then + doa_signal <= din; + end if; + end if; +end process; + +-- processus de comptage des adresses d'empilement +push_process : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + push_address_counter <= (others =>'0'); + elsif wr_en_signal ='1' then + RAM(conv_integer(push_address_counter)) <=din; + push_address_counter <= push_address_counter +1; + end if; + end if; +end process; + + -- processus de comptage des adresses depilement du fifo +pop_process : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + pop_address_counter <= (others =>'0'); + elsif rd_en_signal ='1' then + pop_address_counter <= pop_address_counter +1; + end if; + end if; + end process; + dob_signal<=RAM(conv_integer(pop_address_counter)); + -- processus de comptage des octets dans le fifo + fifo_counter_process : process(clk) + variable count : std_logic_vector(5 downto 0):= (others=>'0'); +begin + if rising_edge(clk) then + if srst = '1' then + fifo_counter <= (others =>'0'); + count:=(others =>'0'); + else + if wr_en_signal ='1' and rd_en_signal ='0' then + count:=count+1; + end if; + if rd_en_signal ='1' and wr_en_signal ='0' and counter_en='1' then + count:=count-1; + end if; + fifo_counter<=count; + end if; + end if; +end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/FIfo_mem.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/FIfo_mem.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/FIfo_mem.vhd (revision 138) @@ -0,0 +1,91 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04:35:05 10/15/2012 +-- Design Name: +-- Module Name: FIfo_mem - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +entity FIFO is + generic (N: integer := 6; -- number of address bits for 2**N address locations +M: integer := 8); -- number of data bits to/from FIFO + port (CLK, PUSH, POP, INIT: in std_logic; + DIN: in std_logic_vector(N-1 downto 0); +DOUT: out std_logic_vector(N-1 downto 0); + FULL, EMPTY, NOPUSH, NOPOP: out std_logic; + clk: IN std_logic; + + rd_en: IN std_logic; + srst: IN std_logic; + wr_en: IN std_logic; + + empty: OUT std_logic; + full: OUT std_logic); +end entity FIFO; +architecture TOP_HIER of FIFO is +signal WE: std_logic; +signal A: std_logic_vector(N-1 downto 0); +signal PUSH, POP, INIT: std_logic; + +signal NOPUSH, NOPOP: std_logic; + +component FIFO_LOGIC is + generic (N: integer); -- number of address bits + port (CLK, PUSH, POP, INIT: in std_logic; + ADD: out std_logic_vector(N-1 downto 0); + FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic); +end component FIFO_LOGIC; + +COMPONENT RAM_256 + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector(Word-1 downto 0); + addrb : IN std_logic_vector(Word-1 downto 0); + dia : IN std_logic_vector(Word-1 downto 0); + dob : OUT std_logic_vector(Word-1 downto 0) + ); +END COMPONENT; +begin +-- example of component instantiation using positional notation +FL: FIFO_LOGIC generic map (N) + port map (CLK, PUSH, POP, INIT, A, FULL, EMPTY, WE, NOPUSH, NOPOP); +Push<=wr_en; +pop<=rd_en; +nopush<=nopush; +nopop<=nopop; +init<=srst; +-- example of component instantiation using keyword notation +--R: RAM generic map (W => N, K => M) +-- port map (DIN => DIN, ADDR => A, WR => WE, DOUT => DOUT); +R: RAM_256 PORT MAP( + clka => clk, + clkb => clk, + wea => we, + ena => '1', + enb => '1', + addra => A, + addrb => A, + dia => din, + dob => dout + ); +end architecture TOP_HIER; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/FIfo_proc.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/FIfo_proc.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/FIfo_proc.vhd (revision 138) @@ -0,0 +1,102 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04:35:05 10/15/2012 +-- Design Name: +-- Module Name: FIfo_mem - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +entity FIFO_LOGIC is + generic (N: integer := 3); + port (CLK, PUSH, POP, INIT: in std_logic; + ADD: out std_logic_vector(N-1 downto 0); + FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic); +end entity FIFO_LOGIC; +architecture RTL of FIFO_LOGIC is +signal WPTR, RPTR: std_logic_vector(N-1 downto 0); +signal LASTOP: std_logic; +begin +SYNC: process (CLK) begin + if (CLK'event and CLK = '1') then + if (INIT = '1') then -- initialization -- + WPTR <= (others => '0'); + RPTR <= (others => '0'); + LASTOP <= '0'; + elsif (POP = '1' and EMPTY = '0') then -- pop -- + RPTR <= RPTR + 1; + LASTOP <= '0'; + elsif (PUSH = '1' and FULL = '0') then -- push -- + WPTR <= WPTR + 1; + LASTOP <= '1'; + end if; -- otherwise all Fs hold their value -- + end if; +end process SYNC; +COMB: process (PUSH, POP, WPTR, RPTR, LASTOP, FULL, EMPTY) begin +-- full and empty flags -- + if (RPTR = WPTR) then + if (LASTOP = '1') then + FULL <= '1'; + EMPTY <= '0'; + else + FULL <= '0'; + EMPTY <= '1'; + end if; + else + FULL <= '0'; + EMPTY <= '0'; + end if; +-- address, write enable and nopush/nopop logic -- + if (POP = '0' and PUSH = '0') then -- no operation -- + ADD <= RPTR; + WE <= '0'; + NOPUSH <= '0'; + NOPOP <= '0'; + elsif (POP = '0' and PUSH = '1') then -- push only -- + ADD <= WPTR; + NOPOP <= '0'; + if (FULL = '0') then -- valid write condition -- + WE <= '1'; + NOPUSH <= '0'; + else -- no write condition -- + WE <= '0'; + NOPUSH <= '1'; + end if; + elsif (POP = '1' and PUSH = '0') then -- pop only -- + ADD <= RPTR; + NOPUSH <= '0'; + WE <= '0'; + if (EMPTY = '0') then -- valid read condition -- + NOPOP <= '0'; + else + NOPOP <= '1'; -- no red condition -- + end if; + else -- push and pop at same time - + if (EMPTY = '0') then -- valid pop -- + ADD <= RPTR; + WE <= '0'; + NOPUSH <= '1'; + NOPOP <= '0'; + else + ADD <= wptr; + WE <= '1'; + NOPUSH <= '0'; + NOPOP <= '1'; + end if; + end if; +end process COMB; +end architecture RTL; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/HT_4.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/HT_4.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/HT_4.vhd (revision 138) @@ -0,0 +1,526 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:04:21 04/22/2013 +-- Design Name: +-- Module Name: HT_process - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +library NocLib ; +use std.textio.all; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +use work.MPI_RMA.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +--entity HT_process is +-- generic (Task_id : natural:=0); +-- Port ( clk : in STD_LOGIC; +-- reset : in STD_LOGIC; +-- en : in std_logic; -- active la tâche +-- Interf_i : in core_i; --signaux pour l'interface IO +-- Interf_o : out core_o; --signaux pour l'interface IO +-- mem_o : out typ_dpram_o; -- signaux pour l'accès à la mémoire +-- mem_i : in typ_dpram_i -- signaux pour l'accès à la mémoire +-- ); +--end HT_process; + +architecture A2 of HT_process is + + type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinPost,WinStart, + putdata,getdata,WinWait,WinCompleted,MpiSpawn,finalize,st_timeout); + signal sram : typ_dpram; + signal MyGroup:mpi_group; + signal MyWin : mpi_win; + signal MyRank :std_logic_vector(3 downto 0); + signal intercomm,array_of_errcodes : natural; + signal ct_state:natural:=0; +signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque +signal RunState : typ_mae; + +begin + +--MAE du PE +--======================================================================= +-- Interf<=Libr; + + + pPutGet:process(clk,reset,en) + + constant DATAPTR : natural :=256; + variable nb_rma:natural range 0 to 15:=0; + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout,ct,dlen,dcount : natural range 0 to 255; + variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0); + variable mywin : Mpi_win; + variable command , argv , maxprocs , info , root : natural:=0; --variable pour le spawn + variable comm : natural :=0; + variable Spawn_on: std_logic:='0'; + variable adresse,adresse_rd :natural range 0 to 65536; + variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0'); + + --======================================================= + --variables pour la création du fichier de résultats + -- synthesis translate_off + type char_file is file of character; + file f: text; + variable status :file_open_status ; + variable char_count: integer range 0 to 65536 := 0; + variable str: string (1 to 79) ; + variable L: line; + variable fopened: std_logic:='0'; + + constant simres : time :=1 ps; --simulation resolution + constant realres : real :=1.0e-3; --ramener le temps en ns + -- returns real value of time parameter using pure VHDL + function rt(t : time) return real is + begin + return real(t/simres) * realres; + end; + -- synthesis translate_on +--====================================================== + begin + --=== Partie combinatoire du process =================================== + + --=== Fin de la partie combinatoire du process ========================== + + + + --end loop; + + if (clk'event and clk='1') and en='1' then + + + if reset='1' then + RunState<=start; + + else + --========================================================== + --affectation des entrées sorties mémoires + sram.i.data_out<=mem_I.data_out; + mem_o.addr_wr<=sram.O.addr_wr; + mem_o.addr_rd<=sram.O.addr_rd ; + mem_o.we<=sram.O.we; + mem_o.ena<=sram.O.ena; + mem_o.enb<=sram.O.enb; + mem_o.data_in<=sram.O.data_in; + --affectation des entrées sorties MPI_HCL + Interf_o.Instr_EN<=Libr.O.instr_en; + Interf_o.Membusy<=Libr.O.MemBusy; + Interf_o.Instruction<=Libr.O.Instruction; + Libr.i.Instr_ack<=Interf_i.Instr_ack; + Libr.i.InitOk<=Interf_i.InitOk; + Libr.i.Hold_Req<=Interf_i.Hold_req; + Libr.I.Spawned<=Interf_i.Spawned; + --Libr.i.Hold_Ack<=Interf_i.Hold_Ack; + Libr.i.RamSel<=Interf_i.RamSel; + --ct_state<=ct; --pour débogage + --============================================================ + + case RunState is + when start => + --Dcount<=0; + if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide + RunState<=InitApp; + end if; + --Ram_busy<='0'; + Libr.O.MemBusy<='0'; + Libr.O.Instr_En<='0'; + + adresse:=10;--DATAPTR; + + adresse_rd:=0; + timeout:=0; + --dcount<=0; + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + -- synthesis translate_off + if fopened='0' then + file_open(status,f, integer'image(Task_Id) & "test_file0.txt", APPEND_MODE); + --while not endfile(c_file_handle) loop + --end if; + + --write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now))); + --report l.all; + -- writeline (f, l) ; + fopened:='1'; + end if; + -- synthesis translate_on + when Fillmem => + sram.O.we<='1'; + sram.O.ena<='1'; + sram.O.enb<='0'; + if Libr.I.Ramsel='0' then + + sram.O.addr_wr<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + sram.O.data_in<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f"; + Libr.O.Instr_En<='0'; + dcount:=dcount+1; + + if dcount=250 then + bfill:=bfill+1; + + if bfill=4 then + RunState<=WinCreate; + else + RunState<=nextfill; + end if; + else + adresse:=adresse+1; + RunState<=Fillmem; + end if; + else -- attente de la libéraion de la mémoire + timeout:=timeout+1; + if timeout=100 then + RunState<=st_timeout; + end if; + + end if; + when nextfill => --prépare le prochain bloc mémoire qui sera rempli + adresse:=250*bfill+10; + + dcount:=0; + ct:=0; + RunState<=Fillmem; + Libr.O.Instr_En<='0'; + sram.O.we<='1'; + sram.O.ena<='1'; + sram.O.enb<='0'; + when InitApp => + --code pour Init + dlen:=1; + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;"& integer'image(dlen) & " ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now)))); + + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Init(ct,Libr,Clk,SRam); + + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + --if Libr.InitOk='1' then + if ct=0 then + RunState<=GetRank; + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(Dlen) & ";INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + + when GetRank => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(Dlen)& ";Rank1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + + if ct=0 then + RunState<=FillMem; + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when Wincreate => --par défaut la fenêtre 0 est utilisée ! + case MyRank is + when x"0"=> + Mygroup.grp<=x"0002";-- rank 1 + MyGroup.nb<=2; + destRank:=1; + DestAdr:=X"043F"; + nb_rma:=1; + when x"1" => + Mygroup.grp<=x"0000";-- rank 0 + destRank:=0; + DestAdr:=X"043F"; + when x"2" => + Mygroup.grp<=x"0000";-- rank + destRank:=0; + DestAdr:=X"044F"; + when x"3" => + Mygroup.grp<=x"0000";-- rank + destRank:=0; + DestAdr:=X"045F"; + when others => --cas des processus spawn + Mygroup.grp<=x"0000";-- rank 0 + destRank:=0; + end case; + RunState<=WinPost; + when WinPost => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;"& integer'image(dlen) & ";WPost1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + pMPI_Win_Post(ct,Libr,sram,MyGroup,0,MyWin); + + if ct=0 then + if spawn_on='1' then + RunState<=WinWait; + else + RunState<=WinStart; + end if; + -- synthesis translate_off + write (l,string'("Dlen;"& integer'image(dlen) & ";WPost2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + when WinStart => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";WStart1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + RunState<=PutData; + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when putdata => --construire le packet pour le Put + + --dlen:=251; --- + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + SrcAdr:=X"000A";--std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); + --DestAdr:=X"033F"; + pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + RunState<=GetData; + -- synthesis translate_off + report "Put of Process n°; " & image(MyRank) & "; ended at ; " & real'image(rt(now)); + write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when getdata => --positionnement du mot de longueur des données + --dlen:=251; --- + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + SrcAdr:=X"006D"; + DestAdr:=X"1400"; + if unsigned(MyRank) = 0 then + pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + else + + --pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,nb_rma,DestAdr,Dlen,Mpi_int,Default_win); + end if; + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + if unsigned(MyRank)/=0 then + RunState<=wincompleted; + else + nb_rma:=nb_rma+1; + if nb_rma=2 then + RunState<=wincompleted; + nb_rma:=0; + end if; + end if; + -- synthesis translate_off + assert ct/=0 report "GET_END " & integer'image(destrank) + severity Warning ; + write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + + writeline (f, l) ; + -- synthesis translate_on + end if; + + when WinCompleted => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_Complete(ct,Libr,sram,MyWin ); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + RunState<=WinWait; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + when WinWait => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_wait(ct,Libr,sram,MyWin ); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + if Libr.I.Spawned='1' then + RunState<=Finalize; + elsif spawn_on='1' then + RunState<=Finalize; + else + RunState<=MpiSpawn; + end if; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + + when MpiSpawn => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + --(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + + maxprocs:=2; + pMPI_Comm_Spawn(ct,Libr,sram,command,argv,maxprocs,info,root,comm,intercomm,array_of_errcodes); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + if unsigned(MyRank)=0 then + Spawn_on:='1'; + Mygroup.grp<=x"000C";-- rank 3,4 + destRank:=0; + runstate<=WinPost; + else + RunState<=Finalize; + end if; + + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + when finalize => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + if ct=0 then + RunState<=start; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + file_close(f); + -- synthesis translate_on + end if; + + when st_timeout => + + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + + RunState<=start; + end case; + ct_state<=ct; --pour débogage + end if; + end if; + + end process pPutGet; + +end a2; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/HT_5.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/HT_5.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/HT_5.vhd (revision 138) @@ -0,0 +1,493 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:04:21 04/22/2013 +-- Design Name: +-- Module Name: HT_process - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +library NocLib ; +use std.textio.all; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +use work.MPI_RMA.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + + + +architecture A_Count of HT_process is + + type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinPost,WinStart, + putdata,getdata,WinWait,WinCompleted,MpiSpawn,finalize,st_timeout); + signal sram : typ_dpram; + signal MyGroup:mpi_group; + signal MyWin : mpi_win; + signal MyRank :std_logic_vector(3 downto 0); + signal intercomm,array_of_errcodes : natural; + signal ct_state:natural:=0; +signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque +signal RunState : typ_mae; +component count_32 is +port (clk,reset,upDn,load,start:in std_logic; +loadval :in std_logic_vector(31 downto 0); +outval : out std_logic_vector(31 downto 0)); +end component count_32; +signal rescount,updn,load,start :std_logic:='0'; +signal loadval,outval :std_logic_vector(31 downto 0):=(others=>'0'); + +begin + +--MAE du PE +--======================================================================= +-- Interf<=Libr; + + + pPutGet:process(clk,reset,en) + + constant DATAPTR : natural :=256; + variable nb_rma:natural range 0 to 15:=0; + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout,ct,dlen,dcount : natural range 0 to 255; + variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0); + variable mywin : Mpi_win; + variable command , argv , maxprocs , info , root : natural:=0; --variable pour le spawn + variable comm : natural :=0; + variable Spawn_on: std_logic:='0'; + variable adresse,adresse_rd :natural range 0 to 65536; + variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0'); + + --======================================================= + --variables pour la création du fichier de résultats + -- synthesis translate_off + type char_file is file of character; + file f: text; + variable status :file_open_status ; + variable char_count: integer range 0 to 65536 := 0; + variable str: string (1 to 79) ; + variable L: line; + variable fopened: std_logic:='0'; + + constant simres : time :=1 ps; --simulation resolution + constant realres : real :=1.0e-3; --ramener le temps en ns + -- returns real value of time parameter using pure VHDL + function rt(t : time) return real is + begin + return real(t/simres) * realres; + end; + -- synthesis translate_on +--====================================================== + begin + --=== Partie combinatoire du process =================================== + + --=== Fin de la partie combinatoire du process ========================== + + + + --end loop; + + if (clk'event and clk='1') and en='1' then + + + if reset='1' then + RunState<=start; + + else + --========================================================== + --affectation des entrées sorties mémoires + sram.i.data_out<=mem_I.data_out; + mem_o.addr_wr<=sram.O.addr_wr; + mem_o.addr_rd<=sram.O.addr_rd ; + mem_o.we<=sram.O.we; + mem_o.ena<=sram.O.ena; + mem_o.enb<=sram.O.enb; + mem_o.data_in<=sram.O.data_in; + --affectation des entrées sorties MPI_HCL + Interf_o.Instr_EN<=Libr.O.instr_en; + Interf_o.Membusy<=Libr.O.MemBusy; + Interf_o.Instruction<=Libr.O.Instruction; + Libr.i.Instr_ack<=Interf_i.Instr_ack; + Libr.i.InitOk<=Interf_i.InitOk; + Libr.i.Hold_Req<=Interf_i.Hold_req; + Libr.I.Spawned<=Interf_i.Spawned; + --Libr.i.Hold_Ack<=Interf_i.Hold_Ack; + Libr.i.RamSel<=Interf_i.RamSel; + --ct_state<=ct; --pour débogage + --============================================================ + + case RunState is + when start => + --Dcount<=0; + if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide + RunState<=InitApp; + end if; + --Ram_busy<='0'; + Libr.O.MemBusy<='0'; + Libr.O.Instr_En<='0'; + + adresse:=10;--DATAPTR; + + adresse_rd:=0; + timeout:=0; + --dcount<=0; + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + -- synthesis translate_off + if fopened='0' then + file_open(status,f, integer'image(Task_Id) & "test_file0.txt", APPEND_MODE); + --while not endfile(c_file_handle) loop + --end if; + + --write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now))); + --report l.all; + -- writeline (f, l) ; + fopened:='1'; + end if; + -- synthesis translate_on + when ReadData1 => + readmem(ct,libr,sram,x"0010",V); + if ct=0 then + reset_count<=v(0); + UpDn<=v(1); + Load<=v(2); + RunState<=ReadData2 + end if; + when readData2 => + readmem(ct,libr,sram,x"0011",loadval); + if ct=0 then + RunState<=WinCreate; + + end if; + + when InitApp => + --code pour Init + dlen:=1; + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;"& integer'image(dlen) & " ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now)))); + + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Init(ct,Libr,Clk,SRam); + + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + --if Libr.InitOk='1' then + if ct=0 then + RunState<=GetRank; + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(Dlen) & ";INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + + when GetRank => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(Dlen)& ";Rank1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + + if ct=0 then + RunState<=FillMem; + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when Wincreate => --par défaut la fenêtre 0 est utilisée ! + case MyRank is + when x"0"=> + Mygroup.grp<=x"0002";-- rank 1 + MyGroup.nb<=2; + destRank:=1; + DestAdr:=X"043F"; + nb_rma:=1; + when x"1" => + Mygroup.grp<=x"0000";-- rank 0 + destRank:=0; + DestAdr:=X"043F"; + when x"2" => + Mygroup.grp<=x"0000";-- rank + destRank:=0; + DestAdr:=X"044F"; + when x"3" => + Mygroup.grp<=x"0000";-- rank + destRank:=0; + DestAdr:=X"045F"; + when others => --cas des processus spawn + Mygroup.grp<=x"0000";-- rank 0 + destRank:=0; + end case; + RunState<=WinPost; + when WinPost => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;"& integer'image(dlen) & ";WPost1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + pMPI_Win_Post(ct,Libr,sram,MyGroup,0,MyWin); + + if ct=0 then + if spawn_on='1' then + RunState<=WinWait; + else + RunState<=WinStart; + end if; + -- synthesis translate_off + write (l,string'("Dlen;"& integer'image(dlen) & ";WPost2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + when WinStart => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";WStart1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + RunState<=PutData; + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when putdata => --construire le packet pour le Put + + --dlen:=251; --- + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + SrcAdr:=X"000A";--std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); + --DestAdr:=X"033F"; + pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + RunState<=GetData; + -- synthesis translate_off + report "Put of Process n°; " & image(MyRank) & "; ended at ; " & real'image(rt(now)); + write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when getdata => --positionnement du mot de longueur des données + --dlen:=251; --- + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + SrcAdr:=X"006D"; + DestAdr:=X"1400"; + if unsigned(MyRank) = 0 then + pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + else + + --pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,nb_rma,DestAdr,Dlen,Mpi_int,Default_win); + end if; + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + if unsigned(MyRank)/=0 then + RunState<=wincompleted; + else + nb_rma:=nb_rma+1; + if nb_rma=2 then + RunState<=wincompleted; + nb_rma:=0; + end if; + end if; + -- synthesis translate_off + assert ct/=0 report "GET_END " & integer'image(destrank) + severity Warning ; + write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + + writeline (f, l) ; + -- synthesis translate_on + end if; + + when WinCompleted => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_Complete(ct,Libr,sram,MyWin ); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + RunState<=WinWait; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + when WinWait => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_wait(ct,Libr,sram,MyWin ); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + if Libr.I.Spawned='1' then + RunState<=Finalize; + elsif spawn_on='1' then + RunState<=Finalize; + else + RunState<=MpiSpawn; + end if; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + + when MpiSpawn => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + --(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + + maxprocs:=2; + pMPI_Comm_Spawn(ct,Libr,sram,command,argv,maxprocs,info,root,comm,intercomm,array_of_errcodes); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + if unsigned(MyRank)=0 then + Spawn_on:='1'; + Mygroup.grp<=x"000C";-- rank 3,4 + destRank:=0; + runstate<=WinPost; + else + RunState<=Finalize; + end if; + + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + when finalize => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + if ct=0 then + RunState<=start; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + file_close(f); + -- synthesis translate_on + end if; + + when st_timeout => + + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + + RunState<=start; + end case; + ct_state<=ct; --pour débogage + end if; + end if; + + end process pPutGet; + +end a_count; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPICORETEST.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPICORETEST.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPICORETEST.vhd (revision 138) @@ -0,0 +1,702 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 01:27:32 04/20/2012 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/MPICORETEST.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: MPI_NOC +-- +-- Dependencies: +-- +-- Revision: 11 Juillet 2012 +-- Revision 0.01 - File Created +-- Additional Comments:Permet de tester le composant MPI +-- en simulant deux PE qui s'échangent des données. +-- Notes: +-- +-- +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +library NocLib ; +--use IEEE.STD_LOGIC_ARITH.ALL; +--use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +use work.MPI_RMA.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +USE ieee.numeric_std.ALL; + +ENTITY MPICORETEST IS +--port (clkm : in std_logic; +--reset : in std_logic; +--result : out std_logic_vector(Word-1 downto 0)); +END MPICORETEST; + +ARCHITECTURE behavior OF MPICORETEST IS +--constant WORD :positive:=8; +constant MEMSIZE:positive:=65535; + -- Components declaration + COMPONENT RAM_v + generic (width : positive;size :positive); + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector; + addrb : IN std_logic_vector; + dia : IN std_logic_vector; + dob : OUT std_logic_vector + ); + END COMPONENT; + + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT MPI_NOC + generic (NPROC : positive:=2); + PORT( + MPI_Node_in : IN Ar_MPIPort_in(1 to 2); + MPI_Node_Out : OUT Ar_MPIPort_out(1 to 2) + ); + END COMPONENT; + + constant clk_period : time := 10 ns; + +--===================signaux pour l'horloge ============================== +signal reset,clkm : std_logic := '0'; +--======================================================================== + --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0'; + signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic; + signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal PE_Instr_en : std_logic:='0'; + signal sram : typ_dpram; + signal pe_hold_ack,pe_hold_req : std_logic; + --signal pe_putadr:std_logic_vector(MEMSIZE-1 downto 0);-- adresse du bloc pour Put + --signal pe_getadr:std_logic_vector(MEMSIZE-1 downto 0);-- adresse du bloc pour get + signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée + signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO + signal Lib_Init : std_logic; -- l'initialisation est terminée + + --données du programme PE + signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0); + signal dpid,dpid_i : natural range 0 to 15:=1; + --Inputs + signal MPI_Node_in : Ar_MPIPort_in(1 to 2) ; +-- Port details +-- instruction : STD_LOGIC_VECTOR (Word -1 downto 0); +-- instruction_en : STD_LOGIC; +-- packet_ack : std_logic; +-- ram_data_in : STD_LOGIC_VECTOR (Word-1 downto 0); +-- clk : STD_LOGIC; +-- reset : STD_LOGIC; + --Outputs + signal MPI_Node_Out : Ar_MPIPort_out(1 to 2); +-- détails des champs de Typ_MPIPORT_Out +-- +-- +-- ram_we : STD_LOGIC; +-- ram_en : STD_LOGIC; +-- packet_received : STD_LOGIC; +-- barrier_completed : STD_LOGIC; +-- instruction_fifo_full : STD_LOGIC; +-- PushOut : STD_LOGIC_VECTOR (WORD-1 downto 0); +-- ram_data_out : STD_LOGIC_VECTOR (WORD-1 downto 0); +-- ram_address : STD_LOGIC_VECTOR (ADRLEN-1 downto 0); +-- +--end record; + -- + -- a + + + --signaux pour la gestion de la MAE + type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, + putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); +signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées +signal count,count_i : natural range 0 to 15:=0; + +--signal adresse,adresse_rd :natural range 0 to 65536; + + signal etPutGet : typ_mae; + signal Ram_busy :std_logic:='0'; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: MPI_NOC GENERIC MAP (NPROC=>2) + PORT MAP ( + MPI_Node_in => MPI_Node_in, + MPI_Node_Out => MPI_Node_Out + ); +Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN) + PORT MAP( + clka =>clkm, + clkb => clkm, + wea => ram_we, + ena => ram_ena, + enb => ram_enb, + addra => ram_addra, + addrb =>ram_addrb, + dia => ram_din, + dob => ram_do + ); + + --MUX de la RAM + + ram_addrb <= MPI_Node_out(1).ram_address_rd WHEN ramsel ='1' ELSE + pe_ram_addrb; + ram_addra <= MPI_Node_out(1).ram_address_wr WHEN ramsel ='1' ELSE + pe_ram_addra; + + +ram_ena <= MPI_Node_out(1).ram_en WHEN ramsel ='1' ELSE + pe_ram_ena; +ram_enb <= MPI_Node_out(1).ram_en WHEN ramsel ='1' ELSE + pe_ram_enb; +ram_ena <= MPI_Node_out(1).ram_en WHEN ramsel ='1' ELSE + pe_ram_ena; + +ram_we<= MPI_Node_out(1).ram_we WHEN ramsel ='1' ELSE + pe_ram_we; + +ram_din <= MPI_Node_out(1).ram_data_in WHEN ramsel ='1' ELSE + pe_ram_din; + + +MPI_Node_in(1).ram_data_out<=ram_do when ramsel='1' else (others=>'Z'); +pe_ram_do<=ram_do when ramsel='0' else (others=>'Z'); + + +pe_hold_req<=MPI_Node_out(1).hold_req; +MPI_Node_in(1).hold_ack<=pe_hold_ack; +MPI_Node_in(1).reset<=reset; +MPI_Node_in(1).clk<=clkm; +MPI_Node_in(1).instruction_en<=PE_instr_en; +MPI_Node_in(1).instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8)); + +Lib_Instr_ack<=MPI_Node_out(1).Pushout(0); --l'instruction a été copié +Lib_init<=MPI_Node_out(1).Pushout(4); -- Initialized +--============================================================= + -- Clock process definitions +--============================================================= + clk_process :process + begin + clkm <= '0' ; + wait for 10 ns;--clk_period/2; + clkm <= '1' ; + wait for 10 ns;--clk_period/2; + end process; + stim_proc: process + begin + -- hold reset state for 100 ns. + reset<='0'; + wait for 1 ns; + reset<='1'; + wait for clk_period*10; + reset<='0'; + wait; + + + end process; +--================================================================ +dpid<=dpid_i; + pPutGet:process(clkm) + + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout,dlen,ct : natural range 0 to 255; + variable adrToset : std_logic_vector(ADRLEN-1 downto 0); + variable iack : std_logic:='0'; + variable adresse,adresse_rd :natural range 0 to 65536; + + begin + + if (clkm'event and clkm='1') then + if reset='1' then + etputget<=start; + + + dcount<=0; + + else + + case etputget is + when start => + if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide + etputget<=Fillmem; + end if; + Ram_busy<='0'; + PE_Instr_En<='0'; + iack:='0'; + adresse:=256; + adresse_rd:=0; + timeout:=0; + dcount<=0; + when Fillmem => + if mpi_node_out(1).hold_req='0' then + + + + PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f"; + PE_Instr_En<='0'; + dcount<=dcount+1; + + if dcount=50 then + bfill:=bfill+1; + + if bfill=4 then + etputget<=InitApp; + else + etputget<=nextfill; + end if; + else + adresse:=adresse+1; + etputget<=Fillmem; + end if; + else -- attente de la libéraion de la mémoire + timeout:=timeout+1; + if timeout=100 then + etputget<=st_timeout; + end if; + + end if; + when nextfill => --prépare le prochain bloc mémoire qui sera rempli + adresse:=100*bfill; + dcount<=0; + etputget<=Fillmem; + PE_Instr_En<='0'; + when InitApp => + --code pour Init ici + --mettre mpi_init à l'adresse mpi + + PE_Ram_din<=MPI_INIT & x"0" ; + adresse:=core_init_adr; + + PE_Instr_En<='0'; + fsrc:=1; + adrToSet:=std_logic_vector(to_unsigned(core_init_adr,ADRLEN)); + if ret/=fsrc then + dcount<=0; + etputget<=writeptr; + adresse:=core_base_adr+2; + PE_Instr_En<='0'; + else + if Lib_instr_ack='1' then -- attente de la prise en compte de l'instruction + etputget<=InitCompleted; + PE_instr_en<='0'; + + else + PE_Instr_en<='1'; + end if; + + end if; + + when writeptr => + PE_Instr_En<='0'; + if PE_Hold_req = '0' then --s'assurer que le bus est disponible + + if dcount=0 then + PE_RAM_Din<=AdrToSet(Word-1 downto 0); + dcount <=dcount+1; + --adresse:=adresse+1; --prépare la prochaine écriture + elsif dcount=1 then + dcount <=dcount+1; + adresse:=adresse+1; --prépare la prochaine écriture + PE_RAM_Din<=AdrToSet(15 downto 8); + elsif dcount=2 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + ret:=fsrc; + dcount<=0; + timeout:=0; + + if fsrc=1 then + etputget <= InitApp; + elsif fsrc=2 then + etputget <= putdata; + elsif fsrc=3 then + etputget <= getdata; + else + etputget <= start; + end if; + + end if; + + end if; + When InstrCopy => + if Lib_instr_ack='1' then + etputget<=Writeptr; + PE_instr_en<='0'; + iack:='1'; + + else + PE_Instr_en<='1'; + end if; + + when InitCompleted => + + if Lib_Init='1' then + etputget<=putdata; + PE_Instr_En<='0'; + else + PE_Instr_En<='0'; + end if; + when putdata => --construire le packet pour le Put + DestRank:=1; + adresse_rd:=core_base_adr+Core_Rank2port_base+DestRank; + + PE_Instr_En<='0'; + timeout:=0; + dcount<=0; + fsrc:=2; + adrToSet:=std_logic_vector(to_unsigned(core_put_adr,ADRLEN)); + if ret/=fsrc then + adresse:=core_base_adr+2; + etputget<=writeptr; + ret:=0; + else + if Lib_instr_ack/='1' then + etputget<= putdata2; + end if; + end if; + + when putdata2 => + + if ramsel = '0' then --si le PE a accès à la RAM + dlen:=to_integer(unsigned(datalen)); + pMPI_put(clkm,destrank,SrcAdr1 & Srcadr0,DestAdr1 & DestAdr0,Dlen,sram,ct); + adresse:=to_integer(unsigned(sram.addr_wr)); + PE_ram_din<=sram.data_in; + dcount<=ct; + if dcount<=6 then +-- +-- PE_Instr_En<='0'; +-- if dcount=0 then +-- adresse:=core_put_adr; +-- PE_Ram_din<=MPI_PUT & std_logic_vector(to_unsigned(Dpid,4)); +-- elsif dcount=1 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=Datalen ; +-- elsif dcount=2 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=SrcAdr1 ; +-- elsif dcount=3 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=SrcAdr0 ; +-- elsif dcount=4 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=DestAdr1 ; +-- elsif dcount=5 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=DestAdr0 ; + elsif dcount=7 then --juste après la valeur 6 en fait +-- adresse:=core_base_adr+1; +-- adresse_rd:=core_base_adr; +-- PE_Ram_din<=x"01"; --instruction pulse enable; + PE_Instr_En<='1'; +-- + end if; +-- dcount<=dcount+1; +-- end if; + elsif PE_instr_En='0' then + timeout:=timeout+1; + if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire + ram_busy<='1'; + timeout:=0; + PE_Instr_En<='0'; + end if; + end if; + if dcount >=6 then + Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI + if Lib_instr_ack='1' then -- Instruction ack + PE_Instr_En<='0'; + if Ramsel='0' then + adresse:=core_base_adr+1; + PE_Ram_din<=x"00"; --ramener le IPulse à 0; + Ram_busy<='0'; + etPutGet<=putcompleted; + else + + Ram_busy<='1'; --force la prise du bus + end if; + else + + timeout:=timeout+1; + if timeout=150 then + etputget<=st_timeout; + end if; + end if; + end if; + + + when putcompleted => + adresse_rd:=core_put_adr+6; + if PE_Ram_do(0)='1' then --Put completed + etPutGet<=GetData; + end if; + PE_Instr_En<='0'; + when getdata => --positionnement du mot de longueur des données + + DestRank:=1; + timeout:=0; + dcount<=0; + fsrc:=3; + adrToSet:=std_logic_vector(to_unsigned(core_get_adr,ADRLEN)); + if ret/=fsrc then + adresse:=core_base_adr+2; + etputget<=writeptr; + ret:=0; + else + adresse:=core_get_adr; + etputget<= getdata2; + end if; + PE_Instr_En<='0'; + when getdata2 => + + if ramsel='0' then + + pMPI_get(clkm,destrank,SrcAdr1 & Srcadr0,DestAdr1 & DestAdr0,Dlen,sram,ct); + adresse:=to_integer(unsigned(sram.addr_wr)); + PE_ram_din<=sram.data_in; + dcount<=ct; + if dcount<=6 then + +-- if dcount<=0 then +-- adresse:=core_get_adr; +-- PE_Ram_din<=MPI_GET & std_logic_vector(to_unsigned(Dpid,4)); +-- elsif dcount=1 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=Datalen ; +-- elsif dcount=2 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=SrcAdr1 ; +-- elsif dcount=3 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=SrcAdr0 ; +-- elsif dcount=4 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=DestAdr1 ; +-- elsif dcount=5 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=DestAdr0 ; + + elsif dcount=7 then +-- adresse:=core_base_adr+1; + adresse_rd:=core_base_adr; + PE_Instr_En<='1'; +-- PE_Ram_din<=x"01"; --instruction pulse enable; + timeout:=0; + end if; +-- dcount<=dcount+1; +-- end if; + elsif PE_Instr_En='0'then + timeout:=timeout+1; + if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire + ram_busy<='1'; + timeout:=0; + PE_Instr_En<='0'; + end if; + end if; + + if dcount >=6 then + Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI + if Lib_instr_ack='1' then -- Instruction ack + PE_Instr_En<='0'; + if Ramsel='0' then + adresse:=core_base_adr+1; + PE_Ram_din<=x"00"; --ramener le IPulse à 0; + Ram_busy<='0'; + etPutGet<=getcompleted; + else + + Ram_busy<='1'; --force la prise du bus + end if; + else + + timeout:=timeout+1; + if timeout=150 then + etputget<=st_timeout; + end if; + end if; + + + end if; + + + + when getcompleted => + adresse_rd:=core_get_adr+6; + PE_Instr_En<='0'; + if PE_Ram_do(0)='1' then --Put completed + if Ramsel='0' then + adresse:=core_base_adr+1; + PE_Ram_din<=x"00"; --ramener le IPulse à 0; + etPutGet<=Terminate; + else + timeout:=timeout+1; + end if; + end if; + + + when terminate => + + + etputget<=start; + + when st_timeout => + + --if ram_busy='1' then + etputget<=start; + --end if + + etputget<=start; + end case; + pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,ADRLEN)); + pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,ADRLEN)); + end if; --reset='1' + end if; + end process pPutGet; + +majPutGet:process (etputget) + + begin + case etputget is + when start => + + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + when fillmem => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + when nextfill => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + when InitApp => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + when Initcompleted => + --PE_Instr_En<='1'; + when writeptr => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + -- dcount<=dcount+1; + + --PE_Instr_En<='0'; + when InstrCopy => --instruction copy + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + + + when putdata => --positionnement du mot de longueur des données + --dcount<=0; + srcadr0<=X"00"; + srcadr1<=X"01"; + destadr0<=X"00"; + destadr1<=X"02"; + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + --lecture du n° de port de destination + PE_Ram_enb<='1'; + datalen<=std_logic_vector(to_unsigned(50,8)); + dpid_i<=to_integer(unsigned(PE_ram_do(3 downto 0))); --le port est situé ur les 4 bits de poids faible + --PE_Instr_En<='0'; + when putdata2 => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + -- dcount<=dcount+1; + if dcount>=5 then + --PE_Instr_En<='1'; + else + --PE_Instr_En<='0'; + end if; + when putcompleted => + PE_Ram_we <='1'; + PE_Ram_ena <='1'; + -- lecture du résultat + PE_Ram_enb <='1'; + --PE_Instr_En<='1'; + when getdata => + --dcount<=0; + srcadr0<=X"00"; + srcadr1<=X"02"; + destadr0<=X"00"; + destadr1<=X"03"; + datalen<=std_logic_vector(to_unsigned(50,8)); + --PE_Instr_En<='0'; + when getdata2 => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + --dcount<=dcount+1; + if dcount=5 then + --PE_Instr_En<='1'; + else + --PE_Instr_En<='0'; + end if; + when getcompleted => + PE_Ram_we <='1'; + PE_Ram_ena <='1'; + -- lecture du résultat + PE_Ram_enb <='1'; + --PE_Instr_En<='1'; + when terminate => + + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + when st_timeout => + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + end case; + +end process majPutGet ; + + hold:process (pe_hold_req,clkm,reset) + begin + if rising_edge(clkm) then + if reset='1' then + pe_hold_ack<='0'; + else + if pe_hold_req='1' then + ramsel<=not(ram_busy); + pe_hold_ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération + else + pe_hold_ack<='0'; + ramsel<='0'; + end if; + end if; + end if; + end process hold; +END; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_CORE_SCHEDULER.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_CORE_SCHEDULER.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_CORE_SCHEDULER.vhd (revision 138) @@ -0,0 +1,135 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:16:03 06/13/2011 +-- Design Name: +-- Module Name: MPI_CORE_SCHEDULER - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity MPI_CORE_SCHEDULER is + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC; + instruction_fifo_empty : in STD_LOGIC; + instruction_fifo_data : in STD_LOGIC_VECTOR (7 downto 0); + instruction_available : out STD_LOGIC; + + get_request_fifo_data : in STD_LOGIC_VECTOR (7 downto 0); + get_request_fifo_empty : in STD_LOGIC; + instruction_fifo_rd_en : out STD_LOGIC; + get_request_fifo_rd_en : out STD_LOGIC; + + fifo_selected : out STD_LOGIC; + fifo_empty : out STD_LOGIC; + fifo_rd_en : in STD_LOGIC; + data_out : out STD_LOGIC_VECTOR (7 downto 0) + ); +end MPI_CORE_SCHEDULER; + +architecture Behavioral of MPI_CORE_SCHEDULER is + +signal sel_signal : std_logic; +-- declaration des composants du scheduler +COMPONENT CDEMUX1 + PORT( + di : IN std_logic; + sel : IN std_logic; + do1 : OUT std_logic; + do2 : OUT std_logic + ); + END COMPONENT; + +COMPONENT CMUXP1 + PORT( + di1 : IN std_logic; + di2 : IN std_logic; + sel : IN std_logic; + do : OUT std_logic + ); + END COMPONENT; + +COMPONENT CMUX8 + PORT( + di1 : IN std_logic_vector(7 downto 0); + di2 : IN std_logic_vector(7 downto 0); + sel : IN std_logic; + do : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + +COMPONENT round_robbin_machine + PORT( + get_request_fifo_empty : IN std_logic; + instruction_fifo_empty : IN std_logic; + priority_rotation : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + fifo_selected : OUT std_logic; + instruction_available : OUT std_logic; + mux_sel : OUT std_logic + ); +END COMPONENT; +begin +-- instances des composants + + +mpi_core_rr_machine: round_robbin_machine PORT MAP( + get_request_fifo_empty => get_request_fifo_empty, + instruction_fifo_empty => instruction_fifo_empty, + priority_rotation => priority_rotation , + clk => clk, + fifo_selected => fifo_selected, + instruction_available => instruction_available , + reset => reset, + mux_sel => sel_signal + ); + + +Fifo_empty_MUX: CMUXP1 PORT MAP( + di1 => instruction_fifo_empty , + di2 => get_request_fifo_empty, + do => fifo_empty, + sel => sel_signal + ); + + + +rd_en_demux: CDEMUX1 PORT MAP( + di => fifo_rd_en , + sel => sel_signal, + do1 => instruction_fifo_rd_en, + do2 => get_request_fifo_rd_en + ); + +data_MUX8: CMUX8 PORT MAP( + di1 => instruction_fifo_data , + di2 => get_request_fifo_data, + sel => sel_signal, + do => data_out + ); + + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_NOC.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_NOC.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_NOC.vhd (revision 138) @@ -0,0 +1,172 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:05:07 11/19/2011 +-- Design Name: +-- Module Name: MPI_NOC - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library NocLib ; + +use NocLib.CoreTypes.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity MPI_NOC is +generic (NPROC : positive:=4); + port( + + MPI_Node_in : in Ar_MPIPort_in(1 to NPROC); + MPI_Node_Out : out Ar_MPIPort_out(1 to NPROC) + ); +end MPI_NOC; + +architecture structural of MPI_NOC is +-- Declare signals for interconnections + +--constant NPROC : positive :=8 ; + --Inputs + signal noc_portOut :typ_portio(1 to NPROC); + signal noc_portIn :typ_portio(1 to NPROC); + + signal noc_fifo_in_full : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_data_available : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_fifo_in_empty : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_data_in_en : std_logic_vector(NPROC downto 1) := (others => '0'); + signal noc_cmd_in_en : std_logic_vector(NPROC downto 1) := (others => '0'); + signal noc_data_out_en : std_logic_vector(NPROC downto 1) := (others => '0'); + -- signal noc_clk : std_logic := '0'; + --signal noc_reset : std_logic := '0'; + +-- Declare components +COMPONENT SWITCH_GEN + GENERIC (number_of_ports : positive := NPROC); + PORT( + Port_in : IN typ_PortIO(1 to number_of_ports); + Port_out : OUT typ_PortIO(1 to number_of_ports); + data_in_en : IN std_logic_vector(NPROC downto 1); + cmd_in_en : IN std_logic_vector(NPROC downto 1); + data_out_en : IN std_logic_vector(NPROC downto 1); + fifo_in_full : OUT std_logic_vector(NPROC downto 1); + fifo_in_empty : OUT std_logic_vector(NPROC downto 1); + data_available : OUT std_logic_vector(NPROC downto 1); + clk : IN std_logic; + reset : IN std_logic + ); + END COMPONENT; + COMPONENT CORE_MPI is + Port ( instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + instruction_en : in STD_LOGIC; + + barrier_completed : out STD_LOGIC; + packet_received : out STD_LOGIC; + packet_ack : in std_logic; + PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); + ram_we : out STD_LOGIC; + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_address_wr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_in_wr_en : out STD_LOGIC; -- OK (au switch) pour lire les données + switch_port_in_empty : in STD_LOGIC; + switch_port_in_cmd_en : out STD_LOGIC; + switch_port_in_full : in STD_LOGIC; -- port d'entréendu switch saturé + switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); -- port de donées d'entrée + switch_port_out_rd_en : out STD_LOGIC; -- OK (au switch) pour écrire les données + switch_port_out_data_vailaible : in STD_LOGIC; -- Donnée disponible à la sortie (du switch) + clk : in STD_LOGIC; + clkout : out std_logic; + reset : in STD_LOGIC; + ram_en : out STD_LOGIC; + instruction_fifo_full : out STD_LOGIC; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0)); + end COMPONENT; +-- cette fonction met en place l'architecture d'exécution de l'environnement +-- elle permet de construire le Noc et de connecter les différents core MPI +-- chaque core reçoit un ID qui sera son Rank lors de l'appel à MPI_GET_Rank +-- faut il créer une petite mémoire chargée de stocker les IDs ? +-- Oui car cette mémoire sera consultée par la fonction MPI_Init pour associer +-- un communicateur au MPI Core + + + + begin +Socsyst: if nproc > 1 generate --nproc + -- instancier le switch et connecter les différents ports + +sw_gen1: SWITCH_GEN generic map (NPROC) + PORT MAP ( + Port_in => Noc_PortIn, + + Port_out => noc_Portout, + + --signaux de contrôle de la lecture des ports + data_in_en => noc_data_in_en, + cmd_in_en => noc_cmd_in_en, + data_out_en => noc_data_out_en, + fifo_in_full => noc_fifo_in_full, + fifo_in_empty => noc_fifo_in_empty, + data_available => noc_data_available, + clk => MPI_Node_in(1).clk, + reset => MPI_Node_in(1).reset + ); + end generate; +HCL_c: for i in 1 to nproc generate -- nproc + hardmpi:core_mpi port map ( + + + PushOut=>MPI_Node_out(i).PushOut, + ram_we=> MPI_Node_out(i).ram_we, + ram_en=>MPI_Node_out(i).ram_en , + hold_req=>MPI_NODE_out(i).hold_req, + packet_received=>MPI_Node_out(i).packet_received , + packet_ack=>MPI_Node_in(i).packet_ack, + hold_ack=>MPI_NODE_in(i).hold_ack, + ram_address_rd => MPI_Node_out(i).ram_address_rd , + ram_address_wr => MPI_Node_out(i).ram_address_wr , + ram_data_in=>MPI_Node_out(i).ram_data_in , + ram_data_out=>MPI_Node_in(i).ram_data_out, + barrier_completed =>MPI_Node_out(i).barrier_completed, + instruction => MPI_Node_in(i).instruction, + instruction_en => MPI_Node_in(i).instruction_en, + instruction_fifo_full =>MPI_Node_Out(i).instruction_fifo_full, + switch_port_in_wr_en => noc_data_in_en(i), + switch_port_in_cmd_en=>noc_cmd_in_en(i), + switch_port_in_full => noc_fifo_in_full(i), + switch_port_in_empty => noc_fifo_in_empty(i), + switch_port_in_data => noc_PortIn(i), + switch_port_out_rd_en => noc_data_out_en(i), + switch_port_out_data_vailaible => noc_data_available(i), + switch_port_out_data => noc_PortOut(i), + clk =>MPI_Node_in(1).clk, + reset =>MPI_Node_in(1).reset + + ); + end generate; + + + + +end Structural; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_PKG.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_PKG.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_PKG.vhd (revision 138) @@ -0,0 +1,127 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +Library NocLib; +use NocLib.CoreTypes.all; +package mpi_pkg is +-- Declare constants + +-- constant : time := ns; + constant NPROC : positive:= 8; + +-- type declaration +type portio is array(1 to NPROC) of std_logic_vector (Word-1 downto 0); +-- type is +-- record +-- : std_logic_vector( Word-1 downto 0); +-- : std_logic; +-- end record; + + +-- Declare signals for interconnections + + + --Inputs + signal noc_portOut :portio; + signal noc_portIn :portio; + + signal noc_fifo_in_full : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_data_available : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_fifo_in_empty : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_data_in_en : std_logic_vector(NPROC downto 1) := (others => '0'); + signal noc_data_out_en : std_logic_vector(NPROC downto 1) := (others => '0'); + signal noc_clk : std_logic := '0'; + signal noc_reset : std_logic := '0'; + +-- Declare components +COMPONENT SWITCH_GENERIQUE + GENERIC (number_of_ports : positive := 8); + PORT( + Port1_in : IN std_logic_vector(Word-1 downto 0); + Port2_in : IN std_logic_vector(Word-1 downto 0); + Port3_in : IN std_logic_vector(Word-1 downto 0); + Port4_in : IN std_logic_vector(Word-1 downto 0); + Port5_in : IN std_logic_vector(Word-1 downto 0); + Port6_in : IN std_logic_vector(Word-1 downto 0); + Port7_in : IN std_logic_vector(Word-1 downto 0); + Port8_in : IN std_logic_vector(Word-1 downto 0); + Port9_in : IN std_logic_vector(Word-1 downto 0); + Port10_in : IN std_logic_vector(Word-1 downto 0); + Port11_in : IN std_logic_vector(Word-1 downto 0); + Port12_in : IN std_logic_vector(Word-1 downto 0); + Port13_in : IN std_logic_vector(Word-1 downto 0); + Port14_in : IN std_logic_vector(Word-1 downto 0); + Port15_in : IN std_logic_vector(Word-1 downto 0); + Port16_in : IN std_logic_vector(Word-1 downto 0); + Port1_out : OUT std_logic_vector(Word-1 downto 0); + Port2_out : OUT std_logic_vector(Word-1 downto 0); + Port3_out : OUT std_logic_vector(Word-1 downto 0); + Port4_out : OUT std_logic_vector(Word-1 downto 0); + Port5_out : OUT std_logic_vector(Word-1 downto 0); + Port6_out : OUT std_logic_vector(Word-1 downto 0); + Port7_out : OUT std_logic_vector(Word-1 downto 0); + Port8_out : OUT std_logic_vector(Word-1 downto 0); + Port9_out : OUT std_logic_vector(Word-1 downto 0); + Port10_out : OUT std_logic_vector(Word-1 downto 0); + Port11_out : OUT std_logic_vector(Word-1 downto 0); + Port12_out : OUT std_logic_vector(Word-1 downto 0); + Port13_out : OUT std_logic_vector(Word-1 downto 0); + Port14_out : OUT std_logic_vector(Word-1 downto 0); + Port15_out : OUT std_logic_vector(Word-1 downto 0); + Port16_out : OUT std_logic_vector(Word-1 downto 0); + data_in_en : IN std_logic_vector(8 downto 1); + data_out_en : IN std_logic_vector(8 downto 1); + fifo_in_full : OUT std_logic_vector(8 downto 1); + fifo_in_empty : OUT std_logic_vector(8 downto 1); + data_available : OUT std_logic_vector(8 downto 1); + clk : IN std_logic; + reset : IN std_logic + ); + END COMPONENT; + COMPONENT CORE_MPI is + Port ( instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + instruction_en : in STD_LOGIC; + ram_data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + barrier_completed : out STD_LOGIC; + packet_received : out STD_LOGIC; + packet_ack : in std_logic; + PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); + ram_we : out STD_LOGIC; + ram_address : out STD_LOGIC_VECTOR (15 downto 0); + ram_data_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_in_wr_en : out STD_LOGIC; -- OK (au switch) pour lire les données + switch_port_in_full : in STD_LOGIC; -- port d'entréendu switch saturé + switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); -- port de donées d'entrée + switch_port_out_rd_en : out STD_LOGIC; -- OK (au switch) pour écrire les données + switch_port_out_data_vailaible : in STD_LOGIC; -- Donnée disponible à la sortie (du switch) + clk : in STD_LOGIC; + reset : in STD_LOGIC; + ram_en : out STD_LOGIC; + instruction_fifo_full : out STD_LOGIC; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0)); + end COMPONENT; +-- declare functions and procedure + +end MPI_PKG; + + +package body MPI_PKG is + +-- Example 1 + + + +-- cette fonction met en place l'architecture d'exécution de l'environnement +-- elle permet de construire le Noc et de connecter les différents core MPI +-- chaque core reçoit un ID qui sera son Rank lors de l'appel à MPI_GET_Rank +-- faut il créer une petite mémoire chargée de stocker les IDs ? +-- Oui car cette mémoire sera consultée par la fonction MPI_Init pour associer +-- un communicateur au MPI Core + + +end MPI_PKG; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_RMA.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_RMA.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_RMA.vhd (revision 138) @@ -0,0 +1,1778 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +use work.PACKET_TYPE.all; + +package Mpi_Rma is +procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural;signal SysRam :out typ_dpram); +procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram); +procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural); + +procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural); +procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector ); + +procedure pMPI_Win_create(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; + info:natural; comm:Mpi_Comm; Win: inout MPI_Win ); +procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win); +procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win); +procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win); +procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win); +procedure pMPI_Comm_Spawn(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; +command : natural; argv :natural; maxprocs : natural; info : natural; root : natural; comm : natural; +signal intercomm :out natural; signal array_of_errcodes : out natural); +-- declare functions and procedure + procedure ReadMem( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; data: out std_logic_vector); +procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; Data:in std_logic_vector); + +procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + variable AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic); + +end MPI_Rma; + + +package body MPI_Rma is +----int MPI_Put( +-- void *origin_addr, +-- int origin_count, +-- MPI_Datatype origin_datatype, +-- int target_rank, +-- MPI_Aint target_disp, +-- int target_count, +-- MPI_Datatype target_datatype, +-- MPI_Win win +--); +-- Example 1 +procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural) is +variable i,dcount,wr_state : natural:=0; +variable adresse :natural; +variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr; +variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp; +variable put_adr : std_logic_vector (ADRLEN-1 downto 0); +variable config_reg: std_logic_vector (Word-1 downto 0); +constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0'); + begin + put_adr:=conv_Std_logic_vector(Core_put_adr,ADRLEN); + + addr1:=Orig_Addr; + addr2:=Target_Disp; + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + end if; +-- + + if rising_edge(clkin) then + if dcount= 0 then + dcount:=dcount+1; + Interf.S.Intstate1<=0; + elsif dcount>=1 and dcount <=3 then + if interf.I.ramsel='0' then + Interf.O.membusy<='0'; + --SysRam.O.we<='1'; + --SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + wr_state:=interf.S.Intstate1; + WritePtr (put_adr,wr_state,SysRam); + interf.S.Intstate1<=wr_state; + if wr_state =0 then + -- fin de l'écriture du pointeur en mémoire + dcount:=4; + end if; + end if; + + elsif dcount=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + if target_rank <=15 then --limitation de cete version à 16 rang + Interf.S.Gstart(Target_rank)<='1'; + end if; + adresse:=core_put_adr; + SysRam.O.Data_in<=MPI_PUT & conv_std_logic_vector(Target_Rank,4); --code fonction + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=5 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+1; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + Interf.O.Instruction<=x"06"; -- nombre de mots de l'instruction + end if; + elsif dcount=6 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+2; + SysRam.O.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=7 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+3; + SysRam.O.Data_in<=Addr1(Word-1 downto 0); --source Bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=8 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+4; + SysRam.O.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=9 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+5; + SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=10 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + if interf.I.ramsel='0' then + adresse:=core_base_adr+1; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire; + Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction + Interf.O.membusy<='0'; + dcount:=dcount+1; + end if; + elsif dcount=11 then + if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ? + Interf.O.Instr_En<='0'; --désactiver la prise en compte de l'instruction + dcount:=dcount+1; + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + else + Interf.O.Instr_En<='1'; + end if; + adresse:=core_base_adr+1; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + --SysRam.O.Ram_busy<='0'; --?? + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer la lecture du résultat du Put + SysRam.O.enb<='1'; + elsif dcount=12 then + adresse:=core_base_adr+1; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du Put + SysRam.O.enb<='1'; + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=13 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du Put + SysRam.O.enb<='0'; + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + adresse:=core_base_adr+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=14 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_put_adr+6,Adrlen)); + if SysRam.I.Data_out(0)='1' then --fin du MPI PUT ici pour l'envoie ! + dcount:=dcount+1; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + Interf.S.Intstate2<=255; --timer pour la réception + interf.s.tmem(0)<=x"02"; + report "MPV pMPI_PUT():Ex1 de HCL a répondu concernant l'envoi"; + end if; + end if; + elsif dcount=15 or dcount=16 or dcount=17 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + -- ce cycle permet d'attendre la donnée en sortie après le changement d'adresse + + if interf.I.ramsel='0' then + dcount:=dcount+1; -- ce cycle permet d'attendre la donnée en sortie après le changement d'adresse + + elsif Interf.S.Intstate2>0 then + dcount:=15; + Interf.S.Intstate2<=Interf.S.Intstate2-1; + elsif interf.s.tmem(0)>0 then + interf.s.tmem(0)<=interf.s.tmem(0)-1; + Interf.S.Intstate2<=255; + dcount:=15; + else + dcount:=1;--recommencer l'envoi + end if; + elsif dcount=18 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + if SysRam.I.Data_out(5)='1' then --Message du MPI PUT bien reçu ! + dcount:=dcount+1; + report "MPV pMPI_PUT():Ex2 de HCL a reçu un acquittement concernant l'envoi"; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + elsif Interf.S.Intstate2>0 then + Interf.S.Intstate2<=Interf.S.Intstate2-1; + elsif interf.s.tmem(0)>0 then + interf.s.tmem(0)<=interf.s.tmem(0)-1; + Interf.S.Intstate2<=255; + else + dcount:=1;--recommencer l'envoi + report "MPV pMPI_PUT():Timeout EX2 n'a pas reçu d'acquitement concernant l'envoi. reémission en cours..."; + end if; + else + dcount:=15; + end if; + elsif dcount=19 then + dcount:=0; --fin normale de la fonction + Interf.O.membusy<='0'; + report "MPV pMPI_PUT():fin normale de la fonction"; + end if; + + + NExtCtx:=dcount; + end if; + end procedure; + +procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural) is +variable i,wcount,dcount : natural range 0 to 255:=0; +variable adresse :natural; +variable wdata: std_logic_vector(Word-1 downto 0):=(others=>'0'); +variable bitval : std_logic:='0'; +variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr; +variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp; +variable get_adr : std_logic_vector (ADRLEN-1 downto 0); +variable config_reg,win_reg: std_logic_vector (Word-1 downto 0); +constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0'); + begin + get_adr:=Std_logic_vector(to_unsigned(Core_get_adr,ADRLEN)); + + addr1:=Orig_Addr; + addr2:=Target_Disp; + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + end if; +-- + + if rising_edge(clkin) then + + if dcount =0 then + dcount:=dcount+1; + Interf.S.IntState1<=0; + elsif dcount>=1 and dcount <=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + wcount:=Interf.S.IntState1; + WritePtr (get_adr,wcount,SysRam); + Interf.S.IntState1<=wcount; + Interf.O.membusy<='1'; + if wcount =0 then + dcount:=4; + Interf.S.Intstate1<=1; + end if; + else + Interf.S.IntState1<=0; + + end if; + + elsif dcount=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if target_rank <=15 then --limitation de cete version à 16 rang + Interf.S.Gstart(Target_rank)<='1'; + end if; + adresse:=core_get_adr; + SysRam.O.Data_in<=MPI_GET & conv_Std_logic_vector(Target_Rank,4); --code fonction + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + dcount:=dcount+1; + end if; + elsif dcount=5 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+1; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + interf.O.Instruction<=x"06"; --le nbre de mots de l'intstruction + dcount:=dcount+1; + end if; + elsif dcount=6 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+2; + SysRam.O.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + dcount:=dcount+1; + + end if; + elsif dcount=7 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+3; + SysRam.O.Data_in<=Addr1(Word-1 downto 0); --source Bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + dcount:=dcount+1; + end if; + elsif dcount=8 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+4; + SysRam.O.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + dcount:=dcount+1; + end if; + elsif dcount=9 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+5; + SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + dcount:=dcount+1; + end if; + elsif dcount=10 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+7; + SysRam.O.Data_in<=x"00"; -- résultat du GET + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + Interf.S.IntState2<=0; + dcount:=dcount+1; + end if; + elsif dcount=11 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + addr1:=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + wcount:=Interf.S.IntState2; + wdata:=x"01";bitval:='1'; + setBit(wcount,Interf,SysRam,addr1(ADrLen-1 downto 0),wdata,bitval); + Interf.S.IntState2<=wcount; + if wcount=0 then + dcount:=dcount+1; + Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction + end if; + + elsif dcount=12 then + if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ? + Interf.O.Instr_En<='0'; --désactiver la prise en compte de l'instruction + dcount:=dcount+1; + config_reg:=SysRam.I.Data_out and x"f6"; + --SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + end if; + adresse:=core_base_adr+1; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + --SysRam.O.Ram_busy<='0'; --?? + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer la lecture du résultat du get + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + elsif dcount=13 then + + adresse:=core_base_adr+1; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du get + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + Interf.s.IntState2<=255; + Interf.s.tmem(0)<=x"08"; --tempo pour l'attente du résultat de Get + elsif dcount=14 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du GET + SysRam.O.enb<='0'; + adresse:=core_base_adr+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=18;--dcount+1; + Interf.O.membusy<='1'; + + end if; + elsif dcount=15 then + + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer l'écriture du WBusy + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy + SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + elsif dcount=16 then + + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer l'écriture du WBusy + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy + SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy + dcount:=dcount+1; + Interf.O.membusy<='1'; + + end if; + elsif dcount=17 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du GET + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; + SysRam.O.Data_in<=config_reg ; --; + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + elsif dcount>=18 and dcount <=21 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_get_adr+6,Adrlen)); + if SysRam.I.Data_out(0)='1' then --fin du MPI get ici pour l'envoie ! + dcount:=dcount+1; + end if; + end if; + elsif dcount>=22 and dcount <=24 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + if SysRam.I.Data_out(5)='1' then --Message du MPI Get bien reçu ! + dcount:=dcount+1; --ce test est fait avant l'arrivée effective des données ce qui pose problème ! + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + elsif Interf.S.Intstate2>0 then + Interf.S.Intstate2<=Interf.S.Intstate2-1; + elsif interf.s.tmem(0)>0 then + interf.s.tmem(0)<=interf.s.tmem(0)-1; + Interf.S.Intstate2<=255; + else + dcount:=1;--recommencer l'envoi + end if; + end if; + + elsif dcount=25 then + dcount:=0; --fin normale de la fonction + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + end if; + + NExtCtx:=dcount; + end if; + end procedure; +Procedure pMPI_Comm_group(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; COMM :in MPI_Comm; signal grp : out Mpi_group ) is +Begin +--cette procédure permet de récupérer le groupe qui est associé à un communicateur +--dans notre cas c'est la récupération du groupe associé à COMM_WORLD +end procedure; +--int MPI_Group_incl(MPI_Group group, int n, int *ranks, +-- MPI_Group *newgroup) +Procedure pMPI_group_incl(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; + GRP: Mpi_group; n:natural;ranks :natural; newgroup: out Mpi_group) is +Begin +-- cette procedure a pour algo de parcourir les rangs qui sont dans la mémoire pointée par ranks +-- et d'activer l'un des bits de position de newgroup. +-- +-- +end procedure; + +procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector ) is +variable adresse_rd : natural range 0 to 2**ADRLEN-1; + +begin + + if NextCtx =0 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + + NextCtx:=1; + + elsif NextCtx=1 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + NextCtx:=2; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=2 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); + NextCtx:=3; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=3 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); + NextCtx:=4; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=4 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); + NextCtx:=0; + Interf.O.membusy<='0'; + end if; + end if; +end procedure; + +--int MPI_Win_create( +-- void *base, +-- MPI_Aint size, +-- int disp_unit, +-- MPI_Info info, +-- MPI_Comm comm, +-- MPI_Win *win +--); +procedure pMPI_Win_create(NextCtx : inout natural ;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; + info:natural; comm:Mpi_Comm; Win: inout MPI_Win ) is + -- parcours de la liste des fenêtres existantes à la recherche d'un emplacement libre + -- si fenêtre libre trouvée, et + -- mise à 1 du Bit WCreate du registre status + type wtype is array (1 to 4 ) of natural range 0 to 255; + variable AdrWin: std_logic_vector(ADRLEN-1 downto 0); + variable adresse : std_logic_vector(ADRLEN-1 downto 0); + variable clkin : std_logic:='1'; + variable wcreate_adr : std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_wcreate_adr,ADRLEN)); + variable w0 : std_logic_vector(Word-1 downto 0); + variable adrnat : natural; + variable sizewin : std_logic_vector(Word-1 downto 0); + variable count : natural range 0 to 255; + variable wdisp :wtype:=(4,14,24,34); --stocke l'adresse de la prochaine Win libre +begin +-- création d'une fenêtre il s'agit d'affecter l'objet Win et de retourner +-- le pointeur qui permet de le décrire + + +If NextCtx=0 then + NExtCtx:=NextCtx+1; + count:=0; + Interf.O.membusy<='0'; + Interf.S.IntState1<=count; +elsif NextCtx>=1 and NextCtx <= 4 then + count:=Interf.S.IntState1; + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(NextCtx),16)); + readmem(count,interf,sysRam,AdrWin,w0); + if count=0 then + if w0(0)/='1' then -- cette fenêtre est libre + NextCtx:=6; --étape de la création de la fenêtre + Win.addr:=base; --l'adresse de la fenêtre + Win.id:=NextCtx; -- la référence provisoire de la fenêtre + Win.size:=Size; -- la taille de la fenêtre + + else + NextCtx:=NextCtx+1; + end if; + end if; + Interf.S.IntState1<=count;--sauvegarde du statut de la sous-procédure + +elsif NextCtx=5 then + -- Plus de fenêtre disponible erreur + NextCtx:=1; -- boucle sans fin :) + Win.id:=0; + Win.addr:=x"0000"; +elsif NextCtx=6 then + --Affectation de l'objet Windows car une place est disponible + count:=Interf.S.IntState1; + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + Writemem(count,interf,SysRam,AdrWin,x"01"); --signal status pour created + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + +elsif NextCtx=8 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + interf.S.winid<=interf.S.winid+1; + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,AdrWin+1,stdlv(interf.S.winid,8)); --win id de la fenêtre + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=9 then + + adrnat:=Core_base_adr+Wdisp(Win.id); + + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + count:=Interf.S.IntState1; + + + Writemem(count,interf,SysRam,AdrWin+2,base(7 downto 0)); --adresse basse + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=10 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,AdrWin+3,base(15 downto 8)); --adresse haute + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=11 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + sizewin:=std_logic_vector(to_unsigned(size,8)); + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,AdrWin+4,sizewin); -- taille de la fenêtre + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=12 then + --cette étape consiste à envoyer le message WINCREATE Sur le réseau et à récupérer + -- les informations donnant le numéro de la fenêtre + W0:=MPI_WIN_CREATE & std_logic_vector(to_unsigned(0,4)); --code fonction + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,wcreate_adr,w0); + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + + elsif NextCtx=13 then + w0:=std_logic_vector(to_unsigned(Win.Id,8)); -- id proposé pour la fenêtre en création + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,wcreate_adr+1,w0); + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=14 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + count:=Interf.S.IntState1; + if interf.I.ramsel='0' then + WritePtr (wcreate_adr,count,SysRam); --écriture du pointeur d'instruction + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + end if; + elsif NextCtx=15 then + -- il faut mettre instruction_en à 1 + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + adresse:=stdlv(core_base_adr+1); + SysRam.O.addr_rd<=adresse; + SysRam.O.Addr_wr<=adresse; + SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire; + Writemem(count,interf,SysRam,adresse,x"01"); + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + Interf.O.Instr_En<='1'; + adresse:=stdlv(core_base_adr); + SysRam.O.Addr_rd<=adresse; + NextCtx:=NextCtx+1; + elsif NextCtx=16 then --acquittement de la copie des données dans le tampon de la lib + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=NextCtx+1; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + elsif NextCtx=17 then + -- lecture du résultat de l'instruction + + +else + +end if; +end procedure; +--int MPI_Win_start( +-- MPI_Group group, +-- int assert, +-- MPI_Win win +--); +procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is +--cette fonction active les bits WStart pour chaque processus avec lequel +-- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à +--chacune de ces cibles + variable dcount : natural range 0 to 255:=0; + variable cstatus : std_logic_vector(Word-1 downto 0); + begin + + -- retour de l'adresse de de la fenêtre dans la structure Win + -- initialisation des bits concernant + + if NextCtx =0 then + NextCtx:=NextCtx+1; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + SysRam.O.Data_in<=x"01"; --mise à 1 du bit WSTART et remise à zero de tous les autres Bits + + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + Interf.S.GStart<=(others=>'0'); + end if; + elsif NextCtx=2 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + SysRam.O.Data_in<=x"01"; + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + SysRam.O.Data_in<=x"01"; + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=4 then + NextCtx:=0; + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + end if; + + + end procedure; +procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is +variable adresse :natural; +variable wcount: natural range 0 to 255:=0; +variable LRam : typ_dpRam; +variable SyncDest,i : natural range 0 to 15; --destination du message de synchronisation +variable W0 :std_logic_vector(Word-1 downto 0); +variable wcompl_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN)); + +begin + -- + wcompl_adr:=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN)); + LRam:=SysRam; -- nécessaire pour le débogage + if NextCtx =0 then + + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + Interf.O.MemBusy<='1'; --occuper la mémoire + Interf.S.IntState1<=0; + NextCtx:=1; + adresse:=core_wcompl_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + + elsif NextCtx=1 then --écriture du ptr d'intruction + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if interf.I.ramsel='0' then + + adresse:=core_wcompl_adr; + + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + wcount:=Interf.S.IntState1; + WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir + Interf.S.IntState1<=wcount; + + if wcount =0 then + NextCtx:=2; + Interf.S.IntState1<=0; + Interf.S.IntState2<=0; + Interf.S.tmem(0)<=Interf.S.GStart(7 downto 0); --cibles impactées + Interf.S.tmem(1)<=Interf.S.GStart(15 downto 8); --cibles impactées + adresse:=core_wcompl_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + end if; + else + Interf.S.IntState1<=0; --recommencer l'écriture du pointeur + end if; + elsif NextCtx=2 then + if Interf.I.Ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr; + NextCtx:=10; --aller à la fin de la fonction + i:=0; + l1:for i in 0 to 7 loop + -- i:=i+1; + if i>=interf.s.intState2 then + if interf.s.gstart(i)='1' then + SysRam.O.Data_in<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4)); + Interf.S.tmem(2)<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4)); + + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.S.tmem(0)(i)<='0'; --ce dest a été traité ! + NextCtx:=4; + Interf.S.IntState2<=i+1; + exit l1; + end if; + end if; + exit l1 when i=7; + end loop l1; + end if; + elsif NextCtx=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr; + wcount:=Interf.S.IntState1; + WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir + Interf.S.IntState1<=wcount; + SysRam.O.Data_in<= Interf.S.tmem(2); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if wcount=0 then + NextCtx:=NextCtx+1; + end if; + end if; + elsif NextCtx=4 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr+1; + SysRam.O.Data_in<= x"04" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + elsif NextCtx=5 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr+2; + Interf.O.Instruction<=x"04";--longueur de l'instruction + SysRam.O.Data_in<=x"00" ;-- + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=6; + elsif NextCtx=6 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr+3; + SysRam.O.Data_in<= SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=7; + elsif NextCtx=7 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + adresse:=core_wcompl_adr+3; + SysRam.O.Data_in<=SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + + elsif NextCtx=8 then --fin de la fonction + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + --dcount:=0; + Interf.O.membusy<='0'; + Interf.O.Instr_En<='1'; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr+5,AdrLen)); + NextCtx:=NextCtx+1; + elsif NextCtx=9 then --acquittement de la copie des données dans le tampon + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=10; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + + elsif NextCtx=10 then --lecture de la fin de WComplete + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.S.IntState2=0 then --aucune instruction MPI exécutée ? + NextCtx:=12; + elsif Interf.S.tmem(0)/=0 then --plus de message compl à envoyer + NextCtx:=2; + elsif Interf.S.tmem(0)=0 then + if interf.I.ramsel='0' then + NextCtx:=NextCtx+1; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + end if; + end if; + elsif NextCtx=11 then --test de la fin des transferts + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + if SysRam.I.Data_out(0)='1' and SysRam.I.Data_out(6)='0' then --si WStart=1 et Wbusy=0 + --il faut un DSent=1 pour Put ou un DSending pour Get + if SysRam.I.Data_out(5)='1' or (SysRam.I.Data_out(4)='1' and SysRam.I.Data_out(1)='1') then + NextCtx:=NextCtx+1; + end if; + end if; + + end if; + elsif NextCtx=12 then + Interf.S.IntState1<=0; -- initialisation du compteur d'état + Interf.S.IntState2<=0; + SysRam.O.enb<='0'; + NextCtx:=0; --fin de la fonction + end if; + +end procedure; +procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is +--cette fonction active les bits WStart pour chaque processus avec lequel +-- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à +--chacune de ces cibles + variable W_Ptr : natural range 0 to 65535:=0;--adresse de la fenêtre en mémoire + variable dcount : natural range 0 to 255:=0; + variable cstatus : std_logic_vector(Word-1 downto 0); + begin + + -- retour de l'adresse de de la fenêtre dans la structure Win + -- initialisation des bits concernant + if Win.id =0 then + W_ptr:=Core_Base_Adr+4; + end if; + if NextCtx =0 then + + if pgroup.grp=0 then --rien à faire + nextCtx:=5; + Interf.S.GPost<=(others=>'0'); + else + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + SysRam.O.Data_in<=x"48"; --mise à 1 du bit WPOST et WBusy et remise à zero de tous les autres Bits + + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + + end if; + --limitation de cete version à 16 rang + Interf.S.GPost<=pgroup.grp; + elsif NextCtx=2 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + SysRam.O.Data_in<=x"48"; --mise à 1 du bit WPOST et WBusy et remise à zero de tous les autres Bits + + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + + end if; + elsif NextCtx=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_Ptr+W_Gpost,Adrlen)); + SysRam.O.Data_in<=pgroup.grp(7 downto 0); + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; +elsif NextCtx=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_Gpost+1,Adrlen)); + SysRam.O.Data_in<=pgroup.grp(15 downto 8); + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; +elsif NextCtx=6 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_Gpost+1,Adrlen)); + SysRam.O.Data_in<=pgroup.grp(15 downto 8); + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=5 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + NextCtx:=0; + Interf.O.membusy<='0'; + end if; + + + end procedure; + + procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is +--permet de synchroniser la fin des opérations sur une fenêtre +variable dcount : natural range 0 to 255:=0; +variable cstatus : std_logic_vector(Word-1 downto 0); +variable W_Ptr : natural range 0 to 65535:=0;--adresse de la fenêtre en mémoire +begin + W_Ptr:=Core_base_adr+4;--adresse du reg status de la première fenêtre + if NextCtx =0 then + NextCtx:=NextCtx+1; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + NextCtx:=NextCtx+1; + end if; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+4,Adrlen)); + If Interf.S.Gpost=0 then + NextCtx:=5; --rien à synchroniser + end if; + elsif (NextCtx>=2) and (NextCtx <=3) then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + NextCtx:=NextCtx+1; + else + NextCtx:=1; + end if; + elsif NextCtx=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + + if SysRam.I.Data_out(3)='1' and SysRam.I.Data_out(6)='0' then --si WPost=1 et WBusy=0 + --il faut un DSent=1 pour Put ou un DSending pour Get + if SysRam.I.Data_out(4)='1' or (SysRam.I.Data_out(5)='1' and SysRam.I.Data_out(2)='1') then + NextCtx:=NextCtx+1; + Interf.S.GPost<=(others=>'0'); + end if; + elsif SysRam.I.Data_out(3)='0' then + NextCtx:=NextCtx; --pas d'opérations en attente + else + NextCtx:=NextCtx; --on attend + end if; + else + NextCtx:=2; --retour à l'atente du Bit ! + end if; + + elsif NextCtx=5 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + Interf.O.membusy<='0'; + NextCtx:=0; + end if; + + +end procedure; + + + Procedure pMPI_Finalize(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram) is + begin + + end procedure; + + procedure pMPI_Comm_Spawn(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; +command : natural; argv :natural; maxprocs : natural; info : natural; root : natural; comm : natural; +signal intercomm :out natural; signal array_of_errcodes : out natural) is + +variable i,dcount : natural:=0; +variable adresse :natural; +variable spawn_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_spawn_adr,ADRLEN)); +begin + spawn_adr:=Std_logic_vector(to_unsigned(Core_spawn_adr,ADRLEN)); + if NextCtx =0 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + NextCtx:=1; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + NextCtx:=2; + adresse:=core_spawn_adr; + SysRam.O.Data_in<=MPI_SPAWN & x"0" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + Interf.O.Instr_En<='0'; + Interf.S.IntState2<=1; -- préparation de la destination du spawn + end if; + elsif NextCtx=2 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if interf.I.ramsel='0' then + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + adresse:=core_spawn_adr; + if interf.I.ismain='1' then ---déclanche l'éxécution de la commande + SysRam.O.Data_in<=MPI_spawn & x"0";--Std_logic_vector(to_unsigned(Interf.S.IntState2+2,4)) ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + else -- envoie d'une commande spawn à la main lib + SysRam.O.Data_in<=MPI_spawn & x"0" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + + end if; + end if; + + elsif NextCtx=3 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + adresse:=core_spawn_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + elsif NextCtx=4 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+1; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(4,8)) ;--la longueur + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instruction<=x"04"; + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=5 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+2; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(maxprocs,8)) ;--le nombre de processus + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=6 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+3; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Data_in<=SPAWN_LOAD & std_logic_vector(to_unsigned(maxprocs,4)) ;--l'instruction + NextCtx:=NextCtx+1; + + end if; + elsif NextCtx=7 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+3; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Data_in<=SPAWN_LOAD & std_logic_vector(to_unsigned(maxprocs,4)) ;--l'instruction + NextCtx:=NextCtx+1; + report "MPV SPAWN activé " & integer'image(interf.I.Rank); + end if; + elsif NextCtx=8 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + dcount:=Interf.S.IntState1; + if interf.I.ramsel='0' then + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,ADRLEN)); + WritePtr (spawn_adr,dcount,SysRam); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + Interf.S.IntState1<=dcount; + if dcount =0 then + NextCtx:=NextCtx+1; + end if; + end if; + elsif NextCtx=9 then + + --fin de la fonction + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + dcount:=0; + Interf.O.membusy<='0'; + Interf.O.Instr_En<='1'; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen)); + NextCtx:=NextCtx+1; + elsif NextCtx=10 then --acquittement de la copie des données dans le tampon + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=NextCtx+1; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + elsif NextCtx=11 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+7; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + if interf.I.ramsel='0' then + NextCtx:=NextCtx+1; + end if; + + elsif NextCtx=12 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+7; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + if SysRam.I.Data_out(5)='1' then --spawned + NextCtx:=NextCtx+1; + intercomm<=1; + end if; + Interf.O.membusy<='0'; + else + NextCtx:=11; + end if; + elsif NextCtx=13 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+8; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils + NextCtx:=NextCtx+1; + + end if; + Interf.O.membusy<='0'; + + elsif NextCtx=14 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+8; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils + NextCtx:=NextCtx+1; + + end if; + Interf.O.membusy<='0'; + + elsif NextCtx =15 then + Interf.O.Instr_En<='0'; + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + NextCtx:=0; + --array_of_errcodes<=0; + end if; + array_of_errcodes<=NextCtx; + end procedure; + +procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram) is +variable i,dcount,wcount : natural range 0 to 255:=0; +variable adresse :natural; +variable LRam : typ_dpRam; +variable W0 :std_logic_vector(Word-1 downto 0); +variable init_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN)); +begin + init_adr:=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN)); + LRam:=SysRam; -- nécessaire pour le débogage + if NextCtx =0 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.S.IntState1<=0; + NextCtx:=1; + adresse:=core_init_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + + elsif NextCtx=1 then --écriture du ptr d'intruction + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if interf.I.ramsel='0' then + + adresse:=core_init_adr; + + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + + wcount:=Interf.S.IntState1; + WritePtr (Init_adr,wcount,SysRam); + Interf.S.IntState1<=wcount; + + if wcount =0 then + NextCtx:=2; + Interf.S.IntState1<=0; + adresse:=core_init_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + end if; + end if; + elsif NextCtx=2 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + adresse:=core_init_adr; + SysRam.O.Data_in<=MPI_INIT & x"0" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=3; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=3 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_init_adr+1; + SysRam.O.Data_in<= x"04" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=4 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + Interf.O.membusy<='1'; + SysRam.O.enb<='0'; + adresse:=core_init_adr+1; + Interf.O.Instruction<=x"04"; + SysRam.O.Data_in<=x"04" ;--longueur de l'instruction + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=5; + end if; + elsif NextCtx=5 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + Interf.O.membusy<='1'; + SysRam.O.enb<='0'; + adresse:=core_init_adr+2; + SysRam.O.Data_in<= x"00" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=6; + end if; + elsif NextCtx=6 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_init_adr+3; + SysRam.O.Data_in<=x"00" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=7; + end if; + elsif NextCtx=7 then --fin de la fonction + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + dcount:=0; + Interf.O.membusy<='0'; + Interf.O.Instruction(6)<=Interf.I.Spawned; --- préciser que la HT est dynamique + Interf.O.Instr_En<='1'; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen)); + NextCtx:=8; + elsif NextCtx=8 then --acquittement de la copie des données dans le tampon + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=9; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + + elsif NextCtx=9 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,Adrlen)); + if SysRam.I.Data_out(4)='1' then + NextCtx:=10; + Interf.S.IntState1<=0; -- initialisation du compteur d'état + end if; + Interf.O.membusy<='0'; + end if; + elsif NextCtx =10 then + dcount:=Interf.S.IntState1; --permet de sauvegarder l'état interne du compteur + readmem(dcount,interf,sysRam,init_Adr,w0); + Interf.S.IntState1<=dcount; + w0:=SysRam.I.Data_out; + if dcount=0 then + Interf.I.ismain<=all_zeros(SysRam.I.Data_out(3 downto 0));--Rank=0 -> MainLib + NextCtx:=NextCtx+1; + end if; + elsif NextCtx =11 then + Interf.O.Instr_En<='0'; + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + NextCtx:=0; + end if; + + +end procedure; + + +procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; Data:in std_logic_vector) is +--cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + + if dcount=0 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + Interf.O.membusy<='1'; + end if; + SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); + SysRam.O.Addr_wr<=adrToSet; + elsif dcount=1 then + if interf.I.ramsel='0' then + Interf.O.membusy<='1'; + dcount :=dcount+1; + end if; + SysRam.O.Data_in<=data; + SysRam.O.Addr_wr<=adrToSet; + elsif dcount=2 then + SysRam.O.Data_in<=data; + dcount :=dcount+1; + SysRam.O.Addr_wr<=AdrToSet; + elsif dcount=3 then + Interf.O.membusy<='1'; + dcount :=dcount+1; + SysRam.O.Addr_wr<=adrToSet; + SysRam.O.Data_in<=data; + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + Interf.O.membusy<='0'; + SysRam.O.Addr_wr<=AdrToSet; + end if; + + NextCtx:=dcount; +end procedure; + +-- écriture dans la mémoire +procedure ReadMem( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; data: out std_logic_vector) is +--cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + if dcount=0 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + Interf.O.membusy<='1'; + end if; + + SysRam.O.Addr_rd<=adrToSet; + elsif dcount=1 then + data:=SysRam.I.Data_out; + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrToSet; + elsif dcount=2 then + data:=SysRam.I.Data_out; + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrToSet; + elsif dcount=3 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrToSet; + data:=SysRam.I.Data_out; + Interf.O.membusy<='0'; + end if; + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + Interf.O.membusy<='0'; + data:=SysRam.I.Data_out; + end if; + data:=SysRam.I.Data_out; + NextCtx:=dcount; +end procedure; + +procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + variable AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic) is +--cette procédure permet de mettre à jour un Bit un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable tempdata:std_logic_vector(Word-1 downto 0); + + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + if dcount=0 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + Interf.O.membusy<='1'; + end if; + + SysRam.O.Addr_rd<=adrVect; + SysRam.O.Addr_Wr<=adrVect; + elsif dcount=1 then + if interf.I.ramsel='0' then + tempdata:=SysRam.I.Data_out; + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + end if; + SysRam.O.enb<='1'; + SySRam.O.ena<='0'; + SysRam.O.we<='0'; + elsif dcount=2 then + tempdata:=SysRam.I.Data_out; + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + SysRam.O.enb<='1'; + SySRam.O.ena<='0'; + SysRam.O.we<='0'; + elsif dcount=3 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_Wr<=adrVect; + SysRam.O.We<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + tempdata:=SysRam.I.Data_out; + Interf.O.membusy<='1'; + end if; + elsif dcount=4 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_Wr<=adrVect; + SysRam.O.We<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + tempdata:=SysRam.I.Data_out; + if BitVal='1' then + TempData:=Tempdata or BitMask; + else + TempData:=TempData and not (BitMAsk); + end if; + SysRam.O.Data_in<=TempData; + Interf.O.membusy<='1'; + end if; + elsif dcount=5 then --attente d'écriture + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + SysRam.O.We<='1'; + SysRam.O.ena<='1'; + --SysRam.O.Data_in<=TempData; + Interf.O.membusy<='1'; + end if; + elsif dcount=6 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + Interf.O.membusy<='0'; + SysRam.O.We<='0'; + SysRam.O.ena<='0'; + + end if; + + NextCtx:=dcount; +end procedure; + + + + + + + + + + + + + + + + +procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural;signal SysRam :out typ_dpram) is +--cette procédure permet d'écrire dans la mémoire du PE(tâche matérielle) +--les données de l'appel de la procédure +variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; +begin + if count /=0 then --préserver la valeur de count entre les appels + dcount:=count; + else + + + end if; + adresse:=Core_base_adr+2; + AdrToSet:=AdrVect; + if dcount=0 then + SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); + dcount :=dcount+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=1 then + + SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); + SysRam.O.We<='1';SysRam.O.Ena<='1'; + dcount :=dcount+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + elsif dcount=2 then + SysRam.O.We<='1';SysRam.O.Ena<='1'; + SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); + dcount :=dcount+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); + elsif dcount=3 then + dcount :=dcount+1; + SysRam.O.We<='1';SysRam.O.Ena<='1'; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + SysRam.O.We<='0';SysRam.O.Ena<='0'; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + end if; + + count:=dcount; +end procedure; +end MPI_Rma; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_RMA.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_RMA.vhd.bak (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MPI_RMA.vhd.bak (revision 138) @@ -0,0 +1,1774 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +use work.PACKET_TYPE.all; + +package Mpi_Rma is +procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural;signal SysRam :out typ_dpram); +procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram); +procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural); + +procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural); +procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector ); + +procedure pMPI_Win_create(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; + info:natural; comm:Mpi_Comm; Win: inout MPI_Win ); +procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win); +procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win); +procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win); +procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win); +procedure pMPI_Comm_Spawn(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; +command : natural; argv :natural; maxprocs : natural; info : natural; root : natural; comm : natural; +signal intercomm :out natural; signal array_of_errcodes : out natural); +-- declare functions and procedure + procedure ReadMem( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; data: out std_logic_vector); +procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; Data:in std_logic_vector); + +procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + variable AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic); + +end MPI_Rma; + + +package body MPI_Rma is +----int MPI_Put( +-- void *origin_addr, +-- int origin_count, +-- MPI_Datatype origin_datatype, +-- int target_rank, +-- MPI_Aint target_disp, +-- int target_count, +-- MPI_Datatype target_datatype, +-- MPI_Win win +--); +-- Example 1 +procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural) is +variable i,dcount,wr_state : natural:=0; +variable adresse :natural; +variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr; +variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp; +variable put_adr : std_logic_vector (ADRLEN-1 downto 0); +variable config_reg: std_logic_vector (Word-1 downto 0); +constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0'); + begin + put_adr:=conv_Std_logic_vector(Core_put_adr,ADRLEN); + + addr1:=Orig_Addr; + addr2:=Target_Disp; + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + end if; +-- + + if rising_edge(clkin) then + if dcount= 0 then + dcount:=dcount+1; + Interf.S.Intstate1<=0; + elsif dcount>=1 and dcount <=3 then + if interf.I.ramsel='0' then + Interf.O.membusy<='0'; + --SysRam.O.we<='1'; + --SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + wr_state:=interf.S.Intstate1; + WritePtr (put_adr,wr_state,SysRam); + interf.S.Intstate1<=wr_state; + if wr_state =0 then + -- fin de l'écriture du pointeur en mémoire + dcount:=4; + end if; + end if; + + elsif dcount=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + if target_rank <=15 then --limitation de cete version à 16 rang + Interf.S.Gstart(Target_rank)<='1'; + end if; + adresse:=core_put_adr; + SysRam.O.Data_in<=MPI_PUT & conv_std_logic_vector(Target_Rank,4); --code fonction + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=5 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+1; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + Interf.O.Instruction<=x"06"; -- nombre de mots de l'instruction + end if; + elsif dcount=6 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+2; + SysRam.O.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=7 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+3; + SysRam.O.Data_in<=Addr1(Word-1 downto 0); --source Bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=8 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+4; + SysRam.O.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=9 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+5; + SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=10 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + if interf.I.ramsel='0' then + adresse:=core_base_adr+1; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire; + Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction + Interf.O.membusy<='0'; + dcount:=dcount+1; + end if; + elsif dcount=11 then + if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ? + Interf.O.Instr_En<='0'; --désactiver la prise en compte de l'instruction + dcount:=dcount+1; + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + else + Interf.O.Instr_En<='1'; + end if; + adresse:=core_base_adr+1; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + --SysRam.O.Ram_busy<='0'; --?? + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer la lecture du résultat du Put + SysRam.O.enb<='1'; + elsif dcount=12 then + adresse:=core_base_adr+1; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du Put + SysRam.O.enb<='1'; + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=13 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du Put + SysRam.O.enb<='0'; + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + adresse:=core_base_adr+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=14 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_put_adr+6,Adrlen)); + if SysRam.I.Data_out(0)='1' then --fin du MPI PUT ici pour l'envoie ! + dcount:=dcount+1; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + Interf.S.Intstate2<=255; --timer pour la réception + interf.s.tmem(0)<=x"02"; + end if; + end if; + elsif dcount=15 or dcount=16 or dcount=17 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + -- ce cycle permet d'attendre la donnée en sortie après le changement d'adresse + + if interf.I.ramsel='0' then + dcount:=dcount+1; -- ce cycle permet d'attendre la donnée en sortie après le changement d'adresse + + elsif Interf.S.Intstate2>0 then + dcount:=15; + Interf.S.Intstate2<=Interf.S.Intstate2-1; + elsif interf.s.tmem(0)>0 then + interf.s.tmem(0)<=interf.s.tmem(0)-1; + Interf.S.Intstate2<=255; + dcount:=15; + else + dcount:=1;--recommencer l'envoi + end if; + elsif dcount=18 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + if SysRam.I.Data_out(5)='1' then --Message du MPI PUT bien reçu ! + dcount:=dcount+1; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + elsif Interf.S.Intstate2>0 then + Interf.S.Intstate2<=Interf.S.Intstate2-1; + elsif interf.s.tmem(0)>0 then + interf.s.tmem(0)<=interf.s.tmem(0)-1; + Interf.S.Intstate2<=255; + else + dcount:=1;--recommencer l'envoi + end if; + else + dcount:=15; + end if; + elsif dcount=19 then + dcount:=0; --fin normale de la fonction + Interf.O.membusy<='0'; + end if; + + + NExtCtx:=dcount; + end if; + end procedure; + +procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural) is +variable i,wcount,dcount : natural range 0 to 255:=0; +variable adresse :natural; +variable wdata: std_logic_vector(Word-1 downto 0):=(others=>'0'); +variable bitval : std_logic:='0'; +variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr; +variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp; +variable get_adr : std_logic_vector (ADRLEN-1 downto 0); +variable config_reg,win_reg: std_logic_vector (Word-1 downto 0); +constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0'); + begin + get_adr:=Std_logic_vector(to_unsigned(Core_get_adr,ADRLEN)); + + addr1:=Orig_Addr; + addr2:=Target_Disp; + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + end if; +-- + + if rising_edge(clkin) then + + if dcount =0 then + dcount:=dcount+1; + Interf.S.IntState1<=0; + elsif dcount>=1 and dcount <=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + wcount:=Interf.S.IntState1; + WritePtr (get_adr,wcount,SysRam); + Interf.S.IntState1<=wcount; + Interf.O.membusy<='1'; + if wcount =0 then + dcount:=4; + Interf.S.Intstate1<=1; + end if; + else + Interf.S.IntState1<=0; + + end if; + + elsif dcount=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if target_rank <=15 then --limitation de cete version à 16 rang + Interf.S.Gstart(Target_rank)<='1'; + end if; + adresse:=core_get_adr; + SysRam.O.Data_in<=MPI_GET & conv_Std_logic_vector(Target_Rank,4); --code fonction + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + dcount:=dcount+1; + end if; + elsif dcount=5 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+1; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + interf.O.Instruction<=x"06"; --le nbre de mots de l'intstruction + dcount:=dcount+1; + end if; + elsif dcount=6 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+2; + SysRam.O.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + dcount:=dcount+1; + + end if; + elsif dcount=7 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+3; + SysRam.O.Data_in<=Addr1(Word-1 downto 0); --source Bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + dcount:=dcount+1; + end if; + elsif dcount=8 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+4; + SysRam.O.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + dcount:=dcount+1; + end if; + elsif dcount=9 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+5; + SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + dcount:=dcount+1; + end if; + elsif dcount=10 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+7; + SysRam.O.Data_in<=x"00"; -- résultat du GET + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + Interf.S.IntState2<=0; + dcount:=dcount+1; + end if; + elsif dcount=11 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + addr1:=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + wcount:=Interf.S.IntState2; + wdata:=x"01";bitval:='1'; + setBit(wcount,Interf,SysRam,addr1(ADrLen-1 downto 0),wdata,bitval); + Interf.S.IntState2<=wcount; + if wcount=0 then + dcount:=dcount+1; + Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction + end if; + + elsif dcount=12 then + if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ? + Interf.O.Instr_En<='0'; --désactiver la prise en compte de l'instruction + dcount:=dcount+1; + config_reg:=SysRam.I.Data_out and x"f6"; + --SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + end if; + adresse:=core_base_adr+1; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + --SysRam.O.Ram_busy<='0'; --?? + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer la lecture du résultat du get + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + elsif dcount=13 then + + adresse:=core_base_adr+1; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du get + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + Interf.s.IntState2<=255; + Interf.s.tmem(0)<=x"08"; --tempo pour l'attente du résultat de Get + elsif dcount=14 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du GET + SysRam.O.enb<='0'; + adresse:=core_base_adr+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=18;--dcount+1; + Interf.O.membusy<='1'; + + end if; + elsif dcount=15 then + + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer l'écriture du WBusy + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy + SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + elsif dcount=16 then + + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer l'écriture du WBusy + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy + SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy + dcount:=dcount+1; + Interf.O.membusy<='1'; + + end if; + elsif dcount=17 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du GET + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; + SysRam.O.Data_in<=config_reg ; --; + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + elsif dcount>=18 and dcount <=21 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_get_adr+6,Adrlen)); + if SysRam.I.Data_out(0)='1' then --fin du MPI get ici pour l'envoie ! + dcount:=dcount+1; + end if; + end if; + elsif dcount>=22 and dcount <=24 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + if SysRam.I.Data_out(5)='1' then --Message du MPI Get bien reçu ! + dcount:=dcount+1; --ce test est fait avant l'arrivée effective des données ce qui pose problème ! + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + elsif Interf.S.Intstate2>0 then + Interf.S.Intstate2<=Interf.S.Intstate2-1; + elsif interf.s.tmem(0)>0 then + interf.s.tmem(0)<=interf.s.tmem(0)-1; + Interf.S.Intstate2<=255; + else + dcount:=1;--recommencer l'envoi + end if; + end if; + + elsif dcount=25 then + dcount:=0; --fin normale de la fonction + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + end if; + + NExtCtx:=dcount; + end if; + end procedure; +Procedure pMPI_Comm_group(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; COMM :in MPI_Comm; signal grp : out Mpi_group ) is +Begin +--cette procédure permet de récupérer le groupe qui est associé à un communicateur +--dans notre cas c'est la récupération du groupe associé à COMM_WORLD +end procedure; +--int MPI_Group_incl(MPI_Group group, int n, int *ranks, +-- MPI_Group *newgroup) +Procedure pMPI_group_incl(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; + GRP: Mpi_group; n:natural;ranks :natural; newgroup: out Mpi_group) is +Begin +-- cette procedure a pour algo de parcourir les rangs qui sont dans la mémoire pointée par ranks +-- et d'activer l'un des bits de position de newgroup. +-- +-- +end procedure; + +procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector ) is +variable adresse_rd : natural range 0 to 2**ADRLEN-1; + +begin + + if NextCtx =0 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + + NextCtx:=1; + + elsif NextCtx=1 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + NextCtx:=2; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=2 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); + NextCtx:=3; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=3 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); + NextCtx:=4; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=4 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); + NextCtx:=0; + Interf.O.membusy<='0'; + end if; + end if; +end procedure; + +--int MPI_Win_create( +-- void *base, +-- MPI_Aint size, +-- int disp_unit, +-- MPI_Info info, +-- MPI_Comm comm, +-- MPI_Win *win +--); +procedure pMPI_Win_create(NextCtx : inout natural ;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; + info:natural; comm:Mpi_Comm; Win: inout MPI_Win ) is + -- parcours de la liste des fenêtres existantes à la recherche d'un emplacement libre + -- si fenêtre libre trouvée, et + -- mise à 1 du Bit WCreate du registre status + type wtype is array (1 to 4 ) of natural range 0 to 255; + variable AdrWin: std_logic_vector(ADRLEN-1 downto 0); + variable adresse : std_logic_vector(ADRLEN-1 downto 0); + variable clkin : std_logic:='1'; + variable wcreate_adr : std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_wcreate_adr,ADRLEN)); + variable w0 : std_logic_vector(Word-1 downto 0); + variable adrnat : natural; + variable sizewin : std_logic_vector(Word-1 downto 0); + variable count : natural range 0 to 255; + variable wdisp :wtype:=(4,14,24,34); --stocke l'adresse de la prochaine Win libre +begin +-- création d'une fenêtre il s'agit d'affecter l'objet Win et de retourner +-- le pointeur qui permet de le décrire + + +If NextCtx=0 then + NExtCtx:=NextCtx+1; + count:=0; + Interf.O.membusy<='0'; + Interf.S.IntState1<=count; +elsif NextCtx>=1 and NextCtx <= 4 then + count:=Interf.S.IntState1; + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(NextCtx),16)); + readmem(count,interf,sysRam,AdrWin,w0); + if count=0 then + if w0(0)/='1' then -- cette fenêtre est libre + NextCtx:=6; --étape de la création de la fenêtre + Win.addr:=base; --l'adresse de la fenêtre + Win.id:=NextCtx; -- la référence provisoire de la fenêtre + Win.size:=Size; -- la taille de la fenêtre + + else + NextCtx:=NextCtx+1; + end if; + end if; + Interf.S.IntState1<=count;--sauvegarde du statut de la sous-procédure + +elsif NextCtx=5 then + -- Plus de fenêtre disponible erreur + NextCtx:=1; -- boucle sans fin :) + Win.id:=0; + Win.addr:=x"0000"; +elsif NextCtx=6 then + --Affectation de l'objet Windows car une place est disponible + count:=Interf.S.IntState1; + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + Writemem(count,interf,SysRam,AdrWin,x"01"); --signal status pour created + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + +elsif NextCtx=8 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + interf.S.winid<=interf.S.winid+1; + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,AdrWin+1,stdlv(interf.S.winid,8)); --win id de la fenêtre + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=9 then + + adrnat:=Core_base_adr+Wdisp(Win.id); + + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + count:=Interf.S.IntState1; + + + Writemem(count,interf,SysRam,AdrWin+2,base(7 downto 0)); --adresse basse + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=10 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,AdrWin+3,base(15 downto 8)); --adresse haute + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=11 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + sizewin:=std_logic_vector(to_unsigned(size,8)); + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,AdrWin+4,sizewin); -- taille de la fenêtre + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=12 then + --cette étape consiste à envoyer le message WINCREATE Sur le réseau et à récupérer + -- les informations donnant le numéro de la fenêtre + W0:=MPI_WIN_CREATE & std_logic_vector(to_unsigned(0,4)); --code fonction + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,wcreate_adr,w0); + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + + elsif NextCtx=13 then + w0:=std_logic_vector(to_unsigned(Win.Id,8)); -- id proposé pour la fenêtre en création + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,wcreate_adr+1,w0); + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=14 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + count:=Interf.S.IntState1; + if interf.I.ramsel='0' then + WritePtr (wcreate_adr,count,SysRam); --écriture du pointeur d'instruction + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + end if; + elsif NextCtx=15 then + -- il faut mettre instruction_en à 1 + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + adresse:=stdlv(core_base_adr+1); + SysRam.O.addr_rd<=adresse; + SysRam.O.Addr_wr<=adresse; + SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire; + Writemem(count,interf,SysRam,adresse,x"01"); + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + Interf.O.Instr_En<='1'; + adresse:=stdlv(core_base_adr); + SysRam.O.Addr_rd<=adresse; + NextCtx:=NextCtx+1; + elsif NextCtx=16 then --acquittement de la copie des données dans le tampon de la lib + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=NextCtx+1; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + elsif NextCtx=17 then + -- lecture du résultat de l'instruction + + +else + +end if; +end procedure; +--int MPI_Win_start( +-- MPI_Group group, +-- int assert, +-- MPI_Win win +--); +procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is +--cette fonction active les bits WStart pour chaque processus avec lequel +-- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à +--chacune de ces cibles + variable dcount : natural range 0 to 255:=0; + variable cstatus : std_logic_vector(Word-1 downto 0); + begin + + -- retour de l'adresse de de la fenêtre dans la structure Win + -- initialisation des bits concernant + + if NextCtx =0 then + NextCtx:=NextCtx+1; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + SysRam.O.Data_in<=x"01"; --mise à 1 du bit WSTART et remise à zero de tous les autres Bits + + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + Interf.S.GStart<=(others=>'0'); + end if; + elsif NextCtx=2 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + SysRam.O.Data_in<=x"01"; + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + SysRam.O.Data_in<=x"01"; + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=4 then + NextCtx:=0; + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + end if; + + + end procedure; +procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is +variable adresse :natural; +variable wcount: natural range 0 to 255:=0; +variable LRam : typ_dpRam; +variable SyncDest,i : natural range 0 to 15; --destination du message de synchronisation +variable W0 :std_logic_vector(Word-1 downto 0); +variable wcompl_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN)); + +begin + -- + wcompl_adr:=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN)); + LRam:=SysRam; -- nécessaire pour le débogage + if NextCtx =0 then + + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + Interf.O.MemBusy<='1'; --occuper la mémoire + Interf.S.IntState1<=0; + NextCtx:=1; + adresse:=core_wcompl_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + + elsif NextCtx=1 then --écriture du ptr d'intruction + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if interf.I.ramsel='0' then + + adresse:=core_wcompl_adr; + + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + wcount:=Interf.S.IntState1; + WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir + Interf.S.IntState1<=wcount; + + if wcount =0 then + NextCtx:=2; + Interf.S.IntState1<=0; + Interf.S.IntState2<=0; + Interf.S.tmem(0)<=Interf.S.GStart(7 downto 0); --cibles impactées + Interf.S.tmem(1)<=Interf.S.GStart(15 downto 8); --cibles impactées + adresse:=core_wcompl_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + end if; + else + Interf.S.IntState1<=0; --recommencer l'écriture du pointeur + end if; + elsif NextCtx=2 then + if Interf.I.Ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr; + NextCtx:=10; --aller à la fin de la fonction + i:=0; + l1:for i in 0 to 7 loop + -- i:=i+1; + if i>=interf.s.intState2 then + if interf.s.gstart(i)='1' then + SysRam.O.Data_in<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4)); + Interf.S.tmem(2)<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4)); + + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.S.tmem(0)(i)<='0'; --ce dest a été traité ! + NextCtx:=4; + Interf.S.IntState2<=i+1; + exit l1; + end if; + end if; + exit l1 when i=7; + end loop l1; + end if; + elsif NextCtx=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr; + wcount:=Interf.S.IntState1; + WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir + Interf.S.IntState1<=wcount; + SysRam.O.Data_in<= Interf.S.tmem(2); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if wcount=0 then + NextCtx:=NextCtx+1; + end if; + end if; + elsif NextCtx=4 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr+1; + SysRam.O.Data_in<= x"04" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + elsif NextCtx=5 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr+2; + Interf.O.Instruction<=x"04";--longueur de l'instruction + SysRam.O.Data_in<=x"00" ;-- + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=6; + elsif NextCtx=6 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr+3; + SysRam.O.Data_in<= SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=7; + elsif NextCtx=7 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + adresse:=core_wcompl_adr+3; + SysRam.O.Data_in<=SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + + elsif NextCtx=8 then --fin de la fonction + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + --dcount:=0; + Interf.O.membusy<='0'; + Interf.O.Instr_En<='1'; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr+5,AdrLen)); + NextCtx:=NextCtx+1; + elsif NextCtx=9 then --acquittement de la copie des données dans le tampon + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=10; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + + elsif NextCtx=10 then --lecture de la fin de WComplete + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.S.IntState2=0 then --aucune instruction MPI exécutée ? + NextCtx:=12; + elsif Interf.S.tmem(0)/=0 then --plus de message compl à envoyer + NextCtx:=2; + elsif Interf.S.tmem(0)=0 then + if interf.I.ramsel='0' then + NextCtx:=NextCtx+1; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + end if; + end if; + elsif NextCtx=11 then --test de la fin des transferts + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + if SysRam.I.Data_out(0)='1' and SysRam.I.Data_out(6)='0' then --si WStart=1 et Wbusy=0 + --il faut un DSent=1 pour Put ou un DSending pour Get + if SysRam.I.Data_out(5)='1' or (SysRam.I.Data_out(4)='1' and SysRam.I.Data_out(1)='1') then + NextCtx:=NextCtx+1; + end if; + end if; + + end if; + elsif NextCtx=12 then + Interf.S.IntState1<=0; -- initialisation du compteur d'état + Interf.S.IntState2<=0; + SysRam.O.enb<='0'; + NextCtx:=0; --fin de la fonction + end if; + +end procedure; +procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is +--cette fonction active les bits WStart pour chaque processus avec lequel +-- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à +--chacune de ces cibles + variable W_Ptr : natural range 0 to 65535:=0;--adresse de la fenêtre en mémoire + variable dcount : natural range 0 to 255:=0; + variable cstatus : std_logic_vector(Word-1 downto 0); + begin + + -- retour de l'adresse de de la fenêtre dans la structure Win + -- initialisation des bits concernant + if Win.id =0 then + W_ptr:=Core_Base_Adr+4; + end if; + if NextCtx =0 then + + if pgroup.grp=0 then --rien à faire + nextCtx:=5; + Interf.S.GPost<=(others=>'0'); + else + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + SysRam.O.Data_in<=x"48"; --mise à 1 du bit WPOST et WBusy et remise à zero de tous les autres Bits + + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + + end if; + --limitation de cete version à 16 rang + Interf.S.GPost<=pgroup.grp; + elsif NextCtx=2 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + SysRam.O.Data_in<=x"48"; --mise à 1 du bit WPOST et WBusy et remise à zero de tous les autres Bits + + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + + end if; + elsif NextCtx=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_Ptr+W_Gpost,Adrlen)); + SysRam.O.Data_in<=pgroup.grp(7 downto 0); + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; +elsif NextCtx=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_Gpost+1,Adrlen)); + SysRam.O.Data_in<=pgroup.grp(15 downto 8); + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; +elsif NextCtx=6 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_Gpost+1,Adrlen)); + SysRam.O.Data_in<=pgroup.grp(15 downto 8); + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=5 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + NextCtx:=0; + Interf.O.membusy<='0'; + end if; + + + end procedure; + + procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is +--permet de synchroniser la fin des opérations sur une fenêtre +variable dcount : natural range 0 to 255:=0; +variable cstatus : std_logic_vector(Word-1 downto 0); +variable W_Ptr : natural range 0 to 65535:=0;--adresse de la fenêtre en mémoire +begin + W_Ptr:=Core_base_adr+4;--adresse du reg status de la première fenêtre + if NextCtx =0 then + NextCtx:=NextCtx+1; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + NextCtx:=NextCtx+1; + end if; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+4,Adrlen)); + If Interf.S.Gpost=0 then + NextCtx:=5; --rien à synchroniser + end if; + elsif (NextCtx>=2) and (NextCtx <=3) then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + NextCtx:=NextCtx+1; + else + NextCtx:=1; + end if; + elsif NextCtx=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + + if SysRam.I.Data_out(3)='1' and SysRam.I.Data_out(6)='0' then --si WPost=1 et WBusy=0 + --il faut un DSent=1 pour Put ou un DSending pour Get + if SysRam.I.Data_out(4)='1' or (SysRam.I.Data_out(5)='1' and SysRam.I.Data_out(2)='1') then + NextCtx:=NextCtx+1; + Interf.S.GPost<=(others=>'0'); + end if; + elsif SysRam.I.Data_out(3)='0' then + NextCtx:=NextCtx; --pas d'opérations en attente + else + NextCtx:=NextCtx; --on attend + end if; + else + NextCtx:=2; --retour à l'atente du Bit ! + end if; + + elsif NextCtx=5 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + Interf.O.membusy<='0'; + NextCtx:=0; + end if; + + +end procedure; + + + Procedure pMPI_Finalize(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram) is + begin + + end procedure; + + procedure pMPI_Comm_Spawn(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; +command : natural; argv :natural; maxprocs : natural; info : natural; root : natural; comm : natural; +signal intercomm :out natural; signal array_of_errcodes : out natural) is + +variable i,dcount : natural:=0; +variable adresse :natural; +variable spawn_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_spawn_adr,ADRLEN)); +begin + spawn_adr:=Std_logic_vector(to_unsigned(Core_spawn_adr,ADRLEN)); + if NextCtx =0 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + NextCtx:=1; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + NextCtx:=2; + adresse:=core_spawn_adr; + SysRam.O.Data_in<=MPI_SPAWN & x"0" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + Interf.O.Instr_En<='0'; + Interf.S.IntState2<=1; -- préparation de la destination du spawn + end if; + elsif NextCtx=2 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if interf.I.ramsel='0' then + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + adresse:=core_spawn_adr; + if interf.I.ismain='1' then ---déclanche l'éxécution de la commande + SysRam.O.Data_in<=MPI_spawn & x"0";--Std_logic_vector(to_unsigned(Interf.S.IntState2+2,4)) ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + else -- envoie d'une commande spawn à la main lib + SysRam.O.Data_in<=MPI_spawn & x"0" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + + end if; + end if; + + elsif NextCtx=3 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + adresse:=core_spawn_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + elsif NextCtx=4 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+1; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(4,8)) ;--la longueur + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instruction<=x"04"; + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=5 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+2; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(maxprocs,8)) ;--le nombre de processus + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=6 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+3; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Data_in<=SPAWN_LOAD & std_logic_vector(to_unsigned(maxprocs,4)) ;--l'instruction + NextCtx:=NextCtx+1; + + end if; + elsif NextCtx=7 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+3; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Data_in<=SPAWN_LOAD & std_logic_vector(to_unsigned(maxprocs,4)) ;--l'instruction + NextCtx:=NextCtx+1; + report "MPV SPAWN activé " & integer'image(interf.I.Rank); + end if; + elsif NextCtx=8 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + dcount:=Interf.S.IntState1; + if interf.I.ramsel='0' then + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,ADRLEN)); + WritePtr (spawn_adr,dcount,SysRam); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + Interf.S.IntState1<=dcount; + if dcount =0 then + NextCtx:=NextCtx+1; + end if; + end if; + elsif NextCtx=9 then + + --fin de la fonction + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + dcount:=0; + Interf.O.membusy<='0'; + Interf.O.Instr_En<='1'; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen)); + NextCtx:=NextCtx+1; + elsif NextCtx=10 then --acquittement de la copie des données dans le tampon + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=NextCtx+1; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + elsif NextCtx=11 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+7; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + if interf.I.ramsel='0' then + NextCtx:=NextCtx+1; + end if; + + elsif NextCtx=12 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+7; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + if SysRam.I.Data_out(5)='1' then --spawned + NextCtx:=NextCtx+1; + intercomm<=1; + end if; + Interf.O.membusy<='0'; + else + NextCtx:=11; + end if; + elsif NextCtx=13 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+8; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils + NextCtx:=NextCtx+1; + + end if; + Interf.O.membusy<='0'; + + elsif NextCtx=14 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+8; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils + NextCtx:=NextCtx+1; + + end if; + Interf.O.membusy<='0'; + + elsif NextCtx =15 then + Interf.O.Instr_En<='0'; + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + NextCtx:=0; + --array_of_errcodes<=0; + end if; + array_of_errcodes<=NextCtx; + end procedure; + +procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram) is +variable i,dcount,wcount : natural range 0 to 255:=0; +variable adresse :natural; +variable LRam : typ_dpRam; +variable W0 :std_logic_vector(Word-1 downto 0); +variable init_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN)); +begin + init_adr:=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN)); + LRam:=SysRam; -- nécessaire pour le débogage + if NextCtx =0 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.S.IntState1<=0; + NextCtx:=1; + adresse:=core_init_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + + elsif NextCtx=1 then --écriture du ptr d'intruction + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if interf.I.ramsel='0' then + + adresse:=core_init_adr; + + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + + wcount:=Interf.S.IntState1; + WritePtr (Init_adr,wcount,SysRam); + Interf.S.IntState1<=wcount; + + if wcount =0 then + NextCtx:=2; + Interf.S.IntState1<=0; + adresse:=core_init_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + end if; + end if; + elsif NextCtx=2 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + adresse:=core_init_adr; + SysRam.O.Data_in<=MPI_INIT & x"0" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=3; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=3 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_init_adr+1; + SysRam.O.Data_in<= x"04" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=4 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + Interf.O.membusy<='1'; + SysRam.O.enb<='0'; + adresse:=core_init_adr+1; + Interf.O.Instruction<=x"04"; + SysRam.O.Data_in<=x"04" ;--longueur de l'instruction + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=5; + end if; + elsif NextCtx=5 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + Interf.O.membusy<='1'; + SysRam.O.enb<='0'; + adresse:=core_init_adr+2; + SysRam.O.Data_in<= x"00" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=6; + end if; + elsif NextCtx=6 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_init_adr+3; + SysRam.O.Data_in<=x"00" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=7; + end if; + elsif NextCtx=7 then --fin de la fonction + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + dcount:=0; + Interf.O.membusy<='0'; + Interf.O.Instruction(6)<=Interf.I.Spawned; --- préciser que la HT est dynamique + Interf.O.Instr_En<='1'; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen)); + NextCtx:=8; + elsif NextCtx=8 then --acquittement de la copie des données dans le tampon + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=9; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + + elsif NextCtx=9 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,Adrlen)); + if SysRam.I.Data_out(4)='1' then + NextCtx:=10; + Interf.S.IntState1<=0; -- initialisation du compteur d'état + end if; + Interf.O.membusy<='0'; + end if; + elsif NextCtx =10 then + dcount:=Interf.S.IntState1; --permet de sauvegarder l'état interne du compteur + readmem(dcount,interf,sysRam,init_Adr,w0); + Interf.S.IntState1<=dcount; + w0:=SysRam.I.Data_out; + if dcount=0 then + Interf.I.ismain<=all_zeros(SysRam.I.Data_out(3 downto 0));--Rank=0 -> MainLib + NextCtx:=NextCtx+1; + end if; + elsif NextCtx =11 then + Interf.O.Instr_En<='0'; + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + NextCtx:=0; + end if; + + +end procedure; + + +procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; Data:in std_logic_vector) is +--cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + + if dcount=0 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + Interf.O.membusy<='1'; + end if; + SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); + SysRam.O.Addr_wr<=adrToSet; + elsif dcount=1 then + if interf.I.ramsel='0' then + Interf.O.membusy<='1'; + dcount :=dcount+1; + end if; + SysRam.O.Data_in<=data; + SysRam.O.Addr_wr<=adrToSet; + elsif dcount=2 then + SysRam.O.Data_in<=data; + dcount :=dcount+1; + SysRam.O.Addr_wr<=AdrToSet; + elsif dcount=3 then + Interf.O.membusy<='1'; + dcount :=dcount+1; + SysRam.O.Addr_wr<=adrToSet; + SysRam.O.Data_in<=data; + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + Interf.O.membusy<='0'; + SysRam.O.Addr_wr<=AdrToSet; + end if; + + NextCtx:=dcount; +end procedure; + +-- écriture dans la mémoire +procedure ReadMem( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; data: out std_logic_vector) is +--cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + if dcount=0 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + Interf.O.membusy<='1'; + end if; + + SysRam.O.Addr_rd<=adrToSet; + elsif dcount=1 then + data:=SysRam.I.Data_out; + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrToSet; + elsif dcount=2 then + data:=SysRam.I.Data_out; + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrToSet; + elsif dcount=3 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrToSet; + data:=SysRam.I.Data_out; + Interf.O.membusy<='0'; + end if; + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + Interf.O.membusy<='0'; + data:=SysRam.I.Data_out; + end if; + data:=SysRam.I.Data_out; + NextCtx:=dcount; +end procedure; + +procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + variable AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic) is +--cette procédure permet de mettre à jour un Bit un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable tempdata:std_logic_vector(Word-1 downto 0); + + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + if dcount=0 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + Interf.O.membusy<='1'; + end if; + + SysRam.O.Addr_rd<=adrVect; + SysRam.O.Addr_Wr<=adrVect; + elsif dcount=1 then + if interf.I.ramsel='0' then + tempdata:=SysRam.I.Data_out; + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + end if; + SysRam.O.enb<='1'; + SySRam.O.ena<='0'; + SysRam.O.we<='0'; + elsif dcount=2 then + tempdata:=SysRam.I.Data_out; + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + SysRam.O.enb<='1'; + SySRam.O.ena<='0'; + SysRam.O.we<='0'; + elsif dcount=3 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_Wr<=adrVect; + SysRam.O.We<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + tempdata:=SysRam.I.Data_out; + Interf.O.membusy<='1'; + end if; + elsif dcount=4 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_Wr<=adrVect; + SysRam.O.We<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + tempdata:=SysRam.I.Data_out; + if BitVal='1' then + TempData:=Tempdata or BitMask; + else + TempData:=TempData and not (BitMAsk); + end if; + SysRam.O.Data_in<=TempData; + Interf.O.membusy<='1'; + end if; + elsif dcount=5 then --attente d'écriture + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + SysRam.O.We<='1'; + SysRam.O.ena<='1'; + --SysRam.O.Data_in<=TempData; + Interf.O.membusy<='1'; + end if; + elsif dcount=6 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + Interf.O.membusy<='0'; + SysRam.O.We<='0'; + SysRam.O.ena<='0'; + + end if; + + NextCtx:=dcount; +end procedure; + + + + + + + + + + + + + + + + +procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural;signal SysRam :out typ_dpram) is +--cette procédure permet d'écrire dans la mémoire du PE(tâche matérielle) +--les données de l'appel de la procédure +variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; +begin + if count /=0 then --préserver la valeur de count entre les appels + dcount:=count; + else + + + end if; + adresse:=Core_base_adr+2; + AdrToSet:=AdrVect; + if dcount=0 then + SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); + dcount :=dcount+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=1 then + + SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); + SysRam.O.We<='1';SysRam.O.Ena<='1'; + dcount :=dcount+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + elsif dcount=2 then + SysRam.O.We<='1';SysRam.O.Ena<='1'; + SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); + dcount :=dcount+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); + elsif dcount=3 then + dcount :=dcount+1; + SysRam.O.We<='1';SysRam.O.Ena<='1'; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + SysRam.O.We<='0';SysRam.O.Ena<='0'; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + end if; + + count:=dcount; +end procedure; +end MPI_Rma; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MUX1.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MUX1.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MUX1.vhd (revision 138) @@ -0,0 +1,46 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:18:52 06/13/2011 +-- Design Name: +-- Module Name: MUX1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity CMUXP1 is + Port ( di1 : in STD_LOGIC; + di2 : in STD_LOGIC; + do : out STD_LOGIC; + sel : in STD_LOGIC); +end CMUXP1; + +architecture Behavioral of CMUXP1 is + +begin + --modelisation d'un multiplexeur 1 bit + with sel select + do <= di1 when '0', + di2 when '1', + di1 when others; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MUX8.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MUX8.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MUX8.vhd (revision 138) @@ -0,0 +1,45 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:30:26 06/13/2011 +-- Design Name: +-- Module Name: MUX8 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity CMUX8 is + Port ( di1 : in STD_LOGIC_VECTOR (7 downto 0); + di2 : in STD_LOGIC_VECTOR (7 downto 0); + sel : in STD_LOGIC; + do : out STD_LOGIC_VECTOR (7 downto 0)); +end CMUX8; + +architecture Behavioral of CMUX8 is + +begin + with sel select + do <= di1 when '0', + di2 when '1', + di1 when others; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MultiMPITest.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MultiMPITest.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MultiMPITest.vhd (revision 138) @@ -0,0 +1,228 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM Roland Christian +-- +-- Create Date: 16:44:13 08/01/2012 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/MultiMPITest.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: MPI_NOC +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- +-- +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +library NocLib ; + +use NocLib.CoreTypes.all; +LIbrary MPI_HCL; +use MPI_HCL.Packet_type.all; +use work.Hcl_Arch_conf.all; +USE ieee.numeric_std.ALL; + +ENTITY MultiMPITest IS +--simulation translate_off +port (clkm : in std_logic; +reset : in std_logic; +result : out std_logic_vector(Word-1 downto 0)); +--simulation translate_on +END MultiMPITest; + +ARCHITECTURE behavior OF MultiMPITest IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT MPI_NOC + generic (NPROC: natural:=2); + PORT( + MPI_Node_in : IN Ar_MPIPort_in(1 to NPROC); + MPI_Node_Out : OUT Ar_MPIPort_out(1 to NPROC) + ); + END COMPONENT; + Component PE + generic(destid : natural); + Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : out STD_LOGIC; + Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + CE : in STD_LOGIC; + Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_WE : in STD_LOGIC; + Core_RAM_EN : in STD_LOGIC; + --Core_RAM_ENB : in STD_LOGIC; + Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_Hold_req : in STD_LOGIC; + Core_Hold_Ack : out STD_LOGIC); +end Component; + + constant clk_period : time := 15 ns; + constant PROC : positive :=NOC_SIZE; --4 +-- synthesis translate_off +--===================signaux pour l'horloge ============================== +--signal reset,clkm : std_logic := '0'; +--======================================================================== +-- synthesis translate_on + --signaux pour la gestion de la MAE + type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, + putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); +signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées +signal count,count_i : natural range 0 to 15:=0; + +signal MPI_Node_in : Ar_MPIPort_in(1 to PROC) ; +signal MPI_Node_Out : Ar_MPIPort_out(1 to PROC); + + + + +BEGIN + Xbar: MPI_NOC GENERIC MAP (NPROC=>NOC_SIZE) + PORT MAP ( + MPI_Node_in => MPI_Node_in, + MPI_Node_Out => MPI_Node_Out + ); + +--PE1: PE generic map (DestId=>0) +--Port Map ( +--Instruction => MPi_Node_in(1).Instruction, +-- Instruction_en => MPi_Node_in(1).Instruction_en, +-- Core_PushOut => MPi_Node_out(1).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(1).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(1).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(1).ram_we, +-- Core_RAM_EN => MPI_Node_out(1).ram_en, +-- -- Core_RAM_ENB => MPI_Node_out(1).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(1).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(1).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(1).hold_req, +-- Core_Hold_Ack => MPI_Node_in(1).hold_ack +--); +-- +--PE2: PE Generic map (DestId=>1) +-- Port Map ( +-- Instruction => MPi_Node_in(2).Instruction, +-- Instruction_en => MPi_Node_in(2).Instruction_en, +-- Core_PushOut => MPi_Node_out(2).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(2).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(2).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(2).ram_we, +-- Core_RAM_EN => MPI_Node_out(2).ram_en, +-- --Core_RAM_ENB => MPI_Node_out(2).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(2).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(2).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(2).hold_req, +-- Core_Hold_Ack => MPI_Node_in(2).hold_ack +--); +--PE3: PE generic map (DestId=>2) +--Port Map ( +--Instruction => MPi_Node_in(3).Instruction, +-- Instruction_en => MPi_Node_in(3).Instruction_en, +-- Core_PushOut => MPi_Node_out(3).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(3).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(3).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(3).ram_we, +-- Core_RAM_EN => MPI_Node_out(3).ram_en, +-- -- Core_RAM_ENB => MPI_Node_out(1).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(3).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(3).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(3).hold_req, +-- Core_Hold_Ack => MPI_Node_in(3).hold_ack +--); +-- +--PE4: PE Generic map (DestId=>3) +-- Port Map ( +-- Instruction => MPi_Node_in(4).Instruction, +-- Instruction_en => MPi_Node_in(4).Instruction_en, +-- Core_PushOut => MPi_Node_out(4).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(4).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(4).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(4).ram_we, +-- Core_RAM_EN => MPI_Node_out(4).ram_en, +-- --Core_RAM_ENB => MPI_Node_out(2).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(4).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(4).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(4).hold_req, +-- Core_Hold_Ack => MPI_Node_in(4).hold_ack +--); +--MPI_Node_in(1).reset<=reset; +--MPI_Node_in(1).clk<=clkm; +--MPI_Node_in(2).reset<=reset; +--MPI_Node_in(2).clk<=clkm; +--MPI_Node_in(3).reset<=reset; +--MPI_Node_in(3).clk<=clkm; +--MPI_Node_in(4).reset<=reset; +--MPI_Node_in(4).clk<=clkm; +Result<=MPi_Node_out(1).PushOut; +PE_s:for i in 1 to STATIC_HT generate +S: PE Generic map (DestId=>i-1) + Port Map ( + Instruction => MPi_Node_in(i).Instruction, + Instruction_en => MPi_Node_in(i).Instruction_en, + Core_PushOut => MPi_Node_out(i).PushOut, + clk =>clkm, + reset =>reset, + CE => '1', + Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out, + Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in, + Core_RAM_WE => MPI_Node_out(i).ram_we, + Core_RAM_EN => MPI_Node_out(i).ram_en, + --Core_RAM_ENB => MPI_Node_out(2).ram_en, + Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr, + Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd, + Core_Hold_req => MPI_Node_out(i).hold_req, + Core_Hold_Ack => MPI_Node_in(i).hold_ack +); +MPI_Node_in(i).reset<=reset; +MPI_Node_in(i).clk<=clkm; +end generate PE_s; +dyn_HT: if dyn_allowed='1' generate +PE_D:for i in STATIC_HT+1 to NOC_SIZE generate +D: PE Generic map (DestId=>i-1) + Port Map ( + Instruction => MPi_Node_in(i).Instruction, + Instruction_en => MPi_Node_in(i).Instruction_en, + Core_PushOut => MPi_Node_out(i).PushOut, + clk =>clkm, + reset =>reset, + CE => '0', + Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out, + Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in, + Core_RAM_WE => MPI_Node_out(i).ram_we, + Core_RAM_EN => MPI_Node_out(i).ram_en, + --Core_RAM_ENB => MPI_Node_out(2).ram_en, + Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr, + Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd, + Core_Hold_req => MPI_Node_out(i).hold_req, + Core_Hold_Ack => MPI_Node_in(i).hold_ack +); +MPI_Node_in(i).reset<=reset; +MPI_Node_in(i).clk<=clkm; +end generate PE_D; +end generate dyn_HT; +END; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MultiMPITest.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MultiMPITest.vhd.bak (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/MultiMPITest.vhd.bak (revision 138) @@ -0,0 +1,228 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM Roland Christian +-- +-- Create Date: 16:44:13 08/01/2012 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/MultiMPITest.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: MPI_NOC +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- +-- +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +library NocLib ; + +use NocLib.CoreTypes.all; +LIbrary MPI_HCL; +use MPI_HCL.Packet_type.all; +use work.Hcl_Arch_conf.all; +USE ieee.numeric_std.ALL; + +ENTITY MultiMPITest IS +--simulation translate_off +port (clkm : in std_logic; +reset : in std_logic; +result : out std_logic_vector(Word-1 downto 0)); +--simulation translate_on +END MultiMPITest; + +ARCHITECTURE behavior OF MultiMPITest IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT MPI_NOC + generic (NPROC: natural:=2); + PORT( + MPI_Node_in : IN Ar_MPIPort_in(1 to NPROC); + MPI_Node_Out : OUT Ar_MPIPort_out(1 to NPROC) + ); + END COMPONENT; + Component PE + generic(destid : natural); + Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : out STD_LOGIC; + Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + CE : in STD_LOGIC; + Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_WE : in STD_LOGIC; + Core_RAM_EN : in STD_LOGIC; + --Core_RAM_ENB : in STD_LOGIC; + Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_Hold_req : in STD_LOGIC; + Core_Hold_Ack : out STD_LOGIC); +end Component; + + constant clk_period : time := 15 ns; + constant PROC : positive :=4; +-- synthesis translate_off +--===================signaux pour l'horloge ============================== +--signal reset,clkm : std_logic := '0'; +--======================================================================== +-- synthesis translate_on + --signaux pour la gestion de la MAE + type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, + putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); +signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées +signal count,count_i : natural range 0 to 15:=0; + +signal MPI_Node_in : Ar_MPIPort_in(1 to PROC) ; +signal MPI_Node_Out : Ar_MPIPort_out(1 to PROC); + + + + +BEGIN + Xbar: MPI_NOC GENERIC MAP (NPROC=>NOC_SIZE) + PORT MAP ( + MPI_Node_in => MPI_Node_in, + MPI_Node_Out => MPI_Node_Out + ); + +--PE1: PE generic map (DestId=>0) +--Port Map ( +--Instruction => MPi_Node_in(1).Instruction, +-- Instruction_en => MPi_Node_in(1).Instruction_en, +-- Core_PushOut => MPi_Node_out(1).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(1).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(1).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(1).ram_we, +-- Core_RAM_EN => MPI_Node_out(1).ram_en, +-- -- Core_RAM_ENB => MPI_Node_out(1).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(1).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(1).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(1).hold_req, +-- Core_Hold_Ack => MPI_Node_in(1).hold_ack +--); +-- +--PE2: PE Generic map (DestId=>1) +-- Port Map ( +-- Instruction => MPi_Node_in(2).Instruction, +-- Instruction_en => MPi_Node_in(2).Instruction_en, +-- Core_PushOut => MPi_Node_out(2).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(2).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(2).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(2).ram_we, +-- Core_RAM_EN => MPI_Node_out(2).ram_en, +-- --Core_RAM_ENB => MPI_Node_out(2).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(2).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(2).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(2).hold_req, +-- Core_Hold_Ack => MPI_Node_in(2).hold_ack +--); +--PE3: PE generic map (DestId=>2) +--Port Map ( +--Instruction => MPi_Node_in(3).Instruction, +-- Instruction_en => MPi_Node_in(3).Instruction_en, +-- Core_PushOut => MPi_Node_out(3).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(3).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(3).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(3).ram_we, +-- Core_RAM_EN => MPI_Node_out(3).ram_en, +-- -- Core_RAM_ENB => MPI_Node_out(1).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(3).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(3).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(3).hold_req, +-- Core_Hold_Ack => MPI_Node_in(3).hold_ack +--); +-- +--PE4: PE Generic map (DestId=>3) +-- Port Map ( +-- Instruction => MPi_Node_in(4).Instruction, +-- Instruction_en => MPi_Node_in(4).Instruction_en, +-- Core_PushOut => MPi_Node_out(4).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(4).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(4).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(4).ram_we, +-- Core_RAM_EN => MPI_Node_out(4).ram_en, +-- --Core_RAM_ENB => MPI_Node_out(2).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(4).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(4).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(4).hold_req, +-- Core_Hold_Ack => MPI_Node_in(4).hold_ack +--); +--MPI_Node_in(1).reset<=reset; +--MPI_Node_in(1).clk<=clkm; +--MPI_Node_in(2).reset<=reset; +--MPI_Node_in(2).clk<=clkm; +--MPI_Node_in(3).reset<=reset; +--MPI_Node_in(3).clk<=clkm; +--MPI_Node_in(4).reset<=reset; +--MPI_Node_in(4).clk<=clkm; +Result<=MPi_Node_out(1).PushOut; +PE_s:for i in 1 to STATIC_HT generate +S: PE Generic map (DestId=>i-1) + Port Map ( + Instruction => MPi_Node_in(i).Instruction, + Instruction_en => MPi_Node_in(i).Instruction_en, + Core_PushOut => MPi_Node_out(i).PushOut, + clk =>clkm, + reset =>reset, + CE => '1', + Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out, + Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in, + Core_RAM_WE => MPI_Node_out(i).ram_we, + Core_RAM_EN => MPI_Node_out(i).ram_en, + --Core_RAM_ENB => MPI_Node_out(2).ram_en, + Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr, + Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd, + Core_Hold_req => MPI_Node_out(i).hold_req, + Core_Hold_Ack => MPI_Node_in(i).hold_ack +); +MPI_Node_in(i).reset<=reset; +MPI_Node_in(i).clk<=clkm; +end generate PE_s; +dyn_HT: if dyn_allowed='1' generate +PE_D:for i in STATIC_HT+1 to NOC_SIZE generate +D: PE Generic map (DestId=>i-1) + Port Map ( + Instruction => MPi_Node_in(i).Instruction, + Instruction_en => MPi_Node_in(i).Instruction_en, + Core_PushOut => MPi_Node_out(i).PushOut, + clk =>clkm, + reset =>reset, + CE => '0', + Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out, + Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in, + Core_RAM_WE => MPI_Node_out(i).ram_we, + Core_RAM_EN => MPI_Node_out(i).ram_en, + --Core_RAM_ENB => MPI_Node_out(2).ram_en, + Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr, + Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd, + Core_Hold_req => MPI_Node_out(i).hold_req, + Core_Hold_Ack => MPI_Node_in(i).hold_ack +); +MPI_Node_in(i).reset<=reset; +MPI_Node_in(i).clk<=clkm; +end generate PE_D; +end generate dyn_HT; +END; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/Packet_type.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/Packet_type.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/Packet_type.vhd (revision 138) @@ -0,0 +1,104 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions +-- package definissant le codage des fonctions MPI +-- dans le champs packet type des instructions MPI + +-- Ce fichier définit les trames des instruction MPI qui sont utilisables +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package Packet_type is + + constant ADRLEN1 :natural:=16; + constant MPI_COMM_WORLD :natural:=1; + constant MPI_DEFAULT :natural:=0; + constant MPI_INT :natural:=1; + constant MPI_INFO_NULL :natural:=0; + constant Default_Win :natural:=1; + constant MPI_GET_RANK : std_logic_vector(3 downto 0) := "0000"; + constant MPI_GET_SIZE : std_logic_vector(3 downto 0) := "0001"; + constant MPI_BARRIER : std_logic_vector(3 downto 0) := "0010"; + constant MPI_BARRIER_REACHED : std_logic_vector(3 downto 0) := "0011"; + constant MPI_BARRIER_COMPLETED : std_logic_vector(3 downto 0) := "1110"; + constant MPI_ACK : std_logic_vector(3 downto 0) := "0100"; + constant MPI_PUT : std_logic_vector(3 downto 0) := "0101"; + constant MPI_GET : std_logic_vector(3 downto 0) := "0110"; + constant MPI_BROADCAST : std_logic_vector(3 downto 0) := "0111"; + constant MPI_INIT : std_logic_vector(3 downto 0) := "1000"; + constant MPI_SPAWN : std_logic_vector(3 downto 0) := "1001"; + + constant MPI_WIN_CREATE : std_logic_vector(3 downto 0) := "1010"; + constant MPI_WIN_SYNC :std_logic_vector(3 downto 0):="1011"; + constant MPI_WIN_COMPLETE : std_logic_vector(3 downto 0) := "1100"; + constant MPI_WIN_POST : std_logic_vector(3 downto 0) := "1101"; + constant MPI_WIN_WAIT : std_logic_vector(3 downto 0) := "1110"; + + + + constant MPI_WTIME : std_logic_vector(3 downto 0) := "1110"; + constant MPI_WTICK : std_logic_vector(3 downto 0) := "1111"; + constant MPI_CONFIG : std_logic_vector(3 downto 0) := "1101"; + --paramètres des commandes + Constant INIT_SEEKMAIN : std_logic_vector(3 downto 0) := "0001"; + Constant INIT_SETRANK : std_logic_vector(3 downto 0) := "0011"; + Constant INIT_REGISTER : std_logic_vector(3 downto 0) := "0010"; + Constant INIT_STAT : std_logic_vector(3 downto 0) := "0100"; + Constant INIT_SPAWN : std_logic_vector(3 downto 0) := "0101"; + + Constant SPAWN_LOAD : std_logic_vector(3 downto 0) := "1001"; + Constant SPAWN_START : std_logic_vector(3 downto 0) := "1010"; + Constant SPAWN_COMP : std_logic_vector(3 downto 0) := "1011"; + Constant SPAWN_ERR : std_logic_vector(3 downto 0) := "1110"; + +Constant SYNC_WSTART : std_logic_vector(3 downto 0) := "0001"; + Constant SYNC_WPOST : std_logic_vector(3 downto 0) := "0010"; + Constant SYNC_WCOMP : std_logic_vector(3 downto 0) := "0011"; + Constant SYNC_WWAIT : std_logic_vector(3 downto 0) := "0100"; +-- constantes pour le NoC + Constant NOC_GETPORTID : std_logic_vector(7 downto 0) := "00000001"; +--constante pour les Ptr +constant W_Status :natural:=0; --position relative des champs dans la mémoire +constant W_Id :natural:=2; -- pour le type MPI_Win +constant W_GStart :natural:=3; +constant W_GPost :natural:=5; +constant W_Addr :natural:=7; +constant W_Size :natural:=9; +constant W_comm :natural:=10; + +Type MPI_Datatype is (MPI_BYTE,MPI_INTEGER,MPI_REAL,MPI_PACKET, MPI_pointer); +SUBType MPI_COMM is natural range 0 to 2**ADRLEN1-1 ; --pointeur sur la structure du communicateur +subType Mpi_AInt is natural range 0 to 2**ADRLEN1-1 ; +--subType Mpi_win is natural range 0 to 2**ADRLEN1-1 ; +Type MPI_COMM_struc is record + id : natural range 0 to 3; -- id du communicateur + grp : std_logic_vector(15 downto 0); --groupe associé au communicateur + nproc : natural range 0 to 15; -- nombre de membres du groupe de ce communicateur + AddrLib : std_logic_vector(15 downto 0); -- adresse dans la mémoire de la Lib + -- des registres GStart et GPost + ParentId:natural range 0 to 3; --Id du communicateur parent si Intercomm=1 + C_open,C_close,InterComm : std_logic; -- état du communciateur (Inistialisé ou finalisé) +end record; + +Type Mpi_Win is record + status : std_logic_vector(7 downto 0); --état de la fenêtre (create,Start,Complete,Post,WaitSync, etc.) + id : natural range 0 to 15 ; -- numéro de la fenêtre + + Addr : std_logic_vector(15 downto 0); -- adresse dans la mémoire locale du PE + Size : natural range 0 to 65535; -- taille de la fenêtre en octets + GPost : std_logic_vector(15 downto 0);--registres de synchronisation en cible + GStart : std_logic_vector(15 downto 0);-- registre de synchronisation source + comm : MPI_COMM; -- Ptr sur communicateur associé à la fenêtre +end record; +Type Mpi_group is record --normalement sous-goupe d'un communicateur + grp : std_logic_vector(15 downto 0); --( vecteur de la liste des processus du groupe) + nb : natural range 0 to 15; -- nombre de membres(processus du groupe) + comm_id : natural range 0 to 3; -- reférence du communicateur +end record; +end Packet_type; + +package body Packet_type is + + +end Packet_type; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/Processing_node.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/Processing_node.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/Processing_node.vhd (revision 138) @@ -0,0 +1,397 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 01:27:32 04/20/2012 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/MPICORETEST.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: MPI_NOC +-- +-- Dependencies: +-- +-- Revision: 11 Juillet 2012 +-- Revision 0.01 - File Created +-- Additional Comments : entité de test de l'environement MPSOC il est constitué d'une +--MAE simulant le processeur +-- Notes: +-- +-- +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +library NocLib ; +--use IEEE.STD_LOGIC_ARITH.ALL; +--use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +USE ieee.numeric_std.ALL; + +ENTITY PROCESSING_ELEMENT IS +-- entité du processeur du MPI +port ( clk : in std_logic; + reset : in std_logic; + ram_we : in std_logic; + ram_ena : in std_logic; + ram_enb : in std_logic; + ram_do : out std_logic_vector( downto ); --word - 1 downto 0 + ram_din : in std_logic_vector(word - 1 downto 0);--word - 1 downto 0 + ram_addra : out std_logic_vector(ADRLEN - 1 downto 0);-- ADRLEN - 1 downto 0 + ram_addrb : out std_logic_vector(ADRLEN - 1 downto 0);-- ADRLEN - 1 downto 0 + instruction_en : out std_logic; + hold_request : in std_logic; + hold_ack : out std_logic; + ram_sel : out std_logic; + lib_ready : in std_logic; + lib_initialized : in std_logic; + ); +END PROCESSING_ELEMENT; + +ARCHITECTURE behavior OF PROCESSING_ELEMENT IS + + --données du programme PE + signal SrcAdr0, SrcAdr1, destAdr0, destAdr1, Datalen : std_logic_vector(word - 1downto 0);-- + signal dpid,dpid_i : natural range 0 to 15; + --signaux pour la gestion de la MAE + type typ_mae is (InitApp,InitCompleted,writeptr, putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); + signal dcount : natural range 0 to 255:= 0; --permet de compter le packet de données envoyées + signal count,count_i : natural range 0 to 15:=0; +--signal adresse,adresse_rd :natural range 0 to 65536; + signal etPutGet : typ_mae; + signal Ram_busy :std_logic:='0'; + --constant pour la construction du fichier + -- ces lignes devront être commentées lors de l'assemblage final +BEGIN + + +dpid<=dpid_i; + pPutGet : process(clk) + + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout : natural range 0 to 255; + variable adrToset : std_logic_vector(15 downto 0); + variable adresse,adresse_rd :natural range 0 to 65536; + begin + if (clk'event and clk ='1') then + if reset='1' then + etputget<= InitApp; + adresse:=0; + adresse_rd:=0; + timeout:=0; + dcount<=0; + else + case etputget is + + when InitApp => + --code pour Init ici + --mettre mpi_init à l'adresse mpi + --initialisation du module mpi du pn + ram_do <=MPI_INIT & x"0" ; + fsrc:=1; + adrToSet:=std_logic_vector(to_unsigned(core_init_adr,16)); + if ret/=fsrc then + dcount<=0; + etputget<=writeptr; + adresse:=core_base_adr+2; + else + adresse:=core_init_adr; + etputget<= InitCompleted; + end if; + + when writeptr => + + if PE_Hold_req = '0' then --s'assurer que le bus est disponible + if dcount=0 then + ram_do <=AdrToSet(7 downto 0); + dcount <=dcount+1; + --adresse:=adresse+1; --prépare la prochaine écriture + elsif dcount=1 then + dcount <=dcount+1; + adresse:=adresse+1; --prépare la prochaine écriture + ram_do <=AdrToSet(15 downto 8); + elsif dcount=2 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + ret:=fsrc; + dcount<=0; + timeout:=0; + if fsrc=1 then + etputget <= InitApp; + elsif fsrc=2 then + etputget <= putdata; + elsif fsrc=3 then + etputget <= getdata; + else + etputget <= start; + end if; + + end if; + + end if; + when InitCompleted => + if Lib_Init='1' then + etputget <= putdata; + end if; + when putdata => --construire le packet pour le Put + DestRank:=1; + adresse_rd:=core_base_adr+Core_Rank2port_base+DestRank; + timeout:=0; + dcount<=0; + fsrc:=2; + adrToSet:=std_logic_vector(to_unsigned(core_put_adr,16)); + if ret/=fsrc then + etputget<=writeptr; + ret:=0; + else + etputget<= putdata2; + end if; + + when putdata2 => + if dcount<5 then + dcount<=dcount+1; + if dcount=0 then + adresse:=core_put_adr; + ram_do <=MPI_PUT & std_logic_vector(to_unsigned(Dpid,4)); + elsif dcount=1 then + adresse:=core_put_adr+dcount; + ram_do <=SrcAdr1 ; + elsif dcount=2 then + adresse:=core_put_adr+dcount; + ram_do <=SrcAdr0 ; + elsif dcount=3 then + adresse:=core_put_adr+dcount; + ram_do <=DestAdr1 ; + elsif dcount=4 then + adresse:=core_put_adr+dcount; + ram_do <=DestAdr0 ; + elsif dcount=5 then + adresse:=core_put_adr+dcount; + ram_do <=Datalen ; + end if; + else + adresse:=core_base_adr+1; + adresse_rd:=core_base_adr; + ram_do <=x"01"; --instruction pulse enable; + if ram_din(1)='1' then -- Instruction ack + if PE_Hold_Req='0' then + adresse:=core_base_adr+1; + ram_do <=x"00"; --ramener le IPulse à 0; + etPutGet<=putcompleted; + else + + end if; + end if; + end if; + + when putcompleted => + adresse_rd:=core_put_adr+6; + if ram_din(0)='1' then --Put completed + etPutGet<=GetData; + end if; + when getdata => --positionnement du mot de longueur des données + adresse:=core_get_adr; + DestRank:=1; + timeout:=0; + dcount<=0; + fsrc:=3; + adrToSet:=std_logic_vector(to_unsigned(core_get_adr,16)); + if ret/=fsrc then + + etputget<=writeptr; + ret:=0; + else + etputget<= getdata2; + end if; + + when getdata2 => + if dcount<5 then + dcount<=dcount+1; + if dcount=0 then + adresse:=core_get_adr; + ram_do <=MPI_GET & std_logic_vector(to_unsigned(Dpid,4)); + adresse:=core_get_adr+dcount; + ram_do <=SrcAdr1 ; + elsif dcount=2 then + adresse:=core_get_adr+dcount; + ram_do <=SrcAdr0 ; + elsif dcount=3 then + adresse:=core_get_adr+dcount; + ram_do <=DestAdr1 ; + elsif dcount=4 then + adresse:=core_get_adr+dcount; + ram_do <=DestAdr0 ; + elsif dcount=5 then + adresse:=core_get_adr+dcount; + ram_do <=Datalen; + end if; + else + adresse:=core_base_adr+1; + adresse_rd:=core_base_adr; + ram_do <=x"01"; --instruction pulse enable; + if ram_din(1)='1' then -- Instruction ack + etPutGet<=getcompleted; + else + + end if; + end if; + + when getcompleted => + adresse_rd:=core_get_adr+6; + if ram_din(0)='1' then --Put completed + if PE_Hold_Req='0' then + adresse:=core_base_adr+1; + ram_do <=x"00"; --ramener le IPulse à 0; + etPutGet<=Terminate; + else + timeout:=timeout+1; + end if; + end if; + + + when terminate => + + + etputget<=start; + + when st_timeout => + + --if ram_busy='1' then + etputget<=start; + --end if + etputget<=start; + end case; + ram_addra <=STD_LOGIC_VECTOR(to_unsigned(adresse,16)); + ram_addrb <=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16)); + end if; --reset='1' + end if; + end process pPutGet; + +majPutGet:process (etputget) + + begin + case etputget is + when start => + ram_we <='0'; + ram_ena<='0'; + ram_enb<='0'; + instruction_en<='0'; + + when fillmem => + ram_we <='1'; + ram_ena<='1'; + + ram_enb<='0'; + instruction_en<='0'; + when nextfill => + ram_we <='1'; + ram_ena<='1'; + ram_enb<='0'; + instruction_en<='0'; + when InitApp => + ram_we <='1'; + ram_ena<='1'; + ram_enb<='0'; + instruction_en<='0'; + when Initcompleted => + instruction_en<='1'; + when writeptr => + ram_we <='1'; --écriture dans la RAM + ram_ena <='1'; + + ram_enb <='0'; + -- dcount<=dcount+1; + + instruction_en<='0'; + + when putdata => --positionnement du mot de longueur des données + --dcount<=0; + srcadr0<=X"00"; + srcadr1<=X"01"; + destadr0<=X"00"; + destadr1<=X"02"; + ram_we <='0'; + ram_ena<='0'; + --lecture du n° de port de destination + ram_enb<='1'; + datalen<=std_logic_vector(to_unsigned(50,8)); + dpid_i<=to_integer(unsigned(ram_din(3 downto 0))); --le port est situé ur les 4 bits de poids faible + instruction_en<='0'; + when putdata2 => + ram_we <='1'; --écriture dans la RAM + ram_ena <='1'; + + ram_enb <='0'; + -- dcount<=dcount+1; + if dcount=5 then + instruction_en<='1'; + else + instruction_en<='0'; + end if; + when putcompleted => + ram_we <='1'; + ram_ena <='1'; + -- lecture du résultat + ram_enb <='1'; + instruction_en<='1'; + when getdata => + --dcount<=0; + srcadr0<=X"00"; + srcadr1<=X"02"; + destadr0<=X"00"; + destadr1<=X"03"; + datalen<=std_logic_vector(to_unsigned(50,8)); + instruction_en<='0'; + when getdata2 => + ram_we <='1'; --écriture dans la RAM + ram_ena <='1'; + + ram_enb <='0'; + --dcount<=dcount+1; + if dcount=5 then + instruction_en<='1'; + else + instruction_en<='0'; + end if; + when getcompleted => + ram_we <='1'; + ram_ena <='1'; + -- lecture du résultat + ram_enb <='1'; + instruction_en<='1'; + when terminate => + + ram_we <='0'; + ram_ena<='0'; + ram_enb<='0'; + instruction_en<='0'; + + when st_timeout => + ram_we <='0'; + ram_ena<='0'; + ram_enb<='0'; + instruction_en <='0'; + end case; +end process majPutGet ; + + hold:process (clk) + begin + if rising_edge(clk) then + if reset='1' then + hold_ack<='0'; + else + if hold_request ='1' then + ramsel<='1'; + pe_hold_ack<= '1';--not(ram_busy); --si la mémoire est occupé, forcé une libération + else + pe_hold_ack<='0'; + ramsel<='0'; + end if; + end if; + end if; + end process hold; +END; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/RAM_32_32.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/RAM_32_32.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/RAM_32_32.vhd (revision 138) @@ -0,0 +1,105 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM NGOUNOU +-- +-- Create Date: 18:33:31 03/05/2012 +-- Design Name: +-- Module Name: RAM_32_32 - Behavioral +-- Project Name: MPI_Core +-- Target Devices: +-- Tool versions: +-- Description: permet de stocker les données locales de la librairie MPI +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RAM_v is +generic(width : positive:=32; Size:positive:=16); +Port ( clka, clkb : in std_logic; + wea : in std_logic; + ena, enb : in std_logic; + addra, addrb : in std_logic_vector(size-1 downto 0); --cinq lignes d'adresse + dia : in std_logic_vector(width-1 downto 0); + dob : out std_logic_vector(width-1 downto 0)); +end RAM_v; + +architecture Behavioral of RAM_v is + attribute RAM_STYLE : string; + signal Lra,Lrb :std_logic:='0'; + signal sel : std_logic_vector(1 downto 0); + signal doa,dout : std_logic_vector(width-1 downto 0); + type ram_type is array (2**(size-3)-1 downto 0) of std_logic_vector (width-1 downto 0); + signal RAM: ram_type; + attribute RAM_STYLE of RAM: signal is "BLOCK"; +begin + process (clka) + begin + if clka'event and clka = '1' then + if ena = '1' then + if wea = '1' then + if conv_integer(addra)>8191 then + report "Erreur d'adresse"; + else + RAM(conv_integer(addra)) <= dia; + end if; + end if; + if conv_integer(addrb)>8191 then + report "Erreur d'adresse"; + else + doa<=RAM(conv_integer(addrb)); + end if; + Lra<='1'; + else + if lrb='1' then + Lra<='0'; + end if; + end if; + end if; + end process; + + + process (clkb) + begin + if clkb'event and clkb = '1' then + if enb = '1' then + Lrb<='1'; + if conv_integer(addrb)>8191 then + report "Erreur d'adresse"; + else + dout <= RAM(conv_integer(addrb)) ; + end if; + else + if Lra='1' then + Lrb<='0'; + end if; + end if; + end if; + end process; + + sel<=(Lra,Lrb); + With sel select + dob <=dout when "11", + doa when "10", + dout when "01", + dout when "00", + dout when others; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/RAM_64.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/RAM_64.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/RAM_64.vhd (revision 138) @@ -0,0 +1,67 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 18:54:08 04/19/2011 +-- Design Name: +-- Module Name: RAM_64 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: SYNTHESE d'une RAM 64 octet par inferation +-- la ram possède un port d'écriture et un port de lecture +-- le port primaire est à lecture et ecrite et le port secondaire à lecture seule +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RAM_64 is + Port ( clka, clkb : in std_logic; + wea : in std_logic; + ena, enb : in std_logic; + addra, addrb : in std_logic_vector(5 downto 0); + dia : in std_logic_vector(Word-1 downto 0); + dob : out std_logic_vector(Word-1 downto 0)); +end RAM_64; + +architecture Behavioral of RAM_64 is + type ram_type is array (63 downto 0) of std_logic_vector (Word-1 downto 0); + signal RAM: ram_type; +begin + process (clka) + begin + if clka'event and clka = '1' then + if ena = '1' then + if wea = '1' then + RAM(conv_integer(addra)) <= dia; + end if; + end if; + end if; + end process; + + process (clkb) + begin + if clkb'event and clkb = '1' then + if enb = '1' then + --dob <= RAM(conv_integer(addrb)) ; + end if; + end if; + end process; + dob <= RAM(conv_integer(addrb)) ; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/RAM_MUX.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/RAM_MUX.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/RAM_MUX.vhd (revision 138) @@ -0,0 +1,96 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:45:28 07/26/2012 +-- Design Name: +-- Module Name: RAM_MUX - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- Multiplexeur de la memoire du noeud +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +library NocLib ; +--use IEEE.STD_LOGIC_ARITH.ALL; +--use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +USE ieee.numeric_std.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RAM_MUX is + Port ( ram_ena_in : in STD_LOGIC_VECTOR (1 downto 0); + ram_enb_in : in STD_LOGIC_VECTOR (1 downto 0); + ram_we_in : in STD_LOGIC_VECTOR (1 downto 0); + ram_dina_in_0 : in STD_LOGIC_VECTOR (word - 1 downto 0); + ram_dina_in_1 : in STD_LOGIC_VECTOR (word - 1 downto 0); + ram_addra_in_0 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_addra_in_1 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_addrb_in_0 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_addrb_in_1 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_dob_in : in STD_LOGIC_VECTOR (word - 1 downto 0); + + + ram_ena_out : out STD_LOGIC; + ram_enb_out : out STD_LOGIC; + ram_we_out : out STD_LOGIC; + ram_dina_out : out STD_LOGIC_VECTOR (word - 1 downto 0); + ram_addra_out : out STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_addrb_out : out STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_dob_out_0 : out STD_LOGIC_VECTOR (word - 1 downto 0); + ram_dob_out_1 : out STD_LOGIC_VECTOR (word - 1 downto 0); + sel : in std_logic + ); +end RAM_MUX; + +architecture Behavioral of RAM_MUX is + +begin + +mux : process(sel,ram_ena_in,ram_enb_in ,ram_we_in,ram_dina_in_0, ram_dina_in_1,ram_addra_in_0,ram_addra_in_1, ram_addrb_in_0, ram_addrb_in_1, ram_dob_in) + begin + + if sel = '1' then + -- si sel est à 1 les entrées 1 sont sur les sorties correspondantes + ram_ena_out <= ram_ena_in(1); + ram_enb_out <= ram_enb_in(1); + ram_we_out <= ram_we_in(1); + ram_dina_out <= ram_dina_in_1; + ram_addra_out <= ram_addra_in_1; + ram_addrb_out <= ram_addrb_in_1 ; + ram_dob_out_1 <= ram_dob_in; + ram_dob_out_0 <= (others => '0'); + else + -- si est à 0 les entrées 0 sont sur les sorties correspondantes + ram_ena_out <= ram_ena_in(0); + ram_enb_out <= ram_enb_in(0); + ram_we_out <= ram_we_in(0); + ram_dina_out <= ram_dina_in_0; + ram_addra_out <= ram_addra_in_0; + ram_addrb_out <= ram_addrb_in_0 ; + ram_dob_out_0 <= ram_dob_in; + ram_dob_out_1 <= (others => '0'); + + end if; + + + end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/RAM_block.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/RAM_block.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/RAM_block.vhd (revision 138) @@ -0,0 +1,228 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM NGOUNOU +-- +-- Create Date: 18:33:31 03/05/2012 +-- Design Name: +-- Module Name: RAM_32_32 - Behavioral +-- Project Name: MPI_Core +-- Target Devices: +-- Tool versions: +-- Description: permet de stocker les données locales de la librairie MPI +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RAM_v is +generic(width : positive:=32; Size:positive:=16); +Port ( clka, clkb : in std_logic; + reset: in std_logic; + wea : in std_logic; + ena, enb : in std_logic; + addra, addrb : in std_logic_vector(size-1 downto 0); --cinq lignes d'adresse + dia : in std_logic_vector(width-1 downto 0); + dob : out std_logic_vector(width-1 downto 0)); +end RAM_v; + +architecture Behavioral of RAM_v is + attribute RAM_STYLE : string; + signal Lra,Lrb :std_logic:='0'; + signal doado,dobdo:std_logic_vector(15 downto 0); + signal DOPBDOP : std_logic_vector(1 downto 0); + signal ADDRAWRADDR,ADDRBRDADDR :std_logic_vector(13 downto 0); + signal REGCEA:std_logic; + signal DIADI :std_logic_vector(15 downto 0); -- 16-bit input: A port data/LSB data input + signal DIPADIP :std_logic_vector(1 downto 0); -- 2-bit input: A port parity/LSB parity input + signal REGCEBREGCE :std_logic ; -- 1-bit input: B port register enable/Register enable input + signal RSTBRST :std_logic ; -- 1-bit input: B port set/reset input + signal WEBWEU :std_logic_vector(1 downto 0):=(others=>'0') ; -- 2-bit input: B port write enable input + -- Port B Data: 16-bit (each) input: Port B data + signal DIBDI :std_logic_vector(15 downto 0):=(others=>'1'); -- 16-bit input: B port data/MSB data input + signal DIPBDIP :std_logic_vector(1 downto 0):=(others=>'1'); -- 2-bit input: B port parity/MSB parity input + signal sel : std_logic_vector(1 downto 0); + signal doa,dout : std_logic_vector(width-1 downto 0); + type ram_type is array (2**(size-3)-1 downto 0) of std_logic_vector (width-1 downto 0); + signal RAM: ram_type; + attribute RAM_STYLE of RAM: signal is "BLOCK"; +begin + -- RAMB8BWER: 8k-bit Data and 1k-bit Parity Configurable Synchronous Block RAM + -- Spartan-6 + -- Xilinx HDL Language Template, version 13.3 + + RAMB8BWER_inst : RAMB8BWER + generic map ( + -- DATA_WIDTH_A/DATA_WIDTH_B: 'If RAM_MODE="TDP": 0, 1, 2, 4, 9 or 18; If RAM_MODE="SDP": 36' + DATA_WIDTH_A => 9, + DATA_WIDTH_B => 9, + -- DOA_REG/DOB_REG: Optional output register (0 or 1) + DOA_REG => 0, + DOB_REG => 0, + -- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST + EN_RSTRAM_A => TRUE, + EN_RSTRAM_B => TRUE, + -- INITP_00 to INITP_03: Initial memory contents. + INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + -- INIT_00 to INIT_1F: Initial memory contents. + INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", + INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", + -- INIT_A/INIT_B: Initial values on output port + INIT_A => X"00000", + INIT_B => X"00000", + -- INIT_FILE: Not Supported + INIT_FILE => "NONE", -- Do not modify + -- RAM_MODE: "SDP" or "TDP" + RAM_MODE => "TDP", + -- RSTTYPE: "SYNC" or "ASYNC" + RSTTYPE => "SYNC", + -- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR" + RST_PRIORITY_A => "CE", + RST_PRIORITY_B => "CE", + -- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE" + SIM_COLLISION_CHECK => "ALL", + -- SRVAL_A/SRVAL_B: Set/Reset value for RAM output + SRVAL_A => X"00000", + SRVAL_B => X"00000", + -- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" + WRITE_MODE_A => "WRITE_FIRST", + WRITE_MODE_B => "WRITE_FIRST" + ) + port map ( + -- Port A Data: 16-bit (each) output: Port A data + DOADO => DOADO, -- 16-bit output: A port data/LSB data output + DOPADOP => DOPADOP, -- 2-bit output: A port parity/LSB parity output + -- Port B Data: 16-bit (each) output: Port B data + DOBDO => DOBDO, -- 16-bit output: B port data/MSB data output + DOPBDOP => DOPBDOP, -- 2-bit output: B port parity/MSB parity output + -- Port A Address/Control Signals: 13-bit (each) input: Port A address and control signals (write port + -- when RAM_MODE="SDP") + ADDRAWRADDR => ADDRAWRADDR, -- 13-bit input: A port address/Write address input + CLKAWRCLK => CLKA, -- 1-bit input: A port clock/Write clock input + ENAWREN => ENA, -- 1-bit input: A port enable/Write enable input + REGCEA => REGCEA, -- 1-bit input: A port register enable input + RSTA => Reset, -- 1-bit input: A port set/reset input + WEAWEL => WEA, -- 2-bit input: A port write enable input + -- Port A Data: 16-bit (each) input: Port A data + DIADI => DIADI, -- 16-bit input: A port data/LSB data input + DIPADIP => DIPADIP, -- 2-bit input: A port parity/LSB parity input + -- Port B Address/Control Signals: 13-bit (each) input: Port B address and control signals (read port + -- when RAM_MODE="SDP") + ADDRBRDADDR => ADDRBRDADDR, -- 13-bit input: B port address/Read address input + CLKBRDCLK => clkb, -- 1-bit input: B port clock/Read clock input + ENBRDEN => ENB, -- 1-bit input: B port enable/Read enable input + REGCEBREGCE => REGCEBREGCE, -- 1-bit input: B port register enable/Register enable input + RSTBRST => reset, -- 1-bit input: B port set/reset input + WEBWEU => WEBWEU, -- 2-bit input: B port write enable input + -- Port B Data: 16-bit (each) input: Port B data + DIBDI => DIBDI, -- 16-bit input: B port data/MSB data input + DIPBDIP => DIPBDIP -- 2-bit input: B port parity/MSB parity input + ); + + DIADI(width-1 downto 0)<=dia; + ADDRAWRADDR <=addra(10 downto 0); + ADDRBRDADDR <=addrb(10 downto 0); + doa<=DOADO(width-1 downt0 0); + dout<=DOBDO(width-1 downt0 0); + process (clka) + begin + if clka'event and clka = '1' then + if ena = '1' then + if wea = '1' then + if conv_integer(addra)>8191 then + report "Erreur d'adresse"; + else + --RAM(conv_integer(addra)) <= dia; + end if; + end if; + if conv_integer(addrb)>8191 then + report "Erreur d'adresse"; + else + --doa<=RAM(conv_integer(addrb)); + end if; + Lra<='1'; + else + if lrb='1' then + Lra<='0'; + end if; + end if; + end if; + end process; + + + process (clkb) + begin + if clkb'event and clkb = '1' then + if enb = '1' then + Lrb<='1'; + if conv_integer(addrb)>8191 then + report "Erreur d'adresse"; + else + --dout <= RAM(conv_integer(addrb)) ; + end if; + else + if Lra='1' then + Lrb<='0'; + end if; + end if; + end if; + end process; + + sel<=(Lra,Lrb); + With sel select + dob <=dout when "11", + doa when "10", + dout when "01", + dout when "00", + dout when others; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/SetBit.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/SetBit.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/SetBit.vhd (revision 138) @@ -0,0 +1,187 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:30:11 08/01/2013 +-- Design Name: +-- Module Name: SetBit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +Library NocLib; +use NoCLib.CoreTypes.all; +--use work.packet_type.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity SetBit is + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + BitMask : in std_logic_vector(Word-1 downto 0); + BitVal : in std_logic; + whole : in std_logic; + dma_wr_grant : in STD_LOGIC; + dma_wr_request : out STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + ram_rd : out std_logic; + ram_wr : out std_logic; + start : in std_logic; + done : out std_logic; + ram_address : in std_logic_vector(ADRLEN-1 downto 0);--accès au stockage + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0)); +end SetBit; + +architecture Behavioral of SetBit is +signal State,Next_State:natural range 0 to 15 :=0; +signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; +signal tempval,tempval_i : std_logic_vector(Word-1 downto 0):=(others=>'1'); +begin +PSetBit_sync:process(clk,reset) + +begin +if rising_edge(clk) then +if reset='1' then + State<=0; + Tempval<=(others=>'0'); +else + State<=Next_State; + Tempval<=tempval_i; +end if; +end if; +end process; + +PSetBit:process (State,tempval,Start,whole,BitMask,BitVal,Dma_rd_grant,Dma_wr_grant,ram_data_out) + begin + Next_State<=State; + + tempval_i<=tempval; + wr_ok<='0'; + rd_ok<='0'; +if State >0 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; +case State is +when 0 =>Ram_data_in<=tempval; + rd_ok<='0'; + Wr_ok<='0'; + done<='0'; + if start='1' and whole='1' then + Next_State<=5; + wr_ok<='0'; + ram_data_in<=bitmask; + elsif start='1' then + Next_State<=State+1; + end if; + +when 1=> Ram_data_in<=tempval; + if dma_rd_grant='1' then + Next_State<=State+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + done<='0'; + When 2|3=>Ram_data_in<=Ram_data_out; + if dma_rd_grant='1' then --cycle d'attente + Next_State<=State+1; + else + Next_State<=1; --recommencer l'attente si perte de priorité + end if; + rd_ok<='1'; + wr_ok<='0'; + done<='0'; + When 4 => + Ram_data_in<=ram_data_out; + done<='0'; + rd_ok<='1'; + if dma_rd_grant='1' and dma_wr_grant='1' then + Next_State<=5; + --tempval<=Ram_data_out; +-- if bitval='1' then +-- tempval<= Ram_data_out or BitMask; +-- else +-- tempval<= Ram_data_out and not (BitMask); +-- end if; + if whole='1' then + --ram_data_in<=bitmask; + tempval_i<= BitMask; + else + if bitval='1' then + --ram_data_in<=Ram_data_out or BitMask; + tempval_i<= Ram_data_out or BitMask; + else + --Ram_data_in<=Ram_data_out and not (BitMask); + tempval_i<= Ram_data_out and not (BitMask); + end if; + end if; + rd_ok<='1'; + wr_ok<='1'; + else + Next_State<=State; + report "SetBit:Impossible d'avoir accès en R/W à la RAM"; + end if; + When 5 |6 => + Ram_data_in<=tempval; + if dma_wr_grant='1' then + if whole='1' then + ram_data_in<=bitmask; + else + ram_data_in<=tempval; + end if; + Next_State<=State+1; + else + Next_state<=5; + end if; + wr_ok<='1'; + rd_ok<='1'; + done<='0'; + When 7=> + done<='1'; + if start='0' then + Next_State<=0; + wr_ok<='0'; + end if; + rd_ok<='0'; + wr_ok<='0'; + Ram_data_in<=tempval; + When others => + Next_State<=0; + rd_ok<='0'; + wr_ok<='0'; + done<='0'; + Ram_data_in<=tempval; +end case; + +end process PSetBit; +dma_rd_request <= dma_rd; +dma_wr_request <=dma_wr; +Ram_wr<=wr_ok; +Ram_rd<=rd_ok; +--Ram_data_out<=data_to_ram; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/SetBit.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/SetBit.vhd.bak (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/SetBit.vhd.bak (revision 138) @@ -0,0 +1,187 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:30:11 08/01/2013 +-- Design Name: +-- Module Name: SetBit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +Library NocLib; +use NoCLib.CoreTypes.all; +--use work.packet_type.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity SetBit is + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + BitMask : in std_logic_vector(Word-1 downto 0); + BitVal : in std_logic; + whole : in std_logic; + dma_wr_grant : in STD_LOGIC; + dma_wr_request : out STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + ram_rd : out std_logic; + ram_wr : out std_logic; + start : in std_logic; + done : out std_logic; + ram_address : in std_logic_vector(ADRLEN-1 downto 0);--accès au stockage + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0)); +end SetBit; + +architecture Behavioral of SetBit is +signal State,Next_State:natural range 0 to 15 :=0; +signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; +signal tempval,tempval_i : std_logic_vector(Word-1 downto 0):=(others=>'1'); +begin +PSetBit_sync:process(clk,reset) + +begin +if rising_edge(clk) then +if reset='1' then + State<=0; + Tempval<=(others=>'0'); +else + State<=Next_State; + Tempval<=tempval_i; +end if; +end if; +end process; + +PSetBit:process (State,tempval,Start,whole,BitMask,BitVal,Dma_rd_grant,Dma_wr_grant,ram_data_out) + begin + Next_State<=State; + + tempval_i<=tempval; + wr_ok<='0'; + rd_ok<='0'; +if State >0 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; +case State is +when 0 =>Ram_data_in<=tempval; + rd_ok<='0'; + Wr_ok<='0'; + done<='0'; + if start='1' and whole='1' then + Next_State<=5; + wr_ok<='1'; + ram_data_in<=bitmask; + elsif start='1' then + Next_State<=State+1; + end if; + +when 1=> Ram_data_in<=tempval; + if dma_rd_grant='1' then + Next_State<=State+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + done<='0'; + When 2|3=>Ram_data_in<=Ram_data_out; + if dma_rd_grant='1' then --cycle d'attente + Next_State<=State+1; + else + Next_State<=1; --recommencer l'attente si perte de priorité + end if; + rd_ok<='1'; + wr_ok<='0'; + done<='0'; + When 4 => + Ram_data_in<=ram_data_out; + done<='0'; + rd_ok<='1'; + if dma_rd_grant='1' and dma_wr_grant='1' then + Next_State<=5; + --tempval<=Ram_data_out; +-- if bitval='1' then +-- tempval<= Ram_data_out or BitMask; +-- else +-- tempval<= Ram_data_out and not (BitMask); +-- end if; + if whole='1' then + --ram_data_in<=bitmask; + tempval_i<= BitMask; + else + if bitval='1' then + --ram_data_in<=Ram_data_out or BitMask; + tempval_i<= Ram_data_out or BitMask; + else + --Ram_data_in<=Ram_data_out and not (BitMask); + tempval_i<= Ram_data_out and not (BitMask); + end if; + end if; + rd_ok<='1'; + wr_ok<='1'; + else + Next_State<=State; + report "SetBit:Impossible d'avoir accès en R/W à la RAM"; + end if; + When 5 |6 => + Ram_data_in<=tempval; + if dma_wr_grant='1' then + if whole='1' then + ram_data_in<=bitmask; + else + ram_data_in<=tempval; + end if; + Next_State<=State+1; + else + Next_state<=5; + end if; + wr_ok<='1'; + rd_ok<='1'; + done<='0'; + When 7=> + done<='1'; + if start='0' then + Next_State<=0; + wr_ok<='0'; + end if; + rd_ok<='0'; + wr_ok<='0'; + Ram_data_in<=tempval; + When others => + Next_State<=0; + rd_ok<='0'; + wr_ok<='0'; + done<='0'; + Ram_data_in<=tempval; +end case; + +end process PSetBit; +dma_rd_request <= dma_rd; +dma_wr_request <=dma_wr; +Ram_wr<=wr_ok; +Ram_rd<=rd_ok; +--Ram_data_out<=data_to_ram; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/fifo_256_fwft_tb.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/fifo_256_fwft_tb.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/fifo_256_fwft_tb.vhd (revision 138) @@ -0,0 +1,85 @@ +LIBRARY ieee ; +LIBRARY unisim ; +LIBRARY work ; +USE ieee.std_logic_1164.all ; +USE ieee.std_logic_arith.all ; +USE ieee.STD_LOGIC_UNSIGNED.all ; +USE unisim.VCOMPONENTS.all ; +USE work.CoreTypes.all ; +ENTITY fifo_256_fwft_tb IS +END ; + +ARCHITECTURE fifo_256_fwft_tb_arch OF fifo_256_fwft_tb IS + SIGNAL dout : std_logic_vector (7 downto 0) ; + SIGNAL srst : STD_LOGIC ; + SIGNAL rd_en : STD_LOGIC ; + SIGNAL clk : STD_LOGIC:='0' ; + SIGNAL full : STD_LOGIC ; + SIGNAL empty : STD_LOGIC ; + SIGNAL wr_en : STD_LOGIC ; + SIGNAL din : std_logic_vector (7 downto 0) ; + COMPONENT FIFO_256_FWFT + PORT ( + dout : out std_logic_vector (7 downto 0) ; + srst : in STD_LOGIC ; + rd_en : in STD_LOGIC ; + clk : in STD_LOGIC ; + full : out STD_LOGIC ; + empty : out STD_LOGIC ; + wr_en : in STD_LOGIC ; + din : in std_logic_vector (7 downto 0) ); + END COMPONENT ; +BEGIN + DUT : FIFO_256_FWFT + PORT MAP ( + dout => dout , + srst => srst , + rd_en => rd_en , + clk => clk , + full => full , + empty => empty , + wr_en => wr_en , + din => din ) ; + + + +clk <= not clk after 5 ns; +srst<='0','1' after 10 ns,'0' after 100 ns; + +input_data:process +begin + + wr_en<='0'; + wait for 10 ns; + srst<='0'; + wr_en<='1'; + for i in 0 to 10 loop + din<=conv_std_logic_vector(i,8); + wait for 10 ns; +end loop; + wr_en<='0'; + wait for 10 ns; + + for i in 11 to 20 loop + wr_en<='1'; + din<=conv_std_logic_vector(i,8); + wait for 10 ns; + wr_en<='0'; + wait for 10 ns; +end loop; + --wait; +end process; + +output_data:process(clk,empty) +begin + -- if rising_edge(clk) then + if empty='0' then + rd_en<='1'; +else + rd_en<='0'; +end if; + +--end if; +end process; + +end fifo_256_fwft_tb_arch; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/fifo_test.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/fifo_test.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/fifo_test.vhd (revision 138) @@ -0,0 +1,46 @@ +-- TestBench Template + + LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE ieee.numeric_std.ALL; + + ENTITY testbench IS + END testbench; + + ARCHITECTURE behavior OF testbench IS + + -- Component Declaration + COMPONENT + PORT( + : IN std_logic; + : IN std_logic_vector(3 downto 0); + : OUT std_logic_vector(3 downto 0) + ); + END COMPONENT; + + SIGNAL : std_logic; + SIGNAL : std_logic_vector(3 downto 0); + + + BEGIN + + -- Component Instantiation + uut: PORT MAP( + => , + => + ); + + + -- Test Bench Statements + tb : PROCESS + BEGIN + + wait for 100 ns; -- wait until global set/reset completes + + -- Add user defined stimulus here + + wait; -- will wait forever + END PROCESS tb; + -- End Test Bench + + END; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/image_pkg.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/image_pkg.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/image_pkg.vhd (revision 138) @@ -0,0 +1,134 @@ +---------------------------------------------------------------------------- +-- Copyright (c) 1996, Ben Cohen. All rights reserved. +-- This model can be used in conjunction with the Kluwer Academic books +-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0 +-- "VHDL Amswers to Frequently Asked Questions", ISBN 0-7923-9791-6 +-- Web page: http://members.aol.com/vhdlcohen/vhdl +-- email: vhdlcohen@aol.com +-- +-- This source file for the image package +-- may be used and distributed without restriction provided +-- that this copyright statement is not removed from the file +-- and that any derivative work contains this copyright notice. +------------------------------------------------------------------------------- +library IEEE; + use IEEE.Std_Logic_1164.all; + use IEEE.Std_Logic_TextIO.all; + use IEEE.Std_Logic_Arith.all; + +library Std; + use STD.TextIO.all; + +package Image_Pkg is + function Image(In_Image : Time) return String; + function Image(In_Image : Bit) return String; + function Image(In_Image : Bit_Vector) return String; + function Image(In_Image : Integer) return String; + function Image(In_Image : Real) return String; + function Image(In_Image : Std_uLogic) return String; + function Image(In_Image : Std_uLogic_Vector) return String; + function Image(In_Image : Std_Logic_Vector) return String; + function Image(In_Image : Signed) return String; + function Image(In_Image : UnSigned) return String; + +end Image_Pkg; + +package body Image_Pkg is + function Image(In_Image : Time) return String is + variable L : Line; -- access type + variable W : String(1 to 25) := (others => ' '); + -- Long enough to hold a time string + begin + -- the WRITE procedure creates an object with "NEW". + -- L is passed as an output of the procedure. + Std.TextIO.WRITE(L, in_image); + -- Copy L.all onto W + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Bit) return String is + variable L : Line; -- access type + variable W : String(1 to 3) := (others => ' '); + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Bit_Vector) return String is + variable L : Line; -- access type + variable W : String(1 to In_Image'length) := (others => ' '); + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Integer) return String is + variable L : Line; -- access type + variable W : String(1 to 32) := (others => ' '); + -- Long enough to hold a time string + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Real) return String is + variable L : Line; -- access type + variable W : String(1 to 32) := (others => ' '); + -- Long enough to hold a time string + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Std_uLogic) return String is + variable L : Line; -- access type + variable W : String(1 to 3) := (others => ' '); + begin + IEEE.Std_Logic_Textio.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Std_uLogic_Vector) return String is + variable L : Line; -- access type + variable W : String(1 to In_Image'length) := (others => ' '); + begin + IEEE.Std_Logic_Textio.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Std_Logic_Vector) return String is + variable L : Line; -- access type + variable W : String(1 to In_Image'length) := (others => ' '); + begin + IEEE.Std_Logic_TextIO.WRITE(L, In_Image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Signed) return String is + begin + return Image(Std_Logic_Vector(In_Image)); + end Image; + + function Image(In_Image : UnSigned) return String is + begin + return Image(Std_Logic_Vector(In_Image)); + end Image; + +end Image_Pkg; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/load_instr.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/load_instr.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/load_instr.vhd (revision 138) @@ -0,0 +1,319 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM NGOUNOU +-- +-- Create Date: 04:57:14 07/15/2012 +-- Design Name: +-- Module Name: load_instr - Behavioral +-- Project Name: MPI CORE +-- Target Devices: +-- Tool versions: +-- Description: Ce module permet de charger une instruction dans le FIFO 1 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +library NocLib; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; +use NocLib.CoreTypes.all; +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity load_instr is + Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : in STD_LOGIC; + + clk : in STD_LOGIC; + reset : in STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC:='0'; + instruction_ack : out STD_LOGIC:='0'; + fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_wr :out std_logic:='0'; + copying :out std_logic:='0'; + fifo_full : in STD_LOGIC; + ram_address_rd : buffer STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0); + Ram_rd_en : out std_logic); +end load_instr; + +architecture Behavioral of load_instr is +--déclaration des types manipulés +type typ_loadinst is (init,setadr,readptr,getbus,readmem,freebus,st_timeout); +--déclaration des signaux +signal Ram_address_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); +--signal ptr, ptr_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); --pointeur vers l'instruction en RAM +signal Base_Adr : STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); +signal adr_ptr : natural range 0 to 65536:=0; +signal Base_AdrSet : std_logic:='0' ; --indique l'adresse de base des instructions positionée +signal fifo_din_i:std_logic_vector(WORD-1 downto 0):=(others=>'-'); +signal iLen,iLen_i : natural range 0 to 15:=0; --longueur de l'instruction à copier dans le Fifo +signal fifo_wr_i :std_logic:='0'; +signal base_adrset_i : std_logic:='0'; +signal instruction_ack_i :std_logic:='0'; +signal Dma_rd_request_i :std_logic:='0'; +signal count,count_i : natural range 0 to 31:=0; --permet de faie évoluer la sous-MAE +signal etloadinst,next_loadinst : typ_loadinst; +begin +SYNC_PROC: process (clk) + begin + if rising_edge(clk) then + if (reset = '1') or instruction_en='0' then + etloadinst <= init; + Base_adrSet<= '0'; + dma_rd_request<='0'; + instruction_ack<='0'; + else + etloadinst <= next_loadinst; + fifo_din <= fifo_din_i; + Base_AdrSet<=Base_adrSet_i; + ram_address_rd<=ram_address_i; + adr_ptr<=to_integer(unsigned(ram_address_i)); + dma_rd_request<=dma_rd_request_i; + instruction_ack<=instruction_ack_i; + count<=count_i; + Ilen<=Ilen_i; + + + -- assign other outputs to internal signals + end if; + end if; + end process; + + -- + OUTPUT_DECODE: process (etloadinst,Count_i,Ram_data,Dma_rd_grant,fifo_wr_i) + variable Adr_inst1,adr_inst2 : natural; + begin + --insert statements to decode internal output signals + --below is simple example + case etloadinst is + when init => + Dma_rd_request_i<='0'; + fifo_wr<='0'; + copying<='0'; + Ram_rd_en<='0'; + Instruction_ack_i<='0'; + fifo_din_i<=(others=>'-'); + Base_AdrSet_i<='0'; + + when SetAdr => + Dma_rd_request_i<='0'; + Instruction_ack_i<='0'; + fifo_wr<='0'; + copying<='0'; + Ram_rd_en<='0'; + + fifo_din_i<=(others=>'-'); + Base_AdrSet_i<='1'; + + when getbus => + fifo_wr<='0'; + copying<='1'; + Ram_rd_en<=Dma_rd_grant; + Dma_rd_request_i<='1'; + Instruction_ack_i<='0'; + fifo_din_i<=(others=>'-'); + Base_AdrSet_i<='1'; + when readptr => + fifo_wr<='0'; + + copying<='1'; + Ram_rd_en<='1'; + Dma_rd_request_i<='1'; + Instruction_ack_i<='0'; + fifo_din_i<=(others=>'-'); + Base_AdrSet_i<='1'; + when readmem => + Dma_rd_request_i<='1'; + copying<='1'; + Ram_rd_en<='1'; + fifo_wr<=fifo_wr_i; + fifo_din_i<=Ram_data; + Base_AdrSet_i<='1'; + Instruction_ack_i<='0'; + + when freebus => + Dma_rd_request_i<='0'; + fifo_wr<='0'; + copying<='0'; + Ram_rd_en<='0'; + Instruction_ack_i<='1'; + fifo_din_i<=(others=>'-'); + Base_AdrSet_i<='1'; + when st_timeout => + Dma_rd_request_i<='0'; + fifo_wr<='0'; + copying<='0'; + Ram_rd_en<='0'; + Instruction_ack_i<='0'; + fifo_din_i<=(others=>'-'); + Base_AdrSet_i<='1'; + end case; + end process; + + NEXT_STATE_DECODE: process (etloadinst, Ram_address_rd,Base_AdrSet,Ram_data,Instruction,instruction_en, fifo_full,dma_rd_grant,count,Ilen) + + variable ptr : std_logic_vector(ADRLEN-1 downto 0); + variable timeout: natural range 0 to 255; + variable Base_AD,ADRtmp,iptr : natural range 0 to 65535; + begin + --declare default state for next_state to avoid latches + next_loadinst <= etloadinst; --default is to stay in current state + Ram_address_i<=Ram_address_rd; + --below is a simple example + case (etloadinst) is + when init => if base_adrset='1' and Instruction_en='1' then + Ilen_i<=to_integer(unsigned(Instruction(3 downto 0)));--initialisation de longueur + next_loadinst<=getbus; + elsif Instruction_en='1' then + next_loadinst<=Setadr; + Base_Adr<=X"0000"; + else + next_loadinst<=init; + Base_Adr<=X"0000"; + Ilen_i<=0; + end if; + fifo_wr_i<='0'; + count_i<=0; + + -- + When Setadr => if Base_adrSet='0' then + Base_Adr<=std_logic_vector(to_unsigned(Core_upper_adr,8)) & X"00"; --récupération des bits de poids forts de l'instruction + -- + end if; + next_loadinst<=init; + Ram_address_i<=(others=>'0'); + count_i<=0; + when getbus => + BASE_AD:=to_integer(unsigned(base_adr)); + if dma_rd_grant = '1' then + next_loadinst <= readptr; + + -- prépare la prochaine lecture + + else + + end if; + Ram_address_i<=(others=>'0'); + count_i<=0; + When readptr => + --s'assurer que le bus est disponible + + if count=0 then + + Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+2,16)); + if dma_rd_grant='1' then + count_i <=count+1; + end if; + elsif count=1 then-- attend que la donnée soit positionnée + if dma_rd_grant = '1' then + count_i <=count+1; + end if; + elsif count=2 then + if dma_rd_grant = '1' then + count_i <=count+1; + ptr(Word-1 downto 0):=Ram_data; + else + count_i<=0; + end if; + Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16)); + + elsif count=3 then + Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16)); + if dma_rd_grant = '1' then + count_i <=count+1; + end if; + elsif count=4 then + if dma_rd_grant = '1' then + ptr(15 downto 8):=Ram_data; + count_i<=0; + timeout:=0; + next_loadinst <= readmem; + else + count_i<=3; + end if; + report "Readptr " & image(ptr); + else + + end if; + + if dma_rd_grant = '0' then + assert true report "Mauvaise lecture" severity failure; + timeout:=timeout+1; + end if; + when readmem => + if fifo_full='0' then + if ilen >0 then + if count=0 then + iptr:=to_integer(unsigned(ptr)); + AdrTmp:=iptr; + if dma_rd_grant = '1' then + count_i <=count+1; + fifo_wr_i<='0'; + end if; + elsif count=1 then + if dma_rd_grant = '1' then + count_i <=count+1; + fifo_wr_i<='0'; + end if; + elsif count=2 then + if dma_rd_grant = '1' then + count_i <=count+1; + fifo_wr_i<='0'; + else + count_i<=1; + end if; + elsif count=3 then + count_i <=count+1; + fifo_wr_i<='1'; --écriture de la donnée dans le fifo + Ilen_i<=Ilen-1; + AdrTmp:=Adr_Ptr+1; + elsif count=4 then + fifo_wr_i<='0'; + count_i<=1; + end if; + else --Ilen=0 ? + fifo_wr_i<='0'; + next_loadinst<=freebus; + end if; + end if; + + Ram_address_i<=STD_LOGIC_VECTOR(to_unsigned(AdrTmp,16)); + if dma_rd_grant = '0' or Fifo_full='1' then + timeout:=timeout+1; + fifo_wr_i<='0'; + Count_i<=1; --recommencer les cycles d'attente de la donnée + if timeout=200 then + next_loadinst<=st_timeout; + end if; + end if; + + when freebus => + fifo_wr_i<='0'; + count_i<=0; + Ram_address_i<=(others=>'0'); + if instruction_en='0' then + next_loadinst <= init; + end if; + when st_timeout => + fifo_wr_i<='0'; + Ram_address_i<=(others=>'0'); + next_loadinst<=init; + report "Copie D'instruction *** RAM/Fifo a été indisponible pour trop longtemps !!!"; + count_i<=0; + end case; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/round_robbin_machine.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/round_robbin_machine.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/round_robbin_machine.vhd (revision 138) @@ -0,0 +1,79 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:53:00 06/13/2011 +-- Design Name: +-- Module Name: round_robbin_machine - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity round_robbin_machine is + Port ( get_request_fifo_empty : in STD_LOGIC; + instruction_fifo_empty : in STD_LOGIC; + priority_rotation : in STD_LOGIC; + clk : in STD_LOGIC; + fifo_selected : out STD_LOGIC; + instruction_available : out STD_LOGIC; + reset : in STD_LOGIC; + mux_sel : out STD_LOGIC); +end round_robbin_machine; + +architecture Behavioral of round_robbin_machine is +signal priority : std_logic; +signal fifo_selected_signal : std_logic; + +begin +-- instruction disponible si au moins un fifo n'est pas vide +instruction_available <= '1' when instruction_fifo_empty = '0' or get_request_fifo_empty = '0' else + '0'; +--signal indiquant a EX1_FSM le fifo selectionne +fifo_selected <= fifo_selected_signal; +mux_sel <= fifo_selected_signal; + +rr_machine_process : process(clk) +begin + if rising_edge(clk) then + if reset = '1' then + priority <= '0'; + fifo_selected_signal <= '0'; + elsif priority_rotation = '1' then + if priority = '0' then + if instruction_fifo_empty = '0' then + fifo_selected_signal <= '0'; + elsif get_request_fifo_empty = '0' then + fifo_selected_signal <= '1'; + end if; + priority <= '1'; + else + if get_request_fifo_empty = '0' then + fifo_selected_signal <= '1'; + elsif instruction_fifo_empty = '0' then + fifo_selected_signal <= '0'; + end if; + priority <= '0'; + end if; + end if; + end if; + end process; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/sim_fifo.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/sim_fifo.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/sim_fifo.vhd (revision 138) @@ -0,0 +1,185 @@ +-- TestBench Template +-- ce module permet de tester le FIFO et de valider son fonctionnement. + LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE ieee.numeric_std.ALL; + Library NocLib ; + use NocLib.CoreTypes.all; + ENTITY testbench IS + END testbench; + + ARCHITECTURE behavior OF testbench IS +constant clk_period : time := 10 ns; +constant MSIZE :natural :=256; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + -- Component Declaration + +component FIFO_256_FWFT --Le FIFO à tester + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(7 downto 0); + rd_en: IN std_logic; + srst: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(7 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +end component; +component proto_receiv -- permet de tester la lecture dans le FIFO +generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_empty,fifo_full : in std_logic; + pop : out std_logic:='0'; + fifo_out : in std_logic_vector(Word-1 downto 0); + rcv_start : in std_logic; --début de la réception + rcv_ack :in std_logic; -- acquittement de la réception + rcv_comp : out std_logic; -- fin de la réception + mem :out memory(0 to sizemem-1)); +end component; + +component proto_send +generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_empty,fifo_full : in std_logic; + push : out std_logic:='0'; + fifo_in : out std_logic_vector(Word-1 downto 0); + snd_start : in std_logic; --début de l'emission + snd_ack :in std_logic; -- acquittement de l'émission + snd_comp : out std_logic; -- fin de l'émission + mem :in memory(0 to sizemem-1)); + + end component; + +type typ_snd_rec is ( fillmem,send1, send2, recv1,recv2); +type typ_receiv is (r_wait,r_head,r_dlen,r_glen,r_start,r_end); + signal storage1,storage2 : memory (0 to MSIZE-1); + SIGNAL fifo_empty,fifo_full : std_logic:='0'; + signal push,pop ,spush,spop: std_logic:='0'; + SIGNAL data_in,data_out: std_logic_vector(7 downto 0); + signal ROn,Rdone,RAck:std_logic:='0'; + signal SOn,Sdone,SAck:std_logic:='0'; + signal etreceiv :typ_receiv; + + signal pipo : typ_snd_rec; + + BEGIN + + + +uut : FIFO_256_FWFT + port map ( + clk => clk, + din => data_in, + rd_en => pop, + srst => reset, + wr_en => push, + dout => data_out, + empty => fifo_empty, + full => fifo_full); + +rec_pro: proto_receiv generic map(sizemem =>MSIZE) + port map (clk=>clk, + reset=>reset, + fifo_empty=>fifo_empty, + fifo_full=>fifo_full, + rcv_start =>Ron, + rcv_ack => Rack, + rcv_comp=> Rdone, + pop=>pop, + fifo_out =>data_out, + mem=>storage2 + ); +snd_pro: proto_send generic map (sizemem =>MSIZE) +port map (clk=>clk, + reset=>reset, + fifo_empty=>fifo_empty, + fifo_full=>fifo_full, + snd_start =>Son, + snd_ack => Sack, + snd_comp=> Sdone, + push=>push, + fifo_in =>data_in, + mem=>storage1 + ); + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + + end process; +reset_proc: process + begin + -- hold reset state for 100 ns. + reset<='0'; + wait for 1 ns; + reset<='1'; + wait for clk_period*10; + reset<='0'; + wait; + -- insert stimulus here +end process; +pr_pingpong : process(clk,reset) +variable i: natural range 0 to MSIZE-1; +begin +if reset='1' then + pipo<=fillmem; + i:=0; + else + if rising_edge(clk) then + case pipo is + when fillmem => -- remplissage de la mémoire d'envoie + if i=0 then + storage1(0)<=x"51"; -- le code de la fonction + elsif i=1 then + storage1(1)<=x"05"; -- le nombre d'octets à envoyer dans le tampon. + elsif (i>=2) and (i<= MSIZE-2) then + storage1(i)<=std_logic_vector(to_unsigned(i-2,Word)); + + else + pipo<=send1; + i:=0; + end if; + i:=i+1; + when send1 => + + Son<='1'; --activer l'emission des données + Sack<='0'; + if i=2 then --activer la réception des données + Ron<='1'; + else + Ron<='0'; + i:=i+1; + end if; + if sdone='1' then + pipo<=send2; + + end if; + when send2 => + i:=0; + Son<='0'; + Sack<='1'; + pipo<=recv1; + when recv1 => + ron<='1'; + rack<='0'; + if Rdone='1' then + pipo<=recv2; + end if; + when recv2 => + Ron<='0'; + Rack<='1'; + pipo<=send1; + i:=0; + end case; + + + end if; +end if; +end process; + +END; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/test_DMA.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/test_DMA.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/CORE_MPI/test_DMA.vhd (revision 138) @@ -0,0 +1,295 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 14:37:10 03/18/2013 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/test_DMA.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: DMA_ARBITER +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY test_DMA IS +END test_DMA; + +ARCHITECTURE behavior OF test_DMA IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT DMA_ARBITER + PORT( + dma_rd_request : IN std_logic_vector(3 downto 0); + data_wr_in : IN std_logic_vector(7 downto 0); + data_rd_out : OUT std_logic_vector(7 downto 0); + address_rd : IN std_logic_vector(15 downto 0); + address_wr : IN std_logic_vector(15 downto 0); + address_out_wr : OUT std_logic_vector(15 downto 0); + address_out_rd : OUT std_logic_vector(15 downto 0); + ram_en : OUT std_logic; + ram_we : OUT std_logic; + data_wr_mem : OUT std_logic_vector(7 downto 0); + data_rd_mem : IN std_logic_vector(7 downto 0); + dma_wr_grant : OUT std_logic_vector(3 downto 0); + hold_req : OUT std_logic; + hold_ack : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + dma_rd_grant : OUT std_logic_vector(3 downto 0); + dma_wr_request : IN std_logic_vector(3 downto 0) + ); + END COMPONENT; + +COMPONENT RAM_v + generic (width : positive;size :positive); + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector; + addrb : IN std_logic_vector; + dia : IN std_logic_vector; + dob : OUT std_logic_vector + ); + END COMPONENT; + --Inputs + signal dma_rd_request : std_logic_vector(3 downto 0) := (others => '0'); + signal data_wr_in : std_logic_vector(7 downto 0) := (others => '0'); + signal address_rd : std_logic_vector(15 downto 0) := (others => '0'); + signal address_wr : std_logic_vector(15 downto 0) := (others => '0'); + signal data_rd_mem : std_logic_vector(7 downto 0) := (others => '0'); + signal hold_ack : std_logic := '0'; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal dma_wr_request : std_logic_vector(3 downto 0) := (others => '0'); + + --Outputs + signal data_rd_out : std_logic_vector(7 downto 0); + signal address_out_wr : std_logic_vector(15 downto 0); + signal address_out_rd : std_logic_vector(15 downto 0); + signal ram_en : std_logic; + signal ram_we : std_logic; + signal data_wr_mem : std_logic_vector(7 downto 0); + signal dma_wr_grant : std_logic_vector(3 downto 0); + signal hold_req : std_logic; + signal dma_rd_grant : std_logic_vector(3 downto 0); + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: DMA_ARBITER PORT MAP ( + dma_rd_request => dma_rd_request, + data_wr_in => data_wr_in, + data_rd_out => data_rd_out, + address_rd => address_rd, + address_wr => address_wr, + address_out_wr => address_out_wr, + address_out_rd => address_out_rd, + ram_en => ram_en, + ram_we => ram_we, + data_wr_mem => data_wr_mem, + data_rd_mem => data_rd_mem, + dma_wr_grant => dma_wr_grant, + hold_req => hold_req, + hold_ack => hold_ack, + clk => clk, + reset => reset, + dma_rd_grant => dma_rd_grant, + dma_wr_request => dma_wr_request + ); + +Inst_RAM_v: RAM_v generic map(width=>8,size=>16) + PORT MAP( + clka =>clk, + clkb => clk, + wea => ram_we, + ena => ram_en, + enb => ram_en, + addra => address_out_wr, + addrb =>address_out_rd, + dia => data_wr_mem, + dob => data_rd_mem + ); + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + reset_proc: process + begin + -- hold reset state for 100 ns. + reset <='1'; + wait for 100 ns; + reset<='0'; + wait for clk_period*10; + + -- insert stimulus here + + wait; + end process; + + stim_proc: process (clk,reset) + variable i,j,k,l : std_logic_vector(15 downto 0); + variable x: integer ; --indique le temps à partir duquel chaque + --permet de faire des requêtes DMA et de les valider + begin + if rising_edge(clk) then + if reset ='1' then + x:=0; + else + x:=x+1; + if x>=1 and x<=20 then + dma_rd_request<="0001"; + elsif x>=21 and x<=40 then + dma_rd_request<="0011"; + elsif x>=41 and x<=60 then + dma_rd_request<="0010"; + elsif x>=61 and x<=80 then + dma_rd_request<="0110"; + elsif x>=81 and x<=100 then + dma_rd_request<="0100"; + elsif x>=61 and x<=80 then + dma_rd_request<="1100"; + elsif x>=101 and x<=120 then + dma_rd_request<="1101"; + elsif x>=121 and x<=140 then + dma_rd_request<="1001"; + elsif x>=141 and x<=160 then + dma_rd_request<="1000"; + elsif x>=161 and x<=180 then + dma_rd_request<="0000"; + elsif x>=181 and x<=200 then + dma_rd_request<="0111"; + elsif x>=181 and x<=200 then + dma_rd_request<="1111"; + elsif x>=181 and x<=200 then + dma_rd_request<="1110"; + else + x:=0; + + end if; + + end if; + end if; + end process; +stim2_proc: process (clk,reset) + variable i,j,k,l : std_logic_vector(15 downto 0); + variable x: integer ; --indique le temps à partir duquel chaque + --permet de faire des requêtes DMA et de les valider + begin + if rising_edge(clk) then + if reset ='1' then + x:=0; + else + x:=x+1; + if x>=1 and x<=10 then + dma_wr_request<="0001"; + elsif x>=11 and x<=20 then + dma_wr_request<="0011"; + elsif x>=21 and x<=30 then + dma_wr_request<="0010"; + elsif x>=31 and x<=40 then + dma_wr_request<="0110"; + elsif x>=41 and x<=50 then + dma_wr_request<="0100"; + elsif x>=51 and x<=60 then + dma_wr_request<="1100"; + elsif x>=61 and x<=80 then + dma_wr_request<="1101"; + elsif x>=81 and x<=90 then + dma_wr_request<="1001"; + elsif x>=91 and x<=100 then + dma_wr_request<="1000"; + elsif x>=101 and x<=110 then + dma_wr_request<="0000"; + elsif x>=111 and x<=120 then + dma_wr_request<="0111"; + elsif x>=121 and x<=130 then + dma_wr_request<="1111"; + elsif x>=131 and x<=200 then + dma_wr_request<="1110"; + else + x:=0; + + end if; + + end if; + end if; + end process; +liredat:process (dma_rd_grant) +begin + + +if dma_rd_grant="0001" then +address_rd<=x"0000"; +elsif dma_rd_grant="0010" then +address_rd<=x"0002"; +elsif dma_rd_grant="0100" then +address_rd<=x"0004"; +elsif dma_rd_grant="1000" then +address_rd<=x"0006"; +else + + address_rd<=x"0000"; +end if; + +end process; +ecriredat:process (dma_wr_grant) +begin + + +if dma_wr_grant="0001" then +address_wr<=x"0000"; +data_wr_in<=x"0a"; +elsif dma_rd_grant="0010" then +address_wr<=x"0002"; +data_wr_in<=x"20"; +elsif dma_rd_grant="0100" then +address_wr<=x"0004"; +data_wr_in<=x"a0"; +elsif dma_rd_grant="1000" then +address_wr<=x"0006"; +data_wr_in<=x"0F"; +else + + address_wr<=x"0000"; + +end if; + +end process; +Hold_ack<=Hold_req; -- toujours autoriser la gestion de la mémoire par le DMA + +END; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/HCL_Arch_conf.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/HCL_Arch_conf.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/HCL_Arch_conf.vhd (revision 138) @@ -0,0 +1,30 @@ +-- Package File Template +-- +-- Purpose: This package defines the size of NoC ports and the number +-- of hardware tasks to create with the Mpi HCL environment. +-- The NoC_size parameter may vary from 2 to 16 +-- The STATIC_HT parameter must be less or equal to the NoC_Size parameter +-- The DYN_ALLOWED authorize the binding of HT template environment to all the Noc Ports + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package Hcl_Arch_conf is + + + +-- Declare constants + + constant NOC_SIZE : integer :=4; --(2 to 16)indicates the number of NoC port to instantiate + constant STATIC_HT : integer := 2;--(2 to NOC_SIZE)gives the the number of HT to Hardwire + constant DYN_ALLOWED : std_logic:='1'; --allow the creation of dynamic hardware tasks +-- Declare functions and procedure + +end Hcl_Arch_conf; + + +package body Hcl_Arch_conf is + + + +end Hcl_Arch_conf; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/HT_process.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/HT_process.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/HT_process.vhd (revision 138) @@ -0,0 +1,561 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:04:21 04/22/2013 +-- Design Name: +-- Module Name: HT_process - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +library NocLib ; + +use std.textio.all; +use NocLib.CoreTypes.all; +Library MPI_HCL; +use MPI_HCL.Packet_type.all; +use MPI_HCL.MPI_RMA.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity HT_process is + generic (Task_id : natural:=0); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + en : in std_logic; -- active la tâche + Interf_i : in core_i; --signaux pour l'interface IO + Interf_o : out core_o; --signaux pour l'interface IO + mem_o : out typ_dpram_o; -- signaux pour l'accès à la mémoire + mem_i : in typ_dpram_i -- signaux pour l'accès à la mémoire + ); +end HT_process; + +architecture Behavioral of HT_process is + constant simres : time :=1 ps; --simulation resolution + constant realres : real :=1.0e-3; --ramener le temps en ns + + type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinPost,WinStart, + putdata,getdata,WinWait,WinCompleted,MpiSpawn,finalize,st_timeout); + signal sram : typ_dpram; + signal MyGroup:mpi_group; + signal MyWin : mpi_win; + signal MyRank :std_logic_vector(3 downto 0); + signal intercomm,array_of_errcodes : natural; + signal ct_state:natural:=0; +signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque +signal RunState : typ_mae; +signal load : std_logic; +signal start1 : std_logic; +signal loadval : std_logic_vector(31 downto 0); +signal outval : std_logic_vector(31 downto 0); +signal zero : std_logic; +COMPONENT IP_Timer + PORT( + clk : IN std_logic; + reset : IN std_logic; + upDn : IN std_logic; + load : IN std_logic; + start : IN std_logic; + loadval : IN std_logic_vector(31 downto 0); + outval : OUT std_logic_vector(31 downto 0); + zero : OUT std_logic + ); + END COMPONENT; +begin +Inst_IP_Timer: IP_Timer PORT MAP( + clk =>clk , + reset => reset, + upDn => '0', + load => load, + start => start1, + loadval => loadval, + outval => outval, + zero => zero + ); + +--MAE du PE +--======================================================================= +-- Interf<=Libr; + + + pPutGet:process(clk,reset,en) + + constant DATAPTR : natural :=256; + variable nb_rma:natural range 0 to 15:=0; + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout,ct,dlen,dcount : natural range 0 to 511; + variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0); + variable mywin : Mpi_win; + variable command , argv , maxprocs , info , root : natural:=0; --variable pour le spawn + variable comm : natural :=0; + variable iack,spawn : std_logic:='0'; + variable adresse,adresse_rd :natural range 0 to 65536; + variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0'); + + --======================================================= + --variables pour la création du fichier de résultats + -- synthesis translate_off + type char_file is file of character; + file f: text; + variable status :file_open_status ; + variable char_count: integer range 0 to 65536 := 0; + variable str: string (1 to 79) ; + variable L: line; + variable fopened: std_logic:='0'; + + -- constant simres : time :=1 ps; --simulation resolution + -- constant realres : real :=1.0e-3; --ramener le temps en ns + -- returns real value of time parameter using pure VHDL + function rt(t : time) return real is + begin + --if (simres=0) then + return real(t/1 ns) * realres; + -- else + -- return 0.0; + -- end if; + end; + -- synthesis translate_on +--====================================================== + begin + --=== Partie combinatoire du process =================================== + + --=== Fin de la partie combinatoire du process ========================== + + + + --end loop; + + if (clk'event and clk='1') and en='1' then + + + if reset='1' then + RunState<=start; + + else + --========================================================== + --affectation des entrées sorties mémoires + sram.i.data_out<=mem_I.data_out; + mem_o.addr_wr<=sram.O.addr_wr; + mem_o.addr_rd<=sram.O.addr_rd ; + mem_o.we<=sram.O.we; + mem_o.ena<=sram.O.ena; + mem_o.enb<=sram.O.enb; + mem_o.data_in<=sram.O.data_in; + --affectation des entrées sorties MPI_HCL + Interf_o.Instr_EN<=Libr.O.instr_en; + Interf_o.Membusy<=Libr.O.MemBusy; + Interf_o.Instruction<=Libr.O.Instruction; + Libr.i.Instr_ack<=Interf_i.Instr_ack; + Libr.i.InitOk<=Interf_i.InitOk; + Libr.i.Hold_Req<=Interf_i.Hold_req; + Libr.I.Spawned<=Interf_i.Spawned; + --Libr.i.Hold_Ack<=Interf_i.Hold_Ack; + Libr.i.RamSel<=Interf_i.RamSel; + --ct_state<=ct; --pour débogage + --============================================================ + + case RunState is + when start => + --Dcount<=0; + if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide + --RunState<=InitApp; + runstate<=fillmem; + end if; + --Ram_busy<='0'; + Libr.O.MemBusy<='0'; + Libr.O.Instr_En<='0'; + iack:='0'; + adresse:=10;--DATAPTR; + + adresse_rd:=0; + timeout:=0; + --dcount<=0; + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + -- synthesis translate_off + if fopened='0' then + file_open(status,f, integer'image(Task_Id) & "test_file0.txt", APPEND_MODE); + --while not endfile(c_file_handle) loop + --end if; + + --write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now))); + --report l.all; + -- writeline (f, l) ; + fopened:='1'; + end if; + -- synthesis translate_on + when Fillmem => + sram.O.we<='1'; + sram.O.ena<='1'; + sram.O.enb<='1'; + if Libr.I.Ramsel='0' then + sram.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + sram.O.addr_wr<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + sram.O.data_in<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f"; + Libr.O.Instr_En<='0'; + dcount:=dcount+1; + timeout:=0; + if dcount=250 then + bfill:=bfill+1; + + if bfill=4 then + --RunState<=WinCreate; + Runstate<=InitApp; + else + RunState<=nextfill; + end if; + else + adresse:=adresse+1; + sram.O.addr_wr<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + RunState<=Fillmem; + end if; + else -- attente de la libéraion de la mémoire + timeout:=timeout+1; + if timeout=500 then + RunState<=st_timeout; + end if; + + end if; + when nextfill => --prépare le prochain bloc mémoire qui sera rempli + adresse:=250*bfill+10; + + dcount:=0; + ct:=0; + RunState<=Fillmem; + Libr.O.Instr_En<='0'; + sram.O.we<='1'; + sram.O.ena<='1'; + sram.O.enb<='0'; + when InitApp => + --code pour Init + dlen:=248; + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen; ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now)))); + + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Init(ct,Libr,Clk,SRam); + + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + --if Libr.InitOk='1' then + if ct=0 then + RunState<=GetRank; + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(Dlen) & ";INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + + when GetRank => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(Dlen)& ";Rank1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + + if ct=0 then + RunState<=Fillmem; + RunState<=Wincreate; + -- synthesis translate_off + write (l,string'("Dlen;"& integer'image(dlen) & ";Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when Wincreate => --par défaut la fenêtre 0 est utilisée ! + case MyRank is + when x"0"=> + Mygroup.grp<=x"0002";-- rank 1 + MyGroup.nb<=2; + destRank:=1; + DestAdr:=X"043F"; + nb_rma:=1; + when x"1" => + Mygroup.grp<=x"0001";-- rank 0 + destRank:=0; + DestAdr:=X"043F"; + when x"2" => + Mygroup.grp<=x"0000";-- rank + destRank:=0; + DestAdr:=X"044F"; + when x"3" => + Mygroup.grp<=x"0000";-- rank + destRank:=0; + DestAdr:=X"045F"; + when others => --cas des processus spawn + Mygroup.grp<=x"0000";-- rank 0 + DestAdr:=X"022F"; + destRank:=0; + end case; + RunState<=WinPost; + when WinPost => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;"& integer'image(dlen) & ";WPost1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + pMPI_Win_Post(ct,Libr,sram,MyGroup,0,MyWin); + + if ct=0 then + RunState<=WinStart; + -- synthesis translate_off + write (l,string'("Dlen;"& integer'image(dlen) & ";WPost2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + when WinStart => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";WStart1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + if spawn='0' then + RunState<=PutData; + else + RunState<=WinCompleted; + end if; + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when putdata => --construire le packet pour le Put + + --dlen:=251; --- + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + SrcAdr:=X"0105";--std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); + --DestAdr:=X"033F"; + pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + RunState<=GetData; + -- synthesis translate_off + report "Put of Process n°; " & image(MyRank) & "; ended at ; " & real'image(rt(now)); + write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + + when getdata => --positionnement du mot de longueur des données + --dlen:=251; --- + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + + SrcAdr:=X"0104"; + DestAdr:=X"1400"; + if unsigned(MyRank) = 0 then + pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + else + + pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + end if; + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + dcount:=ct; + + if ct=0 then + if unsigned(MyRank)/=0 then + RunState<=wincompleted; + else + nb_rma:=nb_rma+1; + if nb_rma=2 then + RunState<=wincompleted; + nb_rma:=0; + end if; + end if; + -- synthesis translate_off + assert ct/=0 report "GET_END " & integer'image(destrank) + severity Warning ; + write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + + writeline (f, l) ; + -- synthesis translate_on + end if; + + when WinCompleted => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_Complete(ct,Libr,sram,MyWin ); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + RunState<=WinWait; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + when WinWait => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_wait(ct,Libr,sram,MyWin ); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + if unsigned(Myrank)>1 then + RunState<=Finalize; + else + RunState<=MpiSpawn; + end if; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + + when MpiSpawn => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + --(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + + maxprocs:=2; + pMPI_Comm_Spawn(ct,Libr,sram,command,argv,maxprocs,info,root,comm,intercomm,array_of_errcodes); + adresse:=to_integer(unsigned(sram.O.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.O.addr_rd)); + + if ct=0 then + if unsigned(Myrank)=0 and spawn='0' then + MyGroup.Grp<=x"000C"; + spawn:='1'; + Runstate<=WinPost; + else + RunState<=Finalize; + end if; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + + end if; + when finalize => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + if ct=0 then + RunState<=start; + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now)))); + report l.all; + writeline (f, l) ; + file_close(f); + -- synthesis translate_on + end if; + + when st_timeout => + + sram.O.we<='0'; + sram.O.ena<='0'; + sram.O.enb<='0'; + + RunState<=start; + end case; + ct_state<=ct; --pour débogage + end if; + end if; + + end process pPutGet; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Hold_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Hold_FSM.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Hold_FSM.vhd (revision 138) @@ -0,0 +1,124 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM Roland Christian +-- +-- Create Date: 17:38:35 04/20/2013 +-- Design Name: +-- Module Name: Hold_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Hold_FSM is + Port ( Hold_Req : in STD_LOGIC; + ram_busy : in STD_LOGIC; + Clk : in STD_LOGIC; + Reset : in STD_LOGIC; + Ramsel : out STD_LOGIC; + Hold_Ack : out STD_LOGIC); +end Hold_FSM; + +architecture Behavioral of Hold_FSM is +type typ_Hld is (Ht_Lock,Core_Lock,Ht_free); +signal Holdstate,Hold_st :typ_hld; + signal Ram_sel :std_logic:='0'; + signal front_Rbusy,front_hReq:std_logic:='0'; +begin + +hold_sync:process (clk,reset) + begin + if rising_edge(clk) then + + + end if; + end process hold_sync; + Ramsel_state:process(clk)--,HoldState,Hold_Req,ram_Busy,Front_HReq,Front_RBusy) + + begin + + if rising_edge(clk) then + if reset='1' then + HolDState<=Ht_free; + else +-- HolDState<=Hold_St; +-- Hold_St<=HoldState; + case HoldState is + when Ht_free => + if Hold_Req='1' and ram_busy='0' then + HolDState <=Core_lock; + elsif Hold_Req='0' and ram_busy='1' then + HoldState <=HT_lock; + elsif Hold_Req='1' and ram_busy='1' then + HoldState <=HT_lock; + else + HoldState <=HT_free; + end if; + when Ht_lock => + if Hold_Req='0' and ram_busy='0' then + HoldState <=HT_free; + elsif Hold_Req='1' and Ram_busy='0' then + HoldState <=Core_lock; + else + HoldState <=HT_lock; + end if; + + When Core_lock => + If Hold_Req='0' and Ram_busy='0' then + HoldState <=HT_free; + elsif Hold_Req='0' and Ram_busy='1' then + HoldState <=HT_lock; + else + HoldState <=Core_lock; + end if; + end case ; + end if; + end if; + + end process; + + Ramsel_val:process(HoldState,Hold_Req,Ram_Busy) + + begin + case HoldState is + when Ht_free => + ram_sel<='0'; + Hold_Ack<='0'; + when Ht_Lock => + ram_sel<='0'; + Hold_Ack<='0'; + when Core_lock => + Ram_sel <='1'; + Hold_Ack<='1'; + end case; + if Hold_Req= not(front_HReq) then + front_HReq<= not front_HReq; +end if; + +if Ram_busy= not (front_RBusy) then + front_RBusy<= not front_RBusy; +end if; + end process ramsel_val; + Ramsel<=Ram_sel; +--======================================================================= +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/IP_Timer.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/IP_Timer.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/IP_Timer.vhd (revision 138) @@ -0,0 +1,73 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:11:13 01/16/2014 +-- Design Name: +-- Module Name: IP_Timer - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity IP_Timer is + +port (clk,reset,upDn,load,start:in std_logic; +loadval :in std_logic_vector(31 downto 0); +outval : out std_logic_vector(31 downto 0); +zero : out std_logic); + +end IP_Timer; + +architecture Behavioral of IP_Timer is +signal count: std_logic_vector(31 downto 0); +signal z:std_logic:='1'; +begin +process (clk) +begin + if clk='1' and clk'event then + if reset='1' then + count <= (others => '0'); + z<='1'; + elsif start='1' then + if load='1' then + count <= loadval; + else + if UpDn='1' then + count <= count + 1; + else + count <= count - 1; + end if; + end if; + if count=0 then + z<='1'; + else + z<='0'; + end if; + end if; + end if; +end process; +OutVal<=count; +zero<=z; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Arbiter.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Arbiter.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Arbiter.vhd (revision 138) @@ -0,0 +1,85 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: Kiegaing Emmanuel GEL EN5 +-- +-- Create Date: 18:18:09 03/19/2011 +-- Design Name: +-- Module Name: Arbiter - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- cellule d'arbitrage de l'ordonnanceur du crossbar +-- Dependencies: +-- +-- Revision: 1.0 +-- a été ajouté le signal fifo_full pour inclure la codition buffer pas plein dans +-- la cellules d'arbitrage +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Arbiter is + Port ( P: in STD_LOGIC;--vecteur de priorité + Fifo_full : in STD_LOGIC; + Request : in STD_LOGIC;-- demande de permission + West : in STD_LOGIC;-- verouillage ouest + North : in STD_LOGIC;--etc + Grant : out STD_LOGIC;-- validation de la transition + East : out STD_LOGIC; + South : out STD_LOGIC); +end Arbiter; + +architecture Behavioral of Arbiter is +-- modelisation comportementale 3 LUT après synthèse +-- ce module peut aussi facilement s'implémenter en flot de données +signal grant_signal : STD_LOGIC; +--signal not_fifo_full : STD_LOGIC; +signal Mask : STD_LOGIC:='0'; +signal RNW : std_logic:='0'; +begin +--Grant<=grant_signal; -- Grant n'a pas été déclarée InOut +Mask <= P AND (not Fifo_full); +RNW<= Request And North And West; +process(Mask, RNW, North, West)-- genere de la logique purement combinatoire +begin +if Mask ='0' then --cellule inactive +Grant <= '0';-- pas d'autorisation +South <= '1'; +East <= '1'; + else + Grant <= RNW; + South <= (North) And (Not (RNW)); + East <= (West) And (Not (RNW)); +end if; +end process; + +end Behavioral; +--modélidation flot de données elle semble plus efficace 3 LUT +--architecture Behavioral of Arbiter is +--signal x, x1, x2, x3, x4, x5: STD_LOGIC; +--begin +----equations logiques de la cellule +--x <= Mask And Request; +--x1 <= North; +--x2 <= West; +--x3 <= x And x1 And x2; +--x4 <= x1 And (Not x3); +--x5 <= x2 And (Not x3); +--South <= x4 Or (Not Mask); +--East <= x5 Or (Not Mask); +--Grant <= x3; +-- +--end Behavioral; + + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/CoreTypes.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/CoreTypes.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/CoreTypes.vhd (revision 138) @@ -0,0 +1,357 @@ + -- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and components + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.numeric_std.all; +package CoreTypes is +CONSTANT Word :POSITIVE:= 8; +CONSTANT ADRLEN:POSITIVE:=16; +CONSTANT LZFILL :std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0');--indique le nombre de zero à utiliser pour completer le bus de données lorsque la longueur restante du bus d'adresse est inférueure à la largeur du bus de données +CONSTANT IADR0 : NATURAL :=2; --Adresse basse de l'instruction +CONSTANT IADR1 : natural :=3; +CONSTANT CORE_BASE_ADR :natural range 0 to 65535:=4096; +CONSTANT WIN_BASE_ADR :natural range 0 to 65535:=CORE_BASE_ADR+4; +CONSTANT CORE_UPPER_ADR : natural range 0 to 255:=16; +CONSTANT CORE_GET_ADR:natural:=CORE_BASE_ADR+526; +CONSTANT CORE_PUT_ADR :natural:=CORE_BASE_ADR+516; +CONSTANT core_INIT_ADR : natural:=CORE_BASE_ADR+512; +CONSTANT CORE_WCREATE_ADR : natural := CORE_BASE_ADR+536; +CONSTANT CORE_WCOMPL_ADR : natural := CORE_BASE_ADR+546; +CONSTANT CORE_WPOST_ADR : natural := CORE_BASE_ADR+556; +CONSTANT CORE_WWAIT_ADR : natural := CORE_BASE_ADR+566; +CONSTANT CORE_WSYNC_ADR : natural := CORE_BASE_ADR+576; +CONSTANT CORE_SPAWN_ADR : natural := CORE_BASE_ADR+586; +CONSTANT CORE_Rank2port_BASE :NATURAL:=52; +CONSTANT CORE_RANK_ADR : NATURAL:=CORE_BASE_ADR+CORE_Rank2Port_Base; +CONSTANT WIN0_ADR :natural :=CORE_BASE_ADR+4; +CONSTANT WIN1_ADR :natural :=CORE_BASE_ADR+20; +CONSTANT WIN2_ADR :natural :=CORE_BASE_ADR+36; +CONSTANT WIN3_ADR :natural :=CORE_BASE_ADR+52; +CONSTANT GETPORTID : std_logic_vector(3 downto 0):="0001"; + + type Typ_PortIO is + array(natural range <>) of std_logic_vector( Word-1 downto 0); + + type memory is + array (natural range <>) of std_logic_vector(word-1 downto 0); + +type Core_i is + record + Instr_ack :std_logic;-- signal la prise en compte de l'instruction + Ready :std_logic;-- indique que la dernière fonction est terminée + InitOk :std_logic; -- l'initialisation est terminée + Hold_Req :std_logic;--Demande DMA + RamSel :std_logic;-- indique le statut de la RAM (0 ->dispo 1->occupé par Core_MPI) + IsMain : std_logic; -- indique si la librairie est principal + Rank : natural range 0 to 15; --donne le rang du processus courant + Spawned: std_logic; --indique que ce module a été activé par la bibliothèque +end record; +type Core_o is + record + Instr_en :std_logic; -- active une instruction MPI + Hold_Ack :std_logic;-- Autorisation DMA + MemBusy :std_logic;-- active le refus de DMA (1 -> ignoré la requête DMA de MPI HCL) + Instruction :std_logic_vector (word-1 downto 0); -- fonction Mpi à exécuter +end record; +type core_s is +record + Rank : natural range 0 to 15; --donne le rang du processus courant + IntState1 : natural range 0 to 255; --permet de stocker l'état des MAE interne dans les procédures + IntState2 : natural range 0 to 255; + WinId :natural range 0 to 255; --stocke le dernier Id utilisé par WinCreate + GPost : std_logic_vector(15 downto 0); --etat de la fenêtre active + GStart : std_logic_vector(15 downto 0); + tmem : memory(0 to 3); --petite mémoire tampon pour stocker les variables statiques des MVPs +end record; +type core_io is +record + I:core_i; --les entrées + O:core_o; --les sorties + S:core_s; --les signaux temporaires +end record; + +type Core_io_old is + record + Instr_en :std_logic; -- active une instruction MPI + Instr_ack :std_logic;-- signal la prise en compte de l'instruction + Ready :std_logic;-- indique que la dernière fonction est terminée + InitOk :std_logic; -- l'initialisation est terminée + Hold_Req :std_logic;--Demande DMA + Hold_Ack :std_logic;-- Autorisation DMA + MemBusy :std_logic;-- active le refus de DMA (1 -> ignoré la requête DMA) + RamSel :std_logic;-- indique le statut de la RAM (0 ->dispo 1->occupé par Core_MPI) + IntState1 : natural range 0 to 255; --permet de stocker l'état des MAE interne dans les procédures + IntState2 : natural range 0 to 255; + Instruction :std_logic_vector (word-1 downto 0); + WinId :natural range 0 to 255; --stocke le dernier Id utilisé par WinCreate + IsMain : std_logic; -- indique si la librairie est principal + Rank : natural range 0 to 15; --donne le rang du processus courant + Spawned: std_logic; --indique que ce module a été activé par la bibliothèque +end record; + +type typ_dpram_i is +record + data_out : STD_LOGIC_VECTOR (Word-1 downto 0); + +end record; +type typ_dpram_o is +record + clk_wr : STD_LOGIC; + clk_rd : STD_LOGIC; + we : STD_LOGIC; + ena : STD_LOGIC; + enb : STD_LOGIC; + addr_wr: STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + addr_rd : STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + data_in : STD_LOGIC_VECTOR (Word-1 downto 0); +end record; +type typ_dpram is +record +O : typ_dpram_o; +I : typ_dpram_I; +end record; +type Typ_MPIPort_in is +record + instruction : STD_LOGIC_VECTOR (Word -1 downto 0); + instruction_en : STD_LOGIC; + + + packet_ack : std_logic; + ram_data_out : STD_LOGIC_VECTOR (Word-1 downto 0); + + hold_ack : STD_Logic; --autorisation par l'application + clk : STD_LOGIC; + reset : STD_LOGIC; + +end record; +type Typ_MPIPort_out is +record + + + ram_we : STD_LOGIC; + ram_en : STD_LOGIC; + ram_data_in : STD_LOGIC_VECTOR (WORD-1 downto 0); + ram_address_rd : STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_address_wr : STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + packet_received : STD_LOGIC; + barrier_completed : STD_LOGIC; + instruction_fifo_full : STD_LOGIC; + PushOut : STD_LOGIC_VECTOR (WORD-1 downto 0); + + hold_req : STD_Logic; --requete vers application +end record; + +Type Ar_MPIPort_In is array (positive range <>) of Typ_MPIPort_in; +Type Ar_MPIPort_out is array (positive range <>) of Typ_MPIPort_out; + +-- Declare constants + +-- constant : time := ns; +-- constant : integer := ; +-- +-- Declare functions and procedure +Component SWITCH_GEN is + generic(number_of_ports : positive := 8); + port( + -- ports d'entree + Port_in : in typ_portIO(1 to number_of_ports) ; +-- + + -- port de sortie + Port_out : out typ_portIO(1 to number_of_ports); +-- + -- signaux de controle + cmd_in_en : in std_logic_vector(number_of_ports downto 1); + data_in_en : in std_logic_vector(number_of_ports downto 1); + data_out_en : in std_logic_vector(number_of_ports downto 1); + fifo_in_full : out std_logic_vector(number_of_ports downto 1); + fifo_in_empty : out std_logic_vector(number_of_ports downto 1); + data_available : out std_logic_vector(number_of_ports downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC); +end component SWITCH_GEN; +-- déclaration des fonctions utilisées + + FUNCTION all_ones(s1:std_logic_vector) return std_logic; + --This function returns if the input vector has all ones and no zeros + FUNCTION all_zeros(s1:std_logic_vector) return std_logic; + --This function returns if the input vector has all zeros and no ones + FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector; + --This function increments an std_logic_vector type by '1', without + --using any arithmatic + + FUNCTION dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector; + --This function decrements an std_logic_vector type by '1', without + --using any arithmatic + FUNCTION Rol_Vec(s1:std_logic_vector) return std_logic_vector; + --renvoie un std_logic_vector de taille ADRLEN + Function Stdlv (s1 : natural) return std_logic_vector; + --renvoie un std_logic_vector de taille width + Function Stdlv (s1 : natural;width:positive ) return std_logic_vector; + function image(L: bit_vector) return String; + function image(L: bit) return String; + function image(L: std_logic_vector) return String; + function image(L: std_logic) return String; +-- function HexImage(L: unsigned) return String; +-- function HexImage(L: signed) return String; +-- function HexImage(L: std_ulogic_vector) return String; +-- function HexImage(L: std_logic_vector) return String; +-- function HexImage(L: bit_vector) return String; +end CoreTypes; + + +Package body CoreTypes is + + +FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is + --this function increments a std_logic_vector type by '1' + VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE tb : std_logic_vector(s1'high downto s1'low); + BEGIN + tb(s1'low) := en; + V := s1; + for i in (V'low + 1) to V'high loop + tb(i) := V(i - 1) and tb(i -1); + end loop; + for i in V'low to V'high loop + if(tb(i) = '1') then + V(i) := not(V(i)); + end if; + end loop; + return V; + end incr_vec; -- end function + +FUNCTION dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is + --this function decrements a std_logic_vector type by '1' + VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE tb : std_logic_vector(s1'high downto s1'low); + BEGIN + tb(s1'low) := not(en); + V := s1; + for i in (V'low + 1) to V'high loop + tb(i) := V(i - 1) or tb(i -1); + end loop; + for i in V'low to V'high loop + if(tb(i) = '0') then + V(i) := not(V(i)); + end if; + end loop; + return V; + end dcr_vec; -- end function +FUNCTION all_ones(s1:std_logic_vector) return std_logic is + --this function tells if all bits of a vector are '1' + --return value Z is '1', then vector has all 1 bits + --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE Z : std_logic; + BEGIN + Z := s1(s1'low); + FOR i IN (s1'low+1) to s1'high LOOP + Z := Z AND s1(i); + END LOOP; + RETURN Z; + END all_ones; -- end function +FUNCTION all_zeros(s1:std_logic_vector) return std_logic is + --this function tells if all bits of a vector are '0' + --return value Z if '1', then vector has all 0 bits + --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE Z : std_logic; + BEGIN + Z := '0'; + FOR i IN (s1'low) to s1'high LOOP + Z := Z OR s1(i); + END LOOP; + RETURN not(Z); + END all_zeros; -- end function + +FUNCTION Rol_Vec(s1:std_logic_vector) return std_logic_vector is +--cette fonction fait roter un STD_logic d'un pas vers la gauche +VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE lb : std_logic :=s1(s1'left); + BEGIN + + for i in V'left downto (V'right+1) loop + V(i) := s1(i - 1) ; + end loop; + V(V'right):=lb; + return V; + end Rol_vec; + Function Stdlv (s1 : natural ) return std_logic_vector is +VARIABLE V : std_logic_vector(ADRLEN-1 downto 0); + begin + V:=std_logic_vector(to_unsigned(s1,ADRLEN)); + return V; + end stdlv; + Function Stdlv (s1 : natural;width:positive ) return std_logic_vector is +VARIABLE V : std_logic_vector(width-1 downto 0); + begin + V:=std_logic_vector(to_unsigned(s1,width)); + return V; + end stdlv; + + -- Start of heximage functions +--function HexImage(L: bit_vector) return String is +--begin +--return(HexImage(imge(L))); +--end function HexImage; +-- +--function HexImage(L: std_ulogic_vector) return String is +--begin +--return(HexImage(image(to_x01(L)))); +--end function HexImage; + +--function HexImage(L: std_logic_vector) return String is +--begin +--return(HexImage(imge(to_x01(L)))); +--end function HexImage; +-- +--function HexImage(L: signed) return String is +--begin +--return(HexImage(imge(L))); +--end function HexImage; +-- +--function HexImage(L: unsigned) return String is +--begin +--return(HexImage(image(L))); +--end function HexImage; +-- End of heximage functions +-- Start of an example image function +function image(L: bit) return String is +variable bit_image: String(1 to 1) := bit'image(L); +begin +return(bit_image(1 to 1)); +end function image; + + +function image(L: std_logic) return String is +variable bit_image: String(1 to 3) := std_logic'image(L); +begin +return(bit_image(1 to 1)); +end function image; + +function image(L: bit_vector) return String is +variable Lx: bit_vector(1 to L'length); +variable RetVal: String(1 to L'length); +begin +Lx := L; +for i in Lx'range loop +RetVal(i to i) := image(Lx(i)); +end loop; +return(RetVal); +end function image; + + +function image(L: std_logic_vector) return String is +variable Lx: std_logic_vector(1 to L'length); +variable RetVal: String(1 to L'length); +begin +Lx := L; +for i in Lx'range loop +RetVal(i to i) := image(Lx(i)); +end loop; +return(RetVal); +end function image; +end CoreTypes; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Crossbar.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Crossbar.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Crossbar.vhd (revision 138) @@ -0,0 +1,4174 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL / GAMOM NGOUNOU +-- +-- Create Date: 11:48:18 06/19/2011 +-- Design Name: +-- Module Name: Crossbar - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: module implémentant les crossbar +-- ce module instacie les crossbar 1 bit du fichier crossbit.vhd +-- +-- CROSSBAR GENERIQUE +-- Revision: 1.0 +-- a été retiré les signaux inutilisées comme fp, port_source, etc... +-- Revision 0.01 - File Created +-- Revision 0.02 Ajout des signaux clk et reset +-- Additional Comments: pour la gestion du pipeline +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library NocLib ; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Crossbar is + generic + ( + number_of_crossbar_ports: positive := 8 + ); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; --pour gérer le pipeline + Port1_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port2_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port3_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port4_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port5_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port6_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port7_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port8_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port9_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port10_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port11_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port12_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port13_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port14_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port15_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Port16_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + + Port1_pulse_in : in std_logic; + Port2_pulse_in : in std_logic; + Port3_pulse_in : in std_logic; + Port4_pulse_in : in std_logic; + Port5_pulse_in : in std_logic; + Port6_pulse_in : in std_logic; + Port7_pulse_in : in std_logic; + Port8_pulse_in : in std_logic; + Port9_pulse_in : in std_logic; + Port10_pulse_in : in std_logic; + Port11_pulse_in : in std_logic; + Port12_pulse_in : in std_logic; + Port13_pulse_in : in std_logic; + Port14_pulse_in : in std_logic; + Port15_pulse_in : in std_logic; + Port16_pulse_in : in std_logic; + + Port1_pulse_out : out std_logic; + Port2_pulse_out : out std_logic; + Port3_pulse_out : out std_logic; + Port4_pulse_out : out std_logic; + Port5_pulse_out : out std_logic; + Port6_pulse_out : out std_logic; + Port7_pulse_out : out std_logic; + Port8_pulse_out : out std_logic; + Port9_pulse_out : out std_logic; + Port10_pulse_out : out std_logic; + Port11_pulse_out : out std_logic; + Port12_pulse_out : out std_logic; + Port13_pulse_out : out std_logic; + Port14_pulse_out : out std_logic; + Port15_pulse_out : out std_logic; + Port16_pulse_out : out std_logic; + + Port1_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port2_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port3_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port4_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port5_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port6_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port7_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port8_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port9_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port10_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port11_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port12_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port13_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port14_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port15_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Port16_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + + Ctrl : in STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1) + ); +end Crossbar; + +architecture Behavioral of Crossbar is + +-- declaration du crossbar un bit instanciés pour former les crossbars +COMPONENT Crossbit + generic + ( + number_of_ports : positive := 4 + ); + Port ( clk,reset : in std_logic; + Control : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1); + Data_In : in STD_LOGIC_VECTOR (number_of_ports downto 1); + Data_out : out STD_LOGIC_VECTOR (number_of_ports downto 1)); + END COMPONENT; +signal ctrl_buf: STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1):=(others=>'0'); +--signal ctrl_chg:std_logic:='0'; +begin +-- La matrice interconnectee +-- le circuit genere depend du parametre generique nombre de ports +--ctrl_chg<=all_zeros(ctrl_buf xor ctrl); --sur chaque changement du mot de contrôle, mettre à jour ce registre +--ctrl_proc:process(ctrl) +-- begin + ctrl_buf<=ctrl; +-- end process; +--======================crossbar 2 ports======================= + +crossbar2x2 : if number_of_crossbar_ports = 2 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 2) + PORT MAP( + reset => reset, + clk =>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 2) + PORT MAP( + reset => reset, + clk =>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 2) + PORT MAP( + reset => reset, + clk =>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 2) + PORT MAP( + reset => reset, + clk =>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 2) + PORT MAP( + + reset => reset, + clk =>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 2) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 2) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 2) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7) + + ); +-- crossbit du pulse_out 2 ports + + Pulse_out_Crossbit2: Crossbit + GENERIC MAP(number_of_ports => 2) + PORT MAP( + reset => reset, + clk =>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out + + ); +end generate crossbar2x2; + + +--======================crossbar 3 ports======================= + +crossbar3x3 : if number_of_crossbar_ports = 3 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 3) + PORT MAP( + + reset => reset, + clk =>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_In(3) => Port3_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0), + Data_out(3)=> Port3_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 3) + PORT MAP( + reset => reset, + clk =>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_In(3) => Port3_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1), + Data_out(3)=> Port3_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 3) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_In(3) => Port3_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2), + Data_out(3)=> Port3_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 3) + PORT MAP( + reset => reset, + clk =>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_In(3) => Port3_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3), + Data_out(3)=> Port3_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 3) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_In(3) => Port3_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4), + Data_out(3)=> Port3_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 3) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_In(3) => Port3_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5), + Data_out(3)=> Port3_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 3) + PORT MAP( + + reset => reset, + clk =>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_In(3) => Port3_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6), + Data_out(3)=> Port3_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 3) + PORT MAP( + reset => reset, + clk =>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_In(3) => Port3_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7), + Data_out(3)=> Port3_out(7) + + ); +-- crossbit du pulse_out 3 ports + + Pulse_out_Crossbit3: Crossbit + GENERIC MAP(number_of_ports => 3) + PORT MAP( + reset => reset, + clk =>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_In(3) => Port3_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out, + Data_out(3) => Port3_pulse_out + + ); +end generate crossbar3x3; + + +--======================crossbar 4 ports======================= + +crossbar4x4 : if number_of_crossbar_ports = 4 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 4) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_In(3) => Port3_in(0), + Data_In(4) => Port4_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0), + Data_out(3)=> Port3_out(0), + Data_out(4)=> Port4_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 4) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_In(3) => Port3_in(1), + Data_In(4) => Port4_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1), + Data_out(3)=> Port3_out(1), + Data_out(4)=> Port4_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 4) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_In(3) => Port3_in(2), + Data_In(4) => Port4_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2), + Data_out(3)=> Port3_out(2), + Data_out(4)=> Port4_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 4) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_In(3) => Port3_in(3), + Data_In(4) => Port4_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3), + Data_out(3)=> Port3_out(3), + Data_out(4)=> Port4_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 4) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_In(3) => Port3_in(4), + Data_In(4) => Port4_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4), + Data_out(3)=> Port3_out(4), + Data_out(4)=> Port4_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 4) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_In(3) => Port3_in(5), + Data_In(4) => Port4_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5), + Data_out(3)=> Port3_out(5), + Data_out(4)=> Port4_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 4) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_In(3) => Port3_in(6), + Data_In(4) => Port4_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6), + Data_out(3)=> Port3_out(6), + Data_out(4)=> Port4_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 4) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_In(3) => Port3_in(7), + Data_In(4) => Port4_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7), + Data_out(3)=> Port3_out(7), + Data_out(4)=> Port4_out(7) + + ); +-- crossbit du pulse_out 4 ports + + Pulse_out_Crossbit4: Crossbit + GENERIC MAP(number_of_ports => 4) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_In(3) => Port3_pulse_in, + Data_In(4) => Port4_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out, + Data_out(3) => Port3_pulse_out, + Data_out(4) => Port4_pulse_out + + ); +end generate crossbar4x4; + + +--======================crossbar 5 ports======================= + +crossbar5x5 : if number_of_crossbar_ports = 5 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 5) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_In(3) => Port3_in(0), + Data_In(4) => Port4_in(0), + Data_In(5) => Port5_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0), + Data_out(3)=> Port3_out(0), + Data_out(4)=> Port4_out(0), + Data_out(5)=> Port5_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 5) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_In(3) => Port3_in(1), + Data_In(4) => Port4_in(1), + Data_In(5) => Port5_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1), + Data_out(3)=> Port3_out(1), + Data_out(4)=> Port4_out(1), + Data_out(5)=> Port5_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 5) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_In(3) => Port3_in(2), + Data_In(4) => Port4_in(2), + Data_In(5) => Port5_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2), + Data_out(3)=> Port3_out(2), + Data_out(4)=> Port4_out(2), + Data_out(5)=> Port5_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 5) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_In(3) => Port3_in(3), + Data_In(4) => Port4_in(3), + Data_In(5) => Port5_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3), + Data_out(3)=> Port3_out(3), + Data_out(4)=> Port4_out(3), + Data_out(5)=> Port5_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 5) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_In(3) => Port3_in(4), + Data_In(4) => Port4_in(4), + Data_In(5) => Port5_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4), + Data_out(3)=> Port3_out(4), + Data_out(4)=> Port4_out(4), + Data_out(5)=> Port5_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 5) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_In(3) => Port3_in(5), + Data_In(4) => Port4_in(5), + Data_In(5) => Port5_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5), + Data_out(3)=> Port3_out(5), + Data_out(4)=> Port4_out(5), + Data_out(5)=> Port5_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 5) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_In(3) => Port3_in(6), + Data_In(4) => Port4_in(6), + Data_In(5) => Port5_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6), + Data_out(3)=> Port3_out(6), + Data_out(4)=> Port4_out(6), + Data_out(5)=> Port5_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 5) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_In(3) => Port3_in(7), + Data_In(4) => Port4_in(7), + Data_In(5) => Port5_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7), + Data_out(3)=> Port3_out(7), + Data_out(4)=> Port4_out(7), + Data_out(5)=> Port5_out(7) + + ); +-- crossbit du pulse_out 5 ports + + Pulse_out_Crossbit5: Crossbit + GENERIC MAP(number_of_ports => 5) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_In(3) => Port3_pulse_in, + Data_In(4) => Port4_pulse_in, + Data_In(5) => Port5_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out, + Data_out(3) => Port3_pulse_out, + Data_out(4) => Port4_pulse_out, + Data_out(5) => Port5_pulse_out + + ); +end generate crossbar5x5; + + +--======================crossbar 6 ports======================= + +crossbar6x6 : if number_of_crossbar_ports = 6 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 6) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_In(3) => Port3_in(0), + Data_In(4) => Port4_in(0), + Data_In(5) => Port5_in(0), + Data_In(6) => Port6_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0), + Data_out(3)=> Port3_out(0), + Data_out(4)=> Port4_out(0), + Data_out(5)=> Port5_out(0), + Data_out(6)=> Port6_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 6) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_In(3) => Port3_in(1), + Data_In(4) => Port4_in(1), + Data_In(5) => Port5_in(1), + Data_In(6) => Port6_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1), + Data_out(3)=> Port3_out(1), + Data_out(4)=> Port4_out(1), + Data_out(5)=> Port5_out(1), + Data_out(6)=> Port6_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 6) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_In(3) => Port3_in(2), + Data_In(4) => Port4_in(2), + Data_In(5) => Port5_in(2), + Data_In(6) => Port6_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2), + Data_out(3)=> Port3_out(2), + Data_out(4)=> Port4_out(2), + Data_out(5)=> Port5_out(2), + Data_out(6)=> Port6_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 6) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_In(3) => Port3_in(3), + Data_In(4) => Port4_in(3), + Data_In(5) => Port5_in(3), + Data_In(6) => Port6_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3), + Data_out(3)=> Port3_out(3), + Data_out(4)=> Port4_out(3), + Data_out(5)=> Port5_out(3), + Data_out(6)=> Port6_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 6) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_In(3) => Port3_in(4), + Data_In(4) => Port4_in(4), + Data_In(5) => Port5_in(4), + Data_In(6) => Port6_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4), + Data_out(3)=> Port3_out(4), + Data_out(4)=> Port4_out(4), + Data_out(5)=> Port5_out(4), + Data_out(6)=> Port6_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 6) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_In(3) => Port3_in(5), + Data_In(4) => Port4_in(5), + Data_In(5) => Port5_in(5), + Data_In(6) => Port6_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5), + Data_out(3)=> Port3_out(5), + Data_out(4)=> Port4_out(5), + Data_out(5)=> Port5_out(5), + Data_out(6)=> Port6_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 6) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_In(3) => Port3_in(6), + Data_In(4) => Port4_in(6), + Data_In(5) => Port5_in(6), + Data_In(6) => Port6_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6), + Data_out(3)=> Port3_out(6), + Data_out(4)=> Port4_out(6), + Data_out(5)=> Port5_out(6), + Data_out(6)=> Port6_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 6) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_In(3) => Port3_in(7), + Data_In(4) => Port4_in(7), + Data_In(5) => Port5_in(7), + Data_In(6) => Port6_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7), + Data_out(3)=> Port3_out(7), + Data_out(4)=> Port4_out(7), + Data_out(5)=> Port5_out(7), + Data_out(6)=> Port6_out(7) + + ); +-- crossbit du pulse_out 6 ports + + Pulse_out_Crossbit6: Crossbit + GENERIC MAP(number_of_ports => 6) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_In(3) => Port3_pulse_in, + Data_In(4) => Port4_pulse_in, + Data_In(5) => Port5_pulse_in, + Data_In(6) => Port6_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out, + Data_out(3) => Port3_pulse_out, + Data_out(4) => Port4_pulse_out, + Data_out(5) => Port5_pulse_out, + Data_out(6) => Port6_pulse_out + + ); +end generate crossbar6x6; + + +--======================crossbar 7 ports======================= + +crossbar7x7 : if number_of_crossbar_ports = 7 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 7) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_In(3) => Port3_in(0), + Data_In(4) => Port4_in(0), + Data_In(5) => Port5_in(0), + Data_In(6) => Port6_in(0), + Data_In(7) => Port7_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0), + Data_out(3)=> Port3_out(0), + Data_out(4)=> Port4_out(0), + Data_out(5)=> Port5_out(0), + Data_out(6)=> Port6_out(0), + Data_out(7)=> Port7_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 7) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_In(3) => Port3_in(1), + Data_In(4) => Port4_in(1), + Data_In(5) => Port5_in(1), + Data_In(6) => Port6_in(1), + Data_In(7) => Port7_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1), + Data_out(3)=> Port3_out(1), + Data_out(4)=> Port4_out(1), + Data_out(5)=> Port5_out(1), + Data_out(6)=> Port6_out(1), + Data_out(7)=> Port7_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 7) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_In(3) => Port3_in(2), + Data_In(4) => Port4_in(2), + Data_In(5) => Port5_in(2), + Data_In(6) => Port6_in(2), + Data_In(7) => Port7_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2), + Data_out(3)=> Port3_out(2), + Data_out(4)=> Port4_out(2), + Data_out(5)=> Port5_out(2), + Data_out(6)=> Port6_out(2), + Data_out(7)=> Port7_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 7) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_In(3) => Port3_in(3), + Data_In(4) => Port4_in(3), + Data_In(5) => Port5_in(3), + Data_In(6) => Port6_in(3), + Data_In(7) => Port7_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3), + Data_out(3)=> Port3_out(3), + Data_out(4)=> Port4_out(3), + Data_out(5)=> Port5_out(3), + Data_out(6)=> Port6_out(3), + Data_out(7)=> Port7_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 7) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_In(3) => Port3_in(4), + Data_In(4) => Port4_in(4), + Data_In(5) => Port5_in(4), + Data_In(6) => Port6_in(4), + Data_In(7) => Port7_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4), + Data_out(3)=> Port3_out(4), + Data_out(4)=> Port4_out(4), + Data_out(5)=> Port5_out(4), + Data_out(6)=> Port6_out(4), + Data_out(7)=> Port7_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 7) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_In(3) => Port3_in(5), + Data_In(4) => Port4_in(5), + Data_In(5) => Port5_in(5), + Data_In(6) => Port6_in(5), + Data_In(7) => Port7_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5), + Data_out(3)=> Port3_out(5), + Data_out(4)=> Port4_out(5), + Data_out(5)=> Port5_out(5), + Data_out(6)=> Port6_out(5), + Data_out(7)=> Port7_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 7) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_In(3) => Port3_in(6), + Data_In(4) => Port4_in(6), + Data_In(5) => Port5_in(6), + Data_In(6) => Port6_in(6), + Data_In(7) => Port7_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6), + Data_out(3)=> Port3_out(6), + Data_out(4)=> Port4_out(6), + Data_out(5)=> Port5_out(6), + Data_out(6)=> Port6_out(6), + Data_out(7)=> Port7_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 7) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_In(3) => Port3_in(7), + Data_In(4) => Port4_in(7), + Data_In(5) => Port5_in(7), + Data_In(6) => Port6_in(7), + Data_In(7) => Port7_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7), + Data_out(3)=> Port3_out(7), + Data_out(4)=> Port4_out(7), + Data_out(5)=> Port5_out(7), + Data_out(6)=> Port6_out(7), + Data_out(7)=> Port7_out(7) + + ); +-- crossbit du pulse_out 7 ports + + Pulse_out_Crossbit7: Crossbit + GENERIC MAP(number_of_ports => 7) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_In(3) => Port3_pulse_in, + Data_In(4) => Port4_pulse_in, + Data_In(5) => Port5_pulse_in, + Data_In(6) => Port6_pulse_in, + Data_In(7) => Port7_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out, + Data_out(3) => Port3_pulse_out, + Data_out(4) => Port4_pulse_out, + Data_out(5) => Port5_pulse_out, + Data_out(6) => Port6_pulse_out, + Data_out(7) => Port7_pulse_out + + ); +end generate crossbar7x7; + + +--======================crossbar 8 ports======================= + +crossbar8x8 : if number_of_crossbar_ports = 8 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 8) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_In(3) => Port3_in(0), + Data_In(4) => Port4_in(0), + Data_In(5) => Port5_in(0), + Data_In(6) => Port6_in(0), + Data_In(7) => Port7_in(0), + Data_In(8) => Port8_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0), + Data_out(3)=> Port3_out(0), + Data_out(4)=> Port4_out(0), + Data_out(5)=> Port5_out(0), + Data_out(6)=> Port6_out(0), + Data_out(7)=> Port7_out(0), + Data_out(8)=> Port8_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 8) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_In(3) => Port3_in(1), + Data_In(4) => Port4_in(1), + Data_In(5) => Port5_in(1), + Data_In(6) => Port6_in(1), + Data_In(7) => Port7_in(1), + Data_In(8) => Port8_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1), + Data_out(3)=> Port3_out(1), + Data_out(4)=> Port4_out(1), + Data_out(5)=> Port5_out(1), + Data_out(6)=> Port6_out(1), + Data_out(7)=> Port7_out(1), + Data_out(8)=> Port8_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 8) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_In(3) => Port3_in(2), + Data_In(4) => Port4_in(2), + Data_In(5) => Port5_in(2), + Data_In(6) => Port6_in(2), + Data_In(7) => Port7_in(2), + Data_In(8) => Port8_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2), + Data_out(3)=> Port3_out(2), + Data_out(4)=> Port4_out(2), + Data_out(5)=> Port5_out(2), + Data_out(6)=> Port6_out(2), + Data_out(7)=> Port7_out(2), + Data_out(8)=> Port8_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 8) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_In(3) => Port3_in(3), + Data_In(4) => Port4_in(3), + Data_In(5) => Port5_in(3), + Data_In(6) => Port6_in(3), + Data_In(7) => Port7_in(3), + Data_In(8) => Port8_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3), + Data_out(3)=> Port3_out(3), + Data_out(4)=> Port4_out(3), + Data_out(5)=> Port5_out(3), + Data_out(6)=> Port6_out(3), + Data_out(7)=> Port7_out(3), + Data_out(8)=> Port8_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 8) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_In(3) => Port3_in(4), + Data_In(4) => Port4_in(4), + Data_In(5) => Port5_in(4), + Data_In(6) => Port6_in(4), + Data_In(7) => Port7_in(4), + Data_In(8) => Port8_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4), + Data_out(3)=> Port3_out(4), + Data_out(4)=> Port4_out(4), + Data_out(5)=> Port5_out(4), + Data_out(6)=> Port6_out(4), + Data_out(7)=> Port7_out(4), + Data_out(8)=> Port8_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 8) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_In(3) => Port3_in(5), + Data_In(4) => Port4_in(5), + Data_In(5) => Port5_in(5), + Data_In(6) => Port6_in(5), + Data_In(7) => Port7_in(5), + Data_In(8) => Port8_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5), + Data_out(3)=> Port3_out(5), + Data_out(4)=> Port4_out(5), + Data_out(5)=> Port5_out(5), + Data_out(6)=> Port6_out(5), + Data_out(7)=> Port7_out(5), + Data_out(8)=> Port8_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 8) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_In(3) => Port3_in(6), + Data_In(4) => Port4_in(6), + Data_In(5) => Port5_in(6), + Data_In(6) => Port6_in(6), + Data_In(7) => Port7_in(6), + Data_In(8) => Port8_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6), + Data_out(3)=> Port3_out(6), + Data_out(4)=> Port4_out(6), + Data_out(5)=> Port5_out(6), + Data_out(6)=> Port6_out(6), + Data_out(7)=> Port7_out(6), + Data_out(8)=> Port8_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 8) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_In(3) => Port3_in(7), + Data_In(4) => Port4_in(7), + Data_In(5) => Port5_in(7), + Data_In(6) => Port6_in(7), + Data_In(7) => Port7_in(7), + Data_In(8) => Port8_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7), + Data_out(3)=> Port3_out(7), + Data_out(4)=> Port4_out(7), + Data_out(5)=> Port5_out(7), + Data_out(6)=> Port6_out(7), + Data_out(7)=> Port7_out(7), + Data_out(8)=> Port8_out(7) + + ); +-- crossbit du pulse_out 8 ports + + Pulse_out_Crossbit8: Crossbit + GENERIC MAP(number_of_ports => 8) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_In(3) => Port3_pulse_in, + Data_In(4) => Port4_pulse_in, + Data_In(5) => Port5_pulse_in, + Data_In(6) => Port6_pulse_in, + Data_In(7) => Port7_pulse_in, + Data_In(8) => Port8_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out, + Data_out(3) => Port3_pulse_out, + Data_out(4) => Port4_pulse_out, + Data_out(5) => Port5_pulse_out, + Data_out(6) => Port6_pulse_out, + Data_out(7) => Port7_pulse_out, + Data_out(8) => Port8_pulse_out + + ); +end generate crossbar8x8; + + +--======================crossbar 9 ports======================= + +crossbar9x9 : if number_of_crossbar_ports = 9 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 9) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_In(3) => Port3_in(0), + Data_In(4) => Port4_in(0), + Data_In(5) => Port5_in(0), + Data_In(6) => Port6_in(0), + Data_In(7) => Port7_in(0), + Data_In(8) => Port8_in(0), + Data_In(9) => Port9_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0), + Data_out(3)=> Port3_out(0), + Data_out(4)=> Port4_out(0), + Data_out(5)=> Port5_out(0), + Data_out(6)=> Port6_out(0), + Data_out(7)=> Port7_out(0), + Data_out(8)=> Port8_out(0), + Data_out(9)=> Port9_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 9) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_In(3) => Port3_in(1), + Data_In(4) => Port4_in(1), + Data_In(5) => Port5_in(1), + Data_In(6) => Port6_in(1), + Data_In(7) => Port7_in(1), + Data_In(8) => Port8_in(1), + Data_In(9) => Port9_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1), + Data_out(3)=> Port3_out(1), + Data_out(4)=> Port4_out(1), + Data_out(5)=> Port5_out(1), + Data_out(6)=> Port6_out(1), + Data_out(7)=> Port7_out(1), + Data_out(8)=> Port8_out(1), + Data_out(9)=> Port9_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 9) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_In(3) => Port3_in(2), + Data_In(4) => Port4_in(2), + Data_In(5) => Port5_in(2), + Data_In(6) => Port6_in(2), + Data_In(7) => Port7_in(2), + Data_In(8) => Port8_in(2), + Data_In(9) => Port9_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2), + Data_out(3)=> Port3_out(2), + Data_out(4)=> Port4_out(2), + Data_out(5)=> Port5_out(2), + Data_out(6)=> Port6_out(2), + Data_out(7)=> Port7_out(2), + Data_out(8)=> Port8_out(2), + Data_out(9)=> Port9_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 9) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_In(3) => Port3_in(3), + Data_In(4) => Port4_in(3), + Data_In(5) => Port5_in(3), + Data_In(6) => Port6_in(3), + Data_In(7) => Port7_in(3), + Data_In(8) => Port8_in(3), + Data_In(9) => Port9_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3), + Data_out(3)=> Port3_out(3), + Data_out(4)=> Port4_out(3), + Data_out(5)=> Port5_out(3), + Data_out(6)=> Port6_out(3), + Data_out(7)=> Port7_out(3), + Data_out(8)=> Port8_out(3), + Data_out(9)=> Port9_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 9) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_In(3) => Port3_in(4), + Data_In(4) => Port4_in(4), + Data_In(5) => Port5_in(4), + Data_In(6) => Port6_in(4), + Data_In(7) => Port7_in(4), + Data_In(8) => Port8_in(4), + Data_In(9) => Port9_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4), + Data_out(3)=> Port3_out(4), + Data_out(4)=> Port4_out(4), + Data_out(5)=> Port5_out(4), + Data_out(6)=> Port6_out(4), + Data_out(7)=> Port7_out(4), + Data_out(8)=> Port8_out(4), + Data_out(9)=> Port9_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 9) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_In(3) => Port3_in(5), + Data_In(4) => Port4_in(5), + Data_In(5) => Port5_in(5), + Data_In(6) => Port6_in(5), + Data_In(7) => Port7_in(5), + Data_In(8) => Port8_in(5), + Data_In(9) => Port9_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5), + Data_out(3)=> Port3_out(5), + Data_out(4)=> Port4_out(5), + Data_out(5)=> Port5_out(5), + Data_out(6)=> Port6_out(5), + Data_out(7)=> Port7_out(5), + Data_out(8)=> Port8_out(5), + Data_out(9)=> Port9_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 9) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_In(3) => Port3_in(6), + Data_In(4) => Port4_in(6), + Data_In(5) => Port5_in(6), + Data_In(6) => Port6_in(6), + Data_In(7) => Port7_in(6), + Data_In(8) => Port8_in(6), + Data_In(9) => Port9_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6), + Data_out(3)=> Port3_out(6), + Data_out(4)=> Port4_out(6), + Data_out(5)=> Port5_out(6), + Data_out(6)=> Port6_out(6), + Data_out(7)=> Port7_out(6), + Data_out(8)=> Port8_out(6), + Data_out(9)=> Port9_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 9) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_In(3) => Port3_in(7), + Data_In(4) => Port4_in(7), + Data_In(5) => Port5_in(7), + Data_In(6) => Port6_in(7), + Data_In(7) => Port7_in(7), + Data_In(8) => Port8_in(7), + Data_In(9) => Port9_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7), + Data_out(3)=> Port3_out(7), + Data_out(4)=> Port4_out(7), + Data_out(5)=> Port5_out(7), + Data_out(6)=> Port6_out(7), + Data_out(7)=> Port7_out(7), + Data_out(8)=> Port8_out(7), + Data_out(9)=> Port9_out(7) + + ); +-- crossbit du pulse_out 9 ports + + Pulse_out_Crossbit9: Crossbit + GENERIC MAP(number_of_ports => 9) + PORT MAP( + clk =>clk, + reset =>reset, + + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_In(3) => Port3_pulse_in, + Data_In(4) => Port4_pulse_in, + Data_In(5) => Port5_pulse_in, + Data_In(6) => Port6_pulse_in, + Data_In(7) => Port7_pulse_in, + Data_In(8) => Port8_pulse_in, + Data_In(9) => Port9_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out, + Data_out(3) => Port3_pulse_out, + Data_out(4) => Port4_pulse_out, + Data_out(5) => Port5_pulse_out, + Data_out(6) => Port6_pulse_out, + Data_out(7) => Port7_pulse_out, + Data_out(8) => Port8_pulse_out, + Data_out(9) => Port9_pulse_out + + ); +end generate crossbar9x9; + + +--======================crossbar 10 ports======================= + +crossbar10x10 : if number_of_crossbar_ports = 10 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 10) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_In(3) => Port3_in(0), + Data_In(4) => Port4_in(0), + Data_In(5) => Port5_in(0), + Data_In(6) => Port6_in(0), + Data_In(7) => Port7_in(0), + Data_In(8) => Port8_in(0), + Data_In(9) => Port9_in(0), + Data_In(10) => Port10_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0), + Data_out(3)=> Port3_out(0), + Data_out(4)=> Port4_out(0), + Data_out(5)=> Port5_out(0), + Data_out(6)=> Port6_out(0), + Data_out(7)=> Port7_out(0), + Data_out(8)=> Port8_out(0), + Data_out(9)=> Port9_out(0), + Data_out(10)=> Port10_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 10) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_In(3) => Port3_in(1), + Data_In(4) => Port4_in(1), + Data_In(5) => Port5_in(1), + Data_In(6) => Port6_in(1), + Data_In(7) => Port7_in(1), + Data_In(8) => Port8_in(1), + Data_In(9) => Port9_in(1), + Data_In(10) => Port10_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1), + Data_out(3)=> Port3_out(1), + Data_out(4)=> Port4_out(1), + Data_out(5)=> Port5_out(1), + Data_out(6)=> Port6_out(1), + Data_out(7)=> Port7_out(1), + Data_out(8)=> Port8_out(1), + Data_out(9)=> Port9_out(1), + Data_out(10)=> Port10_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 10) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_In(3) => Port3_in(2), + Data_In(4) => Port4_in(2), + Data_In(5) => Port5_in(2), + Data_In(6) => Port6_in(2), + Data_In(7) => Port7_in(2), + Data_In(8) => Port8_in(2), + Data_In(9) => Port9_in(2), + Data_In(10) => Port10_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2), + Data_out(3)=> Port3_out(2), + Data_out(4)=> Port4_out(2), + Data_out(5)=> Port5_out(2), + Data_out(6)=> Port6_out(2), + Data_out(7)=> Port7_out(2), + Data_out(8)=> Port8_out(2), + Data_out(9)=> Port9_out(2), + Data_out(10)=> Port10_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 10) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_In(3) => Port3_in(3), + Data_In(4) => Port4_in(3), + Data_In(5) => Port5_in(3), + Data_In(6) => Port6_in(3), + Data_In(7) => Port7_in(3), + Data_In(8) => Port8_in(3), + Data_In(9) => Port9_in(3), + Data_In(10) => Port10_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3), + Data_out(3)=> Port3_out(3), + Data_out(4)=> Port4_out(3), + Data_out(5)=> Port5_out(3), + Data_out(6)=> Port6_out(3), + Data_out(7)=> Port7_out(3), + Data_out(8)=> Port8_out(3), + Data_out(9)=> Port9_out(3), + Data_out(10)=> Port10_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 10) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_In(3) => Port3_in(4), + Data_In(4) => Port4_in(4), + Data_In(5) => Port5_in(4), + Data_In(6) => Port6_in(4), + Data_In(7) => Port7_in(4), + Data_In(8) => Port8_in(4), + Data_In(9) => Port9_in(4), + Data_In(10) => Port10_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4), + Data_out(3)=> Port3_out(4), + Data_out(4)=> Port4_out(4), + Data_out(5)=> Port5_out(4), + Data_out(6)=> Port6_out(4), + Data_out(7)=> Port7_out(4), + Data_out(8)=> Port8_out(4), + Data_out(9)=> Port9_out(4), + Data_out(10)=> Port10_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 10) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_In(3) => Port3_in(5), + Data_In(4) => Port4_in(5), + Data_In(5) => Port5_in(5), + Data_In(6) => Port6_in(5), + Data_In(7) => Port7_in(5), + Data_In(8) => Port8_in(5), + Data_In(9) => Port9_in(5), + Data_In(10) => Port10_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5), + Data_out(3)=> Port3_out(5), + Data_out(4)=> Port4_out(5), + Data_out(5)=> Port5_out(5), + Data_out(6)=> Port6_out(5), + Data_out(7)=> Port7_out(5), + Data_out(8)=> Port8_out(5), + Data_out(9)=> Port9_out(5), + Data_out(10)=> Port10_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 10) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_In(3) => Port3_in(6), + Data_In(4) => Port4_in(6), + Data_In(5) => Port5_in(6), + Data_In(6) => Port6_in(6), + Data_In(7) => Port7_in(6), + Data_In(8) => Port8_in(6), + Data_In(9) => Port9_in(6), + Data_In(10) => Port10_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6), + Data_out(3)=> Port3_out(6), + Data_out(4)=> Port4_out(6), + Data_out(5)=> Port5_out(6), + Data_out(6)=> Port6_out(6), + Data_out(7)=> Port7_out(6), + Data_out(8)=> Port8_out(6), + Data_out(9)=> Port9_out(6), + Data_out(10)=> Port10_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 10) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_In(3) => Port3_in(7), + Data_In(4) => Port4_in(7), + Data_In(5) => Port5_in(7), + Data_In(6) => Port6_in(7), + Data_In(7) => Port7_in(7), + Data_In(8) => Port8_in(7), + Data_In(9) => Port9_in(7), + Data_In(10) => Port10_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7), + Data_out(3)=> Port3_out(7), + Data_out(4)=> Port4_out(7), + Data_out(5)=> Port5_out(7), + Data_out(6)=> Port6_out(7), + Data_out(7)=> Port7_out(7), + Data_out(8)=> Port8_out(7), + Data_out(9)=> Port9_out(7), + Data_out(10)=> Port10_out(7) + + ); +-- crossbit du pulse_out 10 ports + + Pulse_out_Crossbit10: Crossbit + GENERIC MAP(number_of_ports => 10) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_In(3) => Port3_pulse_in, + Data_In(4) => Port4_pulse_in, + Data_In(5) => Port5_pulse_in, + Data_In(6) => Port6_pulse_in, + Data_In(7) => Port7_pulse_in, + Data_In(8) => Port8_pulse_in, + Data_In(9) => Port9_pulse_in, + Data_In(10) => Port10_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out, + Data_out(3) => Port3_pulse_out, + Data_out(4) => Port4_pulse_out, + Data_out(5) => Port5_pulse_out, + Data_out(6) => Port6_pulse_out, + Data_out(7) => Port7_pulse_out, + Data_out(8) => Port8_pulse_out, + Data_out(9) => Port9_pulse_out, + Data_out(10) => Port10_pulse_out + + ); +end generate crossbar10x10; + + +--======================crossbar 11 ports======================= + +crossbar11x11 : if number_of_crossbar_ports = 11 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 11) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_In(3) => Port3_in(0), + Data_In(4) => Port4_in(0), + Data_In(5) => Port5_in(0), + Data_In(6) => Port6_in(0), + Data_In(7) => Port7_in(0), + Data_In(8) => Port8_in(0), + Data_In(9) => Port9_in(0), + Data_In(10) => Port10_in(0), + Data_In(11) => Port11_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0), + Data_out(3)=> Port3_out(0), + Data_out(4)=> Port4_out(0), + Data_out(5)=> Port5_out(0), + Data_out(6)=> Port6_out(0), + Data_out(7)=> Port7_out(0), + Data_out(8)=> Port8_out(0), + Data_out(9)=> Port9_out(0), + Data_out(10)=> Port10_out(0), + Data_out(11)=> Port11_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 11) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_In(3) => Port3_in(1), + Data_In(4) => Port4_in(1), + Data_In(5) => Port5_in(1), + Data_In(6) => Port6_in(1), + Data_In(7) => Port7_in(1), + Data_In(8) => Port8_in(1), + Data_In(9) => Port9_in(1), + Data_In(10) => Port10_in(1), + Data_In(11) => Port11_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1), + Data_out(3)=> Port3_out(1), + Data_out(4)=> Port4_out(1), + Data_out(5)=> Port5_out(1), + Data_out(6)=> Port6_out(1), + Data_out(7)=> Port7_out(1), + Data_out(8)=> Port8_out(1), + Data_out(9)=> Port9_out(1), + Data_out(10)=> Port10_out(1), + Data_out(11)=> Port11_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 11) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_In(3) => Port3_in(2), + Data_In(4) => Port4_in(2), + Data_In(5) => Port5_in(2), + Data_In(6) => Port6_in(2), + Data_In(7) => Port7_in(2), + Data_In(8) => Port8_in(2), + Data_In(9) => Port9_in(2), + Data_In(10) => Port10_in(2), + Data_In(11) => Port11_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2), + Data_out(3)=> Port3_out(2), + Data_out(4)=> Port4_out(2), + Data_out(5)=> Port5_out(2), + Data_out(6)=> Port6_out(2), + Data_out(7)=> Port7_out(2), + Data_out(8)=> Port8_out(2), + Data_out(9)=> Port9_out(2), + Data_out(10)=> Port10_out(2), + Data_out(11)=> Port11_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 11) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_In(3) => Port3_in(3), + Data_In(4) => Port4_in(3), + Data_In(5) => Port5_in(3), + Data_In(6) => Port6_in(3), + Data_In(7) => Port7_in(3), + Data_In(8) => Port8_in(3), + Data_In(9) => Port9_in(3), + Data_In(10) => Port10_in(3), + Data_In(11) => Port11_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3), + Data_out(3)=> Port3_out(3), + Data_out(4)=> Port4_out(3), + Data_out(5)=> Port5_out(3), + Data_out(6)=> Port6_out(3), + Data_out(7)=> Port7_out(3), + Data_out(8)=> Port8_out(3), + Data_out(9)=> Port9_out(3), + Data_out(10)=> Port10_out(3), + Data_out(11)=> Port11_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 11) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_In(3) => Port3_in(4), + Data_In(4) => Port4_in(4), + Data_In(5) => Port5_in(4), + Data_In(6) => Port6_in(4), + Data_In(7) => Port7_in(4), + Data_In(8) => Port8_in(4), + Data_In(9) => Port9_in(4), + Data_In(10) => Port10_in(4), + Data_In(11) => Port11_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4), + Data_out(3)=> Port3_out(4), + Data_out(4)=> Port4_out(4), + Data_out(5)=> Port5_out(4), + Data_out(6)=> Port6_out(4), + Data_out(7)=> Port7_out(4), + Data_out(8)=> Port8_out(4), + Data_out(9)=> Port9_out(4), + Data_out(10)=> Port10_out(4), + Data_out(11)=> Port11_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 11) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_In(3) => Port3_in(5), + Data_In(4) => Port4_in(5), + Data_In(5) => Port5_in(5), + Data_In(6) => Port6_in(5), + Data_In(7) => Port7_in(5), + Data_In(8) => Port8_in(5), + Data_In(9) => Port9_in(5), + Data_In(10) => Port10_in(5), + Data_In(11) => Port11_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5), + Data_out(3)=> Port3_out(5), + Data_out(4)=> Port4_out(5), + Data_out(5)=> Port5_out(5), + Data_out(6)=> Port6_out(5), + Data_out(7)=> Port7_out(5), + Data_out(8)=> Port8_out(5), + Data_out(9)=> Port9_out(5), + Data_out(10)=> Port10_out(5), + Data_out(11)=> Port11_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 11) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_In(3) => Port3_in(6), + Data_In(4) => Port4_in(6), + Data_In(5) => Port5_in(6), + Data_In(6) => Port6_in(6), + Data_In(7) => Port7_in(6), + Data_In(8) => Port8_in(6), + Data_In(9) => Port9_in(6), + Data_In(10) => Port10_in(6), + Data_In(11) => Port11_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6), + Data_out(3)=> Port3_out(6), + Data_out(4)=> Port4_out(6), + Data_out(5)=> Port5_out(6), + Data_out(6)=> Port6_out(6), + Data_out(7)=> Port7_out(6), + Data_out(8)=> Port8_out(6), + Data_out(9)=> Port9_out(6), + Data_out(10)=> Port10_out(6), + Data_out(11)=> Port11_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 11) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_In(3) => Port3_in(7), + Data_In(4) => Port4_in(7), + Data_In(5) => Port5_in(7), + Data_In(6) => Port6_in(7), + Data_In(7) => Port7_in(7), + Data_In(8) => Port8_in(7), + Data_In(9) => Port9_in(7), + Data_In(10) => Port10_in(7), + Data_In(11) => Port11_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7), + Data_out(3)=> Port3_out(7), + Data_out(4)=> Port4_out(7), + Data_out(5)=> Port5_out(7), + Data_out(6)=> Port6_out(7), + Data_out(7)=> Port7_out(7), + Data_out(8)=> Port8_out(7), + Data_out(9)=> Port9_out(7), + Data_out(10)=> Port10_out(7), + Data_out(11)=> Port11_out(7) + + ); +-- crossbit du pulse_out 11 ports + + Pulse_out_Crossbit11: Crossbit + GENERIC MAP(number_of_ports => 11) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_In(3) => Port3_pulse_in, + Data_In(4) => Port4_pulse_in, + Data_In(5) => Port5_pulse_in, + Data_In(6) => Port6_pulse_in, + Data_In(7) => Port7_pulse_in, + Data_In(8) => Port8_pulse_in, + Data_In(9) => Port9_pulse_in, + Data_In(10) => Port10_pulse_in, + Data_In(11) => Port11_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out, + Data_out(3) => Port3_pulse_out, + Data_out(4) => Port4_pulse_out, + Data_out(5) => Port5_pulse_out, + Data_out(6) => Port6_pulse_out, + Data_out(7) => Port7_pulse_out, + Data_out(8) => Port8_pulse_out, + Data_out(9) => Port9_pulse_out, + Data_out(10) => Port10_pulse_out, + Data_out(11) => Port11_pulse_out + + ); +end generate crossbar11x11; + + +--======================crossbar 12 ports======================= + +crossbar12x12 : if number_of_crossbar_ports = 12 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 12) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_In(3) => Port3_in(0), + Data_In(4) => Port4_in(0), + Data_In(5) => Port5_in(0), + Data_In(6) => Port6_in(0), + Data_In(7) => Port7_in(0), + Data_In(8) => Port8_in(0), + Data_In(9) => Port9_in(0), + Data_In(10) => Port10_in(0), + Data_In(11) => Port11_in(0), + Data_In(12) => Port12_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0), + Data_out(3)=> Port3_out(0), + Data_out(4)=> Port4_out(0), + Data_out(5)=> Port5_out(0), + Data_out(6)=> Port6_out(0), + Data_out(7)=> Port7_out(0), + Data_out(8)=> Port8_out(0), + Data_out(9)=> Port9_out(0), + Data_out(10)=> Port10_out(0), + Data_out(11)=> Port11_out(0), + Data_out(12)=> Port12_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 12) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_In(3) => Port3_in(1), + Data_In(4) => Port4_in(1), + Data_In(5) => Port5_in(1), + Data_In(6) => Port6_in(1), + Data_In(7) => Port7_in(1), + Data_In(8) => Port8_in(1), + Data_In(9) => Port9_in(1), + Data_In(10) => Port10_in(1), + Data_In(11) => Port11_in(1), + Data_In(12) => Port12_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1), + Data_out(3)=> Port3_out(1), + Data_out(4)=> Port4_out(1), + Data_out(5)=> Port5_out(1), + Data_out(6)=> Port6_out(1), + Data_out(7)=> Port7_out(1), + Data_out(8)=> Port8_out(1), + Data_out(9)=> Port9_out(1), + Data_out(10)=> Port10_out(1), + Data_out(11)=> Port11_out(1), + Data_out(12)=> Port12_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 12) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_In(3) => Port3_in(2), + Data_In(4) => Port4_in(2), + Data_In(5) => Port5_in(2), + Data_In(6) => Port6_in(2), + Data_In(7) => Port7_in(2), + Data_In(8) => Port8_in(2), + Data_In(9) => Port9_in(2), + Data_In(10) => Port10_in(2), + Data_In(11) => Port11_in(2), + Data_In(12) => Port12_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2), + Data_out(3)=> Port3_out(2), + Data_out(4)=> Port4_out(2), + Data_out(5)=> Port5_out(2), + Data_out(6)=> Port6_out(2), + Data_out(7)=> Port7_out(2), + Data_out(8)=> Port8_out(2), + Data_out(9)=> Port9_out(2), + Data_out(10)=> Port10_out(2), + Data_out(11)=> Port11_out(2), + Data_out(12)=> Port12_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 12) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_In(3) => Port3_in(3), + Data_In(4) => Port4_in(3), + Data_In(5) => Port5_in(3), + Data_In(6) => Port6_in(3), + Data_In(7) => Port7_in(3), + Data_In(8) => Port8_in(3), + Data_In(9) => Port9_in(3), + Data_In(10) => Port10_in(3), + Data_In(11) => Port11_in(3), + Data_In(12) => Port12_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3), + Data_out(3)=> Port3_out(3), + Data_out(4)=> Port4_out(3), + Data_out(5)=> Port5_out(3), + Data_out(6)=> Port6_out(3), + Data_out(7)=> Port7_out(3), + Data_out(8)=> Port8_out(3), + Data_out(9)=> Port9_out(3), + Data_out(10)=> Port10_out(3), + Data_out(11)=> Port11_out(3), + Data_out(12)=> Port12_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 12) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_In(3) => Port3_in(4), + Data_In(4) => Port4_in(4), + Data_In(5) => Port5_in(4), + Data_In(6) => Port6_in(4), + Data_In(7) => Port7_in(4), + Data_In(8) => Port8_in(4), + Data_In(9) => Port9_in(4), + Data_In(10) => Port10_in(4), + Data_In(11) => Port11_in(4), + Data_In(12) => Port12_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4), + Data_out(3)=> Port3_out(4), + Data_out(4)=> Port4_out(4), + Data_out(5)=> Port5_out(4), + Data_out(6)=> Port6_out(4), + Data_out(7)=> Port7_out(4), + Data_out(8)=> Port8_out(4), + Data_out(9)=> Port9_out(4), + Data_out(10)=> Port10_out(4), + Data_out(11)=> Port11_out(4), + Data_out(12)=> Port12_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 12) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_In(3) => Port3_in(5), + Data_In(4) => Port4_in(5), + Data_In(5) => Port5_in(5), + Data_In(6) => Port6_in(5), + Data_In(7) => Port7_in(5), + Data_In(8) => Port8_in(5), + Data_In(9) => Port9_in(5), + Data_In(10) => Port10_in(5), + Data_In(11) => Port11_in(5), + Data_In(12) => Port12_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5), + Data_out(3)=> Port3_out(5), + Data_out(4)=> Port4_out(5), + Data_out(5)=> Port5_out(5), + Data_out(6)=> Port6_out(5), + Data_out(7)=> Port7_out(5), + Data_out(8)=> Port8_out(5), + Data_out(9)=> Port9_out(5), + Data_out(10)=> Port10_out(5), + Data_out(11)=> Port11_out(5), + Data_out(12)=> Port12_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 12) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_In(3) => Port3_in(6), + Data_In(4) => Port4_in(6), + Data_In(5) => Port5_in(6), + Data_In(6) => Port6_in(6), + Data_In(7) => Port7_in(6), + Data_In(8) => Port8_in(6), + Data_In(9) => Port9_in(6), + Data_In(10) => Port10_in(6), + Data_In(11) => Port11_in(6), + Data_In(12) => Port12_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6), + Data_out(3)=> Port3_out(6), + Data_out(4)=> Port4_out(6), + Data_out(5)=> Port5_out(6), + Data_out(6)=> Port6_out(6), + Data_out(7)=> Port7_out(6), + Data_out(8)=> Port8_out(6), + Data_out(9)=> Port9_out(6), + Data_out(10)=> Port10_out(6), + Data_out(11)=> Port11_out(6), + Data_out(12)=> Port12_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 12) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_In(3) => Port3_in(7), + Data_In(4) => Port4_in(7), + Data_In(5) => Port5_in(7), + Data_In(6) => Port6_in(7), + Data_In(7) => Port7_in(7), + Data_In(8) => Port8_in(7), + Data_In(9) => Port9_in(7), + Data_In(10) => Port10_in(7), + Data_In(11) => Port11_in(7), + Data_In(12) => Port12_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7), + Data_out(3)=> Port3_out(7), + Data_out(4)=> Port4_out(7), + Data_out(5)=> Port5_out(7), + Data_out(6)=> Port6_out(7), + Data_out(7)=> Port7_out(7), + Data_out(8)=> Port8_out(7), + Data_out(9)=> Port9_out(7), + Data_out(10)=> Port10_out(7), + Data_out(11)=> Port11_out(7), + Data_out(12)=> Port12_out(7) + + ); +-- crossbit du pulse_out 12 ports + + Pulse_out_Crossbit12: Crossbit + GENERIC MAP(number_of_ports => 12) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_In(3) => Port3_pulse_in, + Data_In(4) => Port4_pulse_in, + Data_In(5) => Port5_pulse_in, + Data_In(6) => Port6_pulse_in, + Data_In(7) => Port7_pulse_in, + Data_In(8) => Port8_pulse_in, + Data_In(9) => Port9_pulse_in, + Data_In(10) => Port10_pulse_in, + Data_In(11) => Port11_pulse_in, + Data_In(12) => Port12_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out, + Data_out(3) => Port3_pulse_out, + Data_out(4) => Port4_pulse_out, + Data_out(5) => Port5_pulse_out, + Data_out(6) => Port6_pulse_out, + Data_out(7) => Port7_pulse_out, + Data_out(8) => Port8_pulse_out, + Data_out(9) => Port9_pulse_out, + Data_out(10) => Port10_pulse_out, + Data_out(11) => Port11_pulse_out, + Data_out(12) => Port12_pulse_out + + ); +end generate crossbar12x12; + + +--======================crossbar 13 ports======================= + +crossbar13x13 : if number_of_crossbar_ports = 13 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 13) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_In(3) => Port3_in(0), + Data_In(4) => Port4_in(0), + Data_In(5) => Port5_in(0), + Data_In(6) => Port6_in(0), + Data_In(7) => Port7_in(0), + Data_In(8) => Port8_in(0), + Data_In(9) => Port9_in(0), + Data_In(10) => Port10_in(0), + Data_In(11) => Port11_in(0), + Data_In(12) => Port12_in(0), + Data_In(13) => Port13_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0), + Data_out(3)=> Port3_out(0), + Data_out(4)=> Port4_out(0), + Data_out(5)=> Port5_out(0), + Data_out(6)=> Port6_out(0), + Data_out(7)=> Port7_out(0), + Data_out(8)=> Port8_out(0), + Data_out(9)=> Port9_out(0), + Data_out(10)=> Port10_out(0), + Data_out(11)=> Port11_out(0), + Data_out(12)=> Port12_out(0), + Data_out(13)=> Port13_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 13) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_In(3) => Port3_in(1), + Data_In(4) => Port4_in(1), + Data_In(5) => Port5_in(1), + Data_In(6) => Port6_in(1), + Data_In(7) => Port7_in(1), + Data_In(8) => Port8_in(1), + Data_In(9) => Port9_in(1), + Data_In(10) => Port10_in(1), + Data_In(11) => Port11_in(1), + Data_In(12) => Port12_in(1), + Data_In(13) => Port13_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1), + Data_out(3)=> Port3_out(1), + Data_out(4)=> Port4_out(1), + Data_out(5)=> Port5_out(1), + Data_out(6)=> Port6_out(1), + Data_out(7)=> Port7_out(1), + Data_out(8)=> Port8_out(1), + Data_out(9)=> Port9_out(1), + Data_out(10)=> Port10_out(1), + Data_out(11)=> Port11_out(1), + Data_out(12)=> Port12_out(1), + Data_out(13)=> Port13_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 13) + PORT MAP( + + reset => reset, + clk=>clk, + + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_In(3) => Port3_in(2), + Data_In(4) => Port4_in(2), + Data_In(5) => Port5_in(2), + Data_In(6) => Port6_in(2), + Data_In(7) => Port7_in(2), + Data_In(8) => Port8_in(2), + Data_In(9) => Port9_in(2), + Data_In(10) => Port10_in(2), + Data_In(11) => Port11_in(2), + Data_In(12) => Port12_in(2), + Data_In(13) => Port13_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2), + Data_out(3)=> Port3_out(2), + Data_out(4)=> Port4_out(2), + Data_out(5)=> Port5_out(2), + Data_out(6)=> Port6_out(2), + Data_out(7)=> Port7_out(2), + Data_out(8)=> Port8_out(2), + Data_out(9)=> Port9_out(2), + Data_out(10)=> Port10_out(2), + Data_out(11)=> Port11_out(2), + Data_out(12)=> Port12_out(2), + Data_out(13)=> Port13_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 13) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_In(3) => Port3_in(3), + Data_In(4) => Port4_in(3), + Data_In(5) => Port5_in(3), + Data_In(6) => Port6_in(3), + Data_In(7) => Port7_in(3), + Data_In(8) => Port8_in(3), + Data_In(9) => Port9_in(3), + Data_In(10) => Port10_in(3), + Data_In(11) => Port11_in(3), + Data_In(12) => Port12_in(3), + Data_In(13) => Port13_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3), + Data_out(3)=> Port3_out(3), + Data_out(4)=> Port4_out(3), + Data_out(5)=> Port5_out(3), + Data_out(6)=> Port6_out(3), + Data_out(7)=> Port7_out(3), + Data_out(8)=> Port8_out(3), + Data_out(9)=> Port9_out(3), + Data_out(10)=> Port10_out(3), + Data_out(11)=> Port11_out(3), + Data_out(12)=> Port12_out(3), + Data_out(13)=> Port13_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 13) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_In(3) => Port3_in(4), + Data_In(4) => Port4_in(4), + Data_In(5) => Port5_in(4), + Data_In(6) => Port6_in(4), + Data_In(7) => Port7_in(4), + Data_In(8) => Port8_in(4), + Data_In(9) => Port9_in(4), + Data_In(10) => Port10_in(4), + Data_In(11) => Port11_in(4), + Data_In(12) => Port12_in(4), + Data_In(13) => Port13_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4), + Data_out(3)=> Port3_out(4), + Data_out(4)=> Port4_out(4), + Data_out(5)=> Port5_out(4), + Data_out(6)=> Port6_out(4), + Data_out(7)=> Port7_out(4), + Data_out(8)=> Port8_out(4), + Data_out(9)=> Port9_out(4), + Data_out(10)=> Port10_out(4), + Data_out(11)=> Port11_out(4), + Data_out(12)=> Port12_out(4), + Data_out(13)=> Port13_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 13) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_In(3) => Port3_in(5), + Data_In(4) => Port4_in(5), + Data_In(5) => Port5_in(5), + Data_In(6) => Port6_in(5), + Data_In(7) => Port7_in(5), + Data_In(8) => Port8_in(5), + Data_In(9) => Port9_in(5), + Data_In(10) => Port10_in(5), + Data_In(11) => Port11_in(5), + Data_In(12) => Port12_in(5), + Data_In(13) => Port13_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5), + Data_out(3)=> Port3_out(5), + Data_out(4)=> Port4_out(5), + Data_out(5)=> Port5_out(5), + Data_out(6)=> Port6_out(5), + Data_out(7)=> Port7_out(5), + Data_out(8)=> Port8_out(5), + Data_out(9)=> Port9_out(5), + Data_out(10)=> Port10_out(5), + Data_out(11)=> Port11_out(5), + Data_out(12)=> Port12_out(5), + Data_out(13)=> Port13_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 13) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_In(3) => Port3_in(6), + Data_In(4) => Port4_in(6), + Data_In(5) => Port5_in(6), + Data_In(6) => Port6_in(6), + Data_In(7) => Port7_in(6), + Data_In(8) => Port8_in(6), + Data_In(9) => Port9_in(6), + Data_In(10) => Port10_in(6), + Data_In(11) => Port11_in(6), + Data_In(12) => Port12_in(6), + Data_In(13) => Port13_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6), + Data_out(3)=> Port3_out(6), + Data_out(4)=> Port4_out(6), + Data_out(5)=> Port5_out(6), + Data_out(6)=> Port6_out(6), + Data_out(7)=> Port7_out(6), + Data_out(8)=> Port8_out(6), + Data_out(9)=> Port9_out(6), + Data_out(10)=> Port10_out(6), + Data_out(11)=> Port11_out(6), + Data_out(12)=> Port12_out(6), + Data_out(13)=> Port13_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 13) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_In(3) => Port3_in(7), + Data_In(4) => Port4_in(7), + Data_In(5) => Port5_in(7), + Data_In(6) => Port6_in(7), + Data_In(7) => Port7_in(7), + Data_In(8) => Port8_in(7), + Data_In(9) => Port9_in(7), + Data_In(10) => Port10_in(7), + Data_In(11) => Port11_in(7), + Data_In(12) => Port12_in(7), + Data_In(13) => Port13_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7), + Data_out(3)=> Port3_out(7), + Data_out(4)=> Port4_out(7), + Data_out(5)=> Port5_out(7), + Data_out(6)=> Port6_out(7), + Data_out(7)=> Port7_out(7), + Data_out(8)=> Port8_out(7), + Data_out(9)=> Port9_out(7), + Data_out(10)=> Port10_out(7), + Data_out(11)=> Port11_out(7), + Data_out(12)=> Port12_out(7), + Data_out(13)=> Port13_out(7) + + ); +-- crossbit du pulse_out 13 ports + + Pulse_out_Crossbit13: Crossbit + GENERIC MAP(number_of_ports => 13) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_In(3) => Port3_pulse_in, + Data_In(4) => Port4_pulse_in, + Data_In(5) => Port5_pulse_in, + Data_In(6) => Port6_pulse_in, + Data_In(7) => Port7_pulse_in, + Data_In(8) => Port8_pulse_in, + Data_In(9) => Port9_pulse_in, + Data_In(10) => Port10_pulse_in, + Data_In(11) => Port11_pulse_in, + Data_In(12) => Port12_pulse_in, + Data_In(13) => Port13_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out, + Data_out(3) => Port3_pulse_out, + Data_out(4) => Port4_pulse_out, + Data_out(5) => Port5_pulse_out, + Data_out(6) => Port6_pulse_out, + Data_out(7) => Port7_pulse_out, + Data_out(8) => Port8_pulse_out, + Data_out(9) => Port9_pulse_out, + Data_out(10) => Port10_pulse_out, + Data_out(11) => Port11_pulse_out, + Data_out(12) => Port12_pulse_out, + Data_out(13) => Port13_pulse_out + + ); +end generate crossbar13x13; + + +--======================crossbar 14 ports======================= + +crossbar14x14 : if number_of_crossbar_ports = 14 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 14) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_In(3) => Port3_in(0), + Data_In(4) => Port4_in(0), + Data_In(5) => Port5_in(0), + Data_In(6) => Port6_in(0), + Data_In(7) => Port7_in(0), + Data_In(8) => Port8_in(0), + Data_In(9) => Port9_in(0), + Data_In(10) => Port10_in(0), + Data_In(11) => Port11_in(0), + Data_In(12) => Port12_in(0), + Data_In(13) => Port13_in(0), + Data_In(14) => Port14_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0), + Data_out(3)=> Port3_out(0), + Data_out(4)=> Port4_out(0), + Data_out(5)=> Port5_out(0), + Data_out(6)=> Port6_out(0), + Data_out(7)=> Port7_out(0), + Data_out(8)=> Port8_out(0), + Data_out(9)=> Port9_out(0), + Data_out(10)=> Port10_out(0), + Data_out(11)=> Port11_out(0), + Data_out(12)=> Port12_out(0), + Data_out(13)=> Port13_out(0), + Data_out(14)=> Port14_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 14) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_In(3) => Port3_in(1), + Data_In(4) => Port4_in(1), + Data_In(5) => Port5_in(1), + Data_In(6) => Port6_in(1), + Data_In(7) => Port7_in(1), + Data_In(8) => Port8_in(1), + Data_In(9) => Port9_in(1), + Data_In(10) => Port10_in(1), + Data_In(11) => Port11_in(1), + Data_In(12) => Port12_in(1), + Data_In(13) => Port13_in(1), + Data_In(14) => Port14_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1), + Data_out(3)=> Port3_out(1), + Data_out(4)=> Port4_out(1), + Data_out(5)=> Port5_out(1), + Data_out(6)=> Port6_out(1), + Data_out(7)=> Port7_out(1), + Data_out(8)=> Port8_out(1), + Data_out(9)=> Port9_out(1), + Data_out(10)=> Port10_out(1), + Data_out(11)=> Port11_out(1), + Data_out(12)=> Port12_out(1), + Data_out(13)=> Port13_out(1), + Data_out(14)=> Port14_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 14) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_In(3) => Port3_in(2), + Data_In(4) => Port4_in(2), + Data_In(5) => Port5_in(2), + Data_In(6) => Port6_in(2), + Data_In(7) => Port7_in(2), + Data_In(8) => Port8_in(2), + Data_In(9) => Port9_in(2), + Data_In(10) => Port10_in(2), + Data_In(11) => Port11_in(2), + Data_In(12) => Port12_in(2), + Data_In(13) => Port13_in(2), + Data_In(14) => Port14_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2), + Data_out(3)=> Port3_out(2), + Data_out(4)=> Port4_out(2), + Data_out(5)=> Port5_out(2), + Data_out(6)=> Port6_out(2), + Data_out(7)=> Port7_out(2), + Data_out(8)=> Port8_out(2), + Data_out(9)=> Port9_out(2), + Data_out(10)=> Port10_out(2), + Data_out(11)=> Port11_out(2), + Data_out(12)=> Port12_out(2), + Data_out(13)=> Port13_out(2), + Data_out(14)=> Port14_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 14) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_In(3) => Port3_in(3), + Data_In(4) => Port4_in(3), + Data_In(5) => Port5_in(3), + Data_In(6) => Port6_in(3), + Data_In(7) => Port7_in(3), + Data_In(8) => Port8_in(3), + Data_In(9) => Port9_in(3), + Data_In(10) => Port10_in(3), + Data_In(11) => Port11_in(3), + Data_In(12) => Port12_in(3), + Data_In(13) => Port13_in(3), + Data_In(14) => Port14_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3), + Data_out(3)=> Port3_out(3), + Data_out(4)=> Port4_out(3), + Data_out(5)=> Port5_out(3), + Data_out(6)=> Port6_out(3), + Data_out(7)=> Port7_out(3), + Data_out(8)=> Port8_out(3), + Data_out(9)=> Port9_out(3), + Data_out(10)=> Port10_out(3), + Data_out(11)=> Port11_out(3), + Data_out(12)=> Port12_out(3), + Data_out(13)=> Port13_out(3), + Data_out(14)=> Port14_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 14) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_In(3) => Port3_in(4), + Data_In(4) => Port4_in(4), + Data_In(5) => Port5_in(4), + Data_In(6) => Port6_in(4), + Data_In(7) => Port7_in(4), + Data_In(8) => Port8_in(4), + Data_In(9) => Port9_in(4), + Data_In(10) => Port10_in(4), + Data_In(11) => Port11_in(4), + Data_In(12) => Port12_in(4), + Data_In(13) => Port13_in(4), + Data_In(14) => Port14_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4), + Data_out(3)=> Port3_out(4), + Data_out(4)=> Port4_out(4), + Data_out(5)=> Port5_out(4), + Data_out(6)=> Port6_out(4), + Data_out(7)=> Port7_out(4), + Data_out(8)=> Port8_out(4), + Data_out(9)=> Port9_out(4), + Data_out(10)=> Port10_out(4), + Data_out(11)=> Port11_out(4), + Data_out(12)=> Port12_out(4), + Data_out(13)=> Port13_out(4), + Data_out(14)=> Port14_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 14) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_In(3) => Port3_in(5), + Data_In(4) => Port4_in(5), + Data_In(5) => Port5_in(5), + Data_In(6) => Port6_in(5), + Data_In(7) => Port7_in(5), + Data_In(8) => Port8_in(5), + Data_In(9) => Port9_in(5), + Data_In(10) => Port10_in(5), + Data_In(11) => Port11_in(5), + Data_In(12) => Port12_in(5), + Data_In(13) => Port13_in(5), + Data_In(14) => Port14_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5), + Data_out(3)=> Port3_out(5), + Data_out(4)=> Port4_out(5), + Data_out(5)=> Port5_out(5), + Data_out(6)=> Port6_out(5), + Data_out(7)=> Port7_out(5), + Data_out(8)=> Port8_out(5), + Data_out(9)=> Port9_out(5), + Data_out(10)=> Port10_out(5), + Data_out(11)=> Port11_out(5), + Data_out(12)=> Port12_out(5), + Data_out(13)=> Port13_out(5), + Data_out(14)=> Port14_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 14) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_In(3) => Port3_in(6), + Data_In(4) => Port4_in(6), + Data_In(5) => Port5_in(6), + Data_In(6) => Port6_in(6), + Data_In(7) => Port7_in(6), + Data_In(8) => Port8_in(6), + Data_In(9) => Port9_in(6), + Data_In(10) => Port10_in(6), + Data_In(11) => Port11_in(6), + Data_In(12) => Port12_in(6), + Data_In(13) => Port13_in(6), + Data_In(14) => Port14_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6), + Data_out(3)=> Port3_out(6), + Data_out(4)=> Port4_out(6), + Data_out(5)=> Port5_out(6), + Data_out(6)=> Port6_out(6), + Data_out(7)=> Port7_out(6), + Data_out(8)=> Port8_out(6), + Data_out(9)=> Port9_out(6), + Data_out(10)=> Port10_out(6), + Data_out(11)=> Port11_out(6), + Data_out(12)=> Port12_out(6), + Data_out(13)=> Port13_out(6), + Data_out(14)=> Port14_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 14) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_In(3) => Port3_in(7), + Data_In(4) => Port4_in(7), + Data_In(5) => Port5_in(7), + Data_In(6) => Port6_in(7), + Data_In(7) => Port7_in(7), + Data_In(8) => Port8_in(7), + Data_In(9) => Port9_in(7), + Data_In(10) => Port10_in(7), + Data_In(11) => Port11_in(7), + Data_In(12) => Port12_in(7), + Data_In(13) => Port13_in(7), + Data_In(14) => Port14_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7), + Data_out(3)=> Port3_out(7), + Data_out(4)=> Port4_out(7), + Data_out(5)=> Port5_out(7), + Data_out(6)=> Port6_out(7), + Data_out(7)=> Port7_out(7), + Data_out(8)=> Port8_out(7), + Data_out(9)=> Port9_out(7), + Data_out(10)=> Port10_out(7), + Data_out(11)=> Port11_out(7), + Data_out(12)=> Port12_out(7), + Data_out(13)=> Port13_out(7), + Data_out(14)=> Port14_out(7) + + ); +-- crossbit du pulse_out 14 ports + + Pulse_out_Crossbit14: Crossbit + GENERIC MAP(number_of_ports => 14) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_In(3) => Port3_pulse_in, + Data_In(4) => Port4_pulse_in, + Data_In(5) => Port5_pulse_in, + Data_In(6) => Port6_pulse_in, + Data_In(7) => Port7_pulse_in, + Data_In(8) => Port8_pulse_in, + Data_In(9) => Port9_pulse_in, + Data_In(10) => Port10_pulse_in, + Data_In(11) => Port11_pulse_in, + Data_In(12) => Port12_pulse_in, + Data_In(13) => Port13_pulse_in, + Data_In(14) => Port14_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out, + Data_out(3) => Port3_pulse_out, + Data_out(4) => Port4_pulse_out, + Data_out(5) => Port5_pulse_out, + Data_out(6) => Port6_pulse_out, + Data_out(7) => Port7_pulse_out, + Data_out(8) => Port8_pulse_out, + Data_out(9) => Port9_pulse_out, + Data_out(10) => Port10_pulse_out, + Data_out(11) => Port11_pulse_out, + Data_out(12) => Port12_pulse_out, + Data_out(13) => Port13_pulse_out, + Data_out(14) => Port14_pulse_out + + ); +end generate crossbar14x14; + + +--======================crossbar 15 ports======================= + +crossbar15x15 : if number_of_crossbar_ports = 15 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 15) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_In(3) => Port3_in(0), + Data_In(4) => Port4_in(0), + Data_In(5) => Port5_in(0), + Data_In(6) => Port6_in(0), + Data_In(7) => Port7_in(0), + Data_In(8) => Port8_in(0), + Data_In(9) => Port9_in(0), + Data_In(10) => Port10_in(0), + Data_In(11) => Port11_in(0), + Data_In(12) => Port12_in(0), + Data_In(13) => Port13_in(0), + Data_In(14) => Port14_in(0), + Data_In(15) => Port15_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0), + Data_out(3)=> Port3_out(0), + Data_out(4)=> Port4_out(0), + Data_out(5)=> Port5_out(0), + Data_out(6)=> Port6_out(0), + Data_out(7)=> Port7_out(0), + Data_out(8)=> Port8_out(0), + Data_out(9)=> Port9_out(0), + Data_out(10)=> Port10_out(0), + Data_out(11)=> Port11_out(0), + Data_out(12)=> Port12_out(0), + Data_out(13)=> Port13_out(0), + Data_out(14)=> Port14_out(0), + Data_out(15)=> Port15_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 15) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_In(3) => Port3_in(1), + Data_In(4) => Port4_in(1), + Data_In(5) => Port5_in(1), + Data_In(6) => Port6_in(1), + Data_In(7) => Port7_in(1), + Data_In(8) => Port8_in(1), + Data_In(9) => Port9_in(1), + Data_In(10) => Port10_in(1), + Data_In(11) => Port11_in(1), + Data_In(12) => Port12_in(1), + Data_In(13) => Port13_in(1), + Data_In(14) => Port14_in(1), + Data_In(15) => Port15_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1), + Data_out(3)=> Port3_out(1), + Data_out(4)=> Port4_out(1), + Data_out(5)=> Port5_out(1), + Data_out(6)=> Port6_out(1), + Data_out(7)=> Port7_out(1), + Data_out(8)=> Port8_out(1), + Data_out(9)=> Port9_out(1), + Data_out(10)=> Port10_out(1), + Data_out(11)=> Port11_out(1), + Data_out(12)=> Port12_out(1), + Data_out(13)=> Port13_out(1), + Data_out(14)=> Port14_out(1), + Data_out(15)=> Port15_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 15) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_In(3) => Port3_in(2), + Data_In(4) => Port4_in(2), + Data_In(5) => Port5_in(2), + Data_In(6) => Port6_in(2), + Data_In(7) => Port7_in(2), + Data_In(8) => Port8_in(2), + Data_In(9) => Port9_in(2), + Data_In(10) => Port10_in(2), + Data_In(11) => Port11_in(2), + Data_In(12) => Port12_in(2), + Data_In(13) => Port13_in(2), + Data_In(14) => Port14_in(2), + Data_In(15) => Port15_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2), + Data_out(3)=> Port3_out(2), + Data_out(4)=> Port4_out(2), + Data_out(5)=> Port5_out(2), + Data_out(6)=> Port6_out(2), + Data_out(7)=> Port7_out(2), + Data_out(8)=> Port8_out(2), + Data_out(9)=> Port9_out(2), + Data_out(10)=> Port10_out(2), + Data_out(11)=> Port11_out(2), + Data_out(12)=> Port12_out(2), + Data_out(13)=> Port13_out(2), + Data_out(14)=> Port14_out(2), + Data_out(15)=> Port15_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 15) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_In(3) => Port3_in(3), + Data_In(4) => Port4_in(3), + Data_In(5) => Port5_in(3), + Data_In(6) => Port6_in(3), + Data_In(7) => Port7_in(3), + Data_In(8) => Port8_in(3), + Data_In(9) => Port9_in(3), + Data_In(10) => Port10_in(3), + Data_In(11) => Port11_in(3), + Data_In(12) => Port12_in(3), + Data_In(13) => Port13_in(3), + Data_In(14) => Port14_in(3), + Data_In(15) => Port15_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3), + Data_out(3)=> Port3_out(3), + Data_out(4)=> Port4_out(3), + Data_out(5)=> Port5_out(3), + Data_out(6)=> Port6_out(3), + Data_out(7)=> Port7_out(3), + Data_out(8)=> Port8_out(3), + Data_out(9)=> Port9_out(3), + Data_out(10)=> Port10_out(3), + Data_out(11)=> Port11_out(3), + Data_out(12)=> Port12_out(3), + Data_out(13)=> Port13_out(3), + Data_out(14)=> Port14_out(3), + Data_out(15)=> Port15_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 15) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_In(3) => Port3_in(4), + Data_In(4) => Port4_in(4), + Data_In(5) => Port5_in(4), + Data_In(6) => Port6_in(4), + Data_In(7) => Port7_in(4), + Data_In(8) => Port8_in(4), + Data_In(9) => Port9_in(4), + Data_In(10) => Port10_in(4), + Data_In(11) => Port11_in(4), + Data_In(12) => Port12_in(4), + Data_In(13) => Port13_in(4), + Data_In(14) => Port14_in(4), + Data_In(15) => Port15_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4), + Data_out(3)=> Port3_out(4), + Data_out(4)=> Port4_out(4), + Data_out(5)=> Port5_out(4), + Data_out(6)=> Port6_out(4), + Data_out(7)=> Port7_out(4), + Data_out(8)=> Port8_out(4), + Data_out(9)=> Port9_out(4), + Data_out(10)=> Port10_out(4), + Data_out(11)=> Port11_out(4), + Data_out(12)=> Port12_out(4), + Data_out(13)=> Port13_out(4), + Data_out(14)=> Port14_out(4), + Data_out(15)=> Port15_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 15) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_In(3) => Port3_in(5), + Data_In(4) => Port4_in(5), + Data_In(5) => Port5_in(5), + Data_In(6) => Port6_in(5), + Data_In(7) => Port7_in(5), + Data_In(8) => Port8_in(5), + Data_In(9) => Port9_in(5), + Data_In(10) => Port10_in(5), + Data_In(11) => Port11_in(5), + Data_In(12) => Port12_in(5), + Data_In(13) => Port13_in(5), + Data_In(14) => Port14_in(5), + Data_In(15) => Port15_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5), + Data_out(3)=> Port3_out(5), + Data_out(4)=> Port4_out(5), + Data_out(5)=> Port5_out(5), + Data_out(6)=> Port6_out(5), + Data_out(7)=> Port7_out(5), + Data_out(8)=> Port8_out(5), + Data_out(9)=> Port9_out(5), + Data_out(10)=> Port10_out(5), + Data_out(11)=> Port11_out(5), + Data_out(12)=> Port12_out(5), + Data_out(13)=> Port13_out(5), + Data_out(14)=> Port14_out(5), + Data_out(15)=> Port15_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 15) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_In(3) => Port3_in(6), + Data_In(4) => Port4_in(6), + Data_In(5) => Port5_in(6), + Data_In(6) => Port6_in(6), + Data_In(7) => Port7_in(6), + Data_In(8) => Port8_in(6), + Data_In(9) => Port9_in(6), + Data_In(10) => Port10_in(6), + Data_In(11) => Port11_in(6), + Data_In(12) => Port12_in(6), + Data_In(13) => Port13_in(6), + Data_In(14) => Port14_in(6), + Data_In(15) => Port15_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6), + Data_out(3)=> Port3_out(6), + Data_out(4)=> Port4_out(6), + Data_out(5)=> Port5_out(6), + Data_out(6)=> Port6_out(6), + Data_out(7)=> Port7_out(6), + Data_out(8)=> Port8_out(6), + Data_out(9)=> Port9_out(6), + Data_out(10)=> Port10_out(6), + Data_out(11)=> Port11_out(6), + Data_out(12)=> Port12_out(6), + Data_out(13)=> Port13_out(6), + Data_out(14)=> Port14_out(6), + Data_out(15)=> Port15_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 15) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_In(3) => Port3_in(7), + Data_In(4) => Port4_in(7), + Data_In(5) => Port5_in(7), + Data_In(6) => Port6_in(7), + Data_In(7) => Port7_in(7), + Data_In(8) => Port8_in(7), + Data_In(9) => Port9_in(7), + Data_In(10) => Port10_in(7), + Data_In(11) => Port11_in(7), + Data_In(12) => Port12_in(7), + Data_In(13) => Port13_in(7), + Data_In(14) => Port14_in(7), + Data_In(15) => Port15_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7), + Data_out(3)=> Port3_out(7), + Data_out(4)=> Port4_out(7), + Data_out(5)=> Port5_out(7), + Data_out(6)=> Port6_out(7), + Data_out(7)=> Port7_out(7), + Data_out(8)=> Port8_out(7), + Data_out(9)=> Port9_out(7), + Data_out(10)=> Port10_out(7), + Data_out(11)=> Port11_out(7), + Data_out(12)=> Port12_out(7), + Data_out(13)=> Port13_out(7), + Data_out(14)=> Port14_out(7), + Data_out(15)=> Port15_out(7) + + ); +-- crossbit du pulse_out 15 ports + + Pulse_out_Crossbit15: Crossbit + GENERIC MAP(number_of_ports => 15) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_In(3) => Port3_pulse_in, + Data_In(4) => Port4_pulse_in, + Data_In(5) => Port5_pulse_in, + Data_In(6) => Port6_pulse_in, + Data_In(7) => Port7_pulse_in, + Data_In(8) => Port8_pulse_in, + Data_In(9) => Port9_pulse_in, + Data_In(10) => Port10_pulse_in, + Data_In(11) => Port11_pulse_in, + Data_In(12) => Port12_pulse_in, + Data_In(13) => Port13_pulse_in, + Data_In(14) => Port14_pulse_in, + Data_In(15) => Port15_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out, + Data_out(3) => Port3_pulse_out, + Data_out(4) => Port4_pulse_out, + Data_out(5) => Port5_pulse_out, + Data_out(6) => Port6_pulse_out, + Data_out(7) => Port7_pulse_out, + Data_out(8) => Port8_pulse_out, + Data_out(9) => Port9_pulse_out, + Data_out(10) => Port10_pulse_out, + Data_out(11) => Port11_pulse_out, + Data_out(12) => Port12_pulse_out, + Data_out(13) => Port13_pulse_out, + Data_out(14) => Port14_pulse_out, + Data_out(15) => Port15_pulse_out + + ); +end generate crossbar15x15; + + +--======================crossbar 16 ports======================= + +crossbar16x16 : if number_of_crossbar_ports = 16 generate + +-- crossbit du bit 0 de donnée + + Data0_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 16) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(0), + Data_In(2) => Port2_in(0), + Data_In(3) => Port3_in(0), + Data_In(4) => Port4_in(0), + Data_In(5) => Port5_in(0), + Data_In(6) => Port6_in(0), + Data_In(7) => Port7_in(0), + Data_In(8) => Port8_in(0), + Data_In(9) => Port9_in(0), + Data_In(10) => Port10_in(0), + Data_In(11) => Port11_in(0), + Data_In(12) => Port12_in(0), + Data_In(13) => Port13_in(0), + Data_In(14) => Port14_in(0), + Data_In(15) => Port15_in(0), + Data_In(16) => Port16_in(0), + Data_out(1)=> Port1_out(0), + Data_out(2)=> Port2_out(0), + Data_out(3)=> Port3_out(0), + Data_out(4)=> Port4_out(0), + Data_out(5)=> Port5_out(0), + Data_out(6)=> Port6_out(0), + Data_out(7)=> Port7_out(0), + Data_out(8)=> Port8_out(0), + Data_out(9)=> Port9_out(0), + Data_out(10)=> Port10_out(0), + Data_out(11)=> Port11_out(0), + Data_out(12)=> Port12_out(0), + Data_out(13)=> Port13_out(0), + Data_out(14)=> Port14_out(0), + Data_out(15)=> Port15_out(0), + Data_out(16)=> Port16_out(0) + + ); +-- crossbit du bit 1 de donnée + + Data1_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 16) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(1), + Data_In(2) => Port2_in(1), + Data_In(3) => Port3_in(1), + Data_In(4) => Port4_in(1), + Data_In(5) => Port5_in(1), + Data_In(6) => Port6_in(1), + Data_In(7) => Port7_in(1), + Data_In(8) => Port8_in(1), + Data_In(9) => Port9_in(1), + Data_In(10) => Port10_in(1), + Data_In(11) => Port11_in(1), + Data_In(12) => Port12_in(1), + Data_In(13) => Port13_in(1), + Data_In(14) => Port14_in(1), + Data_In(15) => Port15_in(1), + Data_In(16) => Port16_in(1), + Data_out(1)=> Port1_out(1), + Data_out(2)=> Port2_out(1), + Data_out(3)=> Port3_out(1), + Data_out(4)=> Port4_out(1), + Data_out(5)=> Port5_out(1), + Data_out(6)=> Port6_out(1), + Data_out(7)=> Port7_out(1), + Data_out(8)=> Port8_out(1), + Data_out(9)=> Port9_out(1), + Data_out(10)=> Port10_out(1), + Data_out(11)=> Port11_out(1), + Data_out(12)=> Port12_out(1), + Data_out(13)=> Port13_out(1), + Data_out(14)=> Port14_out(1), + Data_out(15)=> Port15_out(1), + Data_out(16)=> Port16_out(1) + + ); +-- crossbit du bit 2 de donnée + + Data2_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 16) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(2), + Data_In(2) => Port2_in(2), + Data_In(3) => Port3_in(2), + Data_In(4) => Port4_in(2), + Data_In(5) => Port5_in(2), + Data_In(6) => Port6_in(2), + Data_In(7) => Port7_in(2), + Data_In(8) => Port8_in(2), + Data_In(9) => Port9_in(2), + Data_In(10) => Port10_in(2), + Data_In(11) => Port11_in(2), + Data_In(12) => Port12_in(2), + Data_In(13) => Port13_in(2), + Data_In(14) => Port14_in(2), + Data_In(15) => Port15_in(2), + Data_In(16) => Port16_in(2), + Data_out(1)=> Port1_out(2), + Data_out(2)=> Port2_out(2), + Data_out(3)=> Port3_out(2), + Data_out(4)=> Port4_out(2), + Data_out(5)=> Port5_out(2), + Data_out(6)=> Port6_out(2), + Data_out(7)=> Port7_out(2), + Data_out(8)=> Port8_out(2), + Data_out(9)=> Port9_out(2), + Data_out(10)=> Port10_out(2), + Data_out(11)=> Port11_out(2), + Data_out(12)=> Port12_out(2), + Data_out(13)=> Port13_out(2), + Data_out(14)=> Port14_out(2), + Data_out(15)=> Port15_out(2), + Data_out(16)=> Port16_out(2) + + ); +-- crossbit du bit 3 de donnée + + Data3_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 16) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(3), + Data_In(2) => Port2_in(3), + Data_In(3) => Port3_in(3), + Data_In(4) => Port4_in(3), + Data_In(5) => Port5_in(3), + Data_In(6) => Port6_in(3), + Data_In(7) => Port7_in(3), + Data_In(8) => Port8_in(3), + Data_In(9) => Port9_in(3), + Data_In(10) => Port10_in(3), + Data_In(11) => Port11_in(3), + Data_In(12) => Port12_in(3), + Data_In(13) => Port13_in(3), + Data_In(14) => Port14_in(3), + Data_In(15) => Port15_in(3), + Data_In(16) => Port16_in(3), + Data_out(1)=> Port1_out(3), + Data_out(2)=> Port2_out(3), + Data_out(3)=> Port3_out(3), + Data_out(4)=> Port4_out(3), + Data_out(5)=> Port5_out(3), + Data_out(6)=> Port6_out(3), + Data_out(7)=> Port7_out(3), + Data_out(8)=> Port8_out(3), + Data_out(9)=> Port9_out(3), + Data_out(10)=> Port10_out(3), + Data_out(11)=> Port11_out(3), + Data_out(12)=> Port12_out(3), + Data_out(13)=> Port13_out(3), + Data_out(14)=> Port14_out(3), + Data_out(15)=> Port15_out(3), + Data_out(16)=> Port16_out(3) + + ); +-- crossbit du bit 4 de donnée + + Data4_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 16) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(4), + Data_In(2) => Port2_in(4), + Data_In(3) => Port3_in(4), + Data_In(4) => Port4_in(4), + Data_In(5) => Port5_in(4), + Data_In(6) => Port6_in(4), + Data_In(7) => Port7_in(4), + Data_In(8) => Port8_in(4), + Data_In(9) => Port9_in(4), + Data_In(10) => Port10_in(4), + Data_In(11) => Port11_in(4), + Data_In(12) => Port12_in(4), + Data_In(13) => Port13_in(4), + Data_In(14) => Port14_in(4), + Data_In(15) => Port15_in(4), + Data_In(16) => Port16_in(4), + Data_out(1)=> Port1_out(4), + Data_out(2)=> Port2_out(4), + Data_out(3)=> Port3_out(4), + Data_out(4)=> Port4_out(4), + Data_out(5)=> Port5_out(4), + Data_out(6)=> Port6_out(4), + Data_out(7)=> Port7_out(4), + Data_out(8)=> Port8_out(4), + Data_out(9)=> Port9_out(4), + Data_out(10)=> Port10_out(4), + Data_out(11)=> Port11_out(4), + Data_out(12)=> Port12_out(4), + Data_out(13)=> Port13_out(4), + Data_out(14)=> Port14_out(4), + Data_out(15)=> Port15_out(4), + Data_out(16)=> Port16_out(4) + + ); +-- crossbit du bit 5 de donnée + + Data5_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 16) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(5), + Data_In(2) => Port2_in(5), + Data_In(3) => Port3_in(5), + Data_In(4) => Port4_in(5), + Data_In(5) => Port5_in(5), + Data_In(6) => Port6_in(5), + Data_In(7) => Port7_in(5), + Data_In(8) => Port8_in(5), + Data_In(9) => Port9_in(5), + Data_In(10) => Port10_in(5), + Data_In(11) => Port11_in(5), + Data_In(12) => Port12_in(5), + Data_In(13) => Port13_in(5), + Data_In(14) => Port14_in(5), + Data_In(15) => Port15_in(5), + Data_In(16) => Port16_in(5), + Data_out(1)=> Port1_out(5), + Data_out(2)=> Port2_out(5), + Data_out(3)=> Port3_out(5), + Data_out(4)=> Port4_out(5), + Data_out(5)=> Port5_out(5), + Data_out(6)=> Port6_out(5), + Data_out(7)=> Port7_out(5), + Data_out(8)=> Port8_out(5), + Data_out(9)=> Port9_out(5), + Data_out(10)=> Port10_out(5), + Data_out(11)=> Port11_out(5), + Data_out(12)=> Port12_out(5), + Data_out(13)=> Port13_out(5), + Data_out(14)=> Port14_out(5), + Data_out(15)=> Port15_out(5), + Data_out(16)=> Port16_out(5) + + ); +-- crossbit du bit 6 de donnée + + Data6_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 16) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(6), + Data_In(2) => Port2_in(6), + Data_In(3) => Port3_in(6), + Data_In(4) => Port4_in(6), + Data_In(5) => Port5_in(6), + Data_In(6) => Port6_in(6), + Data_In(7) => Port7_in(6), + Data_In(8) => Port8_in(6), + Data_In(9) => Port9_in(6), + Data_In(10) => Port10_in(6), + Data_In(11) => Port11_in(6), + Data_In(12) => Port12_in(6), + Data_In(13) => Port13_in(6), + Data_In(14) => Port14_in(6), + Data_In(15) => Port15_in(6), + Data_In(16) => Port16_in(6), + Data_out(1)=> Port1_out(6), + Data_out(2)=> Port2_out(6), + Data_out(3)=> Port3_out(6), + Data_out(4)=> Port4_out(6), + Data_out(5)=> Port5_out(6), + Data_out(6)=> Port6_out(6), + Data_out(7)=> Port7_out(6), + Data_out(8)=> Port8_out(6), + Data_out(9)=> Port9_out(6), + Data_out(10)=> Port10_out(6), + Data_out(11)=> Port11_out(6), + Data_out(12)=> Port12_out(6), + Data_out(13)=> Port13_out(6), + Data_out(14)=> Port14_out(6), + Data_out(15)=> Port15_out(6), + Data_out(16)=> Port16_out(6) + + ); +-- crossbit du bit 7 de donnée + + Data7_Crossbit: Crossbit + GENERIC MAP(number_of_ports => 16) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_in(7), + Data_In(2) => Port2_in(7), + Data_In(3) => Port3_in(7), + Data_In(4) => Port4_in(7), + Data_In(5) => Port5_in(7), + Data_In(6) => Port6_in(7), + Data_In(7) => Port7_in(7), + Data_In(8) => Port8_in(7), + Data_In(9) => Port9_in(7), + Data_In(10) => Port10_in(7), + Data_In(11) => Port11_in(7), + Data_In(12) => Port12_in(7), + Data_In(13) => Port13_in(7), + Data_In(14) => Port14_in(7), + Data_In(15) => Port15_in(7), + Data_In(16) => Port16_in(7), + Data_out(1)=> Port1_out(7), + Data_out(2)=> Port2_out(7), + Data_out(3)=> Port3_out(7), + Data_out(4)=> Port4_out(7), + Data_out(5)=> Port5_out(7), + Data_out(6)=> Port6_out(7), + Data_out(7)=> Port7_out(7), + Data_out(8)=> Port8_out(7), + Data_out(9)=> Port9_out(7), + Data_out(10)=> Port10_out(7), + Data_out(11)=> Port11_out(7), + Data_out(12)=> Port12_out(7), + Data_out(13)=> Port13_out(7), + Data_out(14)=> Port14_out(7), + Data_out(15)=> Port15_out(7), + Data_out(16)=> Port16_out(7) + + ); +-- crossbit du pulse_out 16 ports + + Pulse_out_Crossbit16: Crossbit + GENERIC MAP(number_of_ports => 16) + PORT MAP( + + reset => reset, + clk=>clk, + Control => Ctrl_buf, + Data_In(1) => Port1_pulse_in, + Data_In(2) => Port2_pulse_in, + Data_In(3) => Port3_pulse_in, + Data_In(4) => Port4_pulse_in, + Data_In(5) => Port5_pulse_in, + Data_In(6) => Port6_pulse_in, + Data_In(7) => Port7_pulse_in, + Data_In(8) => Port8_pulse_in, + Data_In(9) => Port9_pulse_in, + Data_In(10) => Port10_pulse_in, + Data_In(11) => Port11_pulse_in, + Data_In(12) => Port12_pulse_in, + Data_In(13) => Port13_pulse_in, + Data_In(14) => Port14_pulse_in, + Data_In(15) => Port15_pulse_in, + Data_In(16) => Port16_pulse_in, + Data_out(1) => Port1_pulse_out, + Data_out(2) => Port2_pulse_out, + Data_out(3) => Port3_pulse_out, + Data_out(4) => Port4_pulse_out, + Data_out(5) => Port5_pulse_out, + Data_out(6) => Port6_pulse_out, + Data_out(7) => Port7_pulse_out, + Data_out(8) => Port8_pulse_out, + Data_out(9) => Port9_pulse_out, + Data_out(10) => Port10_pulse_out, + Data_out(11) => Port11_pulse_out, + Data_out(12) => Port12_pulse_out, + Data_out(13) => Port13_pulse_out, + Data_out(14) => Port14_pulse_out, + Data_out(15) => Port15_pulse_out, + Data_out(16) => Port16_pulse_out + + ); +end generate crossbar16x16; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Crossbit.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Crossbit.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Crossbit.vhd (revision 138) @@ -0,0 +1,300 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: Kiegaing Emmanuel /GAMOM Roland Christian +-- +-- Create Date: 01:47 05/06/2011 +-- Design Name: +-- Module Name: Crossbar - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: module implémentant un crosbar d'un bit +-- ces modules seront instanciés pour faire le switch +-- module generique +-- Dependencies: +-- +-- Revision: 11-01-2013 +-- AJOUT DU CLK pour créer un pipeline dans l'architecture. +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Crossbit is + generic + ( + number_of_ports: positive := 4 + ); + Port ( clk,reset : in std_logic; + Control : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1); + Data_In : in STD_LOGIC_VECTOR (number_of_ports downto 1); + Data_out : out STD_LOGIC_VECTOR (number_of_ports downto 1) + + ); +end Crossbit; + +architecture Behavioral of Crossbit is +signal dout :STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'0'); +begin +-- element de commutation utilisee dans la matrice interconnecte +-- le circuit genere depend du parametre generique nombre de ports +--======================crossbit 2 ports======================= + +crossbit2x2 : if number_of_ports = 2 generate + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(3))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(4))); +end generate crossbit2x2; + + +--======================crossbit 3 ports======================= + +crossbit3x3 : if number_of_ports = 3 generate + + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(4)) OR (Data_in(3) And Control(7))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(5)) OR (Data_in(3) And Control(8))); + Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(9))); +end generate crossbit3x3; + + +--======================crossbit 4 ports======================= + +crossbit4x4 : if number_of_ports = 4 generate + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(5)) OR (Data_in(3) And Control(9)) OR (Data_in(4) And Control(13))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(10)) OR (Data_in(4) And Control(14))); + Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(11)) OR (Data_in(4) And Control(15))); + Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(12)) OR (Data_in(4) And Control(16))); +end generate crossbit4x4; + + +--======================crossbit 5 ports======================= + +crossbit5x5 : if number_of_ports = 5 generate + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(11)) OR (Data_in(4) And Control(16)) OR (Data_in(5) And Control(21))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(12)) OR (Data_in(4) And Control(17)) OR (Data_in(5) And Control(22))); + Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(13)) OR (Data_in(4) And Control(18)) OR (Data_in(5) And Control(23))); + Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(14)) OR (Data_in(4) And Control(19)) OR (Data_in(5) And Control(24))); + Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(20)) OR (Data_in(5) And Control(25))); +end generate crossbit5x5; + + +--======================crossbit 6 ports======================= + +crossbit6x6 : if number_of_ports = 6 generate + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(13)) OR (Data_in(4) And Control(19)) OR (Data_in(5) And Control(25)) OR (Data_in(6) And Control(31))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(14)) OR (Data_in(4) And Control(20)) OR (Data_in(5) And Control(26)) OR (Data_in(6) And Control(32))); + Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(21)) OR (Data_in(5) And Control(27)) OR (Data_in(6) And Control(33))); + Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(16)) OR (Data_in(4) And Control(22)) OR (Data_in(5) And Control(28)) OR (Data_in(6) And Control(34))); + Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(23)) OR (Data_in(5) And Control(29)) OR (Data_in(6) And Control(35))); + Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(24)) OR (Data_in(5) And Control(30)) OR (Data_in(6) And Control(36))); +end generate crossbit6x6; + + +--======================crossbit 7 ports======================= + +crossbit7x7 : if number_of_ports = 7 generate + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(22)) OR (Data_in(5) And Control(29)) OR (Data_in(6) And Control(36)) OR (Data_in(7) And Control(43))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(16)) OR (Data_in(4) And Control(23)) OR (Data_in(5) And Control(30)) OR (Data_in(6) And Control(37)) OR (Data_in(7) And Control(44))); + Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(24)) OR (Data_in(5) And Control(31)) OR (Data_in(6) And Control(38)) OR (Data_in(7) And Control(45))); + Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(25)) OR (Data_in(5) And Control(32)) OR (Data_in(6) And Control(39)) OR (Data_in(7) And Control(46))); + Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(26)) OR (Data_in(5) And Control(33)) OR (Data_in(6) And Control(40)) OR (Data_in(7) And Control(47))); + Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(27)) OR (Data_in(5) And Control(34)) OR (Data_in(6) And Control(41)) OR (Data_in(7) And Control(48))); + Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(35)) OR (Data_in(6) And Control(42)) OR (Data_in(7) And Control(49))); +end generate crossbit7x7; + + +--======================crossbit 8 ports======================= + +crossbit8x8 : if number_of_ports = 8 generate + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(25)) OR (Data_in(5) And Control(33)) OR (Data_in(6) And Control(41)) OR (Data_in(7) And Control(49)) OR (Data_in(8) And Control(57))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(26)) OR (Data_in(5) And Control(34)) OR (Data_in(6) And Control(42)) OR (Data_in(7) And Control(50)) OR (Data_in(8) And Control(58))); + Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(27)) OR (Data_in(5) And Control(35)) OR (Data_in(6) And Control(43)) OR (Data_in(7) And Control(51)) OR (Data_in(8) And Control(59))); + Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(36)) OR (Data_in(6) And Control(44)) OR (Data_in(7) And Control(52)) OR (Data_in(8) And Control(60))); + Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(29)) OR (Data_in(5) And Control(37)) OR (Data_in(6) And Control(45)) OR (Data_in(7) And Control(53)) OR (Data_in(8) And Control(61))); + Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(30)) OR (Data_in(5) And Control(38)) OR (Data_in(6) And Control(46)) OR (Data_in(7) And Control(54)) OR (Data_in(8) And Control(62))); + Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(39)) OR (Data_in(6) And Control(47)) OR (Data_in(7) And Control(55)) OR (Data_in(8) And Control(63))); + Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(40)) OR (Data_in(6) And Control(48)) OR (Data_in(7) And Control(56)) OR (Data_in(8) And Control(64))); +end generate crossbit8x8; + + +--======================crossbit 9 ports======================= + +crossbit9x9 : if number_of_ports = 9 generate + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(37)) OR (Data_in(6) And Control(46)) OR (Data_in(7) And Control(55)) OR (Data_in(8) And Control(64)) OR (Data_in(9) And Control(73))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(29)) OR (Data_in(5) And Control(38)) OR (Data_in(6) And Control(47)) OR (Data_in(7) And Control(56)) OR (Data_in(8) And Control(65)) OR (Data_in(9) And Control(74))); + Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(30)) OR (Data_in(5) And Control(39)) OR (Data_in(6) And Control(48)) OR (Data_in(7) And Control(57)) OR (Data_in(8) And Control(66)) OR (Data_in(9) And Control(75))); + Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(40)) OR (Data_in(6) And Control(49)) OR (Data_in(7) And Control(58)) OR (Data_in(8) And Control(67)) OR (Data_in(9) And Control(76))); + Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(41)) OR (Data_in(6) And Control(50)) OR (Data_in(7) And Control(59)) OR (Data_in(8) And Control(68)) OR (Data_in(9) And Control(77))); + Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(33)) OR (Data_in(5) And Control(42)) OR (Data_in(6) And Control(51)) OR (Data_in(7) And Control(60)) OR (Data_in(8) And Control(69)) OR (Data_in(9) And Control(78))); + Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(43)) OR (Data_in(6) And Control(52)) OR (Data_in(7) And Control(61)) OR (Data_in(8) And Control(70)) OR (Data_in(9) And Control(79))); + Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(44)) OR (Data_in(6) And Control(53)) OR (Data_in(7) And Control(62)) OR (Data_in(8) And Control(71)) OR (Data_in(9) And Control(80))); + Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(54)) OR (Data_in(7) And Control(63)) OR (Data_in(8) And Control(72)) OR (Data_in(9) And Control(81))); +end generate crossbit9x9; + + +--======================crossbit 10 ports======================= + +crossbit10x10 : if number_of_ports = 10 generate + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(41)) OR (Data_in(6) And Control(51)) OR (Data_in(7) And Control(61)) OR (Data_in(8) And Control(71)) OR (Data_in(9) And Control(81)) OR (Data_in(10) And Control(91))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(42)) OR (Data_in(6) And Control(52)) OR (Data_in(7) And Control(62)) OR (Data_in(8) And Control(72)) OR (Data_in(9) And Control(82)) OR (Data_in(10) And Control(92))); + Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(33)) OR (Data_in(5) And Control(43)) OR (Data_in(6) And Control(53)) OR (Data_in(7) And Control(63)) OR (Data_in(8) And Control(73)) OR (Data_in(9) And Control(83)) OR (Data_in(10) And Control(93))); + Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(44)) OR (Data_in(6) And Control(54)) OR (Data_in(7) And Control(64)) OR (Data_in(8) And Control(74)) OR (Data_in(9) And Control(84)) OR (Data_in(10) And Control(94))); + Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(55)) OR (Data_in(7) And Control(65)) OR (Data_in(8) And Control(75)) OR (Data_in(9) And Control(85)) OR (Data_in(10) And Control(95))); + Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(46)) OR (Data_in(6) And Control(56)) OR (Data_in(7) And Control(66)) OR (Data_in(8) And Control(76)) OR (Data_in(9) And Control(86)) OR (Data_in(10) And Control(96))); + Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(47)) OR (Data_in(6) And Control(57)) OR (Data_in(7) And Control(67)) OR (Data_in(8) And Control(77)) OR (Data_in(9) And Control(87)) OR (Data_in(10) And Control(97))); + Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(48)) OR (Data_in(6) And Control(58)) OR (Data_in(7) And Control(68)) OR (Data_in(8) And Control(78)) OR (Data_in(9) And Control(88)) OR (Data_in(10) And Control(98))); + Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(59)) OR (Data_in(7) And Control(69)) OR (Data_in(8) And Control(79)) OR (Data_in(9) And Control(89)) OR (Data_in(10) And Control(99))); + Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(60)) OR (Data_in(7) And Control(70)) OR (Data_in(8) And Control(80)) OR (Data_in(9) And Control(90)) OR (Data_in(10) And Control(100))); +end generate crossbit10x10; + + +--======================crossbit 11 ports======================= + +crossbit11x11 : if number_of_ports = 11 generate + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(56)) OR (Data_in(7) And Control(67)) OR (Data_in(8) And Control(78)) OR (Data_in(9) And Control(89)) OR (Data_in(10) And Control(100)) OR (Data_in(11) And Control(111))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(46)) OR (Data_in(6) And Control(57)) OR (Data_in(7) And Control(68)) OR (Data_in(8) And Control(79)) OR (Data_in(9) And Control(90)) OR (Data_in(10) And Control(101)) OR (Data_in(11) And Control(112))); + Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(47)) OR (Data_in(6) And Control(58)) OR (Data_in(7) And Control(69)) OR (Data_in(8) And Control(80)) OR (Data_in(9) And Control(91)) OR (Data_in(10) And Control(102)) OR (Data_in(11) And Control(113))); + Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(48)) OR (Data_in(6) And Control(59)) OR (Data_in(7) And Control(70)) OR (Data_in(8) And Control(81)) OR (Data_in(9) And Control(92)) OR (Data_in(10) And Control(103)) OR (Data_in(11) And Control(114))); + Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(60)) OR (Data_in(7) And Control(71)) OR (Data_in(8) And Control(82)) OR (Data_in(9) And Control(93)) OR (Data_in(10) And Control(104)) OR (Data_in(11) And Control(115))); + Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(61)) OR (Data_in(7) And Control(72)) OR (Data_in(8) And Control(83)) OR (Data_in(9) And Control(94)) OR (Data_in(10) And Control(105)) OR (Data_in(11) And Control(116))); + Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(51)) OR (Data_in(6) And Control(62)) OR (Data_in(7) And Control(73)) OR (Data_in(8) And Control(84)) OR (Data_in(9) And Control(95)) OR (Data_in(10) And Control(106)) OR (Data_in(11) And Control(117))); + Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(52)) OR (Data_in(6) And Control(63)) OR (Data_in(7) And Control(74)) OR (Data_in(8) And Control(85)) OR (Data_in(9) And Control(96)) OR (Data_in(10) And Control(107)) OR (Data_in(11) And Control(118))); + Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(64)) OR (Data_in(7) And Control(75)) OR (Data_in(8) And Control(86)) OR (Data_in(9) And Control(97)) OR (Data_in(10) And Control(108)) OR (Data_in(11) And Control(119))); + Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(65)) OR (Data_in(7) And Control(76)) OR (Data_in(8) And Control(87)) OR (Data_in(9) And Control(98)) OR (Data_in(10) And Control(109)) OR (Data_in(11) And Control(120))); + Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(77)) OR (Data_in(8) And Control(88)) OR (Data_in(9) And Control(99)) OR (Data_in(10) And Control(110)) OR (Data_in(11) And Control(121))); +end generate crossbit11x11; + + +--======================crossbit 12 ports======================= + +crossbit12x12 : if number_of_ports = 12 generate + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(61)) OR (Data_in(7) And Control(73)) OR (Data_in(8) And Control(85)) OR (Data_in(9) And Control(97)) OR (Data_in(10) And Control(109)) OR (Data_in(11) And Control(121)) OR (Data_in(12) And Control(133))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(62)) OR (Data_in(7) And Control(74)) OR (Data_in(8) And Control(86)) OR (Data_in(9) And Control(98)) OR (Data_in(10) And Control(110)) OR (Data_in(11) And Control(122)) OR (Data_in(12) And Control(134))); + Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(51)) OR (Data_in(6) And Control(63)) OR (Data_in(7) And Control(75)) OR (Data_in(8) And Control(87)) OR (Data_in(9) And Control(99)) OR (Data_in(10) And Control(111)) OR (Data_in(11) And Control(123)) OR (Data_in(12) And Control(135))); + Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(52)) OR (Data_in(6) And Control(64)) OR (Data_in(7) And Control(76)) OR (Data_in(8) And Control(88)) OR (Data_in(9) And Control(100)) OR (Data_in(10) And Control(112)) OR (Data_in(11) And Control(124)) OR (Data_in(12) And Control(136))); + Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(65)) OR (Data_in(7) And Control(77)) OR (Data_in(8) And Control(89)) OR (Data_in(9) And Control(101)) OR (Data_in(10) And Control(113)) OR (Data_in(11) And Control(125)) OR (Data_in(12) And Control(137))); + Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(78)) OR (Data_in(8) And Control(90)) OR (Data_in(9) And Control(102)) OR (Data_in(10) And Control(114)) OR (Data_in(11) And Control(126)) OR (Data_in(12) And Control(138))); + Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(67)) OR (Data_in(7) And Control(79)) OR (Data_in(8) And Control(91)) OR (Data_in(9) And Control(103)) OR (Data_in(10) And Control(115)) OR (Data_in(11) And Control(127)) OR (Data_in(12) And Control(139))); + Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(56)) OR (Data_in(6) And Control(68)) OR (Data_in(7) And Control(80)) OR (Data_in(8) And Control(92)) OR (Data_in(9) And Control(104)) OR (Data_in(10) And Control(116)) OR (Data_in(11) And Control(128)) OR (Data_in(12) And Control(140))); + Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(69)) OR (Data_in(7) And Control(81)) OR (Data_in(8) And Control(93)) OR (Data_in(9) And Control(105)) OR (Data_in(10) And Control(117)) OR (Data_in(11) And Control(129)) OR (Data_in(12) And Control(141))); + Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(70)) OR (Data_in(7) And Control(82)) OR (Data_in(8) And Control(94)) OR (Data_in(9) And Control(106)) OR (Data_in(10) And Control(118)) OR (Data_in(11) And Control(130)) OR (Data_in(12) And Control(142))); + Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(83)) OR (Data_in(8) And Control(95)) OR (Data_in(9) And Control(107)) OR (Data_in(10) And Control(119)) OR (Data_in(11) And Control(131)) OR (Data_in(12) And Control(143))); + Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(84)) OR (Data_in(8) And Control(96)) OR (Data_in(9) And Control(108)) OR (Data_in(10) And Control(120)) OR (Data_in(11) And Control(132)) OR (Data_in(12) And Control(144))); +end generate crossbit12x12; + + +--======================crossbit 13 ports======================= + +crossbit13x13 : if number_of_ports = 13 generate + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(79)) OR (Data_in(8) And Control(92)) OR (Data_in(9) And Control(105)) OR (Data_in(10) And Control(118)) OR (Data_in(11) And Control(131)) OR (Data_in(12) And Control(144)) OR (Data_in(13) And Control(157))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(67)) OR (Data_in(7) And Control(80)) OR (Data_in(8) And Control(93)) OR (Data_in(9) And Control(106)) OR (Data_in(10) And Control(119)) OR (Data_in(11) And Control(132)) OR (Data_in(12) And Control(145)) OR (Data_in(13) And Control(158))); + Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(68)) OR (Data_in(7) And Control(81)) OR (Data_in(8) And Control(94)) OR (Data_in(9) And Control(107)) OR (Data_in(10) And Control(120)) OR (Data_in(11) And Control(133)) OR (Data_in(12) And Control(146)) OR (Data_in(13) And Control(159))); + Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(56)) OR (Data_in(6) And Control(69)) OR (Data_in(7) And Control(82)) OR (Data_in(8) And Control(95)) OR (Data_in(9) And Control(108)) OR (Data_in(10) And Control(121)) OR (Data_in(11) And Control(134)) OR (Data_in(12) And Control(147)) OR (Data_in(13) And Control(160))); + Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(70)) OR (Data_in(7) And Control(83)) OR (Data_in(8) And Control(96)) OR (Data_in(9) And Control(109)) OR (Data_in(10) And Control(122)) OR (Data_in(11) And Control(135)) OR (Data_in(12) And Control(148)) OR (Data_in(13) And Control(161))); + Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(84)) OR (Data_in(8) And Control(97)) OR (Data_in(9) And Control(110)) OR (Data_in(10) And Control(123)) OR (Data_in(11) And Control(136)) OR (Data_in(12) And Control(149)) OR (Data_in(13) And Control(162))); + Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(85)) OR (Data_in(8) And Control(98)) OR (Data_in(9) And Control(111)) OR (Data_in(10) And Control(124)) OR (Data_in(11) And Control(137)) OR (Data_in(12) And Control(150)) OR (Data_in(13) And Control(163))); + Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(73)) OR (Data_in(7) And Control(86)) OR (Data_in(8) And Control(99)) OR (Data_in(9) And Control(112)) OR (Data_in(10) And Control(125)) OR (Data_in(11) And Control(138)) OR (Data_in(12) And Control(151)) OR (Data_in(13) And Control(164))); + Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(74)) OR (Data_in(7) And Control(87)) OR (Data_in(8) And Control(100)) OR (Data_in(9) And Control(113)) OR (Data_in(10) And Control(126)) OR (Data_in(11) And Control(139)) OR (Data_in(12) And Control(152)) OR (Data_in(13) And Control(165))); + Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(75)) OR (Data_in(7) And Control(88)) OR (Data_in(8) And Control(101)) OR (Data_in(9) And Control(114)) OR (Data_in(10) And Control(127)) OR (Data_in(11) And Control(140)) OR (Data_in(12) And Control(153)) OR (Data_in(13) And Control(166))); + Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(89)) OR (Data_in(8) And Control(102)) OR (Data_in(9) And Control(115)) OR (Data_in(10) And Control(128)) OR (Data_in(11) And Control(141)) OR (Data_in(12) And Control(154)) OR (Data_in(13) And Control(167))); + Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(90)) OR (Data_in(8) And Control(103)) OR (Data_in(9) And Control(116)) OR (Data_in(10) And Control(129)) OR (Data_in(11) And Control(142)) OR (Data_in(12) And Control(155)) OR (Data_in(13) And Control(168))); + Dout(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(104)) OR (Data_in(9) And Control(117)) OR (Data_in(10) And Control(130)) OR (Data_in(11) And Control(143)) OR (Data_in(12) And Control(156)) OR (Data_in(13) And Control(169))); +end generate crossbit13x13; + + +--======================crossbit 14 ports======================= + +crossbit14x14 : if number_of_ports = 14 generate + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(85)) OR (Data_in(8) And Control(99)) OR (Data_in(9) And Control(113)) OR (Data_in(10) And Control(127)) OR (Data_in(11) And Control(141)) OR (Data_in(12) And Control(155)) OR (Data_in(13) And Control(169)) OR (Data_in(14) And Control(183))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(86)) OR (Data_in(8) And Control(100)) OR (Data_in(9) And Control(114)) OR (Data_in(10) And Control(128)) OR (Data_in(11) And Control(142)) OR (Data_in(12) And Control(156)) OR (Data_in(13) And Control(170)) OR (Data_in(14) And Control(184))); + Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(73)) OR (Data_in(7) And Control(87)) OR (Data_in(8) And Control(101)) OR (Data_in(9) And Control(115)) OR (Data_in(10) And Control(129)) OR (Data_in(11) And Control(143)) OR (Data_in(12) And Control(157)) OR (Data_in(13) And Control(171)) OR (Data_in(14) And Control(185))); + Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(74)) OR (Data_in(7) And Control(88)) OR (Data_in(8) And Control(102)) OR (Data_in(9) And Control(116)) OR (Data_in(10) And Control(130)) OR (Data_in(11) And Control(144)) OR (Data_in(12) And Control(158)) OR (Data_in(13) And Control(172)) OR (Data_in(14) And Control(186))); + Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(75)) OR (Data_in(7) And Control(89)) OR (Data_in(8) And Control(103)) OR (Data_in(9) And Control(117)) OR (Data_in(10) And Control(131)) OR (Data_in(11) And Control(145)) OR (Data_in(12) And Control(159)) OR (Data_in(13) And Control(173)) OR (Data_in(14) And Control(187))); + Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(90)) OR (Data_in(8) And Control(104)) OR (Data_in(9) And Control(118)) OR (Data_in(10) And Control(132)) OR (Data_in(11) And Control(146)) OR (Data_in(12) And Control(160)) OR (Data_in(13) And Control(174)) OR (Data_in(14) And Control(188))); + Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(105)) OR (Data_in(9) And Control(119)) OR (Data_in(10) And Control(133)) OR (Data_in(11) And Control(147)) OR (Data_in(12) And Control(161)) OR (Data_in(13) And Control(175)) OR (Data_in(14) And Control(189))); + Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(92)) OR (Data_in(8) And Control(106)) OR (Data_in(9) And Control(120)) OR (Data_in(10) And Control(134)) OR (Data_in(11) And Control(148)) OR (Data_in(12) And Control(162)) OR (Data_in(13) And Control(176)) OR (Data_in(14) And Control(190))); + Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(79)) OR (Data_in(7) And Control(93)) OR (Data_in(8) And Control(107)) OR (Data_in(9) And Control(121)) OR (Data_in(10) And Control(135)) OR (Data_in(11) And Control(149)) OR (Data_in(12) And Control(163)) OR (Data_in(13) And Control(177)) OR (Data_in(14) And Control(191))); + Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(80)) OR (Data_in(7) And Control(94)) OR (Data_in(8) And Control(108)) OR (Data_in(9) And Control(122)) OR (Data_in(10) And Control(136)) OR (Data_in(11) And Control(150)) OR (Data_in(12) And Control(164)) OR (Data_in(13) And Control(178)) OR (Data_in(14) And Control(192))); + Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(95)) OR (Data_in(8) And Control(109)) OR (Data_in(9) And Control(123)) OR (Data_in(10) And Control(137)) OR (Data_in(11) And Control(151)) OR (Data_in(12) And Control(165)) OR (Data_in(13) And Control(179)) OR (Data_in(14) And Control(193))); + Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(96)) OR (Data_in(8) And Control(110)) OR (Data_in(9) And Control(124)) OR (Data_in(10) And Control(138)) OR (Data_in(11) And Control(152)) OR (Data_in(12) And Control(166)) OR (Data_in(13) And Control(180)) OR (Data_in(14) And Control(194))); + Dout(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(111)) OR (Data_in(9) And Control(125)) OR (Data_in(10) And Control(139)) OR (Data_in(11) And Control(153)) OR (Data_in(12) And Control(167)) OR (Data_in(13) And Control(181)) OR (Data_in(14) And Control(195))); + Dout(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(112)) OR (Data_in(9) And Control(126)) OR (Data_in(10) And Control(140)) OR (Data_in(11) And Control(154)) OR (Data_in(12) And Control(168)) OR (Data_in(13) And Control(182)) OR (Data_in(14) And Control(196))); +end generate crossbit14x14; + + +--======================crossbit 15 ports======================= + +crossbit15x15 : if number_of_ports = 15 generate + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(106)) OR (Data_in(9) And Control(121)) OR (Data_in(10) And Control(136)) OR (Data_in(11) And Control(151)) OR (Data_in(12) And Control(166)) OR (Data_in(13) And Control(181)) OR (Data_in(14) And Control(196)) OR (Data_in(15) And Control(211))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(92)) OR (Data_in(8) And Control(107)) OR (Data_in(9) And Control(122)) OR (Data_in(10) And Control(137)) OR (Data_in(11) And Control(152)) OR (Data_in(12) And Control(167)) OR (Data_in(13) And Control(182)) OR (Data_in(14) And Control(197)) OR (Data_in(15) And Control(212))); + Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(93)) OR (Data_in(8) And Control(108)) OR (Data_in(9) And Control(123)) OR (Data_in(10) And Control(138)) OR (Data_in(11) And Control(153)) OR (Data_in(12) And Control(168)) OR (Data_in(13) And Control(183)) OR (Data_in(14) And Control(198)) OR (Data_in(15) And Control(213))); + Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(79)) OR (Data_in(7) And Control(94)) OR (Data_in(8) And Control(109)) OR (Data_in(9) And Control(124)) OR (Data_in(10) And Control(139)) OR (Data_in(11) And Control(154)) OR (Data_in(12) And Control(169)) OR (Data_in(13) And Control(184)) OR (Data_in(14) And Control(199)) OR (Data_in(15) And Control(214))); + Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(80)) OR (Data_in(7) And Control(95)) OR (Data_in(8) And Control(110)) OR (Data_in(9) And Control(125)) OR (Data_in(10) And Control(140)) OR (Data_in(11) And Control(155)) OR (Data_in(12) And Control(170)) OR (Data_in(13) And Control(185)) OR (Data_in(14) And Control(200)) OR (Data_in(15) And Control(215))); + Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(96)) OR (Data_in(8) And Control(111)) OR (Data_in(9) And Control(126)) OR (Data_in(10) And Control(141)) OR (Data_in(11) And Control(156)) OR (Data_in(12) And Control(171)) OR (Data_in(13) And Control(186)) OR (Data_in(14) And Control(201)) OR (Data_in(15) And Control(216))); + Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(112)) OR (Data_in(9) And Control(127)) OR (Data_in(10) And Control(142)) OR (Data_in(11) And Control(157)) OR (Data_in(12) And Control(172)) OR (Data_in(13) And Control(187)) OR (Data_in(14) And Control(202)) OR (Data_in(15) And Control(217))); + Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(113)) OR (Data_in(9) And Control(128)) OR (Data_in(10) And Control(143)) OR (Data_in(11) And Control(158)) OR (Data_in(12) And Control(173)) OR (Data_in(13) And Control(188)) OR (Data_in(14) And Control(203)) OR (Data_in(15) And Control(218))); + Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(99)) OR (Data_in(8) And Control(114)) OR (Data_in(9) And Control(129)) OR (Data_in(10) And Control(144)) OR (Data_in(11) And Control(159)) OR (Data_in(12) And Control(174)) OR (Data_in(13) And Control(189)) OR (Data_in(14) And Control(204)) OR (Data_in(15) And Control(219))); + Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(85)) OR (Data_in(7) And Control(100)) OR (Data_in(8) And Control(115)) OR (Data_in(9) And Control(130)) OR (Data_in(10) And Control(145)) OR (Data_in(11) And Control(160)) OR (Data_in(12) And Control(175)) OR (Data_in(13) And Control(190)) OR (Data_in(14) And Control(205)) OR (Data_in(15) And Control(220))); + Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(71)) OR (Data_in(6) And Control(86)) OR (Data_in(7) And Control(101)) OR (Data_in(8) And Control(116)) OR (Data_in(9) And Control(131)) OR (Data_in(10) And Control(146)) OR (Data_in(11) And Control(161)) OR (Data_in(12) And Control(176)) OR (Data_in(13) And Control(191)) OR (Data_in(14) And Control(206)) OR (Data_in(15) And Control(221))); + Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(57)) OR (Data_in(5) And Control(72)) OR (Data_in(6) And Control(87)) OR (Data_in(7) And Control(102)) OR (Data_in(8) And Control(117)) OR (Data_in(9) And Control(132)) OR (Data_in(10) And Control(147)) OR (Data_in(11) And Control(162)) OR (Data_in(12) And Control(177)) OR (Data_in(13) And Control(192)) OR (Data_in(14) And Control(207)) OR (Data_in(15) And Control(222))); + Dout(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(43)) OR (Data_in(4) And Control(58)) OR (Data_in(5) And Control(73)) OR (Data_in(6) And Control(88)) OR (Data_in(7) And Control(103)) OR (Data_in(8) And Control(118)) OR (Data_in(9) And Control(133)) OR (Data_in(10) And Control(148)) OR (Data_in(11) And Control(163)) OR (Data_in(12) And Control(178)) OR (Data_in(13) And Control(193)) OR (Data_in(14) And Control(208)) OR (Data_in(15) And Control(223))); + Dout(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(29)) OR (Data_in(3) And Control(44)) OR (Data_in(4) And Control(59)) OR (Data_in(5) And Control(74)) OR (Data_in(6) And Control(89)) OR (Data_in(7) And Control(104)) OR (Data_in(8) And Control(119)) OR (Data_in(9) And Control(134)) OR (Data_in(10) And Control(149)) OR (Data_in(11) And Control(164)) OR (Data_in(12) And Control(179)) OR (Data_in(13) And Control(194)) OR (Data_in(14) And Control(209)) OR (Data_in(15) And Control(224))); + Dout(15) <= ((Data_in(1) And Control(15)) OR (Data_in(2) And Control(30)) OR (Data_in(3) And Control(45)) OR (Data_in(4) And Control(60)) OR (Data_in(5) And Control(75)) OR (Data_in(6) And Control(90)) OR (Data_in(7) And Control(105)) OR (Data_in(8) And Control(120)) OR (Data_in(9) And Control(135)) OR (Data_in(10) And Control(150)) OR (Data_in(11) And Control(165)) OR (Data_in(12) And Control(180)) OR (Data_in(13) And Control(195)) OR (Data_in(14) And Control(210)) OR (Data_in(15) And Control(225))); +end generate crossbit15x15; + + +--======================crossbit 16 ports======================= + +crossbit16x16 : if number_of_ports = 16 generate + + Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(113)) OR (Data_in(9) And Control(129)) OR (Data_in(10) And Control(145)) OR (Data_in(11) And Control(161)) OR (Data_in(12) And Control(177)) OR (Data_in(13) And Control(193)) OR (Data_in(14) And Control(209)) OR (Data_in(15) And Control(225)) OR (Data_in(16) And Control(241))); + Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(114)) OR (Data_in(9) And Control(130)) OR (Data_in(10) And Control(146)) OR (Data_in(11) And Control(162)) OR (Data_in(12) And Control(178)) OR (Data_in(13) And Control(194)) OR (Data_in(14) And Control(210)) OR (Data_in(15) And Control(226)) OR (Data_in(16) And Control(242))); + Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(99)) OR (Data_in(8) And Control(115)) OR (Data_in(9) And Control(131)) OR (Data_in(10) And Control(147)) OR (Data_in(11) And Control(163)) OR (Data_in(12) And Control(179)) OR (Data_in(13) And Control(195)) OR (Data_in(14) And Control(211)) OR (Data_in(15) And Control(227)) OR (Data_in(16) And Control(243))); + Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(100)) OR (Data_in(8) And Control(116)) OR (Data_in(9) And Control(132)) OR (Data_in(10) And Control(148)) OR (Data_in(11) And Control(164)) OR (Data_in(12) And Control(180)) OR (Data_in(13) And Control(196)) OR (Data_in(14) And Control(212)) OR (Data_in(15) And Control(228)) OR (Data_in(16) And Control(244))); + Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(85)) OR (Data_in(7) And Control(101)) OR (Data_in(8) And Control(117)) OR (Data_in(9) And Control(133)) OR (Data_in(10) And Control(149)) OR (Data_in(11) And Control(165)) OR (Data_in(12) And Control(181)) OR (Data_in(13) And Control(197)) OR (Data_in(14) And Control(213)) OR (Data_in(15) And Control(229)) OR (Data_in(16) And Control(245))); + Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(86)) OR (Data_in(7) And Control(102)) OR (Data_in(8) And Control(118)) OR (Data_in(9) And Control(134)) OR (Data_in(10) And Control(150)) OR (Data_in(11) And Control(166)) OR (Data_in(12) And Control(182)) OR (Data_in(13) And Control(198)) OR (Data_in(14) And Control(214)) OR (Data_in(15) And Control(230)) OR (Data_in(16) And Control(246))); + Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(71)) OR (Data_in(6) And Control(87)) OR (Data_in(7) And Control(103)) OR (Data_in(8) And Control(119)) OR (Data_in(9) And Control(135)) OR (Data_in(10) And Control(151)) OR (Data_in(11) And Control(167)) OR (Data_in(12) And Control(183)) OR (Data_in(13) And Control(199)) OR (Data_in(14) And Control(215)) OR (Data_in(15) And Control(231)) OR (Data_in(16) And Control(247))); + Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(72)) OR (Data_in(6) And Control(88)) OR (Data_in(7) And Control(104)) OR (Data_in(8) And Control(120)) OR (Data_in(9) And Control(136)) OR (Data_in(10) And Control(152)) OR (Data_in(11) And Control(168)) OR (Data_in(12) And Control(184)) OR (Data_in(13) And Control(200)) OR (Data_in(14) And Control(216)) OR (Data_in(15) And Control(232)) OR (Data_in(16) And Control(248))); + Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(57)) OR (Data_in(5) And Control(73)) OR (Data_in(6) And Control(89)) OR (Data_in(7) And Control(105)) OR (Data_in(8) And Control(121)) OR (Data_in(9) And Control(137)) OR (Data_in(10) And Control(153)) OR (Data_in(11) And Control(169)) OR (Data_in(12) And Control(185)) OR (Data_in(13) And Control(201)) OR (Data_in(14) And Control(217)) OR (Data_in(15) And Control(233)) OR (Data_in(16) And Control(249))); + Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(58)) OR (Data_in(5) And Control(74)) OR (Data_in(6) And Control(90)) OR (Data_in(7) And Control(106)) OR (Data_in(8) And Control(122)) OR (Data_in(9) And Control(138)) OR (Data_in(10) And Control(154)) OR (Data_in(11) And Control(170)) OR (Data_in(12) And Control(186)) OR (Data_in(13) And Control(202)) OR (Data_in(14) And Control(218)) OR (Data_in(15) And Control(234)) OR (Data_in(16) And Control(250))); + Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(43)) OR (Data_in(4) And Control(59)) OR (Data_in(5) And Control(75)) OR (Data_in(6) And Control(91)) OR (Data_in(7) And Control(107)) OR (Data_in(8) And Control(123)) OR (Data_in(9) And Control(139)) OR (Data_in(10) And Control(155)) OR (Data_in(11) And Control(171)) OR (Data_in(12) And Control(187)) OR (Data_in(13) And Control(203)) OR (Data_in(14) And Control(219)) OR (Data_in(15) And Control(235)) OR (Data_in(16) And Control(251))); + Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(44)) OR (Data_in(4) And Control(60)) OR (Data_in(5) And Control(76)) OR (Data_in(6) And Control(92)) OR (Data_in(7) And Control(108)) OR (Data_in(8) And Control(124)) OR (Data_in(9) And Control(140)) OR (Data_in(10) And Control(156)) OR (Data_in(11) And Control(172)) OR (Data_in(12) And Control(188)) OR (Data_in(13) And Control(204)) OR (Data_in(14) And Control(220)) OR (Data_in(15) And Control(236)) OR (Data_in(16) And Control(252))); + Dout(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(29)) OR (Data_in(3) And Control(45)) OR (Data_in(4) And Control(61)) OR (Data_in(5) And Control(77)) OR (Data_in(6) And Control(93)) OR (Data_in(7) And Control(109)) OR (Data_in(8) And Control(125)) OR (Data_in(9) And Control(141)) OR (Data_in(10) And Control(157)) OR (Data_in(11) And Control(173)) OR (Data_in(12) And Control(189)) OR (Data_in(13) And Control(205)) OR (Data_in(14) And Control(221)) OR (Data_in(15) And Control(237)) OR (Data_in(16) And Control(253))); + Dout(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(30)) OR (Data_in(3) And Control(46)) OR (Data_in(4) And Control(62)) OR (Data_in(5) And Control(78)) OR (Data_in(6) And Control(94)) OR (Data_in(7) And Control(110)) OR (Data_in(8) And Control(126)) OR (Data_in(9) And Control(142)) OR (Data_in(10) And Control(158)) OR (Data_in(11) And Control(174)) OR (Data_in(12) And Control(190)) OR (Data_in(13) And Control(206)) OR (Data_in(14) And Control(222)) OR (Data_in(15) And Control(238)) OR (Data_in(16) And Control(254))); + Dout(15) <= ((Data_in(1) And Control(15)) OR (Data_in(2) And Control(31)) OR (Data_in(3) And Control(47)) OR (Data_in(4) And Control(63)) OR (Data_in(5) And Control(79)) OR (Data_in(6) And Control(95)) OR (Data_in(7) And Control(111)) OR (Data_in(8) And Control(127)) OR (Data_in(9) And Control(143)) OR (Data_in(10) And Control(159)) OR (Data_in(11) And Control(175)) OR (Data_in(12) And Control(191)) OR (Data_in(13) And Control(207)) OR (Data_in(14) And Control(223)) OR (Data_in(15) And Control(239)) OR (Data_in(16) And Control(255))); + Dout(16) <= ((Data_in(1) And Control(16)) OR (Data_in(2) And Control(32)) OR (Data_in(3) And Control(48)) OR (Data_in(4) And Control(64)) OR (Data_in(5) And Control(80)) OR (Data_in(6) And Control(96)) OR (Data_in(7) And Control(112)) OR (Data_in(8) And Control(128)) OR (Data_in(9) And Control(144)) OR (Data_in(10) And Control(160)) OR (Data_in(11) And Control(176)) OR (Data_in(12) And Control(192)) OR (Data_in(13) And Control(208)) OR (Data_in(14) And Control(224)) OR (Data_in(15) And Control(240)) OR (Data_in(16) And Control(256))); +end generate crossbit16x16; +--pcrossbit:process (clk,reset) +--begin +--if rising_edge(clk) then +-- if reset='1' then +-- data_out<= (others=>'0'); +-- else + data_out<=dout; +-- end if; +--end if; +--end process pcrossbit; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Def_Request.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Def_Request.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Def_Request.vhd (revision 138) @@ -0,0 +1,95 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 17:58:09 04/07/2014 +-- Design Name: +-- Module Name: Def_Request - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Def_Request is +generic (NB_IO :positive:=4); + Port ( Req : in STD_LOGIC_VECTOR (NB_IO**2 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + fifo_full : in STD_LOGIC_VECTOR (NB_IO downto 1); + priority_rotation : in STD_LOGIC_VECTOR (NB_IO downto 1); + grant : in STD_LOGIC_VECTOR (NB_IO**2 downto 1); + request : out STD_LOGIC_VECTOR (NB_IO**2 downto 1)); +end Def_Request; + +architecture Behavioral of Def_Request is +constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S + Signal Fifo_out_full : STD_LOGIC_VECTOR (NB_IO downto 1); + signal grant_latch : std_logic_vector(NB_IO2 downto 1); + signal priority_rotation_en : std_logic; +signal req_grant,Grant_bak : std_logic_vector(NB_IO2 downto 1):=(others=>'0'); + signal Mreq : std_logic_vector(NB_IO2 downto 1):=(others=>'1'); + +begin + Req_grant<=(req and grant ); + priority_rotation_en <= '1' when unsigned(priority_rotation) = 2**NB_IO-1 else '0'; + request<=req and mreq; +--latch qui memorise le signal grant pendant la transmission + grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + Fifo_out_full<=(others => '0'); + elsif priority_rotation_en = '1' or unsigned(req_grant)=0 then + grant_latch <= Grant; + Fifo_out_full<=fifo_full; + else + grant_latch <= Grant; + Fifo_out_full<=fifo_full; + end if; + end if; + + end process; + def_mreq: process(grant_latch,fifo_full) + +variable t:std_logic_vector(NB_IO2 downto 1):=(others=>'0'); +begin + + for i in 0 to NB_IO2-1 loop + t(i+1):='0'; + --sur le front montant de fifo_full sauver l'état Grant courant + if fifo_full(i mod NB_IO+1)='1' and fifo_out_full(i mod NB_IO+1)='0' then + Grant_bak(i+1)<= grant_latch(i+1); + elsif fifo_full(i mod NB_IO+1)='0' and fifo_out_full(i mod NB_IO+1)='0' then + Grant_bak(i+1)<='0'; + end if; + for j in 0 to NB_IO-1 loop + t(i+1):=t(i+1) or grant_latch(j*NB_IO+1+i mod NB_IO) or fifo_out_full(i mod NB_IO+1); + + end loop; + mreq(i+1)<=not(t(i+1) ) or grant_latch(i+1)or grant_bak(i+1); + end loop; +end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/FIFO_256_FWFT.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/FIFO_256_FWFT.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/FIFO_256_FWFT.vhd (revision 138) @@ -0,0 +1,277 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL/GAMOM +-- +-- Create Date: 19:51:54 04/19/2011 +-- Design Name: +-- Module Name: FIFO_64 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +--FIFO 64 Octets utisé pour les modules d'entrée +-- ce fifo est de type fwft first word falls throught ce qui +-- signifie que l'on a toujours la donnée au sommet de la pile en +-- sortie du fifo. +-- Dependencies: RAM_64.vhd +-- +-- Revision: 30-07-2012 +-- Revision 0.01 - File Created +-- Additional Comments: +-- le signal counter_en a été supprimé +---------------------------------------------------------------------------------- +library IEEE; + +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--Library NocLib; +--use NocLib.CoreTypes.all; +use work.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity FIFO_256_FWFT is + Port ( clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR (Word-1 downto 0); + rd_en : in STD_LOGIC; + srst : in STD_LOGIC; + wr_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR (Word-1 downto 0); + empty : out STD_LOGIC; + full : out STD_LOGIC); +end FIFO_256_FWFT; + +architecture Behavioral of FIFO_256_FWFT is +-- declaration de la ram 256 octets +COMPONENT RAM_256 + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector(Word-1 downto 0); + addrb : IN std_logic_vector(Word-1 downto 0); + dia : IN std_logic_vector(Word-1 downto 0); + dob : OUT std_logic_vector(Word-1 downto 0) + ); +END COMPONENT; + +constant MPROOF : positive:=2; --cette constante définit la profondeur des fifos +type fsm_states is (state0, state1, state2, state3);-- definition du type etat pour le codage des etats des fsm +signal fwft_fsm_state,next_fwft_state : fsm_states; +attribute RAM_STYLE : string; + +type ram_type is array (2**(MPROOF+word)-1 downto 0) of std_logic_vector (Word-1 downto 0); + signal RAM: ram_type; + attribute RAM_STYLE of RAM: signal is "BLOCK"; +-- declaration des signeaux des compteurs +signal push_address_counter: std_logic_vector(MPROOF+Word-1 downto 0); +signal pop_address_counter : std_logic_vector(MPROOF+Word-1 downto 0); +signal fifo_counter : std_logic_vector(MPROOF+Word-1 downto 0); +--autre signaux +signal empty_signal: std_logic:='1'; +signal rd_ready,rd_ready_i : std_logic:='0'; +signal full_signal : std_logic; +signal near_full :std_logic; +signal wr_en_signal : std_logic;--_vector(0 downto 0); +signal rd_en_signal : std_logic; +signal clk_signal : std_logic; +signal dob_signal : std_logic_vector(Word-1 downto 0); +signal dout_signal : std_logic_vector(Word-1 downto 0); +signal doa_signal : std_logic_vector(Word-1 downto 0); +signal counter_en : std_logic; + +begin + +-- ram instantiation de la bloc ram 256 octets du FIFO +--fifo_RAM_256: RAM_256 PORT MAP( +-- clka => clk_signal, +-- clkb => clk_signal, +-- wea => wr_en_signal, +-- ena => '1', +-- enb => '1', +-- addra => push_address_counter, +-- addrb => pop_address_counter, +-- dia => din, +-- dob => dob_signal +-- --dob => doa_signal +-- ); + +-- circuiterie des signaux de validation et d'etat du fifo +wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein +rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide +full_signal <= '1' when unsigned(fifo_counter) = 2**(MProof+word)-1 else + '0'; +near_full <= '1' when unsigned(fifo_counter) >= 2**(MProof+word)-5 else + '0'; +--empty_signal <= '1' when fifo_counter = "000000" else +-- '0'; +empty_signal <= '1' when (rd_ready='0') else -- or (All_zeros(fifo_counter) = '0') else + '0'; +clk_signal <= clk; +full <= near_full; +empty <= empty_signal ; + +-- sortie du fifo fwft +dout <= dout_signal; +-- le processus synchrone de la MAE +fwft_fsm_sync : process(clk_signal) + begin + if rising_edge(clk_signal) then + if srst = '1' then + + fwft_fsm_state <= state0; + rd_ready<='0'; + else + fwft_fsm_state<= next_fwft_state; + rd_ready<=rd_ready_i; + end if; + + end if; + end process; +-- le processus des transistion +fwft_fsm_nsl : process(rd_ready,fwft_fsm_state,fifo_counter,rd_en_signal,wr_en_signal) + begin + --Fifo_counter=0 -->state0, + --Fifo_counter=1 -->state1, + --Fifo_counter>1 -->state2, + rd_ready_i<=rd_ready; + next_fwft_state<=fwft_fsm_state; + case fwft_fsm_state is + when state0 => if wr_en_signal = '1' then --tampon vide seule l'écriture est possible + next_fwft_state <= state1; + end if; + rd_ready_i<='0'; + --une seule donnée dans le fifo + when state1 => rd_ready_i<='1'; + if rd_en_signal = '1' and wr_en_signal='1' then + + next_fwft_state <= state1; + elsif rd_en_signal = '1' and wr_en_signal='0' then + next_fwft_state <= state0; + rd_ready_i<='0'; + elsif rd_en_signal = '0' and wr_en_signal='1' then + next_fwft_state <= state2; + else + next_fwft_state <= state1; + end if; + --plus d'une donnée dans le fifo + when state2 => rd_ready_i<='1'; + if unsigned(fifo_counter) > 1 then + next_fwft_state <= state2; + elsif unsigned(fifo_counter)=1 and rd_en_signal = '1' and wr_en_signal = '0' then + next_fwft_state <= state0; + rd_ready_i<='0'; + elsif unsigned(fifo_counter) = 1 and not(rd_en_signal='1' and wr_en_signal='0') then + next_fwft_state <= state1; + elsif unsigned(fifo_counter) = 0 then + next_fwft_state <= state0; + rd_ready_i<='0'; + else + next_fwft_state <= state2; + end if; + + when state3 => rd_ready_i<='1'; + if rd_en_signal = '1' then --écriture seule dans le tampon + next_fwft_state <= state0; + rd_ready_i<='0'; + elsif wr_en_signal='1' then + next_fwft_state <= state2; + end if; + +-- when others => fwft_fsm_state <= state0; + + + end case; + + end process; + -- actions associées à la fsm + -- mux qui oriente les sortie doa et dob vers out + with fwft_fsm_state select + dout_signal <= dob_signal when state0, + doa_signal when state1, --la sortie est la donnée en entrée + dob_signal when state2, -- la sortie vient de la RAM + dob_signal when state3, + doa_signal when others; + -- counter_en + with fwft_fsm_state select + counter_en <= '0' when state0, + '1' when state1, + '1' when state2, + '1' when state3, + '0' when others; + +--with fwft_fsm_state select +-- rd_ready <= '0' when state0, +-- '1' when state1, +-- '1' when state2, +-- '1' when state3, +-- '0' when others; +doa_latch_process : process(clk_signal) +begin + if rising_edge(clk_signal) then + if wr_en_signal ='1' then + doa_signal <= din; + end if; + end if; +end process; + +-- processus de comptage des adresses d'empilement +push_process : process(clk_signal) + begin + if rising_edge(clk_signal) then + if srst = '1' then + push_address_counter <= (others =>'0'); + elsif wr_en_signal ='1' then + RAM(conv_integer(push_address_counter)) <=din; + push_address_counter <= push_address_counter +1; + end if; + if rd_en_signal='1' then + dob_signal<=RAM(conv_integer(pop_address_counter+1)); + else + dob_signal<=RAM(conv_integer(pop_address_counter)); + end if; + end if; +end process; + + -- processus de comptage des adresses depilement du fifo +pop_process : process(clk_signal) + begin + if rising_edge(clk_signal) then + if srst = '1' then + pop_address_counter <= (others =>'0'); --pour avoir un décalage entre la valeur lue et celle qui est écrite + elsif rd_en_signal ='1' then + pop_address_counter <= pop_address_counter+1; + end if; + + end if; + end process; + + -- processus de comptage des octets dans le fifo + fifo_counter_process : process(clk_signal) +variable count : std_logic_vector(MPROOF+word-1 downto 0):= (others=>'0'); +begin + if rising_edge(clk_signal) then + if srst = '1' then + fifo_counter <= (others =>'0'); + count:=(others =>'0'); + else + if wr_en_signal ='1' and rd_en_signal ='0' then + --fifo_counter <= fifo_counter +1; + count:=count+1; + end if; + if rd_en_signal ='1' and wr_en_signal ='0' and counter_en='1' then + --fifo_counter <= fifo_counter - 1; + count:=count-1; + end if; + fifo_counter<=count; + end if; + end if; +end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/FIFO_256_FWFT.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/FIFO_256_FWFT.vhd.bak (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/FIFO_256_FWFT.vhd.bak (revision 138) @@ -0,0 +1,277 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL/GAMOM +-- +-- Create Date: 19:51:54 04/19/2011 +-- Design Name: +-- Module Name: FIFO_64 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +--FIFO 64 Octets utisé pour les modules d'entrée +-- ce fifo est de type fwft first word falls throught ce qui +-- signifie que l'on a toujours la donnée au sommet de la pile en +-- sortie du fifo. +-- Dependencies: RAM_64.vhd +-- +-- Revision: 30-07-2012 +-- Revision 0.01 - File Created +-- Additional Comments: +-- le signal counter_en a été supprimé +---------------------------------------------------------------------------------- +library IEEE; + +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--Library NocLib; +--use NocLib.CoreTypes.all; +use work.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity FIFO_256_FWFT is + Port ( clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR (Word-1 downto 0); + rd_en : in STD_LOGIC; + srst : in STD_LOGIC; + wr_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR (Word-1 downto 0); + empty : out STD_LOGIC; + full : out STD_LOGIC); +end FIFO_256_FWFT; + +architecture Behavioral of FIFO_256_FWFT is +-- declaration de la ram 256 octets +COMPONENT RAM_256 + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector(Word-1 downto 0); + addrb : IN std_logic_vector(Word-1 downto 0); + dia : IN std_logic_vector(Word-1 downto 0); + dob : OUT std_logic_vector(Word-1 downto 0) + ); +END COMPONENT; + +constant MPROOF : positive:=2; --cette constante définit la profondeur des fifos +type fsm_states is (state0, state1, state2, state3);-- definition du type etat pour le codage des etats des fsm +signal fwft_fsm_state,next_fwft_state : fsm_states; +attribute RAM_STYLE : string; + +type ram_type is array (2**(MPROOF+word)-1 downto 0) of std_logic_vector (Word-1 downto 0); + signal RAM: ram_type; + attribute RAM_STYLE of RAM: signal is "BLOCK"; +-- declaration des signeaux des compteurs +signal push_address_counter: std_logic_vector(MPROOF+Word-1 downto 0); +signal pop_address_counter : std_logic_vector(MPROOF+Word-1 downto 0); +signal fifo_counter : std_logic_vector(MPROOF+Word-1 downto 0); +--autre signaux +signal empty_signal: std_logic:='1'; +signal rd_ready,rd_ready_i : std_logic:='0'; +signal full_signal : std_logic; +signal near_full :std_logic; +signal wr_en_signal : std_logic;--_vector(0 downto 0); +signal rd_en_signal : std_logic; +signal clk_signal : std_logic; +signal dob_signal : std_logic_vector(Word-1 downto 0); +signal dout_signal : std_logic_vector(Word-1 downto 0); +signal doa_signal : std_logic_vector(Word-1 downto 0); +signal counter_en : std_logic; + +begin + +-- ram instantiation de la bloc ram 256 octets du FIFO +--fifo_RAM_256: RAM_256 PORT MAP( +-- clka => clk_signal, +-- clkb => clk_signal, +-- wea => wr_en_signal, +-- ena => '1', +-- enb => '1', +-- addra => push_address_counter, +-- addrb => pop_address_counter, +-- dia => din, +-- dob => dob_signal +-- --dob => doa_signal +-- ); + +-- circuiterie des signaux de validation et d'etat du fifo +wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein +rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide +full_signal <= '1' when unsigned(fifo_counter) = 2**(MProof+word)-1 else + '0'; +near_full <= '1' when unsigned(fifo_counter) >= 2**(MProof+word)-5 else + '0'; +--empty_signal <= '1' when fifo_counter = "000000" else +-- '0'; +empty_signal <= '1' when (rd_ready='0') else -- or (All_zeros(fifo_counter) = '0') else + '0'; +clk_signal <= clk; +full <= near_full; +empty <= empty_signal ; + +-- sortie du fifo fwft +dout <= dout_signal; +-- le processus synchrone de la MAE +fwft_fsm_sync : process(clk_signal) + begin + if rising_edge(clk_signal) then + if srst = '1' then + + fwft_fsm_state <= state0; + rd_ready<='0'; + else + fwft_fsm_state<= next_fwft_state; + rd_ready<=rd_ready_i; + end if; + + end if; + end process; +-- le processus des transistion +fwft_fsm_nsl : process(rd_ready,fwft_fsm_state,fifo_counter,rd_en_signal,wr_en_signal) + begin + --Fifo_counter=0 -->state0, + --Fifo_counter=1 -->state1, + --Fifo_counter>1 -->state2, + rd_ready_i<=rd_ready; + next_fwft_state<=fwft_fsm_state; + case fwft_fsm_state is + when state0 => if wr_en_signal = '1' then --tampon vide seule l'écriture est possible + next_fwft_state <= state1; + end if; + rd_ready_i<='0'; + --une seule donnée dans le fifo + when state1 => rd_ready_i<='1'; + if rd_en_signal = '1' and wr_en_signal='1' then + + next_fwft_state <= state1; + elsif rd_en_signal = '1' and wr_en_signal='0' then + next_fwft_state <= state0; + rd_ready_i<='0'; + elsif rd_en_signal = '0' and wr_en_signal='1' then + next_fwft_state <= state2; + else + next_fwft_state <= state1; + end if; + --plus d'une donnée dans le fifo + when state2 => rd_ready_i<='1'; + if unsigned(fifo_counter) > 1 then + next_fwft_state <= state2; + elsif unsigned(fifo_counter)=1 and rd_en_signal = '1' and wr_en_signal = '0' then + next_fwft_state <= state0; + rd_ready_i<='0'; + elsif unsigned(fifo_counter) = 1 then + next_fwft_state <= state1; + elsif unsigned(fifo_counter) = 0 then + next_fwft_state <= state0; + rd_ready_i<='0'; + else + next_fwft_state <= state2; + end if; + + when state3 => rd_ready_i<='1'; + if rd_en_signal = '1' then --écriture seule dans le tampon + next_fwft_state <= state0; + rd_ready_i<='0'; + elsif wr_en_signal='1' then + next_fwft_state <= state2; + end if; + +-- when others => fwft_fsm_state <= state0; + + + end case; + + end process; + -- actions associées à la fsm + -- mux qui oriente les sortie doa et dob vers out + with fwft_fsm_state select + dout_signal <= dob_signal when state0, + doa_signal when state1, --la sortie est la donnée en entrée + dob_signal when state2, -- la sortie vient de la RAM + dob_signal when state3, + doa_signal when others; + -- counter_en + with fwft_fsm_state select + counter_en <= '0' when state0, + '1' when state1, + '1' when state2, + '1' when state3, + '0' when others; + +--with fwft_fsm_state select +-- rd_ready <= '0' when state0, +-- '1' when state1, +-- '1' when state2, +-- '1' when state3, +-- '0' when others; +doa_latch_process : process(clk_signal) +begin + if rising_edge(clk_signal) then + if wr_en_signal ='1' then + doa_signal <= din; + end if; + end if; +end process; + +-- processus de comptage des adresses d'empilement +push_process : process(clk_signal) + begin + if rising_edge(clk_signal) then + if srst = '1' then + push_address_counter <= (others =>'0'); + elsif wr_en_signal ='1' then + RAM(conv_integer(push_address_counter)) <=din; + push_address_counter <= push_address_counter +1; + end if; + if rd_en_signal='1' then + dob_signal<=RAM(conv_integer(pop_address_counter+1)); + else + dob_signal<=RAM(conv_integer(pop_address_counter)); + end if; + end if; +end process; + + -- processus de comptage des adresses depilement du fifo +pop_process : process(clk_signal) + begin + if rising_edge(clk_signal) then + if srst = '1' then + pop_address_counter <= (others =>'0'); --pour avoir un décalage entre la valeur lue et celle qui est écrite + elsif rd_en_signal ='1' then + pop_address_counter <= pop_address_counter+1; + end if; + + end if; + end process; + + -- processus de comptage des octets dans le fifo + fifo_counter_process : process(clk_signal) +variable count : std_logic_vector(MPROOF+word-1 downto 0):= (others=>'0'); +begin + if rising_edge(clk_signal) then + if srst = '1' then + fifo_counter <= (others =>'0'); + count:=(others =>'0'); + else + if wr_en_signal ='1' and rd_en_signal ='0' then + --fifo_counter <= fifo_counter +1; + count:=count+1; + end if; + if rd_en_signal ='1' and wr_en_signal ='0' and counter_en='1' then + --fifo_counter <= fifo_counter - 1; + count:=count-1; + end if; + fifo_counter<=count; + end if; + end if; +end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/FIFO_DP.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/FIFO_DP.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/FIFO_DP.vhd (revision 138) @@ -0,0 +1,102 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:32:59 10/23/2012 +-- Design Name: +-- Module Name: FIFO_DP - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity fifo_dp is +GENERIC +( +ADDRESS_WIDTH : integer:=8;---8 bit +DATA_WIDTH : integer:=8 ---8 bit +); + +port ( clk : in std_logic; +reset : in std_logic; +enr : in std_logic; --enable read,should be '0' when not in use. +enw : in std_logic; --enable write,should be '0' when not in use. +dataout : out std_logic_vector(DATA_WIDTH-1 downto 0); --output data +datain : in std_logic_vector (DATA_WIDTH-1 downto 0); --input data +empty : out std_logic; --set as '1' when the queue is empty +err : out std_logic; +full : out std_logic --set as '1' when the queue is full +); +end fifo_dp; + +architecture Behavioral of fifo_dp is + +type memory_type is array (0 to ((2**ADDRESS_WIDTH)-1)) of std_logic_vector(DATA_WIDTH-1 downto 0); + + +-----distributed------- +signal memory : memory_type ;-- :=(others => (others => '0')); --memory for queue.----- +signal readptr,writeptr : std_logic_vector(ADDRESS_WIDTH-1 downto 0); --read and write pointers. +signal full0 : std_logic; +signal empty0 : std_logic; + +begin +full <= full0; +empty <= empty0; + +fifo0: process(clk,reset) +begin +if reset='1' then + +readptr <= (others => '0'); +writeptr <= (others => '0'); +empty0 <='1'; +full0<='0'; +err<='0'; + + +elsif rising_edge(clk) then + +if (writeptr + '1' = readptr) then +full0<='1'; +else +full0<='0'; +end if ; + +if (readptr = writeptr ) then +empty0<='1'; +else +empty0<='0'; +end if ; + +if (empty0='0' and enr='1') or (full0='0' and enw='1') then +err<='1'; +end if ; + +if enw='1' and full0='0' then +memory (conv_integer(writeptr)) <= datain ; +writeptr <= writeptr + '1' ; +end if ; + +if enr='1' and empty0='0' then +dataout <= memory (conv_integer(readptr)); +readptr <= readptr + '1' ; +end if ; + +end if; + +end process; +end Behavioral; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/INPUT_PORT_MODULE.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/INPUT_PORT_MODULE.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/INPUT_PORT_MODULE.vhd (revision 138) @@ -0,0 +1,878 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL/GAMOM Roland CHristian +-- +-- Create Date: 03:47:50 04/24/2011 +-- Design Name: +-- Module Name: INPUT_PORT_MODULE - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- Module de gestion des entrées des ports du switch crossbar +-- il supose qu'une donnée est empilée à chaque cycle d'horloge +-- Dependencies: +-- FIFO_64_FWFT.vhd +-- RAM_64.vhd +-- Revision: 1 +-- remplacement du fifo ordinaire par un fifo fwft +-- Revision 1.01 - File Created +-- Additional Comments: +-- modifié le 14/05/20011 pour eviter une écriture multiple dans le FIFO de sortie +-- si le FIFO d'entrée vient a se vider pendant le transfert d'un packet +-- le machine a état on été re modeliser et sont maintenant du type FSMD +-- remodéliation pour plus de vitesse +--inclusion du signal priority rotation pour eviter la perte du grant pendant une transmission +--02-08-2012 :Prise en compte du signal Port_Granted dans un process +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +USE ieee.numeric_std.ALL; +use work.Coretypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +entity INPUT_PORT_MODULE is + generic(number_of_ports : positive := 4; + + Port_num: natural:=1); -- port_num est l'id du port + Port ( data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + data_in_en : in STD_LOGIC; -- signaler la présence des données en entrée + cmd_in_en :in STD_LOGIC; --permet d'identifier les données qui sont dans le tampon + reset : in STD_LOGIC; + clk : in STD_LOGIC; + request : out STD_LOGIC_VECTOR (number_of_ports downto 1); --demande de canal de transmission + grant : in STD_LOGIC_VECTOR (number_of_ports downto 1); -- autorisation de transmission + fifo_full : out STD_LOGIC; -- signaler que les données ne peuvent plus être acceptées en entrée + fifo_empty : out STD_LOGIC; -- le tampon d'entrée est vide + priority_rotation : out std_logic; -- reserver le canal de transmission + data_out : out STD_LOGIC_VECTOR (Word-1 downto 0); --données vers le réseau crossbar + data_out_pulse : out std_logic); -- permet de ... + +end INPUT_PORT_MODULE; + +architecture Behavioral of INPUT_PORT_MODULE is + +-- declaration du fifo 64 octet utilisé pour chaque port +component FIFO_256_FWFT + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(Word-1 downto 0); + rd_en: IN std_logic; + srst: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(Word-1 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +end component; + +--definition du type etat pour les fsm +type fsm_states is (state0, CmdOn, WaitGrant, ReqPort, state1, state2,strecover,stpulse,stateErr, state3);-- definition du type etat pour le codage des etats des fsm +type fsm_states2 is(cmdstart,cmdwait,cmdread,cmdSetDest,cmdSetCount,cmdSetId,cmdpulse,CmdEnd); +signal pop_state : fsm_states; +signal cmdstate : fsm_states2; +signal cmd_exec : std_logic:='0'; --indique que le port est en train d'exécuter une commande +signal dat_exec :std_logic:='0'; -- indique le port est en train de transférer des données +signal dat_Err :std_logic:='0'; -- signal une erreur pendant l'exécution +signal wrok,readOk,CmdReadOk : std_logic:='0'; --indique s'il est possible de lire les données +-- signaux utilisés dans les fsm +signal request_decoder,req_grant : STD_LOGIC_VECTOR(number_of_ports downto 1); +signal request_decoder_en : std_logic; +signal request_latch : STD_LOGIC_VECTOR(4 downto 1):=(others=>'0'); -- pourquoi pas 3 downto 0 ? +signal request_latch_en : std_logic; +signal pipeline_latch : std_logic_vector(Word-1 downto 0); +signal pipeline_latch_en : std_logic; +signal request_word : std_logic_vector(5 downto 1); +signal port_granted : std_logic; +signal rd_en_signal : std_logic; +--signaux utilisés dans la MAE de gestion des commandes +signal cmd_request_latch_en :std_logic; +signal cmd_pipeline_latch_en :std_logic; +signal cmd_fifo_read_signal :std_logic; +signal cmd_request_decoder_en :std_logic; +signal cmd_data_out_pulse :std_logic; +signal cmd_priority_rotation :std_logic; +--signaux utilisés dans la MAE de transfert des données +signal dat_request_latch_en :std_logic; +signal dat_pipeline_latch_en :std_logic; +signal dat_fifo_read_signal :std_logic; +signal dat_request_decoder_en :std_logic; +signal dat_data_out_pulse :std_logic; +signal dat_priority_rotation :std_logic; +-- signaux utilisés pour les connections entre composants +signal clk_signal : std_logic; +signal reset_signal : std_logic; +signal fifo_empty_signal : std_logic; +signal fifo_read_signal : std_logic; +signal fifo_out_signal,cmd_data_signal : std_logic_vector(Word-1 downto 0); +signal push_dout : std_logic_vector(Word-1 downto 0); +signal empty_latch : std_logic ; +signal PORT_ID :std_logic_vector(Word-1 downto 0):=STD_LOGIC_VECTOR(to_unsigned(number_of_ports-1,4))& STD_LOGIC_VECTOR(to_unsigned(port_num-1,4)); +-- signaux du compteur de données +signal data_counter : std_logic_vector(Word-1 downto 0); + +begin +-- instantiation du FIFO_256 + INPUT_PORT_FIFO : FIFO_256_FWFT + port map ( + clk => clk_signal, + din => data_in, + rd_en => fifo_read_signal, + srst => reset_signal, + wr_en => data_in_en, + dout => fifo_out_signal, + empty => fifo_empty_signal, + full => fifo_full); +-- connections avec les ports de l'entité + +data_out <= pipeline_latch ;--when cmd_exec='0' else cmd_data_signal; +fifo_empty <= empty_latch; +reset_signal <= reset; +grant_proc:process(req_grant) +begin +--if rising_edge(clk) then +-- if unsigned(grant)> 0 then + if unsigned(req_grant) > 0 then + port_granted <= '1'; --il faut veiller à ce que ce port soit vraiment autorisé + else + Port_granted<='0'; --ceci présuppose que la valeur qu'il reçoit est forcément la sienne + end if; +--end if; +end process; +rd_en_signal <= not(fifo_empty_signal);--not(empty_latch) ; +request <= request_decoder; +reg_grant:process (request_decoder,grant) +begin +req_grant<=request_decoder and grant; +end process reg_grant; +request_word <= request_latch & request_decoder_en; +clk_signal <= clk; + + + +WITH cmd_exec SELECT + request_latch_en <= dat_request_latch_en WHEN '0', + cmd_request_latch_en WHEN others; + +WITH cmd_exec SELECT + pipeline_latch_en <= dat_pipeline_latch_en WHEN '0', + cmd_pipeline_latch_en WHEN others; + +WITH cmd_exec SELECT + fifo_read_signal <=dat_fifo_read_signal WHEN '0', + + cmd_fifo_read_signal WHEN others; +WITH cmd_exec SELECT + request_decoder_en <=dat_request_decoder_en WHEN '0', + cmd_request_decoder_en WHEN others; +WITH cmd_exec SELECT + data_out_pulse <=dat_data_out_pulse WHEN '0', + cmd_data_out_pulse WHEN others; +WITH cmd_exec SELECT + priority_rotation<=dat_priority_rotation WHEN '0', + cmd_priority_rotation WHEN others; + + +--processus permettant de latcher le signal empty +-- evite une perte de données en cas d'arret au cours d'une transmission +empty_latch_process : process(clk) +begin + if rising_edge(clk) then + if reset_signal = '1' then + empty_latch <= '1'; + else + empty_latch <= fifo_empty_signal; + end if; + end if; + +end process; +-- decodeur de requete en fonction de l'adresse destination +-- le circuit genere depend du parametre generique nombre de ports +-- switch 2 ports +switch2x2 : if number_of_ports = 2 generate + +with request_word select + request_decoder <="01" when "00001", + "10" when "00011", + "00" when others; + +end generate switch2x2; + + +-- switch 3 ports +switch3x3 : if number_of_ports = 3 generate + +with request_word select + request_decoder <="001" when "00001", + "010" when "00011", + "100" when "00101", + "000" when others; + +end generate switch3x3; + + +-- switch 4 ports +switch4x4 : if number_of_ports = 4 generate + +with request_word select + request_decoder <="0001" when "00001", + "0010" when "00011", + "0100" when "00101", + "1000" when "00111", + "0000" when others; + +end generate switch4x4; + + +-- switch 5 ports +switch5x5 : if number_of_ports = 5 generate + +with request_word select + request_decoder <="00001" when "00001", + "00010" when "00011", + "00100" when "00101", + "01000" when "00111", + "10000" when "01001", + "00000" when others; + +end generate switch5x5; + + +-- switch 6 ports +switch6x6 : if number_of_ports = 6 generate + +with request_word select + request_decoder <="000001" when "00001", + "000010" when "00011", + "000100" when "00101", + "001000" when "00111", + "010000" when "01001", + "100000" when "01011", + "000000" when others; + +end generate switch6x6; + + +-- switch 7 ports +switch7x7 : if number_of_ports = 7 generate + +with request_word select + request_decoder <="0000001" when "00001", + "0000010" when "00011", + "0000100" when "00101", + "0001000" when "00111", + "0010000" when "01001", + "0100000" when "01011", + "1000000" when "01101", + "0000000" when others; + +end generate switch7x7; + + +-- switch 8 ports +switch8x8 : if number_of_ports = 8 generate + +with request_word select + request_decoder <="00000001" when "00001", + "00000010" when "00011", + "00000100" when "00101", + "00001000" when "00111", + "00010000" when "01001", + "00100000" when "01011", + "01000000" when "01101", + "10000000" when "01111", + "00000000" when others; + +end generate switch8x8; + + +-- switch 9 ports +switch9x9 : if number_of_ports = 9 generate + +with request_word select + request_decoder <="000000001" when "00001", + "000000010" when "00011", + "000000100" when "00101", + "000001000" when "00111", + "000010000" when "01001", + "000100000" when "01011", + "001000000" when "01101", + "010000000" when "01111", + "100000000" when "10001", + "000000000" when others; + +end generate switch9x9; + + +-- switch 10 ports +switch10x10 : if number_of_ports = 10 generate + +with request_word select + request_decoder <="0000000001" when "00001", + "0000000010" when "00011", + "0000000100" when "00101", + "0000001000" when "00111", + "0000010000" when "01001", + "0000100000" when "01011", + "0001000000" when "01101", + "0010000000" when "01111", + "0100000000" when "10001", + "1000000000" when "10011", + "0000000000" when others; + +end generate switch10x10; + + +-- switch 11 ports +switch11x11 : if number_of_ports = 11 generate + +with request_word select + request_decoder <="00000000001" when "00001", + "00000000010" when "00011", + "00000000100" when "00101", + "00000001000" when "00111", + "00000010000" when "01001", + "00000100000" when "01011", + "00001000000" when "01101", + "00010000000" when "01111", + "00100000000" when "10001", + "01000000000" when "10011", + "10000000000" when "10101", + "00000000000" when others; + +end generate switch11x11; + + +-- switch 12 ports +switch12x12 : if number_of_ports = 12 generate + +with request_word select + request_decoder <="000000000001" when "00001", + "000000000010" when "00011", + "000000000100" when "00101", + "000000001000" when "00111", + "000000010000" when "01001", + "000000100000" when "01011", + "000001000000" when "01101", + "000010000000" when "01111", + "000100000000" when "10001", + "001000000000" when "10011", + "010000000000" when "10101", + "100000000000" when "10111", + "000000000000" when others; + +end generate switch12x12; + + +-- switch 13 ports +switch13x13 : if number_of_ports = 13 generate + +with request_word select + request_decoder <="0000000000001" when "00001", + "0000000000010" when "00011", + "0000000000100" when "00101", + "0000000001000" when "00111", + "0000000010000" when "01001", + "0000000100000" when "01011", + "0000001000000" when "01101", + "0000010000000" when "01111", + "0000100000000" when "10001", + "0001000000000" when "10011", + "0010000000000" when "10101", + "0100000000000" when "10111", + "1000000000000" when "11001", + "0000000000000" when others; + +end generate switch13x13; + + +-- switch 14 ports +switch14x14 : if number_of_ports = 14 generate + +with request_word select + request_decoder <="00000000000001" when "00001", + "00000000000010" when "00011", + "00000000000100" when "00101", + "00000000001000" when "00111", + "00000000010000" when "01001", + "00000000100000" when "01011", + "00000001000000" when "01101", + "00000010000000" when "01111", + "00000100000000" when "10001", + "00001000000000" when "10011", + "00010000000000" when "10101", + "00100000000000" when "10111", + "01000000000000" when "11001", + "10000000000000" when "11011", + "00000000000000" when others; + +end generate switch14x14; + + +-- switch 15 ports +switch15x15 : if number_of_ports = 15 generate + +with request_word select + request_decoder <="000000000000001" when "00001", + "000000000000010" when "00011", + "000000000000100" when "00101", + "000000000001000" when "00111", + "000000000010000" when "01001", + "000000000100000" when "01011", + "000000001000000" when "01101", + "000000010000000" when "01111", + "000000100000000" when "10001", + "000001000000000" when "10011", + "000010000000000" when "10101", + "000100000000000" when "10111", + "001000000000000" when "11001", + "010000000000000" when "11011", + "100000000000000" when "11101", + "000000000000000" when others; + +end generate switch15x15; + + +-- switch 16 ports +switch16x16 : if number_of_ports = 16 generate + +with request_word select + request_decoder <="0000000000000001" when "00001", + "0000000000000010" when "00011", + "0000000000000100" when "00101", + "0000000000001000" when "00111", + "0000000000010000" when "01001", + "0000000000100000" when "01011", + "0000000001000000" when "01101", + "0000000010000000" when "01111", + "0000000100000000" when "10001", + "0000001000000000" when "10011", + "0000010000000000" when "10101", + "0000100000000000" when "10111", + "0001000000000000" when "11001", + "0010000000000000" when "11011", + "0100000000000000" when "11101", + "1000000000000000" when "11111", + "0000000000000000" when others; + +end generate switch16x16; +--latch du fifo de sortie ?? +pipeline_latch_process : process(clk) +begin + if rising_edge(clk) then + if reset_signal = '1' then + pipeline_latch <= (others => '0'); + elsif pipeline_latch_en = '1' and cmd_exec='0' then + pipeline_latch <= push_dout; + elsif pipeline_latch_en = '1' and cmd_exec='1' then + pipeline_latch <= cmd_data_signal; + end if; + end if; +end process; + +--latch qui memorise l'adresse de destination du packet + +request_latch_process : process(clk) +begin + if rising_edge(clk) then + if reset_signal = '1' then + request_latch <= (others => '0'); + elsif request_latch_en = '1' and cmd_in_en='0' then --si la lecture de la destination est autorisée + request_latch <=fifo_out_signal(3 downto 0); --fifo_out_signal(3) & fifo_out_signal(2) & fifo_out_signal(1) & fifo_out_signal(0); + assert (unsigned(fifo_out_signal(3 downto 0)) '0'); + elsif cmd_exec='0' then --il ne faut pas exécuter cette MAE + -- lorsque l'autre est en cours + wrok<='0'; + case pop_state is + when state0 => if cmd_in_en='0' then --il ne faut pas exécuter les deux MAE ... + if empty_latch ='0' then -- pile pas vide on doit dépiler + pop_state <= WaitGrant; + end if; + else + pop_state <= CmdOn; + end if; + when CmdOn => if empty_latch='1' and cmd_in_en='0' then + pop_state <= state0; + elsif empty_latch='0' and cmd_in_en='1' then + pop_state <= CmdOn; + elsif empty_latch='1' and cmd_in_en='1' then + pop_state <= state0; + else -- empty_latch='0' and cmd_in_en='0' + pop_state <= WaitGrant; + end if; + + when WaitGrant => if port_granted = '1' then + -- + pop_state <= ReqPort; + end if; + + when ReqPort => --if port_granted = '1' then + -- + pop_state <= state1; + + --end if; + + when state1 => if port_granted ='1' then --lecture de la longueur des données + data_counter <= fifo_out_signal; + if unsigned(fifo_out_signal)<=3 then + ReadOk<='1'; + else + readOk<='1'; + end if; + pop_state <= state2; + wrok<='1'; + else + wrok<='0'; + end if; + + when state2 => if port_granted='1' then + wrok<='1'; + if fifo_empty_signal ='0' then + if rd_en_signal ='1' and unsigned(data_counter)<= 3 then + data_counter <= data_counter - 1; + pop_state <= stpulse; + ReadOk<='1'; + elsif rd_en_signal ='1' then + data_counter <= data_counter - 1; + pop_state <= state2; + ReadOk<='1'; + else --fifo_empty_signal='1' fin prématurée de la lecture + ReadOk<='0'; + wrok<='0'; + --pop_state<=stateErr; + --data_counter<=(others => '0'); + end if; + else + pop_state<=strecover; + data_counter <= data_counter + 1; + report "Input_port_module : Le fifo d'entrée du port " & integer'image(to_integer(unsigned(Port_id(3 downto 0))+1)) & " est vide !!!"; + wrok<='0'; + readok<='0'; + end if; + else + wrOk<='0'; + readok<='0'; + report "Input_port_module : Le fifo de réception du port " & integer'image(to_integer(unsigned(request_latch)+1)) & " est probablement plein !!!"; + pop_state<=strecover; + data_counter <= data_counter + 1; + end if; + when strecover => if fifo_empty_signal='0' and port_granted='1' then + pop_state<=state2; + readok<='0'; + wrok<='0'; + else + readok<='0'; + wrok<='0'; + end if; + + + when stpulse => if port_granted='1' then + pop_state <= state3; --pousser la dernière donnée dehors + data_counter <= data_counter - 1; + wrok<='1'; + end if; + wrok<='0'; + when state3 => wrok<='0'; + data_counter <= data_counter - 1; + pop_state <= state0; + when stateErr => wrok<='0'; + data_counter <= data_counter; + pop_state <= stateErr; + report "Error in the NoC when sending data " ; + when others => pop_state <= state0; + wrok<='0'; + end case; + end if; + end if; +end process; + +-- actions associées à chaque etat de la fsm de mealy +pop_fsm_action : process(pop_state, fifo_out_signal,empty_latch, rd_en_signal,readok, port_granted ) + begin +-- code fonctionnel + case pop_state is + when state0 => dat_request_latch_en <= '0'; + dat_pipeline_latch_en <= '0'; + dat_fifo_read_signal <='0'; + dat_request_decoder_en <= '0'; + dat_data_out_pulse <= '0'; + dat_priority_rotation <= '1'; + dat_exec<='0'; + dat_Err<='0'; + push_dout<=fifo_out_signal; + + when CmdOn => dat_request_latch_en <= '0'; + dat_pipeline_latch_en <= '0'; + dat_fifo_read_signal <='0'; + dat_request_decoder_en <= '0'; + dat_data_out_pulse <= '0'; + dat_priority_rotation <= '1'; + dat_exec<='0'; + dat_Err<='0'; + push_dout<=fifo_out_signal; + when WaitGrant => + dat_request_latch_en <='1'; --autoriser l'identification du port de destination + dat_pipeline_latch_en <= '0'; --pour le transmettre à travers le réseau + dat_fifo_read_signal <= '0'; + dat_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request + dat_data_out_pulse <= '0'; --transmettre le signal pour le dernier mot + dat_priority_rotation <= Port_granted; --dès qu'on a la priorité on la garde + dat_exec<='1'; + dat_Err<='0'; + push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0); + when ReqPort => + dat_request_latch_en <='1'; --autoriser l'identification du port de destination + dat_pipeline_latch_en <= '1'; --pour le transmettre à travers le réseau + dat_fifo_read_signal <= '1'; + dat_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request + dat_data_out_pulse <= '0'; --transmettre le signal pour le dernier mot + dat_priority_rotation <= '0'; + dat_exec<='1'; + dat_Err<='0'; + push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0); + + when state1 => dat_request_latch_en <= '0'; + dat_pipeline_latch_en <= rd_en_signal and port_granted; + dat_fifo_read_signal <= rd_en_signal and port_granted; + dat_request_decoder_en <= '1'; + dat_data_out_pulse <= port_granted; + dat_priority_rotation <= '0'; + dat_exec<='1'; + dat_Err<='0'; + push_dout<=fifo_out_signal; + + when state2 |strecover => dat_request_latch_en <= '0'; + dat_pipeline_latch_en <= port_granted and wrok and not(fifo_empty_signal); --autoriser la lecture du fifo en sortie + dat_fifo_read_signal <= port_granted and readok; + dat_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request + dat_data_out_pulse <= port_granted and wrOk and not(fifo_empty_signal); + dat_priority_rotation <= '0'; + dat_exec<='1'; + dat_Err<='0'; + push_dout<=fifo_out_signal; + + when stpulse => dat_request_latch_en <= '0'; --pousser la dernière donnée + dat_pipeline_latch_en <= '0'; --autoriser la lecture du fifo en sortie + dat_fifo_read_signal <='0'; + dat_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request + dat_data_out_pulse <= '1'; -- pousser le dernier mot + dat_priority_rotation <= '0'; + dat_exec<='1'; + dat_Err<='0'; + push_dout<=fifo_out_signal; + + when state3 => dat_request_latch_en <= '0'; + dat_pipeline_latch_en <= '0'; + dat_priority_rotation <= '1'; -- libérer la priorité + dat_fifo_read_signal <= '0'; + dat_request_decoder_en <= '0'; --libérer le décodeur + dat_data_out_pulse <= '0'; + dat_exec<='0'; + dat_Err<='0'; + push_dout<=fifo_out_signal; + when stateErr => dat_request_latch_en <= '0'; + dat_pipeline_latch_en <= '0'; + dat_priority_rotation <= '1'; -- libérer la priorité + dat_fifo_read_signal <= '0'; + dat_request_decoder_en <= '0'; --libérer le décodeur + dat_data_out_pulse <= '0'; + dat_exec<='1'; + dat_Err<='1'; + push_dout<=fifo_out_signal; + when others => dat_request_latch_en <= '0'; + dat_pipeline_latch_en <= '0'; + dat_priority_rotation <= '1'; + dat_fifo_read_signal <= '0'; + dat_request_decoder_en <= '0'; + dat_data_out_pulse <= '0'; + dat_exec<='0'; + dat_Err<='0'; + push_dout<=fifo_out_signal; + + end case; + end process; + -- traitement des commandes reçues par le switch +fsm_cmd:process(clk,cmd_in_en) +variable timeout : natural:=0; +variable cmdcode : natural range 0 to 255; +begin +if rising_edge(clk) then + if reset_signal = '1' then + cmdstate<=cmdstart; + else -- il ne faut pas traiter les cmdes et les données en même temps + case cmdstate is + + when cmdstart => + if cmd_in_en='1' and dat_exec='0' and empty_latch='0' then + cmdstate<=cmdread; + end if; + cmdReadOk<='0'; + when cmdwait => if port_granted='1' then -- demande du port de sortie + + cmdstate<=cmdsetdest; + elsif cmd_in_en='1' then + cmdstate<=cmdwait; + else + cmdstate<=cmdstart; + end if; + cmdReadOk<='0'; + when cmdread => +-- if port_granted ='1'then -- ne pas modifier l'état des priorités si on ne l'avait pas + cmdcode:= to_integer(unsigned(fifo_out_signal)); + if cmdcode=1 then --code de getportid + cmdstate<=cmdwait; + cmdReadOk<='1'; + else + --ne pas prendre le code inconnu en compte + cmdstate<=cmdend; -- la commande n'a pas été reconnu + + cmdReadOk<='0'; + end if; +-- end if; + when cmdsetdest => + if port_granted='1' then + cmdstate<=cmdsetcount; + end if; + cmdReadOk<='0'; + when cmdsetcount => + if port_granted='1' then + cmdstate<=cmdsetID; + else + cmdstate<=cmdsetdest; + end if; + cmdReadOk<='0'; + when cmdsetID=> + if port_granted='1' then + cmdstate <=cmdpulse; + end if; + cmdReadOk<='0'; + when cmdpulse => + if port_granted='1' then + cmdstate <=cmdEnd; + end if; + cmdReadOk<='0'; + when cmdend => + if cmd_in_en='0' then --éviter l'exécution en boucle + cmdstate<=cmdstart; + end if; + cmdReadOk<='0'; + + end case; + end if; +end if; +end process fsm_cmd; + +cmdaffect:process (cmdstate,fifo_empty_signal, port_granted, PORT_ID) +begin +case cmdstate is + + when cmdstart => + cmd_exec<='0'; + cmd_pipeline_latch_en <='0'; + cmd_priority_rotation <= '1'; + cmd_request_latch_en<='0'; + cmd_fifo_read_signal <= '0'; + cmd_request_decoder_en <= '0'; + cmd_data_signal<=(others=>'0'); + cmd_data_out_pulse <= '0'; + + when cmdread => + cmd_exec<='1'; + cmd_pipeline_latch_en <= '0'; + cmd_fifo_read_signal <= '1'; -- vider le tampon d'entrée + cmd_request_latch_en<='1'; --mémoriser l'adresse de destination + cmd_request_decoder_en <= '1'; --demande d'émission + cmd_data_out_pulse <= '0'; + cmd_priority_rotation <= '1'; --sans priorité + cmd_data_signal<=Port_ID; + when cmdwait => + cmd_exec<='1'; + cmd_pipeline_latch_en <='0'; + cmd_fifo_read_signal <= '0'; + cmd_request_latch_en<='1'; + cmd_priority_rotation <= '0'; --avec priorité + cmd_request_decoder_en <= '1'; --demande d'émission + cmd_data_signal<=Port_ID; + cmd_data_out_pulse <= '0'; + when cmdsetdest => + --cmd_request_decoder_en <= '1'; + cmd_exec<='1'; + cmd_pipeline_latch_en <='1'; --empiler dans le tampon de sortie la donnée + cmd_fifo_read_signal <='0'; + cmd_request_latch_en<='0'; + cmd_request_decoder_en <= '1'; --autoriser le decodeur à activer le dernier bit de request + cmd_data_out_pulse <= '0'; + cmd_priority_rotation <= '0'; + cmd_data_signal<=Port_ID; -- le numéro du port et le nombre total des ports est envoyé + when cmdsetcount => + + cmd_exec<='1'; + cmd_pipeline_latch_en <='1'; -- empiler dans le tampon de sortie les données + cmd_fifo_read_signal <='0'; + cmd_request_latch_en<='0'; --enregistrer l'adresse de destination + cmd_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request + cmd_data_out_pulse <= port_granted; + cmd_priority_rotation <= '0'; + cmd_data_signal<=STD_LOGIC_VECTOR(to_unsigned(3,8)); + when cmdSetId => + --cmd_request_decoder_en <= '1'; + cmd_exec<='1'; + cmd_pipeline_latch_en <='1'; + cmd_fifo_read_signal <='0'; + cmd_request_latch_en<='0'; --enregistrer l'adresse de destination + cmd_request_decoder_en <= '1'; --autoriser le decodeur à activer le dernier bit de request + cmd_data_out_pulse <= port_granted; + cmd_priority_rotation <= '0'; + cmd_data_signal<=Port_ID; -- le numéro du port et le nombre total des ports est envoyé + + when cmdpulse => cmd_exec<='1'; + cmd_pipeline_latch_en <='0'; + cmd_fifo_read_signal <='0'; + cmd_request_latch_en<='0'; + cmd_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request + cmd_data_out_pulse <= '1';--port_granted; --s'assurer que la dernière donnée est bien lue + cmd_priority_rotation <= '0'; + --cmd_data_signal<=Port_ID ; + cmd_data_signal<=Port_ID; + + when cmdend => + cmd_exec<='0'; + cmd_request_latch_en <= '0'; + cmd_pipeline_latch_en <= '0'; + cmd_fifo_read_signal <= '0'; + cmd_request_latch_en<='0'; + cmd_request_decoder_en <= '0'; + cmd_data_out_pulse <= '0'; + cmd_priority_rotation <= '1'; + cmd_data_signal<=(others=>'0'); + + +end case ; +end process cmdaffect; + +end Behavioral; + + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/INPUT_PORT_MODULE.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/INPUT_PORT_MODULE.vhd.bak (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/INPUT_PORT_MODULE.vhd.bak (revision 138) @@ -0,0 +1,878 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL/GAMOM Roland CHristian +-- +-- Create Date: 03:47:50 04/24/2011 +-- Design Name: +-- Module Name: INPUT_PORT_MODULE - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- Module de gestion des entrées des ports du switch crossbar +-- il supose qu'une donnée est empilée à chaque cycle d'horloge +-- Dependencies: +-- FIFO_64_FWFT.vhd +-- RAM_64.vhd +-- Revision: 1 +-- remplacement du fifo ordinaire par un fifo fwft +-- Revision 1.01 - File Created +-- Additional Comments: +-- modifié le 14/05/20011 pour eviter une écriture multiple dans le FIFO de sortie +-- si le FIFO d'entrée vient a se vider pendant le transfert d'un packet +-- le machine a état on été re modeliser et sont maintenant du type FSMD +-- remodéliation pour plus de vitesse +--inclusion du signal priority rotation pour eviter la perte du grant pendant une transmission +--02-08-2012 :Prise en compte du signal Port_Granted dans un process +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +USE ieee.numeric_std.ALL; +use work.Coretypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +entity INPUT_PORT_MODULE is + generic(number_of_ports : positive := 4; + + Port_num: natural:=1); -- port_num est l'id du port + Port ( data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + data_in_en : in STD_LOGIC; -- signaler la présence des données en entrée + cmd_in_en :in STD_LOGIC; --permet d'identifier les données qui sont dans le tampon + reset : in STD_LOGIC; + clk : in STD_LOGIC; + request : out STD_LOGIC_VECTOR (number_of_ports downto 1); --demande de canal de transmission + grant : in STD_LOGIC_VECTOR (number_of_ports downto 1); -- autorisation de transmission + fifo_full : out STD_LOGIC; -- signaler que les données ne peuvent plus être acceptées en entrée + fifo_empty : out STD_LOGIC; -- le tampon d'entrée est vide + priority_rotation : out std_logic; -- reserver le canal de transmission + data_out : out STD_LOGIC_VECTOR (Word-1 downto 0); --données vers le réseau crossbar + data_out_pulse : out std_logic); -- permet de ... + +end INPUT_PORT_MODULE; + +architecture Behavioral of INPUT_PORT_MODULE is + +-- declaration du fifo 64 octet utilisé pour chaque port +component FIFO_256_FWFT + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(Word-1 downto 0); + rd_en: IN std_logic; + srst: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(Word-1 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +end component; + +--definition du type etat pour les fsm +type fsm_states is (state0, CmdOn, WaitGrant, ReqPort, state1, state2,strecover,stpulse,stateErr, state3);-- definition du type etat pour le codage des etats des fsm +type fsm_states2 is(cmdstart,cmdwait,cmdread,cmdSetDest,cmdSetCount,cmdSetId,cmdpulse,CmdEnd); +signal pop_state : fsm_states; +signal cmdstate : fsm_states2; +signal cmd_exec : std_logic:='0'; --indique que le port est en train d'exécuter une commande +signal dat_exec :std_logic:='0'; -- indique le port est en train de transférer des données +signal dat_Err :std_logic:='0'; -- signal une erreur pendant l'exécution +signal wrok,readOk,CmdReadOk : std_logic:='0'; --indique s'il est possible de lire les données +-- signaux utilisés dans les fsm +signal request_decoder,req_grant : STD_LOGIC_VECTOR(number_of_ports downto 1); +signal request_decoder_en : std_logic; +signal request_latch : STD_LOGIC_VECTOR(4 downto 1):=(others=>'0'); -- pourquoi pas 3 downto 0 ? +signal request_latch_en : std_logic; +signal pipeline_latch : std_logic_vector(Word-1 downto 0); +signal pipeline_latch_en : std_logic; +signal request_word : std_logic_vector(5 downto 1); +signal port_granted : std_logic; +signal rd_en_signal : std_logic; +--signaux utilisés dans la MAE de gestion des commandes +signal cmd_request_latch_en :std_logic; +signal cmd_pipeline_latch_en :std_logic; +signal cmd_fifo_read_signal :std_logic; +signal cmd_request_decoder_en :std_logic; +signal cmd_data_out_pulse :std_logic; +signal cmd_priority_rotation :std_logic; +--signaux utilisés dans la MAE de transfert des données +signal dat_request_latch_en :std_logic; +signal dat_pipeline_latch_en :std_logic; +signal dat_fifo_read_signal :std_logic; +signal dat_request_decoder_en :std_logic; +signal dat_data_out_pulse :std_logic; +signal dat_priority_rotation :std_logic; +-- signaux utilisés pour les connections entre composants +signal clk_signal : std_logic; +signal reset_signal : std_logic; +signal fifo_empty_signal : std_logic; +signal fifo_read_signal : std_logic; +signal fifo_out_signal,cmd_data_signal : std_logic_vector(Word-1 downto 0); +signal push_dout : std_logic_vector(Word-1 downto 0); +signal empty_latch : std_logic ; +signal PORT_ID :std_logic_vector(Word-1 downto 0):=STD_LOGIC_VECTOR(to_unsigned(number_of_ports-1,4))& STD_LOGIC_VECTOR(to_unsigned(port_num-1,4)); +-- signaux du compteur de données +signal data_counter : std_logic_vector(Word-1 downto 0); + +begin +-- instantiation du FIFO_256 + INPUT_PORT_FIFO : FIFO_256_FWFT + port map ( + clk => clk_signal, + din => data_in, + rd_en => fifo_read_signal, + srst => reset_signal, + wr_en => data_in_en, + dout => fifo_out_signal, + empty => fifo_empty_signal, + full => fifo_full); +-- connections avec les ports de l'entité + +data_out <= pipeline_latch ;--when cmd_exec='0' else cmd_data_signal; +fifo_empty <= empty_latch; +reset_signal <= reset; +grant_proc:process(req_grant) +begin +--if rising_edge(clk) then +-- if unsigned(grant)> 0 then + if unsigned(req_grant) > 0 then + port_granted <= '1'; --il faut veiller à ce que ce port soit vraiment autorisé + else + Port_granted<='0'; --ceci présuppose que la valeur qu'il reçoit est forcément la sienne + end if; +--end if; +end process; +rd_en_signal <= fifo_empty_signal;--not(empty_latch) ; +request <= request_decoder; +reg_grant:process (request_decoder,grant) +begin +req_grant<=request_decoder and grant; +end process reg_grant; +request_word <= request_latch & request_decoder_en; +clk_signal <= clk; + + + +WITH cmd_exec SELECT + request_latch_en <= dat_request_latch_en WHEN '0', + cmd_request_latch_en WHEN others; + +WITH cmd_exec SELECT + pipeline_latch_en <= dat_pipeline_latch_en WHEN '0', + cmd_pipeline_latch_en WHEN others; + +WITH cmd_exec SELECT + fifo_read_signal <=dat_fifo_read_signal WHEN '0', + + cmd_fifo_read_signal WHEN others; +WITH cmd_exec SELECT + request_decoder_en <=dat_request_decoder_en WHEN '0', + cmd_request_decoder_en WHEN others; +WITH cmd_exec SELECT + data_out_pulse <=dat_data_out_pulse WHEN '0', + cmd_data_out_pulse WHEN others; +WITH cmd_exec SELECT + priority_rotation<=dat_priority_rotation WHEN '0', + cmd_priority_rotation WHEN others; + + +--processus permettant de latcher le signal empty +-- evite une perte de données en cas d'arret au cours d'une transmission +empty_latch_process : process(clk) +begin + if rising_edge(clk) then + if reset_signal = '1' then + empty_latch <= '1'; + else + empty_latch <= fifo_empty_signal; + end if; + end if; + +end process; +-- decodeur de requete en fonction de l'adresse destination +-- le circuit genere depend du parametre generique nombre de ports +-- switch 2 ports +switch2x2 : if number_of_ports = 2 generate + +with request_word select + request_decoder <="01" when "00001", + "10" when "00011", + "00" when others; + +end generate switch2x2; + + +-- switch 3 ports +switch3x3 : if number_of_ports = 3 generate + +with request_word select + request_decoder <="001" when "00001", + "010" when "00011", + "100" when "00101", + "000" when others; + +end generate switch3x3; + + +-- switch 4 ports +switch4x4 : if number_of_ports = 4 generate + +with request_word select + request_decoder <="0001" when "00001", + "0010" when "00011", + "0100" when "00101", + "1000" when "00111", + "0000" when others; + +end generate switch4x4; + + +-- switch 5 ports +switch5x5 : if number_of_ports = 5 generate + +with request_word select + request_decoder <="00001" when "00001", + "00010" when "00011", + "00100" when "00101", + "01000" when "00111", + "10000" when "01001", + "00000" when others; + +end generate switch5x5; + + +-- switch 6 ports +switch6x6 : if number_of_ports = 6 generate + +with request_word select + request_decoder <="000001" when "00001", + "000010" when "00011", + "000100" when "00101", + "001000" when "00111", + "010000" when "01001", + "100000" when "01011", + "000000" when others; + +end generate switch6x6; + + +-- switch 7 ports +switch7x7 : if number_of_ports = 7 generate + +with request_word select + request_decoder <="0000001" when "00001", + "0000010" when "00011", + "0000100" when "00101", + "0001000" when "00111", + "0010000" when "01001", + "0100000" when "01011", + "1000000" when "01101", + "0000000" when others; + +end generate switch7x7; + + +-- switch 8 ports +switch8x8 : if number_of_ports = 8 generate + +with request_word select + request_decoder <="00000001" when "00001", + "00000010" when "00011", + "00000100" when "00101", + "00001000" when "00111", + "00010000" when "01001", + "00100000" when "01011", + "01000000" when "01101", + "10000000" when "01111", + "00000000" when others; + +end generate switch8x8; + + +-- switch 9 ports +switch9x9 : if number_of_ports = 9 generate + +with request_word select + request_decoder <="000000001" when "00001", + "000000010" when "00011", + "000000100" when "00101", + "000001000" when "00111", + "000010000" when "01001", + "000100000" when "01011", + "001000000" when "01101", + "010000000" when "01111", + "100000000" when "10001", + "000000000" when others; + +end generate switch9x9; + + +-- switch 10 ports +switch10x10 : if number_of_ports = 10 generate + +with request_word select + request_decoder <="0000000001" when "00001", + "0000000010" when "00011", + "0000000100" when "00101", + "0000001000" when "00111", + "0000010000" when "01001", + "0000100000" when "01011", + "0001000000" when "01101", + "0010000000" when "01111", + "0100000000" when "10001", + "1000000000" when "10011", + "0000000000" when others; + +end generate switch10x10; + + +-- switch 11 ports +switch11x11 : if number_of_ports = 11 generate + +with request_word select + request_decoder <="00000000001" when "00001", + "00000000010" when "00011", + "00000000100" when "00101", + "00000001000" when "00111", + "00000010000" when "01001", + "00000100000" when "01011", + "00001000000" when "01101", + "00010000000" when "01111", + "00100000000" when "10001", + "01000000000" when "10011", + "10000000000" when "10101", + "00000000000" when others; + +end generate switch11x11; + + +-- switch 12 ports +switch12x12 : if number_of_ports = 12 generate + +with request_word select + request_decoder <="000000000001" when "00001", + "000000000010" when "00011", + "000000000100" when "00101", + "000000001000" when "00111", + "000000010000" when "01001", + "000000100000" when "01011", + "000001000000" when "01101", + "000010000000" when "01111", + "000100000000" when "10001", + "001000000000" when "10011", + "010000000000" when "10101", + "100000000000" when "10111", + "000000000000" when others; + +end generate switch12x12; + + +-- switch 13 ports +switch13x13 : if number_of_ports = 13 generate + +with request_word select + request_decoder <="0000000000001" when "00001", + "0000000000010" when "00011", + "0000000000100" when "00101", + "0000000001000" when "00111", + "0000000010000" when "01001", + "0000000100000" when "01011", + "0000001000000" when "01101", + "0000010000000" when "01111", + "0000100000000" when "10001", + "0001000000000" when "10011", + "0010000000000" when "10101", + "0100000000000" when "10111", + "1000000000000" when "11001", + "0000000000000" when others; + +end generate switch13x13; + + +-- switch 14 ports +switch14x14 : if number_of_ports = 14 generate + +with request_word select + request_decoder <="00000000000001" when "00001", + "00000000000010" when "00011", + "00000000000100" when "00101", + "00000000001000" when "00111", + "00000000010000" when "01001", + "00000000100000" when "01011", + "00000001000000" when "01101", + "00000010000000" when "01111", + "00000100000000" when "10001", + "00001000000000" when "10011", + "00010000000000" when "10101", + "00100000000000" when "10111", + "01000000000000" when "11001", + "10000000000000" when "11011", + "00000000000000" when others; + +end generate switch14x14; + + +-- switch 15 ports +switch15x15 : if number_of_ports = 15 generate + +with request_word select + request_decoder <="000000000000001" when "00001", + "000000000000010" when "00011", + "000000000000100" when "00101", + "000000000001000" when "00111", + "000000000010000" when "01001", + "000000000100000" when "01011", + "000000001000000" when "01101", + "000000010000000" when "01111", + "000000100000000" when "10001", + "000001000000000" when "10011", + "000010000000000" when "10101", + "000100000000000" when "10111", + "001000000000000" when "11001", + "010000000000000" when "11011", + "100000000000000" when "11101", + "000000000000000" when others; + +end generate switch15x15; + + +-- switch 16 ports +switch16x16 : if number_of_ports = 16 generate + +with request_word select + request_decoder <="0000000000000001" when "00001", + "0000000000000010" when "00011", + "0000000000000100" when "00101", + "0000000000001000" when "00111", + "0000000000010000" when "01001", + "0000000000100000" when "01011", + "0000000001000000" when "01101", + "0000000010000000" when "01111", + "0000000100000000" when "10001", + "0000001000000000" when "10011", + "0000010000000000" when "10101", + "0000100000000000" when "10111", + "0001000000000000" when "11001", + "0010000000000000" when "11011", + "0100000000000000" when "11101", + "1000000000000000" when "11111", + "0000000000000000" when others; + +end generate switch16x16; +--latch du fifo de sortie ?? +pipeline_latch_process : process(clk) +begin + if rising_edge(clk) then + if reset_signal = '1' then + pipeline_latch <= (others => '0'); + elsif pipeline_latch_en = '1' and cmd_exec='0' then + pipeline_latch <= push_dout; + elsif pipeline_latch_en = '1' and cmd_exec='1' then + pipeline_latch <= cmd_data_signal; + end if; + end if; +end process; + +--latch qui memorise l'adresse de destination du packet + +request_latch_process : process(clk) +begin + if rising_edge(clk) then + if reset_signal = '1' then + request_latch <= (others => '0'); + elsif request_latch_en = '1' and cmd_in_en='0' then --si la lecture de la destination est autorisée + request_latch <=fifo_out_signal(3 downto 0); --fifo_out_signal(3) & fifo_out_signal(2) & fifo_out_signal(1) & fifo_out_signal(0); + assert (unsigned(fifo_out_signal(3 downto 0)) '0'); + elsif cmd_exec='0' then --il ne faut pas exécuter cette MAE + -- lorsque l'autre est en cours + wrok<='0'; + case pop_state is + when state0 => if cmd_in_en='0' then --il ne faut pas exécuter les deux MAE ... + if empty_latch ='0' then -- pile pas vide on doit dépiler + pop_state <= WaitGrant; + end if; + else + pop_state <= CmdOn; + end if; + when CmdOn => if empty_latch='1' and cmd_in_en='0' then + pop_state <= state0; + elsif empty_latch='0' and cmd_in_en='1' then + pop_state <= CmdOn; + elsif empty_latch='1' and cmd_in_en='1' then + pop_state <= state0; + else -- empty_latch='0' and cmd_in_en='0' + pop_state <= WaitGrant; + end if; + + when WaitGrant => if port_granted = '1' then + -- + pop_state <= ReqPort; + end if; + + when ReqPort => --if port_granted = '1' then + -- + pop_state <= state1; + + --end if; + + when state1 => if port_granted ='1' then --lecture de la longueur des données + data_counter <= fifo_out_signal; + if unsigned(fifo_out_signal)<=3 then + ReadOk<='1'; + else + readOk<='1'; + end if; + pop_state <= state2; + wrok<='1'; + else + wrok<='0'; + end if; + + when state2 => if port_granted='1' then + wrok<='1'; + if fifo_empty_signal ='0' then + if rd_en_signal ='1' and unsigned(data_counter)<= 3 then + data_counter <= data_counter - 1; + pop_state <= stpulse; + ReadOk<='1'; + elsif rd_en_signal ='1' then + data_counter <= data_counter - 1; + pop_state <= state2; + ReadOk<='1'; + else --fifo_empty_signal='1' fin prématurée de la lecture + ReadOk<='0'; + wrok<='0'; + --pop_state<=stateErr; + --data_counter<=(others => '0'); + end if; + else + pop_state<=strecover; + data_counter <= data_counter + 1; + report "Input_port_module : Le fifo d'entrée du port " & integer'image(to_integer(unsigned(Port_id(3 downto 0))+1)) & " est vide !!!"; + wrok<='0'; + readok<='0'; + end if; + else + wrOk<='0'; + readok<='0'; + report "Input_port_module : Le fifo de réception du port " & integer'image(to_integer(unsigned(request_latch)+1)) & " est probablement plein !!!"; + pop_state<=strecover; + data_counter <= data_counter + 1; + end if; + when strecover => if fifo_empty_signal='0' and port_granted='1' then + pop_state<=state2; + readok<='0'; + wrok<='0'; + else + readok<='0'; + wrok<='0'; + end if; + + + when stpulse => if port_granted='1' then + pop_state <= state3; --pousser la dernière donnée dehors + data_counter <= data_counter - 1; + wrok<='1'; + end if; + wrok<='0'; + when state3 => wrok<='0'; + data_counter <= data_counter - 1; + pop_state <= state0; + when stateErr => wrok<='0'; + data_counter <= data_counter; + pop_state <= stateErr; + report "Error in the NoC when sending data " ; + when others => pop_state <= state0; + wrok<='0'; + end case; + end if; + end if; +end process; + +-- actions associées à chaque etat de la fsm de mealy +pop_fsm_action : process(pop_state, fifo_out_signal,empty_latch, rd_en_signal,readok, port_granted ) + begin +-- code fonctionnel + case pop_state is + when state0 => dat_request_latch_en <= '0'; + dat_pipeline_latch_en <= '0'; + dat_fifo_read_signal <='0'; + dat_request_decoder_en <= '0'; + dat_data_out_pulse <= '0'; + dat_priority_rotation <= '1'; + dat_exec<='0'; + dat_Err<='0'; + push_dout<=fifo_out_signal; + + when CmdOn => dat_request_latch_en <= '0'; + dat_pipeline_latch_en <= '0'; + dat_fifo_read_signal <='0'; + dat_request_decoder_en <= '0'; + dat_data_out_pulse <= '0'; + dat_priority_rotation <= '1'; + dat_exec<='0'; + dat_Err<='0'; + push_dout<=fifo_out_signal; + when WaitGrant => + dat_request_latch_en <='1'; --autoriser l'identification du port de destination + dat_pipeline_latch_en <= '0'; --pour le transmettre à travers le réseau + dat_fifo_read_signal <= '0'; + dat_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request + dat_data_out_pulse <= '0'; --transmettre le signal pour le dernier mot + dat_priority_rotation <= Port_granted; --dès qu'on a la priorité on la garde + dat_exec<='1'; + dat_Err<='0'; + push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0); + when ReqPort => + dat_request_latch_en <='1'; --autoriser l'identification du port de destination + dat_pipeline_latch_en <= '1'; --pour le transmettre à travers le réseau + dat_fifo_read_signal <= '1'; + dat_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request + dat_data_out_pulse <= '0'; --transmettre le signal pour le dernier mot + dat_priority_rotation <= '0'; + dat_exec<='1'; + dat_Err<='0'; + push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0); + + when state1 => dat_request_latch_en <= '0'; + dat_pipeline_latch_en <= rd_en_signal and port_granted; + dat_fifo_read_signal <= rd_en_signal and port_granted; + dat_request_decoder_en <= '1'; + dat_data_out_pulse <= port_granted; + dat_priority_rotation <= '0'; + dat_exec<='1'; + dat_Err<='0'; + push_dout<=fifo_out_signal; + + when state2 |strecover => dat_request_latch_en <= '0'; + dat_pipeline_latch_en <= port_granted and wrok and not(fifo_empty_signal); --autoriser la lecture du fifo en sortie + dat_fifo_read_signal <= port_granted and readok; + dat_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request + dat_data_out_pulse <= port_granted and wrOk and not(fifo_empty_signal); + dat_priority_rotation <= '0'; + dat_exec<='1'; + dat_Err<='0'; + push_dout<=fifo_out_signal; + + when stpulse => dat_request_latch_en <= '0'; --pousser la dernière donnée + dat_pipeline_latch_en <= '0'; --autoriser la lecture du fifo en sortie + dat_fifo_read_signal <='0'; + dat_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request + dat_data_out_pulse <= '1'; -- pousser le dernier mot + dat_priority_rotation <= '0'; + dat_exec<='1'; + dat_Err<='0'; + push_dout<=fifo_out_signal; + + when state3 => dat_request_latch_en <= '0'; + dat_pipeline_latch_en <= '0'; + dat_priority_rotation <= '1'; -- libérer la priorité + dat_fifo_read_signal <= '0'; + dat_request_decoder_en <= '0'; --libérer le décodeur + dat_data_out_pulse <= '0'; + dat_exec<='0'; + dat_Err<='0'; + push_dout<=fifo_out_signal; + when stateErr => dat_request_latch_en <= '0'; + dat_pipeline_latch_en <= '0'; + dat_priority_rotation <= '1'; -- libérer la priorité + dat_fifo_read_signal <= '0'; + dat_request_decoder_en <= '0'; --libérer le décodeur + dat_data_out_pulse <= '0'; + dat_exec<='1'; + dat_Err<='1'; + push_dout<=fifo_out_signal; + when others => dat_request_latch_en <= '0'; + dat_pipeline_latch_en <= '0'; + dat_priority_rotation <= '1'; + dat_fifo_read_signal <= '0'; + dat_request_decoder_en <= '0'; + dat_data_out_pulse <= '0'; + dat_exec<='0'; + dat_Err<='0'; + push_dout<=fifo_out_signal; + + end case; + end process; + -- traitement des commandes reçues par le switch +fsm_cmd:process(clk,cmd_in_en) +variable timeout : natural:=0; +variable cmdcode : natural range 0 to 255; +begin +if rising_edge(clk) then + if reset_signal = '1' then + cmdstate<=cmdstart; + else -- il ne faut pas traiter les cmdes et les données en même temps + case cmdstate is + + when cmdstart => + if cmd_in_en='1' and dat_exec='0' and empty_latch='0' then + cmdstate<=cmdread; + end if; + cmdReadOk<='0'; + when cmdwait => if port_granted='1' then -- demande du port de sortie + + cmdstate<=cmdsetdest; + elsif cmd_in_en='1' then + cmdstate<=cmdwait; + else + cmdstate<=cmdstart; + end if; + cmdReadOk<='0'; + when cmdread => +-- if port_granted ='1'then -- ne pas modifier l'état des priorités si on ne l'avait pas + cmdcode:= to_integer(unsigned(fifo_out_signal)); + if cmdcode=1 then --code de getportid + cmdstate<=cmdwait; + cmdReadOk<='1'; + else + --ne pas prendre le code inconnu en compte + cmdstate<=cmdend; -- la commande n'a pas été reconnu + + cmdReadOk<='0'; + end if; +-- end if; + when cmdsetdest => + if port_granted='1' then + cmdstate<=cmdsetcount; + end if; + cmdReadOk<='0'; + when cmdsetcount => + if port_granted='1' then + cmdstate<=cmdsetID; + else + cmdstate<=cmdsetdest; + end if; + cmdReadOk<='0'; + when cmdsetID=> + if port_granted='1' then + cmdstate <=cmdpulse; + end if; + cmdReadOk<='0'; + when cmdpulse => + if port_granted='1' then + cmdstate <=cmdEnd; + end if; + cmdReadOk<='0'; + when cmdend => + if cmd_in_en='0' then --éviter l'exécution en boucle + cmdstate<=cmdstart; + end if; + cmdReadOk<='0'; + + end case; + end if; +end if; +end process fsm_cmd; + +cmdaffect:process (cmdstate,fifo_empty_signal, port_granted, PORT_ID) +begin +case cmdstate is + + when cmdstart => + cmd_exec<='0'; + cmd_pipeline_latch_en <='0'; + cmd_priority_rotation <= '1'; + cmd_request_latch_en<='0'; + cmd_fifo_read_signal <= '0'; + cmd_request_decoder_en <= '0'; + cmd_data_signal<=(others=>'0'); + cmd_data_out_pulse <= '0'; + + when cmdread => + cmd_exec<='1'; + cmd_pipeline_latch_en <= '0'; + cmd_fifo_read_signal <= '1'; -- vider le tampon d'entrée + cmd_request_latch_en<='1'; --mémoriser l'adresse de destination + cmd_request_decoder_en <= '1'; --demande d'émission + cmd_data_out_pulse <= '0'; + cmd_priority_rotation <= '1'; --sans priorité + cmd_data_signal<=Port_ID; + when cmdwait => + cmd_exec<='1'; + cmd_pipeline_latch_en <='0'; + cmd_fifo_read_signal <= '0'; + cmd_request_latch_en<='1'; + cmd_priority_rotation <= '0'; --avec priorité + cmd_request_decoder_en <= '1'; --demande d'émission + cmd_data_signal<=Port_ID; + cmd_data_out_pulse <= '0'; + when cmdsetdest => + --cmd_request_decoder_en <= '1'; + cmd_exec<='1'; + cmd_pipeline_latch_en <='1'; --empiler dans le tampon de sortie la donnée + cmd_fifo_read_signal <='0'; + cmd_request_latch_en<='0'; + cmd_request_decoder_en <= '1'; --autoriser le decodeur à activer le dernier bit de request + cmd_data_out_pulse <= '0'; + cmd_priority_rotation <= '0'; + cmd_data_signal<=Port_ID; -- le numéro du port et le nombre total des ports est envoyé + when cmdsetcount => + + cmd_exec<='1'; + cmd_pipeline_latch_en <='1'; -- empiler dans le tampon de sortie les données + cmd_fifo_read_signal <='0'; + cmd_request_latch_en<='0'; --enregistrer l'adresse de destination + cmd_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request + cmd_data_out_pulse <= port_granted; + cmd_priority_rotation <= '0'; + cmd_data_signal<=STD_LOGIC_VECTOR(to_unsigned(3,8)); + when cmdSetId => + --cmd_request_decoder_en <= '1'; + cmd_exec<='1'; + cmd_pipeline_latch_en <='1'; + cmd_fifo_read_signal <='0'; + cmd_request_latch_en<='0'; --enregistrer l'adresse de destination + cmd_request_decoder_en <= '1'; --autoriser le decodeur à activer le dernier bit de request + cmd_data_out_pulse <= port_granted; + cmd_priority_rotation <= '0'; + cmd_data_signal<=Port_ID; -- le numéro du port et le nombre total des ports est envoyé + + when cmdpulse => cmd_exec<='1'; + cmd_pipeline_latch_en <='0'; + cmd_fifo_read_signal <='0'; + cmd_request_latch_en<='0'; + cmd_request_decoder_en <= '1'; --autoriser le decodeur activer le dernier bit de request + cmd_data_out_pulse <= '1';--port_granted; --s'assurer que la dernière donnée est bien lue + cmd_priority_rotation <= '0'; + --cmd_data_signal<=Port_ID ; + cmd_data_signal<=Port_ID; + + when cmdend => + cmd_exec<='0'; + cmd_request_latch_en <= '0'; + cmd_pipeline_latch_en <= '0'; + cmd_fifo_read_signal <= '0'; + cmd_request_latch_en<='0'; + cmd_request_decoder_en <= '0'; + cmd_data_out_pulse <= '0'; + cmd_priority_rotation <= '1'; + cmd_data_signal<=(others=>'0'); + + +end case ; +end process cmdaffect; + +end Behavioral; + + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/OUTPUT_PORT_MODULE.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/OUTPUT_PORT_MODULE.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/OUTPUT_PORT_MODULE.vhd (revision 138) @@ -0,0 +1,248 @@ + +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:29:48 04/18/2011 +-- Design Name: +-- Module Name: OUTPUT_PORT_MODULE - Behavioral_description +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- cette version du module de sortie se limite à une instance du fifo ordinaire +-- les données son emise en sortie à chaque cycle d'horloge +-- Dependencies: +-- +-- Revision: 07-08-2013 +-- Revision 0.01 - File Created +-- Additional Comments: Ajout d'un délai pour ignorer les paquets qui sont là depuis +-- longtemps +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--use IEEE.STD_LOGIC_ARITH.ALL; +--use IEEE.STD_LOGIC_UNSIGNED.ALL; +USE ieee.numeric_std.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity OUTPUT_PORT_MODULE is + Port ( data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + reset : in STD_LOGIC; + clk : in STD_LOGIC; + wr_en : in STD_LOGIC; + data_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_full : out std_logic; + data_avalaible : out std_logic; + rd_out_en : in STD_LOGIC); +end OUTPUT_PORT_MODULE; + +architecture Behavioral_description of OUTPUT_PORT_MODULE is +-- declaration du FIFO 64 octets +component FIFO_256_FWFT + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(Word-1 downto 0); + rd_en: IN std_logic; + srst: IN std_logic; + wr_en: IN std_logic; + dout: out std_logic_VECTOR(Word-1 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +end component; +--definition du type etat pour les fsm +type typ_outfsm is (Idle,waiting,dropping,reading); +type typ_receiv is (r_wait,r_head,r_len,r_glen,r_data,r_pulse,r_end); + +signal EtRec : typ_receiv; +signal Et_out_fsm : typ_outfsm; +signal fifo_empty : std_logic; +signal sw : std_logic:='0'; -- permet de positionner le mux sur les signaux internes +signal tlimit : natural:=0; --permet de compter les impulsions de temps +signal n : natural:=0; --utiliser pour la mae du tampon de sortie +signal rcv_start : std_logic; --début de la réception +signal rcv_ack : std_logic; -- acquittement de la réception +signal rcv_comp : std_logic; -- fin de la réception +signal spop,pop,rd_en,dat_avail : std_logic:='0'; +signal mem,fifo_out : std_logic_vector(Word-1 downto 0); --variable tampon sans intérêt réel +begin +-- instantiation du FIFO_64 + OUTPUT_PORT_FIFO : FIFO_256_FWFT + port map ( + clk => clk, + din => data_in, + rd_en => rd_en, + srst => reset, + wr_en => wr_en, + dout => fifo_out, + empty => fifo_empty, + full => fifo_full); + + +outport_proc : process(clk,reset,fifo_empty) +begin +if rising_edge(clk) then +if reset='1' then +n<=0; +Et_out_fsm<=Idle; +else +case(Et_out_fsm) is + +when Idle => --idle + if fifo_empty = '0' then + Et_Out_fsm<=waiting; + end if; + tlimit<=0; + sw<='0'; +when reading => +if rd_out_en='0' then + Et_out_fsm<=Idle; +end if; +sw<='0'; +when waiting => --counting +if rd_out_en='1' then + Et_out_fsm<=reading; +elsif tlimit=5000 then + Et_out_fsm<=dropping; + tlimit<=0; +else + tlimit<=tlimit+1; +end if; +sw<='0'; +when dropping => --dropping packet + if n=0 then + rcv_start<='1'; + n<=1; + sw<='1'; + elsif n=1 then + if rcv_comp='1' then + rcv_ack<='1'; + rcv_start<='0'; + n<=2; + end if; + sw<='1'; + elsif n=2 then + sw<='0'; + Et_out_fsm<=Idle; + report "Attention Paquet perdu !à Output_Port_Module"; + n<=0; + end if; + +end case; +end if; +end if; +end process outport_proc; +data_out<=fifo_out; +mux_proc : process (sw,rd_out_en,pop,fifo_empty) +begin +if sw='1' then --mode drop + rd_en<=pop; + data_avalaible <='0'; --plus de données dans le tampon ! +else + rd_en<=rd_out_en; + data_avalaible <= not fifo_empty; +end if; +end process mux_proc; +proc_receiv : process (clk,reset) +variable dlen,i: natural range 0 to 255 :=0; + + begin + if reset='1' then + etrec<=r_wait; + + else + if rising_edge(clk) then -- le process s'exécute sur chaque front + -- montant de l'horloge + case etrec is + when r_wait => + + i:=0; + if fifo_empty='0' and rcv_start='1' then + + etrec<=r_head; + mem<=fifo_out; + + end if; + when r_head => + mem<=fifo_out; --l'en-tête + + etrec<=r_len; + when r_len => + dlen:=to_integer(unsigned(fifo_out)); + mem<=fifo_out; -- la longueur + + if dlen>2 then + etrec<=r_data; + else + etrec<=r_end; + end if; + i:=1; + + when r_data => + if fifo_empty='0' then + if i + etrec<=r_end; + + when r_end => + if rcv_ack='1' then + etrec<=r_wait; + end if; + + when others => + + + etrec<=r_wait; + end case; + end if; + end if; + end process; + + pop<=spop; + +rec_value : process (etrec) +begin +case etrec is + when r_wait => + spop<='0'; + rcv_comp<='0'; + when r_head => + + spop<='1'; + rcv_comp<='0'; + + when r_len => + spop<='1'; + when r_data => + spop<='1'; + when r_pulse => + spop<='0'; + rcv_comp<='1'; + when r_end => + spop<='0'; + rcv_comp<='1'; + when others => + spop<='0'; + rcv_comp<='0'; + end case; + end process; + +end Behavioral_description; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/PortRam.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/PortRam.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/PortRam.vhd (revision 138) @@ -0,0 +1,74 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM NGOUNOU ROland Christian +-- +-- Create Date: 12:49:02 02/02/2012 +-- Design Name: +-- Module Name: Portdata - arch_portdata +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use ieee.numeric_std.all; +--USE ieee.std_logic_arith.all; + + +entity Portdata is +generic (N:Natural:=8); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + datain : in STD_LOGIC_VECTOR (N-1 downto 0); + dataout : out STD_LOGIC_VECTOR (N-1 downto 0); + address : in STD_LOGIC_VECTOR (3 downto 0)); +end Portdata; + +architecture arch_portdata of Portdata is + +Type Ram_type is array (0 to 3) of std_logic_vector (N-1 downto 0); +constant zero : integer :=0; +constant Zero_log:STD_LOGIC_VECTOR:=STD_LOGIC_VECTOR(to_unsigned(zero,N)); +constant portid:STD_LOGIC_VECTOR:="00000001"; +signal RAM : Ram_type; + +constant max_address : natural:=15; +signal address_counter : natural := 0; +begin + +dataout <= RAM(address_counter); +process (clk) + begin + if rising_edge(clk) then + if reset = '1' then + address_counter <= 0; + for address_counter in 1 to max_address --la mémoire d'adresse 0 contient + loop -- l'ID du port + RAM(address_counter)<=(others=>'0'); + end loop; + RAM(0)<=portid; -- portid est une valeur fixé par le générateur de port + elsif rd_en='1' and wr_en='0' then + + RAM(to_integer(unsigned(address)))<=datain; + + elsif rd_en='0' and wr_en='1' then + dataout <= RAM(to_integer(unsigned(address))); + + end if; + end if; + end process; +end arch_portdata; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Proto_receiv.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Proto_receiv.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Proto_receiv.vhd (revision 138) @@ -0,0 +1,153 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 17:03:41 10/22/2012 +-- Design Name: +-- Module Name: Proto_receiv - ReceiveProto +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +use work.CoreTypes.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Proto_receiv is + generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_empty,fifo_full : in std_logic; + rcv_start : in std_logic; --début de la réception + rcv_ack :in std_logic; -- acquittement de la réception + rcv_comp : out std_logic; -- fin de la réception + pop : out std_logic:='0'; + fifo_out : in std_logic_vector(Word-1 downto 0); + mem :out memory(0 to sizemem-1)); +end Proto_receiv; + +architecture ReceiveProto of Proto_receiv is +type typ_receiv is (r_wait,r_head,r_len,r_glen,r_data,r_pulse,r_end); + + signal spush,spop : std_logic:='0'; + SIGNAL data_in: std_logic_vector(7 downto 0); + signal etrec :typ_receiv; +begin + +proc_receiv : process (clk,reset) +variable dlen,i: natural range 0 to 255 :=0; + + begin + if reset='1' then + etrec<=r_wait; + + else + if rising_edge(clk) then -- le process s'exécute sur chaque front + -- montant de l'horloge + case etrec is + when r_wait => + + i:=0; + if fifo_empty='0' and rcv_start='1' then + + etrec<=r_head; + mem(0)<=fifo_out; + + end if; + when r_head => + mem(0)<=fifo_out; --l'en-tête + + etrec<=r_len; + + + when r_len => + dlen:=to_integer(unsigned(fifo_out)); + mem(1)<=fifo_out; -- la longueur + + if dlen>2 then + etrec<=r_data; + else + etrec<=r_end; + end if; + i:=1; + + when r_data => + if fifo_empty='0' then + if i + etrec<=r_end; + + when r_end => + if rcv_ack='1' then + etrec<=r_wait; + end if; + + when others => + + + etrec<=r_wait; + end case; + end if; + end if; + end process; + + pop<=spop; + +rec_value : process (etrec) +begin +case etrec is + when r_wait => + spop<='0'; + rcv_comp<='0'; + when r_head => + + spop<='1'; + rcv_comp<='0'; +-- when r_sync => +-- spop<='1'; +-- rcv_comp<='0'; + when r_len => + spop<='1'; + when r_data => + spop<='1'; + when r_pulse => + spop<='0'; + rcv_comp<='1'; + when r_end => + spop<='0'; + rcv_comp<='1'; + when others => + spop<='0'; + rcv_comp<='0'; + end case; + end process; +end ReceiveProto; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/RAM_256.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/RAM_256.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/RAM_256.vhd (revision 138) @@ -0,0 +1,68 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 18:54:08 04/19/2011 +-- Design Name: +-- Module Name: RAM_64 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: SYNTHESE d'une RAM 256 octet par inferation +-- la ram possède un port d'écriture et un port de lecture +-- le port primaire est à lecture et ecrite et le port secondaire à lecture seule +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--Library NocLib; +--use NocLib.CoreTypes.all; +use work.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RAM_256 is + Port ( clka, clkb : in std_logic; + wea : in std_logic; + ena, enb : in std_logic; + addra, addrb : in std_logic_vector(Word-1 downto 0); + dia : in std_logic_vector(Word-1 downto 0); + dob : out std_logic_vector(Word-1 downto 0)); +end RAM_256; + +architecture Behavioral of RAM_256 is + type ram_type is array (255 downto 0) of std_logic_vector (Word-1 downto 0); + signal RAM: ram_type; +begin + process (clka) + begin + if clka'event and clka = '1' then + if ena = '1' then + if wea = '1' then + RAM(conv_integer(addra)) <= dia; + end if; + end if; + end if; + end process; + + process (clkb) + begin + if clkb'event and clkb = '1' then + if enb = '1' then + dob <= RAM(conv_integer(addrb)) ; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER10_10.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER10_10.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER10_10.VHD (revision 138) @@ -0,0 +1,1212 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler10_10 is + Port ( Request : in STD_LOGIC_VECTOR (100 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (10 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (10 downto 1); + port_grant : out STD_LOGIC_VECTOR (100 downto 1)); +end Scheduler10_10; + +architecture Behavioral of Scheduler10_10 is +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(19 downto 1) of STD_LOGIC_VECTOR(10 downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (19 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(100 downto 1); + signal priority_rotation_en : std_logic; + signal Grant : std_logic_vector(100 downto 1); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet + priority_rotation_en <= '1' when unsigned(priority_rotation) = 1023 else '0'; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + elsif priority_rotation_en = '1' then + grant_latch <= Grant; + end if; + end if; + end process; + port_grant <= Grant and grant_latch; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(11)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(12)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(13)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) or Signal_grant(14)(4); -- Grant(1,4) +Grant(5) <= Signal_grant(5)(5) or Signal_grant(15)(5); -- Grant(1,5) +Grant(6) <= Signal_grant(6)(6) or Signal_grant(16)(6); -- Grant(1,6) +Grant(7) <= Signal_grant(7)(7) or Signal_grant(17)(7); -- Grant(1,7) +Grant(8) <= Signal_grant(8)(8) or Signal_grant(18)(8); -- Grant(1,8) +Grant(9) <= Signal_grant(9)(9) or Signal_grant(19)(9); -- Grant(1,9) +Grant(10) <= Signal_grant(10)(10) ; -- Grant(1,10) +Grant(11) <= Signal_grant(2)(1) or Signal_grant(12)(1); -- Grant(2,1) +Grant(12) <= Signal_grant(3)(2) or Signal_grant(13)(2); -- Grant(2,2) +Grant(13) <= Signal_grant(4)(3) or Signal_grant(14)(3); -- Grant(2,3) +Grant(14) <= Signal_grant(5)(4) or Signal_grant(15)(4); -- Grant(2,4) +Grant(15) <= Signal_grant(6)(5) or Signal_grant(16)(5); -- Grant(2,5) +Grant(16) <= Signal_grant(7)(6) or Signal_grant(17)(6); -- Grant(2,6) +Grant(17) <= Signal_grant(8)(7) or Signal_grant(18)(7); -- Grant(2,7) +Grant(18) <= Signal_grant(9)(8) or Signal_grant(19)(8); -- Grant(2,8) +Grant(19) <= Signal_grant(10)(9) ; -- Grant(2,9) +Grant(20) <= Signal_grant(1)(10) or Signal_grant(11)(10); -- Grant(2,10) +Grant(21) <= Signal_grant(3)(1) or Signal_grant(13)(1); -- Grant(3,1) +Grant(22) <= Signal_grant(4)(2) or Signal_grant(14)(2); -- Grant(3,2) +Grant(23) <= Signal_grant(5)(3) or Signal_grant(15)(3); -- Grant(3,3) +Grant(24) <= Signal_grant(6)(4) or Signal_grant(16)(4); -- Grant(3,4) +Grant(25) <= Signal_grant(7)(5) or Signal_grant(17)(5); -- Grant(3,5) +Grant(26) <= Signal_grant(8)(6) or Signal_grant(18)(6); -- Grant(3,6) +Grant(27) <= Signal_grant(9)(7) or Signal_grant(19)(7); -- Grant(3,7) +Grant(28) <= Signal_grant(10)(8) ; -- Grant(3,8) +Grant(29) <= Signal_grant(1)(9) or Signal_grant(11)(9); -- Grant(3,9) +Grant(30) <= Signal_grant(2)(10) or Signal_grant(12)(10); -- Grant(3,10) +Grant(31) <= Signal_grant(4)(1) or Signal_grant(14)(1); -- Grant(4,1) +Grant(32) <= Signal_grant(5)(2) or Signal_grant(15)(2); -- Grant(4,2) +Grant(33) <= Signal_grant(6)(3) or Signal_grant(16)(3); -- Grant(4,3) +Grant(34) <= Signal_grant(7)(4) or Signal_grant(17)(4); -- Grant(4,4) +Grant(35) <= Signal_grant(8)(5) or Signal_grant(18)(5); -- Grant(4,5) +Grant(36) <= Signal_grant(9)(6) or Signal_grant(19)(6); -- Grant(4,6) +Grant(37) <= Signal_grant(10)(7) ; -- Grant(4,7) +Grant(38) <= Signal_grant(1)(8) or Signal_grant(11)(8); -- Grant(4,8) +Grant(39) <= Signal_grant(2)(9) or Signal_grant(12)(9); -- Grant(4,9) +Grant(40) <= Signal_grant(3)(10) or Signal_grant(13)(10); -- Grant(4,10) +Grant(41) <= Signal_grant(5)(1) or Signal_grant(15)(1); -- Grant(5,1) +Grant(42) <= Signal_grant(6)(2) or Signal_grant(16)(2); -- Grant(5,2) +Grant(43) <= Signal_grant(7)(3) or Signal_grant(17)(3); -- Grant(5,3) +Grant(44) <= Signal_grant(8)(4) or Signal_grant(18)(4); -- Grant(5,4) +Grant(45) <= Signal_grant(9)(5) or Signal_grant(19)(5); -- Grant(5,5) +Grant(46) <= Signal_grant(10)(6) ; -- Grant(5,6) +Grant(47) <= Signal_grant(1)(7) or Signal_grant(11)(7); -- Grant(5,7) +Grant(48) <= Signal_grant(2)(8) or Signal_grant(12)(8); -- Grant(5,8) +Grant(49) <= Signal_grant(3)(9) or Signal_grant(13)(9); -- Grant(5,9) +Grant(50) <= Signal_grant(4)(10) or Signal_grant(14)(10); -- Grant(5,10) +Grant(51) <= Signal_grant(6)(1) or Signal_grant(16)(1); -- Grant(6,1) +Grant(52) <= Signal_grant(7)(2) or Signal_grant(17)(2); -- Grant(6,2) +Grant(53) <= Signal_grant(8)(3) or Signal_grant(18)(3); -- Grant(6,3) +Grant(54) <= Signal_grant(9)(4) or Signal_grant(19)(4); -- Grant(6,4) +Grant(55) <= Signal_grant(10)(5) ; -- Grant(6,5) +Grant(56) <= Signal_grant(1)(6) or Signal_grant(11)(6); -- Grant(6,6) +Grant(57) <= Signal_grant(2)(7) or Signal_grant(12)(7); -- Grant(6,7) +Grant(58) <= Signal_grant(3)(8) or Signal_grant(13)(8); -- Grant(6,8) +Grant(59) <= Signal_grant(4)(9) or Signal_grant(14)(9); -- Grant(6,9) +Grant(60) <= Signal_grant(5)(10) or Signal_grant(15)(10); -- Grant(6,10) +Grant(61) <= Signal_grant(7)(1) or Signal_grant(17)(1); -- Grant(7,1) +Grant(62) <= Signal_grant(8)(2) or Signal_grant(18)(2); -- Grant(7,2) +Grant(63) <= Signal_grant(9)(3) or Signal_grant(19)(3); -- Grant(7,3) +Grant(64) <= Signal_grant(10)(4) ; -- Grant(7,4) +Grant(65) <= Signal_grant(1)(5) or Signal_grant(11)(5); -- Grant(7,5) +Grant(66) <= Signal_grant(2)(6) or Signal_grant(12)(6); -- Grant(7,6) +Grant(67) <= Signal_grant(3)(7) or Signal_grant(13)(7); -- Grant(7,7) +Grant(68) <= Signal_grant(4)(8) or Signal_grant(14)(8); -- Grant(7,8) +Grant(69) <= Signal_grant(5)(9) or Signal_grant(15)(9); -- Grant(7,9) +Grant(70) <= Signal_grant(6)(10) or Signal_grant(16)(10); -- Grant(7,10) +Grant(71) <= Signal_grant(8)(1) or Signal_grant(18)(1); -- Grant(8,1) +Grant(72) <= Signal_grant(9)(2) or Signal_grant(19)(2); -- Grant(8,2) +Grant(73) <= Signal_grant(10)(3) ; -- Grant(8,3) +Grant(74) <= Signal_grant(1)(4) or Signal_grant(11)(4); -- Grant(8,4) +Grant(75) <= Signal_grant(2)(5) or Signal_grant(12)(5); -- Grant(8,5) +Grant(76) <= Signal_grant(3)(6) or Signal_grant(13)(6); -- Grant(8,6) +Grant(77) <= Signal_grant(4)(7) or Signal_grant(14)(7); -- Grant(8,7) +Grant(78) <= Signal_grant(5)(8) or Signal_grant(15)(8); -- Grant(8,8) +Grant(79) <= Signal_grant(6)(9) or Signal_grant(16)(9); -- Grant(8,9) +Grant(80) <= Signal_grant(7)(10) or Signal_grant(17)(10); -- Grant(8,10) +Grant(81) <= Signal_grant(9)(1) or Signal_grant(19)(1); -- Grant(9,1) +Grant(82) <= Signal_grant(10)(2) ; -- Grant(9,2) +Grant(83) <= Signal_grant(1)(3) or Signal_grant(11)(3); -- Grant(9,3) +Grant(84) <= Signal_grant(2)(4) or Signal_grant(12)(4); -- Grant(9,4) +Grant(85) <= Signal_grant(3)(5) or Signal_grant(13)(5); -- Grant(9,5) +Grant(86) <= Signal_grant(4)(6) or Signal_grant(14)(6); -- Grant(9,6) +Grant(87) <= Signal_grant(5)(7) or Signal_grant(15)(7); -- Grant(9,7) +Grant(88) <= Signal_grant(6)(8) or Signal_grant(16)(8); -- Grant(9,8) +Grant(89) <= Signal_grant(7)(9) or Signal_grant(17)(9); -- Grant(9,9) +Grant(90) <= Signal_grant(8)(10) or Signal_grant(18)(10); -- Grant(9,10) +Grant(91) <= Signal_grant(10)(1) ; -- Grant(10,1) +Grant(92) <= Signal_grant(1)(2) or Signal_grant(11)(2); -- Grant(10,2) +Grant(93) <= Signal_grant(2)(3) or Signal_grant(12)(3); -- Grant(10,3) +Grant(94) <= Signal_grant(3)(4) or Signal_grant(13)(4); -- Grant(10,4) +Grant(95) <= Signal_grant(4)(5) or Signal_grant(14)(5); -- Grant(10,5) +Grant(96) <= Signal_grant(5)(6) or Signal_grant(15)(6); -- Grant(10,6) +Grant(97) <= Signal_grant(6)(7) or Signal_grant(16)(7); -- Grant(10,7) +Grant(98) <= Signal_grant(7)(8) or Signal_grant(17)(8); -- Grant(10,8) +Grant(99) <= Signal_grant(8)(9) or Signal_grant(18)(9); -- Grant(10,9) +Grant(100) <= Signal_grant(9)(10) or Signal_grant(19)(10); -- Grant(10,10) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(92), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(83), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(74), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +Arbiter_1_5 : Arbiter + +PORT MAP (Request => Request(65), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(5), +South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); + +Arbiter_1_6 : Arbiter + +PORT MAP (Request => Request(56), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(6), +South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); + +Arbiter_1_7 : Arbiter + +PORT MAP (Request => Request(47), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(7), +South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); + +Arbiter_1_8 : Arbiter + +PORT MAP (Request => Request(38), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(8), +South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); + +Arbiter_1_9 : Arbiter + +PORT MAP (Request => Request(29), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(9), +South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); + +Arbiter_1_10 : Arbiter + +PORT MAP (Request => Request(20), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(10), +South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(1)(1), West => east_2_west(1)(10), P => Signal_priority(18), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(93), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(84), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +Arbiter_2_5 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5), +South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); + +Arbiter_2_6 : Arbiter + +PORT MAP (Request => Request(66), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6), +South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); + +Arbiter_2_7 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7), +South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); + +Arbiter_2_8 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8), +South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); + +Arbiter_2_9 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9), +South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); + +Arbiter_2_10 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10), +South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(2)(1), West => east_2_west(2)(10), P => Signal_priority(17), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(94), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +Arbiter_3_5 : Arbiter + +PORT MAP (Request => Request(85), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5), +South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); + +Arbiter_3_6 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6), +South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); + +Arbiter_3_7 : Arbiter + +PORT MAP (Request => Request(67), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7), +South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); + +Arbiter_3_8 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8), +South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); + +Arbiter_3_9 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9), +South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); + +Arbiter_3_10 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10), +South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(3)(1), West => east_2_west(3)(10), P => Signal_priority(16), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +Arbiter_4_5 : Arbiter + +PORT MAP (Request => Request(95), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5), +South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); + +Arbiter_4_6 : Arbiter + +PORT MAP (Request => Request(86), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6), +South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); + +Arbiter_4_7 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7), +South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); + +Arbiter_4_8 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8), +South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); + +Arbiter_4_9 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9), +South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); + +Arbiter_4_10 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10), +South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(4)(1), West => east_2_west(4)(10), P => Signal_priority(15), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +Arbiter_5_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5), +South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); + +Arbiter_5_6 : Arbiter + +PORT MAP (Request => Request(96), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6), +South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); + +Arbiter_5_7 : Arbiter + +PORT MAP (Request => Request(87), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7), +South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); + +Arbiter_5_8 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8), +South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); + +Arbiter_5_9 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9), +South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); + +Arbiter_5_10 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10), +South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(5)(1), West => east_2_west(5)(10), P => Signal_priority(14), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +Arbiter_6_5 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5), +South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); + +Arbiter_6_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6), +South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); + +Arbiter_6_7 : Arbiter + +PORT MAP (Request => Request(97), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7), +South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); + +Arbiter_6_8 : Arbiter + +PORT MAP (Request => Request(88), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8), +South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); + +Arbiter_6_9 : Arbiter + +PORT MAP (Request => Request(79), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9), +South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); + +Arbiter_6_10 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10), +South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(6)(1), West => east_2_west(6)(10), P => Signal_priority(13), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + +Arbiter_7_5 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5), +South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); + +Arbiter_7_6 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6), +South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); + +Arbiter_7_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7), +South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); + +Arbiter_7_8 : Arbiter + +PORT MAP (Request => Request(98), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8), +South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); + +Arbiter_7_9 : Arbiter + +PORT MAP (Request => Request(89), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9), +South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); + +Arbiter_7_10 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10), +South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); + +-------------------------- Diagonale n° 8 + + +Arbiter_8_1 : Arbiter + +PORT MAP (Request => Request(71), North => south_2_north(7)(1), West => east_2_west(7)(10), P => Signal_priority(12), Fifo_full => Fifo_full(1), +South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); + +Arbiter_8_2 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2), +South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); + +Arbiter_8_3 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3), +South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); + +Arbiter_8_4 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4), +South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); + +Arbiter_8_5 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5), +South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); + +Arbiter_8_6 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6), +South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); + +Arbiter_8_7 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7), +South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); + +Arbiter_8_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8), +South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); + +Arbiter_8_9 : Arbiter + +PORT MAP (Request => Request(99), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9), +South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); + +Arbiter_8_10 : Arbiter + +PORT MAP (Request => Request(90), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10), +South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); + +-------------------------- Diagonale n° 9 + + +Arbiter_9_1 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(8)(1), West => east_2_west(8)(10), P => Signal_priority(11), Fifo_full => Fifo_full(1), +South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); + +Arbiter_9_2 : Arbiter + +PORT MAP (Request => Request(72), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2), +South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); + +Arbiter_9_3 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3), +South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); + +Arbiter_9_4 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4), +South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); + +Arbiter_9_5 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5), +South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); + +Arbiter_9_6 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6), +South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); + +Arbiter_9_7 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7), +South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); + +Arbiter_9_8 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8), +South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); + +Arbiter_9_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9), +South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); + +Arbiter_9_10 : Arbiter + +PORT MAP (Request => Request(100), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10), +South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); + +-------------------------- Diagonale n° 10 + + +Arbiter_10_1 : Arbiter + +PORT MAP (Request => Request(91), North => south_2_north(9)(1), West => east_2_west(9)(10), P => Signal_priority(10), Fifo_full => Fifo_full(1), +South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); + +Arbiter_10_2 : Arbiter + +PORT MAP (Request => Request(82), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2), +South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); + +Arbiter_10_3 : Arbiter + +PORT MAP (Request => Request(73), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3), +South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); + +Arbiter_10_4 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4), +South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); + +Arbiter_10_5 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5), +South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); + +Arbiter_10_6 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6), +South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); + +Arbiter_10_7 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7), +South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); + +Arbiter_10_8 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8), +South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); + +Arbiter_10_9 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9), +South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); + +Arbiter_10_10 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10), +South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); + +-------------------------- Diagonale n° 11 + + +Arbiter_11_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(10)(1), West => east_2_west(10)(10), P => Signal_priority(9), Fifo_full => Fifo_full(1), +South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); + +Arbiter_11_2 : Arbiter + +PORT MAP (Request => Request(92), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2), +South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); + +Arbiter_11_3 : Arbiter + +PORT MAP (Request => Request(83), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3), +South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); + +Arbiter_11_4 : Arbiter + +PORT MAP (Request => Request(74), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4), +South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); + +Arbiter_11_5 : Arbiter + +PORT MAP (Request => Request(65), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5), +South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); + +Arbiter_11_6 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6), +South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); + +Arbiter_11_7 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7), +South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); + +Arbiter_11_8 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8), +South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); + +Arbiter_11_9 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9), +South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); + +Arbiter_11_10 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10), +South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); + +-------------------------- Diagonale n° 12 + + +Arbiter_12_1 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(11)(1), West => east_2_west(11)(10), P => Signal_priority(8), Fifo_full => Fifo_full(1), +South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); + +Arbiter_12_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2), +South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); + +Arbiter_12_3 : Arbiter + +PORT MAP (Request => Request(93), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3), +South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); + +Arbiter_12_4 : Arbiter + +PORT MAP (Request => Request(84), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4), +South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); + +Arbiter_12_5 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5), +South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); + +Arbiter_12_6 : Arbiter + +PORT MAP (Request => Request(66), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6), +South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); + +Arbiter_12_7 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7), +South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); + +Arbiter_12_8 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8), +South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); + +Arbiter_12_9 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9), +South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); + +Arbiter_12_10 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10), +South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); + +-------------------------- Diagonale n° 13 + + +Arbiter_13_1 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(12)(1), West => east_2_west(12)(10), P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); + +Arbiter_13_2 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); + +Arbiter_13_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); + +Arbiter_13_4 : Arbiter + +PORT MAP (Request => Request(94), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); + +Arbiter_13_5 : Arbiter + +PORT MAP (Request => Request(85), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5), +South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); + +Arbiter_13_6 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6), +South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); + +Arbiter_13_7 : Arbiter + +PORT MAP (Request => Request(67), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7), +South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); + +Arbiter_13_8 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8), +South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); + +Arbiter_13_9 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9), +South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); + +Arbiter_13_10 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10), +South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); + +-------------------------- Diagonale n° 14 + + +Arbiter_14_1 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(13)(1), West => east_2_west(13)(10), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); + +Arbiter_14_2 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); + +Arbiter_14_3 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); + +Arbiter_14_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); + +Arbiter_14_5 : Arbiter + +PORT MAP (Request => Request(95), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5), +South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); + +Arbiter_14_6 : Arbiter + +PORT MAP (Request => Request(86), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6), +South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); + +Arbiter_14_7 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7), +South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); + +Arbiter_14_8 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8), +South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); + +Arbiter_14_9 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9), +South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); + +Arbiter_14_10 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10), +South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); + +-------------------------- Diagonale n° 15 + + +Arbiter_15_1 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(14)(1), West => east_2_west(14)(10), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); + +Arbiter_15_2 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); + +Arbiter_15_3 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); + +Arbiter_15_4 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); + +Arbiter_15_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5), +South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); + +Arbiter_15_6 : Arbiter + +PORT MAP (Request => Request(96), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6), +South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); + +Arbiter_15_7 : Arbiter + +PORT MAP (Request => Request(87), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7), +South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); + +Arbiter_15_8 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8), +South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); + +Arbiter_15_9 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9), +South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); + +Arbiter_15_10 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10), +South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); + +-------------------------- Diagonale n° 16 + + +Arbiter_16_1 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(15)(1), West => east_2_west(15)(10), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); + +Arbiter_16_2 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); + +Arbiter_16_3 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); + +Arbiter_16_4 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); + +Arbiter_16_5 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5), +South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); + +Arbiter_16_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6), +South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); + +Arbiter_16_7 : Arbiter + +PORT MAP (Request => Request(97), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7), +South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); + +Arbiter_16_8 : Arbiter + +PORT MAP (Request => Request(88), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8), +South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); + +Arbiter_16_9 : Arbiter + +PORT MAP (Request => Request(79), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9), +South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); + +Arbiter_16_10 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10), +South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); + +-------------------------- Diagonale n° 17 + + +Arbiter_17_1 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(16)(1), West => east_2_west(16)(10), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); + +Arbiter_17_2 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); + +Arbiter_17_3 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); + +Arbiter_17_4 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); + +Arbiter_17_5 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5), +South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); + +Arbiter_17_6 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6), +South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); + +Arbiter_17_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7), +South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); + +Arbiter_17_8 : Arbiter + +PORT MAP (Request => Request(98), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8), +South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); + +Arbiter_17_9 : Arbiter + +PORT MAP (Request => Request(89), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9), +South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); + +Arbiter_17_10 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10), +South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); + +-------------------------- Diagonale n° 18 + + +Arbiter_18_1 : Arbiter + +PORT MAP (Request => Request(71), North => south_2_north(17)(1), West => east_2_west(17)(10), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); + +Arbiter_18_2 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); + +Arbiter_18_3 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); + +Arbiter_18_4 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); + +Arbiter_18_5 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5), +South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); + +Arbiter_18_6 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6), +South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); + +Arbiter_18_7 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7), +South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); + +Arbiter_18_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8), +South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); + +Arbiter_18_9 : Arbiter + +PORT MAP (Request => Request(99), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9), +South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); + +Arbiter_18_10 : Arbiter + +PORT MAP (Request => Request(90), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10), +South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); + +-------------------------- Diagonale n° 19 + + +Arbiter_19_1 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(18)(1), West => east_2_west(18)(10), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); + +Arbiter_19_2 : Arbiter + +PORT MAP (Request => Request(72), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); + +Arbiter_19_3 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); + +Arbiter_19_4 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); + +Arbiter_19_5 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5), +South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); + +Arbiter_19_6 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6), +South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); + +Arbiter_19_7 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7), +South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); + +Arbiter_19_8 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8), +South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); + +Arbiter_19_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9), +South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); + +Arbiter_19_10 : Arbiter + +PORT MAP (Request => Request(100), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10), +South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "1111111111000000000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "1111111111000000000" => Signal_priority <= "0111111111100000000"; + when "0111111111100000000" => Signal_priority <= "0011111111110000000"; + when "0011111111110000000" => Signal_priority <= "0001111111111000000"; + when "0001111111111000000" => Signal_priority <= "0000111111111100000"; + when "0000111111111100000" => Signal_priority <= "0000011111111110000"; + when "0000011111111110000" => Signal_priority <= "0000001111111111000"; + when "0000001111111111000" => Signal_priority <= "0000000111111111100"; + when "0000000111111111100" => Signal_priority <= "0000000011111111110"; + when "0000000011111111110" => Signal_priority <= "0000000001111111111"; + when "0000000001111111111" => Signal_priority <= "1111111111000000000"; + when others => Signal_priority <= "1111111111000000000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER11_11.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER11_11.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER11_11.VHD (revision 138) @@ -0,0 +1,1445 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler11_11 is + Port ( Request : in STD_LOGIC_VECTOR (121 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (11 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (11 downto 1); + port_grant : out STD_LOGIC_VECTOR (121 downto 1)); +end Scheduler11_11; + +architecture Behavioral of Scheduler11_11 is +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(21 downto 1) of STD_LOGIC_VECTOR(11 downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (21 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(121 downto 1); + signal priority_rotation_en : std_logic; + signal Grant : std_logic_vector(121 downto 1); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet + priority_rotation_en <= '1' when unsigned(priority_rotation) = 2047 else '0'; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + elsif priority_rotation_en = '1' then + grant_latch <= Grant; + end if; + end if; + end process; + port_grant <= Grant and grant_latch; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(12)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(13)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(14)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) or Signal_grant(15)(4); -- Grant(1,4) +Grant(5) <= Signal_grant(5)(5) or Signal_grant(16)(5); -- Grant(1,5) +Grant(6) <= Signal_grant(6)(6) or Signal_grant(17)(6); -- Grant(1,6) +Grant(7) <= Signal_grant(7)(7) or Signal_grant(18)(7); -- Grant(1,7) +Grant(8) <= Signal_grant(8)(8) or Signal_grant(19)(8); -- Grant(1,8) +Grant(9) <= Signal_grant(9)(9) or Signal_grant(20)(9); -- Grant(1,9) +Grant(10) <= Signal_grant(10)(10) or Signal_grant(21)(10); -- Grant(1,10) +Grant(11) <= Signal_grant(11)(11) ; -- Grant(1,11) +Grant(12) <= Signal_grant(2)(1) or Signal_grant(13)(1); -- Grant(2,1) +Grant(13) <= Signal_grant(3)(2) or Signal_grant(14)(2); -- Grant(2,2) +Grant(14) <= Signal_grant(4)(3) or Signal_grant(15)(3); -- Grant(2,3) +Grant(15) <= Signal_grant(5)(4) or Signal_grant(16)(4); -- Grant(2,4) +Grant(16) <= Signal_grant(6)(5) or Signal_grant(17)(5); -- Grant(2,5) +Grant(17) <= Signal_grant(7)(6) or Signal_grant(18)(6); -- Grant(2,6) +Grant(18) <= Signal_grant(8)(7) or Signal_grant(19)(7); -- Grant(2,7) +Grant(19) <= Signal_grant(9)(8) or Signal_grant(20)(8); -- Grant(2,8) +Grant(20) <= Signal_grant(10)(9) or Signal_grant(21)(9); -- Grant(2,9) +Grant(21) <= Signal_grant(11)(10) ; -- Grant(2,10) +Grant(22) <= Signal_grant(1)(11) or Signal_grant(12)(11); -- Grant(2,11) +Grant(23) <= Signal_grant(3)(1) or Signal_grant(14)(1); -- Grant(3,1) +Grant(24) <= Signal_grant(4)(2) or Signal_grant(15)(2); -- Grant(3,2) +Grant(25) <= Signal_grant(5)(3) or Signal_grant(16)(3); -- Grant(3,3) +Grant(26) <= Signal_grant(6)(4) or Signal_grant(17)(4); -- Grant(3,4) +Grant(27) <= Signal_grant(7)(5) or Signal_grant(18)(5); -- Grant(3,5) +Grant(28) <= Signal_grant(8)(6) or Signal_grant(19)(6); -- Grant(3,6) +Grant(29) <= Signal_grant(9)(7) or Signal_grant(20)(7); -- Grant(3,7) +Grant(30) <= Signal_grant(10)(8) or Signal_grant(21)(8); -- Grant(3,8) +Grant(31) <= Signal_grant(11)(9) ; -- Grant(3,9) +Grant(32) <= Signal_grant(1)(10) or Signal_grant(12)(10); -- Grant(3,10) +Grant(33) <= Signal_grant(2)(11) or Signal_grant(13)(11); -- Grant(3,11) +Grant(34) <= Signal_grant(4)(1) or Signal_grant(15)(1); -- Grant(4,1) +Grant(35) <= Signal_grant(5)(2) or Signal_grant(16)(2); -- Grant(4,2) +Grant(36) <= Signal_grant(6)(3) or Signal_grant(17)(3); -- Grant(4,3) +Grant(37) <= Signal_grant(7)(4) or Signal_grant(18)(4); -- Grant(4,4) +Grant(38) <= Signal_grant(8)(5) or Signal_grant(19)(5); -- Grant(4,5) +Grant(39) <= Signal_grant(9)(6) or Signal_grant(20)(6); -- Grant(4,6) +Grant(40) <= Signal_grant(10)(7) or Signal_grant(21)(7); -- Grant(4,7) +Grant(41) <= Signal_grant(11)(8) ; -- Grant(4,8) +Grant(42) <= Signal_grant(1)(9) or Signal_grant(12)(9); -- Grant(4,9) +Grant(43) <= Signal_grant(2)(10) or Signal_grant(13)(10); -- Grant(4,10) +Grant(44) <= Signal_grant(3)(11) or Signal_grant(14)(11); -- Grant(4,11) +Grant(45) <= Signal_grant(5)(1) or Signal_grant(16)(1); -- Grant(5,1) +Grant(46) <= Signal_grant(6)(2) or Signal_grant(17)(2); -- Grant(5,2) +Grant(47) <= Signal_grant(7)(3) or Signal_grant(18)(3); -- Grant(5,3) +Grant(48) <= Signal_grant(8)(4) or Signal_grant(19)(4); -- Grant(5,4) +Grant(49) <= Signal_grant(9)(5) or Signal_grant(20)(5); -- Grant(5,5) +Grant(50) <= Signal_grant(10)(6) or Signal_grant(21)(6); -- Grant(5,6) +Grant(51) <= Signal_grant(11)(7) ; -- Grant(5,7) +Grant(52) <= Signal_grant(1)(8) or Signal_grant(12)(8); -- Grant(5,8) +Grant(53) <= Signal_grant(2)(9) or Signal_grant(13)(9); -- Grant(5,9) +Grant(54) <= Signal_grant(3)(10) or Signal_grant(14)(10); -- Grant(5,10) +Grant(55) <= Signal_grant(4)(11) or Signal_grant(15)(11); -- Grant(5,11) +Grant(56) <= Signal_grant(6)(1) or Signal_grant(17)(1); -- Grant(6,1) +Grant(57) <= Signal_grant(7)(2) or Signal_grant(18)(2); -- Grant(6,2) +Grant(58) <= Signal_grant(8)(3) or Signal_grant(19)(3); -- Grant(6,3) +Grant(59) <= Signal_grant(9)(4) or Signal_grant(20)(4); -- Grant(6,4) +Grant(60) <= Signal_grant(10)(5) or Signal_grant(21)(5); -- Grant(6,5) +Grant(61) <= Signal_grant(11)(6) ; -- Grant(6,6) +Grant(62) <= Signal_grant(1)(7) or Signal_grant(12)(7); -- Grant(6,7) +Grant(63) <= Signal_grant(2)(8) or Signal_grant(13)(8); -- Grant(6,8) +Grant(64) <= Signal_grant(3)(9) or Signal_grant(14)(9); -- Grant(6,9) +Grant(65) <= Signal_grant(4)(10) or Signal_grant(15)(10); -- Grant(6,10) +Grant(66) <= Signal_grant(5)(11) or Signal_grant(16)(11); -- Grant(6,11) +Grant(67) <= Signal_grant(7)(1) or Signal_grant(18)(1); -- Grant(7,1) +Grant(68) <= Signal_grant(8)(2) or Signal_grant(19)(2); -- Grant(7,2) +Grant(69) <= Signal_grant(9)(3) or Signal_grant(20)(3); -- Grant(7,3) +Grant(70) <= Signal_grant(10)(4) or Signal_grant(21)(4); -- Grant(7,4) +Grant(71) <= Signal_grant(11)(5) ; -- Grant(7,5) +Grant(72) <= Signal_grant(1)(6) or Signal_grant(12)(6); -- Grant(7,6) +Grant(73) <= Signal_grant(2)(7) or Signal_grant(13)(7); -- Grant(7,7) +Grant(74) <= Signal_grant(3)(8) or Signal_grant(14)(8); -- Grant(7,8) +Grant(75) <= Signal_grant(4)(9) or Signal_grant(15)(9); -- Grant(7,9) +Grant(76) <= Signal_grant(5)(10) or Signal_grant(16)(10); -- Grant(7,10) +Grant(77) <= Signal_grant(6)(11) or Signal_grant(17)(11); -- Grant(7,11) +Grant(78) <= Signal_grant(8)(1) or Signal_grant(19)(1); -- Grant(8,1) +Grant(79) <= Signal_grant(9)(2) or Signal_grant(20)(2); -- Grant(8,2) +Grant(80) <= Signal_grant(10)(3) or Signal_grant(21)(3); -- Grant(8,3) +Grant(81) <= Signal_grant(11)(4) ; -- Grant(8,4) +Grant(82) <= Signal_grant(1)(5) or Signal_grant(12)(5); -- Grant(8,5) +Grant(83) <= Signal_grant(2)(6) or Signal_grant(13)(6); -- Grant(8,6) +Grant(84) <= Signal_grant(3)(7) or Signal_grant(14)(7); -- Grant(8,7) +Grant(85) <= Signal_grant(4)(8) or Signal_grant(15)(8); -- Grant(8,8) +Grant(86) <= Signal_grant(5)(9) or Signal_grant(16)(9); -- Grant(8,9) +Grant(87) <= Signal_grant(6)(10) or Signal_grant(17)(10); -- Grant(8,10) +Grant(88) <= Signal_grant(7)(11) or Signal_grant(18)(11); -- Grant(8,11) +Grant(89) <= Signal_grant(9)(1) or Signal_grant(20)(1); -- Grant(9,1) +Grant(90) <= Signal_grant(10)(2) or Signal_grant(21)(2); -- Grant(9,2) +Grant(91) <= Signal_grant(11)(3) ; -- Grant(9,3) +Grant(92) <= Signal_grant(1)(4) or Signal_grant(12)(4); -- Grant(9,4) +Grant(93) <= Signal_grant(2)(5) or Signal_grant(13)(5); -- Grant(9,5) +Grant(94) <= Signal_grant(3)(6) or Signal_grant(14)(6); -- Grant(9,6) +Grant(95) <= Signal_grant(4)(7) or Signal_grant(15)(7); -- Grant(9,7) +Grant(96) <= Signal_grant(5)(8) or Signal_grant(16)(8); -- Grant(9,8) +Grant(97) <= Signal_grant(6)(9) or Signal_grant(17)(9); -- Grant(9,9) +Grant(98) <= Signal_grant(7)(10) or Signal_grant(18)(10); -- Grant(9,10) +Grant(99) <= Signal_grant(8)(11) or Signal_grant(19)(11); -- Grant(9,11) +Grant(100) <= Signal_grant(10)(1) or Signal_grant(21)(1); -- Grant(10,1) +Grant(101) <= Signal_grant(11)(2) ; -- Grant(10,2) +Grant(102) <= Signal_grant(1)(3) or Signal_grant(12)(3); -- Grant(10,3) +Grant(103) <= Signal_grant(2)(4) or Signal_grant(13)(4); -- Grant(10,4) +Grant(104) <= Signal_grant(3)(5) or Signal_grant(14)(5); -- Grant(10,5) +Grant(105) <= Signal_grant(4)(6) or Signal_grant(15)(6); -- Grant(10,6) +Grant(106) <= Signal_grant(5)(7) or Signal_grant(16)(7); -- Grant(10,7) +Grant(107) <= Signal_grant(6)(8) or Signal_grant(17)(8); -- Grant(10,8) +Grant(108) <= Signal_grant(7)(9) or Signal_grant(18)(9); -- Grant(10,9) +Grant(109) <= Signal_grant(8)(10) or Signal_grant(19)(10); -- Grant(10,10) +Grant(110) <= Signal_grant(9)(11) or Signal_grant(20)(11); -- Grant(10,11) +Grant(111) <= Signal_grant(11)(1) ; -- Grant(11,1) +Grant(112) <= Signal_grant(1)(2) or Signal_grant(12)(2); -- Grant(11,2) +Grant(113) <= Signal_grant(2)(3) or Signal_grant(13)(3); -- Grant(11,3) +Grant(114) <= Signal_grant(3)(4) or Signal_grant(14)(4); -- Grant(11,4) +Grant(115) <= Signal_grant(4)(5) or Signal_grant(15)(5); -- Grant(11,5) +Grant(116) <= Signal_grant(5)(6) or Signal_grant(16)(6); -- Grant(11,6) +Grant(117) <= Signal_grant(6)(7) or Signal_grant(17)(7); -- Grant(11,7) +Grant(118) <= Signal_grant(7)(8) or Signal_grant(18)(8); -- Grant(11,8) +Grant(119) <= Signal_grant(8)(9) or Signal_grant(19)(9); -- Grant(11,9) +Grant(120) <= Signal_grant(9)(10) or Signal_grant(20)(10); -- Grant(11,10) +Grant(121) <= Signal_grant(10)(11) or Signal_grant(21)(11); -- Grant(11,11) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(112), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(102), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(92), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +Arbiter_1_5 : Arbiter + +PORT MAP (Request => Request(82), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(5), +South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); + +Arbiter_1_6 : Arbiter + +PORT MAP (Request => Request(72), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(6), +South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); + +Arbiter_1_7 : Arbiter + +PORT MAP (Request => Request(62), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(7), +South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); + +Arbiter_1_8 : Arbiter + +PORT MAP (Request => Request(52), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(8), +South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); + +Arbiter_1_9 : Arbiter + +PORT MAP (Request => Request(42), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(9), +South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); + +Arbiter_1_10 : Arbiter + +PORT MAP (Request => Request(32), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(10), +South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); + +Arbiter_1_11 : Arbiter + +PORT MAP (Request => Request(22), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(11), +South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(1)(1), West => east_2_west(1)(11), P => Signal_priority(20), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(113), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(103), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +Arbiter_2_5 : Arbiter + +PORT MAP (Request => Request(93), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5), +South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); + +Arbiter_2_6 : Arbiter + +PORT MAP (Request => Request(83), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6), +South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); + +Arbiter_2_7 : Arbiter + +PORT MAP (Request => Request(73), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7), +South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); + +Arbiter_2_8 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8), +South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); + +Arbiter_2_9 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9), +South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); + +Arbiter_2_10 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10), +South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); + +Arbiter_2_11 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11), +South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(2)(1), West => east_2_west(2)(11), P => Signal_priority(19), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(114), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +Arbiter_3_5 : Arbiter + +PORT MAP (Request => Request(104), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5), +South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); + +Arbiter_3_6 : Arbiter + +PORT MAP (Request => Request(94), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6), +South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); + +Arbiter_3_7 : Arbiter + +PORT MAP (Request => Request(84), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7), +South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); + +Arbiter_3_8 : Arbiter + +PORT MAP (Request => Request(74), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8), +South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); + +Arbiter_3_9 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9), +South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); + +Arbiter_3_10 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10), +South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); + +Arbiter_3_11 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11), +South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(3)(1), West => east_2_west(3)(11), P => Signal_priority(18), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +Arbiter_4_5 : Arbiter + +PORT MAP (Request => Request(115), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5), +South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); + +Arbiter_4_6 : Arbiter + +PORT MAP (Request => Request(105), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6), +South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); + +Arbiter_4_7 : Arbiter + +PORT MAP (Request => Request(95), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7), +South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); + +Arbiter_4_8 : Arbiter + +PORT MAP (Request => Request(85), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8), +South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); + +Arbiter_4_9 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9), +South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); + +Arbiter_4_10 : Arbiter + +PORT MAP (Request => Request(65), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10), +South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); + +Arbiter_4_11 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11), +South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(4)(1), West => east_2_west(4)(11), P => Signal_priority(17), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +Arbiter_5_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5), +South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); + +Arbiter_5_6 : Arbiter + +PORT MAP (Request => Request(116), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6), +South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); + +Arbiter_5_7 : Arbiter + +PORT MAP (Request => Request(106), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7), +South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); + +Arbiter_5_8 : Arbiter + +PORT MAP (Request => Request(96), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8), +South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); + +Arbiter_5_9 : Arbiter + +PORT MAP (Request => Request(86), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9), +South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); + +Arbiter_5_10 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10), +South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); + +Arbiter_5_11 : Arbiter + +PORT MAP (Request => Request(66), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11), +South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(5)(1), West => east_2_west(5)(11), P => Signal_priority(16), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +Arbiter_6_5 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5), +South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); + +Arbiter_6_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6), +South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); + +Arbiter_6_7 : Arbiter + +PORT MAP (Request => Request(117), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7), +South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); + +Arbiter_6_8 : Arbiter + +PORT MAP (Request => Request(107), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8), +South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); + +Arbiter_6_9 : Arbiter + +PORT MAP (Request => Request(97), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9), +South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); + +Arbiter_6_10 : Arbiter + +PORT MAP (Request => Request(87), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10), +South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); + +Arbiter_6_11 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11), +South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(67), North => south_2_north(6)(1), West => east_2_west(6)(11), P => Signal_priority(15), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + +Arbiter_7_5 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5), +South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); + +Arbiter_7_6 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6), +South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); + +Arbiter_7_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7), +South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); + +Arbiter_7_8 : Arbiter + +PORT MAP (Request => Request(118), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8), +South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); + +Arbiter_7_9 : Arbiter + +PORT MAP (Request => Request(108), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9), +South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); + +Arbiter_7_10 : Arbiter + +PORT MAP (Request => Request(98), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10), +South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); + +Arbiter_7_11 : Arbiter + +PORT MAP (Request => Request(88), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11), +South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); + +-------------------------- Diagonale n° 8 + + +Arbiter_8_1 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(7)(1), West => east_2_west(7)(11), P => Signal_priority(14), Fifo_full => Fifo_full(1), +South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); + +Arbiter_8_2 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2), +South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); + +Arbiter_8_3 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3), +South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); + +Arbiter_8_4 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4), +South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); + +Arbiter_8_5 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5), +South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); + +Arbiter_8_6 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6), +South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); + +Arbiter_8_7 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7), +South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); + +Arbiter_8_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8), +South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); + +Arbiter_8_9 : Arbiter + +PORT MAP (Request => Request(119), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9), +South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); + +Arbiter_8_10 : Arbiter + +PORT MAP (Request => Request(109), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10), +South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); + +Arbiter_8_11 : Arbiter + +PORT MAP (Request => Request(99), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11), +South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); + +-------------------------- Diagonale n° 9 + + +Arbiter_9_1 : Arbiter + +PORT MAP (Request => Request(89), North => south_2_north(8)(1), West => east_2_west(8)(11), P => Signal_priority(13), Fifo_full => Fifo_full(1), +South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); + +Arbiter_9_2 : Arbiter + +PORT MAP (Request => Request(79), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2), +South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); + +Arbiter_9_3 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3), +South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); + +Arbiter_9_4 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4), +South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); + +Arbiter_9_5 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5), +South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); + +Arbiter_9_6 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6), +South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); + +Arbiter_9_7 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7), +South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); + +Arbiter_9_8 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8), +South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); + +Arbiter_9_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9), +South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); + +Arbiter_9_10 : Arbiter + +PORT MAP (Request => Request(120), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10), +South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); + +Arbiter_9_11 : Arbiter + +PORT MAP (Request => Request(110), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11), +South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); + +-------------------------- Diagonale n° 10 + + +Arbiter_10_1 : Arbiter + +PORT MAP (Request => Request(100), North => south_2_north(9)(1), West => east_2_west(9)(11), P => Signal_priority(12), Fifo_full => Fifo_full(1), +South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); + +Arbiter_10_2 : Arbiter + +PORT MAP (Request => Request(90), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2), +South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); + +Arbiter_10_3 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3), +South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); + +Arbiter_10_4 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4), +South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); + +Arbiter_10_5 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5), +South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); + +Arbiter_10_6 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6), +South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); + +Arbiter_10_7 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7), +South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); + +Arbiter_10_8 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8), +South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); + +Arbiter_10_9 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9), +South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); + +Arbiter_10_10 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10), +South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); + +Arbiter_10_11 : Arbiter + +PORT MAP (Request => Request(121), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11), +South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); + +-------------------------- Diagonale n° 11 + + +Arbiter_11_1 : Arbiter + +PORT MAP (Request => Request(111), North => south_2_north(10)(1), West => east_2_west(10)(11), P => Signal_priority(11), Fifo_full => Fifo_full(1), +South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); + +Arbiter_11_2 : Arbiter + +PORT MAP (Request => Request(101), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2), +South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); + +Arbiter_11_3 : Arbiter + +PORT MAP (Request => Request(91), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3), +South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); + +Arbiter_11_4 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4), +South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); + +Arbiter_11_5 : Arbiter + +PORT MAP (Request => Request(71), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5), +South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); + +Arbiter_11_6 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6), +South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); + +Arbiter_11_7 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7), +South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); + +Arbiter_11_8 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8), +South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); + +Arbiter_11_9 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9), +South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); + +Arbiter_11_10 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10), +South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); + +Arbiter_11_11 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11), +South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); + +-------------------------- Diagonale n° 12 + + +Arbiter_12_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(11)(1), West => east_2_west(11)(11), P => Signal_priority(10), Fifo_full => Fifo_full(1), +South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); + +Arbiter_12_2 : Arbiter + +PORT MAP (Request => Request(112), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2), +South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); + +Arbiter_12_3 : Arbiter + +PORT MAP (Request => Request(102), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3), +South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); + +Arbiter_12_4 : Arbiter + +PORT MAP (Request => Request(92), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4), +South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); + +Arbiter_12_5 : Arbiter + +PORT MAP (Request => Request(82), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5), +South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); + +Arbiter_12_6 : Arbiter + +PORT MAP (Request => Request(72), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6), +South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); + +Arbiter_12_7 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7), +South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); + +Arbiter_12_8 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8), +South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); + +Arbiter_12_9 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9), +South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); + +Arbiter_12_10 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10), +South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); + +Arbiter_12_11 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11), +South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); + +-------------------------- Diagonale n° 13 + + +Arbiter_13_1 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(12)(1), West => east_2_west(12)(11), P => Signal_priority(9), Fifo_full => Fifo_full(1), +South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); + +Arbiter_13_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2), +South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); + +Arbiter_13_3 : Arbiter + +PORT MAP (Request => Request(113), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3), +South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); + +Arbiter_13_4 : Arbiter + +PORT MAP (Request => Request(103), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4), +South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); + +Arbiter_13_5 : Arbiter + +PORT MAP (Request => Request(93), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5), +South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); + +Arbiter_13_6 : Arbiter + +PORT MAP (Request => Request(83), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6), +South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); + +Arbiter_13_7 : Arbiter + +PORT MAP (Request => Request(73), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7), +South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); + +Arbiter_13_8 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8), +South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); + +Arbiter_13_9 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9), +South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); + +Arbiter_13_10 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10), +South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); + +Arbiter_13_11 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11), +South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); + +-------------------------- Diagonale n° 14 + + +Arbiter_14_1 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(13)(1), West => east_2_west(13)(11), P => Signal_priority(8), Fifo_full => Fifo_full(1), +South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); + +Arbiter_14_2 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2), +South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); + +Arbiter_14_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3), +South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); + +Arbiter_14_4 : Arbiter + +PORT MAP (Request => Request(114), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4), +South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); + +Arbiter_14_5 : Arbiter + +PORT MAP (Request => Request(104), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5), +South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); + +Arbiter_14_6 : Arbiter + +PORT MAP (Request => Request(94), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6), +South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); + +Arbiter_14_7 : Arbiter + +PORT MAP (Request => Request(84), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7), +South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); + +Arbiter_14_8 : Arbiter + +PORT MAP (Request => Request(74), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8), +South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); + +Arbiter_14_9 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9), +South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); + +Arbiter_14_10 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10), +South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); + +Arbiter_14_11 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11), +South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); + +-------------------------- Diagonale n° 15 + + +Arbiter_15_1 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(14)(1), West => east_2_west(14)(11), P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); + +Arbiter_15_2 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); + +Arbiter_15_3 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); + +Arbiter_15_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); + +Arbiter_15_5 : Arbiter + +PORT MAP (Request => Request(115), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5), +South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); + +Arbiter_15_6 : Arbiter + +PORT MAP (Request => Request(105), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6), +South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); + +Arbiter_15_7 : Arbiter + +PORT MAP (Request => Request(95), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7), +South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); + +Arbiter_15_8 : Arbiter + +PORT MAP (Request => Request(85), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8), +South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); + +Arbiter_15_9 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9), +South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); + +Arbiter_15_10 : Arbiter + +PORT MAP (Request => Request(65), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10), +South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); + +Arbiter_15_11 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11), +South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); + +-------------------------- Diagonale n° 16 + + +Arbiter_16_1 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(15)(1), West => east_2_west(15)(11), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); + +Arbiter_16_2 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); + +Arbiter_16_3 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); + +Arbiter_16_4 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); + +Arbiter_16_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5), +South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); + +Arbiter_16_6 : Arbiter + +PORT MAP (Request => Request(116), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6), +South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); + +Arbiter_16_7 : Arbiter + +PORT MAP (Request => Request(106), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7), +South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); + +Arbiter_16_8 : Arbiter + +PORT MAP (Request => Request(96), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8), +South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); + +Arbiter_16_9 : Arbiter + +PORT MAP (Request => Request(86), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9), +South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); + +Arbiter_16_10 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10), +South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); + +Arbiter_16_11 : Arbiter + +PORT MAP (Request => Request(66), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11), +South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); + +-------------------------- Diagonale n° 17 + + +Arbiter_17_1 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(16)(1), West => east_2_west(16)(11), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); + +Arbiter_17_2 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); + +Arbiter_17_3 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); + +Arbiter_17_4 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); + +Arbiter_17_5 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5), +South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); + +Arbiter_17_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6), +South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); + +Arbiter_17_7 : Arbiter + +PORT MAP (Request => Request(117), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7), +South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); + +Arbiter_17_8 : Arbiter + +PORT MAP (Request => Request(107), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8), +South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); + +Arbiter_17_9 : Arbiter + +PORT MAP (Request => Request(97), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9), +South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); + +Arbiter_17_10 : Arbiter + +PORT MAP (Request => Request(87), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10), +South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); + +Arbiter_17_11 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11), +South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); + +-------------------------- Diagonale n° 18 + + +Arbiter_18_1 : Arbiter + +PORT MAP (Request => Request(67), North => south_2_north(17)(1), West => east_2_west(17)(11), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); + +Arbiter_18_2 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); + +Arbiter_18_3 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); + +Arbiter_18_4 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); + +Arbiter_18_5 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5), +South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); + +Arbiter_18_6 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6), +South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); + +Arbiter_18_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7), +South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); + +Arbiter_18_8 : Arbiter + +PORT MAP (Request => Request(118), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8), +South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); + +Arbiter_18_9 : Arbiter + +PORT MAP (Request => Request(108), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9), +South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); + +Arbiter_18_10 : Arbiter + +PORT MAP (Request => Request(98), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10), +South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); + +Arbiter_18_11 : Arbiter + +PORT MAP (Request => Request(88), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11), +South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); + +-------------------------- Diagonale n° 19 + + +Arbiter_19_1 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(18)(1), West => east_2_west(18)(11), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); + +Arbiter_19_2 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); + +Arbiter_19_3 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); + +Arbiter_19_4 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); + +Arbiter_19_5 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5), +South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); + +Arbiter_19_6 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6), +South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); + +Arbiter_19_7 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7), +South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); + +Arbiter_19_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8), +South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); + +Arbiter_19_9 : Arbiter + +PORT MAP (Request => Request(119), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9), +South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); + +Arbiter_19_10 : Arbiter + +PORT MAP (Request => Request(109), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10), +South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); + +Arbiter_19_11 : Arbiter + +PORT MAP (Request => Request(99), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11), +South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); + +-------------------------- Diagonale n° 20 + + +Arbiter_20_1 : Arbiter + +PORT MAP (Request => Request(89), North => south_2_north(19)(1), West => east_2_west(19)(11), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); + +Arbiter_20_2 : Arbiter + +PORT MAP (Request => Request(79), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); + +Arbiter_20_3 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); + +Arbiter_20_4 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); + +Arbiter_20_5 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5), +South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); + +Arbiter_20_6 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6), +South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); + +Arbiter_20_7 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7), +South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); + +Arbiter_20_8 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8), +South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); + +Arbiter_20_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9), +South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); + +Arbiter_20_10 : Arbiter + +PORT MAP (Request => Request(120), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10), +South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); + +Arbiter_20_11 : Arbiter + +PORT MAP (Request => Request(110), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11), +South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); + +-------------------------- Diagonale n° 21 + + +Arbiter_21_1 : Arbiter + +PORT MAP (Request => Request(100), North => south_2_north(20)(1), West => east_2_west(20)(11), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); + +Arbiter_21_2 : Arbiter + +PORT MAP (Request => Request(90), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); + +Arbiter_21_3 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); + +Arbiter_21_4 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); + +Arbiter_21_5 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5), +South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); + +Arbiter_21_6 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6), +South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); + +Arbiter_21_7 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7), +South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); + +Arbiter_21_8 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8), +South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); + +Arbiter_21_9 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9), +South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); + +Arbiter_21_10 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10), +South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); + +Arbiter_21_11 : Arbiter + +PORT MAP (Request => Request(121), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11), +South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "111111111110000000000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "111111111110000000000" => Signal_priority <= "011111111111000000000"; + when "011111111111000000000" => Signal_priority <= "001111111111100000000"; + when "001111111111100000000" => Signal_priority <= "000111111111110000000"; + when "000111111111110000000" => Signal_priority <= "000011111111111000000"; + when "000011111111111000000" => Signal_priority <= "000001111111111100000"; + when "000001111111111100000" => Signal_priority <= "000000111111111110000"; + when "000000111111111110000" => Signal_priority <= "000000011111111111000"; + when "000000011111111111000" => Signal_priority <= "000000001111111111100"; + when "000000001111111111100" => Signal_priority <= "000000000111111111110"; + when "000000000111111111110" => Signal_priority <= "000000000011111111111"; + when "000000000011111111111" => Signal_priority <= "111111111110000000000"; + when others => Signal_priority <= "111111111110000000000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER12_12.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER12_12.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER12_12.VHD (revision 138) @@ -0,0 +1,1701 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler12_12 is + Port ( Request : in STD_LOGIC_VECTOR (144 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (12 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (12 downto 1); + port_grant : out STD_LOGIC_VECTOR (144 downto 1)); +end Scheduler12_12; + +architecture Behavioral of Scheduler12_12 is +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(23 downto 1) of STD_LOGIC_VECTOR(12 downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (23 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(144 downto 1); + signal priority_rotation_en : std_logic; + signal Grant,req_grant : std_logic_vector(144 downto 1); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet +req_grant<=(request and grant_latch); + priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 4095 else '0'; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + elsif priority_rotation_en = '1' or unsigned(Grant_latch)=0 then + grant_latch <= Grant; + end if; + end if; + end process; + port_grant <= grant_latch; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(13)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(14)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(15)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) or Signal_grant(16)(4); -- Grant(1,4) +Grant(5) <= Signal_grant(5)(5) or Signal_grant(17)(5); -- Grant(1,5) +Grant(6) <= Signal_grant(6)(6) or Signal_grant(18)(6); -- Grant(1,6) +Grant(7) <= Signal_grant(7)(7) or Signal_grant(19)(7); -- Grant(1,7) +Grant(8) <= Signal_grant(8)(8) or Signal_grant(20)(8); -- Grant(1,8) +Grant(9) <= Signal_grant(9)(9) or Signal_grant(21)(9); -- Grant(1,9) +Grant(10) <= Signal_grant(10)(10) or Signal_grant(22)(10); -- Grant(1,10) +Grant(11) <= Signal_grant(11)(11) or Signal_grant(23)(11); -- Grant(1,11) +Grant(12) <= Signal_grant(12)(12) ; -- Grant(1,12) +Grant(13) <= Signal_grant(2)(1) or Signal_grant(14)(1); -- Grant(2,1) +Grant(14) <= Signal_grant(3)(2) or Signal_grant(15)(2); -- Grant(2,2) +Grant(15) <= Signal_grant(4)(3) or Signal_grant(16)(3); -- Grant(2,3) +Grant(16) <= Signal_grant(5)(4) or Signal_grant(17)(4); -- Grant(2,4) +Grant(17) <= Signal_grant(6)(5) or Signal_grant(18)(5); -- Grant(2,5) +Grant(18) <= Signal_grant(7)(6) or Signal_grant(19)(6); -- Grant(2,6) +Grant(19) <= Signal_grant(8)(7) or Signal_grant(20)(7); -- Grant(2,7) +Grant(20) <= Signal_grant(9)(8) or Signal_grant(21)(8); -- Grant(2,8) +Grant(21) <= Signal_grant(10)(9) or Signal_grant(22)(9); -- Grant(2,9) +Grant(22) <= Signal_grant(11)(10) or Signal_grant(23)(10); -- Grant(2,10) +Grant(23) <= Signal_grant(12)(11) ; -- Grant(2,11) +Grant(24) <= Signal_grant(1)(12) or Signal_grant(13)(12); -- Grant(2,12) +Grant(25) <= Signal_grant(3)(1) or Signal_grant(15)(1); -- Grant(3,1) +Grant(26) <= Signal_grant(4)(2) or Signal_grant(16)(2); -- Grant(3,2) +Grant(27) <= Signal_grant(5)(3) or Signal_grant(17)(3); -- Grant(3,3) +Grant(28) <= Signal_grant(6)(4) or Signal_grant(18)(4); -- Grant(3,4) +Grant(29) <= Signal_grant(7)(5) or Signal_grant(19)(5); -- Grant(3,5) +Grant(30) <= Signal_grant(8)(6) or Signal_grant(20)(6); -- Grant(3,6) +Grant(31) <= Signal_grant(9)(7) or Signal_grant(21)(7); -- Grant(3,7) +Grant(32) <= Signal_grant(10)(8) or Signal_grant(22)(8); -- Grant(3,8) +Grant(33) <= Signal_grant(11)(9) or Signal_grant(23)(9); -- Grant(3,9) +Grant(34) <= Signal_grant(12)(10) ; -- Grant(3,10) +Grant(35) <= Signal_grant(1)(11) or Signal_grant(13)(11); -- Grant(3,11) +Grant(36) <= Signal_grant(2)(12) or Signal_grant(14)(12); -- Grant(3,12) +Grant(37) <= Signal_grant(4)(1) or Signal_grant(16)(1); -- Grant(4,1) +Grant(38) <= Signal_grant(5)(2) or Signal_grant(17)(2); -- Grant(4,2) +Grant(39) <= Signal_grant(6)(3) or Signal_grant(18)(3); -- Grant(4,3) +Grant(40) <= Signal_grant(7)(4) or Signal_grant(19)(4); -- Grant(4,4) +Grant(41) <= Signal_grant(8)(5) or Signal_grant(20)(5); -- Grant(4,5) +Grant(42) <= Signal_grant(9)(6) or Signal_grant(21)(6); -- Grant(4,6) +Grant(43) <= Signal_grant(10)(7) or Signal_grant(22)(7); -- Grant(4,7) +Grant(44) <= Signal_grant(11)(8) or Signal_grant(23)(8); -- Grant(4,8) +Grant(45) <= Signal_grant(12)(9) ; -- Grant(4,9) +Grant(46) <= Signal_grant(1)(10) or Signal_grant(13)(10); -- Grant(4,10) +Grant(47) <= Signal_grant(2)(11) or Signal_grant(14)(11); -- Grant(4,11) +Grant(48) <= Signal_grant(3)(12) or Signal_grant(15)(12); -- Grant(4,12) +Grant(49) <= Signal_grant(5)(1) or Signal_grant(17)(1); -- Grant(5,1) +Grant(50) <= Signal_grant(6)(2) or Signal_grant(18)(2); -- Grant(5,2) +Grant(51) <= Signal_grant(7)(3) or Signal_grant(19)(3); -- Grant(5,3) +Grant(52) <= Signal_grant(8)(4) or Signal_grant(20)(4); -- Grant(5,4) +Grant(53) <= Signal_grant(9)(5) or Signal_grant(21)(5); -- Grant(5,5) +Grant(54) <= Signal_grant(10)(6) or Signal_grant(22)(6); -- Grant(5,6) +Grant(55) <= Signal_grant(11)(7) or Signal_grant(23)(7); -- Grant(5,7) +Grant(56) <= Signal_grant(12)(8) ; -- Grant(5,8) +Grant(57) <= Signal_grant(1)(9) or Signal_grant(13)(9); -- Grant(5,9) +Grant(58) <= Signal_grant(2)(10) or Signal_grant(14)(10); -- Grant(5,10) +Grant(59) <= Signal_grant(3)(11) or Signal_grant(15)(11); -- Grant(5,11) +Grant(60) <= Signal_grant(4)(12) or Signal_grant(16)(12); -- Grant(5,12) +Grant(61) <= Signal_grant(6)(1) or Signal_grant(18)(1); -- Grant(6,1) +Grant(62) <= Signal_grant(7)(2) or Signal_grant(19)(2); -- Grant(6,2) +Grant(63) <= Signal_grant(8)(3) or Signal_grant(20)(3); -- Grant(6,3) +Grant(64) <= Signal_grant(9)(4) or Signal_grant(21)(4); -- Grant(6,4) +Grant(65) <= Signal_grant(10)(5) or Signal_grant(22)(5); -- Grant(6,5) +Grant(66) <= Signal_grant(11)(6) or Signal_grant(23)(6); -- Grant(6,6) +Grant(67) <= Signal_grant(12)(7) ; -- Grant(6,7) +Grant(68) <= Signal_grant(1)(8) or Signal_grant(13)(8); -- Grant(6,8) +Grant(69) <= Signal_grant(2)(9) or Signal_grant(14)(9); -- Grant(6,9) +Grant(70) <= Signal_grant(3)(10) or Signal_grant(15)(10); -- Grant(6,10) +Grant(71) <= Signal_grant(4)(11) or Signal_grant(16)(11); -- Grant(6,11) +Grant(72) <= Signal_grant(5)(12) or Signal_grant(17)(12); -- Grant(6,12) +Grant(73) <= Signal_grant(7)(1) or Signal_grant(19)(1); -- Grant(7,1) +Grant(74) <= Signal_grant(8)(2) or Signal_grant(20)(2); -- Grant(7,2) +Grant(75) <= Signal_grant(9)(3) or Signal_grant(21)(3); -- Grant(7,3) +Grant(76) <= Signal_grant(10)(4) or Signal_grant(22)(4); -- Grant(7,4) +Grant(77) <= Signal_grant(11)(5) or Signal_grant(23)(5); -- Grant(7,5) +Grant(78) <= Signal_grant(12)(6) ; -- Grant(7,6) +Grant(79) <= Signal_grant(1)(7) or Signal_grant(13)(7); -- Grant(7,7) +Grant(80) <= Signal_grant(2)(8) or Signal_grant(14)(8); -- Grant(7,8) +Grant(81) <= Signal_grant(3)(9) or Signal_grant(15)(9); -- Grant(7,9) +Grant(82) <= Signal_grant(4)(10) or Signal_grant(16)(10); -- Grant(7,10) +Grant(83) <= Signal_grant(5)(11) or Signal_grant(17)(11); -- Grant(7,11) +Grant(84) <= Signal_grant(6)(12) or Signal_grant(18)(12); -- Grant(7,12) +Grant(85) <= Signal_grant(8)(1) or Signal_grant(20)(1); -- Grant(8,1) +Grant(86) <= Signal_grant(9)(2) or Signal_grant(21)(2); -- Grant(8,2) +Grant(87) <= Signal_grant(10)(3) or Signal_grant(22)(3); -- Grant(8,3) +Grant(88) <= Signal_grant(11)(4) or Signal_grant(23)(4); -- Grant(8,4) +Grant(89) <= Signal_grant(12)(5) ; -- Grant(8,5) +Grant(90) <= Signal_grant(1)(6) or Signal_grant(13)(6); -- Grant(8,6) +Grant(91) <= Signal_grant(2)(7) or Signal_grant(14)(7); -- Grant(8,7) +Grant(92) <= Signal_grant(3)(8) or Signal_grant(15)(8); -- Grant(8,8) +Grant(93) <= Signal_grant(4)(9) or Signal_grant(16)(9); -- Grant(8,9) +Grant(94) <= Signal_grant(5)(10) or Signal_grant(17)(10); -- Grant(8,10) +Grant(95) <= Signal_grant(6)(11) or Signal_grant(18)(11); -- Grant(8,11) +Grant(96) <= Signal_grant(7)(12) or Signal_grant(19)(12); -- Grant(8,12) +Grant(97) <= Signal_grant(9)(1) or Signal_grant(21)(1); -- Grant(9,1) +Grant(98) <= Signal_grant(10)(2) or Signal_grant(22)(2); -- Grant(9,2) +Grant(99) <= Signal_grant(11)(3) or Signal_grant(23)(3); -- Grant(9,3) +Grant(100) <= Signal_grant(12)(4) ; -- Grant(9,4) +Grant(101) <= Signal_grant(1)(5) or Signal_grant(13)(5); -- Grant(9,5) +Grant(102) <= Signal_grant(2)(6) or Signal_grant(14)(6); -- Grant(9,6) +Grant(103) <= Signal_grant(3)(7) or Signal_grant(15)(7); -- Grant(9,7) +Grant(104) <= Signal_grant(4)(8) or Signal_grant(16)(8); -- Grant(9,8) +Grant(105) <= Signal_grant(5)(9) or Signal_grant(17)(9); -- Grant(9,9) +Grant(106) <= Signal_grant(6)(10) or Signal_grant(18)(10); -- Grant(9,10) +Grant(107) <= Signal_grant(7)(11) or Signal_grant(19)(11); -- Grant(9,11) +Grant(108) <= Signal_grant(8)(12) or Signal_grant(20)(12); -- Grant(9,12) +Grant(109) <= Signal_grant(10)(1) or Signal_grant(22)(1); -- Grant(10,1) +Grant(110) <= Signal_grant(11)(2) or Signal_grant(23)(2); -- Grant(10,2) +Grant(111) <= Signal_grant(12)(3) ; -- Grant(10,3) +Grant(112) <= Signal_grant(1)(4) or Signal_grant(13)(4); -- Grant(10,4) +Grant(113) <= Signal_grant(2)(5) or Signal_grant(14)(5); -- Grant(10,5) +Grant(114) <= Signal_grant(3)(6) or Signal_grant(15)(6); -- Grant(10,6) +Grant(115) <= Signal_grant(4)(7) or Signal_grant(16)(7); -- Grant(10,7) +Grant(116) <= Signal_grant(5)(8) or Signal_grant(17)(8); -- Grant(10,8) +Grant(117) <= Signal_grant(6)(9) or Signal_grant(18)(9); -- Grant(10,9) +Grant(118) <= Signal_grant(7)(10) or Signal_grant(19)(10); -- Grant(10,10) +Grant(119) <= Signal_grant(8)(11) or Signal_grant(20)(11); -- Grant(10,11) +Grant(120) <= Signal_grant(9)(12) or Signal_grant(21)(12); -- Grant(10,12) +Grant(121) <= Signal_grant(11)(1) or Signal_grant(23)(1); -- Grant(11,1) +Grant(122) <= Signal_grant(12)(2) ; -- Grant(11,2) +Grant(123) <= Signal_grant(1)(3) or Signal_grant(13)(3); -- Grant(11,3) +Grant(124) <= Signal_grant(2)(4) or Signal_grant(14)(4); -- Grant(11,4) +Grant(125) <= Signal_grant(3)(5) or Signal_grant(15)(5); -- Grant(11,5) +Grant(126) <= Signal_grant(4)(6) or Signal_grant(16)(6); -- Grant(11,6) +Grant(127) <= Signal_grant(5)(7) or Signal_grant(17)(7); -- Grant(11,7) +Grant(128) <= Signal_grant(6)(8) or Signal_grant(18)(8); -- Grant(11,8) +Grant(129) <= Signal_grant(7)(9) or Signal_grant(19)(9); -- Grant(11,9) +Grant(130) <= Signal_grant(8)(10) or Signal_grant(20)(10); -- Grant(11,10) +Grant(131) <= Signal_grant(9)(11) or Signal_grant(21)(11); -- Grant(11,11) +Grant(132) <= Signal_grant(10)(12) or Signal_grant(22)(12); -- Grant(11,12) +Grant(133) <= Signal_grant(12)(1) ; -- Grant(12,1) +Grant(134) <= Signal_grant(1)(2) or Signal_grant(13)(2); -- Grant(12,2) +Grant(135) <= Signal_grant(2)(3) or Signal_grant(14)(3); -- Grant(12,3) +Grant(136) <= Signal_grant(3)(4) or Signal_grant(15)(4); -- Grant(12,4) +Grant(137) <= Signal_grant(4)(5) or Signal_grant(16)(5); -- Grant(12,5) +Grant(138) <= Signal_grant(5)(6) or Signal_grant(17)(6); -- Grant(12,6) +Grant(139) <= Signal_grant(6)(7) or Signal_grant(18)(7); -- Grant(12,7) +Grant(140) <= Signal_grant(7)(8) or Signal_grant(19)(8); -- Grant(12,8) +Grant(141) <= Signal_grant(8)(9) or Signal_grant(20)(9); -- Grant(12,9) +Grant(142) <= Signal_grant(9)(10) or Signal_grant(21)(10); -- Grant(12,10) +Grant(143) <= Signal_grant(10)(11) or Signal_grant(22)(11); -- Grant(12,11) +Grant(144) <= Signal_grant(11)(12) or Signal_grant(23)(12); -- Grant(12,12) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(134), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(123), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(112), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +Arbiter_1_5 : Arbiter + +PORT MAP (Request => Request(101), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(5), +South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); + +Arbiter_1_6 : Arbiter + +PORT MAP (Request => Request(90), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(6), +South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); + +Arbiter_1_7 : Arbiter + +PORT MAP (Request => Request(79), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(7), +South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); + +Arbiter_1_8 : Arbiter + +PORT MAP (Request => Request(68), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(8), +South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); + +Arbiter_1_9 : Arbiter + +PORT MAP (Request => Request(57), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(9), +South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); + +Arbiter_1_10 : Arbiter + +PORT MAP (Request => Request(46), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(10), +South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); + +Arbiter_1_11 : Arbiter + +PORT MAP (Request => Request(35), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(11), +South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); + +Arbiter_1_12 : Arbiter + +PORT MAP (Request => Request(24), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(12), +South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(1)(1), West => east_2_west(1)(12), P => Signal_priority(22), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(135), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(124), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +Arbiter_2_5 : Arbiter + +PORT MAP (Request => Request(113), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5), +South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); + +Arbiter_2_6 : Arbiter + +PORT MAP (Request => Request(102), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6), +South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); + +Arbiter_2_7 : Arbiter + +PORT MAP (Request => Request(91), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7), +South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); + +Arbiter_2_8 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8), +South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); + +Arbiter_2_9 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9), +South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); + +Arbiter_2_10 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10), +South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); + +Arbiter_2_11 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11), +South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); + +Arbiter_2_12 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12), +South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(2)(1), West => east_2_west(2)(12), P => Signal_priority(21), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(136), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +Arbiter_3_5 : Arbiter + +PORT MAP (Request => Request(125), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5), +South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); + +Arbiter_3_6 : Arbiter + +PORT MAP (Request => Request(114), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6), +South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); + +Arbiter_3_7 : Arbiter + +PORT MAP (Request => Request(103), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7), +South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); + +Arbiter_3_8 : Arbiter + +PORT MAP (Request => Request(92), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8), +South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); + +Arbiter_3_9 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9), +South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); + +Arbiter_3_10 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10), +South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); + +Arbiter_3_11 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11), +South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); + +Arbiter_3_12 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12), +South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(3)(1), West => east_2_west(3)(12), P => Signal_priority(20), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +Arbiter_4_5 : Arbiter + +PORT MAP (Request => Request(137), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5), +South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); + +Arbiter_4_6 : Arbiter + +PORT MAP (Request => Request(126), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6), +South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); + +Arbiter_4_7 : Arbiter + +PORT MAP (Request => Request(115), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7), +South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); + +Arbiter_4_8 : Arbiter + +PORT MAP (Request => Request(104), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8), +South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); + +Arbiter_4_9 : Arbiter + +PORT MAP (Request => Request(93), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9), +South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); + +Arbiter_4_10 : Arbiter + +PORT MAP (Request => Request(82), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10), +South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); + +Arbiter_4_11 : Arbiter + +PORT MAP (Request => Request(71), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11), +South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); + +Arbiter_4_12 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12), +South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(4)(1), West => east_2_west(4)(12), P => Signal_priority(19), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +Arbiter_5_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5), +South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); + +Arbiter_5_6 : Arbiter + +PORT MAP (Request => Request(138), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6), +South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); + +Arbiter_5_7 : Arbiter + +PORT MAP (Request => Request(127), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7), +South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); + +Arbiter_5_8 : Arbiter + +PORT MAP (Request => Request(116), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8), +South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); + +Arbiter_5_9 : Arbiter + +PORT MAP (Request => Request(105), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9), +South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); + +Arbiter_5_10 : Arbiter + +PORT MAP (Request => Request(94), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10), +South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); + +Arbiter_5_11 : Arbiter + +PORT MAP (Request => Request(83), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11), +South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); + +Arbiter_5_12 : Arbiter + +PORT MAP (Request => Request(72), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12), +South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(5)(1), West => east_2_west(5)(12), P => Signal_priority(18), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +Arbiter_6_5 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5), +South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); + +Arbiter_6_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6), +South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); + +Arbiter_6_7 : Arbiter + +PORT MAP (Request => Request(139), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7), +South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); + +Arbiter_6_8 : Arbiter + +PORT MAP (Request => Request(128), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8), +South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); + +Arbiter_6_9 : Arbiter + +PORT MAP (Request => Request(117), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9), +South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); + +Arbiter_6_10 : Arbiter + +PORT MAP (Request => Request(106), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10), +South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); + +Arbiter_6_11 : Arbiter + +PORT MAP (Request => Request(95), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11), +South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); + +Arbiter_6_12 : Arbiter + +PORT MAP (Request => Request(84), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12), +South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(73), North => south_2_north(6)(1), West => east_2_west(6)(12), P => Signal_priority(17), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + +Arbiter_7_5 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5), +South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); + +Arbiter_7_6 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6), +South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); + +Arbiter_7_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7), +South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); + +Arbiter_7_8 : Arbiter + +PORT MAP (Request => Request(140), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8), +South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); + +Arbiter_7_9 : Arbiter + +PORT MAP (Request => Request(129), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9), +South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); + +Arbiter_7_10 : Arbiter + +PORT MAP (Request => Request(118), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10), +South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); + +Arbiter_7_11 : Arbiter + +PORT MAP (Request => Request(107), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11), +South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); + +Arbiter_7_12 : Arbiter + +PORT MAP (Request => Request(96), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12), +South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); + +-------------------------- Diagonale n° 8 + + +Arbiter_8_1 : Arbiter + +PORT MAP (Request => Request(85), North => south_2_north(7)(1), West => east_2_west(7)(12), P => Signal_priority(16), Fifo_full => Fifo_full(1), +South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); + +Arbiter_8_2 : Arbiter + +PORT MAP (Request => Request(74), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2), +South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); + +Arbiter_8_3 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3), +South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); + +Arbiter_8_4 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4), +South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); + +Arbiter_8_5 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5), +South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); + +Arbiter_8_6 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6), +South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); + +Arbiter_8_7 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7), +South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); + +Arbiter_8_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8), +South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); + +Arbiter_8_9 : Arbiter + +PORT MAP (Request => Request(141), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9), +South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); + +Arbiter_8_10 : Arbiter + +PORT MAP (Request => Request(130), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10), +South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); + +Arbiter_8_11 : Arbiter + +PORT MAP (Request => Request(119), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11), +South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); + +Arbiter_8_12 : Arbiter + +PORT MAP (Request => Request(108), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12), +South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); + +-------------------------- Diagonale n° 9 + + +Arbiter_9_1 : Arbiter + +PORT MAP (Request => Request(97), North => south_2_north(8)(1), West => east_2_west(8)(12), P => Signal_priority(15), Fifo_full => Fifo_full(1), +South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); + +Arbiter_9_2 : Arbiter + +PORT MAP (Request => Request(86), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2), +South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); + +Arbiter_9_3 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3), +South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); + +Arbiter_9_4 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4), +South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); + +Arbiter_9_5 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5), +South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); + +Arbiter_9_6 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6), +South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); + +Arbiter_9_7 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7), +South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); + +Arbiter_9_8 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8), +South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); + +Arbiter_9_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9), +South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); + +Arbiter_9_10 : Arbiter + +PORT MAP (Request => Request(142), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10), +South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); + +Arbiter_9_11 : Arbiter + +PORT MAP (Request => Request(131), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11), +South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); + +Arbiter_9_12 : Arbiter + +PORT MAP (Request => Request(120), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12), +South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); + +-------------------------- Diagonale n° 10 + + +Arbiter_10_1 : Arbiter + +PORT MAP (Request => Request(109), North => south_2_north(9)(1), West => east_2_west(9)(12), P => Signal_priority(14), Fifo_full => Fifo_full(1), +South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); + +Arbiter_10_2 : Arbiter + +PORT MAP (Request => Request(98), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2), +South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); + +Arbiter_10_3 : Arbiter + +PORT MAP (Request => Request(87), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3), +South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); + +Arbiter_10_4 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4), +South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); + +Arbiter_10_5 : Arbiter + +PORT MAP (Request => Request(65), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5), +South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); + +Arbiter_10_6 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6), +South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); + +Arbiter_10_7 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7), +South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); + +Arbiter_10_8 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8), +South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); + +Arbiter_10_9 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9), +South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); + +Arbiter_10_10 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10), +South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); + +Arbiter_10_11 : Arbiter + +PORT MAP (Request => Request(143), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11), +South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); + +Arbiter_10_12 : Arbiter + +PORT MAP (Request => Request(132), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12), +South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); + +-------------------------- Diagonale n° 11 + + +Arbiter_11_1 : Arbiter + +PORT MAP (Request => Request(121), North => south_2_north(10)(1), West => east_2_west(10)(12), P => Signal_priority(13), Fifo_full => Fifo_full(1), +South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); + +Arbiter_11_2 : Arbiter + +PORT MAP (Request => Request(110), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2), +South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); + +Arbiter_11_3 : Arbiter + +PORT MAP (Request => Request(99), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3), +South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); + +Arbiter_11_4 : Arbiter + +PORT MAP (Request => Request(88), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4), +South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); + +Arbiter_11_5 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5), +South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); + +Arbiter_11_6 : Arbiter + +PORT MAP (Request => Request(66), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6), +South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); + +Arbiter_11_7 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7), +South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); + +Arbiter_11_8 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8), +South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); + +Arbiter_11_9 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9), +South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); + +Arbiter_11_10 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10), +South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); + +Arbiter_11_11 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11), +South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); + +Arbiter_11_12 : Arbiter + +PORT MAP (Request => Request(144), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12), +South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); + +-------------------------- Diagonale n° 12 + + +Arbiter_12_1 : Arbiter + +PORT MAP (Request => Request(133), North => south_2_north(11)(1), West => east_2_west(11)(12), P => Signal_priority(12), Fifo_full => Fifo_full(1), +South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); + +Arbiter_12_2 : Arbiter + +PORT MAP (Request => Request(122), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2), +South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); + +Arbiter_12_3 : Arbiter + +PORT MAP (Request => Request(111), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3), +South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); + +Arbiter_12_4 : Arbiter + +PORT MAP (Request => Request(100), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4), +South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); + +Arbiter_12_5 : Arbiter + +PORT MAP (Request => Request(89), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5), +South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); + +Arbiter_12_6 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6), +South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); + +Arbiter_12_7 : Arbiter + +PORT MAP (Request => Request(67), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7), +South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); + +Arbiter_12_8 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8), +South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); + +Arbiter_12_9 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9), +South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); + +Arbiter_12_10 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10), +South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); + +Arbiter_12_11 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11), +South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); + +Arbiter_12_12 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12), +South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); + +-------------------------- Diagonale n° 13 + + +Arbiter_13_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(12)(1), West => east_2_west(12)(12), P => Signal_priority(11), Fifo_full => Fifo_full(1), +South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); + +Arbiter_13_2 : Arbiter + +PORT MAP (Request => Request(134), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2), +South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); + +Arbiter_13_3 : Arbiter + +PORT MAP (Request => Request(123), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3), +South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); + +Arbiter_13_4 : Arbiter + +PORT MAP (Request => Request(112), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4), +South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); + +Arbiter_13_5 : Arbiter + +PORT MAP (Request => Request(101), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5), +South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); + +Arbiter_13_6 : Arbiter + +PORT MAP (Request => Request(90), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6), +South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); + +Arbiter_13_7 : Arbiter + +PORT MAP (Request => Request(79), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7), +South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); + +Arbiter_13_8 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8), +South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); + +Arbiter_13_9 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9), +South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); + +Arbiter_13_10 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10), +South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); + +Arbiter_13_11 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11), +South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); + +Arbiter_13_12 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12), +South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); + +-------------------------- Diagonale n° 14 + + +Arbiter_14_1 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(13)(1), West => east_2_west(13)(12), P => Signal_priority(10), Fifo_full => Fifo_full(1), +South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); + +Arbiter_14_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2), +South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); + +Arbiter_14_3 : Arbiter + +PORT MAP (Request => Request(135), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3), +South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); + +Arbiter_14_4 : Arbiter + +PORT MAP (Request => Request(124), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4), +South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); + +Arbiter_14_5 : Arbiter + +PORT MAP (Request => Request(113), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5), +South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); + +Arbiter_14_6 : Arbiter + +PORT MAP (Request => Request(102), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6), +South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); + +Arbiter_14_7 : Arbiter + +PORT MAP (Request => Request(91), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7), +South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); + +Arbiter_14_8 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8), +South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); + +Arbiter_14_9 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9), +South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); + +Arbiter_14_10 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10), +South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); + +Arbiter_14_11 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11), +South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); + +Arbiter_14_12 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12), +South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); + +-------------------------- Diagonale n° 15 + + +Arbiter_15_1 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(14)(1), West => east_2_west(14)(12), P => Signal_priority(9), Fifo_full => Fifo_full(1), +South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); + +Arbiter_15_2 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2), +South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); + +Arbiter_15_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3), +South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); + +Arbiter_15_4 : Arbiter + +PORT MAP (Request => Request(136), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4), +South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); + +Arbiter_15_5 : Arbiter + +PORT MAP (Request => Request(125), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5), +South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); + +Arbiter_15_6 : Arbiter + +PORT MAP (Request => Request(114), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6), +South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); + +Arbiter_15_7 : Arbiter + +PORT MAP (Request => Request(103), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7), +South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); + +Arbiter_15_8 : Arbiter + +PORT MAP (Request => Request(92), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8), +South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); + +Arbiter_15_9 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9), +South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); + +Arbiter_15_10 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10), +South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); + +Arbiter_15_11 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11), +South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); + +Arbiter_15_12 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12), +South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); + +-------------------------- Diagonale n° 16 + + +Arbiter_16_1 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(15)(1), West => east_2_west(15)(12), P => Signal_priority(8), Fifo_full => Fifo_full(1), +South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); + +Arbiter_16_2 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2), +South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); + +Arbiter_16_3 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3), +South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); + +Arbiter_16_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4), +South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); + +Arbiter_16_5 : Arbiter + +PORT MAP (Request => Request(137), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5), +South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); + +Arbiter_16_6 : Arbiter + +PORT MAP (Request => Request(126), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6), +South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); + +Arbiter_16_7 : Arbiter + +PORT MAP (Request => Request(115), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7), +South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); + +Arbiter_16_8 : Arbiter + +PORT MAP (Request => Request(104), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8), +South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); + +Arbiter_16_9 : Arbiter + +PORT MAP (Request => Request(93), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9), +South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); + +Arbiter_16_10 : Arbiter + +PORT MAP (Request => Request(82), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10), +South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); + +Arbiter_16_11 : Arbiter + +PORT MAP (Request => Request(71), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11), +South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); + +Arbiter_16_12 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12), +South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); + +-------------------------- Diagonale n° 17 + + +Arbiter_17_1 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(16)(1), West => east_2_west(16)(12), P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); + +Arbiter_17_2 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); + +Arbiter_17_3 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); + +Arbiter_17_4 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); + +Arbiter_17_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5), +South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); + +Arbiter_17_6 : Arbiter + +PORT MAP (Request => Request(138), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6), +South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); + +Arbiter_17_7 : Arbiter + +PORT MAP (Request => Request(127), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7), +South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); + +Arbiter_17_8 : Arbiter + +PORT MAP (Request => Request(116), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8), +South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); + +Arbiter_17_9 : Arbiter + +PORT MAP (Request => Request(105), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9), +South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); + +Arbiter_17_10 : Arbiter + +PORT MAP (Request => Request(94), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10), +South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); + +Arbiter_17_11 : Arbiter + +PORT MAP (Request => Request(83), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11), +South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); + +Arbiter_17_12 : Arbiter + +PORT MAP (Request => Request(72), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12), +South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); + +-------------------------- Diagonale n° 18 + + +Arbiter_18_1 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(17)(1), West => east_2_west(17)(12), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); + +Arbiter_18_2 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); + +Arbiter_18_3 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); + +Arbiter_18_4 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); + +Arbiter_18_5 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5), +South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); + +Arbiter_18_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6), +South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); + +Arbiter_18_7 : Arbiter + +PORT MAP (Request => Request(139), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7), +South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); + +Arbiter_18_8 : Arbiter + +PORT MAP (Request => Request(128), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8), +South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); + +Arbiter_18_9 : Arbiter + +PORT MAP (Request => Request(117), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9), +South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); + +Arbiter_18_10 : Arbiter + +PORT MAP (Request => Request(106), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10), +South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); + +Arbiter_18_11 : Arbiter + +PORT MAP (Request => Request(95), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11), +South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); + +Arbiter_18_12 : Arbiter + +PORT MAP (Request => Request(84), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12), +South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); + +-------------------------- Diagonale n° 19 + + +Arbiter_19_1 : Arbiter + +PORT MAP (Request => Request(73), North => south_2_north(18)(1), West => east_2_west(18)(12), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); + +Arbiter_19_2 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); + +Arbiter_19_3 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); + +Arbiter_19_4 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); + +Arbiter_19_5 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5), +South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); + +Arbiter_19_6 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6), +South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); + +Arbiter_19_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7), +South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); + +Arbiter_19_8 : Arbiter + +PORT MAP (Request => Request(140), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8), +South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); + +Arbiter_19_9 : Arbiter + +PORT MAP (Request => Request(129), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9), +South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); + +Arbiter_19_10 : Arbiter + +PORT MAP (Request => Request(118), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10), +South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); + +Arbiter_19_11 : Arbiter + +PORT MAP (Request => Request(107), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11), +South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); + +Arbiter_19_12 : Arbiter + +PORT MAP (Request => Request(96), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12), +South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); + +-------------------------- Diagonale n° 20 + + +Arbiter_20_1 : Arbiter + +PORT MAP (Request => Request(85), North => south_2_north(19)(1), West => east_2_west(19)(12), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); + +Arbiter_20_2 : Arbiter + +PORT MAP (Request => Request(74), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); + +Arbiter_20_3 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); + +Arbiter_20_4 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); + +Arbiter_20_5 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5), +South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); + +Arbiter_20_6 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6), +South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); + +Arbiter_20_7 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7), +South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); + +Arbiter_20_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8), +South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); + +Arbiter_20_9 : Arbiter + +PORT MAP (Request => Request(141), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9), +South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); + +Arbiter_20_10 : Arbiter + +PORT MAP (Request => Request(130), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10), +South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); + +Arbiter_20_11 : Arbiter + +PORT MAP (Request => Request(119), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11), +South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); + +Arbiter_20_12 : Arbiter + +PORT MAP (Request => Request(108), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12), +South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); + +-------------------------- Diagonale n° 21 + + +Arbiter_21_1 : Arbiter + +PORT MAP (Request => Request(97), North => south_2_north(20)(1), West => east_2_west(20)(12), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); + +Arbiter_21_2 : Arbiter + +PORT MAP (Request => Request(86), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); + +Arbiter_21_3 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); + +Arbiter_21_4 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); + +Arbiter_21_5 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5), +South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); + +Arbiter_21_6 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6), +South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); + +Arbiter_21_7 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7), +South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); + +Arbiter_21_8 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8), +South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); + +Arbiter_21_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9), +South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); + +Arbiter_21_10 : Arbiter + +PORT MAP (Request => Request(142), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10), +South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); + +Arbiter_21_11 : Arbiter + +PORT MAP (Request => Request(131), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11), +South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); + +Arbiter_21_12 : Arbiter + +PORT MAP (Request => Request(120), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12), +South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); + +-------------------------- Diagonale n° 22 + + +Arbiter_22_1 : Arbiter + +PORT MAP (Request => Request(109), North => south_2_north(21)(1), West => east_2_west(21)(12), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); + +Arbiter_22_2 : Arbiter + +PORT MAP (Request => Request(98), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); + +Arbiter_22_3 : Arbiter + +PORT MAP (Request => Request(87), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); + +Arbiter_22_4 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); + +Arbiter_22_5 : Arbiter + +PORT MAP (Request => Request(65), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5), +South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); + +Arbiter_22_6 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6), +South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); + +Arbiter_22_7 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7), +South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); + +Arbiter_22_8 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8), +South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); + +Arbiter_22_9 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9), +South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); + +Arbiter_22_10 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10), +South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); + +Arbiter_22_11 : Arbiter + +PORT MAP (Request => Request(143), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11), +South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); + +Arbiter_22_12 : Arbiter + +PORT MAP (Request => Request(132), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12), +South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); + +-------------------------- Diagonale n° 23 + + +Arbiter_23_1 : Arbiter + +PORT MAP (Request => Request(121), North => south_2_north(22)(1), West => east_2_west(22)(12), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); + +Arbiter_23_2 : Arbiter + +PORT MAP (Request => Request(110), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); + +Arbiter_23_3 : Arbiter + +PORT MAP (Request => Request(99), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); + +Arbiter_23_4 : Arbiter + +PORT MAP (Request => Request(88), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); + +Arbiter_23_5 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5), +South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); + +Arbiter_23_6 : Arbiter + +PORT MAP (Request => Request(66), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6), +South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); + +Arbiter_23_7 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7), +South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); + +Arbiter_23_8 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8), +South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); + +Arbiter_23_9 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9), +South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); + +Arbiter_23_10 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10), +South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); + +Arbiter_23_11 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11), +South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); + +Arbiter_23_12 : Arbiter + +PORT MAP (Request => Request(144), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12), +South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "11111111111100000000000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "11111111111100000000000" => Signal_priority <= "01111111111110000000000"; + when "01111111111110000000000" => Signal_priority <= "00111111111111000000000"; + when "00111111111111000000000" => Signal_priority <= "00011111111111100000000"; + when "00011111111111100000000" => Signal_priority <= "00001111111111110000000"; + when "00001111111111110000000" => Signal_priority <= "00000111111111111000000"; + when "00000111111111111000000" => Signal_priority <= "00000011111111111100000"; + when "00000011111111111100000" => Signal_priority <= "00000001111111111110000"; + when "00000001111111111110000" => Signal_priority <= "00000000111111111111000"; + when "00000000111111111111000" => Signal_priority <= "00000000011111111111100"; + when "00000000011111111111100" => Signal_priority <= "00000000001111111111110"; + when "00000000001111111111110" => Signal_priority <= "00000000000111111111111"; + when "00000000000111111111111" => Signal_priority <= "11111111111100000000000"; + when others => Signal_priority <= "11111111111100000000000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER13_13.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER13_13.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER13_13.VHD (revision 138) @@ -0,0 +1,1978 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler13_13 is + Port ( Request : in STD_LOGIC_VECTOR (169 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (13 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (13 downto 1); + port_grant : out STD_LOGIC_VECTOR (169 downto 1)); +end Scheduler13_13; + +architecture Behavioral of Scheduler13_13 is +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(25 downto 1) of STD_LOGIC_VECTOR(13 downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (25 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(169 downto 1); + signal priority_rotation_en : std_logic; + signal Grant,req_grant : std_logic_vector(169 downto 1); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet +req_grant<=(request and grant_latch); + priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 8191 else '0'; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + elsif priority_rotation_en = '1' or unsigned(Grant_latch)=0 then + grant_latch <= Grant; + end if; + end if; + end process; + port_grant <= grant_latch; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(14)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(15)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(16)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) or Signal_grant(17)(4); -- Grant(1,4) +Grant(5) <= Signal_grant(5)(5) or Signal_grant(18)(5); -- Grant(1,5) +Grant(6) <= Signal_grant(6)(6) or Signal_grant(19)(6); -- Grant(1,6) +Grant(7) <= Signal_grant(7)(7) or Signal_grant(20)(7); -- Grant(1,7) +Grant(8) <= Signal_grant(8)(8) or Signal_grant(21)(8); -- Grant(1,8) +Grant(9) <= Signal_grant(9)(9) or Signal_grant(22)(9); -- Grant(1,9) +Grant(10) <= Signal_grant(10)(10) or Signal_grant(23)(10); -- Grant(1,10) +Grant(11) <= Signal_grant(11)(11) or Signal_grant(24)(11); -- Grant(1,11) +Grant(12) <= Signal_grant(12)(12) or Signal_grant(25)(12); -- Grant(1,12) +Grant(13) <= Signal_grant(13)(13) ; -- Grant(1,13) +Grant(14) <= Signal_grant(2)(1) or Signal_grant(15)(1); -- Grant(2,1) +Grant(15) <= Signal_grant(3)(2) or Signal_grant(16)(2); -- Grant(2,2) +Grant(16) <= Signal_grant(4)(3) or Signal_grant(17)(3); -- Grant(2,3) +Grant(17) <= Signal_grant(5)(4) or Signal_grant(18)(4); -- Grant(2,4) +Grant(18) <= Signal_grant(6)(5) or Signal_grant(19)(5); -- Grant(2,5) +Grant(19) <= Signal_grant(7)(6) or Signal_grant(20)(6); -- Grant(2,6) +Grant(20) <= Signal_grant(8)(7) or Signal_grant(21)(7); -- Grant(2,7) +Grant(21) <= Signal_grant(9)(8) or Signal_grant(22)(8); -- Grant(2,8) +Grant(22) <= Signal_grant(10)(9) or Signal_grant(23)(9); -- Grant(2,9) +Grant(23) <= Signal_grant(11)(10) or Signal_grant(24)(10); -- Grant(2,10) +Grant(24) <= Signal_grant(12)(11) or Signal_grant(25)(11); -- Grant(2,11) +Grant(25) <= Signal_grant(13)(12) ; -- Grant(2,12) +Grant(26) <= Signal_grant(1)(13) or Signal_grant(14)(13); -- Grant(2,13) +Grant(27) <= Signal_grant(3)(1) or Signal_grant(16)(1); -- Grant(3,1) +Grant(28) <= Signal_grant(4)(2) or Signal_grant(17)(2); -- Grant(3,2) +Grant(29) <= Signal_grant(5)(3) or Signal_grant(18)(3); -- Grant(3,3) +Grant(30) <= Signal_grant(6)(4) or Signal_grant(19)(4); -- Grant(3,4) +Grant(31) <= Signal_grant(7)(5) or Signal_grant(20)(5); -- Grant(3,5) +Grant(32) <= Signal_grant(8)(6) or Signal_grant(21)(6); -- Grant(3,6) +Grant(33) <= Signal_grant(9)(7) or Signal_grant(22)(7); -- Grant(3,7) +Grant(34) <= Signal_grant(10)(8) or Signal_grant(23)(8); -- Grant(3,8) +Grant(35) <= Signal_grant(11)(9) or Signal_grant(24)(9); -- Grant(3,9) +Grant(36) <= Signal_grant(12)(10) or Signal_grant(25)(10); -- Grant(3,10) +Grant(37) <= Signal_grant(13)(11) ; -- Grant(3,11) +Grant(38) <= Signal_grant(1)(12) or Signal_grant(14)(12); -- Grant(3,12) +Grant(39) <= Signal_grant(2)(13) or Signal_grant(15)(13); -- Grant(3,13) +Grant(40) <= Signal_grant(4)(1) or Signal_grant(17)(1); -- Grant(4,1) +Grant(41) <= Signal_grant(5)(2) or Signal_grant(18)(2); -- Grant(4,2) +Grant(42) <= Signal_grant(6)(3) or Signal_grant(19)(3); -- Grant(4,3) +Grant(43) <= Signal_grant(7)(4) or Signal_grant(20)(4); -- Grant(4,4) +Grant(44) <= Signal_grant(8)(5) or Signal_grant(21)(5); -- Grant(4,5) +Grant(45) <= Signal_grant(9)(6) or Signal_grant(22)(6); -- Grant(4,6) +Grant(46) <= Signal_grant(10)(7) or Signal_grant(23)(7); -- Grant(4,7) +Grant(47) <= Signal_grant(11)(8) or Signal_grant(24)(8); -- Grant(4,8) +Grant(48) <= Signal_grant(12)(9) or Signal_grant(25)(9); -- Grant(4,9) +Grant(49) <= Signal_grant(13)(10) ; -- Grant(4,10) +Grant(50) <= Signal_grant(1)(11) or Signal_grant(14)(11); -- Grant(4,11) +Grant(51) <= Signal_grant(2)(12) or Signal_grant(15)(12); -- Grant(4,12) +Grant(52) <= Signal_grant(3)(13) or Signal_grant(16)(13); -- Grant(4,13) +Grant(53) <= Signal_grant(5)(1) or Signal_grant(18)(1); -- Grant(5,1) +Grant(54) <= Signal_grant(6)(2) or Signal_grant(19)(2); -- Grant(5,2) +Grant(55) <= Signal_grant(7)(3) or Signal_grant(20)(3); -- Grant(5,3) +Grant(56) <= Signal_grant(8)(4) or Signal_grant(21)(4); -- Grant(5,4) +Grant(57) <= Signal_grant(9)(5) or Signal_grant(22)(5); -- Grant(5,5) +Grant(58) <= Signal_grant(10)(6) or Signal_grant(23)(6); -- Grant(5,6) +Grant(59) <= Signal_grant(11)(7) or Signal_grant(24)(7); -- Grant(5,7) +Grant(60) <= Signal_grant(12)(8) or Signal_grant(25)(8); -- Grant(5,8) +Grant(61) <= Signal_grant(13)(9) ; -- Grant(5,9) +Grant(62) <= Signal_grant(1)(10) or Signal_grant(14)(10); -- Grant(5,10) +Grant(63) <= Signal_grant(2)(11) or Signal_grant(15)(11); -- Grant(5,11) +Grant(64) <= Signal_grant(3)(12) or Signal_grant(16)(12); -- Grant(5,12) +Grant(65) <= Signal_grant(4)(13) or Signal_grant(17)(13); -- Grant(5,13) +Grant(66) <= Signal_grant(6)(1) or Signal_grant(19)(1); -- Grant(6,1) +Grant(67) <= Signal_grant(7)(2) or Signal_grant(20)(2); -- Grant(6,2) +Grant(68) <= Signal_grant(8)(3) or Signal_grant(21)(3); -- Grant(6,3) +Grant(69) <= Signal_grant(9)(4) or Signal_grant(22)(4); -- Grant(6,4) +Grant(70) <= Signal_grant(10)(5) or Signal_grant(23)(5); -- Grant(6,5) +Grant(71) <= Signal_grant(11)(6) or Signal_grant(24)(6); -- Grant(6,6) +Grant(72) <= Signal_grant(12)(7) or Signal_grant(25)(7); -- Grant(6,7) +Grant(73) <= Signal_grant(13)(8) ; -- Grant(6,8) +Grant(74) <= Signal_grant(1)(9) or Signal_grant(14)(9); -- Grant(6,9) +Grant(75) <= Signal_grant(2)(10) or Signal_grant(15)(10); -- Grant(6,10) +Grant(76) <= Signal_grant(3)(11) or Signal_grant(16)(11); -- Grant(6,11) +Grant(77) <= Signal_grant(4)(12) or Signal_grant(17)(12); -- Grant(6,12) +Grant(78) <= Signal_grant(5)(13) or Signal_grant(18)(13); -- Grant(6,13) +Grant(79) <= Signal_grant(7)(1) or Signal_grant(20)(1); -- Grant(7,1) +Grant(80) <= Signal_grant(8)(2) or Signal_grant(21)(2); -- Grant(7,2) +Grant(81) <= Signal_grant(9)(3) or Signal_grant(22)(3); -- Grant(7,3) +Grant(82) <= Signal_grant(10)(4) or Signal_grant(23)(4); -- Grant(7,4) +Grant(83) <= Signal_grant(11)(5) or Signal_grant(24)(5); -- Grant(7,5) +Grant(84) <= Signal_grant(12)(6) or Signal_grant(25)(6); -- Grant(7,6) +Grant(85) <= Signal_grant(13)(7) ; -- Grant(7,7) +Grant(86) <= Signal_grant(1)(8) or Signal_grant(14)(8); -- Grant(7,8) +Grant(87) <= Signal_grant(2)(9) or Signal_grant(15)(9); -- Grant(7,9) +Grant(88) <= Signal_grant(3)(10) or Signal_grant(16)(10); -- Grant(7,10) +Grant(89) <= Signal_grant(4)(11) or Signal_grant(17)(11); -- Grant(7,11) +Grant(90) <= Signal_grant(5)(12) or Signal_grant(18)(12); -- Grant(7,12) +Grant(91) <= Signal_grant(6)(13) or Signal_grant(19)(13); -- Grant(7,13) +Grant(92) <= Signal_grant(8)(1) or Signal_grant(21)(1); -- Grant(8,1) +Grant(93) <= Signal_grant(9)(2) or Signal_grant(22)(2); -- Grant(8,2) +Grant(94) <= Signal_grant(10)(3) or Signal_grant(23)(3); -- Grant(8,3) +Grant(95) <= Signal_grant(11)(4) or Signal_grant(24)(4); -- Grant(8,4) +Grant(96) <= Signal_grant(12)(5) or Signal_grant(25)(5); -- Grant(8,5) +Grant(97) <= Signal_grant(13)(6) ; -- Grant(8,6) +Grant(98) <= Signal_grant(1)(7) or Signal_grant(14)(7); -- Grant(8,7) +Grant(99) <= Signal_grant(2)(8) or Signal_grant(15)(8); -- Grant(8,8) +Grant(100) <= Signal_grant(3)(9) or Signal_grant(16)(9); -- Grant(8,9) +Grant(101) <= Signal_grant(4)(10) or Signal_grant(17)(10); -- Grant(8,10) +Grant(102) <= Signal_grant(5)(11) or Signal_grant(18)(11); -- Grant(8,11) +Grant(103) <= Signal_grant(6)(12) or Signal_grant(19)(12); -- Grant(8,12) +Grant(104) <= Signal_grant(7)(13) or Signal_grant(20)(13); -- Grant(8,13) +Grant(105) <= Signal_grant(9)(1) or Signal_grant(22)(1); -- Grant(9,1) +Grant(106) <= Signal_grant(10)(2) or Signal_grant(23)(2); -- Grant(9,2) +Grant(107) <= Signal_grant(11)(3) or Signal_grant(24)(3); -- Grant(9,3) +Grant(108) <= Signal_grant(12)(4) or Signal_grant(25)(4); -- Grant(9,4) +Grant(109) <= Signal_grant(13)(5) ; -- Grant(9,5) +Grant(110) <= Signal_grant(1)(6) or Signal_grant(14)(6); -- Grant(9,6) +Grant(111) <= Signal_grant(2)(7) or Signal_grant(15)(7); -- Grant(9,7) +Grant(112) <= Signal_grant(3)(8) or Signal_grant(16)(8); -- Grant(9,8) +Grant(113) <= Signal_grant(4)(9) or Signal_grant(17)(9); -- Grant(9,9) +Grant(114) <= Signal_grant(5)(10) or Signal_grant(18)(10); -- Grant(9,10) +Grant(115) <= Signal_grant(6)(11) or Signal_grant(19)(11); -- Grant(9,11) +Grant(116) <= Signal_grant(7)(12) or Signal_grant(20)(12); -- Grant(9,12) +Grant(117) <= Signal_grant(8)(13) or Signal_grant(21)(13); -- Grant(9,13) +Grant(118) <= Signal_grant(10)(1) or Signal_grant(23)(1); -- Grant(10,1) +Grant(119) <= Signal_grant(11)(2) or Signal_grant(24)(2); -- Grant(10,2) +Grant(120) <= Signal_grant(12)(3) or Signal_grant(25)(3); -- Grant(10,3) +Grant(121) <= Signal_grant(13)(4) ; -- Grant(10,4) +Grant(122) <= Signal_grant(1)(5) or Signal_grant(14)(5); -- Grant(10,5) +Grant(123) <= Signal_grant(2)(6) or Signal_grant(15)(6); -- Grant(10,6) +Grant(124) <= Signal_grant(3)(7) or Signal_grant(16)(7); -- Grant(10,7) +Grant(125) <= Signal_grant(4)(8) or Signal_grant(17)(8); -- Grant(10,8) +Grant(126) <= Signal_grant(5)(9) or Signal_grant(18)(9); -- Grant(10,9) +Grant(127) <= Signal_grant(6)(10) or Signal_grant(19)(10); -- Grant(10,10) +Grant(128) <= Signal_grant(7)(11) or Signal_grant(20)(11); -- Grant(10,11) +Grant(129) <= Signal_grant(8)(12) or Signal_grant(21)(12); -- Grant(10,12) +Grant(130) <= Signal_grant(9)(13) or Signal_grant(22)(13); -- Grant(10,13) +Grant(131) <= Signal_grant(11)(1) or Signal_grant(24)(1); -- Grant(11,1) +Grant(132) <= Signal_grant(12)(2) or Signal_grant(25)(2); -- Grant(11,2) +Grant(133) <= Signal_grant(13)(3) ; -- Grant(11,3) +Grant(134) <= Signal_grant(1)(4) or Signal_grant(14)(4); -- Grant(11,4) +Grant(135) <= Signal_grant(2)(5) or Signal_grant(15)(5); -- Grant(11,5) +Grant(136) <= Signal_grant(3)(6) or Signal_grant(16)(6); -- Grant(11,6) +Grant(137) <= Signal_grant(4)(7) or Signal_grant(17)(7); -- Grant(11,7) +Grant(138) <= Signal_grant(5)(8) or Signal_grant(18)(8); -- Grant(11,8) +Grant(139) <= Signal_grant(6)(9) or Signal_grant(19)(9); -- Grant(11,9) +Grant(140) <= Signal_grant(7)(10) or Signal_grant(20)(10); -- Grant(11,10) +Grant(141) <= Signal_grant(8)(11) or Signal_grant(21)(11); -- Grant(11,11) +Grant(142) <= Signal_grant(9)(12) or Signal_grant(22)(12); -- Grant(11,12) +Grant(143) <= Signal_grant(10)(13) or Signal_grant(23)(13); -- Grant(11,13) +Grant(144) <= Signal_grant(12)(1) or Signal_grant(25)(1); -- Grant(12,1) +Grant(145) <= Signal_grant(13)(2) ; -- Grant(12,2) +Grant(146) <= Signal_grant(1)(3) or Signal_grant(14)(3); -- Grant(12,3) +Grant(147) <= Signal_grant(2)(4) or Signal_grant(15)(4); -- Grant(12,4) +Grant(148) <= Signal_grant(3)(5) or Signal_grant(16)(5); -- Grant(12,5) +Grant(149) <= Signal_grant(4)(6) or Signal_grant(17)(6); -- Grant(12,6) +Grant(150) <= Signal_grant(5)(7) or Signal_grant(18)(7); -- Grant(12,7) +Grant(151) <= Signal_grant(6)(8) or Signal_grant(19)(8); -- Grant(12,8) +Grant(152) <= Signal_grant(7)(9) or Signal_grant(20)(9); -- Grant(12,9) +Grant(153) <= Signal_grant(8)(10) or Signal_grant(21)(10); -- Grant(12,10) +Grant(154) <= Signal_grant(9)(11) or Signal_grant(22)(11); -- Grant(12,11) +Grant(155) <= Signal_grant(10)(12) or Signal_grant(23)(12); -- Grant(12,12) +Grant(156) <= Signal_grant(11)(13) or Signal_grant(24)(13); -- Grant(12,13) +Grant(157) <= Signal_grant(13)(1) ; -- Grant(13,1) +Grant(158) <= Signal_grant(1)(2) or Signal_grant(14)(2); -- Grant(13,2) +Grant(159) <= Signal_grant(2)(3) or Signal_grant(15)(3); -- Grant(13,3) +Grant(160) <= Signal_grant(3)(4) or Signal_grant(16)(4); -- Grant(13,4) +Grant(161) <= Signal_grant(4)(5) or Signal_grant(17)(5); -- Grant(13,5) +Grant(162) <= Signal_grant(5)(6) or Signal_grant(18)(6); -- Grant(13,6) +Grant(163) <= Signal_grant(6)(7) or Signal_grant(19)(7); -- Grant(13,7) +Grant(164) <= Signal_grant(7)(8) or Signal_grant(20)(8); -- Grant(13,8) +Grant(165) <= Signal_grant(8)(9) or Signal_grant(21)(9); -- Grant(13,9) +Grant(166) <= Signal_grant(9)(10) or Signal_grant(22)(10); -- Grant(13,10) +Grant(167) <= Signal_grant(10)(11) or Signal_grant(23)(11); -- Grant(13,11) +Grant(168) <= Signal_grant(11)(12) or Signal_grant(24)(12); -- Grant(13,12) +Grant(169) <= Signal_grant(12)(13) or Signal_grant(25)(13); -- Grant(13,13) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(158), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(146), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(134), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +Arbiter_1_5 : Arbiter + +PORT MAP (Request => Request(122), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(5), +South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); + +Arbiter_1_6 : Arbiter + +PORT MAP (Request => Request(110), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(6), +South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); + +Arbiter_1_7 : Arbiter + +PORT MAP (Request => Request(98), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(7), +South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); + +Arbiter_1_8 : Arbiter + +PORT MAP (Request => Request(86), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(8), +South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); + +Arbiter_1_9 : Arbiter + +PORT MAP (Request => Request(74), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(9), +South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); + +Arbiter_1_10 : Arbiter + +PORT MAP (Request => Request(62), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(10), +South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); + +Arbiter_1_11 : Arbiter + +PORT MAP (Request => Request(50), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(11), +South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); + +Arbiter_1_12 : Arbiter + +PORT MAP (Request => Request(38), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(12), +South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); + +Arbiter_1_13 : Arbiter + +PORT MAP (Request => Request(26), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(13), +South => south_2_north(1)(13), East => east_2_west(1)(13) , Grant => Signal_grant(1)(13)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(1)(1), West => east_2_west(1)(13), P => Signal_priority(24), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(24), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(159), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(24), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(147), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(24), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +Arbiter_2_5 : Arbiter + +PORT MAP (Request => Request(135), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(24), Fifo_full => Fifo_full(5), +South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); + +Arbiter_2_6 : Arbiter + +PORT MAP (Request => Request(123), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(24), Fifo_full => Fifo_full(6), +South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); + +Arbiter_2_7 : Arbiter + +PORT MAP (Request => Request(111), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(24), Fifo_full => Fifo_full(7), +South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); + +Arbiter_2_8 : Arbiter + +PORT MAP (Request => Request(99), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(24), Fifo_full => Fifo_full(8), +South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); + +Arbiter_2_9 : Arbiter + +PORT MAP (Request => Request(87), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(24), Fifo_full => Fifo_full(9), +South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); + +Arbiter_2_10 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(24), Fifo_full => Fifo_full(10), +South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); + +Arbiter_2_11 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(24), Fifo_full => Fifo_full(11), +South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); + +Arbiter_2_12 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(24), Fifo_full => Fifo_full(12), +South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); + +Arbiter_2_13 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(1)(13), West => east_2_west(1)(12), P => Signal_priority(24), Fifo_full => Fifo_full(13), +South => south_2_north(2)(13), East => east_2_west(2)(13) , Grant => Signal_grant(2)(13)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(2)(1), West => east_2_west(2)(13), P => Signal_priority(23), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(23), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(23), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(160), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(23), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +Arbiter_3_5 : Arbiter + +PORT MAP (Request => Request(148), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(23), Fifo_full => Fifo_full(5), +South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); + +Arbiter_3_6 : Arbiter + +PORT MAP (Request => Request(136), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(23), Fifo_full => Fifo_full(6), +South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); + +Arbiter_3_7 : Arbiter + +PORT MAP (Request => Request(124), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(23), Fifo_full => Fifo_full(7), +South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); + +Arbiter_3_8 : Arbiter + +PORT MAP (Request => Request(112), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(23), Fifo_full => Fifo_full(8), +South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); + +Arbiter_3_9 : Arbiter + +PORT MAP (Request => Request(100), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(23), Fifo_full => Fifo_full(9), +South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); + +Arbiter_3_10 : Arbiter + +PORT MAP (Request => Request(88), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(23), Fifo_full => Fifo_full(10), +South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); + +Arbiter_3_11 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(23), Fifo_full => Fifo_full(11), +South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); + +Arbiter_3_12 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(23), Fifo_full => Fifo_full(12), +South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); + +Arbiter_3_13 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(2)(13), West => east_2_west(2)(12), P => Signal_priority(23), Fifo_full => Fifo_full(13), +South => south_2_north(3)(13), East => east_2_west(3)(13) , Grant => Signal_grant(3)(13)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(3)(1), West => east_2_west(3)(13), P => Signal_priority(22), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +Arbiter_4_5 : Arbiter + +PORT MAP (Request => Request(161), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5), +South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); + +Arbiter_4_6 : Arbiter + +PORT MAP (Request => Request(149), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6), +South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); + +Arbiter_4_7 : Arbiter + +PORT MAP (Request => Request(137), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7), +South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); + +Arbiter_4_8 : Arbiter + +PORT MAP (Request => Request(125), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8), +South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); + +Arbiter_4_9 : Arbiter + +PORT MAP (Request => Request(113), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9), +South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); + +Arbiter_4_10 : Arbiter + +PORT MAP (Request => Request(101), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10), +South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); + +Arbiter_4_11 : Arbiter + +PORT MAP (Request => Request(89), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11), +South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); + +Arbiter_4_12 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12), +South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); + +Arbiter_4_13 : Arbiter + +PORT MAP (Request => Request(65), North => south_2_north(3)(13), West => east_2_west(3)(12), P => Signal_priority(22), Fifo_full => Fifo_full(13), +South => south_2_north(4)(13), East => east_2_west(4)(13) , Grant => Signal_grant(4)(13)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(4)(1), West => east_2_west(4)(13), P => Signal_priority(21), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +Arbiter_5_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5), +South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); + +Arbiter_5_6 : Arbiter + +PORT MAP (Request => Request(162), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6), +South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); + +Arbiter_5_7 : Arbiter + +PORT MAP (Request => Request(150), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7), +South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); + +Arbiter_5_8 : Arbiter + +PORT MAP (Request => Request(138), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8), +South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); + +Arbiter_5_9 : Arbiter + +PORT MAP (Request => Request(126), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9), +South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); + +Arbiter_5_10 : Arbiter + +PORT MAP (Request => Request(114), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10), +South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); + +Arbiter_5_11 : Arbiter + +PORT MAP (Request => Request(102), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11), +South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); + +Arbiter_5_12 : Arbiter + +PORT MAP (Request => Request(90), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12), +South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); + +Arbiter_5_13 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(4)(13), West => east_2_west(4)(12), P => Signal_priority(21), Fifo_full => Fifo_full(13), +South => south_2_north(5)(13), East => east_2_west(5)(13) , Grant => Signal_grant(5)(13)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(66), North => south_2_north(5)(1), West => east_2_west(5)(13), P => Signal_priority(20), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +Arbiter_6_5 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5), +South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); + +Arbiter_6_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6), +South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); + +Arbiter_6_7 : Arbiter + +PORT MAP (Request => Request(163), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7), +South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); + +Arbiter_6_8 : Arbiter + +PORT MAP (Request => Request(151), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8), +South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); + +Arbiter_6_9 : Arbiter + +PORT MAP (Request => Request(139), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9), +South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); + +Arbiter_6_10 : Arbiter + +PORT MAP (Request => Request(127), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10), +South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); + +Arbiter_6_11 : Arbiter + +PORT MAP (Request => Request(115), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11), +South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); + +Arbiter_6_12 : Arbiter + +PORT MAP (Request => Request(103), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12), +South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); + +Arbiter_6_13 : Arbiter + +PORT MAP (Request => Request(91), North => south_2_north(5)(13), West => east_2_west(5)(12), P => Signal_priority(20), Fifo_full => Fifo_full(13), +South => south_2_north(6)(13), East => east_2_west(6)(13) , Grant => Signal_grant(6)(13)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(79), North => south_2_north(6)(1), West => east_2_west(6)(13), P => Signal_priority(19), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(67), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + +Arbiter_7_5 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5), +South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); + +Arbiter_7_6 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6), +South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); + +Arbiter_7_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7), +South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); + +Arbiter_7_8 : Arbiter + +PORT MAP (Request => Request(164), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8), +South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); + +Arbiter_7_9 : Arbiter + +PORT MAP (Request => Request(152), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9), +South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); + +Arbiter_7_10 : Arbiter + +PORT MAP (Request => Request(140), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10), +South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); + +Arbiter_7_11 : Arbiter + +PORT MAP (Request => Request(128), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11), +South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); + +Arbiter_7_12 : Arbiter + +PORT MAP (Request => Request(116), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12), +South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); + +Arbiter_7_13 : Arbiter + +PORT MAP (Request => Request(104), North => south_2_north(6)(13), West => east_2_west(6)(12), P => Signal_priority(19), Fifo_full => Fifo_full(13), +South => south_2_north(7)(13), East => east_2_west(7)(13) , Grant => Signal_grant(7)(13)); + +-------------------------- Diagonale n° 8 + + +Arbiter_8_1 : Arbiter + +PORT MAP (Request => Request(92), North => south_2_north(7)(1), West => east_2_west(7)(13), P => Signal_priority(18), Fifo_full => Fifo_full(1), +South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); + +Arbiter_8_2 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2), +South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); + +Arbiter_8_3 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3), +South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); + +Arbiter_8_4 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4), +South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); + +Arbiter_8_5 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5), +South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); + +Arbiter_8_6 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6), +South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); + +Arbiter_8_7 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7), +South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); + +Arbiter_8_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8), +South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); + +Arbiter_8_9 : Arbiter + +PORT MAP (Request => Request(165), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9), +South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); + +Arbiter_8_10 : Arbiter + +PORT MAP (Request => Request(153), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10), +South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); + +Arbiter_8_11 : Arbiter + +PORT MAP (Request => Request(141), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11), +South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); + +Arbiter_8_12 : Arbiter + +PORT MAP (Request => Request(129), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12), +South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); + +Arbiter_8_13 : Arbiter + +PORT MAP (Request => Request(117), North => south_2_north(7)(13), West => east_2_west(7)(12), P => Signal_priority(18), Fifo_full => Fifo_full(13), +South => south_2_north(8)(13), East => east_2_west(8)(13) , Grant => Signal_grant(8)(13)); + +-------------------------- Diagonale n° 9 + + +Arbiter_9_1 : Arbiter + +PORT MAP (Request => Request(105), North => south_2_north(8)(1), West => east_2_west(8)(13), P => Signal_priority(17), Fifo_full => Fifo_full(1), +South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); + +Arbiter_9_2 : Arbiter + +PORT MAP (Request => Request(93), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2), +South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); + +Arbiter_9_3 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3), +South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); + +Arbiter_9_4 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4), +South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); + +Arbiter_9_5 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5), +South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); + +Arbiter_9_6 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6), +South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); + +Arbiter_9_7 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7), +South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); + +Arbiter_9_8 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8), +South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); + +Arbiter_9_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9), +South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); + +Arbiter_9_10 : Arbiter + +PORT MAP (Request => Request(166), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10), +South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); + +Arbiter_9_11 : Arbiter + +PORT MAP (Request => Request(154), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11), +South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); + +Arbiter_9_12 : Arbiter + +PORT MAP (Request => Request(142), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12), +South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); + +Arbiter_9_13 : Arbiter + +PORT MAP (Request => Request(130), North => south_2_north(8)(13), West => east_2_west(8)(12), P => Signal_priority(17), Fifo_full => Fifo_full(13), +South => south_2_north(9)(13), East => east_2_west(9)(13) , Grant => Signal_grant(9)(13)); + +-------------------------- Diagonale n° 10 + + +Arbiter_10_1 : Arbiter + +PORT MAP (Request => Request(118), North => south_2_north(9)(1), West => east_2_west(9)(13), P => Signal_priority(16), Fifo_full => Fifo_full(1), +South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); + +Arbiter_10_2 : Arbiter + +PORT MAP (Request => Request(106), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2), +South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); + +Arbiter_10_3 : Arbiter + +PORT MAP (Request => Request(94), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3), +South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); + +Arbiter_10_4 : Arbiter + +PORT MAP (Request => Request(82), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4), +South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); + +Arbiter_10_5 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5), +South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); + +Arbiter_10_6 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6), +South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); + +Arbiter_10_7 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7), +South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); + +Arbiter_10_8 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8), +South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); + +Arbiter_10_9 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9), +South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); + +Arbiter_10_10 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10), +South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); + +Arbiter_10_11 : Arbiter + +PORT MAP (Request => Request(167), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11), +South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); + +Arbiter_10_12 : Arbiter + +PORT MAP (Request => Request(155), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12), +South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); + +Arbiter_10_13 : Arbiter + +PORT MAP (Request => Request(143), North => south_2_north(9)(13), West => east_2_west(9)(12), P => Signal_priority(16), Fifo_full => Fifo_full(13), +South => south_2_north(10)(13), East => east_2_west(10)(13) , Grant => Signal_grant(10)(13)); + +-------------------------- Diagonale n° 11 + + +Arbiter_11_1 : Arbiter + +PORT MAP (Request => Request(131), North => south_2_north(10)(1), West => east_2_west(10)(13), P => Signal_priority(15), Fifo_full => Fifo_full(1), +South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); + +Arbiter_11_2 : Arbiter + +PORT MAP (Request => Request(119), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2), +South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); + +Arbiter_11_3 : Arbiter + +PORT MAP (Request => Request(107), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3), +South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); + +Arbiter_11_4 : Arbiter + +PORT MAP (Request => Request(95), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4), +South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); + +Arbiter_11_5 : Arbiter + +PORT MAP (Request => Request(83), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5), +South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); + +Arbiter_11_6 : Arbiter + +PORT MAP (Request => Request(71), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6), +South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); + +Arbiter_11_7 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7), +South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); + +Arbiter_11_8 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8), +South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); + +Arbiter_11_9 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9), +South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); + +Arbiter_11_10 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10), +South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); + +Arbiter_11_11 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11), +South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); + +Arbiter_11_12 : Arbiter + +PORT MAP (Request => Request(168), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12), +South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); + +Arbiter_11_13 : Arbiter + +PORT MAP (Request => Request(156), North => south_2_north(10)(13), West => east_2_west(10)(12), P => Signal_priority(15), Fifo_full => Fifo_full(13), +South => south_2_north(11)(13), East => east_2_west(11)(13) , Grant => Signal_grant(11)(13)); + +-------------------------- Diagonale n° 12 + + +Arbiter_12_1 : Arbiter + +PORT MAP (Request => Request(144), North => south_2_north(11)(1), West => east_2_west(11)(13), P => Signal_priority(14), Fifo_full => Fifo_full(1), +South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); + +Arbiter_12_2 : Arbiter + +PORT MAP (Request => Request(132), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2), +South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); + +Arbiter_12_3 : Arbiter + +PORT MAP (Request => Request(120), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3), +South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); + +Arbiter_12_4 : Arbiter + +PORT MAP (Request => Request(108), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4), +South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); + +Arbiter_12_5 : Arbiter + +PORT MAP (Request => Request(96), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5), +South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); + +Arbiter_12_6 : Arbiter + +PORT MAP (Request => Request(84), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6), +South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); + +Arbiter_12_7 : Arbiter + +PORT MAP (Request => Request(72), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7), +South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); + +Arbiter_12_8 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8), +South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); + +Arbiter_12_9 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9), +South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); + +Arbiter_12_10 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10), +South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); + +Arbiter_12_11 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11), +South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); + +Arbiter_12_12 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12), +South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); + +Arbiter_12_13 : Arbiter + +PORT MAP (Request => Request(169), North => south_2_north(11)(13), West => east_2_west(11)(12), P => Signal_priority(14), Fifo_full => Fifo_full(13), +South => south_2_north(12)(13), East => east_2_west(12)(13) , Grant => Signal_grant(12)(13)); + +-------------------------- Diagonale n° 13 + + +Arbiter_13_1 : Arbiter + +PORT MAP (Request => Request(157), North => south_2_north(12)(1), West => east_2_west(12)(13), P => Signal_priority(13), Fifo_full => Fifo_full(1), +South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); + +Arbiter_13_2 : Arbiter + +PORT MAP (Request => Request(145), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2), +South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); + +Arbiter_13_3 : Arbiter + +PORT MAP (Request => Request(133), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3), +South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); + +Arbiter_13_4 : Arbiter + +PORT MAP (Request => Request(121), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4), +South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); + +Arbiter_13_5 : Arbiter + +PORT MAP (Request => Request(109), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5), +South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); + +Arbiter_13_6 : Arbiter + +PORT MAP (Request => Request(97), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6), +South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); + +Arbiter_13_7 : Arbiter + +PORT MAP (Request => Request(85), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7), +South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); + +Arbiter_13_8 : Arbiter + +PORT MAP (Request => Request(73), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8), +South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); + +Arbiter_13_9 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9), +South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); + +Arbiter_13_10 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10), +South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); + +Arbiter_13_11 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11), +South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); + +Arbiter_13_12 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12), +South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); + +Arbiter_13_13 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(12)(13), West => east_2_west(12)(12), P => Signal_priority(13), Fifo_full => Fifo_full(13), +South => south_2_north(13)(13), East => east_2_west(13)(13) , Grant => Signal_grant(13)(13)); + +-------------------------- Diagonale n° 14 + + +Arbiter_14_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(13)(1), West => east_2_west(13)(13), P => Signal_priority(12), Fifo_full => Fifo_full(1), +South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); + +Arbiter_14_2 : Arbiter + +PORT MAP (Request => Request(158), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2), +South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); + +Arbiter_14_3 : Arbiter + +PORT MAP (Request => Request(146), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3), +South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); + +Arbiter_14_4 : Arbiter + +PORT MAP (Request => Request(134), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4), +South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); + +Arbiter_14_5 : Arbiter + +PORT MAP (Request => Request(122), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5), +South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); + +Arbiter_14_6 : Arbiter + +PORT MAP (Request => Request(110), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6), +South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); + +Arbiter_14_7 : Arbiter + +PORT MAP (Request => Request(98), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7), +South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); + +Arbiter_14_8 : Arbiter + +PORT MAP (Request => Request(86), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8), +South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); + +Arbiter_14_9 : Arbiter + +PORT MAP (Request => Request(74), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9), +South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); + +Arbiter_14_10 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10), +South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); + +Arbiter_14_11 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11), +South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); + +Arbiter_14_12 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12), +South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); + +Arbiter_14_13 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(13)(13), West => east_2_west(13)(12), P => Signal_priority(12), Fifo_full => Fifo_full(13), +South => south_2_north(14)(13), East => east_2_west(14)(13) , Grant => Signal_grant(14)(13)); + +-------------------------- Diagonale n° 15 + + +Arbiter_15_1 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(14)(1), West => east_2_west(14)(13), P => Signal_priority(11), Fifo_full => Fifo_full(1), +South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); + +Arbiter_15_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2), +South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); + +Arbiter_15_3 : Arbiter + +PORT MAP (Request => Request(159), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3), +South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); + +Arbiter_15_4 : Arbiter + +PORT MAP (Request => Request(147), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4), +South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); + +Arbiter_15_5 : Arbiter + +PORT MAP (Request => Request(135), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5), +South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); + +Arbiter_15_6 : Arbiter + +PORT MAP (Request => Request(123), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6), +South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); + +Arbiter_15_7 : Arbiter + +PORT MAP (Request => Request(111), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7), +South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); + +Arbiter_15_8 : Arbiter + +PORT MAP (Request => Request(99), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8), +South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); + +Arbiter_15_9 : Arbiter + +PORT MAP (Request => Request(87), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9), +South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); + +Arbiter_15_10 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10), +South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); + +Arbiter_15_11 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11), +South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); + +Arbiter_15_12 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12), +South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); + +Arbiter_15_13 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(14)(13), West => east_2_west(14)(12), P => Signal_priority(11), Fifo_full => Fifo_full(13), +South => south_2_north(15)(13), East => east_2_west(15)(13) , Grant => Signal_grant(15)(13)); + +-------------------------- Diagonale n° 16 + + +Arbiter_16_1 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(15)(1), West => east_2_west(15)(13), P => Signal_priority(10), Fifo_full => Fifo_full(1), +South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); + +Arbiter_16_2 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2), +South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); + +Arbiter_16_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3), +South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); + +Arbiter_16_4 : Arbiter + +PORT MAP (Request => Request(160), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4), +South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); + +Arbiter_16_5 : Arbiter + +PORT MAP (Request => Request(148), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5), +South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); + +Arbiter_16_6 : Arbiter + +PORT MAP (Request => Request(136), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6), +South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); + +Arbiter_16_7 : Arbiter + +PORT MAP (Request => Request(124), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7), +South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); + +Arbiter_16_8 : Arbiter + +PORT MAP (Request => Request(112), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8), +South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); + +Arbiter_16_9 : Arbiter + +PORT MAP (Request => Request(100), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9), +South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); + +Arbiter_16_10 : Arbiter + +PORT MAP (Request => Request(88), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10), +South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); + +Arbiter_16_11 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11), +South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); + +Arbiter_16_12 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12), +South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); + +Arbiter_16_13 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(15)(13), West => east_2_west(15)(12), P => Signal_priority(10), Fifo_full => Fifo_full(13), +South => south_2_north(16)(13), East => east_2_west(16)(13) , Grant => Signal_grant(16)(13)); + +-------------------------- Diagonale n° 17 + + +Arbiter_17_1 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(16)(1), West => east_2_west(16)(13), P => Signal_priority(9), Fifo_full => Fifo_full(1), +South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); + +Arbiter_17_2 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2), +South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); + +Arbiter_17_3 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3), +South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); + +Arbiter_17_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4), +South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); + +Arbiter_17_5 : Arbiter + +PORT MAP (Request => Request(161), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5), +South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); + +Arbiter_17_6 : Arbiter + +PORT MAP (Request => Request(149), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6), +South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); + +Arbiter_17_7 : Arbiter + +PORT MAP (Request => Request(137), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7), +South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); + +Arbiter_17_8 : Arbiter + +PORT MAP (Request => Request(125), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8), +South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); + +Arbiter_17_9 : Arbiter + +PORT MAP (Request => Request(113), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9), +South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); + +Arbiter_17_10 : Arbiter + +PORT MAP (Request => Request(101), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10), +South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); + +Arbiter_17_11 : Arbiter + +PORT MAP (Request => Request(89), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11), +South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); + +Arbiter_17_12 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12), +South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); + +Arbiter_17_13 : Arbiter + +PORT MAP (Request => Request(65), North => south_2_north(16)(13), West => east_2_west(16)(12), P => Signal_priority(9), Fifo_full => Fifo_full(13), +South => south_2_north(17)(13), East => east_2_west(17)(13) , Grant => Signal_grant(17)(13)); + +-------------------------- Diagonale n° 18 + + +Arbiter_18_1 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(17)(1), West => east_2_west(17)(13), P => Signal_priority(8), Fifo_full => Fifo_full(1), +South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); + +Arbiter_18_2 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2), +South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); + +Arbiter_18_3 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3), +South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); + +Arbiter_18_4 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4), +South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); + +Arbiter_18_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5), +South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); + +Arbiter_18_6 : Arbiter + +PORT MAP (Request => Request(162), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6), +South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); + +Arbiter_18_7 : Arbiter + +PORT MAP (Request => Request(150), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7), +South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); + +Arbiter_18_8 : Arbiter + +PORT MAP (Request => Request(138), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8), +South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); + +Arbiter_18_9 : Arbiter + +PORT MAP (Request => Request(126), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9), +South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); + +Arbiter_18_10 : Arbiter + +PORT MAP (Request => Request(114), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10), +South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); + +Arbiter_18_11 : Arbiter + +PORT MAP (Request => Request(102), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11), +South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); + +Arbiter_18_12 : Arbiter + +PORT MAP (Request => Request(90), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12), +South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); + +Arbiter_18_13 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(17)(13), West => east_2_west(17)(12), P => Signal_priority(8), Fifo_full => Fifo_full(13), +South => south_2_north(18)(13), East => east_2_west(18)(13) , Grant => Signal_grant(18)(13)); + +-------------------------- Diagonale n° 19 + + +Arbiter_19_1 : Arbiter + +PORT MAP (Request => Request(66), North => south_2_north(18)(1), West => east_2_west(18)(13), P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); + +Arbiter_19_2 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); + +Arbiter_19_3 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); + +Arbiter_19_4 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); + +Arbiter_19_5 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5), +South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); + +Arbiter_19_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6), +South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); + +Arbiter_19_7 : Arbiter + +PORT MAP (Request => Request(163), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7), +South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); + +Arbiter_19_8 : Arbiter + +PORT MAP (Request => Request(151), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8), +South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); + +Arbiter_19_9 : Arbiter + +PORT MAP (Request => Request(139), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9), +South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); + +Arbiter_19_10 : Arbiter + +PORT MAP (Request => Request(127), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10), +South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); + +Arbiter_19_11 : Arbiter + +PORT MAP (Request => Request(115), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11), +South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); + +Arbiter_19_12 : Arbiter + +PORT MAP (Request => Request(103), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12), +South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); + +Arbiter_19_13 : Arbiter + +PORT MAP (Request => Request(91), North => south_2_north(18)(13), West => east_2_west(18)(12), P => Signal_priority(7), Fifo_full => Fifo_full(13), +South => south_2_north(19)(13), East => east_2_west(19)(13) , Grant => Signal_grant(19)(13)); + +-------------------------- Diagonale n° 20 + + +Arbiter_20_1 : Arbiter + +PORT MAP (Request => Request(79), North => south_2_north(19)(1), West => east_2_west(19)(13), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); + +Arbiter_20_2 : Arbiter + +PORT MAP (Request => Request(67), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); + +Arbiter_20_3 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); + +Arbiter_20_4 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); + +Arbiter_20_5 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5), +South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); + +Arbiter_20_6 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6), +South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); + +Arbiter_20_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7), +South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); + +Arbiter_20_8 : Arbiter + +PORT MAP (Request => Request(164), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8), +South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); + +Arbiter_20_9 : Arbiter + +PORT MAP (Request => Request(152), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9), +South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); + +Arbiter_20_10 : Arbiter + +PORT MAP (Request => Request(140), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10), +South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); + +Arbiter_20_11 : Arbiter + +PORT MAP (Request => Request(128), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11), +South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); + +Arbiter_20_12 : Arbiter + +PORT MAP (Request => Request(116), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12), +South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); + +Arbiter_20_13 : Arbiter + +PORT MAP (Request => Request(104), North => south_2_north(19)(13), West => east_2_west(19)(12), P => Signal_priority(6), Fifo_full => Fifo_full(13), +South => south_2_north(20)(13), East => east_2_west(20)(13) , Grant => Signal_grant(20)(13)); + +-------------------------- Diagonale n° 21 + + +Arbiter_21_1 : Arbiter + +PORT MAP (Request => Request(92), North => south_2_north(20)(1), West => east_2_west(20)(13), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); + +Arbiter_21_2 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); + +Arbiter_21_3 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); + +Arbiter_21_4 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); + +Arbiter_21_5 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5), +South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); + +Arbiter_21_6 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6), +South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); + +Arbiter_21_7 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7), +South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); + +Arbiter_21_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8), +South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); + +Arbiter_21_9 : Arbiter + +PORT MAP (Request => Request(165), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9), +South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); + +Arbiter_21_10 : Arbiter + +PORT MAP (Request => Request(153), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10), +South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); + +Arbiter_21_11 : Arbiter + +PORT MAP (Request => Request(141), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11), +South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); + +Arbiter_21_12 : Arbiter + +PORT MAP (Request => Request(129), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12), +South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); + +Arbiter_21_13 : Arbiter + +PORT MAP (Request => Request(117), North => south_2_north(20)(13), West => east_2_west(20)(12), P => Signal_priority(5), Fifo_full => Fifo_full(13), +South => south_2_north(21)(13), East => east_2_west(21)(13) , Grant => Signal_grant(21)(13)); + +-------------------------- Diagonale n° 22 + + +Arbiter_22_1 : Arbiter + +PORT MAP (Request => Request(105), North => south_2_north(21)(1), West => east_2_west(21)(13), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); + +Arbiter_22_2 : Arbiter + +PORT MAP (Request => Request(93), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); + +Arbiter_22_3 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); + +Arbiter_22_4 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); + +Arbiter_22_5 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5), +South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); + +Arbiter_22_6 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6), +South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); + +Arbiter_22_7 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7), +South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); + +Arbiter_22_8 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8), +South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); + +Arbiter_22_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9), +South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); + +Arbiter_22_10 : Arbiter + +PORT MAP (Request => Request(166), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10), +South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); + +Arbiter_22_11 : Arbiter + +PORT MAP (Request => Request(154), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11), +South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); + +Arbiter_22_12 : Arbiter + +PORT MAP (Request => Request(142), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12), +South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); + +Arbiter_22_13 : Arbiter + +PORT MAP (Request => Request(130), North => south_2_north(21)(13), West => east_2_west(21)(12), P => Signal_priority(4), Fifo_full => Fifo_full(13), +South => south_2_north(22)(13), East => east_2_west(22)(13) , Grant => Signal_grant(22)(13)); + +-------------------------- Diagonale n° 23 + + +Arbiter_23_1 : Arbiter + +PORT MAP (Request => Request(118), North => south_2_north(22)(1), West => east_2_west(22)(13), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); + +Arbiter_23_2 : Arbiter + +PORT MAP (Request => Request(106), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); + +Arbiter_23_3 : Arbiter + +PORT MAP (Request => Request(94), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); + +Arbiter_23_4 : Arbiter + +PORT MAP (Request => Request(82), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); + +Arbiter_23_5 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5), +South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); + +Arbiter_23_6 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6), +South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); + +Arbiter_23_7 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7), +South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); + +Arbiter_23_8 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8), +South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); + +Arbiter_23_9 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9), +South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); + +Arbiter_23_10 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10), +South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); + +Arbiter_23_11 : Arbiter + +PORT MAP (Request => Request(167), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11), +South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); + +Arbiter_23_12 : Arbiter + +PORT MAP (Request => Request(155), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12), +South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); + +Arbiter_23_13 : Arbiter + +PORT MAP (Request => Request(143), North => south_2_north(22)(13), West => east_2_west(22)(12), P => Signal_priority(3), Fifo_full => Fifo_full(13), +South => south_2_north(23)(13), East => east_2_west(23)(13) , Grant => Signal_grant(23)(13)); + +-------------------------- Diagonale n° 24 + + +Arbiter_24_1 : Arbiter + +PORT MAP (Request => Request(131), North => south_2_north(23)(1), West => east_2_west(23)(13), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(24)(1), East => east_2_west(24)(1) , Grant => Signal_grant(24)(1)); + +Arbiter_24_2 : Arbiter + +PORT MAP (Request => Request(119), North => south_2_north(23)(2), West => east_2_west(23)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(24)(2), East => east_2_west(24)(2) , Grant => Signal_grant(24)(2)); + +Arbiter_24_3 : Arbiter + +PORT MAP (Request => Request(107), North => south_2_north(23)(3), West => east_2_west(23)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(24)(3), East => east_2_west(24)(3) , Grant => Signal_grant(24)(3)); + +Arbiter_24_4 : Arbiter + +PORT MAP (Request => Request(95), North => south_2_north(23)(4), West => east_2_west(23)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(24)(4), East => east_2_west(24)(4) , Grant => Signal_grant(24)(4)); + +Arbiter_24_5 : Arbiter + +PORT MAP (Request => Request(83), North => south_2_north(23)(5), West => east_2_west(23)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5), +South => south_2_north(24)(5), East => east_2_west(24)(5) , Grant => Signal_grant(24)(5)); + +Arbiter_24_6 : Arbiter + +PORT MAP (Request => Request(71), North => south_2_north(23)(6), West => east_2_west(23)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6), +South => south_2_north(24)(6), East => east_2_west(24)(6) , Grant => Signal_grant(24)(6)); + +Arbiter_24_7 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(23)(7), West => east_2_west(23)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7), +South => south_2_north(24)(7), East => east_2_west(24)(7) , Grant => Signal_grant(24)(7)); + +Arbiter_24_8 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(23)(8), West => east_2_west(23)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8), +South => south_2_north(24)(8), East => east_2_west(24)(8) , Grant => Signal_grant(24)(8)); + +Arbiter_24_9 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(23)(9), West => east_2_west(23)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9), +South => south_2_north(24)(9), East => east_2_west(24)(9) , Grant => Signal_grant(24)(9)); + +Arbiter_24_10 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(23)(10), West => east_2_west(23)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10), +South => south_2_north(24)(10), East => east_2_west(24)(10) , Grant => Signal_grant(24)(10)); + +Arbiter_24_11 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(23)(11), West => east_2_west(23)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11), +South => south_2_north(24)(11), East => east_2_west(24)(11) , Grant => Signal_grant(24)(11)); + +Arbiter_24_12 : Arbiter + +PORT MAP (Request => Request(168), North => south_2_north(23)(12), West => east_2_west(23)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12), +South => south_2_north(24)(12), East => east_2_west(24)(12) , Grant => Signal_grant(24)(12)); + +Arbiter_24_13 : Arbiter + +PORT MAP (Request => Request(156), North => south_2_north(23)(13), West => east_2_west(23)(12), P => Signal_priority(2), Fifo_full => Fifo_full(13), +South => south_2_north(24)(13), East => east_2_west(24)(13) , Grant => Signal_grant(24)(13)); + +-------------------------- Diagonale n° 25 + + +Arbiter_25_1 : Arbiter + +PORT MAP (Request => Request(144), North => south_2_north(24)(1), West => east_2_west(24)(13), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(25)(1), East => east_2_west(25)(1) , Grant => Signal_grant(25)(1)); + +Arbiter_25_2 : Arbiter + +PORT MAP (Request => Request(132), North => south_2_north(24)(2), West => east_2_west(24)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(25)(2), East => east_2_west(25)(2) , Grant => Signal_grant(25)(2)); + +Arbiter_25_3 : Arbiter + +PORT MAP (Request => Request(120), North => south_2_north(24)(3), West => east_2_west(24)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(25)(3), East => east_2_west(25)(3) , Grant => Signal_grant(25)(3)); + +Arbiter_25_4 : Arbiter + +PORT MAP (Request => Request(108), North => south_2_north(24)(4), West => east_2_west(24)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(25)(4), East => east_2_west(25)(4) , Grant => Signal_grant(25)(4)); + +Arbiter_25_5 : Arbiter + +PORT MAP (Request => Request(96), North => south_2_north(24)(5), West => east_2_west(24)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5), +South => south_2_north(25)(5), East => east_2_west(25)(5) , Grant => Signal_grant(25)(5)); + +Arbiter_25_6 : Arbiter + +PORT MAP (Request => Request(84), North => south_2_north(24)(6), West => east_2_west(24)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6), +South => south_2_north(25)(6), East => east_2_west(25)(6) , Grant => Signal_grant(25)(6)); + +Arbiter_25_7 : Arbiter + +PORT MAP (Request => Request(72), North => south_2_north(24)(7), West => east_2_west(24)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7), +South => south_2_north(25)(7), East => east_2_west(25)(7) , Grant => Signal_grant(25)(7)); + +Arbiter_25_8 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(24)(8), West => east_2_west(24)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8), +South => south_2_north(25)(8), East => east_2_west(25)(8) , Grant => Signal_grant(25)(8)); + +Arbiter_25_9 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(24)(9), West => east_2_west(24)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9), +South => south_2_north(25)(9), East => east_2_west(25)(9) , Grant => Signal_grant(25)(9)); + +Arbiter_25_10 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(24)(10), West => east_2_west(24)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10), +South => south_2_north(25)(10), East => east_2_west(25)(10) , Grant => Signal_grant(25)(10)); + +Arbiter_25_11 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(24)(11), West => east_2_west(24)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11), +South => south_2_north(25)(11), East => east_2_west(25)(11) , Grant => Signal_grant(25)(11)); + +Arbiter_25_12 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(24)(12), West => east_2_west(24)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12), +South => south_2_north(25)(12), East => east_2_west(25)(12) , Grant => Signal_grant(25)(12)); + +Arbiter_25_13 : Arbiter + +PORT MAP (Request => Request(169), North => south_2_north(24)(13), West => east_2_west(24)(12), P => Signal_priority(1), Fifo_full => Fifo_full(13), +South => south_2_north(25)(13), East => east_2_west(25)(13) , Grant => Signal_grant(25)(13)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "1111111111111000000000000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "1111111111111000000000000" => Signal_priority <= "0111111111111100000000000"; + when "0111111111111100000000000" => Signal_priority <= "0011111111111110000000000"; + when "0011111111111110000000000" => Signal_priority <= "0001111111111111000000000"; + when "0001111111111111000000000" => Signal_priority <= "0000111111111111100000000"; + when "0000111111111111100000000" => Signal_priority <= "0000011111111111110000000"; + when "0000011111111111110000000" => Signal_priority <= "0000001111111111111000000"; + when "0000001111111111111000000" => Signal_priority <= "0000000111111111111100000"; + when "0000000111111111111100000" => Signal_priority <= "0000000011111111111110000"; + when "0000000011111111111110000" => Signal_priority <= "0000000001111111111111000"; + when "0000000001111111111111000" => Signal_priority <= "0000000000111111111111100"; + when "0000000000111111111111100" => Signal_priority <= "0000000000011111111111110"; + when "0000000000011111111111110" => Signal_priority <= "0000000000001111111111111"; + when "0000000000001111111111111" => Signal_priority <= "1111111111111000000000000"; + when others => Signal_priority <= "1111111111111000000000000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER14_14.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER14_14.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER14_14.VHD (revision 138) @@ -0,0 +1,2277 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler14_14 is + Port ( Request : in STD_LOGIC_VECTOR (196 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (14 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (14 downto 1); + port_grant : out STD_LOGIC_VECTOR (196 downto 1)); +end Scheduler14_14; + +architecture Behavioral of Scheduler14_14 is +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(27 downto 1) of STD_LOGIC_VECTOR(14 downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (27 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(196 downto 1); + signal priority_rotation_en : std_logic; + signal Grant,req_grant : std_logic_vector(196 downto 1); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet +req_grant<=(request and grant_latch); + priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 16383 else '0'; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + elsif priority_rotation_en = '1' or unsigned(Grant_latch)=0 then + grant_latch <= Grant; + end if; + end if; + end process; + port_grant <= grant_latch; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(15)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(16)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(17)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) or Signal_grant(18)(4); -- Grant(1,4) +Grant(5) <= Signal_grant(5)(5) or Signal_grant(19)(5); -- Grant(1,5) +Grant(6) <= Signal_grant(6)(6) or Signal_grant(20)(6); -- Grant(1,6) +Grant(7) <= Signal_grant(7)(7) or Signal_grant(21)(7); -- Grant(1,7) +Grant(8) <= Signal_grant(8)(8) or Signal_grant(22)(8); -- Grant(1,8) +Grant(9) <= Signal_grant(9)(9) or Signal_grant(23)(9); -- Grant(1,9) +Grant(10) <= Signal_grant(10)(10) or Signal_grant(24)(10); -- Grant(1,10) +Grant(11) <= Signal_grant(11)(11) or Signal_grant(25)(11); -- Grant(1,11) +Grant(12) <= Signal_grant(12)(12) or Signal_grant(26)(12); -- Grant(1,12) +Grant(13) <= Signal_grant(13)(13) or Signal_grant(27)(13); -- Grant(1,13) +Grant(14) <= Signal_grant(14)(14) ; -- Grant(1,14) +Grant(15) <= Signal_grant(2)(1) or Signal_grant(16)(1); -- Grant(2,1) +Grant(16) <= Signal_grant(3)(2) or Signal_grant(17)(2); -- Grant(2,2) +Grant(17) <= Signal_grant(4)(3) or Signal_grant(18)(3); -- Grant(2,3) +Grant(18) <= Signal_grant(5)(4) or Signal_grant(19)(4); -- Grant(2,4) +Grant(19) <= Signal_grant(6)(5) or Signal_grant(20)(5); -- Grant(2,5) +Grant(20) <= Signal_grant(7)(6) or Signal_grant(21)(6); -- Grant(2,6) +Grant(21) <= Signal_grant(8)(7) or Signal_grant(22)(7); -- Grant(2,7) +Grant(22) <= Signal_grant(9)(8) or Signal_grant(23)(8); -- Grant(2,8) +Grant(23) <= Signal_grant(10)(9) or Signal_grant(24)(9); -- Grant(2,9) +Grant(24) <= Signal_grant(11)(10) or Signal_grant(25)(10); -- Grant(2,10) +Grant(25) <= Signal_grant(12)(11) or Signal_grant(26)(11); -- Grant(2,11) +Grant(26) <= Signal_grant(13)(12) or Signal_grant(27)(12); -- Grant(2,12) +Grant(27) <= Signal_grant(14)(13) ; -- Grant(2,13) +Grant(28) <= Signal_grant(1)(14) or Signal_grant(15)(14); -- Grant(2,14) +Grant(29) <= Signal_grant(3)(1) or Signal_grant(17)(1); -- Grant(3,1) +Grant(30) <= Signal_grant(4)(2) or Signal_grant(18)(2); -- Grant(3,2) +Grant(31) <= Signal_grant(5)(3) or Signal_grant(19)(3); -- Grant(3,3) +Grant(32) <= Signal_grant(6)(4) or Signal_grant(20)(4); -- Grant(3,4) +Grant(33) <= Signal_grant(7)(5) or Signal_grant(21)(5); -- Grant(3,5) +Grant(34) <= Signal_grant(8)(6) or Signal_grant(22)(6); -- Grant(3,6) +Grant(35) <= Signal_grant(9)(7) or Signal_grant(23)(7); -- Grant(3,7) +Grant(36) <= Signal_grant(10)(8) or Signal_grant(24)(8); -- Grant(3,8) +Grant(37) <= Signal_grant(11)(9) or Signal_grant(25)(9); -- Grant(3,9) +Grant(38) <= Signal_grant(12)(10) or Signal_grant(26)(10); -- Grant(3,10) +Grant(39) <= Signal_grant(13)(11) or Signal_grant(27)(11); -- Grant(3,11) +Grant(40) <= Signal_grant(14)(12) ; -- Grant(3,12) +Grant(41) <= Signal_grant(1)(13) or Signal_grant(15)(13); -- Grant(3,13) +Grant(42) <= Signal_grant(2)(14) or Signal_grant(16)(14); -- Grant(3,14) +Grant(43) <= Signal_grant(4)(1) or Signal_grant(18)(1); -- Grant(4,1) +Grant(44) <= Signal_grant(5)(2) or Signal_grant(19)(2); -- Grant(4,2) +Grant(45) <= Signal_grant(6)(3) or Signal_grant(20)(3); -- Grant(4,3) +Grant(46) <= Signal_grant(7)(4) or Signal_grant(21)(4); -- Grant(4,4) +Grant(47) <= Signal_grant(8)(5) or Signal_grant(22)(5); -- Grant(4,5) +Grant(48) <= Signal_grant(9)(6) or Signal_grant(23)(6); -- Grant(4,6) +Grant(49) <= Signal_grant(10)(7) or Signal_grant(24)(7); -- Grant(4,7) +Grant(50) <= Signal_grant(11)(8) or Signal_grant(25)(8); -- Grant(4,8) +Grant(51) <= Signal_grant(12)(9) or Signal_grant(26)(9); -- Grant(4,9) +Grant(52) <= Signal_grant(13)(10) or Signal_grant(27)(10); -- Grant(4,10) +Grant(53) <= Signal_grant(14)(11) ; -- Grant(4,11) +Grant(54) <= Signal_grant(1)(12) or Signal_grant(15)(12); -- Grant(4,12) +Grant(55) <= Signal_grant(2)(13) or Signal_grant(16)(13); -- Grant(4,13) +Grant(56) <= Signal_grant(3)(14) or Signal_grant(17)(14); -- Grant(4,14) +Grant(57) <= Signal_grant(5)(1) or Signal_grant(19)(1); -- Grant(5,1) +Grant(58) <= Signal_grant(6)(2) or Signal_grant(20)(2); -- Grant(5,2) +Grant(59) <= Signal_grant(7)(3) or Signal_grant(21)(3); -- Grant(5,3) +Grant(60) <= Signal_grant(8)(4) or Signal_grant(22)(4); -- Grant(5,4) +Grant(61) <= Signal_grant(9)(5) or Signal_grant(23)(5); -- Grant(5,5) +Grant(62) <= Signal_grant(10)(6) or Signal_grant(24)(6); -- Grant(5,6) +Grant(63) <= Signal_grant(11)(7) or Signal_grant(25)(7); -- Grant(5,7) +Grant(64) <= Signal_grant(12)(8) or Signal_grant(26)(8); -- Grant(5,8) +Grant(65) <= Signal_grant(13)(9) or Signal_grant(27)(9); -- Grant(5,9) +Grant(66) <= Signal_grant(14)(10) ; -- Grant(5,10) +Grant(67) <= Signal_grant(1)(11) or Signal_grant(15)(11); -- Grant(5,11) +Grant(68) <= Signal_grant(2)(12) or Signal_grant(16)(12); -- Grant(5,12) +Grant(69) <= Signal_grant(3)(13) or Signal_grant(17)(13); -- Grant(5,13) +Grant(70) <= Signal_grant(4)(14) or Signal_grant(18)(14); -- Grant(5,14) +Grant(71) <= Signal_grant(6)(1) or Signal_grant(20)(1); -- Grant(6,1) +Grant(72) <= Signal_grant(7)(2) or Signal_grant(21)(2); -- Grant(6,2) +Grant(73) <= Signal_grant(8)(3) or Signal_grant(22)(3); -- Grant(6,3) +Grant(74) <= Signal_grant(9)(4) or Signal_grant(23)(4); -- Grant(6,4) +Grant(75) <= Signal_grant(10)(5) or Signal_grant(24)(5); -- Grant(6,5) +Grant(76) <= Signal_grant(11)(6) or Signal_grant(25)(6); -- Grant(6,6) +Grant(77) <= Signal_grant(12)(7) or Signal_grant(26)(7); -- Grant(6,7) +Grant(78) <= Signal_grant(13)(8) or Signal_grant(27)(8); -- Grant(6,8) +Grant(79) <= Signal_grant(14)(9) ; -- Grant(6,9) +Grant(80) <= Signal_grant(1)(10) or Signal_grant(15)(10); -- Grant(6,10) +Grant(81) <= Signal_grant(2)(11) or Signal_grant(16)(11); -- Grant(6,11) +Grant(82) <= Signal_grant(3)(12) or Signal_grant(17)(12); -- Grant(6,12) +Grant(83) <= Signal_grant(4)(13) or Signal_grant(18)(13); -- Grant(6,13) +Grant(84) <= Signal_grant(5)(14) or Signal_grant(19)(14); -- Grant(6,14) +Grant(85) <= Signal_grant(7)(1) or Signal_grant(21)(1); -- Grant(7,1) +Grant(86) <= Signal_grant(8)(2) or Signal_grant(22)(2); -- Grant(7,2) +Grant(87) <= Signal_grant(9)(3) or Signal_grant(23)(3); -- Grant(7,3) +Grant(88) <= Signal_grant(10)(4) or Signal_grant(24)(4); -- Grant(7,4) +Grant(89) <= Signal_grant(11)(5) or Signal_grant(25)(5); -- Grant(7,5) +Grant(90) <= Signal_grant(12)(6) or Signal_grant(26)(6); -- Grant(7,6) +Grant(91) <= Signal_grant(13)(7) or Signal_grant(27)(7); -- Grant(7,7) +Grant(92) <= Signal_grant(14)(8) ; -- Grant(7,8) +Grant(93) <= Signal_grant(1)(9) or Signal_grant(15)(9); -- Grant(7,9) +Grant(94) <= Signal_grant(2)(10) or Signal_grant(16)(10); -- Grant(7,10) +Grant(95) <= Signal_grant(3)(11) or Signal_grant(17)(11); -- Grant(7,11) +Grant(96) <= Signal_grant(4)(12) or Signal_grant(18)(12); -- Grant(7,12) +Grant(97) <= Signal_grant(5)(13) or Signal_grant(19)(13); -- Grant(7,13) +Grant(98) <= Signal_grant(6)(14) or Signal_grant(20)(14); -- Grant(7,14) +Grant(99) <= Signal_grant(8)(1) or Signal_grant(22)(1); -- Grant(8,1) +Grant(100) <= Signal_grant(9)(2) or Signal_grant(23)(2); -- Grant(8,2) +Grant(101) <= Signal_grant(10)(3) or Signal_grant(24)(3); -- Grant(8,3) +Grant(102) <= Signal_grant(11)(4) or Signal_grant(25)(4); -- Grant(8,4) +Grant(103) <= Signal_grant(12)(5) or Signal_grant(26)(5); -- Grant(8,5) +Grant(104) <= Signal_grant(13)(6) or Signal_grant(27)(6); -- Grant(8,6) +Grant(105) <= Signal_grant(14)(7) ; -- Grant(8,7) +Grant(106) <= Signal_grant(1)(8) or Signal_grant(15)(8); -- Grant(8,8) +Grant(107) <= Signal_grant(2)(9) or Signal_grant(16)(9); -- Grant(8,9) +Grant(108) <= Signal_grant(3)(10) or Signal_grant(17)(10); -- Grant(8,10) +Grant(109) <= Signal_grant(4)(11) or Signal_grant(18)(11); -- Grant(8,11) +Grant(110) <= Signal_grant(5)(12) or Signal_grant(19)(12); -- Grant(8,12) +Grant(111) <= Signal_grant(6)(13) or Signal_grant(20)(13); -- Grant(8,13) +Grant(112) <= Signal_grant(7)(14) or Signal_grant(21)(14); -- Grant(8,14) +Grant(113) <= Signal_grant(9)(1) or Signal_grant(23)(1); -- Grant(9,1) +Grant(114) <= Signal_grant(10)(2) or Signal_grant(24)(2); -- Grant(9,2) +Grant(115) <= Signal_grant(11)(3) or Signal_grant(25)(3); -- Grant(9,3) +Grant(116) <= Signal_grant(12)(4) or Signal_grant(26)(4); -- Grant(9,4) +Grant(117) <= Signal_grant(13)(5) or Signal_grant(27)(5); -- Grant(9,5) +Grant(118) <= Signal_grant(14)(6) ; -- Grant(9,6) +Grant(119) <= Signal_grant(1)(7) or Signal_grant(15)(7); -- Grant(9,7) +Grant(120) <= Signal_grant(2)(8) or Signal_grant(16)(8); -- Grant(9,8) +Grant(121) <= Signal_grant(3)(9) or Signal_grant(17)(9); -- Grant(9,9) +Grant(122) <= Signal_grant(4)(10) or Signal_grant(18)(10); -- Grant(9,10) +Grant(123) <= Signal_grant(5)(11) or Signal_grant(19)(11); -- Grant(9,11) +Grant(124) <= Signal_grant(6)(12) or Signal_grant(20)(12); -- Grant(9,12) +Grant(125) <= Signal_grant(7)(13) or Signal_grant(21)(13); -- Grant(9,13) +Grant(126) <= Signal_grant(8)(14) or Signal_grant(22)(14); -- Grant(9,14) +Grant(127) <= Signal_grant(10)(1) or Signal_grant(24)(1); -- Grant(10,1) +Grant(128) <= Signal_grant(11)(2) or Signal_grant(25)(2); -- Grant(10,2) +Grant(129) <= Signal_grant(12)(3) or Signal_grant(26)(3); -- Grant(10,3) +Grant(130) <= Signal_grant(13)(4) or Signal_grant(27)(4); -- Grant(10,4) +Grant(131) <= Signal_grant(14)(5) ; -- Grant(10,5) +Grant(132) <= Signal_grant(1)(6) or Signal_grant(15)(6); -- Grant(10,6) +Grant(133) <= Signal_grant(2)(7) or Signal_grant(16)(7); -- Grant(10,7) +Grant(134) <= Signal_grant(3)(8) or Signal_grant(17)(8); -- Grant(10,8) +Grant(135) <= Signal_grant(4)(9) or Signal_grant(18)(9); -- Grant(10,9) +Grant(136) <= Signal_grant(5)(10) or Signal_grant(19)(10); -- Grant(10,10) +Grant(137) <= Signal_grant(6)(11) or Signal_grant(20)(11); -- Grant(10,11) +Grant(138) <= Signal_grant(7)(12) or Signal_grant(21)(12); -- Grant(10,12) +Grant(139) <= Signal_grant(8)(13) or Signal_grant(22)(13); -- Grant(10,13) +Grant(140) <= Signal_grant(9)(14) or Signal_grant(23)(14); -- Grant(10,14) +Grant(141) <= Signal_grant(11)(1) or Signal_grant(25)(1); -- Grant(11,1) +Grant(142) <= Signal_grant(12)(2) or Signal_grant(26)(2); -- Grant(11,2) +Grant(143) <= Signal_grant(13)(3) or Signal_grant(27)(3); -- Grant(11,3) +Grant(144) <= Signal_grant(14)(4) ; -- Grant(11,4) +Grant(145) <= Signal_grant(1)(5) or Signal_grant(15)(5); -- Grant(11,5) +Grant(146) <= Signal_grant(2)(6) or Signal_grant(16)(6); -- Grant(11,6) +Grant(147) <= Signal_grant(3)(7) or Signal_grant(17)(7); -- Grant(11,7) +Grant(148) <= Signal_grant(4)(8) or Signal_grant(18)(8); -- Grant(11,8) +Grant(149) <= Signal_grant(5)(9) or Signal_grant(19)(9); -- Grant(11,9) +Grant(150) <= Signal_grant(6)(10) or Signal_grant(20)(10); -- Grant(11,10) +Grant(151) <= Signal_grant(7)(11) or Signal_grant(21)(11); -- Grant(11,11) +Grant(152) <= Signal_grant(8)(12) or Signal_grant(22)(12); -- Grant(11,12) +Grant(153) <= Signal_grant(9)(13) or Signal_grant(23)(13); -- Grant(11,13) +Grant(154) <= Signal_grant(10)(14) or Signal_grant(24)(14); -- Grant(11,14) +Grant(155) <= Signal_grant(12)(1) or Signal_grant(26)(1); -- Grant(12,1) +Grant(156) <= Signal_grant(13)(2) or Signal_grant(27)(2); -- Grant(12,2) +Grant(157) <= Signal_grant(14)(3) ; -- Grant(12,3) +Grant(158) <= Signal_grant(1)(4) or Signal_grant(15)(4); -- Grant(12,4) +Grant(159) <= Signal_grant(2)(5) or Signal_grant(16)(5); -- Grant(12,5) +Grant(160) <= Signal_grant(3)(6) or Signal_grant(17)(6); -- Grant(12,6) +Grant(161) <= Signal_grant(4)(7) or Signal_grant(18)(7); -- Grant(12,7) +Grant(162) <= Signal_grant(5)(8) or Signal_grant(19)(8); -- Grant(12,8) +Grant(163) <= Signal_grant(6)(9) or Signal_grant(20)(9); -- Grant(12,9) +Grant(164) <= Signal_grant(7)(10) or Signal_grant(21)(10); -- Grant(12,10) +Grant(165) <= Signal_grant(8)(11) or Signal_grant(22)(11); -- Grant(12,11) +Grant(166) <= Signal_grant(9)(12) or Signal_grant(23)(12); -- Grant(12,12) +Grant(167) <= Signal_grant(10)(13) or Signal_grant(24)(13); -- Grant(12,13) +Grant(168) <= Signal_grant(11)(14) or Signal_grant(25)(14); -- Grant(12,14) +Grant(169) <= Signal_grant(13)(1) or Signal_grant(27)(1); -- Grant(13,1) +Grant(170) <= Signal_grant(14)(2) ; -- Grant(13,2) +Grant(171) <= Signal_grant(1)(3) or Signal_grant(15)(3); -- Grant(13,3) +Grant(172) <= Signal_grant(2)(4) or Signal_grant(16)(4); -- Grant(13,4) +Grant(173) <= Signal_grant(3)(5) or Signal_grant(17)(5); -- Grant(13,5) +Grant(174) <= Signal_grant(4)(6) or Signal_grant(18)(6); -- Grant(13,6) +Grant(175) <= Signal_grant(5)(7) or Signal_grant(19)(7); -- Grant(13,7) +Grant(176) <= Signal_grant(6)(8) or Signal_grant(20)(8); -- Grant(13,8) +Grant(177) <= Signal_grant(7)(9) or Signal_grant(21)(9); -- Grant(13,9) +Grant(178) <= Signal_grant(8)(10) or Signal_grant(22)(10); -- Grant(13,10) +Grant(179) <= Signal_grant(9)(11) or Signal_grant(23)(11); -- Grant(13,11) +Grant(180) <= Signal_grant(10)(12) or Signal_grant(24)(12); -- Grant(13,12) +Grant(181) <= Signal_grant(11)(13) or Signal_grant(25)(13); -- Grant(13,13) +Grant(182) <= Signal_grant(12)(14) or Signal_grant(26)(14); -- Grant(13,14) +Grant(183) <= Signal_grant(14)(1) ; -- Grant(14,1) +Grant(184) <= Signal_grant(1)(2) or Signal_grant(15)(2); -- Grant(14,2) +Grant(185) <= Signal_grant(2)(3) or Signal_grant(16)(3); -- Grant(14,3) +Grant(186) <= Signal_grant(3)(4) or Signal_grant(17)(4); -- Grant(14,4) +Grant(187) <= Signal_grant(4)(5) or Signal_grant(18)(5); -- Grant(14,5) +Grant(188) <= Signal_grant(5)(6) or Signal_grant(19)(6); -- Grant(14,6) +Grant(189) <= Signal_grant(6)(7) or Signal_grant(20)(7); -- Grant(14,7) +Grant(190) <= Signal_grant(7)(8) or Signal_grant(21)(8); -- Grant(14,8) +Grant(191) <= Signal_grant(8)(9) or Signal_grant(22)(9); -- Grant(14,9) +Grant(192) <= Signal_grant(9)(10) or Signal_grant(23)(10); -- Grant(14,10) +Grant(193) <= Signal_grant(10)(11) or Signal_grant(24)(11); -- Grant(14,11) +Grant(194) <= Signal_grant(11)(12) or Signal_grant(25)(12); -- Grant(14,12) +Grant(195) <= Signal_grant(12)(13) or Signal_grant(26)(13); -- Grant(14,13) +Grant(196) <= Signal_grant(13)(14) or Signal_grant(27)(14); -- Grant(14,14) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(184), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(171), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(158), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +Arbiter_1_5 : Arbiter + +PORT MAP (Request => Request(145), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(5), +South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); + +Arbiter_1_6 : Arbiter + +PORT MAP (Request => Request(132), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(6), +South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); + +Arbiter_1_7 : Arbiter + +PORT MAP (Request => Request(119), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(7), +South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); + +Arbiter_1_8 : Arbiter + +PORT MAP (Request => Request(106), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(8), +South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); + +Arbiter_1_9 : Arbiter + +PORT MAP (Request => Request(93), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(9), +South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); + +Arbiter_1_10 : Arbiter + +PORT MAP (Request => Request(80), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(10), +South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); + +Arbiter_1_11 : Arbiter + +PORT MAP (Request => Request(67), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(11), +South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); + +Arbiter_1_12 : Arbiter + +PORT MAP (Request => Request(54), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(12), +South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); + +Arbiter_1_13 : Arbiter + +PORT MAP (Request => Request(41), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(13), +South => south_2_north(1)(13), East => east_2_west(1)(13) , Grant => Signal_grant(1)(13)); + +Arbiter_1_14 : Arbiter + +PORT MAP (Request => Request(28), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(14), +South => south_2_north(1)(14), East => east_2_west(1)(14) , Grant => Signal_grant(1)(14)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(1)(1), West => east_2_west(1)(14), P => Signal_priority(26), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(26), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(185), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(26), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(172), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(26), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +Arbiter_2_5 : Arbiter + +PORT MAP (Request => Request(159), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(26), Fifo_full => Fifo_full(5), +South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); + +Arbiter_2_6 : Arbiter + +PORT MAP (Request => Request(146), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(26), Fifo_full => Fifo_full(6), +South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); + +Arbiter_2_7 : Arbiter + +PORT MAP (Request => Request(133), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(26), Fifo_full => Fifo_full(7), +South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); + +Arbiter_2_8 : Arbiter + +PORT MAP (Request => Request(120), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(26), Fifo_full => Fifo_full(8), +South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); + +Arbiter_2_9 : Arbiter + +PORT MAP (Request => Request(107), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(26), Fifo_full => Fifo_full(9), +South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); + +Arbiter_2_10 : Arbiter + +PORT MAP (Request => Request(94), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(26), Fifo_full => Fifo_full(10), +South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); + +Arbiter_2_11 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(26), Fifo_full => Fifo_full(11), +South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); + +Arbiter_2_12 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(26), Fifo_full => Fifo_full(12), +South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); + +Arbiter_2_13 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(1)(13), West => east_2_west(1)(12), P => Signal_priority(26), Fifo_full => Fifo_full(13), +South => south_2_north(2)(13), East => east_2_west(2)(13) , Grant => Signal_grant(2)(13)); + +Arbiter_2_14 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(1)(14), West => east_2_west(1)(13), P => Signal_priority(26), Fifo_full => Fifo_full(14), +South => south_2_north(2)(14), East => east_2_west(2)(14) , Grant => Signal_grant(2)(14)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(2)(1), West => east_2_west(2)(14), P => Signal_priority(25), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(25), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(25), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(186), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(25), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +Arbiter_3_5 : Arbiter + +PORT MAP (Request => Request(173), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(25), Fifo_full => Fifo_full(5), +South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); + +Arbiter_3_6 : Arbiter + +PORT MAP (Request => Request(160), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(25), Fifo_full => Fifo_full(6), +South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); + +Arbiter_3_7 : Arbiter + +PORT MAP (Request => Request(147), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(25), Fifo_full => Fifo_full(7), +South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); + +Arbiter_3_8 : Arbiter + +PORT MAP (Request => Request(134), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(25), Fifo_full => Fifo_full(8), +South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); + +Arbiter_3_9 : Arbiter + +PORT MAP (Request => Request(121), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(25), Fifo_full => Fifo_full(9), +South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); + +Arbiter_3_10 : Arbiter + +PORT MAP (Request => Request(108), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(25), Fifo_full => Fifo_full(10), +South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); + +Arbiter_3_11 : Arbiter + +PORT MAP (Request => Request(95), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(25), Fifo_full => Fifo_full(11), +South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); + +Arbiter_3_12 : Arbiter + +PORT MAP (Request => Request(82), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(25), Fifo_full => Fifo_full(12), +South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); + +Arbiter_3_13 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(2)(13), West => east_2_west(2)(12), P => Signal_priority(25), Fifo_full => Fifo_full(13), +South => south_2_north(3)(13), East => east_2_west(3)(13) , Grant => Signal_grant(3)(13)); + +Arbiter_3_14 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(2)(14), West => east_2_west(2)(13), P => Signal_priority(25), Fifo_full => Fifo_full(14), +South => south_2_north(3)(14), East => east_2_west(3)(14) , Grant => Signal_grant(3)(14)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(3)(1), West => east_2_west(3)(14), P => Signal_priority(24), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(24), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(24), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(24), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +Arbiter_4_5 : Arbiter + +PORT MAP (Request => Request(187), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(24), Fifo_full => Fifo_full(5), +South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); + +Arbiter_4_6 : Arbiter + +PORT MAP (Request => Request(174), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(24), Fifo_full => Fifo_full(6), +South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); + +Arbiter_4_7 : Arbiter + +PORT MAP (Request => Request(161), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(24), Fifo_full => Fifo_full(7), +South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); + +Arbiter_4_8 : Arbiter + +PORT MAP (Request => Request(148), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(24), Fifo_full => Fifo_full(8), +South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); + +Arbiter_4_9 : Arbiter + +PORT MAP (Request => Request(135), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(24), Fifo_full => Fifo_full(9), +South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); + +Arbiter_4_10 : Arbiter + +PORT MAP (Request => Request(122), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(24), Fifo_full => Fifo_full(10), +South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); + +Arbiter_4_11 : Arbiter + +PORT MAP (Request => Request(109), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(24), Fifo_full => Fifo_full(11), +South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); + +Arbiter_4_12 : Arbiter + +PORT MAP (Request => Request(96), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(24), Fifo_full => Fifo_full(12), +South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); + +Arbiter_4_13 : Arbiter + +PORT MAP (Request => Request(83), North => south_2_north(3)(13), West => east_2_west(3)(12), P => Signal_priority(24), Fifo_full => Fifo_full(13), +South => south_2_north(4)(13), East => east_2_west(4)(13) , Grant => Signal_grant(4)(13)); + +Arbiter_4_14 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(3)(14), West => east_2_west(3)(13), P => Signal_priority(24), Fifo_full => Fifo_full(14), +South => south_2_north(4)(14), East => east_2_west(4)(14) , Grant => Signal_grant(4)(14)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(4)(1), West => east_2_west(4)(14), P => Signal_priority(23), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(23), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(23), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(23), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +Arbiter_5_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(23), Fifo_full => Fifo_full(5), +South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); + +Arbiter_5_6 : Arbiter + +PORT MAP (Request => Request(188), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(23), Fifo_full => Fifo_full(6), +South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); + +Arbiter_5_7 : Arbiter + +PORT MAP (Request => Request(175), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(23), Fifo_full => Fifo_full(7), +South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); + +Arbiter_5_8 : Arbiter + +PORT MAP (Request => Request(162), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(23), Fifo_full => Fifo_full(8), +South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); + +Arbiter_5_9 : Arbiter + +PORT MAP (Request => Request(149), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(23), Fifo_full => Fifo_full(9), +South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); + +Arbiter_5_10 : Arbiter + +PORT MAP (Request => Request(136), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(23), Fifo_full => Fifo_full(10), +South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); + +Arbiter_5_11 : Arbiter + +PORT MAP (Request => Request(123), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(23), Fifo_full => Fifo_full(11), +South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); + +Arbiter_5_12 : Arbiter + +PORT MAP (Request => Request(110), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(23), Fifo_full => Fifo_full(12), +South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); + +Arbiter_5_13 : Arbiter + +PORT MAP (Request => Request(97), North => south_2_north(4)(13), West => east_2_west(4)(12), P => Signal_priority(23), Fifo_full => Fifo_full(13), +South => south_2_north(5)(13), East => east_2_west(5)(13) , Grant => Signal_grant(5)(13)); + +Arbiter_5_14 : Arbiter + +PORT MAP (Request => Request(84), North => south_2_north(4)(14), West => east_2_west(4)(13), P => Signal_priority(23), Fifo_full => Fifo_full(14), +South => south_2_north(5)(14), East => east_2_west(5)(14) , Grant => Signal_grant(5)(14)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(71), North => south_2_north(5)(1), West => east_2_west(5)(14), P => Signal_priority(22), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +Arbiter_6_5 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5), +South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); + +Arbiter_6_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6), +South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); + +Arbiter_6_7 : Arbiter + +PORT MAP (Request => Request(189), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7), +South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); + +Arbiter_6_8 : Arbiter + +PORT MAP (Request => Request(176), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8), +South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); + +Arbiter_6_9 : Arbiter + +PORT MAP (Request => Request(163), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9), +South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); + +Arbiter_6_10 : Arbiter + +PORT MAP (Request => Request(150), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10), +South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); + +Arbiter_6_11 : Arbiter + +PORT MAP (Request => Request(137), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11), +South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); + +Arbiter_6_12 : Arbiter + +PORT MAP (Request => Request(124), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12), +South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); + +Arbiter_6_13 : Arbiter + +PORT MAP (Request => Request(111), North => south_2_north(5)(13), West => east_2_west(5)(12), P => Signal_priority(22), Fifo_full => Fifo_full(13), +South => south_2_north(6)(13), East => east_2_west(6)(13) , Grant => Signal_grant(6)(13)); + +Arbiter_6_14 : Arbiter + +PORT MAP (Request => Request(98), North => south_2_north(5)(14), West => east_2_west(5)(13), P => Signal_priority(22), Fifo_full => Fifo_full(14), +South => south_2_north(6)(14), East => east_2_west(6)(14) , Grant => Signal_grant(6)(14)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(85), North => south_2_north(6)(1), West => east_2_west(6)(14), P => Signal_priority(21), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(72), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + +Arbiter_7_5 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5), +South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); + +Arbiter_7_6 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6), +South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); + +Arbiter_7_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7), +South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); + +Arbiter_7_8 : Arbiter + +PORT MAP (Request => Request(190), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8), +South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); + +Arbiter_7_9 : Arbiter + +PORT MAP (Request => Request(177), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9), +South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); + +Arbiter_7_10 : Arbiter + +PORT MAP (Request => Request(164), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10), +South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); + +Arbiter_7_11 : Arbiter + +PORT MAP (Request => Request(151), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11), +South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); + +Arbiter_7_12 : Arbiter + +PORT MAP (Request => Request(138), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12), +South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); + +Arbiter_7_13 : Arbiter + +PORT MAP (Request => Request(125), North => south_2_north(6)(13), West => east_2_west(6)(12), P => Signal_priority(21), Fifo_full => Fifo_full(13), +South => south_2_north(7)(13), East => east_2_west(7)(13) , Grant => Signal_grant(7)(13)); + +Arbiter_7_14 : Arbiter + +PORT MAP (Request => Request(112), North => south_2_north(6)(14), West => east_2_west(6)(13), P => Signal_priority(21), Fifo_full => Fifo_full(14), +South => south_2_north(7)(14), East => east_2_west(7)(14) , Grant => Signal_grant(7)(14)); + +-------------------------- Diagonale n° 8 + + +Arbiter_8_1 : Arbiter + +PORT MAP (Request => Request(99), North => south_2_north(7)(1), West => east_2_west(7)(14), P => Signal_priority(20), Fifo_full => Fifo_full(1), +South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); + +Arbiter_8_2 : Arbiter + +PORT MAP (Request => Request(86), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2), +South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); + +Arbiter_8_3 : Arbiter + +PORT MAP (Request => Request(73), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3), +South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); + +Arbiter_8_4 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4), +South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); + +Arbiter_8_5 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5), +South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); + +Arbiter_8_6 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6), +South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); + +Arbiter_8_7 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7), +South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); + +Arbiter_8_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8), +South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); + +Arbiter_8_9 : Arbiter + +PORT MAP (Request => Request(191), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9), +South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); + +Arbiter_8_10 : Arbiter + +PORT MAP (Request => Request(178), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10), +South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); + +Arbiter_8_11 : Arbiter + +PORT MAP (Request => Request(165), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11), +South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); + +Arbiter_8_12 : Arbiter + +PORT MAP (Request => Request(152), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12), +South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); + +Arbiter_8_13 : Arbiter + +PORT MAP (Request => Request(139), North => south_2_north(7)(13), West => east_2_west(7)(12), P => Signal_priority(20), Fifo_full => Fifo_full(13), +South => south_2_north(8)(13), East => east_2_west(8)(13) , Grant => Signal_grant(8)(13)); + +Arbiter_8_14 : Arbiter + +PORT MAP (Request => Request(126), North => south_2_north(7)(14), West => east_2_west(7)(13), P => Signal_priority(20), Fifo_full => Fifo_full(14), +South => south_2_north(8)(14), East => east_2_west(8)(14) , Grant => Signal_grant(8)(14)); + +-------------------------- Diagonale n° 9 + + +Arbiter_9_1 : Arbiter + +PORT MAP (Request => Request(113), North => south_2_north(8)(1), West => east_2_west(8)(14), P => Signal_priority(19), Fifo_full => Fifo_full(1), +South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); + +Arbiter_9_2 : Arbiter + +PORT MAP (Request => Request(100), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2), +South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); + +Arbiter_9_3 : Arbiter + +PORT MAP (Request => Request(87), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3), +South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); + +Arbiter_9_4 : Arbiter + +PORT MAP (Request => Request(74), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4), +South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); + +Arbiter_9_5 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5), +South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); + +Arbiter_9_6 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6), +South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); + +Arbiter_9_7 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7), +South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); + +Arbiter_9_8 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8), +South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); + +Arbiter_9_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9), +South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); + +Arbiter_9_10 : Arbiter + +PORT MAP (Request => Request(192), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10), +South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); + +Arbiter_9_11 : Arbiter + +PORT MAP (Request => Request(179), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11), +South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); + +Arbiter_9_12 : Arbiter + +PORT MAP (Request => Request(166), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12), +South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); + +Arbiter_9_13 : Arbiter + +PORT MAP (Request => Request(153), North => south_2_north(8)(13), West => east_2_west(8)(12), P => Signal_priority(19), Fifo_full => Fifo_full(13), +South => south_2_north(9)(13), East => east_2_west(9)(13) , Grant => Signal_grant(9)(13)); + +Arbiter_9_14 : Arbiter + +PORT MAP (Request => Request(140), North => south_2_north(8)(14), West => east_2_west(8)(13), P => Signal_priority(19), Fifo_full => Fifo_full(14), +South => south_2_north(9)(14), East => east_2_west(9)(14) , Grant => Signal_grant(9)(14)); + +-------------------------- Diagonale n° 10 + + +Arbiter_10_1 : Arbiter + +PORT MAP (Request => Request(127), North => south_2_north(9)(1), West => east_2_west(9)(14), P => Signal_priority(18), Fifo_full => Fifo_full(1), +South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); + +Arbiter_10_2 : Arbiter + +PORT MAP (Request => Request(114), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2), +South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); + +Arbiter_10_3 : Arbiter + +PORT MAP (Request => Request(101), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3), +South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); + +Arbiter_10_4 : Arbiter + +PORT MAP (Request => Request(88), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4), +South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); + +Arbiter_10_5 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5), +South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); + +Arbiter_10_6 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6), +South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); + +Arbiter_10_7 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7), +South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); + +Arbiter_10_8 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8), +South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); + +Arbiter_10_9 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9), +South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); + +Arbiter_10_10 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10), +South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); + +Arbiter_10_11 : Arbiter + +PORT MAP (Request => Request(193), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11), +South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); + +Arbiter_10_12 : Arbiter + +PORT MAP (Request => Request(180), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12), +South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); + +Arbiter_10_13 : Arbiter + +PORT MAP (Request => Request(167), North => south_2_north(9)(13), West => east_2_west(9)(12), P => Signal_priority(18), Fifo_full => Fifo_full(13), +South => south_2_north(10)(13), East => east_2_west(10)(13) , Grant => Signal_grant(10)(13)); + +Arbiter_10_14 : Arbiter + +PORT MAP (Request => Request(154), North => south_2_north(9)(14), West => east_2_west(9)(13), P => Signal_priority(18), Fifo_full => Fifo_full(14), +South => south_2_north(10)(14), East => east_2_west(10)(14) , Grant => Signal_grant(10)(14)); + +-------------------------- Diagonale n° 11 + + +Arbiter_11_1 : Arbiter + +PORT MAP (Request => Request(141), North => south_2_north(10)(1), West => east_2_west(10)(14), P => Signal_priority(17), Fifo_full => Fifo_full(1), +South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); + +Arbiter_11_2 : Arbiter + +PORT MAP (Request => Request(128), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2), +South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); + +Arbiter_11_3 : Arbiter + +PORT MAP (Request => Request(115), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3), +South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); + +Arbiter_11_4 : Arbiter + +PORT MAP (Request => Request(102), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4), +South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); + +Arbiter_11_5 : Arbiter + +PORT MAP (Request => Request(89), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5), +South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); + +Arbiter_11_6 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6), +South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); + +Arbiter_11_7 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7), +South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); + +Arbiter_11_8 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8), +South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); + +Arbiter_11_9 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9), +South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); + +Arbiter_11_10 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10), +South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); + +Arbiter_11_11 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11), +South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); + +Arbiter_11_12 : Arbiter + +PORT MAP (Request => Request(194), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12), +South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); + +Arbiter_11_13 : Arbiter + +PORT MAP (Request => Request(181), North => south_2_north(10)(13), West => east_2_west(10)(12), P => Signal_priority(17), Fifo_full => Fifo_full(13), +South => south_2_north(11)(13), East => east_2_west(11)(13) , Grant => Signal_grant(11)(13)); + +Arbiter_11_14 : Arbiter + +PORT MAP (Request => Request(168), North => south_2_north(10)(14), West => east_2_west(10)(13), P => Signal_priority(17), Fifo_full => Fifo_full(14), +South => south_2_north(11)(14), East => east_2_west(11)(14) , Grant => Signal_grant(11)(14)); + +-------------------------- Diagonale n° 12 + + +Arbiter_12_1 : Arbiter + +PORT MAP (Request => Request(155), North => south_2_north(11)(1), West => east_2_west(11)(14), P => Signal_priority(16), Fifo_full => Fifo_full(1), +South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); + +Arbiter_12_2 : Arbiter + +PORT MAP (Request => Request(142), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2), +South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); + +Arbiter_12_3 : Arbiter + +PORT MAP (Request => Request(129), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3), +South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); + +Arbiter_12_4 : Arbiter + +PORT MAP (Request => Request(116), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4), +South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); + +Arbiter_12_5 : Arbiter + +PORT MAP (Request => Request(103), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5), +South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); + +Arbiter_12_6 : Arbiter + +PORT MAP (Request => Request(90), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6), +South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); + +Arbiter_12_7 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7), +South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); + +Arbiter_12_8 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8), +South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); + +Arbiter_12_9 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9), +South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); + +Arbiter_12_10 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10), +South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); + +Arbiter_12_11 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11), +South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); + +Arbiter_12_12 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12), +South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); + +Arbiter_12_13 : Arbiter + +PORT MAP (Request => Request(195), North => south_2_north(11)(13), West => east_2_west(11)(12), P => Signal_priority(16), Fifo_full => Fifo_full(13), +South => south_2_north(12)(13), East => east_2_west(12)(13) , Grant => Signal_grant(12)(13)); + +Arbiter_12_14 : Arbiter + +PORT MAP (Request => Request(182), North => south_2_north(11)(14), West => east_2_west(11)(13), P => Signal_priority(16), Fifo_full => Fifo_full(14), +South => south_2_north(12)(14), East => east_2_west(12)(14) , Grant => Signal_grant(12)(14)); + +-------------------------- Diagonale n° 13 + + +Arbiter_13_1 : Arbiter + +PORT MAP (Request => Request(169), North => south_2_north(12)(1), West => east_2_west(12)(14), P => Signal_priority(15), Fifo_full => Fifo_full(1), +South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); + +Arbiter_13_2 : Arbiter + +PORT MAP (Request => Request(156), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2), +South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); + +Arbiter_13_3 : Arbiter + +PORT MAP (Request => Request(143), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3), +South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); + +Arbiter_13_4 : Arbiter + +PORT MAP (Request => Request(130), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4), +South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); + +Arbiter_13_5 : Arbiter + +PORT MAP (Request => Request(117), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5), +South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); + +Arbiter_13_6 : Arbiter + +PORT MAP (Request => Request(104), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6), +South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); + +Arbiter_13_7 : Arbiter + +PORT MAP (Request => Request(91), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7), +South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); + +Arbiter_13_8 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8), +South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); + +Arbiter_13_9 : Arbiter + +PORT MAP (Request => Request(65), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9), +South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); + +Arbiter_13_10 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10), +South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); + +Arbiter_13_11 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11), +South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); + +Arbiter_13_12 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12), +South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); + +Arbiter_13_13 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(12)(13), West => east_2_west(12)(12), P => Signal_priority(15), Fifo_full => Fifo_full(13), +South => south_2_north(13)(13), East => east_2_west(13)(13) , Grant => Signal_grant(13)(13)); + +Arbiter_13_14 : Arbiter + +PORT MAP (Request => Request(196), North => south_2_north(12)(14), West => east_2_west(12)(13), P => Signal_priority(15), Fifo_full => Fifo_full(14), +South => south_2_north(13)(14), East => east_2_west(13)(14) , Grant => Signal_grant(13)(14)); + +-------------------------- Diagonale n° 14 + + +Arbiter_14_1 : Arbiter + +PORT MAP (Request => Request(183), North => south_2_north(13)(1), West => east_2_west(13)(14), P => Signal_priority(14), Fifo_full => Fifo_full(1), +South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); + +Arbiter_14_2 : Arbiter + +PORT MAP (Request => Request(170), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2), +South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); + +Arbiter_14_3 : Arbiter + +PORT MAP (Request => Request(157), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3), +South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); + +Arbiter_14_4 : Arbiter + +PORT MAP (Request => Request(144), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4), +South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); + +Arbiter_14_5 : Arbiter + +PORT MAP (Request => Request(131), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5), +South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); + +Arbiter_14_6 : Arbiter + +PORT MAP (Request => Request(118), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6), +South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); + +Arbiter_14_7 : Arbiter + +PORT MAP (Request => Request(105), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7), +South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); + +Arbiter_14_8 : Arbiter + +PORT MAP (Request => Request(92), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8), +South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); + +Arbiter_14_9 : Arbiter + +PORT MAP (Request => Request(79), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9), +South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); + +Arbiter_14_10 : Arbiter + +PORT MAP (Request => Request(66), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10), +South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); + +Arbiter_14_11 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11), +South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); + +Arbiter_14_12 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12), +South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); + +Arbiter_14_13 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(13)(13), West => east_2_west(13)(12), P => Signal_priority(14), Fifo_full => Fifo_full(13), +South => south_2_north(14)(13), East => east_2_west(14)(13) , Grant => Signal_grant(14)(13)); + +Arbiter_14_14 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(13)(14), West => east_2_west(13)(13), P => Signal_priority(14), Fifo_full => Fifo_full(14), +South => south_2_north(14)(14), East => east_2_west(14)(14) , Grant => Signal_grant(14)(14)); + +-------------------------- Diagonale n° 15 + + +Arbiter_15_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(14)(1), West => east_2_west(14)(14), P => Signal_priority(13), Fifo_full => Fifo_full(1), +South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); + +Arbiter_15_2 : Arbiter + +PORT MAP (Request => Request(184), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2), +South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); + +Arbiter_15_3 : Arbiter + +PORT MAP (Request => Request(171), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3), +South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); + +Arbiter_15_4 : Arbiter + +PORT MAP (Request => Request(158), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4), +South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); + +Arbiter_15_5 : Arbiter + +PORT MAP (Request => Request(145), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5), +South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); + +Arbiter_15_6 : Arbiter + +PORT MAP (Request => Request(132), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6), +South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); + +Arbiter_15_7 : Arbiter + +PORT MAP (Request => Request(119), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7), +South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); + +Arbiter_15_8 : Arbiter + +PORT MAP (Request => Request(106), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8), +South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); + +Arbiter_15_9 : Arbiter + +PORT MAP (Request => Request(93), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9), +South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); + +Arbiter_15_10 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10), +South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); + +Arbiter_15_11 : Arbiter + +PORT MAP (Request => Request(67), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11), +South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); + +Arbiter_15_12 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12), +South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); + +Arbiter_15_13 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(14)(13), West => east_2_west(14)(12), P => Signal_priority(13), Fifo_full => Fifo_full(13), +South => south_2_north(15)(13), East => east_2_west(15)(13) , Grant => Signal_grant(15)(13)); + +Arbiter_15_14 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(14)(14), West => east_2_west(14)(13), P => Signal_priority(13), Fifo_full => Fifo_full(14), +South => south_2_north(15)(14), East => east_2_west(15)(14) , Grant => Signal_grant(15)(14)); + +-------------------------- Diagonale n° 16 + + +Arbiter_16_1 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(15)(1), West => east_2_west(15)(14), P => Signal_priority(12), Fifo_full => Fifo_full(1), +South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); + +Arbiter_16_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2), +South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); + +Arbiter_16_3 : Arbiter + +PORT MAP (Request => Request(185), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3), +South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); + +Arbiter_16_4 : Arbiter + +PORT MAP (Request => Request(172), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4), +South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); + +Arbiter_16_5 : Arbiter + +PORT MAP (Request => Request(159), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5), +South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); + +Arbiter_16_6 : Arbiter + +PORT MAP (Request => Request(146), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6), +South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); + +Arbiter_16_7 : Arbiter + +PORT MAP (Request => Request(133), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7), +South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); + +Arbiter_16_8 : Arbiter + +PORT MAP (Request => Request(120), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8), +South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); + +Arbiter_16_9 : Arbiter + +PORT MAP (Request => Request(107), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9), +South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); + +Arbiter_16_10 : Arbiter + +PORT MAP (Request => Request(94), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10), +South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); + +Arbiter_16_11 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11), +South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); + +Arbiter_16_12 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12), +South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); + +Arbiter_16_13 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(15)(13), West => east_2_west(15)(12), P => Signal_priority(12), Fifo_full => Fifo_full(13), +South => south_2_north(16)(13), East => east_2_west(16)(13) , Grant => Signal_grant(16)(13)); + +Arbiter_16_14 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(15)(14), West => east_2_west(15)(13), P => Signal_priority(12), Fifo_full => Fifo_full(14), +South => south_2_north(16)(14), East => east_2_west(16)(14) , Grant => Signal_grant(16)(14)); + +-------------------------- Diagonale n° 17 + + +Arbiter_17_1 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(16)(1), West => east_2_west(16)(14), P => Signal_priority(11), Fifo_full => Fifo_full(1), +South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); + +Arbiter_17_2 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2), +South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); + +Arbiter_17_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3), +South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); + +Arbiter_17_4 : Arbiter + +PORT MAP (Request => Request(186), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4), +South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); + +Arbiter_17_5 : Arbiter + +PORT MAP (Request => Request(173), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5), +South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); + +Arbiter_17_6 : Arbiter + +PORT MAP (Request => Request(160), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6), +South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); + +Arbiter_17_7 : Arbiter + +PORT MAP (Request => Request(147), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7), +South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); + +Arbiter_17_8 : Arbiter + +PORT MAP (Request => Request(134), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8), +South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); + +Arbiter_17_9 : Arbiter + +PORT MAP (Request => Request(121), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9), +South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); + +Arbiter_17_10 : Arbiter + +PORT MAP (Request => Request(108), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10), +South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); + +Arbiter_17_11 : Arbiter + +PORT MAP (Request => Request(95), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11), +South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); + +Arbiter_17_12 : Arbiter + +PORT MAP (Request => Request(82), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12), +South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); + +Arbiter_17_13 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(16)(13), West => east_2_west(16)(12), P => Signal_priority(11), Fifo_full => Fifo_full(13), +South => south_2_north(17)(13), East => east_2_west(17)(13) , Grant => Signal_grant(17)(13)); + +Arbiter_17_14 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(16)(14), West => east_2_west(16)(13), P => Signal_priority(11), Fifo_full => Fifo_full(14), +South => south_2_north(17)(14), East => east_2_west(17)(14) , Grant => Signal_grant(17)(14)); + +-------------------------- Diagonale n° 18 + + +Arbiter_18_1 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(17)(1), West => east_2_west(17)(14), P => Signal_priority(10), Fifo_full => Fifo_full(1), +South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); + +Arbiter_18_2 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2), +South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); + +Arbiter_18_3 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3), +South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); + +Arbiter_18_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4), +South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); + +Arbiter_18_5 : Arbiter + +PORT MAP (Request => Request(187), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5), +South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); + +Arbiter_18_6 : Arbiter + +PORT MAP (Request => Request(174), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6), +South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); + +Arbiter_18_7 : Arbiter + +PORT MAP (Request => Request(161), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7), +South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); + +Arbiter_18_8 : Arbiter + +PORT MAP (Request => Request(148), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8), +South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); + +Arbiter_18_9 : Arbiter + +PORT MAP (Request => Request(135), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9), +South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); + +Arbiter_18_10 : Arbiter + +PORT MAP (Request => Request(122), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10), +South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); + +Arbiter_18_11 : Arbiter + +PORT MAP (Request => Request(109), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11), +South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); + +Arbiter_18_12 : Arbiter + +PORT MAP (Request => Request(96), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12), +South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); + +Arbiter_18_13 : Arbiter + +PORT MAP (Request => Request(83), North => south_2_north(17)(13), West => east_2_west(17)(12), P => Signal_priority(10), Fifo_full => Fifo_full(13), +South => south_2_north(18)(13), East => east_2_west(18)(13) , Grant => Signal_grant(18)(13)); + +Arbiter_18_14 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(17)(14), West => east_2_west(17)(13), P => Signal_priority(10), Fifo_full => Fifo_full(14), +South => south_2_north(18)(14), East => east_2_west(18)(14) , Grant => Signal_grant(18)(14)); + +-------------------------- Diagonale n° 19 + + +Arbiter_19_1 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(18)(1), West => east_2_west(18)(14), P => Signal_priority(9), Fifo_full => Fifo_full(1), +South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); + +Arbiter_19_2 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2), +South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); + +Arbiter_19_3 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3), +South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); + +Arbiter_19_4 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4), +South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); + +Arbiter_19_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5), +South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); + +Arbiter_19_6 : Arbiter + +PORT MAP (Request => Request(188), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6), +South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); + +Arbiter_19_7 : Arbiter + +PORT MAP (Request => Request(175), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7), +South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); + +Arbiter_19_8 : Arbiter + +PORT MAP (Request => Request(162), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8), +South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); + +Arbiter_19_9 : Arbiter + +PORT MAP (Request => Request(149), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9), +South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); + +Arbiter_19_10 : Arbiter + +PORT MAP (Request => Request(136), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10), +South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); + +Arbiter_19_11 : Arbiter + +PORT MAP (Request => Request(123), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11), +South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); + +Arbiter_19_12 : Arbiter + +PORT MAP (Request => Request(110), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12), +South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); + +Arbiter_19_13 : Arbiter + +PORT MAP (Request => Request(97), North => south_2_north(18)(13), West => east_2_west(18)(12), P => Signal_priority(9), Fifo_full => Fifo_full(13), +South => south_2_north(19)(13), East => east_2_west(19)(13) , Grant => Signal_grant(19)(13)); + +Arbiter_19_14 : Arbiter + +PORT MAP (Request => Request(84), North => south_2_north(18)(14), West => east_2_west(18)(13), P => Signal_priority(9), Fifo_full => Fifo_full(14), +South => south_2_north(19)(14), East => east_2_west(19)(14) , Grant => Signal_grant(19)(14)); + +-------------------------- Diagonale n° 20 + + +Arbiter_20_1 : Arbiter + +PORT MAP (Request => Request(71), North => south_2_north(19)(1), West => east_2_west(19)(14), P => Signal_priority(8), Fifo_full => Fifo_full(1), +South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); + +Arbiter_20_2 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2), +South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); + +Arbiter_20_3 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3), +South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); + +Arbiter_20_4 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4), +South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); + +Arbiter_20_5 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5), +South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); + +Arbiter_20_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6), +South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); + +Arbiter_20_7 : Arbiter + +PORT MAP (Request => Request(189), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7), +South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); + +Arbiter_20_8 : Arbiter + +PORT MAP (Request => Request(176), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8), +South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); + +Arbiter_20_9 : Arbiter + +PORT MAP (Request => Request(163), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9), +South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); + +Arbiter_20_10 : Arbiter + +PORT MAP (Request => Request(150), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10), +South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); + +Arbiter_20_11 : Arbiter + +PORT MAP (Request => Request(137), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11), +South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); + +Arbiter_20_12 : Arbiter + +PORT MAP (Request => Request(124), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12), +South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); + +Arbiter_20_13 : Arbiter + +PORT MAP (Request => Request(111), North => south_2_north(19)(13), West => east_2_west(19)(12), P => Signal_priority(8), Fifo_full => Fifo_full(13), +South => south_2_north(20)(13), East => east_2_west(20)(13) , Grant => Signal_grant(20)(13)); + +Arbiter_20_14 : Arbiter + +PORT MAP (Request => Request(98), North => south_2_north(19)(14), West => east_2_west(19)(13), P => Signal_priority(8), Fifo_full => Fifo_full(14), +South => south_2_north(20)(14), East => east_2_west(20)(14) , Grant => Signal_grant(20)(14)); + +-------------------------- Diagonale n° 21 + + +Arbiter_21_1 : Arbiter + +PORT MAP (Request => Request(85), North => south_2_north(20)(1), West => east_2_west(20)(14), P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); + +Arbiter_21_2 : Arbiter + +PORT MAP (Request => Request(72), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); + +Arbiter_21_3 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); + +Arbiter_21_4 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); + +Arbiter_21_5 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5), +South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); + +Arbiter_21_6 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6), +South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); + +Arbiter_21_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7), +South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); + +Arbiter_21_8 : Arbiter + +PORT MAP (Request => Request(190), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8), +South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); + +Arbiter_21_9 : Arbiter + +PORT MAP (Request => Request(177), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9), +South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); + +Arbiter_21_10 : Arbiter + +PORT MAP (Request => Request(164), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10), +South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); + +Arbiter_21_11 : Arbiter + +PORT MAP (Request => Request(151), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11), +South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); + +Arbiter_21_12 : Arbiter + +PORT MAP (Request => Request(138), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12), +South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); + +Arbiter_21_13 : Arbiter + +PORT MAP (Request => Request(125), North => south_2_north(20)(13), West => east_2_west(20)(12), P => Signal_priority(7), Fifo_full => Fifo_full(13), +South => south_2_north(21)(13), East => east_2_west(21)(13) , Grant => Signal_grant(21)(13)); + +Arbiter_21_14 : Arbiter + +PORT MAP (Request => Request(112), North => south_2_north(20)(14), West => east_2_west(20)(13), P => Signal_priority(7), Fifo_full => Fifo_full(14), +South => south_2_north(21)(14), East => east_2_west(21)(14) , Grant => Signal_grant(21)(14)); + +-------------------------- Diagonale n° 22 + + +Arbiter_22_1 : Arbiter + +PORT MAP (Request => Request(99), North => south_2_north(21)(1), West => east_2_west(21)(14), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); + +Arbiter_22_2 : Arbiter + +PORT MAP (Request => Request(86), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); + +Arbiter_22_3 : Arbiter + +PORT MAP (Request => Request(73), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); + +Arbiter_22_4 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); + +Arbiter_22_5 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5), +South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); + +Arbiter_22_6 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6), +South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); + +Arbiter_22_7 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7), +South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); + +Arbiter_22_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8), +South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); + +Arbiter_22_9 : Arbiter + +PORT MAP (Request => Request(191), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9), +South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); + +Arbiter_22_10 : Arbiter + +PORT MAP (Request => Request(178), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10), +South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); + +Arbiter_22_11 : Arbiter + +PORT MAP (Request => Request(165), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11), +South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); + +Arbiter_22_12 : Arbiter + +PORT MAP (Request => Request(152), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12), +South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); + +Arbiter_22_13 : Arbiter + +PORT MAP (Request => Request(139), North => south_2_north(21)(13), West => east_2_west(21)(12), P => Signal_priority(6), Fifo_full => Fifo_full(13), +South => south_2_north(22)(13), East => east_2_west(22)(13) , Grant => Signal_grant(22)(13)); + +Arbiter_22_14 : Arbiter + +PORT MAP (Request => Request(126), North => south_2_north(21)(14), West => east_2_west(21)(13), P => Signal_priority(6), Fifo_full => Fifo_full(14), +South => south_2_north(22)(14), East => east_2_west(22)(14) , Grant => Signal_grant(22)(14)); + +-------------------------- Diagonale n° 23 + + +Arbiter_23_1 : Arbiter + +PORT MAP (Request => Request(113), North => south_2_north(22)(1), West => east_2_west(22)(14), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); + +Arbiter_23_2 : Arbiter + +PORT MAP (Request => Request(100), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); + +Arbiter_23_3 : Arbiter + +PORT MAP (Request => Request(87), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); + +Arbiter_23_4 : Arbiter + +PORT MAP (Request => Request(74), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); + +Arbiter_23_5 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5), +South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); + +Arbiter_23_6 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6), +South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); + +Arbiter_23_7 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7), +South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); + +Arbiter_23_8 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8), +South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); + +Arbiter_23_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9), +South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); + +Arbiter_23_10 : Arbiter + +PORT MAP (Request => Request(192), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10), +South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); + +Arbiter_23_11 : Arbiter + +PORT MAP (Request => Request(179), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11), +South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); + +Arbiter_23_12 : Arbiter + +PORT MAP (Request => Request(166), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12), +South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); + +Arbiter_23_13 : Arbiter + +PORT MAP (Request => Request(153), North => south_2_north(22)(13), West => east_2_west(22)(12), P => Signal_priority(5), Fifo_full => Fifo_full(13), +South => south_2_north(23)(13), East => east_2_west(23)(13) , Grant => Signal_grant(23)(13)); + +Arbiter_23_14 : Arbiter + +PORT MAP (Request => Request(140), North => south_2_north(22)(14), West => east_2_west(22)(13), P => Signal_priority(5), Fifo_full => Fifo_full(14), +South => south_2_north(23)(14), East => east_2_west(23)(14) , Grant => Signal_grant(23)(14)); + +-------------------------- Diagonale n° 24 + + +Arbiter_24_1 : Arbiter + +PORT MAP (Request => Request(127), North => south_2_north(23)(1), West => east_2_west(23)(14), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(24)(1), East => east_2_west(24)(1) , Grant => Signal_grant(24)(1)); + +Arbiter_24_2 : Arbiter + +PORT MAP (Request => Request(114), North => south_2_north(23)(2), West => east_2_west(23)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(24)(2), East => east_2_west(24)(2) , Grant => Signal_grant(24)(2)); + +Arbiter_24_3 : Arbiter + +PORT MAP (Request => Request(101), North => south_2_north(23)(3), West => east_2_west(23)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(24)(3), East => east_2_west(24)(3) , Grant => Signal_grant(24)(3)); + +Arbiter_24_4 : Arbiter + +PORT MAP (Request => Request(88), North => south_2_north(23)(4), West => east_2_west(23)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(24)(4), East => east_2_west(24)(4) , Grant => Signal_grant(24)(4)); + +Arbiter_24_5 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(23)(5), West => east_2_west(23)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5), +South => south_2_north(24)(5), East => east_2_west(24)(5) , Grant => Signal_grant(24)(5)); + +Arbiter_24_6 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(23)(6), West => east_2_west(23)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6), +South => south_2_north(24)(6), East => east_2_west(24)(6) , Grant => Signal_grant(24)(6)); + +Arbiter_24_7 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(23)(7), West => east_2_west(23)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7), +South => south_2_north(24)(7), East => east_2_west(24)(7) , Grant => Signal_grant(24)(7)); + +Arbiter_24_8 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(23)(8), West => east_2_west(23)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8), +South => south_2_north(24)(8), East => east_2_west(24)(8) , Grant => Signal_grant(24)(8)); + +Arbiter_24_9 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(23)(9), West => east_2_west(23)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9), +South => south_2_north(24)(9), East => east_2_west(24)(9) , Grant => Signal_grant(24)(9)); + +Arbiter_24_10 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(23)(10), West => east_2_west(23)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10), +South => south_2_north(24)(10), East => east_2_west(24)(10) , Grant => Signal_grant(24)(10)); + +Arbiter_24_11 : Arbiter + +PORT MAP (Request => Request(193), North => south_2_north(23)(11), West => east_2_west(23)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11), +South => south_2_north(24)(11), East => east_2_west(24)(11) , Grant => Signal_grant(24)(11)); + +Arbiter_24_12 : Arbiter + +PORT MAP (Request => Request(180), North => south_2_north(23)(12), West => east_2_west(23)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12), +South => south_2_north(24)(12), East => east_2_west(24)(12) , Grant => Signal_grant(24)(12)); + +Arbiter_24_13 : Arbiter + +PORT MAP (Request => Request(167), North => south_2_north(23)(13), West => east_2_west(23)(12), P => Signal_priority(4), Fifo_full => Fifo_full(13), +South => south_2_north(24)(13), East => east_2_west(24)(13) , Grant => Signal_grant(24)(13)); + +Arbiter_24_14 : Arbiter + +PORT MAP (Request => Request(154), North => south_2_north(23)(14), West => east_2_west(23)(13), P => Signal_priority(4), Fifo_full => Fifo_full(14), +South => south_2_north(24)(14), East => east_2_west(24)(14) , Grant => Signal_grant(24)(14)); + +-------------------------- Diagonale n° 25 + + +Arbiter_25_1 : Arbiter + +PORT MAP (Request => Request(141), North => south_2_north(24)(1), West => east_2_west(24)(14), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(25)(1), East => east_2_west(25)(1) , Grant => Signal_grant(25)(1)); + +Arbiter_25_2 : Arbiter + +PORT MAP (Request => Request(128), North => south_2_north(24)(2), West => east_2_west(24)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(25)(2), East => east_2_west(25)(2) , Grant => Signal_grant(25)(2)); + +Arbiter_25_3 : Arbiter + +PORT MAP (Request => Request(115), North => south_2_north(24)(3), West => east_2_west(24)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(25)(3), East => east_2_west(25)(3) , Grant => Signal_grant(25)(3)); + +Arbiter_25_4 : Arbiter + +PORT MAP (Request => Request(102), North => south_2_north(24)(4), West => east_2_west(24)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(25)(4), East => east_2_west(25)(4) , Grant => Signal_grant(25)(4)); + +Arbiter_25_5 : Arbiter + +PORT MAP (Request => Request(89), North => south_2_north(24)(5), West => east_2_west(24)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5), +South => south_2_north(25)(5), East => east_2_west(25)(5) , Grant => Signal_grant(25)(5)); + +Arbiter_25_6 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(24)(6), West => east_2_west(24)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6), +South => south_2_north(25)(6), East => east_2_west(25)(6) , Grant => Signal_grant(25)(6)); + +Arbiter_25_7 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(24)(7), West => east_2_west(24)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7), +South => south_2_north(25)(7), East => east_2_west(25)(7) , Grant => Signal_grant(25)(7)); + +Arbiter_25_8 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(24)(8), West => east_2_west(24)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8), +South => south_2_north(25)(8), East => east_2_west(25)(8) , Grant => Signal_grant(25)(8)); + +Arbiter_25_9 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(24)(9), West => east_2_west(24)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9), +South => south_2_north(25)(9), East => east_2_west(25)(9) , Grant => Signal_grant(25)(9)); + +Arbiter_25_10 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(24)(10), West => east_2_west(24)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10), +South => south_2_north(25)(10), East => east_2_west(25)(10) , Grant => Signal_grant(25)(10)); + +Arbiter_25_11 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(24)(11), West => east_2_west(24)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11), +South => south_2_north(25)(11), East => east_2_west(25)(11) , Grant => Signal_grant(25)(11)); + +Arbiter_25_12 : Arbiter + +PORT MAP (Request => Request(194), North => south_2_north(24)(12), West => east_2_west(24)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12), +South => south_2_north(25)(12), East => east_2_west(25)(12) , Grant => Signal_grant(25)(12)); + +Arbiter_25_13 : Arbiter + +PORT MAP (Request => Request(181), North => south_2_north(24)(13), West => east_2_west(24)(12), P => Signal_priority(3), Fifo_full => Fifo_full(13), +South => south_2_north(25)(13), East => east_2_west(25)(13) , Grant => Signal_grant(25)(13)); + +Arbiter_25_14 : Arbiter + +PORT MAP (Request => Request(168), North => south_2_north(24)(14), West => east_2_west(24)(13), P => Signal_priority(3), Fifo_full => Fifo_full(14), +South => south_2_north(25)(14), East => east_2_west(25)(14) , Grant => Signal_grant(25)(14)); + +-------------------------- Diagonale n° 26 + + +Arbiter_26_1 : Arbiter + +PORT MAP (Request => Request(155), North => south_2_north(25)(1), West => east_2_west(25)(14), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(26)(1), East => east_2_west(26)(1) , Grant => Signal_grant(26)(1)); + +Arbiter_26_2 : Arbiter + +PORT MAP (Request => Request(142), North => south_2_north(25)(2), West => east_2_west(25)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(26)(2), East => east_2_west(26)(2) , Grant => Signal_grant(26)(2)); + +Arbiter_26_3 : Arbiter + +PORT MAP (Request => Request(129), North => south_2_north(25)(3), West => east_2_west(25)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(26)(3), East => east_2_west(26)(3) , Grant => Signal_grant(26)(3)); + +Arbiter_26_4 : Arbiter + +PORT MAP (Request => Request(116), North => south_2_north(25)(4), West => east_2_west(25)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(26)(4), East => east_2_west(26)(4) , Grant => Signal_grant(26)(4)); + +Arbiter_26_5 : Arbiter + +PORT MAP (Request => Request(103), North => south_2_north(25)(5), West => east_2_west(25)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5), +South => south_2_north(26)(5), East => east_2_west(26)(5) , Grant => Signal_grant(26)(5)); + +Arbiter_26_6 : Arbiter + +PORT MAP (Request => Request(90), North => south_2_north(25)(6), West => east_2_west(25)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6), +South => south_2_north(26)(6), East => east_2_west(26)(6) , Grant => Signal_grant(26)(6)); + +Arbiter_26_7 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(25)(7), West => east_2_west(25)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7), +South => south_2_north(26)(7), East => east_2_west(26)(7) , Grant => Signal_grant(26)(7)); + +Arbiter_26_8 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(25)(8), West => east_2_west(25)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8), +South => south_2_north(26)(8), East => east_2_west(26)(8) , Grant => Signal_grant(26)(8)); + +Arbiter_26_9 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(25)(9), West => east_2_west(25)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9), +South => south_2_north(26)(9), East => east_2_west(26)(9) , Grant => Signal_grant(26)(9)); + +Arbiter_26_10 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(25)(10), West => east_2_west(25)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10), +South => south_2_north(26)(10), East => east_2_west(26)(10) , Grant => Signal_grant(26)(10)); + +Arbiter_26_11 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(25)(11), West => east_2_west(25)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11), +South => south_2_north(26)(11), East => east_2_west(26)(11) , Grant => Signal_grant(26)(11)); + +Arbiter_26_12 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(25)(12), West => east_2_west(25)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12), +South => south_2_north(26)(12), East => east_2_west(26)(12) , Grant => Signal_grant(26)(12)); + +Arbiter_26_13 : Arbiter + +PORT MAP (Request => Request(195), North => south_2_north(25)(13), West => east_2_west(25)(12), P => Signal_priority(2), Fifo_full => Fifo_full(13), +South => south_2_north(26)(13), East => east_2_west(26)(13) , Grant => Signal_grant(26)(13)); + +Arbiter_26_14 : Arbiter + +PORT MAP (Request => Request(182), North => south_2_north(25)(14), West => east_2_west(25)(13), P => Signal_priority(2), Fifo_full => Fifo_full(14), +South => south_2_north(26)(14), East => east_2_west(26)(14) , Grant => Signal_grant(26)(14)); + +-------------------------- Diagonale n° 27 + + +Arbiter_27_1 : Arbiter + +PORT MAP (Request => Request(169), North => south_2_north(26)(1), West => east_2_west(26)(14), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(27)(1), East => east_2_west(27)(1) , Grant => Signal_grant(27)(1)); + +Arbiter_27_2 : Arbiter + +PORT MAP (Request => Request(156), North => south_2_north(26)(2), West => east_2_west(26)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(27)(2), East => east_2_west(27)(2) , Grant => Signal_grant(27)(2)); + +Arbiter_27_3 : Arbiter + +PORT MAP (Request => Request(143), North => south_2_north(26)(3), West => east_2_west(26)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(27)(3), East => east_2_west(27)(3) , Grant => Signal_grant(27)(3)); + +Arbiter_27_4 : Arbiter + +PORT MAP (Request => Request(130), North => south_2_north(26)(4), West => east_2_west(26)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(27)(4), East => east_2_west(27)(4) , Grant => Signal_grant(27)(4)); + +Arbiter_27_5 : Arbiter + +PORT MAP (Request => Request(117), North => south_2_north(26)(5), West => east_2_west(26)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5), +South => south_2_north(27)(5), East => east_2_west(27)(5) , Grant => Signal_grant(27)(5)); + +Arbiter_27_6 : Arbiter + +PORT MAP (Request => Request(104), North => south_2_north(26)(6), West => east_2_west(26)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6), +South => south_2_north(27)(6), East => east_2_west(27)(6) , Grant => Signal_grant(27)(6)); + +Arbiter_27_7 : Arbiter + +PORT MAP (Request => Request(91), North => south_2_north(26)(7), West => east_2_west(26)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7), +South => south_2_north(27)(7), East => east_2_west(27)(7) , Grant => Signal_grant(27)(7)); + +Arbiter_27_8 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(26)(8), West => east_2_west(26)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8), +South => south_2_north(27)(8), East => east_2_west(27)(8) , Grant => Signal_grant(27)(8)); + +Arbiter_27_9 : Arbiter + +PORT MAP (Request => Request(65), North => south_2_north(26)(9), West => east_2_west(26)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9), +South => south_2_north(27)(9), East => east_2_west(27)(9) , Grant => Signal_grant(27)(9)); + +Arbiter_27_10 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(26)(10), West => east_2_west(26)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10), +South => south_2_north(27)(10), East => east_2_west(27)(10) , Grant => Signal_grant(27)(10)); + +Arbiter_27_11 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(26)(11), West => east_2_west(26)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11), +South => south_2_north(27)(11), East => east_2_west(27)(11) , Grant => Signal_grant(27)(11)); + +Arbiter_27_12 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(26)(12), West => east_2_west(26)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12), +South => south_2_north(27)(12), East => east_2_west(27)(12) , Grant => Signal_grant(27)(12)); + +Arbiter_27_13 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(26)(13), West => east_2_west(26)(12), P => Signal_priority(1), Fifo_full => Fifo_full(13), +South => south_2_north(27)(13), East => east_2_west(27)(13) , Grant => Signal_grant(27)(13)); + +Arbiter_27_14 : Arbiter + +PORT MAP (Request => Request(196), North => south_2_north(26)(14), West => east_2_west(26)(13), P => Signal_priority(1), Fifo_full => Fifo_full(14), +South => south_2_north(27)(14), East => east_2_west(27)(14) , Grant => Signal_grant(27)(14)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "111111111111110000000000000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "111111111111110000000000000" => Signal_priority <= "011111111111111000000000000"; + when "011111111111111000000000000" => Signal_priority <= "001111111111111100000000000"; + when "001111111111111100000000000" => Signal_priority <= "000111111111111110000000000"; + when "000111111111111110000000000" => Signal_priority <= "000011111111111111000000000"; + when "000011111111111111000000000" => Signal_priority <= "000001111111111111100000000"; + when "000001111111111111100000000" => Signal_priority <= "000000111111111111110000000"; + when "000000111111111111110000000" => Signal_priority <= "000000011111111111111000000"; + when "000000011111111111111000000" => Signal_priority <= "000000001111111111111100000"; + when "000000001111111111111100000" => Signal_priority <= "000000000111111111111110000"; + when "000000000111111111111110000" => Signal_priority <= "000000000011111111111111000"; + when "000000000011111111111111000" => Signal_priority <= "000000000001111111111111100"; + when "000000000001111111111111100" => Signal_priority <= "000000000000111111111111110"; + when "000000000000111111111111110" => Signal_priority <= "000000000000011111111111111"; + when "000000000000011111111111111" => Signal_priority <= "111111111111110000000000000"; + when others => Signal_priority <= "111111111111110000000000000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER15_15.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER15_15.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER15_15.VHD (revision 138) @@ -0,0 +1,2598 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler15_15 is + Port ( Request : in STD_LOGIC_VECTOR (225 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (15 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (15 downto 1); + port_grant : out STD_LOGIC_VECTOR (225 downto 1)); +end Scheduler15_15; + +architecture Behavioral of Scheduler15_15 is +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(29 downto 1) of STD_LOGIC_VECTOR(15 downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (29 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(225 downto 1); + signal priority_rotation_en : std_logic; + signal Grant ,req_grant: std_logic_vector(225 downto 1); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet +req_grant<=(request and grant_latch); + priority_rotation_en <= '1' when unsigned(req_grant)=0 or unsigned(priority_rotation) = 32767 else '0'; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + elsif priority_rotation_en = '1'or unsigned(Grant_latch)=0 then + grant_latch <= Grant; + end if; + end if; + end process; + port_grant <= grant_latch; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(16)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(17)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(18)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) or Signal_grant(19)(4); -- Grant(1,4) +Grant(5) <= Signal_grant(5)(5) or Signal_grant(20)(5); -- Grant(1,5) +Grant(6) <= Signal_grant(6)(6) or Signal_grant(21)(6); -- Grant(1,6) +Grant(7) <= Signal_grant(7)(7) or Signal_grant(22)(7); -- Grant(1,7) +Grant(8) <= Signal_grant(8)(8) or Signal_grant(23)(8); -- Grant(1,8) +Grant(9) <= Signal_grant(9)(9) or Signal_grant(24)(9); -- Grant(1,9) +Grant(10) <= Signal_grant(10)(10) or Signal_grant(25)(10); -- Grant(1,10) +Grant(11) <= Signal_grant(11)(11) or Signal_grant(26)(11); -- Grant(1,11) +Grant(12) <= Signal_grant(12)(12) or Signal_grant(27)(12); -- Grant(1,12) +Grant(13) <= Signal_grant(13)(13) or Signal_grant(28)(13); -- Grant(1,13) +Grant(14) <= Signal_grant(14)(14) or Signal_grant(29)(14); -- Grant(1,14) +Grant(15) <= Signal_grant(15)(15) ; -- Grant(1,15) +Grant(16) <= Signal_grant(2)(1) or Signal_grant(17)(1); -- Grant(2,1) +Grant(17) <= Signal_grant(3)(2) or Signal_grant(18)(2); -- Grant(2,2) +Grant(18) <= Signal_grant(4)(3) or Signal_grant(19)(3); -- Grant(2,3) +Grant(19) <= Signal_grant(5)(4) or Signal_grant(20)(4); -- Grant(2,4) +Grant(20) <= Signal_grant(6)(5) or Signal_grant(21)(5); -- Grant(2,5) +Grant(21) <= Signal_grant(7)(6) or Signal_grant(22)(6); -- Grant(2,6) +Grant(22) <= Signal_grant(8)(7) or Signal_grant(23)(7); -- Grant(2,7) +Grant(23) <= Signal_grant(9)(8) or Signal_grant(24)(8); -- Grant(2,8) +Grant(24) <= Signal_grant(10)(9) or Signal_grant(25)(9); -- Grant(2,9) +Grant(25) <= Signal_grant(11)(10) or Signal_grant(26)(10); -- Grant(2,10) +Grant(26) <= Signal_grant(12)(11) or Signal_grant(27)(11); -- Grant(2,11) +Grant(27) <= Signal_grant(13)(12) or Signal_grant(28)(12); -- Grant(2,12) +Grant(28) <= Signal_grant(14)(13) or Signal_grant(29)(13); -- Grant(2,13) +Grant(29) <= Signal_grant(15)(14) ; -- Grant(2,14) +Grant(30) <= Signal_grant(1)(15) or Signal_grant(16)(15); -- Grant(2,15) +Grant(31) <= Signal_grant(3)(1) or Signal_grant(18)(1); -- Grant(3,1) +Grant(32) <= Signal_grant(4)(2) or Signal_grant(19)(2); -- Grant(3,2) +Grant(33) <= Signal_grant(5)(3) or Signal_grant(20)(3); -- Grant(3,3) +Grant(34) <= Signal_grant(6)(4) or Signal_grant(21)(4); -- Grant(3,4) +Grant(35) <= Signal_grant(7)(5) or Signal_grant(22)(5); -- Grant(3,5) +Grant(36) <= Signal_grant(8)(6) or Signal_grant(23)(6); -- Grant(3,6) +Grant(37) <= Signal_grant(9)(7) or Signal_grant(24)(7); -- Grant(3,7) +Grant(38) <= Signal_grant(10)(8) or Signal_grant(25)(8); -- Grant(3,8) +Grant(39) <= Signal_grant(11)(9) or Signal_grant(26)(9); -- Grant(3,9) +Grant(40) <= Signal_grant(12)(10) or Signal_grant(27)(10); -- Grant(3,10) +Grant(41) <= Signal_grant(13)(11) or Signal_grant(28)(11); -- Grant(3,11) +Grant(42) <= Signal_grant(14)(12) or Signal_grant(29)(12); -- Grant(3,12) +Grant(43) <= Signal_grant(15)(13) ; -- Grant(3,13) +Grant(44) <= Signal_grant(1)(14) or Signal_grant(16)(14); -- Grant(3,14) +Grant(45) <= Signal_grant(2)(15) or Signal_grant(17)(15); -- Grant(3,15) +Grant(46) <= Signal_grant(4)(1) or Signal_grant(19)(1); -- Grant(4,1) +Grant(47) <= Signal_grant(5)(2) or Signal_grant(20)(2); -- Grant(4,2) +Grant(48) <= Signal_grant(6)(3) or Signal_grant(21)(3); -- Grant(4,3) +Grant(49) <= Signal_grant(7)(4) or Signal_grant(22)(4); -- Grant(4,4) +Grant(50) <= Signal_grant(8)(5) or Signal_grant(23)(5); -- Grant(4,5) +Grant(51) <= Signal_grant(9)(6) or Signal_grant(24)(6); -- Grant(4,6) +Grant(52) <= Signal_grant(10)(7) or Signal_grant(25)(7); -- Grant(4,7) +Grant(53) <= Signal_grant(11)(8) or Signal_grant(26)(8); -- Grant(4,8) +Grant(54) <= Signal_grant(12)(9) or Signal_grant(27)(9); -- Grant(4,9) +Grant(55) <= Signal_grant(13)(10) or Signal_grant(28)(10); -- Grant(4,10) +Grant(56) <= Signal_grant(14)(11) or Signal_grant(29)(11); -- Grant(4,11) +Grant(57) <= Signal_grant(15)(12) ; -- Grant(4,12) +Grant(58) <= Signal_grant(1)(13) or Signal_grant(16)(13); -- Grant(4,13) +Grant(59) <= Signal_grant(2)(14) or Signal_grant(17)(14); -- Grant(4,14) +Grant(60) <= Signal_grant(3)(15) or Signal_grant(18)(15); -- Grant(4,15) +Grant(61) <= Signal_grant(5)(1) or Signal_grant(20)(1); -- Grant(5,1) +Grant(62) <= Signal_grant(6)(2) or Signal_grant(21)(2); -- Grant(5,2) +Grant(63) <= Signal_grant(7)(3) or Signal_grant(22)(3); -- Grant(5,3) +Grant(64) <= Signal_grant(8)(4) or Signal_grant(23)(4); -- Grant(5,4) +Grant(65) <= Signal_grant(9)(5) or Signal_grant(24)(5); -- Grant(5,5) +Grant(66) <= Signal_grant(10)(6) or Signal_grant(25)(6); -- Grant(5,6) +Grant(67) <= Signal_grant(11)(7) or Signal_grant(26)(7); -- Grant(5,7) +Grant(68) <= Signal_grant(12)(8) or Signal_grant(27)(8); -- Grant(5,8) +Grant(69) <= Signal_grant(13)(9) or Signal_grant(28)(9); -- Grant(5,9) +Grant(70) <= Signal_grant(14)(10) or Signal_grant(29)(10); -- Grant(5,10) +Grant(71) <= Signal_grant(15)(11) ; -- Grant(5,11) +Grant(72) <= Signal_grant(1)(12) or Signal_grant(16)(12); -- Grant(5,12) +Grant(73) <= Signal_grant(2)(13) or Signal_grant(17)(13); -- Grant(5,13) +Grant(74) <= Signal_grant(3)(14) or Signal_grant(18)(14); -- Grant(5,14) +Grant(75) <= Signal_grant(4)(15) or Signal_grant(19)(15); -- Grant(5,15) +Grant(76) <= Signal_grant(6)(1) or Signal_grant(21)(1); -- Grant(6,1) +Grant(77) <= Signal_grant(7)(2) or Signal_grant(22)(2); -- Grant(6,2) +Grant(78) <= Signal_grant(8)(3) or Signal_grant(23)(3); -- Grant(6,3) +Grant(79) <= Signal_grant(9)(4) or Signal_grant(24)(4); -- Grant(6,4) +Grant(80) <= Signal_grant(10)(5) or Signal_grant(25)(5); -- Grant(6,5) +Grant(81) <= Signal_grant(11)(6) or Signal_grant(26)(6); -- Grant(6,6) +Grant(82) <= Signal_grant(12)(7) or Signal_grant(27)(7); -- Grant(6,7) +Grant(83) <= Signal_grant(13)(8) or Signal_grant(28)(8); -- Grant(6,8) +Grant(84) <= Signal_grant(14)(9) or Signal_grant(29)(9); -- Grant(6,9) +Grant(85) <= Signal_grant(15)(10) ; -- Grant(6,10) +Grant(86) <= Signal_grant(1)(11) or Signal_grant(16)(11); -- Grant(6,11) +Grant(87) <= Signal_grant(2)(12) or Signal_grant(17)(12); -- Grant(6,12) +Grant(88) <= Signal_grant(3)(13) or Signal_grant(18)(13); -- Grant(6,13) +Grant(89) <= Signal_grant(4)(14) or Signal_grant(19)(14); -- Grant(6,14) +Grant(90) <= Signal_grant(5)(15) or Signal_grant(20)(15); -- Grant(6,15) +Grant(91) <= Signal_grant(7)(1) or Signal_grant(22)(1); -- Grant(7,1) +Grant(92) <= Signal_grant(8)(2) or Signal_grant(23)(2); -- Grant(7,2) +Grant(93) <= Signal_grant(9)(3) or Signal_grant(24)(3); -- Grant(7,3) +Grant(94) <= Signal_grant(10)(4) or Signal_grant(25)(4); -- Grant(7,4) +Grant(95) <= Signal_grant(11)(5) or Signal_grant(26)(5); -- Grant(7,5) +Grant(96) <= Signal_grant(12)(6) or Signal_grant(27)(6); -- Grant(7,6) +Grant(97) <= Signal_grant(13)(7) or Signal_grant(28)(7); -- Grant(7,7) +Grant(98) <= Signal_grant(14)(8) or Signal_grant(29)(8); -- Grant(7,8) +Grant(99) <= Signal_grant(15)(9) ; -- Grant(7,9) +Grant(100) <= Signal_grant(1)(10) or Signal_grant(16)(10); -- Grant(7,10) +Grant(101) <= Signal_grant(2)(11) or Signal_grant(17)(11); -- Grant(7,11) +Grant(102) <= Signal_grant(3)(12) or Signal_grant(18)(12); -- Grant(7,12) +Grant(103) <= Signal_grant(4)(13) or Signal_grant(19)(13); -- Grant(7,13) +Grant(104) <= Signal_grant(5)(14) or Signal_grant(20)(14); -- Grant(7,14) +Grant(105) <= Signal_grant(6)(15) or Signal_grant(21)(15); -- Grant(7,15) +Grant(106) <= Signal_grant(8)(1) or Signal_grant(23)(1); -- Grant(8,1) +Grant(107) <= Signal_grant(9)(2) or Signal_grant(24)(2); -- Grant(8,2) +Grant(108) <= Signal_grant(10)(3) or Signal_grant(25)(3); -- Grant(8,3) +Grant(109) <= Signal_grant(11)(4) or Signal_grant(26)(4); -- Grant(8,4) +Grant(110) <= Signal_grant(12)(5) or Signal_grant(27)(5); -- Grant(8,5) +Grant(111) <= Signal_grant(13)(6) or Signal_grant(28)(6); -- Grant(8,6) +Grant(112) <= Signal_grant(14)(7) or Signal_grant(29)(7); -- Grant(8,7) +Grant(113) <= Signal_grant(15)(8) ; -- Grant(8,8) +Grant(114) <= Signal_grant(1)(9) or Signal_grant(16)(9); -- Grant(8,9) +Grant(115) <= Signal_grant(2)(10) or Signal_grant(17)(10); -- Grant(8,10) +Grant(116) <= Signal_grant(3)(11) or Signal_grant(18)(11); -- Grant(8,11) +Grant(117) <= Signal_grant(4)(12) or Signal_grant(19)(12); -- Grant(8,12) +Grant(118) <= Signal_grant(5)(13) or Signal_grant(20)(13); -- Grant(8,13) +Grant(119) <= Signal_grant(6)(14) or Signal_grant(21)(14); -- Grant(8,14) +Grant(120) <= Signal_grant(7)(15) or Signal_grant(22)(15); -- Grant(8,15) +Grant(121) <= Signal_grant(9)(1) or Signal_grant(24)(1); -- Grant(9,1) +Grant(122) <= Signal_grant(10)(2) or Signal_grant(25)(2); -- Grant(9,2) +Grant(123) <= Signal_grant(11)(3) or Signal_grant(26)(3); -- Grant(9,3) +Grant(124) <= Signal_grant(12)(4) or Signal_grant(27)(4); -- Grant(9,4) +Grant(125) <= Signal_grant(13)(5) or Signal_grant(28)(5); -- Grant(9,5) +Grant(126) <= Signal_grant(14)(6) or Signal_grant(29)(6); -- Grant(9,6) +Grant(127) <= Signal_grant(15)(7) ; -- Grant(9,7) +Grant(128) <= Signal_grant(1)(8) or Signal_grant(16)(8); -- Grant(9,8) +Grant(129) <= Signal_grant(2)(9) or Signal_grant(17)(9); -- Grant(9,9) +Grant(130) <= Signal_grant(3)(10) or Signal_grant(18)(10); -- Grant(9,10) +Grant(131) <= Signal_grant(4)(11) or Signal_grant(19)(11); -- Grant(9,11) +Grant(132) <= Signal_grant(5)(12) or Signal_grant(20)(12); -- Grant(9,12) +Grant(133) <= Signal_grant(6)(13) or Signal_grant(21)(13); -- Grant(9,13) +Grant(134) <= Signal_grant(7)(14) or Signal_grant(22)(14); -- Grant(9,14) +Grant(135) <= Signal_grant(8)(15) or Signal_grant(23)(15); -- Grant(9,15) +Grant(136) <= Signal_grant(10)(1) or Signal_grant(25)(1); -- Grant(10,1) +Grant(137) <= Signal_grant(11)(2) or Signal_grant(26)(2); -- Grant(10,2) +Grant(138) <= Signal_grant(12)(3) or Signal_grant(27)(3); -- Grant(10,3) +Grant(139) <= Signal_grant(13)(4) or Signal_grant(28)(4); -- Grant(10,4) +Grant(140) <= Signal_grant(14)(5) or Signal_grant(29)(5); -- Grant(10,5) +Grant(141) <= Signal_grant(15)(6) ; -- Grant(10,6) +Grant(142) <= Signal_grant(1)(7) or Signal_grant(16)(7); -- Grant(10,7) +Grant(143) <= Signal_grant(2)(8) or Signal_grant(17)(8); -- Grant(10,8) +Grant(144) <= Signal_grant(3)(9) or Signal_grant(18)(9); -- Grant(10,9) +Grant(145) <= Signal_grant(4)(10) or Signal_grant(19)(10); -- Grant(10,10) +Grant(146) <= Signal_grant(5)(11) or Signal_grant(20)(11); -- Grant(10,11) +Grant(147) <= Signal_grant(6)(12) or Signal_grant(21)(12); -- Grant(10,12) +Grant(148) <= Signal_grant(7)(13) or Signal_grant(22)(13); -- Grant(10,13) +Grant(149) <= Signal_grant(8)(14) or Signal_grant(23)(14); -- Grant(10,14) +Grant(150) <= Signal_grant(9)(15) or Signal_grant(24)(15); -- Grant(10,15) +Grant(151) <= Signal_grant(11)(1) or Signal_grant(26)(1); -- Grant(11,1) +Grant(152) <= Signal_grant(12)(2) or Signal_grant(27)(2); -- Grant(11,2) +Grant(153) <= Signal_grant(13)(3) or Signal_grant(28)(3); -- Grant(11,3) +Grant(154) <= Signal_grant(14)(4) or Signal_grant(29)(4); -- Grant(11,4) +Grant(155) <= Signal_grant(15)(5) ; -- Grant(11,5) +Grant(156) <= Signal_grant(1)(6) or Signal_grant(16)(6); -- Grant(11,6) +Grant(157) <= Signal_grant(2)(7) or Signal_grant(17)(7); -- Grant(11,7) +Grant(158) <= Signal_grant(3)(8) or Signal_grant(18)(8); -- Grant(11,8) +Grant(159) <= Signal_grant(4)(9) or Signal_grant(19)(9); -- Grant(11,9) +Grant(160) <= Signal_grant(5)(10) or Signal_grant(20)(10); -- Grant(11,10) +Grant(161) <= Signal_grant(6)(11) or Signal_grant(21)(11); -- Grant(11,11) +Grant(162) <= Signal_grant(7)(12) or Signal_grant(22)(12); -- Grant(11,12) +Grant(163) <= Signal_grant(8)(13) or Signal_grant(23)(13); -- Grant(11,13) +Grant(164) <= Signal_grant(9)(14) or Signal_grant(24)(14); -- Grant(11,14) +Grant(165) <= Signal_grant(10)(15) or Signal_grant(25)(15); -- Grant(11,15) +Grant(166) <= Signal_grant(12)(1) or Signal_grant(27)(1); -- Grant(12,1) +Grant(167) <= Signal_grant(13)(2) or Signal_grant(28)(2); -- Grant(12,2) +Grant(168) <= Signal_grant(14)(3) or Signal_grant(29)(3); -- Grant(12,3) +Grant(169) <= Signal_grant(15)(4) ; -- Grant(12,4) +Grant(170) <= Signal_grant(1)(5) or Signal_grant(16)(5); -- Grant(12,5) +Grant(171) <= Signal_grant(2)(6) or Signal_grant(17)(6); -- Grant(12,6) +Grant(172) <= Signal_grant(3)(7) or Signal_grant(18)(7); -- Grant(12,7) +Grant(173) <= Signal_grant(4)(8) or Signal_grant(19)(8); -- Grant(12,8) +Grant(174) <= Signal_grant(5)(9) or Signal_grant(20)(9); -- Grant(12,9) +Grant(175) <= Signal_grant(6)(10) or Signal_grant(21)(10); -- Grant(12,10) +Grant(176) <= Signal_grant(7)(11) or Signal_grant(22)(11); -- Grant(12,11) +Grant(177) <= Signal_grant(8)(12) or Signal_grant(23)(12); -- Grant(12,12) +Grant(178) <= Signal_grant(9)(13) or Signal_grant(24)(13); -- Grant(12,13) +Grant(179) <= Signal_grant(10)(14) or Signal_grant(25)(14); -- Grant(12,14) +Grant(180) <= Signal_grant(11)(15) or Signal_grant(26)(15); -- Grant(12,15) +Grant(181) <= Signal_grant(13)(1) or Signal_grant(28)(1); -- Grant(13,1) +Grant(182) <= Signal_grant(14)(2) or Signal_grant(29)(2); -- Grant(13,2) +Grant(183) <= Signal_grant(15)(3) ; -- Grant(13,3) +Grant(184) <= Signal_grant(1)(4) or Signal_grant(16)(4); -- Grant(13,4) +Grant(185) <= Signal_grant(2)(5) or Signal_grant(17)(5); -- Grant(13,5) +Grant(186) <= Signal_grant(3)(6) or Signal_grant(18)(6); -- Grant(13,6) +Grant(187) <= Signal_grant(4)(7) or Signal_grant(19)(7); -- Grant(13,7) +Grant(188) <= Signal_grant(5)(8) or Signal_grant(20)(8); -- Grant(13,8) +Grant(189) <= Signal_grant(6)(9) or Signal_grant(21)(9); -- Grant(13,9) +Grant(190) <= Signal_grant(7)(10) or Signal_grant(22)(10); -- Grant(13,10) +Grant(191) <= Signal_grant(8)(11) or Signal_grant(23)(11); -- Grant(13,11) +Grant(192) <= Signal_grant(9)(12) or Signal_grant(24)(12); -- Grant(13,12) +Grant(193) <= Signal_grant(10)(13) or Signal_grant(25)(13); -- Grant(13,13) +Grant(194) <= Signal_grant(11)(14) or Signal_grant(26)(14); -- Grant(13,14) +Grant(195) <= Signal_grant(12)(15) or Signal_grant(27)(15); -- Grant(13,15) +Grant(196) <= Signal_grant(14)(1) or Signal_grant(29)(1); -- Grant(14,1) +Grant(197) <= Signal_grant(15)(2) ; -- Grant(14,2) +Grant(198) <= Signal_grant(1)(3) or Signal_grant(16)(3); -- Grant(14,3) +Grant(199) <= Signal_grant(2)(4) or Signal_grant(17)(4); -- Grant(14,4) +Grant(200) <= Signal_grant(3)(5) or Signal_grant(18)(5); -- Grant(14,5) +Grant(201) <= Signal_grant(4)(6) or Signal_grant(19)(6); -- Grant(14,6) +Grant(202) <= Signal_grant(5)(7) or Signal_grant(20)(7); -- Grant(14,7) +Grant(203) <= Signal_grant(6)(8) or Signal_grant(21)(8); -- Grant(14,8) +Grant(204) <= Signal_grant(7)(9) or Signal_grant(22)(9); -- Grant(14,9) +Grant(205) <= Signal_grant(8)(10) or Signal_grant(23)(10); -- Grant(14,10) +Grant(206) <= Signal_grant(9)(11) or Signal_grant(24)(11); -- Grant(14,11) +Grant(207) <= Signal_grant(10)(12) or Signal_grant(25)(12); -- Grant(14,12) +Grant(208) <= Signal_grant(11)(13) or Signal_grant(26)(13); -- Grant(14,13) +Grant(209) <= Signal_grant(12)(14) or Signal_grant(27)(14); -- Grant(14,14) +Grant(210) <= Signal_grant(13)(15) or Signal_grant(28)(15); -- Grant(14,15) +Grant(211) <= Signal_grant(15)(1) ; -- Grant(15,1) +Grant(212) <= Signal_grant(1)(2) or Signal_grant(16)(2); -- Grant(15,2) +Grant(213) <= Signal_grant(2)(3) or Signal_grant(17)(3); -- Grant(15,3) +Grant(214) <= Signal_grant(3)(4) or Signal_grant(18)(4); -- Grant(15,4) +Grant(215) <= Signal_grant(4)(5) or Signal_grant(19)(5); -- Grant(15,5) +Grant(216) <= Signal_grant(5)(6) or Signal_grant(20)(6); -- Grant(15,6) +Grant(217) <= Signal_grant(6)(7) or Signal_grant(21)(7); -- Grant(15,7) +Grant(218) <= Signal_grant(7)(8) or Signal_grant(22)(8); -- Grant(15,8) +Grant(219) <= Signal_grant(8)(9) or Signal_grant(23)(9); -- Grant(15,9) +Grant(220) <= Signal_grant(9)(10) or Signal_grant(24)(10); -- Grant(15,10) +Grant(221) <= Signal_grant(10)(11) or Signal_grant(25)(11); -- Grant(15,11) +Grant(222) <= Signal_grant(11)(12) or Signal_grant(26)(12); -- Grant(15,12) +Grant(223) <= Signal_grant(12)(13) or Signal_grant(27)(13); -- Grant(15,13) +Grant(224) <= Signal_grant(13)(14) or Signal_grant(28)(14); -- Grant(15,14) +Grant(225) <= Signal_grant(14)(15) or Signal_grant(29)(15); -- Grant(15,15) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(212), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(198), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(184), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +Arbiter_1_5 : Arbiter + +PORT MAP (Request => Request(170), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(5), +South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); + +Arbiter_1_6 : Arbiter + +PORT MAP (Request => Request(156), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(6), +South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); + +Arbiter_1_7 : Arbiter + +PORT MAP (Request => Request(142), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(7), +South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); + +Arbiter_1_8 : Arbiter + +PORT MAP (Request => Request(128), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(8), +South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); + +Arbiter_1_9 : Arbiter + +PORT MAP (Request => Request(114), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(9), +South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); + +Arbiter_1_10 : Arbiter + +PORT MAP (Request => Request(100), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(10), +South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); + +Arbiter_1_11 : Arbiter + +PORT MAP (Request => Request(86), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(11), +South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); + +Arbiter_1_12 : Arbiter + +PORT MAP (Request => Request(72), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(12), +South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); + +Arbiter_1_13 : Arbiter + +PORT MAP (Request => Request(58), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(13), +South => south_2_north(1)(13), East => east_2_west(1)(13) , Grant => Signal_grant(1)(13)); + +Arbiter_1_14 : Arbiter + +PORT MAP (Request => Request(44), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(14), +South => south_2_north(1)(14), East => east_2_west(1)(14) , Grant => Signal_grant(1)(14)); + +Arbiter_1_15 : Arbiter + +PORT MAP (Request => Request(30), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(15), +South => south_2_north(1)(15), East => east_2_west(1)(15) , Grant => Signal_grant(1)(15)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(1)(1), West => east_2_west(1)(15), P => Signal_priority(28), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(28), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(213), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(28), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(199), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(28), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +Arbiter_2_5 : Arbiter + +PORT MAP (Request => Request(185), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(28), Fifo_full => Fifo_full(5), +South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); + +Arbiter_2_6 : Arbiter + +PORT MAP (Request => Request(171), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(28), Fifo_full => Fifo_full(6), +South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); + +Arbiter_2_7 : Arbiter + +PORT MAP (Request => Request(157), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(28), Fifo_full => Fifo_full(7), +South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); + +Arbiter_2_8 : Arbiter + +PORT MAP (Request => Request(143), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(28), Fifo_full => Fifo_full(8), +South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); + +Arbiter_2_9 : Arbiter + +PORT MAP (Request => Request(129), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(28), Fifo_full => Fifo_full(9), +South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); + +Arbiter_2_10 : Arbiter + +PORT MAP (Request => Request(115), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(28), Fifo_full => Fifo_full(10), +South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); + +Arbiter_2_11 : Arbiter + +PORT MAP (Request => Request(101), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(28), Fifo_full => Fifo_full(11), +South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); + +Arbiter_2_12 : Arbiter + +PORT MAP (Request => Request(87), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(28), Fifo_full => Fifo_full(12), +South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); + +Arbiter_2_13 : Arbiter + +PORT MAP (Request => Request(73), North => south_2_north(1)(13), West => east_2_west(1)(12), P => Signal_priority(28), Fifo_full => Fifo_full(13), +South => south_2_north(2)(13), East => east_2_west(2)(13) , Grant => Signal_grant(2)(13)); + +Arbiter_2_14 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(1)(14), West => east_2_west(1)(13), P => Signal_priority(28), Fifo_full => Fifo_full(14), +South => south_2_north(2)(14), East => east_2_west(2)(14) , Grant => Signal_grant(2)(14)); + +Arbiter_2_15 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(1)(15), West => east_2_west(1)(14), P => Signal_priority(28), Fifo_full => Fifo_full(15), +South => south_2_north(2)(15), East => east_2_west(2)(15) , Grant => Signal_grant(2)(15)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(2)(1), West => east_2_west(2)(15), P => Signal_priority(27), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(27), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(27), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(214), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(27), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +Arbiter_3_5 : Arbiter + +PORT MAP (Request => Request(200), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(27), Fifo_full => Fifo_full(5), +South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); + +Arbiter_3_6 : Arbiter + +PORT MAP (Request => Request(186), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(27), Fifo_full => Fifo_full(6), +South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); + +Arbiter_3_7 : Arbiter + +PORT MAP (Request => Request(172), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(27), Fifo_full => Fifo_full(7), +South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); + +Arbiter_3_8 : Arbiter + +PORT MAP (Request => Request(158), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(27), Fifo_full => Fifo_full(8), +South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); + +Arbiter_3_9 : Arbiter + +PORT MAP (Request => Request(144), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(27), Fifo_full => Fifo_full(9), +South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); + +Arbiter_3_10 : Arbiter + +PORT MAP (Request => Request(130), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(27), Fifo_full => Fifo_full(10), +South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); + +Arbiter_3_11 : Arbiter + +PORT MAP (Request => Request(116), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(27), Fifo_full => Fifo_full(11), +South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); + +Arbiter_3_12 : Arbiter + +PORT MAP (Request => Request(102), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(27), Fifo_full => Fifo_full(12), +South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); + +Arbiter_3_13 : Arbiter + +PORT MAP (Request => Request(88), North => south_2_north(2)(13), West => east_2_west(2)(12), P => Signal_priority(27), Fifo_full => Fifo_full(13), +South => south_2_north(3)(13), East => east_2_west(3)(13) , Grant => Signal_grant(3)(13)); + +Arbiter_3_14 : Arbiter + +PORT MAP (Request => Request(74), North => south_2_north(2)(14), West => east_2_west(2)(13), P => Signal_priority(27), Fifo_full => Fifo_full(14), +South => south_2_north(3)(14), East => east_2_west(3)(14) , Grant => Signal_grant(3)(14)); + +Arbiter_3_15 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(2)(15), West => east_2_west(2)(14), P => Signal_priority(27), Fifo_full => Fifo_full(15), +South => south_2_north(3)(15), East => east_2_west(3)(15) , Grant => Signal_grant(3)(15)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(3)(1), West => east_2_west(3)(15), P => Signal_priority(26), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(26), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(26), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(26), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +Arbiter_4_5 : Arbiter + +PORT MAP (Request => Request(215), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(26), Fifo_full => Fifo_full(5), +South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); + +Arbiter_4_6 : Arbiter + +PORT MAP (Request => Request(201), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(26), Fifo_full => Fifo_full(6), +South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); + +Arbiter_4_7 : Arbiter + +PORT MAP (Request => Request(187), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(26), Fifo_full => Fifo_full(7), +South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); + +Arbiter_4_8 : Arbiter + +PORT MAP (Request => Request(173), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(26), Fifo_full => Fifo_full(8), +South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); + +Arbiter_4_9 : Arbiter + +PORT MAP (Request => Request(159), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(26), Fifo_full => Fifo_full(9), +South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); + +Arbiter_4_10 : Arbiter + +PORT MAP (Request => Request(145), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(26), Fifo_full => Fifo_full(10), +South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); + +Arbiter_4_11 : Arbiter + +PORT MAP (Request => Request(131), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(26), Fifo_full => Fifo_full(11), +South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); + +Arbiter_4_12 : Arbiter + +PORT MAP (Request => Request(117), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(26), Fifo_full => Fifo_full(12), +South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); + +Arbiter_4_13 : Arbiter + +PORT MAP (Request => Request(103), North => south_2_north(3)(13), West => east_2_west(3)(12), P => Signal_priority(26), Fifo_full => Fifo_full(13), +South => south_2_north(4)(13), East => east_2_west(4)(13) , Grant => Signal_grant(4)(13)); + +Arbiter_4_14 : Arbiter + +PORT MAP (Request => Request(89), North => south_2_north(3)(14), West => east_2_west(3)(13), P => Signal_priority(26), Fifo_full => Fifo_full(14), +South => south_2_north(4)(14), East => east_2_west(4)(14) , Grant => Signal_grant(4)(14)); + +Arbiter_4_15 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(3)(15), West => east_2_west(3)(14), P => Signal_priority(26), Fifo_full => Fifo_full(15), +South => south_2_north(4)(15), East => east_2_west(4)(15) , Grant => Signal_grant(4)(15)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(4)(1), West => east_2_west(4)(15), P => Signal_priority(25), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(25), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(25), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(25), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +Arbiter_5_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(25), Fifo_full => Fifo_full(5), +South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); + +Arbiter_5_6 : Arbiter + +PORT MAP (Request => Request(216), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(25), Fifo_full => Fifo_full(6), +South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); + +Arbiter_5_7 : Arbiter + +PORT MAP (Request => Request(202), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(25), Fifo_full => Fifo_full(7), +South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); + +Arbiter_5_8 : Arbiter + +PORT MAP (Request => Request(188), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(25), Fifo_full => Fifo_full(8), +South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); + +Arbiter_5_9 : Arbiter + +PORT MAP (Request => Request(174), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(25), Fifo_full => Fifo_full(9), +South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); + +Arbiter_5_10 : Arbiter + +PORT MAP (Request => Request(160), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(25), Fifo_full => Fifo_full(10), +South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); + +Arbiter_5_11 : Arbiter + +PORT MAP (Request => Request(146), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(25), Fifo_full => Fifo_full(11), +South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); + +Arbiter_5_12 : Arbiter + +PORT MAP (Request => Request(132), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(25), Fifo_full => Fifo_full(12), +South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); + +Arbiter_5_13 : Arbiter + +PORT MAP (Request => Request(118), North => south_2_north(4)(13), West => east_2_west(4)(12), P => Signal_priority(25), Fifo_full => Fifo_full(13), +South => south_2_north(5)(13), East => east_2_west(5)(13) , Grant => Signal_grant(5)(13)); + +Arbiter_5_14 : Arbiter + +PORT MAP (Request => Request(104), North => south_2_north(4)(14), West => east_2_west(4)(13), P => Signal_priority(25), Fifo_full => Fifo_full(14), +South => south_2_north(5)(14), East => east_2_west(5)(14) , Grant => Signal_grant(5)(14)); + +Arbiter_5_15 : Arbiter + +PORT MAP (Request => Request(90), North => south_2_north(4)(15), West => east_2_west(4)(14), P => Signal_priority(25), Fifo_full => Fifo_full(15), +South => south_2_north(5)(15), East => east_2_west(5)(15) , Grant => Signal_grant(5)(15)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(5)(1), West => east_2_west(5)(15), P => Signal_priority(24), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(24), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(24), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(24), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +Arbiter_6_5 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(24), Fifo_full => Fifo_full(5), +South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); + +Arbiter_6_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(24), Fifo_full => Fifo_full(6), +South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); + +Arbiter_6_7 : Arbiter + +PORT MAP (Request => Request(217), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(24), Fifo_full => Fifo_full(7), +South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); + +Arbiter_6_8 : Arbiter + +PORT MAP (Request => Request(203), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(24), Fifo_full => Fifo_full(8), +South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); + +Arbiter_6_9 : Arbiter + +PORT MAP (Request => Request(189), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(24), Fifo_full => Fifo_full(9), +South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); + +Arbiter_6_10 : Arbiter + +PORT MAP (Request => Request(175), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(24), Fifo_full => Fifo_full(10), +South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); + +Arbiter_6_11 : Arbiter + +PORT MAP (Request => Request(161), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(24), Fifo_full => Fifo_full(11), +South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); + +Arbiter_6_12 : Arbiter + +PORT MAP (Request => Request(147), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(24), Fifo_full => Fifo_full(12), +South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); + +Arbiter_6_13 : Arbiter + +PORT MAP (Request => Request(133), North => south_2_north(5)(13), West => east_2_west(5)(12), P => Signal_priority(24), Fifo_full => Fifo_full(13), +South => south_2_north(6)(13), East => east_2_west(6)(13) , Grant => Signal_grant(6)(13)); + +Arbiter_6_14 : Arbiter + +PORT MAP (Request => Request(119), North => south_2_north(5)(14), West => east_2_west(5)(13), P => Signal_priority(24), Fifo_full => Fifo_full(14), +South => south_2_north(6)(14), East => east_2_west(6)(14) , Grant => Signal_grant(6)(14)); + +Arbiter_6_15 : Arbiter + +PORT MAP (Request => Request(105), North => south_2_north(5)(15), West => east_2_west(5)(14), P => Signal_priority(24), Fifo_full => Fifo_full(15), +South => south_2_north(6)(15), East => east_2_west(6)(15) , Grant => Signal_grant(6)(15)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(91), North => south_2_north(6)(1), West => east_2_west(6)(15), P => Signal_priority(23), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(23), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(23), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(23), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + +Arbiter_7_5 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(23), Fifo_full => Fifo_full(5), +South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); + +Arbiter_7_6 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(23), Fifo_full => Fifo_full(6), +South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); + +Arbiter_7_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(23), Fifo_full => Fifo_full(7), +South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); + +Arbiter_7_8 : Arbiter + +PORT MAP (Request => Request(218), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(23), Fifo_full => Fifo_full(8), +South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); + +Arbiter_7_9 : Arbiter + +PORT MAP (Request => Request(204), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(23), Fifo_full => Fifo_full(9), +South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); + +Arbiter_7_10 : Arbiter + +PORT MAP (Request => Request(190), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(23), Fifo_full => Fifo_full(10), +South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); + +Arbiter_7_11 : Arbiter + +PORT MAP (Request => Request(176), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(23), Fifo_full => Fifo_full(11), +South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); + +Arbiter_7_12 : Arbiter + +PORT MAP (Request => Request(162), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(23), Fifo_full => Fifo_full(12), +South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); + +Arbiter_7_13 : Arbiter + +PORT MAP (Request => Request(148), North => south_2_north(6)(13), West => east_2_west(6)(12), P => Signal_priority(23), Fifo_full => Fifo_full(13), +South => south_2_north(7)(13), East => east_2_west(7)(13) , Grant => Signal_grant(7)(13)); + +Arbiter_7_14 : Arbiter + +PORT MAP (Request => Request(134), North => south_2_north(6)(14), West => east_2_west(6)(13), P => Signal_priority(23), Fifo_full => Fifo_full(14), +South => south_2_north(7)(14), East => east_2_west(7)(14) , Grant => Signal_grant(7)(14)); + +Arbiter_7_15 : Arbiter + +PORT MAP (Request => Request(120), North => south_2_north(6)(15), West => east_2_west(6)(14), P => Signal_priority(23), Fifo_full => Fifo_full(15), +South => south_2_north(7)(15), East => east_2_west(7)(15) , Grant => Signal_grant(7)(15)); + +-------------------------- Diagonale n° 8 + + +Arbiter_8_1 : Arbiter + +PORT MAP (Request => Request(106), North => south_2_north(7)(1), West => east_2_west(7)(15), P => Signal_priority(22), Fifo_full => Fifo_full(1), +South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); + +Arbiter_8_2 : Arbiter + +PORT MAP (Request => Request(92), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2), +South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); + +Arbiter_8_3 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3), +South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); + +Arbiter_8_4 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4), +South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); + +Arbiter_8_5 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5), +South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); + +Arbiter_8_6 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6), +South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); + +Arbiter_8_7 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7), +South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); + +Arbiter_8_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8), +South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); + +Arbiter_8_9 : Arbiter + +PORT MAP (Request => Request(219), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9), +South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); + +Arbiter_8_10 : Arbiter + +PORT MAP (Request => Request(205), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10), +South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); + +Arbiter_8_11 : Arbiter + +PORT MAP (Request => Request(191), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11), +South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); + +Arbiter_8_12 : Arbiter + +PORT MAP (Request => Request(177), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12), +South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); + +Arbiter_8_13 : Arbiter + +PORT MAP (Request => Request(163), North => south_2_north(7)(13), West => east_2_west(7)(12), P => Signal_priority(22), Fifo_full => Fifo_full(13), +South => south_2_north(8)(13), East => east_2_west(8)(13) , Grant => Signal_grant(8)(13)); + +Arbiter_8_14 : Arbiter + +PORT MAP (Request => Request(149), North => south_2_north(7)(14), West => east_2_west(7)(13), P => Signal_priority(22), Fifo_full => Fifo_full(14), +South => south_2_north(8)(14), East => east_2_west(8)(14) , Grant => Signal_grant(8)(14)); + +Arbiter_8_15 : Arbiter + +PORT MAP (Request => Request(135), North => south_2_north(7)(15), West => east_2_west(7)(14), P => Signal_priority(22), Fifo_full => Fifo_full(15), +South => south_2_north(8)(15), East => east_2_west(8)(15) , Grant => Signal_grant(8)(15)); + +-------------------------- Diagonale n° 9 + + +Arbiter_9_1 : Arbiter + +PORT MAP (Request => Request(121), North => south_2_north(8)(1), West => east_2_west(8)(15), P => Signal_priority(21), Fifo_full => Fifo_full(1), +South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); + +Arbiter_9_2 : Arbiter + +PORT MAP (Request => Request(107), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2), +South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); + +Arbiter_9_3 : Arbiter + +PORT MAP (Request => Request(93), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3), +South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); + +Arbiter_9_4 : Arbiter + +PORT MAP (Request => Request(79), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4), +South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); + +Arbiter_9_5 : Arbiter + +PORT MAP (Request => Request(65), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5), +South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); + +Arbiter_9_6 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6), +South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); + +Arbiter_9_7 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7), +South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); + +Arbiter_9_8 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8), +South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); + +Arbiter_9_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9), +South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); + +Arbiter_9_10 : Arbiter + +PORT MAP (Request => Request(220), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10), +South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); + +Arbiter_9_11 : Arbiter + +PORT MAP (Request => Request(206), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11), +South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); + +Arbiter_9_12 : Arbiter + +PORT MAP (Request => Request(192), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12), +South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); + +Arbiter_9_13 : Arbiter + +PORT MAP (Request => Request(178), North => south_2_north(8)(13), West => east_2_west(8)(12), P => Signal_priority(21), Fifo_full => Fifo_full(13), +South => south_2_north(9)(13), East => east_2_west(9)(13) , Grant => Signal_grant(9)(13)); + +Arbiter_9_14 : Arbiter + +PORT MAP (Request => Request(164), North => south_2_north(8)(14), West => east_2_west(8)(13), P => Signal_priority(21), Fifo_full => Fifo_full(14), +South => south_2_north(9)(14), East => east_2_west(9)(14) , Grant => Signal_grant(9)(14)); + +Arbiter_9_15 : Arbiter + +PORT MAP (Request => Request(150), North => south_2_north(8)(15), West => east_2_west(8)(14), P => Signal_priority(21), Fifo_full => Fifo_full(15), +South => south_2_north(9)(15), East => east_2_west(9)(15) , Grant => Signal_grant(9)(15)); + +-------------------------- Diagonale n° 10 + + +Arbiter_10_1 : Arbiter + +PORT MAP (Request => Request(136), North => south_2_north(9)(1), West => east_2_west(9)(15), P => Signal_priority(20), Fifo_full => Fifo_full(1), +South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); + +Arbiter_10_2 : Arbiter + +PORT MAP (Request => Request(122), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2), +South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); + +Arbiter_10_3 : Arbiter + +PORT MAP (Request => Request(108), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3), +South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); + +Arbiter_10_4 : Arbiter + +PORT MAP (Request => Request(94), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4), +South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); + +Arbiter_10_5 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5), +South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); + +Arbiter_10_6 : Arbiter + +PORT MAP (Request => Request(66), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6), +South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); + +Arbiter_10_7 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7), +South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); + +Arbiter_10_8 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8), +South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); + +Arbiter_10_9 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9), +South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); + +Arbiter_10_10 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10), +South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); + +Arbiter_10_11 : Arbiter + +PORT MAP (Request => Request(221), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11), +South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); + +Arbiter_10_12 : Arbiter + +PORT MAP (Request => Request(207), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12), +South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); + +Arbiter_10_13 : Arbiter + +PORT MAP (Request => Request(193), North => south_2_north(9)(13), West => east_2_west(9)(12), P => Signal_priority(20), Fifo_full => Fifo_full(13), +South => south_2_north(10)(13), East => east_2_west(10)(13) , Grant => Signal_grant(10)(13)); + +Arbiter_10_14 : Arbiter + +PORT MAP (Request => Request(179), North => south_2_north(9)(14), West => east_2_west(9)(13), P => Signal_priority(20), Fifo_full => Fifo_full(14), +South => south_2_north(10)(14), East => east_2_west(10)(14) , Grant => Signal_grant(10)(14)); + +Arbiter_10_15 : Arbiter + +PORT MAP (Request => Request(165), North => south_2_north(9)(15), West => east_2_west(9)(14), P => Signal_priority(20), Fifo_full => Fifo_full(15), +South => south_2_north(10)(15), East => east_2_west(10)(15) , Grant => Signal_grant(10)(15)); + +-------------------------- Diagonale n° 11 + + +Arbiter_11_1 : Arbiter + +PORT MAP (Request => Request(151), North => south_2_north(10)(1), West => east_2_west(10)(15), P => Signal_priority(19), Fifo_full => Fifo_full(1), +South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); + +Arbiter_11_2 : Arbiter + +PORT MAP (Request => Request(137), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2), +South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); + +Arbiter_11_3 : Arbiter + +PORT MAP (Request => Request(123), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3), +South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); + +Arbiter_11_4 : Arbiter + +PORT MAP (Request => Request(109), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4), +South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); + +Arbiter_11_5 : Arbiter + +PORT MAP (Request => Request(95), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5), +South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); + +Arbiter_11_6 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6), +South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); + +Arbiter_11_7 : Arbiter + +PORT MAP (Request => Request(67), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7), +South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); + +Arbiter_11_8 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8), +South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); + +Arbiter_11_9 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9), +South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); + +Arbiter_11_10 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10), +South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); + +Arbiter_11_11 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11), +South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); + +Arbiter_11_12 : Arbiter + +PORT MAP (Request => Request(222), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12), +South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); + +Arbiter_11_13 : Arbiter + +PORT MAP (Request => Request(208), North => south_2_north(10)(13), West => east_2_west(10)(12), P => Signal_priority(19), Fifo_full => Fifo_full(13), +South => south_2_north(11)(13), East => east_2_west(11)(13) , Grant => Signal_grant(11)(13)); + +Arbiter_11_14 : Arbiter + +PORT MAP (Request => Request(194), North => south_2_north(10)(14), West => east_2_west(10)(13), P => Signal_priority(19), Fifo_full => Fifo_full(14), +South => south_2_north(11)(14), East => east_2_west(11)(14) , Grant => Signal_grant(11)(14)); + +Arbiter_11_15 : Arbiter + +PORT MAP (Request => Request(180), North => south_2_north(10)(15), West => east_2_west(10)(14), P => Signal_priority(19), Fifo_full => Fifo_full(15), +South => south_2_north(11)(15), East => east_2_west(11)(15) , Grant => Signal_grant(11)(15)); + +-------------------------- Diagonale n° 12 + + +Arbiter_12_1 : Arbiter + +PORT MAP (Request => Request(166), North => south_2_north(11)(1), West => east_2_west(11)(15), P => Signal_priority(18), Fifo_full => Fifo_full(1), +South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); + +Arbiter_12_2 : Arbiter + +PORT MAP (Request => Request(152), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2), +South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); + +Arbiter_12_3 : Arbiter + +PORT MAP (Request => Request(138), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3), +South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); + +Arbiter_12_4 : Arbiter + +PORT MAP (Request => Request(124), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4), +South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); + +Arbiter_12_5 : Arbiter + +PORT MAP (Request => Request(110), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5), +South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); + +Arbiter_12_6 : Arbiter + +PORT MAP (Request => Request(96), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6), +South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); + +Arbiter_12_7 : Arbiter + +PORT MAP (Request => Request(82), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7), +South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); + +Arbiter_12_8 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8), +South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); + +Arbiter_12_9 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9), +South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); + +Arbiter_12_10 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10), +South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); + +Arbiter_12_11 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11), +South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); + +Arbiter_12_12 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12), +South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); + +Arbiter_12_13 : Arbiter + +PORT MAP (Request => Request(223), North => south_2_north(11)(13), West => east_2_west(11)(12), P => Signal_priority(18), Fifo_full => Fifo_full(13), +South => south_2_north(12)(13), East => east_2_west(12)(13) , Grant => Signal_grant(12)(13)); + +Arbiter_12_14 : Arbiter + +PORT MAP (Request => Request(209), North => south_2_north(11)(14), West => east_2_west(11)(13), P => Signal_priority(18), Fifo_full => Fifo_full(14), +South => south_2_north(12)(14), East => east_2_west(12)(14) , Grant => Signal_grant(12)(14)); + +Arbiter_12_15 : Arbiter + +PORT MAP (Request => Request(195), North => south_2_north(11)(15), West => east_2_west(11)(14), P => Signal_priority(18), Fifo_full => Fifo_full(15), +South => south_2_north(12)(15), East => east_2_west(12)(15) , Grant => Signal_grant(12)(15)); + +-------------------------- Diagonale n° 13 + + +Arbiter_13_1 : Arbiter + +PORT MAP (Request => Request(181), North => south_2_north(12)(1), West => east_2_west(12)(15), P => Signal_priority(17), Fifo_full => Fifo_full(1), +South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); + +Arbiter_13_2 : Arbiter + +PORT MAP (Request => Request(167), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2), +South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); + +Arbiter_13_3 : Arbiter + +PORT MAP (Request => Request(153), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3), +South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); + +Arbiter_13_4 : Arbiter + +PORT MAP (Request => Request(139), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4), +South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); + +Arbiter_13_5 : Arbiter + +PORT MAP (Request => Request(125), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5), +South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); + +Arbiter_13_6 : Arbiter + +PORT MAP (Request => Request(111), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6), +South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); + +Arbiter_13_7 : Arbiter + +PORT MAP (Request => Request(97), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7), +South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); + +Arbiter_13_8 : Arbiter + +PORT MAP (Request => Request(83), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8), +South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); + +Arbiter_13_9 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9), +South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); + +Arbiter_13_10 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10), +South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); + +Arbiter_13_11 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11), +South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); + +Arbiter_13_12 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12), +South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); + +Arbiter_13_13 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(12)(13), West => east_2_west(12)(12), P => Signal_priority(17), Fifo_full => Fifo_full(13), +South => south_2_north(13)(13), East => east_2_west(13)(13) , Grant => Signal_grant(13)(13)); + +Arbiter_13_14 : Arbiter + +PORT MAP (Request => Request(224), North => south_2_north(12)(14), West => east_2_west(12)(13), P => Signal_priority(17), Fifo_full => Fifo_full(14), +South => south_2_north(13)(14), East => east_2_west(13)(14) , Grant => Signal_grant(13)(14)); + +Arbiter_13_15 : Arbiter + +PORT MAP (Request => Request(210), North => south_2_north(12)(15), West => east_2_west(12)(14), P => Signal_priority(17), Fifo_full => Fifo_full(15), +South => south_2_north(13)(15), East => east_2_west(13)(15) , Grant => Signal_grant(13)(15)); + +-------------------------- Diagonale n° 14 + + +Arbiter_14_1 : Arbiter + +PORT MAP (Request => Request(196), North => south_2_north(13)(1), West => east_2_west(13)(15), P => Signal_priority(16), Fifo_full => Fifo_full(1), +South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); + +Arbiter_14_2 : Arbiter + +PORT MAP (Request => Request(182), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2), +South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); + +Arbiter_14_3 : Arbiter + +PORT MAP (Request => Request(168), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3), +South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); + +Arbiter_14_4 : Arbiter + +PORT MAP (Request => Request(154), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4), +South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); + +Arbiter_14_5 : Arbiter + +PORT MAP (Request => Request(140), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5), +South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); + +Arbiter_14_6 : Arbiter + +PORT MAP (Request => Request(126), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6), +South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); + +Arbiter_14_7 : Arbiter + +PORT MAP (Request => Request(112), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7), +South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); + +Arbiter_14_8 : Arbiter + +PORT MAP (Request => Request(98), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8), +South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); + +Arbiter_14_9 : Arbiter + +PORT MAP (Request => Request(84), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9), +South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); + +Arbiter_14_10 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10), +South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); + +Arbiter_14_11 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11), +South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); + +Arbiter_14_12 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12), +South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); + +Arbiter_14_13 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(13)(13), West => east_2_west(13)(12), P => Signal_priority(16), Fifo_full => Fifo_full(13), +South => south_2_north(14)(13), East => east_2_west(14)(13) , Grant => Signal_grant(14)(13)); + +Arbiter_14_14 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(13)(14), West => east_2_west(13)(13), P => Signal_priority(16), Fifo_full => Fifo_full(14), +South => south_2_north(14)(14), East => east_2_west(14)(14) , Grant => Signal_grant(14)(14)); + +Arbiter_14_15 : Arbiter + +PORT MAP (Request => Request(225), North => south_2_north(13)(15), West => east_2_west(13)(14), P => Signal_priority(16), Fifo_full => Fifo_full(15), +South => south_2_north(14)(15), East => east_2_west(14)(15) , Grant => Signal_grant(14)(15)); + +-------------------------- Diagonale n° 15 + + +Arbiter_15_1 : Arbiter + +PORT MAP (Request => Request(211), North => south_2_north(14)(1), West => east_2_west(14)(15), P => Signal_priority(15), Fifo_full => Fifo_full(1), +South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); + +Arbiter_15_2 : Arbiter + +PORT MAP (Request => Request(197), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2), +South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); + +Arbiter_15_3 : Arbiter + +PORT MAP (Request => Request(183), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3), +South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); + +Arbiter_15_4 : Arbiter + +PORT MAP (Request => Request(169), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4), +South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); + +Arbiter_15_5 : Arbiter + +PORT MAP (Request => Request(155), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5), +South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); + +Arbiter_15_6 : Arbiter + +PORT MAP (Request => Request(141), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6), +South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); + +Arbiter_15_7 : Arbiter + +PORT MAP (Request => Request(127), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7), +South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); + +Arbiter_15_8 : Arbiter + +PORT MAP (Request => Request(113), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8), +South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); + +Arbiter_15_9 : Arbiter + +PORT MAP (Request => Request(99), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9), +South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); + +Arbiter_15_10 : Arbiter + +PORT MAP (Request => Request(85), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10), +South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); + +Arbiter_15_11 : Arbiter + +PORT MAP (Request => Request(71), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11), +South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); + +Arbiter_15_12 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12), +South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); + +Arbiter_15_13 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(14)(13), West => east_2_west(14)(12), P => Signal_priority(15), Fifo_full => Fifo_full(13), +South => south_2_north(15)(13), East => east_2_west(15)(13) , Grant => Signal_grant(15)(13)); + +Arbiter_15_14 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(14)(14), West => east_2_west(14)(13), P => Signal_priority(15), Fifo_full => Fifo_full(14), +South => south_2_north(15)(14), East => east_2_west(15)(14) , Grant => Signal_grant(15)(14)); + +Arbiter_15_15 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(14)(15), West => east_2_west(14)(14), P => Signal_priority(15), Fifo_full => Fifo_full(15), +South => south_2_north(15)(15), East => east_2_west(15)(15) , Grant => Signal_grant(15)(15)); + +-------------------------- Diagonale n° 16 + + +Arbiter_16_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(15)(1), West => east_2_west(15)(15), P => Signal_priority(14), Fifo_full => Fifo_full(1), +South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); + +Arbiter_16_2 : Arbiter + +PORT MAP (Request => Request(212), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2), +South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); + +Arbiter_16_3 : Arbiter + +PORT MAP (Request => Request(198), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3), +South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); + +Arbiter_16_4 : Arbiter + +PORT MAP (Request => Request(184), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4), +South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); + +Arbiter_16_5 : Arbiter + +PORT MAP (Request => Request(170), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5), +South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); + +Arbiter_16_6 : Arbiter + +PORT MAP (Request => Request(156), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6), +South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); + +Arbiter_16_7 : Arbiter + +PORT MAP (Request => Request(142), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7), +South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); + +Arbiter_16_8 : Arbiter + +PORT MAP (Request => Request(128), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8), +South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); + +Arbiter_16_9 : Arbiter + +PORT MAP (Request => Request(114), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9), +South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); + +Arbiter_16_10 : Arbiter + +PORT MAP (Request => Request(100), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10), +South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); + +Arbiter_16_11 : Arbiter + +PORT MAP (Request => Request(86), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11), +South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); + +Arbiter_16_12 : Arbiter + +PORT MAP (Request => Request(72), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12), +South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); + +Arbiter_16_13 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(15)(13), West => east_2_west(15)(12), P => Signal_priority(14), Fifo_full => Fifo_full(13), +South => south_2_north(16)(13), East => east_2_west(16)(13) , Grant => Signal_grant(16)(13)); + +Arbiter_16_14 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(15)(14), West => east_2_west(15)(13), P => Signal_priority(14), Fifo_full => Fifo_full(14), +South => south_2_north(16)(14), East => east_2_west(16)(14) , Grant => Signal_grant(16)(14)); + +Arbiter_16_15 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(15)(15), West => east_2_west(15)(14), P => Signal_priority(14), Fifo_full => Fifo_full(15), +South => south_2_north(16)(15), East => east_2_west(16)(15) , Grant => Signal_grant(16)(15)); + +-------------------------- Diagonale n° 17 + + +Arbiter_17_1 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(16)(1), West => east_2_west(16)(15), P => Signal_priority(13), Fifo_full => Fifo_full(1), +South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); + +Arbiter_17_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2), +South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); + +Arbiter_17_3 : Arbiter + +PORT MAP (Request => Request(213), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3), +South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); + +Arbiter_17_4 : Arbiter + +PORT MAP (Request => Request(199), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4), +South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); + +Arbiter_17_5 : Arbiter + +PORT MAP (Request => Request(185), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5), +South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); + +Arbiter_17_6 : Arbiter + +PORT MAP (Request => Request(171), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6), +South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); + +Arbiter_17_7 : Arbiter + +PORT MAP (Request => Request(157), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7), +South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); + +Arbiter_17_8 : Arbiter + +PORT MAP (Request => Request(143), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8), +South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); + +Arbiter_17_9 : Arbiter + +PORT MAP (Request => Request(129), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9), +South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); + +Arbiter_17_10 : Arbiter + +PORT MAP (Request => Request(115), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10), +South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); + +Arbiter_17_11 : Arbiter + +PORT MAP (Request => Request(101), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11), +South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); + +Arbiter_17_12 : Arbiter + +PORT MAP (Request => Request(87), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12), +South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); + +Arbiter_17_13 : Arbiter + +PORT MAP (Request => Request(73), North => south_2_north(16)(13), West => east_2_west(16)(12), P => Signal_priority(13), Fifo_full => Fifo_full(13), +South => south_2_north(17)(13), East => east_2_west(17)(13) , Grant => Signal_grant(17)(13)); + +Arbiter_17_14 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(16)(14), West => east_2_west(16)(13), P => Signal_priority(13), Fifo_full => Fifo_full(14), +South => south_2_north(17)(14), East => east_2_west(17)(14) , Grant => Signal_grant(17)(14)); + +Arbiter_17_15 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(16)(15), West => east_2_west(16)(14), P => Signal_priority(13), Fifo_full => Fifo_full(15), +South => south_2_north(17)(15), East => east_2_west(17)(15) , Grant => Signal_grant(17)(15)); + +-------------------------- Diagonale n° 18 + + +Arbiter_18_1 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(17)(1), West => east_2_west(17)(15), P => Signal_priority(12), Fifo_full => Fifo_full(1), +South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); + +Arbiter_18_2 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2), +South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); + +Arbiter_18_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3), +South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); + +Arbiter_18_4 : Arbiter + +PORT MAP (Request => Request(214), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4), +South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); + +Arbiter_18_5 : Arbiter + +PORT MAP (Request => Request(200), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5), +South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); + +Arbiter_18_6 : Arbiter + +PORT MAP (Request => Request(186), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6), +South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); + +Arbiter_18_7 : Arbiter + +PORT MAP (Request => Request(172), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7), +South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); + +Arbiter_18_8 : Arbiter + +PORT MAP (Request => Request(158), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8), +South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); + +Arbiter_18_9 : Arbiter + +PORT MAP (Request => Request(144), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9), +South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); + +Arbiter_18_10 : Arbiter + +PORT MAP (Request => Request(130), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10), +South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); + +Arbiter_18_11 : Arbiter + +PORT MAP (Request => Request(116), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11), +South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); + +Arbiter_18_12 : Arbiter + +PORT MAP (Request => Request(102), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12), +South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); + +Arbiter_18_13 : Arbiter + +PORT MAP (Request => Request(88), North => south_2_north(17)(13), West => east_2_west(17)(12), P => Signal_priority(12), Fifo_full => Fifo_full(13), +South => south_2_north(18)(13), East => east_2_west(18)(13) , Grant => Signal_grant(18)(13)); + +Arbiter_18_14 : Arbiter + +PORT MAP (Request => Request(74), North => south_2_north(17)(14), West => east_2_west(17)(13), P => Signal_priority(12), Fifo_full => Fifo_full(14), +South => south_2_north(18)(14), East => east_2_west(18)(14) , Grant => Signal_grant(18)(14)); + +Arbiter_18_15 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(17)(15), West => east_2_west(17)(14), P => Signal_priority(12), Fifo_full => Fifo_full(15), +South => south_2_north(18)(15), East => east_2_west(18)(15) , Grant => Signal_grant(18)(15)); + +-------------------------- Diagonale n° 19 + + +Arbiter_19_1 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(18)(1), West => east_2_west(18)(15), P => Signal_priority(11), Fifo_full => Fifo_full(1), +South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); + +Arbiter_19_2 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2), +South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); + +Arbiter_19_3 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3), +South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); + +Arbiter_19_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4), +South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); + +Arbiter_19_5 : Arbiter + +PORT MAP (Request => Request(215), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5), +South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); + +Arbiter_19_6 : Arbiter + +PORT MAP (Request => Request(201), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6), +South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); + +Arbiter_19_7 : Arbiter + +PORT MAP (Request => Request(187), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7), +South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); + +Arbiter_19_8 : Arbiter + +PORT MAP (Request => Request(173), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8), +South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); + +Arbiter_19_9 : Arbiter + +PORT MAP (Request => Request(159), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9), +South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); + +Arbiter_19_10 : Arbiter + +PORT MAP (Request => Request(145), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10), +South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); + +Arbiter_19_11 : Arbiter + +PORT MAP (Request => Request(131), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11), +South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); + +Arbiter_19_12 : Arbiter + +PORT MAP (Request => Request(117), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12), +South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); + +Arbiter_19_13 : Arbiter + +PORT MAP (Request => Request(103), North => south_2_north(18)(13), West => east_2_west(18)(12), P => Signal_priority(11), Fifo_full => Fifo_full(13), +South => south_2_north(19)(13), East => east_2_west(19)(13) , Grant => Signal_grant(19)(13)); + +Arbiter_19_14 : Arbiter + +PORT MAP (Request => Request(89), North => south_2_north(18)(14), West => east_2_west(18)(13), P => Signal_priority(11), Fifo_full => Fifo_full(14), +South => south_2_north(19)(14), East => east_2_west(19)(14) , Grant => Signal_grant(19)(14)); + +Arbiter_19_15 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(18)(15), West => east_2_west(18)(14), P => Signal_priority(11), Fifo_full => Fifo_full(15), +South => south_2_north(19)(15), East => east_2_west(19)(15) , Grant => Signal_grant(19)(15)); + +-------------------------- Diagonale n° 20 + + +Arbiter_20_1 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(19)(1), West => east_2_west(19)(15), P => Signal_priority(10), Fifo_full => Fifo_full(1), +South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); + +Arbiter_20_2 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2), +South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); + +Arbiter_20_3 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3), +South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); + +Arbiter_20_4 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4), +South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); + +Arbiter_20_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5), +South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); + +Arbiter_20_6 : Arbiter + +PORT MAP (Request => Request(216), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6), +South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); + +Arbiter_20_7 : Arbiter + +PORT MAP (Request => Request(202), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7), +South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); + +Arbiter_20_8 : Arbiter + +PORT MAP (Request => Request(188), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8), +South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); + +Arbiter_20_9 : Arbiter + +PORT MAP (Request => Request(174), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9), +South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); + +Arbiter_20_10 : Arbiter + +PORT MAP (Request => Request(160), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10), +South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); + +Arbiter_20_11 : Arbiter + +PORT MAP (Request => Request(146), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11), +South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); + +Arbiter_20_12 : Arbiter + +PORT MAP (Request => Request(132), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12), +South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); + +Arbiter_20_13 : Arbiter + +PORT MAP (Request => Request(118), North => south_2_north(19)(13), West => east_2_west(19)(12), P => Signal_priority(10), Fifo_full => Fifo_full(13), +South => south_2_north(20)(13), East => east_2_west(20)(13) , Grant => Signal_grant(20)(13)); + +Arbiter_20_14 : Arbiter + +PORT MAP (Request => Request(104), North => south_2_north(19)(14), West => east_2_west(19)(13), P => Signal_priority(10), Fifo_full => Fifo_full(14), +South => south_2_north(20)(14), East => east_2_west(20)(14) , Grant => Signal_grant(20)(14)); + +Arbiter_20_15 : Arbiter + +PORT MAP (Request => Request(90), North => south_2_north(19)(15), West => east_2_west(19)(14), P => Signal_priority(10), Fifo_full => Fifo_full(15), +South => south_2_north(20)(15), East => east_2_west(20)(15) , Grant => Signal_grant(20)(15)); + +-------------------------- Diagonale n° 21 + + +Arbiter_21_1 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(20)(1), West => east_2_west(20)(15), P => Signal_priority(9), Fifo_full => Fifo_full(1), +South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); + +Arbiter_21_2 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2), +South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); + +Arbiter_21_3 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3), +South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); + +Arbiter_21_4 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4), +South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); + +Arbiter_21_5 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5), +South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); + +Arbiter_21_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6), +South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); + +Arbiter_21_7 : Arbiter + +PORT MAP (Request => Request(217), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7), +South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); + +Arbiter_21_8 : Arbiter + +PORT MAP (Request => Request(203), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8), +South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); + +Arbiter_21_9 : Arbiter + +PORT MAP (Request => Request(189), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9), +South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); + +Arbiter_21_10 : Arbiter + +PORT MAP (Request => Request(175), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10), +South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); + +Arbiter_21_11 : Arbiter + +PORT MAP (Request => Request(161), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11), +South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); + +Arbiter_21_12 : Arbiter + +PORT MAP (Request => Request(147), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12), +South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); + +Arbiter_21_13 : Arbiter + +PORT MAP (Request => Request(133), North => south_2_north(20)(13), West => east_2_west(20)(12), P => Signal_priority(9), Fifo_full => Fifo_full(13), +South => south_2_north(21)(13), East => east_2_west(21)(13) , Grant => Signal_grant(21)(13)); + +Arbiter_21_14 : Arbiter + +PORT MAP (Request => Request(119), North => south_2_north(20)(14), West => east_2_west(20)(13), P => Signal_priority(9), Fifo_full => Fifo_full(14), +South => south_2_north(21)(14), East => east_2_west(21)(14) , Grant => Signal_grant(21)(14)); + +Arbiter_21_15 : Arbiter + +PORT MAP (Request => Request(105), North => south_2_north(20)(15), West => east_2_west(20)(14), P => Signal_priority(9), Fifo_full => Fifo_full(15), +South => south_2_north(21)(15), East => east_2_west(21)(15) , Grant => Signal_grant(21)(15)); + +-------------------------- Diagonale n° 22 + + +Arbiter_22_1 : Arbiter + +PORT MAP (Request => Request(91), North => south_2_north(21)(1), West => east_2_west(21)(15), P => Signal_priority(8), Fifo_full => Fifo_full(1), +South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); + +Arbiter_22_2 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2), +South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); + +Arbiter_22_3 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3), +South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); + +Arbiter_22_4 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4), +South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); + +Arbiter_22_5 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5), +South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); + +Arbiter_22_6 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6), +South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); + +Arbiter_22_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7), +South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); + +Arbiter_22_8 : Arbiter + +PORT MAP (Request => Request(218), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8), +South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); + +Arbiter_22_9 : Arbiter + +PORT MAP (Request => Request(204), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9), +South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); + +Arbiter_22_10 : Arbiter + +PORT MAP (Request => Request(190), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10), +South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); + +Arbiter_22_11 : Arbiter + +PORT MAP (Request => Request(176), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11), +South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); + +Arbiter_22_12 : Arbiter + +PORT MAP (Request => Request(162), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12), +South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); + +Arbiter_22_13 : Arbiter + +PORT MAP (Request => Request(148), North => south_2_north(21)(13), West => east_2_west(21)(12), P => Signal_priority(8), Fifo_full => Fifo_full(13), +South => south_2_north(22)(13), East => east_2_west(22)(13) , Grant => Signal_grant(22)(13)); + +Arbiter_22_14 : Arbiter + +PORT MAP (Request => Request(134), North => south_2_north(21)(14), West => east_2_west(21)(13), P => Signal_priority(8), Fifo_full => Fifo_full(14), +South => south_2_north(22)(14), East => east_2_west(22)(14) , Grant => Signal_grant(22)(14)); + +Arbiter_22_15 : Arbiter + +PORT MAP (Request => Request(120), North => south_2_north(21)(15), West => east_2_west(21)(14), P => Signal_priority(8), Fifo_full => Fifo_full(15), +South => south_2_north(22)(15), East => east_2_west(22)(15) , Grant => Signal_grant(22)(15)); + +-------------------------- Diagonale n° 23 + + +Arbiter_23_1 : Arbiter + +PORT MAP (Request => Request(106), North => south_2_north(22)(1), West => east_2_west(22)(15), P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); + +Arbiter_23_2 : Arbiter + +PORT MAP (Request => Request(92), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); + +Arbiter_23_3 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); + +Arbiter_23_4 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); + +Arbiter_23_5 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5), +South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); + +Arbiter_23_6 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6), +South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); + +Arbiter_23_7 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7), +South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); + +Arbiter_23_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8), +South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); + +Arbiter_23_9 : Arbiter + +PORT MAP (Request => Request(219), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9), +South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); + +Arbiter_23_10 : Arbiter + +PORT MAP (Request => Request(205), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10), +South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); + +Arbiter_23_11 : Arbiter + +PORT MAP (Request => Request(191), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11), +South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); + +Arbiter_23_12 : Arbiter + +PORT MAP (Request => Request(177), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12), +South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); + +Arbiter_23_13 : Arbiter + +PORT MAP (Request => Request(163), North => south_2_north(22)(13), West => east_2_west(22)(12), P => Signal_priority(7), Fifo_full => Fifo_full(13), +South => south_2_north(23)(13), East => east_2_west(23)(13) , Grant => Signal_grant(23)(13)); + +Arbiter_23_14 : Arbiter + +PORT MAP (Request => Request(149), North => south_2_north(22)(14), West => east_2_west(22)(13), P => Signal_priority(7), Fifo_full => Fifo_full(14), +South => south_2_north(23)(14), East => east_2_west(23)(14) , Grant => Signal_grant(23)(14)); + +Arbiter_23_15 : Arbiter + +PORT MAP (Request => Request(135), North => south_2_north(22)(15), West => east_2_west(22)(14), P => Signal_priority(7), Fifo_full => Fifo_full(15), +South => south_2_north(23)(15), East => east_2_west(23)(15) , Grant => Signal_grant(23)(15)); + +-------------------------- Diagonale n° 24 + + +Arbiter_24_1 : Arbiter + +PORT MAP (Request => Request(121), North => south_2_north(23)(1), West => east_2_west(23)(15), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(24)(1), East => east_2_west(24)(1) , Grant => Signal_grant(24)(1)); + +Arbiter_24_2 : Arbiter + +PORT MAP (Request => Request(107), North => south_2_north(23)(2), West => east_2_west(23)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(24)(2), East => east_2_west(24)(2) , Grant => Signal_grant(24)(2)); + +Arbiter_24_3 : Arbiter + +PORT MAP (Request => Request(93), North => south_2_north(23)(3), West => east_2_west(23)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(24)(3), East => east_2_west(24)(3) , Grant => Signal_grant(24)(3)); + +Arbiter_24_4 : Arbiter + +PORT MAP (Request => Request(79), North => south_2_north(23)(4), West => east_2_west(23)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(24)(4), East => east_2_west(24)(4) , Grant => Signal_grant(24)(4)); + +Arbiter_24_5 : Arbiter + +PORT MAP (Request => Request(65), North => south_2_north(23)(5), West => east_2_west(23)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5), +South => south_2_north(24)(5), East => east_2_west(24)(5) , Grant => Signal_grant(24)(5)); + +Arbiter_24_6 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(23)(6), West => east_2_west(23)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6), +South => south_2_north(24)(6), East => east_2_west(24)(6) , Grant => Signal_grant(24)(6)); + +Arbiter_24_7 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(23)(7), West => east_2_west(23)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7), +South => south_2_north(24)(7), East => east_2_west(24)(7) , Grant => Signal_grant(24)(7)); + +Arbiter_24_8 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(23)(8), West => east_2_west(23)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8), +South => south_2_north(24)(8), East => east_2_west(24)(8) , Grant => Signal_grant(24)(8)); + +Arbiter_24_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(23)(9), West => east_2_west(23)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9), +South => south_2_north(24)(9), East => east_2_west(24)(9) , Grant => Signal_grant(24)(9)); + +Arbiter_24_10 : Arbiter + +PORT MAP (Request => Request(220), North => south_2_north(23)(10), West => east_2_west(23)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10), +South => south_2_north(24)(10), East => east_2_west(24)(10) , Grant => Signal_grant(24)(10)); + +Arbiter_24_11 : Arbiter + +PORT MAP (Request => Request(206), North => south_2_north(23)(11), West => east_2_west(23)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11), +South => south_2_north(24)(11), East => east_2_west(24)(11) , Grant => Signal_grant(24)(11)); + +Arbiter_24_12 : Arbiter + +PORT MAP (Request => Request(192), North => south_2_north(23)(12), West => east_2_west(23)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12), +South => south_2_north(24)(12), East => east_2_west(24)(12) , Grant => Signal_grant(24)(12)); + +Arbiter_24_13 : Arbiter + +PORT MAP (Request => Request(178), North => south_2_north(23)(13), West => east_2_west(23)(12), P => Signal_priority(6), Fifo_full => Fifo_full(13), +South => south_2_north(24)(13), East => east_2_west(24)(13) , Grant => Signal_grant(24)(13)); + +Arbiter_24_14 : Arbiter + +PORT MAP (Request => Request(164), North => south_2_north(23)(14), West => east_2_west(23)(13), P => Signal_priority(6), Fifo_full => Fifo_full(14), +South => south_2_north(24)(14), East => east_2_west(24)(14) , Grant => Signal_grant(24)(14)); + +Arbiter_24_15 : Arbiter + +PORT MAP (Request => Request(150), North => south_2_north(23)(15), West => east_2_west(23)(14), P => Signal_priority(6), Fifo_full => Fifo_full(15), +South => south_2_north(24)(15), East => east_2_west(24)(15) , Grant => Signal_grant(24)(15)); + +-------------------------- Diagonale n° 25 + + +Arbiter_25_1 : Arbiter + +PORT MAP (Request => Request(136), North => south_2_north(24)(1), West => east_2_west(24)(15), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(25)(1), East => east_2_west(25)(1) , Grant => Signal_grant(25)(1)); + +Arbiter_25_2 : Arbiter + +PORT MAP (Request => Request(122), North => south_2_north(24)(2), West => east_2_west(24)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(25)(2), East => east_2_west(25)(2) , Grant => Signal_grant(25)(2)); + +Arbiter_25_3 : Arbiter + +PORT MAP (Request => Request(108), North => south_2_north(24)(3), West => east_2_west(24)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(25)(3), East => east_2_west(25)(3) , Grant => Signal_grant(25)(3)); + +Arbiter_25_4 : Arbiter + +PORT MAP (Request => Request(94), North => south_2_north(24)(4), West => east_2_west(24)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(25)(4), East => east_2_west(25)(4) , Grant => Signal_grant(25)(4)); + +Arbiter_25_5 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(24)(5), West => east_2_west(24)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5), +South => south_2_north(25)(5), East => east_2_west(25)(5) , Grant => Signal_grant(25)(5)); + +Arbiter_25_6 : Arbiter + +PORT MAP (Request => Request(66), North => south_2_north(24)(6), West => east_2_west(24)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6), +South => south_2_north(25)(6), East => east_2_west(25)(6) , Grant => Signal_grant(25)(6)); + +Arbiter_25_7 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(24)(7), West => east_2_west(24)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7), +South => south_2_north(25)(7), East => east_2_west(25)(7) , Grant => Signal_grant(25)(7)); + +Arbiter_25_8 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(24)(8), West => east_2_west(24)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8), +South => south_2_north(25)(8), East => east_2_west(25)(8) , Grant => Signal_grant(25)(8)); + +Arbiter_25_9 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(24)(9), West => east_2_west(24)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9), +South => south_2_north(25)(9), East => east_2_west(25)(9) , Grant => Signal_grant(25)(9)); + +Arbiter_25_10 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(24)(10), West => east_2_west(24)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10), +South => south_2_north(25)(10), East => east_2_west(25)(10) , Grant => Signal_grant(25)(10)); + +Arbiter_25_11 : Arbiter + +PORT MAP (Request => Request(221), North => south_2_north(24)(11), West => east_2_west(24)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11), +South => south_2_north(25)(11), East => east_2_west(25)(11) , Grant => Signal_grant(25)(11)); + +Arbiter_25_12 : Arbiter + +PORT MAP (Request => Request(207), North => south_2_north(24)(12), West => east_2_west(24)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12), +South => south_2_north(25)(12), East => east_2_west(25)(12) , Grant => Signal_grant(25)(12)); + +Arbiter_25_13 : Arbiter + +PORT MAP (Request => Request(193), North => south_2_north(24)(13), West => east_2_west(24)(12), P => Signal_priority(5), Fifo_full => Fifo_full(13), +South => south_2_north(25)(13), East => east_2_west(25)(13) , Grant => Signal_grant(25)(13)); + +Arbiter_25_14 : Arbiter + +PORT MAP (Request => Request(179), North => south_2_north(24)(14), West => east_2_west(24)(13), P => Signal_priority(5), Fifo_full => Fifo_full(14), +South => south_2_north(25)(14), East => east_2_west(25)(14) , Grant => Signal_grant(25)(14)); + +Arbiter_25_15 : Arbiter + +PORT MAP (Request => Request(165), North => south_2_north(24)(15), West => east_2_west(24)(14), P => Signal_priority(5), Fifo_full => Fifo_full(15), +South => south_2_north(25)(15), East => east_2_west(25)(15) , Grant => Signal_grant(25)(15)); + +-------------------------- Diagonale n° 26 + + +Arbiter_26_1 : Arbiter + +PORT MAP (Request => Request(151), North => south_2_north(25)(1), West => east_2_west(25)(15), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(26)(1), East => east_2_west(26)(1) , Grant => Signal_grant(26)(1)); + +Arbiter_26_2 : Arbiter + +PORT MAP (Request => Request(137), North => south_2_north(25)(2), West => east_2_west(25)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(26)(2), East => east_2_west(26)(2) , Grant => Signal_grant(26)(2)); + +Arbiter_26_3 : Arbiter + +PORT MAP (Request => Request(123), North => south_2_north(25)(3), West => east_2_west(25)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(26)(3), East => east_2_west(26)(3) , Grant => Signal_grant(26)(3)); + +Arbiter_26_4 : Arbiter + +PORT MAP (Request => Request(109), North => south_2_north(25)(4), West => east_2_west(25)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(26)(4), East => east_2_west(26)(4) , Grant => Signal_grant(26)(4)); + +Arbiter_26_5 : Arbiter + +PORT MAP (Request => Request(95), North => south_2_north(25)(5), West => east_2_west(25)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5), +South => south_2_north(26)(5), East => east_2_west(26)(5) , Grant => Signal_grant(26)(5)); + +Arbiter_26_6 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(25)(6), West => east_2_west(25)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6), +South => south_2_north(26)(6), East => east_2_west(26)(6) , Grant => Signal_grant(26)(6)); + +Arbiter_26_7 : Arbiter + +PORT MAP (Request => Request(67), North => south_2_north(25)(7), West => east_2_west(25)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7), +South => south_2_north(26)(7), East => east_2_west(26)(7) , Grant => Signal_grant(26)(7)); + +Arbiter_26_8 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(25)(8), West => east_2_west(25)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8), +South => south_2_north(26)(8), East => east_2_west(26)(8) , Grant => Signal_grant(26)(8)); + +Arbiter_26_9 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(25)(9), West => east_2_west(25)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9), +South => south_2_north(26)(9), East => east_2_west(26)(9) , Grant => Signal_grant(26)(9)); + +Arbiter_26_10 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(25)(10), West => east_2_west(25)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10), +South => south_2_north(26)(10), East => east_2_west(26)(10) , Grant => Signal_grant(26)(10)); + +Arbiter_26_11 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(25)(11), West => east_2_west(25)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11), +South => south_2_north(26)(11), East => east_2_west(26)(11) , Grant => Signal_grant(26)(11)); + +Arbiter_26_12 : Arbiter + +PORT MAP (Request => Request(222), North => south_2_north(25)(12), West => east_2_west(25)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12), +South => south_2_north(26)(12), East => east_2_west(26)(12) , Grant => Signal_grant(26)(12)); + +Arbiter_26_13 : Arbiter + +PORT MAP (Request => Request(208), North => south_2_north(25)(13), West => east_2_west(25)(12), P => Signal_priority(4), Fifo_full => Fifo_full(13), +South => south_2_north(26)(13), East => east_2_west(26)(13) , Grant => Signal_grant(26)(13)); + +Arbiter_26_14 : Arbiter + +PORT MAP (Request => Request(194), North => south_2_north(25)(14), West => east_2_west(25)(13), P => Signal_priority(4), Fifo_full => Fifo_full(14), +South => south_2_north(26)(14), East => east_2_west(26)(14) , Grant => Signal_grant(26)(14)); + +Arbiter_26_15 : Arbiter + +PORT MAP (Request => Request(180), North => south_2_north(25)(15), West => east_2_west(25)(14), P => Signal_priority(4), Fifo_full => Fifo_full(15), +South => south_2_north(26)(15), East => east_2_west(26)(15) , Grant => Signal_grant(26)(15)); + +-------------------------- Diagonale n° 27 + + +Arbiter_27_1 : Arbiter + +PORT MAP (Request => Request(166), North => south_2_north(26)(1), West => east_2_west(26)(15), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(27)(1), East => east_2_west(27)(1) , Grant => Signal_grant(27)(1)); + +Arbiter_27_2 : Arbiter + +PORT MAP (Request => Request(152), North => south_2_north(26)(2), West => east_2_west(26)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(27)(2), East => east_2_west(27)(2) , Grant => Signal_grant(27)(2)); + +Arbiter_27_3 : Arbiter + +PORT MAP (Request => Request(138), North => south_2_north(26)(3), West => east_2_west(26)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(27)(3), East => east_2_west(27)(3) , Grant => Signal_grant(27)(3)); + +Arbiter_27_4 : Arbiter + +PORT MAP (Request => Request(124), North => south_2_north(26)(4), West => east_2_west(26)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(27)(4), East => east_2_west(27)(4) , Grant => Signal_grant(27)(4)); + +Arbiter_27_5 : Arbiter + +PORT MAP (Request => Request(110), North => south_2_north(26)(5), West => east_2_west(26)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5), +South => south_2_north(27)(5), East => east_2_west(27)(5) , Grant => Signal_grant(27)(5)); + +Arbiter_27_6 : Arbiter + +PORT MAP (Request => Request(96), North => south_2_north(26)(6), West => east_2_west(26)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6), +South => south_2_north(27)(6), East => east_2_west(27)(6) , Grant => Signal_grant(27)(6)); + +Arbiter_27_7 : Arbiter + +PORT MAP (Request => Request(82), North => south_2_north(26)(7), West => east_2_west(26)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7), +South => south_2_north(27)(7), East => east_2_west(27)(7) , Grant => Signal_grant(27)(7)); + +Arbiter_27_8 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(26)(8), West => east_2_west(26)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8), +South => south_2_north(27)(8), East => east_2_west(27)(8) , Grant => Signal_grant(27)(8)); + +Arbiter_27_9 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(26)(9), West => east_2_west(26)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9), +South => south_2_north(27)(9), East => east_2_west(27)(9) , Grant => Signal_grant(27)(9)); + +Arbiter_27_10 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(26)(10), West => east_2_west(26)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10), +South => south_2_north(27)(10), East => east_2_west(27)(10) , Grant => Signal_grant(27)(10)); + +Arbiter_27_11 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(26)(11), West => east_2_west(26)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11), +South => south_2_north(27)(11), East => east_2_west(27)(11) , Grant => Signal_grant(27)(11)); + +Arbiter_27_12 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(26)(12), West => east_2_west(26)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12), +South => south_2_north(27)(12), East => east_2_west(27)(12) , Grant => Signal_grant(27)(12)); + +Arbiter_27_13 : Arbiter + +PORT MAP (Request => Request(223), North => south_2_north(26)(13), West => east_2_west(26)(12), P => Signal_priority(3), Fifo_full => Fifo_full(13), +South => south_2_north(27)(13), East => east_2_west(27)(13) , Grant => Signal_grant(27)(13)); + +Arbiter_27_14 : Arbiter + +PORT MAP (Request => Request(209), North => south_2_north(26)(14), West => east_2_west(26)(13), P => Signal_priority(3), Fifo_full => Fifo_full(14), +South => south_2_north(27)(14), East => east_2_west(27)(14) , Grant => Signal_grant(27)(14)); + +Arbiter_27_15 : Arbiter + +PORT MAP (Request => Request(195), North => south_2_north(26)(15), West => east_2_west(26)(14), P => Signal_priority(3), Fifo_full => Fifo_full(15), +South => south_2_north(27)(15), East => east_2_west(27)(15) , Grant => Signal_grant(27)(15)); + +-------------------------- Diagonale n° 28 + + +Arbiter_28_1 : Arbiter + +PORT MAP (Request => Request(181), North => south_2_north(27)(1), West => east_2_west(27)(15), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(28)(1), East => east_2_west(28)(1) , Grant => Signal_grant(28)(1)); + +Arbiter_28_2 : Arbiter + +PORT MAP (Request => Request(167), North => south_2_north(27)(2), West => east_2_west(27)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(28)(2), East => east_2_west(28)(2) , Grant => Signal_grant(28)(2)); + +Arbiter_28_3 : Arbiter + +PORT MAP (Request => Request(153), North => south_2_north(27)(3), West => east_2_west(27)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(28)(3), East => east_2_west(28)(3) , Grant => Signal_grant(28)(3)); + +Arbiter_28_4 : Arbiter + +PORT MAP (Request => Request(139), North => south_2_north(27)(4), West => east_2_west(27)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(28)(4), East => east_2_west(28)(4) , Grant => Signal_grant(28)(4)); + +Arbiter_28_5 : Arbiter + +PORT MAP (Request => Request(125), North => south_2_north(27)(5), West => east_2_west(27)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5), +South => south_2_north(28)(5), East => east_2_west(28)(5) , Grant => Signal_grant(28)(5)); + +Arbiter_28_6 : Arbiter + +PORT MAP (Request => Request(111), North => south_2_north(27)(6), West => east_2_west(27)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6), +South => south_2_north(28)(6), East => east_2_west(28)(6) , Grant => Signal_grant(28)(6)); + +Arbiter_28_7 : Arbiter + +PORT MAP (Request => Request(97), North => south_2_north(27)(7), West => east_2_west(27)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7), +South => south_2_north(28)(7), East => east_2_west(28)(7) , Grant => Signal_grant(28)(7)); + +Arbiter_28_8 : Arbiter + +PORT MAP (Request => Request(83), North => south_2_north(27)(8), West => east_2_west(27)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8), +South => south_2_north(28)(8), East => east_2_west(28)(8) , Grant => Signal_grant(28)(8)); + +Arbiter_28_9 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(27)(9), West => east_2_west(27)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9), +South => south_2_north(28)(9), East => east_2_west(28)(9) , Grant => Signal_grant(28)(9)); + +Arbiter_28_10 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(27)(10), West => east_2_west(27)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10), +South => south_2_north(28)(10), East => east_2_west(28)(10) , Grant => Signal_grant(28)(10)); + +Arbiter_28_11 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(27)(11), West => east_2_west(27)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11), +South => south_2_north(28)(11), East => east_2_west(28)(11) , Grant => Signal_grant(28)(11)); + +Arbiter_28_12 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(27)(12), West => east_2_west(27)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12), +South => south_2_north(28)(12), East => east_2_west(28)(12) , Grant => Signal_grant(28)(12)); + +Arbiter_28_13 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(27)(13), West => east_2_west(27)(12), P => Signal_priority(2), Fifo_full => Fifo_full(13), +South => south_2_north(28)(13), East => east_2_west(28)(13) , Grant => Signal_grant(28)(13)); + +Arbiter_28_14 : Arbiter + +PORT MAP (Request => Request(224), North => south_2_north(27)(14), West => east_2_west(27)(13), P => Signal_priority(2), Fifo_full => Fifo_full(14), +South => south_2_north(28)(14), East => east_2_west(28)(14) , Grant => Signal_grant(28)(14)); + +Arbiter_28_15 : Arbiter + +PORT MAP (Request => Request(210), North => south_2_north(27)(15), West => east_2_west(27)(14), P => Signal_priority(2), Fifo_full => Fifo_full(15), +South => south_2_north(28)(15), East => east_2_west(28)(15) , Grant => Signal_grant(28)(15)); + +-------------------------- Diagonale n° 29 + + +Arbiter_29_1 : Arbiter + +PORT MAP (Request => Request(196), North => south_2_north(28)(1), West => east_2_west(28)(15), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(29)(1), East => east_2_west(29)(1) , Grant => Signal_grant(29)(1)); + +Arbiter_29_2 : Arbiter + +PORT MAP (Request => Request(182), North => south_2_north(28)(2), West => east_2_west(28)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(29)(2), East => east_2_west(29)(2) , Grant => Signal_grant(29)(2)); + +Arbiter_29_3 : Arbiter + +PORT MAP (Request => Request(168), North => south_2_north(28)(3), West => east_2_west(28)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(29)(3), East => east_2_west(29)(3) , Grant => Signal_grant(29)(3)); + +Arbiter_29_4 : Arbiter + +PORT MAP (Request => Request(154), North => south_2_north(28)(4), West => east_2_west(28)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(29)(4), East => east_2_west(29)(4) , Grant => Signal_grant(29)(4)); + +Arbiter_29_5 : Arbiter + +PORT MAP (Request => Request(140), North => south_2_north(28)(5), West => east_2_west(28)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5), +South => south_2_north(29)(5), East => east_2_west(29)(5) , Grant => Signal_grant(29)(5)); + +Arbiter_29_6 : Arbiter + +PORT MAP (Request => Request(126), North => south_2_north(28)(6), West => east_2_west(28)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6), +South => south_2_north(29)(6), East => east_2_west(29)(6) , Grant => Signal_grant(29)(6)); + +Arbiter_29_7 : Arbiter + +PORT MAP (Request => Request(112), North => south_2_north(28)(7), West => east_2_west(28)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7), +South => south_2_north(29)(7), East => east_2_west(29)(7) , Grant => Signal_grant(29)(7)); + +Arbiter_29_8 : Arbiter + +PORT MAP (Request => Request(98), North => south_2_north(28)(8), West => east_2_west(28)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8), +South => south_2_north(29)(8), East => east_2_west(29)(8) , Grant => Signal_grant(29)(8)); + +Arbiter_29_9 : Arbiter + +PORT MAP (Request => Request(84), North => south_2_north(28)(9), West => east_2_west(28)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9), +South => south_2_north(29)(9), East => east_2_west(29)(9) , Grant => Signal_grant(29)(9)); + +Arbiter_29_10 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(28)(10), West => east_2_west(28)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10), +South => south_2_north(29)(10), East => east_2_west(29)(10) , Grant => Signal_grant(29)(10)); + +Arbiter_29_11 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(28)(11), West => east_2_west(28)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11), +South => south_2_north(29)(11), East => east_2_west(29)(11) , Grant => Signal_grant(29)(11)); + +Arbiter_29_12 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(28)(12), West => east_2_west(28)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12), +South => south_2_north(29)(12), East => east_2_west(29)(12) , Grant => Signal_grant(29)(12)); + +Arbiter_29_13 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(28)(13), West => east_2_west(28)(12), P => Signal_priority(1), Fifo_full => Fifo_full(13), +South => south_2_north(29)(13), East => east_2_west(29)(13) , Grant => Signal_grant(29)(13)); + +Arbiter_29_14 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(28)(14), West => east_2_west(28)(13), P => Signal_priority(1), Fifo_full => Fifo_full(14), +South => south_2_north(29)(14), East => east_2_west(29)(14) , Grant => Signal_grant(29)(14)); + +Arbiter_29_15 : Arbiter + +PORT MAP (Request => Request(225), North => south_2_north(28)(15), West => east_2_west(28)(14), P => Signal_priority(1), Fifo_full => Fifo_full(15), +South => south_2_north(29)(15), East => east_2_west(29)(15) , Grant => Signal_grant(29)(15)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "11111111111111100000000000000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "11111111111111100000000000000" => Signal_priority <= "01111111111111110000000000000"; + when "01111111111111110000000000000" => Signal_priority <= "00111111111111111000000000000"; + when "00111111111111111000000000000" => Signal_priority <= "00011111111111111100000000000"; + when "00011111111111111100000000000" => Signal_priority <= "00001111111111111110000000000"; + when "00001111111111111110000000000" => Signal_priority <= "00000111111111111111000000000"; + when "00000111111111111111000000000" => Signal_priority <= "00000011111111111111100000000"; + when "00000011111111111111100000000" => Signal_priority <= "00000001111111111111110000000"; + when "00000001111111111111110000000" => Signal_priority <= "00000000111111111111111000000"; + when "00000000111111111111111000000" => Signal_priority <= "00000000011111111111111100000"; + when "00000000011111111111111100000" => Signal_priority <= "00000000001111111111111110000"; + when "00000000001111111111111110000" => Signal_priority <= "00000000000111111111111111000"; + when "00000000000111111111111111000" => Signal_priority <= "00000000000011111111111111100"; + when "00000000000011111111111111100" => Signal_priority <= "00000000000001111111111111110"; + when "00000000000001111111111111110" => Signal_priority <= "00000000000000111111111111111"; + when "00000000000000111111111111111" => Signal_priority <= "11111111111111100000000000000"; + when others => Signal_priority <= "11111111111111100000000000000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER16_16.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER16_16.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER16_16.VHD (revision 138) @@ -0,0 +1,2941 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler16_16 is + Port ( Request : in STD_LOGIC_VECTOR (256 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (16 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (16 downto 1); + port_grant : out STD_LOGIC_VECTOR (256 downto 1)); +end Scheduler16_16; + +architecture Behavioral of Scheduler16_16 is +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(31 downto 1) of STD_LOGIC_VECTOR(16 downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (31 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(256 downto 1); + signal priority_rotation_en : std_logic; + signal Grant,req_grant : std_logic_vector(256 downto 1); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet +req_grant<=(request and grant_latch); + priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 65535 else '0'; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + elsif priority_rotation_en = '1' or unsigned(Grant_latch)=0 then + grant_latch <= Grant; + end if; + end if; + end process; + port_grant <= grant_latch; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(17)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(18)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(19)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) or Signal_grant(20)(4); -- Grant(1,4) +Grant(5) <= Signal_grant(5)(5) or Signal_grant(21)(5); -- Grant(1,5) +Grant(6) <= Signal_grant(6)(6) or Signal_grant(22)(6); -- Grant(1,6) +Grant(7) <= Signal_grant(7)(7) or Signal_grant(23)(7); -- Grant(1,7) +Grant(8) <= Signal_grant(8)(8) or Signal_grant(24)(8); -- Grant(1,8) +Grant(9) <= Signal_grant(9)(9) or Signal_grant(25)(9); -- Grant(1,9) +Grant(10) <= Signal_grant(10)(10) or Signal_grant(26)(10); -- Grant(1,10) +Grant(11) <= Signal_grant(11)(11) or Signal_grant(27)(11); -- Grant(1,11) +Grant(12) <= Signal_grant(12)(12) or Signal_grant(28)(12); -- Grant(1,12) +Grant(13) <= Signal_grant(13)(13) or Signal_grant(29)(13); -- Grant(1,13) +Grant(14) <= Signal_grant(14)(14) or Signal_grant(30)(14); -- Grant(1,14) +Grant(15) <= Signal_grant(15)(15) or Signal_grant(31)(15); -- Grant(1,15) +Grant(16) <= Signal_grant(16)(16) ; -- Grant(1,16) +Grant(17) <= Signal_grant(2)(1) or Signal_grant(18)(1); -- Grant(2,1) +Grant(18) <= Signal_grant(3)(2) or Signal_grant(19)(2); -- Grant(2,2) +Grant(19) <= Signal_grant(4)(3) or Signal_grant(20)(3); -- Grant(2,3) +Grant(20) <= Signal_grant(5)(4) or Signal_grant(21)(4); -- Grant(2,4) +Grant(21) <= Signal_grant(6)(5) or Signal_grant(22)(5); -- Grant(2,5) +Grant(22) <= Signal_grant(7)(6) or Signal_grant(23)(6); -- Grant(2,6) +Grant(23) <= Signal_grant(8)(7) or Signal_grant(24)(7); -- Grant(2,7) +Grant(24) <= Signal_grant(9)(8) or Signal_grant(25)(8); -- Grant(2,8) +Grant(25) <= Signal_grant(10)(9) or Signal_grant(26)(9); -- Grant(2,9) +Grant(26) <= Signal_grant(11)(10) or Signal_grant(27)(10); -- Grant(2,10) +Grant(27) <= Signal_grant(12)(11) or Signal_grant(28)(11); -- Grant(2,11) +Grant(28) <= Signal_grant(13)(12) or Signal_grant(29)(12); -- Grant(2,12) +Grant(29) <= Signal_grant(14)(13) or Signal_grant(30)(13); -- Grant(2,13) +Grant(30) <= Signal_grant(15)(14) or Signal_grant(31)(14); -- Grant(2,14) +Grant(31) <= Signal_grant(16)(15) ; -- Grant(2,15) +Grant(32) <= Signal_grant(1)(16) or Signal_grant(17)(16); -- Grant(2,16) +Grant(33) <= Signal_grant(3)(1) or Signal_grant(19)(1); -- Grant(3,1) +Grant(34) <= Signal_grant(4)(2) or Signal_grant(20)(2); -- Grant(3,2) +Grant(35) <= Signal_grant(5)(3) or Signal_grant(21)(3); -- Grant(3,3) +Grant(36) <= Signal_grant(6)(4) or Signal_grant(22)(4); -- Grant(3,4) +Grant(37) <= Signal_grant(7)(5) or Signal_grant(23)(5); -- Grant(3,5) +Grant(38) <= Signal_grant(8)(6) or Signal_grant(24)(6); -- Grant(3,6) +Grant(39) <= Signal_grant(9)(7) or Signal_grant(25)(7); -- Grant(3,7) +Grant(40) <= Signal_grant(10)(8) or Signal_grant(26)(8); -- Grant(3,8) +Grant(41) <= Signal_grant(11)(9) or Signal_grant(27)(9); -- Grant(3,9) +Grant(42) <= Signal_grant(12)(10) or Signal_grant(28)(10); -- Grant(3,10) +Grant(43) <= Signal_grant(13)(11) or Signal_grant(29)(11); -- Grant(3,11) +Grant(44) <= Signal_grant(14)(12) or Signal_grant(30)(12); -- Grant(3,12) +Grant(45) <= Signal_grant(15)(13) or Signal_grant(31)(13); -- Grant(3,13) +Grant(46) <= Signal_grant(16)(14) ; -- Grant(3,14) +Grant(47) <= Signal_grant(1)(15) or Signal_grant(17)(15); -- Grant(3,15) +Grant(48) <= Signal_grant(2)(16) or Signal_grant(18)(16); -- Grant(3,16) +Grant(49) <= Signal_grant(4)(1) or Signal_grant(20)(1); -- Grant(4,1) +Grant(50) <= Signal_grant(5)(2) or Signal_grant(21)(2); -- Grant(4,2) +Grant(51) <= Signal_grant(6)(3) or Signal_grant(22)(3); -- Grant(4,3) +Grant(52) <= Signal_grant(7)(4) or Signal_grant(23)(4); -- Grant(4,4) +Grant(53) <= Signal_grant(8)(5) or Signal_grant(24)(5); -- Grant(4,5) +Grant(54) <= Signal_grant(9)(6) or Signal_grant(25)(6); -- Grant(4,6) +Grant(55) <= Signal_grant(10)(7) or Signal_grant(26)(7); -- Grant(4,7) +Grant(56) <= Signal_grant(11)(8) or Signal_grant(27)(8); -- Grant(4,8) +Grant(57) <= Signal_grant(12)(9) or Signal_grant(28)(9); -- Grant(4,9) +Grant(58) <= Signal_grant(13)(10) or Signal_grant(29)(10); -- Grant(4,10) +Grant(59) <= Signal_grant(14)(11) or Signal_grant(30)(11); -- Grant(4,11) +Grant(60) <= Signal_grant(15)(12) or Signal_grant(31)(12); -- Grant(4,12) +Grant(61) <= Signal_grant(16)(13) ; -- Grant(4,13) +Grant(62) <= Signal_grant(1)(14) or Signal_grant(17)(14); -- Grant(4,14) +Grant(63) <= Signal_grant(2)(15) or Signal_grant(18)(15); -- Grant(4,15) +Grant(64) <= Signal_grant(3)(16) or Signal_grant(19)(16); -- Grant(4,16) +Grant(65) <= Signal_grant(5)(1) or Signal_grant(21)(1); -- Grant(5,1) +Grant(66) <= Signal_grant(6)(2) or Signal_grant(22)(2); -- Grant(5,2) +Grant(67) <= Signal_grant(7)(3) or Signal_grant(23)(3); -- Grant(5,3) +Grant(68) <= Signal_grant(8)(4) or Signal_grant(24)(4); -- Grant(5,4) +Grant(69) <= Signal_grant(9)(5) or Signal_grant(25)(5); -- Grant(5,5) +Grant(70) <= Signal_grant(10)(6) or Signal_grant(26)(6); -- Grant(5,6) +Grant(71) <= Signal_grant(11)(7) or Signal_grant(27)(7); -- Grant(5,7) +Grant(72) <= Signal_grant(12)(8) or Signal_grant(28)(8); -- Grant(5,8) +Grant(73) <= Signal_grant(13)(9) or Signal_grant(29)(9); -- Grant(5,9) +Grant(74) <= Signal_grant(14)(10) or Signal_grant(30)(10); -- Grant(5,10) +Grant(75) <= Signal_grant(15)(11) or Signal_grant(31)(11); -- Grant(5,11) +Grant(76) <= Signal_grant(16)(12) ; -- Grant(5,12) +Grant(77) <= Signal_grant(1)(13) or Signal_grant(17)(13); -- Grant(5,13) +Grant(78) <= Signal_grant(2)(14) or Signal_grant(18)(14); -- Grant(5,14) +Grant(79) <= Signal_grant(3)(15) or Signal_grant(19)(15); -- Grant(5,15) +Grant(80) <= Signal_grant(4)(16) or Signal_grant(20)(16); -- Grant(5,16) +Grant(81) <= Signal_grant(6)(1) or Signal_grant(22)(1); -- Grant(6,1) +Grant(82) <= Signal_grant(7)(2) or Signal_grant(23)(2); -- Grant(6,2) +Grant(83) <= Signal_grant(8)(3) or Signal_grant(24)(3); -- Grant(6,3) +Grant(84) <= Signal_grant(9)(4) or Signal_grant(25)(4); -- Grant(6,4) +Grant(85) <= Signal_grant(10)(5) or Signal_grant(26)(5); -- Grant(6,5) +Grant(86) <= Signal_grant(11)(6) or Signal_grant(27)(6); -- Grant(6,6) +Grant(87) <= Signal_grant(12)(7) or Signal_grant(28)(7); -- Grant(6,7) +Grant(88) <= Signal_grant(13)(8) or Signal_grant(29)(8); -- Grant(6,8) +Grant(89) <= Signal_grant(14)(9) or Signal_grant(30)(9); -- Grant(6,9) +Grant(90) <= Signal_grant(15)(10) or Signal_grant(31)(10); -- Grant(6,10) +Grant(91) <= Signal_grant(16)(11) ; -- Grant(6,11) +Grant(92) <= Signal_grant(1)(12) or Signal_grant(17)(12); -- Grant(6,12) +Grant(93) <= Signal_grant(2)(13) or Signal_grant(18)(13); -- Grant(6,13) +Grant(94) <= Signal_grant(3)(14) or Signal_grant(19)(14); -- Grant(6,14) +Grant(95) <= Signal_grant(4)(15) or Signal_grant(20)(15); -- Grant(6,15) +Grant(96) <= Signal_grant(5)(16) or Signal_grant(21)(16); -- Grant(6,16) +Grant(97) <= Signal_grant(7)(1) or Signal_grant(23)(1); -- Grant(7,1) +Grant(98) <= Signal_grant(8)(2) or Signal_grant(24)(2); -- Grant(7,2) +Grant(99) <= Signal_grant(9)(3) or Signal_grant(25)(3); -- Grant(7,3) +Grant(100) <= Signal_grant(10)(4) or Signal_grant(26)(4); -- Grant(7,4) +Grant(101) <= Signal_grant(11)(5) or Signal_grant(27)(5); -- Grant(7,5) +Grant(102) <= Signal_grant(12)(6) or Signal_grant(28)(6); -- Grant(7,6) +Grant(103) <= Signal_grant(13)(7) or Signal_grant(29)(7); -- Grant(7,7) +Grant(104) <= Signal_grant(14)(8) or Signal_grant(30)(8); -- Grant(7,8) +Grant(105) <= Signal_grant(15)(9) or Signal_grant(31)(9); -- Grant(7,9) +Grant(106) <= Signal_grant(16)(10) ; -- Grant(7,10) +Grant(107) <= Signal_grant(1)(11) or Signal_grant(17)(11); -- Grant(7,11) +Grant(108) <= Signal_grant(2)(12) or Signal_grant(18)(12); -- Grant(7,12) +Grant(109) <= Signal_grant(3)(13) or Signal_grant(19)(13); -- Grant(7,13) +Grant(110) <= Signal_grant(4)(14) or Signal_grant(20)(14); -- Grant(7,14) +Grant(111) <= Signal_grant(5)(15) or Signal_grant(21)(15); -- Grant(7,15) +Grant(112) <= Signal_grant(6)(16) or Signal_grant(22)(16); -- Grant(7,16) +Grant(113) <= Signal_grant(8)(1) or Signal_grant(24)(1); -- Grant(8,1) +Grant(114) <= Signal_grant(9)(2) or Signal_grant(25)(2); -- Grant(8,2) +Grant(115) <= Signal_grant(10)(3) or Signal_grant(26)(3); -- Grant(8,3) +Grant(116) <= Signal_grant(11)(4) or Signal_grant(27)(4); -- Grant(8,4) +Grant(117) <= Signal_grant(12)(5) or Signal_grant(28)(5); -- Grant(8,5) +Grant(118) <= Signal_grant(13)(6) or Signal_grant(29)(6); -- Grant(8,6) +Grant(119) <= Signal_grant(14)(7) or Signal_grant(30)(7); -- Grant(8,7) +Grant(120) <= Signal_grant(15)(8) or Signal_grant(31)(8); -- Grant(8,8) +Grant(121) <= Signal_grant(16)(9) ; -- Grant(8,9) +Grant(122) <= Signal_grant(1)(10) or Signal_grant(17)(10); -- Grant(8,10) +Grant(123) <= Signal_grant(2)(11) or Signal_grant(18)(11); -- Grant(8,11) +Grant(124) <= Signal_grant(3)(12) or Signal_grant(19)(12); -- Grant(8,12) +Grant(125) <= Signal_grant(4)(13) or Signal_grant(20)(13); -- Grant(8,13) +Grant(126) <= Signal_grant(5)(14) or Signal_grant(21)(14); -- Grant(8,14) +Grant(127) <= Signal_grant(6)(15) or Signal_grant(22)(15); -- Grant(8,15) +Grant(128) <= Signal_grant(7)(16) or Signal_grant(23)(16); -- Grant(8,16) +Grant(129) <= Signal_grant(9)(1) or Signal_grant(25)(1); -- Grant(9,1) +Grant(130) <= Signal_grant(10)(2) or Signal_grant(26)(2); -- Grant(9,2) +Grant(131) <= Signal_grant(11)(3) or Signal_grant(27)(3); -- Grant(9,3) +Grant(132) <= Signal_grant(12)(4) or Signal_grant(28)(4); -- Grant(9,4) +Grant(133) <= Signal_grant(13)(5) or Signal_grant(29)(5); -- Grant(9,5) +Grant(134) <= Signal_grant(14)(6) or Signal_grant(30)(6); -- Grant(9,6) +Grant(135) <= Signal_grant(15)(7) or Signal_grant(31)(7); -- Grant(9,7) +Grant(136) <= Signal_grant(16)(8) ; -- Grant(9,8) +Grant(137) <= Signal_grant(1)(9) or Signal_grant(17)(9); -- Grant(9,9) +Grant(138) <= Signal_grant(2)(10) or Signal_grant(18)(10); -- Grant(9,10) +Grant(139) <= Signal_grant(3)(11) or Signal_grant(19)(11); -- Grant(9,11) +Grant(140) <= Signal_grant(4)(12) or Signal_grant(20)(12); -- Grant(9,12) +Grant(141) <= Signal_grant(5)(13) or Signal_grant(21)(13); -- Grant(9,13) +Grant(142) <= Signal_grant(6)(14) or Signal_grant(22)(14); -- Grant(9,14) +Grant(143) <= Signal_grant(7)(15) or Signal_grant(23)(15); -- Grant(9,15) +Grant(144) <= Signal_grant(8)(16) or Signal_grant(24)(16); -- Grant(9,16) +Grant(145) <= Signal_grant(10)(1) or Signal_grant(26)(1); -- Grant(10,1) +Grant(146) <= Signal_grant(11)(2) or Signal_grant(27)(2); -- Grant(10,2) +Grant(147) <= Signal_grant(12)(3) or Signal_grant(28)(3); -- Grant(10,3) +Grant(148) <= Signal_grant(13)(4) or Signal_grant(29)(4); -- Grant(10,4) +Grant(149) <= Signal_grant(14)(5) or Signal_grant(30)(5); -- Grant(10,5) +Grant(150) <= Signal_grant(15)(6) or Signal_grant(31)(6); -- Grant(10,6) +Grant(151) <= Signal_grant(16)(7) ; -- Grant(10,7) +Grant(152) <= Signal_grant(1)(8) or Signal_grant(17)(8); -- Grant(10,8) +Grant(153) <= Signal_grant(2)(9) or Signal_grant(18)(9); -- Grant(10,9) +Grant(154) <= Signal_grant(3)(10) or Signal_grant(19)(10); -- Grant(10,10) +Grant(155) <= Signal_grant(4)(11) or Signal_grant(20)(11); -- Grant(10,11) +Grant(156) <= Signal_grant(5)(12) or Signal_grant(21)(12); -- Grant(10,12) +Grant(157) <= Signal_grant(6)(13) or Signal_grant(22)(13); -- Grant(10,13) +Grant(158) <= Signal_grant(7)(14) or Signal_grant(23)(14); -- Grant(10,14) +Grant(159) <= Signal_grant(8)(15) or Signal_grant(24)(15); -- Grant(10,15) +Grant(160) <= Signal_grant(9)(16) or Signal_grant(25)(16); -- Grant(10,16) +Grant(161) <= Signal_grant(11)(1) or Signal_grant(27)(1); -- Grant(11,1) +Grant(162) <= Signal_grant(12)(2) or Signal_grant(28)(2); -- Grant(11,2) +Grant(163) <= Signal_grant(13)(3) or Signal_grant(29)(3); -- Grant(11,3) +Grant(164) <= Signal_grant(14)(4) or Signal_grant(30)(4); -- Grant(11,4) +Grant(165) <= Signal_grant(15)(5) or Signal_grant(31)(5); -- Grant(11,5) +Grant(166) <= Signal_grant(16)(6) ; -- Grant(11,6) +Grant(167) <= Signal_grant(1)(7) or Signal_grant(17)(7); -- Grant(11,7) +Grant(168) <= Signal_grant(2)(8) or Signal_grant(18)(8); -- Grant(11,8) +Grant(169) <= Signal_grant(3)(9) or Signal_grant(19)(9); -- Grant(11,9) +Grant(170) <= Signal_grant(4)(10) or Signal_grant(20)(10); -- Grant(11,10) +Grant(171) <= Signal_grant(5)(11) or Signal_grant(21)(11); -- Grant(11,11) +Grant(172) <= Signal_grant(6)(12) or Signal_grant(22)(12); -- Grant(11,12) +Grant(173) <= Signal_grant(7)(13) or Signal_grant(23)(13); -- Grant(11,13) +Grant(174) <= Signal_grant(8)(14) or Signal_grant(24)(14); -- Grant(11,14) +Grant(175) <= Signal_grant(9)(15) or Signal_grant(25)(15); -- Grant(11,15) +Grant(176) <= Signal_grant(10)(16) or Signal_grant(26)(16); -- Grant(11,16) +Grant(177) <= Signal_grant(12)(1) or Signal_grant(28)(1); -- Grant(12,1) +Grant(178) <= Signal_grant(13)(2) or Signal_grant(29)(2); -- Grant(12,2) +Grant(179) <= Signal_grant(14)(3) or Signal_grant(30)(3); -- Grant(12,3) +Grant(180) <= Signal_grant(15)(4) or Signal_grant(31)(4); -- Grant(12,4) +Grant(181) <= Signal_grant(16)(5) ; -- Grant(12,5) +Grant(182) <= Signal_grant(1)(6) or Signal_grant(17)(6); -- Grant(12,6) +Grant(183) <= Signal_grant(2)(7) or Signal_grant(18)(7); -- Grant(12,7) +Grant(184) <= Signal_grant(3)(8) or Signal_grant(19)(8); -- Grant(12,8) +Grant(185) <= Signal_grant(4)(9) or Signal_grant(20)(9); -- Grant(12,9) +Grant(186) <= Signal_grant(5)(10) or Signal_grant(21)(10); -- Grant(12,10) +Grant(187) <= Signal_grant(6)(11) or Signal_grant(22)(11); -- Grant(12,11) +Grant(188) <= Signal_grant(7)(12) or Signal_grant(23)(12); -- Grant(12,12) +Grant(189) <= Signal_grant(8)(13) or Signal_grant(24)(13); -- Grant(12,13) +Grant(190) <= Signal_grant(9)(14) or Signal_grant(25)(14); -- Grant(12,14) +Grant(191) <= Signal_grant(10)(15) or Signal_grant(26)(15); -- Grant(12,15) +Grant(192) <= Signal_grant(11)(16) or Signal_grant(27)(16); -- Grant(12,16) +Grant(193) <= Signal_grant(13)(1) or Signal_grant(29)(1); -- Grant(13,1) +Grant(194) <= Signal_grant(14)(2) or Signal_grant(30)(2); -- Grant(13,2) +Grant(195) <= Signal_grant(15)(3) or Signal_grant(31)(3); -- Grant(13,3) +Grant(196) <= Signal_grant(16)(4) ; -- Grant(13,4) +Grant(197) <= Signal_grant(1)(5) or Signal_grant(17)(5); -- Grant(13,5) +Grant(198) <= Signal_grant(2)(6) or Signal_grant(18)(6); -- Grant(13,6) +Grant(199) <= Signal_grant(3)(7) or Signal_grant(19)(7); -- Grant(13,7) +Grant(200) <= Signal_grant(4)(8) or Signal_grant(20)(8); -- Grant(13,8) +Grant(201) <= Signal_grant(5)(9) or Signal_grant(21)(9); -- Grant(13,9) +Grant(202) <= Signal_grant(6)(10) or Signal_grant(22)(10); -- Grant(13,10) +Grant(203) <= Signal_grant(7)(11) or Signal_grant(23)(11); -- Grant(13,11) +Grant(204) <= Signal_grant(8)(12) or Signal_grant(24)(12); -- Grant(13,12) +Grant(205) <= Signal_grant(9)(13) or Signal_grant(25)(13); -- Grant(13,13) +Grant(206) <= Signal_grant(10)(14) or Signal_grant(26)(14); -- Grant(13,14) +Grant(207) <= Signal_grant(11)(15) or Signal_grant(27)(15); -- Grant(13,15) +Grant(208) <= Signal_grant(12)(16) or Signal_grant(28)(16); -- Grant(13,16) +Grant(209) <= Signal_grant(14)(1) or Signal_grant(30)(1); -- Grant(14,1) +Grant(210) <= Signal_grant(15)(2) or Signal_grant(31)(2); -- Grant(14,2) +Grant(211) <= Signal_grant(16)(3) ; -- Grant(14,3) +Grant(212) <= Signal_grant(1)(4) or Signal_grant(17)(4); -- Grant(14,4) +Grant(213) <= Signal_grant(2)(5) or Signal_grant(18)(5); -- Grant(14,5) +Grant(214) <= Signal_grant(3)(6) or Signal_grant(19)(6); -- Grant(14,6) +Grant(215) <= Signal_grant(4)(7) or Signal_grant(20)(7); -- Grant(14,7) +Grant(216) <= Signal_grant(5)(8) or Signal_grant(21)(8); -- Grant(14,8) +Grant(217) <= Signal_grant(6)(9) or Signal_grant(22)(9); -- Grant(14,9) +Grant(218) <= Signal_grant(7)(10) or Signal_grant(23)(10); -- Grant(14,10) +Grant(219) <= Signal_grant(8)(11) or Signal_grant(24)(11); -- Grant(14,11) +Grant(220) <= Signal_grant(9)(12) or Signal_grant(25)(12); -- Grant(14,12) +Grant(221) <= Signal_grant(10)(13) or Signal_grant(26)(13); -- Grant(14,13) +Grant(222) <= Signal_grant(11)(14) or Signal_grant(27)(14); -- Grant(14,14) +Grant(223) <= Signal_grant(12)(15) or Signal_grant(28)(15); -- Grant(14,15) +Grant(224) <= Signal_grant(13)(16) or Signal_grant(29)(16); -- Grant(14,16) +Grant(225) <= Signal_grant(15)(1) or Signal_grant(31)(1); -- Grant(15,1) +Grant(226) <= Signal_grant(16)(2) ; -- Grant(15,2) +Grant(227) <= Signal_grant(1)(3) or Signal_grant(17)(3); -- Grant(15,3) +Grant(228) <= Signal_grant(2)(4) or Signal_grant(18)(4); -- Grant(15,4) +Grant(229) <= Signal_grant(3)(5) or Signal_grant(19)(5); -- Grant(15,5) +Grant(230) <= Signal_grant(4)(6) or Signal_grant(20)(6); -- Grant(15,6) +Grant(231) <= Signal_grant(5)(7) or Signal_grant(21)(7); -- Grant(15,7) +Grant(232) <= Signal_grant(6)(8) or Signal_grant(22)(8); -- Grant(15,8) +Grant(233) <= Signal_grant(7)(9) or Signal_grant(23)(9); -- Grant(15,9) +Grant(234) <= Signal_grant(8)(10) or Signal_grant(24)(10); -- Grant(15,10) +Grant(235) <= Signal_grant(9)(11) or Signal_grant(25)(11); -- Grant(15,11) +Grant(236) <= Signal_grant(10)(12) or Signal_grant(26)(12); -- Grant(15,12) +Grant(237) <= Signal_grant(11)(13) or Signal_grant(27)(13); -- Grant(15,13) +Grant(238) <= Signal_grant(12)(14) or Signal_grant(28)(14); -- Grant(15,14) +Grant(239) <= Signal_grant(13)(15) or Signal_grant(29)(15); -- Grant(15,15) +Grant(240) <= Signal_grant(14)(16) or Signal_grant(30)(16); -- Grant(15,16) +Grant(241) <= Signal_grant(16)(1) ; -- Grant(16,1) +Grant(242) <= Signal_grant(1)(2) or Signal_grant(17)(2); -- Grant(16,2) +Grant(243) <= Signal_grant(2)(3) or Signal_grant(18)(3); -- Grant(16,3) +Grant(244) <= Signal_grant(3)(4) or Signal_grant(19)(4); -- Grant(16,4) +Grant(245) <= Signal_grant(4)(5) or Signal_grant(20)(5); -- Grant(16,5) +Grant(246) <= Signal_grant(5)(6) or Signal_grant(21)(6); -- Grant(16,6) +Grant(247) <= Signal_grant(6)(7) or Signal_grant(22)(7); -- Grant(16,7) +Grant(248) <= Signal_grant(7)(8) or Signal_grant(23)(8); -- Grant(16,8) +Grant(249) <= Signal_grant(8)(9) or Signal_grant(24)(9); -- Grant(16,9) +Grant(250) <= Signal_grant(9)(10) or Signal_grant(25)(10); -- Grant(16,10) +Grant(251) <= Signal_grant(10)(11) or Signal_grant(26)(11); -- Grant(16,11) +Grant(252) <= Signal_grant(11)(12) or Signal_grant(27)(12); -- Grant(16,12) +Grant(253) <= Signal_grant(12)(13) or Signal_grant(28)(13); -- Grant(16,13) +Grant(254) <= Signal_grant(13)(14) or Signal_grant(29)(14); -- Grant(16,14) +Grant(255) <= Signal_grant(14)(15) or Signal_grant(30)(15); -- Grant(16,15) +Grant(256) <= Signal_grant(15)(16) or Signal_grant(31)(16); -- Grant(16,16) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(242), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(227), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(212), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +Arbiter_1_5 : Arbiter + +PORT MAP (Request => Request(197), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(5), +South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); + +Arbiter_1_6 : Arbiter + +PORT MAP (Request => Request(182), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(6), +South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); + +Arbiter_1_7 : Arbiter + +PORT MAP (Request => Request(167), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(7), +South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); + +Arbiter_1_8 : Arbiter + +PORT MAP (Request => Request(152), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(8), +South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); + +Arbiter_1_9 : Arbiter + +PORT MAP (Request => Request(137), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(9), +South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); + +Arbiter_1_10 : Arbiter + +PORT MAP (Request => Request(122), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(10), +South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); + +Arbiter_1_11 : Arbiter + +PORT MAP (Request => Request(107), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(11), +South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); + +Arbiter_1_12 : Arbiter + +PORT MAP (Request => Request(92), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(12), +South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); + +Arbiter_1_13 : Arbiter + +PORT MAP (Request => Request(77), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(13), +South => south_2_north(1)(13), East => east_2_west(1)(13) , Grant => Signal_grant(1)(13)); + +Arbiter_1_14 : Arbiter + +PORT MAP (Request => Request(62), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(14), +South => south_2_north(1)(14), East => east_2_west(1)(14) , Grant => Signal_grant(1)(14)); + +Arbiter_1_15 : Arbiter + +PORT MAP (Request => Request(47), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(15), +South => south_2_north(1)(15), East => east_2_west(1)(15) , Grant => Signal_grant(1)(15)); + +Arbiter_1_16 : Arbiter + +PORT MAP (Request => Request(32), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(16), +South => south_2_north(1)(16), East => east_2_west(1)(16) , Grant => Signal_grant(1)(16)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(1)(1), West => east_2_west(1)(16), P => Signal_priority(30), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(30), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(243), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(30), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(228), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(30), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +Arbiter_2_5 : Arbiter + +PORT MAP (Request => Request(213), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(30), Fifo_full => Fifo_full(5), +South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); + +Arbiter_2_6 : Arbiter + +PORT MAP (Request => Request(198), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(30), Fifo_full => Fifo_full(6), +South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); + +Arbiter_2_7 : Arbiter + +PORT MAP (Request => Request(183), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(30), Fifo_full => Fifo_full(7), +South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); + +Arbiter_2_8 : Arbiter + +PORT MAP (Request => Request(168), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(30), Fifo_full => Fifo_full(8), +South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); + +Arbiter_2_9 : Arbiter + +PORT MAP (Request => Request(153), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(30), Fifo_full => Fifo_full(9), +South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); + +Arbiter_2_10 : Arbiter + +PORT MAP (Request => Request(138), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(30), Fifo_full => Fifo_full(10), +South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); + +Arbiter_2_11 : Arbiter + +PORT MAP (Request => Request(123), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(30), Fifo_full => Fifo_full(11), +South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); + +Arbiter_2_12 : Arbiter + +PORT MAP (Request => Request(108), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(30), Fifo_full => Fifo_full(12), +South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); + +Arbiter_2_13 : Arbiter + +PORT MAP (Request => Request(93), North => south_2_north(1)(13), West => east_2_west(1)(12), P => Signal_priority(30), Fifo_full => Fifo_full(13), +South => south_2_north(2)(13), East => east_2_west(2)(13) , Grant => Signal_grant(2)(13)); + +Arbiter_2_14 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(1)(14), West => east_2_west(1)(13), P => Signal_priority(30), Fifo_full => Fifo_full(14), +South => south_2_north(2)(14), East => east_2_west(2)(14) , Grant => Signal_grant(2)(14)); + +Arbiter_2_15 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(1)(15), West => east_2_west(1)(14), P => Signal_priority(30), Fifo_full => Fifo_full(15), +South => south_2_north(2)(15), East => east_2_west(2)(15) , Grant => Signal_grant(2)(15)); + +Arbiter_2_16 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(1)(16), West => east_2_west(1)(15), P => Signal_priority(30), Fifo_full => Fifo_full(16), +South => south_2_north(2)(16), East => east_2_west(2)(16) , Grant => Signal_grant(2)(16)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(2)(1), West => east_2_west(2)(16), P => Signal_priority(29), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(29), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(29), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(244), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(29), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +Arbiter_3_5 : Arbiter + +PORT MAP (Request => Request(229), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(29), Fifo_full => Fifo_full(5), +South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); + +Arbiter_3_6 : Arbiter + +PORT MAP (Request => Request(214), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(29), Fifo_full => Fifo_full(6), +South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); + +Arbiter_3_7 : Arbiter + +PORT MAP (Request => Request(199), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(29), Fifo_full => Fifo_full(7), +South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); + +Arbiter_3_8 : Arbiter + +PORT MAP (Request => Request(184), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(29), Fifo_full => Fifo_full(8), +South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); + +Arbiter_3_9 : Arbiter + +PORT MAP (Request => Request(169), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(29), Fifo_full => Fifo_full(9), +South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); + +Arbiter_3_10 : Arbiter + +PORT MAP (Request => Request(154), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(29), Fifo_full => Fifo_full(10), +South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); + +Arbiter_3_11 : Arbiter + +PORT MAP (Request => Request(139), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(29), Fifo_full => Fifo_full(11), +South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); + +Arbiter_3_12 : Arbiter + +PORT MAP (Request => Request(124), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(29), Fifo_full => Fifo_full(12), +South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); + +Arbiter_3_13 : Arbiter + +PORT MAP (Request => Request(109), North => south_2_north(2)(13), West => east_2_west(2)(12), P => Signal_priority(29), Fifo_full => Fifo_full(13), +South => south_2_north(3)(13), East => east_2_west(3)(13) , Grant => Signal_grant(3)(13)); + +Arbiter_3_14 : Arbiter + +PORT MAP (Request => Request(94), North => south_2_north(2)(14), West => east_2_west(2)(13), P => Signal_priority(29), Fifo_full => Fifo_full(14), +South => south_2_north(3)(14), East => east_2_west(3)(14) , Grant => Signal_grant(3)(14)); + +Arbiter_3_15 : Arbiter + +PORT MAP (Request => Request(79), North => south_2_north(2)(15), West => east_2_west(2)(14), P => Signal_priority(29), Fifo_full => Fifo_full(15), +South => south_2_north(3)(15), East => east_2_west(3)(15) , Grant => Signal_grant(3)(15)); + +Arbiter_3_16 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(2)(16), West => east_2_west(2)(15), P => Signal_priority(29), Fifo_full => Fifo_full(16), +South => south_2_north(3)(16), East => east_2_west(3)(16) , Grant => Signal_grant(3)(16)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(3)(1), West => east_2_west(3)(16), P => Signal_priority(28), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(28), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(28), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(28), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +Arbiter_4_5 : Arbiter + +PORT MAP (Request => Request(245), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(28), Fifo_full => Fifo_full(5), +South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); + +Arbiter_4_6 : Arbiter + +PORT MAP (Request => Request(230), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(28), Fifo_full => Fifo_full(6), +South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); + +Arbiter_4_7 : Arbiter + +PORT MAP (Request => Request(215), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(28), Fifo_full => Fifo_full(7), +South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); + +Arbiter_4_8 : Arbiter + +PORT MAP (Request => Request(200), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(28), Fifo_full => Fifo_full(8), +South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); + +Arbiter_4_9 : Arbiter + +PORT MAP (Request => Request(185), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(28), Fifo_full => Fifo_full(9), +South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); + +Arbiter_4_10 : Arbiter + +PORT MAP (Request => Request(170), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(28), Fifo_full => Fifo_full(10), +South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); + +Arbiter_4_11 : Arbiter + +PORT MAP (Request => Request(155), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(28), Fifo_full => Fifo_full(11), +South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); + +Arbiter_4_12 : Arbiter + +PORT MAP (Request => Request(140), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(28), Fifo_full => Fifo_full(12), +South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); + +Arbiter_4_13 : Arbiter + +PORT MAP (Request => Request(125), North => south_2_north(3)(13), West => east_2_west(3)(12), P => Signal_priority(28), Fifo_full => Fifo_full(13), +South => south_2_north(4)(13), East => east_2_west(4)(13) , Grant => Signal_grant(4)(13)); + +Arbiter_4_14 : Arbiter + +PORT MAP (Request => Request(110), North => south_2_north(3)(14), West => east_2_west(3)(13), P => Signal_priority(28), Fifo_full => Fifo_full(14), +South => south_2_north(4)(14), East => east_2_west(4)(14) , Grant => Signal_grant(4)(14)); + +Arbiter_4_15 : Arbiter + +PORT MAP (Request => Request(95), North => south_2_north(3)(15), West => east_2_west(3)(14), P => Signal_priority(28), Fifo_full => Fifo_full(15), +South => south_2_north(4)(15), East => east_2_west(4)(15) , Grant => Signal_grant(4)(15)); + +Arbiter_4_16 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(3)(16), West => east_2_west(3)(15), P => Signal_priority(28), Fifo_full => Fifo_full(16), +South => south_2_north(4)(16), East => east_2_west(4)(16) , Grant => Signal_grant(4)(16)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(65), North => south_2_north(4)(1), West => east_2_west(4)(16), P => Signal_priority(27), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(27), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(27), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(27), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +Arbiter_5_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(27), Fifo_full => Fifo_full(5), +South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); + +Arbiter_5_6 : Arbiter + +PORT MAP (Request => Request(246), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(27), Fifo_full => Fifo_full(6), +South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); + +Arbiter_5_7 : Arbiter + +PORT MAP (Request => Request(231), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(27), Fifo_full => Fifo_full(7), +South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); + +Arbiter_5_8 : Arbiter + +PORT MAP (Request => Request(216), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(27), Fifo_full => Fifo_full(8), +South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); + +Arbiter_5_9 : Arbiter + +PORT MAP (Request => Request(201), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(27), Fifo_full => Fifo_full(9), +South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); + +Arbiter_5_10 : Arbiter + +PORT MAP (Request => Request(186), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(27), Fifo_full => Fifo_full(10), +South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); + +Arbiter_5_11 : Arbiter + +PORT MAP (Request => Request(171), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(27), Fifo_full => Fifo_full(11), +South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); + +Arbiter_5_12 : Arbiter + +PORT MAP (Request => Request(156), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(27), Fifo_full => Fifo_full(12), +South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); + +Arbiter_5_13 : Arbiter + +PORT MAP (Request => Request(141), North => south_2_north(4)(13), West => east_2_west(4)(12), P => Signal_priority(27), Fifo_full => Fifo_full(13), +South => south_2_north(5)(13), East => east_2_west(5)(13) , Grant => Signal_grant(5)(13)); + +Arbiter_5_14 : Arbiter + +PORT MAP (Request => Request(126), North => south_2_north(4)(14), West => east_2_west(4)(13), P => Signal_priority(27), Fifo_full => Fifo_full(14), +South => south_2_north(5)(14), East => east_2_west(5)(14) , Grant => Signal_grant(5)(14)); + +Arbiter_5_15 : Arbiter + +PORT MAP (Request => Request(111), North => south_2_north(4)(15), West => east_2_west(4)(14), P => Signal_priority(27), Fifo_full => Fifo_full(15), +South => south_2_north(5)(15), East => east_2_west(5)(15) , Grant => Signal_grant(5)(15)); + +Arbiter_5_16 : Arbiter + +PORT MAP (Request => Request(96), North => south_2_north(4)(16), West => east_2_west(4)(15), P => Signal_priority(27), Fifo_full => Fifo_full(16), +South => south_2_north(5)(16), East => east_2_west(5)(16) , Grant => Signal_grant(5)(16)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(5)(1), West => east_2_west(5)(16), P => Signal_priority(26), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(66), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(26), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(26), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(26), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +Arbiter_6_5 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(26), Fifo_full => Fifo_full(5), +South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); + +Arbiter_6_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(26), Fifo_full => Fifo_full(6), +South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); + +Arbiter_6_7 : Arbiter + +PORT MAP (Request => Request(247), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(26), Fifo_full => Fifo_full(7), +South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); + +Arbiter_6_8 : Arbiter + +PORT MAP (Request => Request(232), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(26), Fifo_full => Fifo_full(8), +South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); + +Arbiter_6_9 : Arbiter + +PORT MAP (Request => Request(217), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(26), Fifo_full => Fifo_full(9), +South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); + +Arbiter_6_10 : Arbiter + +PORT MAP (Request => Request(202), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(26), Fifo_full => Fifo_full(10), +South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); + +Arbiter_6_11 : Arbiter + +PORT MAP (Request => Request(187), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(26), Fifo_full => Fifo_full(11), +South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); + +Arbiter_6_12 : Arbiter + +PORT MAP (Request => Request(172), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(26), Fifo_full => Fifo_full(12), +South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); + +Arbiter_6_13 : Arbiter + +PORT MAP (Request => Request(157), North => south_2_north(5)(13), West => east_2_west(5)(12), P => Signal_priority(26), Fifo_full => Fifo_full(13), +South => south_2_north(6)(13), East => east_2_west(6)(13) , Grant => Signal_grant(6)(13)); + +Arbiter_6_14 : Arbiter + +PORT MAP (Request => Request(142), North => south_2_north(5)(14), West => east_2_west(5)(13), P => Signal_priority(26), Fifo_full => Fifo_full(14), +South => south_2_north(6)(14), East => east_2_west(6)(14) , Grant => Signal_grant(6)(14)); + +Arbiter_6_15 : Arbiter + +PORT MAP (Request => Request(127), North => south_2_north(5)(15), West => east_2_west(5)(14), P => Signal_priority(26), Fifo_full => Fifo_full(15), +South => south_2_north(6)(15), East => east_2_west(6)(15) , Grant => Signal_grant(6)(15)); + +Arbiter_6_16 : Arbiter + +PORT MAP (Request => Request(112), North => south_2_north(5)(16), West => east_2_west(5)(15), P => Signal_priority(26), Fifo_full => Fifo_full(16), +South => south_2_north(6)(16), East => east_2_west(6)(16) , Grant => Signal_grant(6)(16)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(97), North => south_2_north(6)(1), West => east_2_west(6)(16), P => Signal_priority(25), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(82), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(25), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(67), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(25), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(25), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + +Arbiter_7_5 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(25), Fifo_full => Fifo_full(5), +South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); + +Arbiter_7_6 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(25), Fifo_full => Fifo_full(6), +South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); + +Arbiter_7_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(25), Fifo_full => Fifo_full(7), +South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); + +Arbiter_7_8 : Arbiter + +PORT MAP (Request => Request(248), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(25), Fifo_full => Fifo_full(8), +South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); + +Arbiter_7_9 : Arbiter + +PORT MAP (Request => Request(233), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(25), Fifo_full => Fifo_full(9), +South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); + +Arbiter_7_10 : Arbiter + +PORT MAP (Request => Request(218), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(25), Fifo_full => Fifo_full(10), +South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); + +Arbiter_7_11 : Arbiter + +PORT MAP (Request => Request(203), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(25), Fifo_full => Fifo_full(11), +South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); + +Arbiter_7_12 : Arbiter + +PORT MAP (Request => Request(188), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(25), Fifo_full => Fifo_full(12), +South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); + +Arbiter_7_13 : Arbiter + +PORT MAP (Request => Request(173), North => south_2_north(6)(13), West => east_2_west(6)(12), P => Signal_priority(25), Fifo_full => Fifo_full(13), +South => south_2_north(7)(13), East => east_2_west(7)(13) , Grant => Signal_grant(7)(13)); + +Arbiter_7_14 : Arbiter + +PORT MAP (Request => Request(158), North => south_2_north(6)(14), West => east_2_west(6)(13), P => Signal_priority(25), Fifo_full => Fifo_full(14), +South => south_2_north(7)(14), East => east_2_west(7)(14) , Grant => Signal_grant(7)(14)); + +Arbiter_7_15 : Arbiter + +PORT MAP (Request => Request(143), North => south_2_north(6)(15), West => east_2_west(6)(14), P => Signal_priority(25), Fifo_full => Fifo_full(15), +South => south_2_north(7)(15), East => east_2_west(7)(15) , Grant => Signal_grant(7)(15)); + +Arbiter_7_16 : Arbiter + +PORT MAP (Request => Request(128), North => south_2_north(6)(16), West => east_2_west(6)(15), P => Signal_priority(25), Fifo_full => Fifo_full(16), +South => south_2_north(7)(16), East => east_2_west(7)(16) , Grant => Signal_grant(7)(16)); + +-------------------------- Diagonale n° 8 + + +Arbiter_8_1 : Arbiter + +PORT MAP (Request => Request(113), North => south_2_north(7)(1), West => east_2_west(7)(16), P => Signal_priority(24), Fifo_full => Fifo_full(1), +South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); + +Arbiter_8_2 : Arbiter + +PORT MAP (Request => Request(98), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(24), Fifo_full => Fifo_full(2), +South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); + +Arbiter_8_3 : Arbiter + +PORT MAP (Request => Request(83), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(24), Fifo_full => Fifo_full(3), +South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); + +Arbiter_8_4 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(24), Fifo_full => Fifo_full(4), +South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); + +Arbiter_8_5 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(24), Fifo_full => Fifo_full(5), +South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); + +Arbiter_8_6 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(24), Fifo_full => Fifo_full(6), +South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); + +Arbiter_8_7 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(24), Fifo_full => Fifo_full(7), +South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); + +Arbiter_8_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(24), Fifo_full => Fifo_full(8), +South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); + +Arbiter_8_9 : Arbiter + +PORT MAP (Request => Request(249), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(24), Fifo_full => Fifo_full(9), +South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); + +Arbiter_8_10 : Arbiter + +PORT MAP (Request => Request(234), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(24), Fifo_full => Fifo_full(10), +South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); + +Arbiter_8_11 : Arbiter + +PORT MAP (Request => Request(219), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(24), Fifo_full => Fifo_full(11), +South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); + +Arbiter_8_12 : Arbiter + +PORT MAP (Request => Request(204), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(24), Fifo_full => Fifo_full(12), +South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); + +Arbiter_8_13 : Arbiter + +PORT MAP (Request => Request(189), North => south_2_north(7)(13), West => east_2_west(7)(12), P => Signal_priority(24), Fifo_full => Fifo_full(13), +South => south_2_north(8)(13), East => east_2_west(8)(13) , Grant => Signal_grant(8)(13)); + +Arbiter_8_14 : Arbiter + +PORT MAP (Request => Request(174), North => south_2_north(7)(14), West => east_2_west(7)(13), P => Signal_priority(24), Fifo_full => Fifo_full(14), +South => south_2_north(8)(14), East => east_2_west(8)(14) , Grant => Signal_grant(8)(14)); + +Arbiter_8_15 : Arbiter + +PORT MAP (Request => Request(159), North => south_2_north(7)(15), West => east_2_west(7)(14), P => Signal_priority(24), Fifo_full => Fifo_full(15), +South => south_2_north(8)(15), East => east_2_west(8)(15) , Grant => Signal_grant(8)(15)); + +Arbiter_8_16 : Arbiter + +PORT MAP (Request => Request(144), North => south_2_north(7)(16), West => east_2_west(7)(15), P => Signal_priority(24), Fifo_full => Fifo_full(16), +South => south_2_north(8)(16), East => east_2_west(8)(16) , Grant => Signal_grant(8)(16)); + +-------------------------- Diagonale n° 9 + + +Arbiter_9_1 : Arbiter + +PORT MAP (Request => Request(129), North => south_2_north(8)(1), West => east_2_west(8)(16), P => Signal_priority(23), Fifo_full => Fifo_full(1), +South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); + +Arbiter_9_2 : Arbiter + +PORT MAP (Request => Request(114), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(23), Fifo_full => Fifo_full(2), +South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); + +Arbiter_9_3 : Arbiter + +PORT MAP (Request => Request(99), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(23), Fifo_full => Fifo_full(3), +South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); + +Arbiter_9_4 : Arbiter + +PORT MAP (Request => Request(84), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(23), Fifo_full => Fifo_full(4), +South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); + +Arbiter_9_5 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(23), Fifo_full => Fifo_full(5), +South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); + +Arbiter_9_6 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(23), Fifo_full => Fifo_full(6), +South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); + +Arbiter_9_7 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(23), Fifo_full => Fifo_full(7), +South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); + +Arbiter_9_8 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(23), Fifo_full => Fifo_full(8), +South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); + +Arbiter_9_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(23), Fifo_full => Fifo_full(9), +South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); + +Arbiter_9_10 : Arbiter + +PORT MAP (Request => Request(250), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(23), Fifo_full => Fifo_full(10), +South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); + +Arbiter_9_11 : Arbiter + +PORT MAP (Request => Request(235), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(23), Fifo_full => Fifo_full(11), +South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); + +Arbiter_9_12 : Arbiter + +PORT MAP (Request => Request(220), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(23), Fifo_full => Fifo_full(12), +South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); + +Arbiter_9_13 : Arbiter + +PORT MAP (Request => Request(205), North => south_2_north(8)(13), West => east_2_west(8)(12), P => Signal_priority(23), Fifo_full => Fifo_full(13), +South => south_2_north(9)(13), East => east_2_west(9)(13) , Grant => Signal_grant(9)(13)); + +Arbiter_9_14 : Arbiter + +PORT MAP (Request => Request(190), North => south_2_north(8)(14), West => east_2_west(8)(13), P => Signal_priority(23), Fifo_full => Fifo_full(14), +South => south_2_north(9)(14), East => east_2_west(9)(14) , Grant => Signal_grant(9)(14)); + +Arbiter_9_15 : Arbiter + +PORT MAP (Request => Request(175), North => south_2_north(8)(15), West => east_2_west(8)(14), P => Signal_priority(23), Fifo_full => Fifo_full(15), +South => south_2_north(9)(15), East => east_2_west(9)(15) , Grant => Signal_grant(9)(15)); + +Arbiter_9_16 : Arbiter + +PORT MAP (Request => Request(160), North => south_2_north(8)(16), West => east_2_west(8)(15), P => Signal_priority(23), Fifo_full => Fifo_full(16), +South => south_2_north(9)(16), East => east_2_west(9)(16) , Grant => Signal_grant(9)(16)); + +-------------------------- Diagonale n° 10 + + +Arbiter_10_1 : Arbiter + +PORT MAP (Request => Request(145), North => south_2_north(9)(1), West => east_2_west(9)(16), P => Signal_priority(22), Fifo_full => Fifo_full(1), +South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); + +Arbiter_10_2 : Arbiter + +PORT MAP (Request => Request(130), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2), +South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); + +Arbiter_10_3 : Arbiter + +PORT MAP (Request => Request(115), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3), +South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); + +Arbiter_10_4 : Arbiter + +PORT MAP (Request => Request(100), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4), +South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); + +Arbiter_10_5 : Arbiter + +PORT MAP (Request => Request(85), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5), +South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); + +Arbiter_10_6 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6), +South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); + +Arbiter_10_7 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7), +South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); + +Arbiter_10_8 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8), +South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); + +Arbiter_10_9 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9), +South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); + +Arbiter_10_10 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10), +South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); + +Arbiter_10_11 : Arbiter + +PORT MAP (Request => Request(251), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11), +South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); + +Arbiter_10_12 : Arbiter + +PORT MAP (Request => Request(236), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12), +South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); + +Arbiter_10_13 : Arbiter + +PORT MAP (Request => Request(221), North => south_2_north(9)(13), West => east_2_west(9)(12), P => Signal_priority(22), Fifo_full => Fifo_full(13), +South => south_2_north(10)(13), East => east_2_west(10)(13) , Grant => Signal_grant(10)(13)); + +Arbiter_10_14 : Arbiter + +PORT MAP (Request => Request(206), North => south_2_north(9)(14), West => east_2_west(9)(13), P => Signal_priority(22), Fifo_full => Fifo_full(14), +South => south_2_north(10)(14), East => east_2_west(10)(14) , Grant => Signal_grant(10)(14)); + +Arbiter_10_15 : Arbiter + +PORT MAP (Request => Request(191), North => south_2_north(9)(15), West => east_2_west(9)(14), P => Signal_priority(22), Fifo_full => Fifo_full(15), +South => south_2_north(10)(15), East => east_2_west(10)(15) , Grant => Signal_grant(10)(15)); + +Arbiter_10_16 : Arbiter + +PORT MAP (Request => Request(176), North => south_2_north(9)(16), West => east_2_west(9)(15), P => Signal_priority(22), Fifo_full => Fifo_full(16), +South => south_2_north(10)(16), East => east_2_west(10)(16) , Grant => Signal_grant(10)(16)); + +-------------------------- Diagonale n° 11 + + +Arbiter_11_1 : Arbiter + +PORT MAP (Request => Request(161), North => south_2_north(10)(1), West => east_2_west(10)(16), P => Signal_priority(21), Fifo_full => Fifo_full(1), +South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); + +Arbiter_11_2 : Arbiter + +PORT MAP (Request => Request(146), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2), +South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); + +Arbiter_11_3 : Arbiter + +PORT MAP (Request => Request(131), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3), +South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); + +Arbiter_11_4 : Arbiter + +PORT MAP (Request => Request(116), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4), +South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); + +Arbiter_11_5 : Arbiter + +PORT MAP (Request => Request(101), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5), +South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); + +Arbiter_11_6 : Arbiter + +PORT MAP (Request => Request(86), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6), +South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); + +Arbiter_11_7 : Arbiter + +PORT MAP (Request => Request(71), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7), +South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); + +Arbiter_11_8 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8), +South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); + +Arbiter_11_9 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9), +South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); + +Arbiter_11_10 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10), +South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); + +Arbiter_11_11 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11), +South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); + +Arbiter_11_12 : Arbiter + +PORT MAP (Request => Request(252), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12), +South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); + +Arbiter_11_13 : Arbiter + +PORT MAP (Request => Request(237), North => south_2_north(10)(13), West => east_2_west(10)(12), P => Signal_priority(21), Fifo_full => Fifo_full(13), +South => south_2_north(11)(13), East => east_2_west(11)(13) , Grant => Signal_grant(11)(13)); + +Arbiter_11_14 : Arbiter + +PORT MAP (Request => Request(222), North => south_2_north(10)(14), West => east_2_west(10)(13), P => Signal_priority(21), Fifo_full => Fifo_full(14), +South => south_2_north(11)(14), East => east_2_west(11)(14) , Grant => Signal_grant(11)(14)); + +Arbiter_11_15 : Arbiter + +PORT MAP (Request => Request(207), North => south_2_north(10)(15), West => east_2_west(10)(14), P => Signal_priority(21), Fifo_full => Fifo_full(15), +South => south_2_north(11)(15), East => east_2_west(11)(15) , Grant => Signal_grant(11)(15)); + +Arbiter_11_16 : Arbiter + +PORT MAP (Request => Request(192), North => south_2_north(10)(16), West => east_2_west(10)(15), P => Signal_priority(21), Fifo_full => Fifo_full(16), +South => south_2_north(11)(16), East => east_2_west(11)(16) , Grant => Signal_grant(11)(16)); + +-------------------------- Diagonale n° 12 + + +Arbiter_12_1 : Arbiter + +PORT MAP (Request => Request(177), North => south_2_north(11)(1), West => east_2_west(11)(16), P => Signal_priority(20), Fifo_full => Fifo_full(1), +South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); + +Arbiter_12_2 : Arbiter + +PORT MAP (Request => Request(162), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2), +South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); + +Arbiter_12_3 : Arbiter + +PORT MAP (Request => Request(147), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3), +South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); + +Arbiter_12_4 : Arbiter + +PORT MAP (Request => Request(132), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4), +South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); + +Arbiter_12_5 : Arbiter + +PORT MAP (Request => Request(117), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5), +South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); + +Arbiter_12_6 : Arbiter + +PORT MAP (Request => Request(102), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6), +South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); + +Arbiter_12_7 : Arbiter + +PORT MAP (Request => Request(87), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7), +South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); + +Arbiter_12_8 : Arbiter + +PORT MAP (Request => Request(72), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8), +South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); + +Arbiter_12_9 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9), +South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); + +Arbiter_12_10 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10), +South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); + +Arbiter_12_11 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11), +South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); + +Arbiter_12_12 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12), +South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); + +Arbiter_12_13 : Arbiter + +PORT MAP (Request => Request(253), North => south_2_north(11)(13), West => east_2_west(11)(12), P => Signal_priority(20), Fifo_full => Fifo_full(13), +South => south_2_north(12)(13), East => east_2_west(12)(13) , Grant => Signal_grant(12)(13)); + +Arbiter_12_14 : Arbiter + +PORT MAP (Request => Request(238), North => south_2_north(11)(14), West => east_2_west(11)(13), P => Signal_priority(20), Fifo_full => Fifo_full(14), +South => south_2_north(12)(14), East => east_2_west(12)(14) , Grant => Signal_grant(12)(14)); + +Arbiter_12_15 : Arbiter + +PORT MAP (Request => Request(223), North => south_2_north(11)(15), West => east_2_west(11)(14), P => Signal_priority(20), Fifo_full => Fifo_full(15), +South => south_2_north(12)(15), East => east_2_west(12)(15) , Grant => Signal_grant(12)(15)); + +Arbiter_12_16 : Arbiter + +PORT MAP (Request => Request(208), North => south_2_north(11)(16), West => east_2_west(11)(15), P => Signal_priority(20), Fifo_full => Fifo_full(16), +South => south_2_north(12)(16), East => east_2_west(12)(16) , Grant => Signal_grant(12)(16)); + +-------------------------- Diagonale n° 13 + + +Arbiter_13_1 : Arbiter + +PORT MAP (Request => Request(193), North => south_2_north(12)(1), West => east_2_west(12)(16), P => Signal_priority(19), Fifo_full => Fifo_full(1), +South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); + +Arbiter_13_2 : Arbiter + +PORT MAP (Request => Request(178), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2), +South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); + +Arbiter_13_3 : Arbiter + +PORT MAP (Request => Request(163), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3), +South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); + +Arbiter_13_4 : Arbiter + +PORT MAP (Request => Request(148), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4), +South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); + +Arbiter_13_5 : Arbiter + +PORT MAP (Request => Request(133), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5), +South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); + +Arbiter_13_6 : Arbiter + +PORT MAP (Request => Request(118), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6), +South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); + +Arbiter_13_7 : Arbiter + +PORT MAP (Request => Request(103), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7), +South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); + +Arbiter_13_8 : Arbiter + +PORT MAP (Request => Request(88), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8), +South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); + +Arbiter_13_9 : Arbiter + +PORT MAP (Request => Request(73), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9), +South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); + +Arbiter_13_10 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10), +South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); + +Arbiter_13_11 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11), +South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); + +Arbiter_13_12 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12), +South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); + +Arbiter_13_13 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(12)(13), West => east_2_west(12)(12), P => Signal_priority(19), Fifo_full => Fifo_full(13), +South => south_2_north(13)(13), East => east_2_west(13)(13) , Grant => Signal_grant(13)(13)); + +Arbiter_13_14 : Arbiter + +PORT MAP (Request => Request(254), North => south_2_north(12)(14), West => east_2_west(12)(13), P => Signal_priority(19), Fifo_full => Fifo_full(14), +South => south_2_north(13)(14), East => east_2_west(13)(14) , Grant => Signal_grant(13)(14)); + +Arbiter_13_15 : Arbiter + +PORT MAP (Request => Request(239), North => south_2_north(12)(15), West => east_2_west(12)(14), P => Signal_priority(19), Fifo_full => Fifo_full(15), +South => south_2_north(13)(15), East => east_2_west(13)(15) , Grant => Signal_grant(13)(15)); + +Arbiter_13_16 : Arbiter + +PORT MAP (Request => Request(224), North => south_2_north(12)(16), West => east_2_west(12)(15), P => Signal_priority(19), Fifo_full => Fifo_full(16), +South => south_2_north(13)(16), East => east_2_west(13)(16) , Grant => Signal_grant(13)(16)); + +-------------------------- Diagonale n° 14 + + +Arbiter_14_1 : Arbiter + +PORT MAP (Request => Request(209), North => south_2_north(13)(1), West => east_2_west(13)(16), P => Signal_priority(18), Fifo_full => Fifo_full(1), +South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); + +Arbiter_14_2 : Arbiter + +PORT MAP (Request => Request(194), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2), +South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); + +Arbiter_14_3 : Arbiter + +PORT MAP (Request => Request(179), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3), +South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); + +Arbiter_14_4 : Arbiter + +PORT MAP (Request => Request(164), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4), +South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); + +Arbiter_14_5 : Arbiter + +PORT MAP (Request => Request(149), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5), +South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); + +Arbiter_14_6 : Arbiter + +PORT MAP (Request => Request(134), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6), +South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); + +Arbiter_14_7 : Arbiter + +PORT MAP (Request => Request(119), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7), +South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); + +Arbiter_14_8 : Arbiter + +PORT MAP (Request => Request(104), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8), +South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); + +Arbiter_14_9 : Arbiter + +PORT MAP (Request => Request(89), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9), +South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); + +Arbiter_14_10 : Arbiter + +PORT MAP (Request => Request(74), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10), +South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); + +Arbiter_14_11 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11), +South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); + +Arbiter_14_12 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12), +South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); + +Arbiter_14_13 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(13)(13), West => east_2_west(13)(12), P => Signal_priority(18), Fifo_full => Fifo_full(13), +South => south_2_north(14)(13), East => east_2_west(14)(13) , Grant => Signal_grant(14)(13)); + +Arbiter_14_14 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(13)(14), West => east_2_west(13)(13), P => Signal_priority(18), Fifo_full => Fifo_full(14), +South => south_2_north(14)(14), East => east_2_west(14)(14) , Grant => Signal_grant(14)(14)); + +Arbiter_14_15 : Arbiter + +PORT MAP (Request => Request(255), North => south_2_north(13)(15), West => east_2_west(13)(14), P => Signal_priority(18), Fifo_full => Fifo_full(15), +South => south_2_north(14)(15), East => east_2_west(14)(15) , Grant => Signal_grant(14)(15)); + +Arbiter_14_16 : Arbiter + +PORT MAP (Request => Request(240), North => south_2_north(13)(16), West => east_2_west(13)(15), P => Signal_priority(18), Fifo_full => Fifo_full(16), +South => south_2_north(14)(16), East => east_2_west(14)(16) , Grant => Signal_grant(14)(16)); + +-------------------------- Diagonale n° 15 + + +Arbiter_15_1 : Arbiter + +PORT MAP (Request => Request(225), North => south_2_north(14)(1), West => east_2_west(14)(16), P => Signal_priority(17), Fifo_full => Fifo_full(1), +South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); + +Arbiter_15_2 : Arbiter + +PORT MAP (Request => Request(210), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2), +South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); + +Arbiter_15_3 : Arbiter + +PORT MAP (Request => Request(195), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3), +South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); + +Arbiter_15_4 : Arbiter + +PORT MAP (Request => Request(180), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4), +South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); + +Arbiter_15_5 : Arbiter + +PORT MAP (Request => Request(165), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5), +South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); + +Arbiter_15_6 : Arbiter + +PORT MAP (Request => Request(150), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6), +South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); + +Arbiter_15_7 : Arbiter + +PORT MAP (Request => Request(135), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7), +South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); + +Arbiter_15_8 : Arbiter + +PORT MAP (Request => Request(120), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8), +South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); + +Arbiter_15_9 : Arbiter + +PORT MAP (Request => Request(105), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9), +South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); + +Arbiter_15_10 : Arbiter + +PORT MAP (Request => Request(90), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10), +South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); + +Arbiter_15_11 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11), +South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); + +Arbiter_15_12 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12), +South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); + +Arbiter_15_13 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(14)(13), West => east_2_west(14)(12), P => Signal_priority(17), Fifo_full => Fifo_full(13), +South => south_2_north(15)(13), East => east_2_west(15)(13) , Grant => Signal_grant(15)(13)); + +Arbiter_15_14 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(14)(14), West => east_2_west(14)(13), P => Signal_priority(17), Fifo_full => Fifo_full(14), +South => south_2_north(15)(14), East => east_2_west(15)(14) , Grant => Signal_grant(15)(14)); + +Arbiter_15_15 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(14)(15), West => east_2_west(14)(14), P => Signal_priority(17), Fifo_full => Fifo_full(15), +South => south_2_north(15)(15), East => east_2_west(15)(15) , Grant => Signal_grant(15)(15)); + +Arbiter_15_16 : Arbiter + +PORT MAP (Request => Request(256), North => south_2_north(14)(16), West => east_2_west(14)(15), P => Signal_priority(17), Fifo_full => Fifo_full(16), +South => south_2_north(15)(16), East => east_2_west(15)(16) , Grant => Signal_grant(15)(16)); + +-------------------------- Diagonale n° 16 + + +Arbiter_16_1 : Arbiter + +PORT MAP (Request => Request(241), North => south_2_north(15)(1), West => east_2_west(15)(16), P => Signal_priority(16), Fifo_full => Fifo_full(1), +South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); + +Arbiter_16_2 : Arbiter + +PORT MAP (Request => Request(226), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2), +South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); + +Arbiter_16_3 : Arbiter + +PORT MAP (Request => Request(211), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3), +South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); + +Arbiter_16_4 : Arbiter + +PORT MAP (Request => Request(196), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4), +South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); + +Arbiter_16_5 : Arbiter + +PORT MAP (Request => Request(181), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5), +South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); + +Arbiter_16_6 : Arbiter + +PORT MAP (Request => Request(166), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6), +South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); + +Arbiter_16_7 : Arbiter + +PORT MAP (Request => Request(151), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7), +South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); + +Arbiter_16_8 : Arbiter + +PORT MAP (Request => Request(136), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8), +South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); + +Arbiter_16_9 : Arbiter + +PORT MAP (Request => Request(121), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9), +South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); + +Arbiter_16_10 : Arbiter + +PORT MAP (Request => Request(106), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10), +South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); + +Arbiter_16_11 : Arbiter + +PORT MAP (Request => Request(91), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11), +South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); + +Arbiter_16_12 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12), +South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); + +Arbiter_16_13 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(15)(13), West => east_2_west(15)(12), P => Signal_priority(16), Fifo_full => Fifo_full(13), +South => south_2_north(16)(13), East => east_2_west(16)(13) , Grant => Signal_grant(16)(13)); + +Arbiter_16_14 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(15)(14), West => east_2_west(15)(13), P => Signal_priority(16), Fifo_full => Fifo_full(14), +South => south_2_north(16)(14), East => east_2_west(16)(14) , Grant => Signal_grant(16)(14)); + +Arbiter_16_15 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(15)(15), West => east_2_west(15)(14), P => Signal_priority(16), Fifo_full => Fifo_full(15), +South => south_2_north(16)(15), East => east_2_west(16)(15) , Grant => Signal_grant(16)(15)); + +Arbiter_16_16 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(15)(16), West => east_2_west(15)(15), P => Signal_priority(16), Fifo_full => Fifo_full(16), +South => south_2_north(16)(16), East => east_2_west(16)(16) , Grant => Signal_grant(16)(16)); + +-------------------------- Diagonale n° 17 + + +Arbiter_17_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(16)(1), West => east_2_west(16)(16), P => Signal_priority(15), Fifo_full => Fifo_full(1), +South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); + +Arbiter_17_2 : Arbiter + +PORT MAP (Request => Request(242), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2), +South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); + +Arbiter_17_3 : Arbiter + +PORT MAP (Request => Request(227), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3), +South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); + +Arbiter_17_4 : Arbiter + +PORT MAP (Request => Request(212), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4), +South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); + +Arbiter_17_5 : Arbiter + +PORT MAP (Request => Request(197), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5), +South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); + +Arbiter_17_6 : Arbiter + +PORT MAP (Request => Request(182), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6), +South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); + +Arbiter_17_7 : Arbiter + +PORT MAP (Request => Request(167), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7), +South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); + +Arbiter_17_8 : Arbiter + +PORT MAP (Request => Request(152), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8), +South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); + +Arbiter_17_9 : Arbiter + +PORT MAP (Request => Request(137), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9), +South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); + +Arbiter_17_10 : Arbiter + +PORT MAP (Request => Request(122), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10), +South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); + +Arbiter_17_11 : Arbiter + +PORT MAP (Request => Request(107), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11), +South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); + +Arbiter_17_12 : Arbiter + +PORT MAP (Request => Request(92), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12), +South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); + +Arbiter_17_13 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(16)(13), West => east_2_west(16)(12), P => Signal_priority(15), Fifo_full => Fifo_full(13), +South => south_2_north(17)(13), East => east_2_west(17)(13) , Grant => Signal_grant(17)(13)); + +Arbiter_17_14 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(16)(14), West => east_2_west(16)(13), P => Signal_priority(15), Fifo_full => Fifo_full(14), +South => south_2_north(17)(14), East => east_2_west(17)(14) , Grant => Signal_grant(17)(14)); + +Arbiter_17_15 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(16)(15), West => east_2_west(16)(14), P => Signal_priority(15), Fifo_full => Fifo_full(15), +South => south_2_north(17)(15), East => east_2_west(17)(15) , Grant => Signal_grant(17)(15)); + +Arbiter_17_16 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(16)(16), West => east_2_west(16)(15), P => Signal_priority(15), Fifo_full => Fifo_full(16), +South => south_2_north(17)(16), East => east_2_west(17)(16) , Grant => Signal_grant(17)(16)); + +-------------------------- Diagonale n° 18 + + +Arbiter_18_1 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(17)(1), West => east_2_west(17)(16), P => Signal_priority(14), Fifo_full => Fifo_full(1), +South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); + +Arbiter_18_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2), +South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); + +Arbiter_18_3 : Arbiter + +PORT MAP (Request => Request(243), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3), +South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); + +Arbiter_18_4 : Arbiter + +PORT MAP (Request => Request(228), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4), +South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); + +Arbiter_18_5 : Arbiter + +PORT MAP (Request => Request(213), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5), +South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); + +Arbiter_18_6 : Arbiter + +PORT MAP (Request => Request(198), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6), +South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); + +Arbiter_18_7 : Arbiter + +PORT MAP (Request => Request(183), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7), +South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); + +Arbiter_18_8 : Arbiter + +PORT MAP (Request => Request(168), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8), +South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); + +Arbiter_18_9 : Arbiter + +PORT MAP (Request => Request(153), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9), +South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); + +Arbiter_18_10 : Arbiter + +PORT MAP (Request => Request(138), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10), +South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); + +Arbiter_18_11 : Arbiter + +PORT MAP (Request => Request(123), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11), +South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); + +Arbiter_18_12 : Arbiter + +PORT MAP (Request => Request(108), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12), +South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); + +Arbiter_18_13 : Arbiter + +PORT MAP (Request => Request(93), North => south_2_north(17)(13), West => east_2_west(17)(12), P => Signal_priority(14), Fifo_full => Fifo_full(13), +South => south_2_north(18)(13), East => east_2_west(18)(13) , Grant => Signal_grant(18)(13)); + +Arbiter_18_14 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(17)(14), West => east_2_west(17)(13), P => Signal_priority(14), Fifo_full => Fifo_full(14), +South => south_2_north(18)(14), East => east_2_west(18)(14) , Grant => Signal_grant(18)(14)); + +Arbiter_18_15 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(17)(15), West => east_2_west(17)(14), P => Signal_priority(14), Fifo_full => Fifo_full(15), +South => south_2_north(18)(15), East => east_2_west(18)(15) , Grant => Signal_grant(18)(15)); + +Arbiter_18_16 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(17)(16), West => east_2_west(17)(15), P => Signal_priority(14), Fifo_full => Fifo_full(16), +South => south_2_north(18)(16), East => east_2_west(18)(16) , Grant => Signal_grant(18)(16)); + +-------------------------- Diagonale n° 19 + + +Arbiter_19_1 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(18)(1), West => east_2_west(18)(16), P => Signal_priority(13), Fifo_full => Fifo_full(1), +South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); + +Arbiter_19_2 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2), +South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); + +Arbiter_19_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3), +South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); + +Arbiter_19_4 : Arbiter + +PORT MAP (Request => Request(244), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4), +South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); + +Arbiter_19_5 : Arbiter + +PORT MAP (Request => Request(229), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5), +South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); + +Arbiter_19_6 : Arbiter + +PORT MAP (Request => Request(214), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6), +South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); + +Arbiter_19_7 : Arbiter + +PORT MAP (Request => Request(199), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7), +South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); + +Arbiter_19_8 : Arbiter + +PORT MAP (Request => Request(184), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8), +South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); + +Arbiter_19_9 : Arbiter + +PORT MAP (Request => Request(169), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9), +South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); + +Arbiter_19_10 : Arbiter + +PORT MAP (Request => Request(154), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10), +South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); + +Arbiter_19_11 : Arbiter + +PORT MAP (Request => Request(139), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11), +South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); + +Arbiter_19_12 : Arbiter + +PORT MAP (Request => Request(124), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12), +South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); + +Arbiter_19_13 : Arbiter + +PORT MAP (Request => Request(109), North => south_2_north(18)(13), West => east_2_west(18)(12), P => Signal_priority(13), Fifo_full => Fifo_full(13), +South => south_2_north(19)(13), East => east_2_west(19)(13) , Grant => Signal_grant(19)(13)); + +Arbiter_19_14 : Arbiter + +PORT MAP (Request => Request(94), North => south_2_north(18)(14), West => east_2_west(18)(13), P => Signal_priority(13), Fifo_full => Fifo_full(14), +South => south_2_north(19)(14), East => east_2_west(19)(14) , Grant => Signal_grant(19)(14)); + +Arbiter_19_15 : Arbiter + +PORT MAP (Request => Request(79), North => south_2_north(18)(15), West => east_2_west(18)(14), P => Signal_priority(13), Fifo_full => Fifo_full(15), +South => south_2_north(19)(15), East => east_2_west(19)(15) , Grant => Signal_grant(19)(15)); + +Arbiter_19_16 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(18)(16), West => east_2_west(18)(15), P => Signal_priority(13), Fifo_full => Fifo_full(16), +South => south_2_north(19)(16), East => east_2_west(19)(16) , Grant => Signal_grant(19)(16)); + +-------------------------- Diagonale n° 20 + + +Arbiter_20_1 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(19)(1), West => east_2_west(19)(16), P => Signal_priority(12), Fifo_full => Fifo_full(1), +South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); + +Arbiter_20_2 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2), +South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); + +Arbiter_20_3 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3), +South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); + +Arbiter_20_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4), +South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); + +Arbiter_20_5 : Arbiter + +PORT MAP (Request => Request(245), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5), +South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); + +Arbiter_20_6 : Arbiter + +PORT MAP (Request => Request(230), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6), +South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); + +Arbiter_20_7 : Arbiter + +PORT MAP (Request => Request(215), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7), +South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); + +Arbiter_20_8 : Arbiter + +PORT MAP (Request => Request(200), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8), +South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); + +Arbiter_20_9 : Arbiter + +PORT MAP (Request => Request(185), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9), +South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); + +Arbiter_20_10 : Arbiter + +PORT MAP (Request => Request(170), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10), +South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); + +Arbiter_20_11 : Arbiter + +PORT MAP (Request => Request(155), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11), +South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); + +Arbiter_20_12 : Arbiter + +PORT MAP (Request => Request(140), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12), +South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); + +Arbiter_20_13 : Arbiter + +PORT MAP (Request => Request(125), North => south_2_north(19)(13), West => east_2_west(19)(12), P => Signal_priority(12), Fifo_full => Fifo_full(13), +South => south_2_north(20)(13), East => east_2_west(20)(13) , Grant => Signal_grant(20)(13)); + +Arbiter_20_14 : Arbiter + +PORT MAP (Request => Request(110), North => south_2_north(19)(14), West => east_2_west(19)(13), P => Signal_priority(12), Fifo_full => Fifo_full(14), +South => south_2_north(20)(14), East => east_2_west(20)(14) , Grant => Signal_grant(20)(14)); + +Arbiter_20_15 : Arbiter + +PORT MAP (Request => Request(95), North => south_2_north(19)(15), West => east_2_west(19)(14), P => Signal_priority(12), Fifo_full => Fifo_full(15), +South => south_2_north(20)(15), East => east_2_west(20)(15) , Grant => Signal_grant(20)(15)); + +Arbiter_20_16 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(19)(16), West => east_2_west(19)(15), P => Signal_priority(12), Fifo_full => Fifo_full(16), +South => south_2_north(20)(16), East => east_2_west(20)(16) , Grant => Signal_grant(20)(16)); + +-------------------------- Diagonale n° 21 + + +Arbiter_21_1 : Arbiter + +PORT MAP (Request => Request(65), North => south_2_north(20)(1), West => east_2_west(20)(16), P => Signal_priority(11), Fifo_full => Fifo_full(1), +South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); + +Arbiter_21_2 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2), +South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); + +Arbiter_21_3 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3), +South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); + +Arbiter_21_4 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4), +South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); + +Arbiter_21_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5), +South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); + +Arbiter_21_6 : Arbiter + +PORT MAP (Request => Request(246), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6), +South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); + +Arbiter_21_7 : Arbiter + +PORT MAP (Request => Request(231), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7), +South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); + +Arbiter_21_8 : Arbiter + +PORT MAP (Request => Request(216), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8), +South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); + +Arbiter_21_9 : Arbiter + +PORT MAP (Request => Request(201), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9), +South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); + +Arbiter_21_10 : Arbiter + +PORT MAP (Request => Request(186), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10), +South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); + +Arbiter_21_11 : Arbiter + +PORT MAP (Request => Request(171), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11), +South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); + +Arbiter_21_12 : Arbiter + +PORT MAP (Request => Request(156), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12), +South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); + +Arbiter_21_13 : Arbiter + +PORT MAP (Request => Request(141), North => south_2_north(20)(13), West => east_2_west(20)(12), P => Signal_priority(11), Fifo_full => Fifo_full(13), +South => south_2_north(21)(13), East => east_2_west(21)(13) , Grant => Signal_grant(21)(13)); + +Arbiter_21_14 : Arbiter + +PORT MAP (Request => Request(126), North => south_2_north(20)(14), West => east_2_west(20)(13), P => Signal_priority(11), Fifo_full => Fifo_full(14), +South => south_2_north(21)(14), East => east_2_west(21)(14) , Grant => Signal_grant(21)(14)); + +Arbiter_21_15 : Arbiter + +PORT MAP (Request => Request(111), North => south_2_north(20)(15), West => east_2_west(20)(14), P => Signal_priority(11), Fifo_full => Fifo_full(15), +South => south_2_north(21)(15), East => east_2_west(21)(15) , Grant => Signal_grant(21)(15)); + +Arbiter_21_16 : Arbiter + +PORT MAP (Request => Request(96), North => south_2_north(20)(16), West => east_2_west(20)(15), P => Signal_priority(11), Fifo_full => Fifo_full(16), +South => south_2_north(21)(16), East => east_2_west(21)(16) , Grant => Signal_grant(21)(16)); + +-------------------------- Diagonale n° 22 + + +Arbiter_22_1 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(21)(1), West => east_2_west(21)(16), P => Signal_priority(10), Fifo_full => Fifo_full(1), +South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); + +Arbiter_22_2 : Arbiter + +PORT MAP (Request => Request(66), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2), +South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); + +Arbiter_22_3 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3), +South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); + +Arbiter_22_4 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4), +South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); + +Arbiter_22_5 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5), +South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); + +Arbiter_22_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6), +South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); + +Arbiter_22_7 : Arbiter + +PORT MAP (Request => Request(247), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7), +South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); + +Arbiter_22_8 : Arbiter + +PORT MAP (Request => Request(232), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8), +South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); + +Arbiter_22_9 : Arbiter + +PORT MAP (Request => Request(217), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9), +South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); + +Arbiter_22_10 : Arbiter + +PORT MAP (Request => Request(202), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10), +South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); + +Arbiter_22_11 : Arbiter + +PORT MAP (Request => Request(187), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11), +South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); + +Arbiter_22_12 : Arbiter + +PORT MAP (Request => Request(172), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12), +South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); + +Arbiter_22_13 : Arbiter + +PORT MAP (Request => Request(157), North => south_2_north(21)(13), West => east_2_west(21)(12), P => Signal_priority(10), Fifo_full => Fifo_full(13), +South => south_2_north(22)(13), East => east_2_west(22)(13) , Grant => Signal_grant(22)(13)); + +Arbiter_22_14 : Arbiter + +PORT MAP (Request => Request(142), North => south_2_north(21)(14), West => east_2_west(21)(13), P => Signal_priority(10), Fifo_full => Fifo_full(14), +South => south_2_north(22)(14), East => east_2_west(22)(14) , Grant => Signal_grant(22)(14)); + +Arbiter_22_15 : Arbiter + +PORT MAP (Request => Request(127), North => south_2_north(21)(15), West => east_2_west(21)(14), P => Signal_priority(10), Fifo_full => Fifo_full(15), +South => south_2_north(22)(15), East => east_2_west(22)(15) , Grant => Signal_grant(22)(15)); + +Arbiter_22_16 : Arbiter + +PORT MAP (Request => Request(112), North => south_2_north(21)(16), West => east_2_west(21)(15), P => Signal_priority(10), Fifo_full => Fifo_full(16), +South => south_2_north(22)(16), East => east_2_west(22)(16) , Grant => Signal_grant(22)(16)); + +-------------------------- Diagonale n° 23 + + +Arbiter_23_1 : Arbiter + +PORT MAP (Request => Request(97), North => south_2_north(22)(1), West => east_2_west(22)(16), P => Signal_priority(9), Fifo_full => Fifo_full(1), +South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); + +Arbiter_23_2 : Arbiter + +PORT MAP (Request => Request(82), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2), +South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); + +Arbiter_23_3 : Arbiter + +PORT MAP (Request => Request(67), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3), +South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); + +Arbiter_23_4 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4), +South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); + +Arbiter_23_5 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5), +South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); + +Arbiter_23_6 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6), +South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); + +Arbiter_23_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7), +South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); + +Arbiter_23_8 : Arbiter + +PORT MAP (Request => Request(248), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8), +South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); + +Arbiter_23_9 : Arbiter + +PORT MAP (Request => Request(233), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9), +South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); + +Arbiter_23_10 : Arbiter + +PORT MAP (Request => Request(218), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10), +South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); + +Arbiter_23_11 : Arbiter + +PORT MAP (Request => Request(203), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11), +South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); + +Arbiter_23_12 : Arbiter + +PORT MAP (Request => Request(188), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12), +South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); + +Arbiter_23_13 : Arbiter + +PORT MAP (Request => Request(173), North => south_2_north(22)(13), West => east_2_west(22)(12), P => Signal_priority(9), Fifo_full => Fifo_full(13), +South => south_2_north(23)(13), East => east_2_west(23)(13) , Grant => Signal_grant(23)(13)); + +Arbiter_23_14 : Arbiter + +PORT MAP (Request => Request(158), North => south_2_north(22)(14), West => east_2_west(22)(13), P => Signal_priority(9), Fifo_full => Fifo_full(14), +South => south_2_north(23)(14), East => east_2_west(23)(14) , Grant => Signal_grant(23)(14)); + +Arbiter_23_15 : Arbiter + +PORT MAP (Request => Request(143), North => south_2_north(22)(15), West => east_2_west(22)(14), P => Signal_priority(9), Fifo_full => Fifo_full(15), +South => south_2_north(23)(15), East => east_2_west(23)(15) , Grant => Signal_grant(23)(15)); + +Arbiter_23_16 : Arbiter + +PORT MAP (Request => Request(128), North => south_2_north(22)(16), West => east_2_west(22)(15), P => Signal_priority(9), Fifo_full => Fifo_full(16), +South => south_2_north(23)(16), East => east_2_west(23)(16) , Grant => Signal_grant(23)(16)); + +-------------------------- Diagonale n° 24 + + +Arbiter_24_1 : Arbiter + +PORT MAP (Request => Request(113), North => south_2_north(23)(1), West => east_2_west(23)(16), P => Signal_priority(8), Fifo_full => Fifo_full(1), +South => south_2_north(24)(1), East => east_2_west(24)(1) , Grant => Signal_grant(24)(1)); + +Arbiter_24_2 : Arbiter + +PORT MAP (Request => Request(98), North => south_2_north(23)(2), West => east_2_west(23)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2), +South => south_2_north(24)(2), East => east_2_west(24)(2) , Grant => Signal_grant(24)(2)); + +Arbiter_24_3 : Arbiter + +PORT MAP (Request => Request(83), North => south_2_north(23)(3), West => east_2_west(23)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3), +South => south_2_north(24)(3), East => east_2_west(24)(3) , Grant => Signal_grant(24)(3)); + +Arbiter_24_4 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(23)(4), West => east_2_west(23)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4), +South => south_2_north(24)(4), East => east_2_west(24)(4) , Grant => Signal_grant(24)(4)); + +Arbiter_24_5 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(23)(5), West => east_2_west(23)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5), +South => south_2_north(24)(5), East => east_2_west(24)(5) , Grant => Signal_grant(24)(5)); + +Arbiter_24_6 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(23)(6), West => east_2_west(23)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6), +South => south_2_north(24)(6), East => east_2_west(24)(6) , Grant => Signal_grant(24)(6)); + +Arbiter_24_7 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(23)(7), West => east_2_west(23)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7), +South => south_2_north(24)(7), East => east_2_west(24)(7) , Grant => Signal_grant(24)(7)); + +Arbiter_24_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(23)(8), West => east_2_west(23)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8), +South => south_2_north(24)(8), East => east_2_west(24)(8) , Grant => Signal_grant(24)(8)); + +Arbiter_24_9 : Arbiter + +PORT MAP (Request => Request(249), North => south_2_north(23)(9), West => east_2_west(23)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9), +South => south_2_north(24)(9), East => east_2_west(24)(9) , Grant => Signal_grant(24)(9)); + +Arbiter_24_10 : Arbiter + +PORT MAP (Request => Request(234), North => south_2_north(23)(10), West => east_2_west(23)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10), +South => south_2_north(24)(10), East => east_2_west(24)(10) , Grant => Signal_grant(24)(10)); + +Arbiter_24_11 : Arbiter + +PORT MAP (Request => Request(219), North => south_2_north(23)(11), West => east_2_west(23)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11), +South => south_2_north(24)(11), East => east_2_west(24)(11) , Grant => Signal_grant(24)(11)); + +Arbiter_24_12 : Arbiter + +PORT MAP (Request => Request(204), North => south_2_north(23)(12), West => east_2_west(23)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12), +South => south_2_north(24)(12), East => east_2_west(24)(12) , Grant => Signal_grant(24)(12)); + +Arbiter_24_13 : Arbiter + +PORT MAP (Request => Request(189), North => south_2_north(23)(13), West => east_2_west(23)(12), P => Signal_priority(8), Fifo_full => Fifo_full(13), +South => south_2_north(24)(13), East => east_2_west(24)(13) , Grant => Signal_grant(24)(13)); + +Arbiter_24_14 : Arbiter + +PORT MAP (Request => Request(174), North => south_2_north(23)(14), West => east_2_west(23)(13), P => Signal_priority(8), Fifo_full => Fifo_full(14), +South => south_2_north(24)(14), East => east_2_west(24)(14) , Grant => Signal_grant(24)(14)); + +Arbiter_24_15 : Arbiter + +PORT MAP (Request => Request(159), North => south_2_north(23)(15), West => east_2_west(23)(14), P => Signal_priority(8), Fifo_full => Fifo_full(15), +South => south_2_north(24)(15), East => east_2_west(24)(15) , Grant => Signal_grant(24)(15)); + +Arbiter_24_16 : Arbiter + +PORT MAP (Request => Request(144), North => south_2_north(23)(16), West => east_2_west(23)(15), P => Signal_priority(8), Fifo_full => Fifo_full(16), +South => south_2_north(24)(16), East => east_2_west(24)(16) , Grant => Signal_grant(24)(16)); + +-------------------------- Diagonale n° 25 + + +Arbiter_25_1 : Arbiter + +PORT MAP (Request => Request(129), North => south_2_north(24)(1), West => east_2_west(24)(16), P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(25)(1), East => east_2_west(25)(1) , Grant => Signal_grant(25)(1)); + +Arbiter_25_2 : Arbiter + +PORT MAP (Request => Request(114), North => south_2_north(24)(2), West => east_2_west(24)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(25)(2), East => east_2_west(25)(2) , Grant => Signal_grant(25)(2)); + +Arbiter_25_3 : Arbiter + +PORT MAP (Request => Request(99), North => south_2_north(24)(3), West => east_2_west(24)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(25)(3), East => east_2_west(25)(3) , Grant => Signal_grant(25)(3)); + +Arbiter_25_4 : Arbiter + +PORT MAP (Request => Request(84), North => south_2_north(24)(4), West => east_2_west(24)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(25)(4), East => east_2_west(25)(4) , Grant => Signal_grant(25)(4)); + +Arbiter_25_5 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(24)(5), West => east_2_west(24)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5), +South => south_2_north(25)(5), East => east_2_west(25)(5) , Grant => Signal_grant(25)(5)); + +Arbiter_25_6 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(24)(6), West => east_2_west(24)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6), +South => south_2_north(25)(6), East => east_2_west(25)(6) , Grant => Signal_grant(25)(6)); + +Arbiter_25_7 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(24)(7), West => east_2_west(24)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7), +South => south_2_north(25)(7), East => east_2_west(25)(7) , Grant => Signal_grant(25)(7)); + +Arbiter_25_8 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(24)(8), West => east_2_west(24)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8), +South => south_2_north(25)(8), East => east_2_west(25)(8) , Grant => Signal_grant(25)(8)); + +Arbiter_25_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(24)(9), West => east_2_west(24)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9), +South => south_2_north(25)(9), East => east_2_west(25)(9) , Grant => Signal_grant(25)(9)); + +Arbiter_25_10 : Arbiter + +PORT MAP (Request => Request(250), North => south_2_north(24)(10), West => east_2_west(24)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10), +South => south_2_north(25)(10), East => east_2_west(25)(10) , Grant => Signal_grant(25)(10)); + +Arbiter_25_11 : Arbiter + +PORT MAP (Request => Request(235), North => south_2_north(24)(11), West => east_2_west(24)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11), +South => south_2_north(25)(11), East => east_2_west(25)(11) , Grant => Signal_grant(25)(11)); + +Arbiter_25_12 : Arbiter + +PORT MAP (Request => Request(220), North => south_2_north(24)(12), West => east_2_west(24)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12), +South => south_2_north(25)(12), East => east_2_west(25)(12) , Grant => Signal_grant(25)(12)); + +Arbiter_25_13 : Arbiter + +PORT MAP (Request => Request(205), North => south_2_north(24)(13), West => east_2_west(24)(12), P => Signal_priority(7), Fifo_full => Fifo_full(13), +South => south_2_north(25)(13), East => east_2_west(25)(13) , Grant => Signal_grant(25)(13)); + +Arbiter_25_14 : Arbiter + +PORT MAP (Request => Request(190), North => south_2_north(24)(14), West => east_2_west(24)(13), P => Signal_priority(7), Fifo_full => Fifo_full(14), +South => south_2_north(25)(14), East => east_2_west(25)(14) , Grant => Signal_grant(25)(14)); + +Arbiter_25_15 : Arbiter + +PORT MAP (Request => Request(175), North => south_2_north(24)(15), West => east_2_west(24)(14), P => Signal_priority(7), Fifo_full => Fifo_full(15), +South => south_2_north(25)(15), East => east_2_west(25)(15) , Grant => Signal_grant(25)(15)); + +Arbiter_25_16 : Arbiter + +PORT MAP (Request => Request(160), North => south_2_north(24)(16), West => east_2_west(24)(15), P => Signal_priority(7), Fifo_full => Fifo_full(16), +South => south_2_north(25)(16), East => east_2_west(25)(16) , Grant => Signal_grant(25)(16)); + +-------------------------- Diagonale n° 26 + + +Arbiter_26_1 : Arbiter + +PORT MAP (Request => Request(145), North => south_2_north(25)(1), West => east_2_west(25)(16), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(26)(1), East => east_2_west(26)(1) , Grant => Signal_grant(26)(1)); + +Arbiter_26_2 : Arbiter + +PORT MAP (Request => Request(130), North => south_2_north(25)(2), West => east_2_west(25)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(26)(2), East => east_2_west(26)(2) , Grant => Signal_grant(26)(2)); + +Arbiter_26_3 : Arbiter + +PORT MAP (Request => Request(115), North => south_2_north(25)(3), West => east_2_west(25)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(26)(3), East => east_2_west(26)(3) , Grant => Signal_grant(26)(3)); + +Arbiter_26_4 : Arbiter + +PORT MAP (Request => Request(100), North => south_2_north(25)(4), West => east_2_west(25)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(26)(4), East => east_2_west(26)(4) , Grant => Signal_grant(26)(4)); + +Arbiter_26_5 : Arbiter + +PORT MAP (Request => Request(85), North => south_2_north(25)(5), West => east_2_west(25)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5), +South => south_2_north(26)(5), East => east_2_west(26)(5) , Grant => Signal_grant(26)(5)); + +Arbiter_26_6 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(25)(6), West => east_2_west(25)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6), +South => south_2_north(26)(6), East => east_2_west(26)(6) , Grant => Signal_grant(26)(6)); + +Arbiter_26_7 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(25)(7), West => east_2_west(25)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7), +South => south_2_north(26)(7), East => east_2_west(26)(7) , Grant => Signal_grant(26)(7)); + +Arbiter_26_8 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(25)(8), West => east_2_west(25)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8), +South => south_2_north(26)(8), East => east_2_west(26)(8) , Grant => Signal_grant(26)(8)); + +Arbiter_26_9 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(25)(9), West => east_2_west(25)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9), +South => south_2_north(26)(9), East => east_2_west(26)(9) , Grant => Signal_grant(26)(9)); + +Arbiter_26_10 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(25)(10), West => east_2_west(25)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10), +South => south_2_north(26)(10), East => east_2_west(26)(10) , Grant => Signal_grant(26)(10)); + +Arbiter_26_11 : Arbiter + +PORT MAP (Request => Request(251), North => south_2_north(25)(11), West => east_2_west(25)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11), +South => south_2_north(26)(11), East => east_2_west(26)(11) , Grant => Signal_grant(26)(11)); + +Arbiter_26_12 : Arbiter + +PORT MAP (Request => Request(236), North => south_2_north(25)(12), West => east_2_west(25)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12), +South => south_2_north(26)(12), East => east_2_west(26)(12) , Grant => Signal_grant(26)(12)); + +Arbiter_26_13 : Arbiter + +PORT MAP (Request => Request(221), North => south_2_north(25)(13), West => east_2_west(25)(12), P => Signal_priority(6), Fifo_full => Fifo_full(13), +South => south_2_north(26)(13), East => east_2_west(26)(13) , Grant => Signal_grant(26)(13)); + +Arbiter_26_14 : Arbiter + +PORT MAP (Request => Request(206), North => south_2_north(25)(14), West => east_2_west(25)(13), P => Signal_priority(6), Fifo_full => Fifo_full(14), +South => south_2_north(26)(14), East => east_2_west(26)(14) , Grant => Signal_grant(26)(14)); + +Arbiter_26_15 : Arbiter + +PORT MAP (Request => Request(191), North => south_2_north(25)(15), West => east_2_west(25)(14), P => Signal_priority(6), Fifo_full => Fifo_full(15), +South => south_2_north(26)(15), East => east_2_west(26)(15) , Grant => Signal_grant(26)(15)); + +Arbiter_26_16 : Arbiter + +PORT MAP (Request => Request(176), North => south_2_north(25)(16), West => east_2_west(25)(15), P => Signal_priority(6), Fifo_full => Fifo_full(16), +South => south_2_north(26)(16), East => east_2_west(26)(16) , Grant => Signal_grant(26)(16)); + +-------------------------- Diagonale n° 27 + + +Arbiter_27_1 : Arbiter + +PORT MAP (Request => Request(161), North => south_2_north(26)(1), West => east_2_west(26)(16), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(27)(1), East => east_2_west(27)(1) , Grant => Signal_grant(27)(1)); + +Arbiter_27_2 : Arbiter + +PORT MAP (Request => Request(146), North => south_2_north(26)(2), West => east_2_west(26)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(27)(2), East => east_2_west(27)(2) , Grant => Signal_grant(27)(2)); + +Arbiter_27_3 : Arbiter + +PORT MAP (Request => Request(131), North => south_2_north(26)(3), West => east_2_west(26)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(27)(3), East => east_2_west(27)(3) , Grant => Signal_grant(27)(3)); + +Arbiter_27_4 : Arbiter + +PORT MAP (Request => Request(116), North => south_2_north(26)(4), West => east_2_west(26)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(27)(4), East => east_2_west(27)(4) , Grant => Signal_grant(27)(4)); + +Arbiter_27_5 : Arbiter + +PORT MAP (Request => Request(101), North => south_2_north(26)(5), West => east_2_west(26)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5), +South => south_2_north(27)(5), East => east_2_west(27)(5) , Grant => Signal_grant(27)(5)); + +Arbiter_27_6 : Arbiter + +PORT MAP (Request => Request(86), North => south_2_north(26)(6), West => east_2_west(26)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6), +South => south_2_north(27)(6), East => east_2_west(27)(6) , Grant => Signal_grant(27)(6)); + +Arbiter_27_7 : Arbiter + +PORT MAP (Request => Request(71), North => south_2_north(26)(7), West => east_2_west(26)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7), +South => south_2_north(27)(7), East => east_2_west(27)(7) , Grant => Signal_grant(27)(7)); + +Arbiter_27_8 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(26)(8), West => east_2_west(26)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8), +South => south_2_north(27)(8), East => east_2_west(27)(8) , Grant => Signal_grant(27)(8)); + +Arbiter_27_9 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(26)(9), West => east_2_west(26)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9), +South => south_2_north(27)(9), East => east_2_west(27)(9) , Grant => Signal_grant(27)(9)); + +Arbiter_27_10 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(26)(10), West => east_2_west(26)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10), +South => south_2_north(27)(10), East => east_2_west(27)(10) , Grant => Signal_grant(27)(10)); + +Arbiter_27_11 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(26)(11), West => east_2_west(26)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11), +South => south_2_north(27)(11), East => east_2_west(27)(11) , Grant => Signal_grant(27)(11)); + +Arbiter_27_12 : Arbiter + +PORT MAP (Request => Request(252), North => south_2_north(26)(12), West => east_2_west(26)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12), +South => south_2_north(27)(12), East => east_2_west(27)(12) , Grant => Signal_grant(27)(12)); + +Arbiter_27_13 : Arbiter + +PORT MAP (Request => Request(237), North => south_2_north(26)(13), West => east_2_west(26)(12), P => Signal_priority(5), Fifo_full => Fifo_full(13), +South => south_2_north(27)(13), East => east_2_west(27)(13) , Grant => Signal_grant(27)(13)); + +Arbiter_27_14 : Arbiter + +PORT MAP (Request => Request(222), North => south_2_north(26)(14), West => east_2_west(26)(13), P => Signal_priority(5), Fifo_full => Fifo_full(14), +South => south_2_north(27)(14), East => east_2_west(27)(14) , Grant => Signal_grant(27)(14)); + +Arbiter_27_15 : Arbiter + +PORT MAP (Request => Request(207), North => south_2_north(26)(15), West => east_2_west(26)(14), P => Signal_priority(5), Fifo_full => Fifo_full(15), +South => south_2_north(27)(15), East => east_2_west(27)(15) , Grant => Signal_grant(27)(15)); + +Arbiter_27_16 : Arbiter + +PORT MAP (Request => Request(192), North => south_2_north(26)(16), West => east_2_west(26)(15), P => Signal_priority(5), Fifo_full => Fifo_full(16), +South => south_2_north(27)(16), East => east_2_west(27)(16) , Grant => Signal_grant(27)(16)); + +-------------------------- Diagonale n° 28 + + +Arbiter_28_1 : Arbiter + +PORT MAP (Request => Request(177), North => south_2_north(27)(1), West => east_2_west(27)(16), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(28)(1), East => east_2_west(28)(1) , Grant => Signal_grant(28)(1)); + +Arbiter_28_2 : Arbiter + +PORT MAP (Request => Request(162), North => south_2_north(27)(2), West => east_2_west(27)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(28)(2), East => east_2_west(28)(2) , Grant => Signal_grant(28)(2)); + +Arbiter_28_3 : Arbiter + +PORT MAP (Request => Request(147), North => south_2_north(27)(3), West => east_2_west(27)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(28)(3), East => east_2_west(28)(3) , Grant => Signal_grant(28)(3)); + +Arbiter_28_4 : Arbiter + +PORT MAP (Request => Request(132), North => south_2_north(27)(4), West => east_2_west(27)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(28)(4), East => east_2_west(28)(4) , Grant => Signal_grant(28)(4)); + +Arbiter_28_5 : Arbiter + +PORT MAP (Request => Request(117), North => south_2_north(27)(5), West => east_2_west(27)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5), +South => south_2_north(28)(5), East => east_2_west(28)(5) , Grant => Signal_grant(28)(5)); + +Arbiter_28_6 : Arbiter + +PORT MAP (Request => Request(102), North => south_2_north(27)(6), West => east_2_west(27)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6), +South => south_2_north(28)(6), East => east_2_west(28)(6) , Grant => Signal_grant(28)(6)); + +Arbiter_28_7 : Arbiter + +PORT MAP (Request => Request(87), North => south_2_north(27)(7), West => east_2_west(27)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7), +South => south_2_north(28)(7), East => east_2_west(28)(7) , Grant => Signal_grant(28)(7)); + +Arbiter_28_8 : Arbiter + +PORT MAP (Request => Request(72), North => south_2_north(27)(8), West => east_2_west(27)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8), +South => south_2_north(28)(8), East => east_2_west(28)(8) , Grant => Signal_grant(28)(8)); + +Arbiter_28_9 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(27)(9), West => east_2_west(27)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9), +South => south_2_north(28)(9), East => east_2_west(28)(9) , Grant => Signal_grant(28)(9)); + +Arbiter_28_10 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(27)(10), West => east_2_west(27)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10), +South => south_2_north(28)(10), East => east_2_west(28)(10) , Grant => Signal_grant(28)(10)); + +Arbiter_28_11 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(27)(11), West => east_2_west(27)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11), +South => south_2_north(28)(11), East => east_2_west(28)(11) , Grant => Signal_grant(28)(11)); + +Arbiter_28_12 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(27)(12), West => east_2_west(27)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12), +South => south_2_north(28)(12), East => east_2_west(28)(12) , Grant => Signal_grant(28)(12)); + +Arbiter_28_13 : Arbiter + +PORT MAP (Request => Request(253), North => south_2_north(27)(13), West => east_2_west(27)(12), P => Signal_priority(4), Fifo_full => Fifo_full(13), +South => south_2_north(28)(13), East => east_2_west(28)(13) , Grant => Signal_grant(28)(13)); + +Arbiter_28_14 : Arbiter + +PORT MAP (Request => Request(238), North => south_2_north(27)(14), West => east_2_west(27)(13), P => Signal_priority(4), Fifo_full => Fifo_full(14), +South => south_2_north(28)(14), East => east_2_west(28)(14) , Grant => Signal_grant(28)(14)); + +Arbiter_28_15 : Arbiter + +PORT MAP (Request => Request(223), North => south_2_north(27)(15), West => east_2_west(27)(14), P => Signal_priority(4), Fifo_full => Fifo_full(15), +South => south_2_north(28)(15), East => east_2_west(28)(15) , Grant => Signal_grant(28)(15)); + +Arbiter_28_16 : Arbiter + +PORT MAP (Request => Request(208), North => south_2_north(27)(16), West => east_2_west(27)(15), P => Signal_priority(4), Fifo_full => Fifo_full(16), +South => south_2_north(28)(16), East => east_2_west(28)(16) , Grant => Signal_grant(28)(16)); + +-------------------------- Diagonale n° 29 + + +Arbiter_29_1 : Arbiter + +PORT MAP (Request => Request(193), North => south_2_north(28)(1), West => east_2_west(28)(16), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(29)(1), East => east_2_west(29)(1) , Grant => Signal_grant(29)(1)); + +Arbiter_29_2 : Arbiter + +PORT MAP (Request => Request(178), North => south_2_north(28)(2), West => east_2_west(28)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(29)(2), East => east_2_west(29)(2) , Grant => Signal_grant(29)(2)); + +Arbiter_29_3 : Arbiter + +PORT MAP (Request => Request(163), North => south_2_north(28)(3), West => east_2_west(28)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(29)(3), East => east_2_west(29)(3) , Grant => Signal_grant(29)(3)); + +Arbiter_29_4 : Arbiter + +PORT MAP (Request => Request(148), North => south_2_north(28)(4), West => east_2_west(28)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(29)(4), East => east_2_west(29)(4) , Grant => Signal_grant(29)(4)); + +Arbiter_29_5 : Arbiter + +PORT MAP (Request => Request(133), North => south_2_north(28)(5), West => east_2_west(28)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5), +South => south_2_north(29)(5), East => east_2_west(29)(5) , Grant => Signal_grant(29)(5)); + +Arbiter_29_6 : Arbiter + +PORT MAP (Request => Request(118), North => south_2_north(28)(6), West => east_2_west(28)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6), +South => south_2_north(29)(6), East => east_2_west(29)(6) , Grant => Signal_grant(29)(6)); + +Arbiter_29_7 : Arbiter + +PORT MAP (Request => Request(103), North => south_2_north(28)(7), West => east_2_west(28)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7), +South => south_2_north(29)(7), East => east_2_west(29)(7) , Grant => Signal_grant(29)(7)); + +Arbiter_29_8 : Arbiter + +PORT MAP (Request => Request(88), North => south_2_north(28)(8), West => east_2_west(28)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8), +South => south_2_north(29)(8), East => east_2_west(29)(8) , Grant => Signal_grant(29)(8)); + +Arbiter_29_9 : Arbiter + +PORT MAP (Request => Request(73), North => south_2_north(28)(9), West => east_2_west(28)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9), +South => south_2_north(29)(9), East => east_2_west(29)(9) , Grant => Signal_grant(29)(9)); + +Arbiter_29_10 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(28)(10), West => east_2_west(28)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10), +South => south_2_north(29)(10), East => east_2_west(29)(10) , Grant => Signal_grant(29)(10)); + +Arbiter_29_11 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(28)(11), West => east_2_west(28)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11), +South => south_2_north(29)(11), East => east_2_west(29)(11) , Grant => Signal_grant(29)(11)); + +Arbiter_29_12 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(28)(12), West => east_2_west(28)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12), +South => south_2_north(29)(12), East => east_2_west(29)(12) , Grant => Signal_grant(29)(12)); + +Arbiter_29_13 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(28)(13), West => east_2_west(28)(12), P => Signal_priority(3), Fifo_full => Fifo_full(13), +South => south_2_north(29)(13), East => east_2_west(29)(13) , Grant => Signal_grant(29)(13)); + +Arbiter_29_14 : Arbiter + +PORT MAP (Request => Request(254), North => south_2_north(28)(14), West => east_2_west(28)(13), P => Signal_priority(3), Fifo_full => Fifo_full(14), +South => south_2_north(29)(14), East => east_2_west(29)(14) , Grant => Signal_grant(29)(14)); + +Arbiter_29_15 : Arbiter + +PORT MAP (Request => Request(239), North => south_2_north(28)(15), West => east_2_west(28)(14), P => Signal_priority(3), Fifo_full => Fifo_full(15), +South => south_2_north(29)(15), East => east_2_west(29)(15) , Grant => Signal_grant(29)(15)); + +Arbiter_29_16 : Arbiter + +PORT MAP (Request => Request(224), North => south_2_north(28)(16), West => east_2_west(28)(15), P => Signal_priority(3), Fifo_full => Fifo_full(16), +South => south_2_north(29)(16), East => east_2_west(29)(16) , Grant => Signal_grant(29)(16)); + +-------------------------- Diagonale n° 30 + + +Arbiter_30_1 : Arbiter + +PORT MAP (Request => Request(209), North => south_2_north(29)(1), West => east_2_west(29)(16), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(30)(1), East => east_2_west(30)(1) , Grant => Signal_grant(30)(1)); + +Arbiter_30_2 : Arbiter + +PORT MAP (Request => Request(194), North => south_2_north(29)(2), West => east_2_west(29)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(30)(2), East => east_2_west(30)(2) , Grant => Signal_grant(30)(2)); + +Arbiter_30_3 : Arbiter + +PORT MAP (Request => Request(179), North => south_2_north(29)(3), West => east_2_west(29)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(30)(3), East => east_2_west(30)(3) , Grant => Signal_grant(30)(3)); + +Arbiter_30_4 : Arbiter + +PORT MAP (Request => Request(164), North => south_2_north(29)(4), West => east_2_west(29)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(30)(4), East => east_2_west(30)(4) , Grant => Signal_grant(30)(4)); + +Arbiter_30_5 : Arbiter + +PORT MAP (Request => Request(149), North => south_2_north(29)(5), West => east_2_west(29)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5), +South => south_2_north(30)(5), East => east_2_west(30)(5) , Grant => Signal_grant(30)(5)); + +Arbiter_30_6 : Arbiter + +PORT MAP (Request => Request(134), North => south_2_north(29)(6), West => east_2_west(29)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6), +South => south_2_north(30)(6), East => east_2_west(30)(6) , Grant => Signal_grant(30)(6)); + +Arbiter_30_7 : Arbiter + +PORT MAP (Request => Request(119), North => south_2_north(29)(7), West => east_2_west(29)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7), +South => south_2_north(30)(7), East => east_2_west(30)(7) , Grant => Signal_grant(30)(7)); + +Arbiter_30_8 : Arbiter + +PORT MAP (Request => Request(104), North => south_2_north(29)(8), West => east_2_west(29)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8), +South => south_2_north(30)(8), East => east_2_west(30)(8) , Grant => Signal_grant(30)(8)); + +Arbiter_30_9 : Arbiter + +PORT MAP (Request => Request(89), North => south_2_north(29)(9), West => east_2_west(29)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9), +South => south_2_north(30)(9), East => east_2_west(30)(9) , Grant => Signal_grant(30)(9)); + +Arbiter_30_10 : Arbiter + +PORT MAP (Request => Request(74), North => south_2_north(29)(10), West => east_2_west(29)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10), +South => south_2_north(30)(10), East => east_2_west(30)(10) , Grant => Signal_grant(30)(10)); + +Arbiter_30_11 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(29)(11), West => east_2_west(29)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11), +South => south_2_north(30)(11), East => east_2_west(30)(11) , Grant => Signal_grant(30)(11)); + +Arbiter_30_12 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(29)(12), West => east_2_west(29)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12), +South => south_2_north(30)(12), East => east_2_west(30)(12) , Grant => Signal_grant(30)(12)); + +Arbiter_30_13 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(29)(13), West => east_2_west(29)(12), P => Signal_priority(2), Fifo_full => Fifo_full(13), +South => south_2_north(30)(13), East => east_2_west(30)(13) , Grant => Signal_grant(30)(13)); + +Arbiter_30_14 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(29)(14), West => east_2_west(29)(13), P => Signal_priority(2), Fifo_full => Fifo_full(14), +South => south_2_north(30)(14), East => east_2_west(30)(14) , Grant => Signal_grant(30)(14)); + +Arbiter_30_15 : Arbiter + +PORT MAP (Request => Request(255), North => south_2_north(29)(15), West => east_2_west(29)(14), P => Signal_priority(2), Fifo_full => Fifo_full(15), +South => south_2_north(30)(15), East => east_2_west(30)(15) , Grant => Signal_grant(30)(15)); + +Arbiter_30_16 : Arbiter + +PORT MAP (Request => Request(240), North => south_2_north(29)(16), West => east_2_west(29)(15), P => Signal_priority(2), Fifo_full => Fifo_full(16), +South => south_2_north(30)(16), East => east_2_west(30)(16) , Grant => Signal_grant(30)(16)); + +-------------------------- Diagonale n° 31 + + +Arbiter_31_1 : Arbiter + +PORT MAP (Request => Request(225), North => south_2_north(30)(1), West => east_2_west(30)(16), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(31)(1), East => east_2_west(31)(1) , Grant => Signal_grant(31)(1)); + +Arbiter_31_2 : Arbiter + +PORT MAP (Request => Request(210), North => south_2_north(30)(2), West => east_2_west(30)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(31)(2), East => east_2_west(31)(2) , Grant => Signal_grant(31)(2)); + +Arbiter_31_3 : Arbiter + +PORT MAP (Request => Request(195), North => south_2_north(30)(3), West => east_2_west(30)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(31)(3), East => east_2_west(31)(3) , Grant => Signal_grant(31)(3)); + +Arbiter_31_4 : Arbiter + +PORT MAP (Request => Request(180), North => south_2_north(30)(4), West => east_2_west(30)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(31)(4), East => east_2_west(31)(4) , Grant => Signal_grant(31)(4)); + +Arbiter_31_5 : Arbiter + +PORT MAP (Request => Request(165), North => south_2_north(30)(5), West => east_2_west(30)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5), +South => south_2_north(31)(5), East => east_2_west(31)(5) , Grant => Signal_grant(31)(5)); + +Arbiter_31_6 : Arbiter + +PORT MAP (Request => Request(150), North => south_2_north(30)(6), West => east_2_west(30)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6), +South => south_2_north(31)(6), East => east_2_west(31)(6) , Grant => Signal_grant(31)(6)); + +Arbiter_31_7 : Arbiter + +PORT MAP (Request => Request(135), North => south_2_north(30)(7), West => east_2_west(30)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7), +South => south_2_north(31)(7), East => east_2_west(31)(7) , Grant => Signal_grant(31)(7)); + +Arbiter_31_8 : Arbiter + +PORT MAP (Request => Request(120), North => south_2_north(30)(8), West => east_2_west(30)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8), +South => south_2_north(31)(8), East => east_2_west(31)(8) , Grant => Signal_grant(31)(8)); + +Arbiter_31_9 : Arbiter + +PORT MAP (Request => Request(105), North => south_2_north(30)(9), West => east_2_west(30)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9), +South => south_2_north(31)(9), East => east_2_west(31)(9) , Grant => Signal_grant(31)(9)); + +Arbiter_31_10 : Arbiter + +PORT MAP (Request => Request(90), North => south_2_north(30)(10), West => east_2_west(30)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10), +South => south_2_north(31)(10), East => east_2_west(31)(10) , Grant => Signal_grant(31)(10)); + +Arbiter_31_11 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(30)(11), West => east_2_west(30)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11), +South => south_2_north(31)(11), East => east_2_west(31)(11) , Grant => Signal_grant(31)(11)); + +Arbiter_31_12 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(30)(12), West => east_2_west(30)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12), +South => south_2_north(31)(12), East => east_2_west(31)(12) , Grant => Signal_grant(31)(12)); + +Arbiter_31_13 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(30)(13), West => east_2_west(30)(12), P => Signal_priority(1), Fifo_full => Fifo_full(13), +South => south_2_north(31)(13), East => east_2_west(31)(13) , Grant => Signal_grant(31)(13)); + +Arbiter_31_14 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(30)(14), West => east_2_west(30)(13), P => Signal_priority(1), Fifo_full => Fifo_full(14), +South => south_2_north(31)(14), East => east_2_west(31)(14) , Grant => Signal_grant(31)(14)); + +Arbiter_31_15 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(30)(15), West => east_2_west(30)(14), P => Signal_priority(1), Fifo_full => Fifo_full(15), +South => south_2_north(31)(15), East => east_2_west(31)(15) , Grant => Signal_grant(31)(15)); + +Arbiter_31_16 : Arbiter + +PORT MAP (Request => Request(256), North => south_2_north(30)(16), West => east_2_west(30)(15), P => Signal_priority(1), Fifo_full => Fifo_full(16), +South => south_2_north(31)(16), East => east_2_west(31)(16) , Grant => Signal_grant(31)(16)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "1111111111111111000000000000000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "1111111111111111000000000000000" => Signal_priority <= "0111111111111111100000000000000"; + when "0111111111111111100000000000000" => Signal_priority <= "0011111111111111110000000000000"; + when "0011111111111111110000000000000" => Signal_priority <= "0001111111111111111000000000000"; + when "0001111111111111111000000000000" => Signal_priority <= "0000111111111111111100000000000"; + when "0000111111111111111100000000000" => Signal_priority <= "0000011111111111111110000000000"; + when "0000011111111111111110000000000" => Signal_priority <= "0000001111111111111111000000000"; + when "0000001111111111111111000000000" => Signal_priority <= "0000000111111111111111100000000"; + when "0000000111111111111111100000000" => Signal_priority <= "0000000011111111111111110000000"; + when "0000000011111111111111110000000" => Signal_priority <= "0000000001111111111111111000000"; + when "0000000001111111111111111000000" => Signal_priority <= "0000000000111111111111111100000"; + when "0000000000111111111111111100000" => Signal_priority <= "0000000000011111111111111110000"; + when "0000000000011111111111111110000" => Signal_priority <= "0000000000001111111111111111000"; + when "0000000000001111111111111111000" => Signal_priority <= "0000000000000111111111111111100"; + when "0000000000000111111111111111100" => Signal_priority <= "0000000000000011111111111111110"; + when "0000000000000011111111111111110" => Signal_priority <= "0000000000000001111111111111111"; + when "0000000000000001111111111111111" => Signal_priority <= "1111111111111111000000000000000"; + when others => Signal_priority <= "1111111111111111000000000000000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER2_2.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER2_2.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER2_2.VHD (revision 138) @@ -0,0 +1,141 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler2_2 is + Port ( Request : in STD_LOGIC_VECTOR (4 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (2 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (2 downto 1); + port_grant : out STD_LOGIC_VECTOR (4 downto 1)); +end Scheduler2_2; + +architecture Behavioral of Scheduler2_2 is +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(3 downto 1) of STD_LOGIC_VECTOR(2 downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (3 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(4 downto 1); + signal priority_rotation_en : std_logic; + signal Grant ,req_grant : std_logic_vector(4 downto 1); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet + req_grant<=(request and grant_latch); + priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 3 else '0'; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + elsif priority_rotation_en = '1' then + grant_latch <= Grant; + end if; + end if; + end process; + port_grant <= grant_latch; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(3)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) ; -- Grant(1,2) +Grant(3) <= Signal_grant(2)(1) ; -- Grant(2,1) +Grant(4) <= Signal_grant(1)(2) or Signal_grant(3)(2); -- Grant(2,2) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(4), North => High, West => High, P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(1)(1), West => east_2_west(1)(2), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(2)(1), West => east_2_west(2)(2), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "110"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "110" => Signal_priority <= "011"; + when "011" => Signal_priority <= "110"; + when others => Signal_priority <= "110"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER3_3.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER3_3.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER3_3.VHD (revision 138) @@ -0,0 +1,198 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler3_3 is + Port ( Request : in STD_LOGIC_VECTOR (9 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (3 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (3 downto 1); + port_grant : out STD_LOGIC_VECTOR (9 downto 1)); +end Scheduler3_3; + +architecture Behavioral of Scheduler3_3 is +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(5 downto 1) of STD_LOGIC_VECTOR(3 downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (5 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(9 downto 1); + signal priority_rotation_en : std_logic; + signal Grant,req_grant : std_logic_vector(9 downto 1); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet + req_grant<=(request and grant_latch); + priority_rotation_en <= '1' when unsigned(priority_rotation) = 7 else '0'; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + elsif priority_rotation_en = '1' then + grant_latch <= Grant; + end if; + end if; + end process; + port_grant <= grant_latch; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(4)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(5)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) ; -- Grant(1,3) +Grant(4) <= Signal_grant(2)(1) or Signal_grant(5)(1); -- Grant(2,1) +Grant(5) <= Signal_grant(3)(2) ; -- Grant(2,2) +Grant(6) <= Signal_grant(1)(3) or Signal_grant(4)(3); -- Grant(2,3) +Grant(7) <= Signal_grant(3)(1) ; -- Grant(3,1) +Grant(8) <= Signal_grant(1)(2) or Signal_grant(4)(2); -- Grant(3,2) +Grant(9) <= Signal_grant(2)(3) or Signal_grant(5)(3); -- Grant(3,3) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(8), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(6), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(1)(1), West => east_2_west(1)(3), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(2)(1), West => east_2_west(2)(3), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(3)(1), West => east_2_west(3)(3), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(4)(1), West => east_2_west(4)(3), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "11100"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "11100" => Signal_priority <= "01110"; + when "01110" => Signal_priority <= "00111"; + when "00111" => Signal_priority <= "11100"; + when others => Signal_priority <= "11100"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER4_4.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER4_4.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER4_4.VHD (revision 138) @@ -0,0 +1,332 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler4_4 is + Port ( Req : in STD_LOGIC_VECTOR (16 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (4 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (4 downto 1); + port_grant : out STD_LOGIC_VECTOR (16 downto 1)); +end Scheduler4_4; + +architecture Behavioral of Scheduler4_4 is +--déclaration de constantes +Constant NB_IO : positive:=4; --le nombre de ports d'entrée/sortie +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(7 downto 1) of STD_LOGIC_VECTOR(NB_IO downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +component Def_Request is +generic (NB_IO :positive:=4); + Port ( Req : in STD_LOGIC_VECTOR (NB_IO**2 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + fifo_full : in STD_LOGIC_VECTOR (NB_IO downto 1); + priority_rotation : in STD_LOGIC_VECTOR (NB_IO downto 1); + grant : in STD_LOGIC_VECTOR (NB_IO**2 downto 1); + request : out STD_LOGIC_VECTOR (NB_IO**2 downto 1)); +end component; +constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S + +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (7 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest +-- Signal Fifo_out_full : STD_LOGIC_VECTOR (NB_IO downto 1); +-- signal grant_latch : std_logic_vector(NB_IO2 downto 1); + signal priority_rotation_en : std_logic; +signal Grant,request : std_logic_vector(NB_IO2 downto 1):=(others=>'0'); +-- signal Mreq : std_logic_vector(NB_IO2 downto 1):=(others=>'1'); + + begin + +----validation de la rotation de priorité lorsque aucun port n'emet +-- req_grant<=(req and grant ); + priority_rotation_en <= '1' when unsigned(priority_rotation) = 2**NB_IO-1 else '0'; +--request<=req and mreq; +----latch qui memorise le signal grant pendant la transmission +--grant_latch_process : process(clk) +-- begin +-- if rising_edge(clk) then +-- if reset = '1' then +-- grant_latch <= (others => '0'); +-- Fifo_out_full<=(others => '0'); +-- elsif priority_rotation_en = '1' or unsigned(req_grant)=0 then +-- grant_latch <= Grant; +-- Fifo_out_full<=fifo_full; +-- else +-- grant_latch <= Grant; +-- Fifo_out_full<=fifo_full; +-- end if; +-- end if; +-- +-- end process; +-- def_mreq: process(grant_latch,fifo_full) +-- +--variable t:std_logic_vector(NB_IO2 downto 1):=(others=>'0'); +--begin +-- +-- for i in 0 to NB_IO2-1 loop +-- t(i+1):='0'; +-- --sur le front montant de fifo_full sauver l'état Grant courant +-- if fifo_full(i mod NB_IO+1)='1' and fifo_out_full(i mod NB_IO+1)='0' then +-- Grant_bak(i+1)<= grant_latch(i+1); +-- elsif fifo_full(i mod NB_IO+1)='0' and fifo_out_full(i mod NB_IO+1)='0' then +-- Grant_bak(i+1)<='0'; +-- end if; +-- for j in 0 to NB_IO-1 loop +-- t(i+1):=t(i+1) or grant_latch(j*NB_IO+1+i mod NB_IO) or fifo_out_full(i mod NB_IO+1); +-- +-- end loop; +-- mreq(i+1)<=not(t(i+1) ) or grant_latch(i+1)or grant_bak(i+1); +-- end loop; +--end process; +--cette instance permet de déterminer le vecteur request en fonction de l'état fifo_full et de la requête initiale +inst_defreq: def_request generic map (NB_IO=>4) +port map (clk=>clk, +reset=>reset, +req=>req, +fifo_full=>fifo_full, +priority_rotation=>priority_rotation, +grant=>grant, +request=>request +); + + port_grant <= grant; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(5)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(6)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(7)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) ; -- Grant(1,4) +Grant(5) <= Signal_grant(2)(1) or Signal_grant(6)(1); -- Grant(2,1) +Grant(6) <= Signal_grant(3)(2) or Signal_grant(7)(2); -- Grant(2,2) +Grant(7) <= Signal_grant(4)(3) ; -- Grant(2,3) +Grant(8) <= Signal_grant(1)(4) or Signal_grant(5)(4); -- Grant(2,4) +Grant(9) <= Signal_grant(3)(1) or Signal_grant(7)(1); -- Grant(3,1) +Grant(10) <= Signal_grant(4)(2) ; -- Grant(3,2) +Grant(11) <= Signal_grant(1)(3) or Signal_grant(5)(3); -- Grant(3,3) +Grant(12) <= Signal_grant(2)(4) or Signal_grant(6)(4); -- Grant(3,4) +Grant(13) <= Signal_grant(4)(1) ; -- Grant(4,1) +Grant(14) <= Signal_grant(1)(2) or Signal_grant(5)(2); -- Grant(4,2) +Grant(15) <= Signal_grant(2)(3) or Signal_grant(6)(3); -- Grant(4,3) +Grant(16) <= Signal_grant(3)(4) or Signal_grant(7)(4); -- Grant(4,4) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(14), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(11), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(8), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(1)(1), West => east_2_west(1)(4), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(2)(1), West => east_2_west(2)(4), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(3)(1), West => east_2_west(3)(4), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(4)(1), West => east_2_west(4)(4), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(5)(1), West => east_2_west(5)(4), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(6)(1), West => east_2_west(6)(4), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "1111000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "1111000" => Signal_priority <= "0111100"; + when "0111100" => Signal_priority <= "0011110"; + when "0011110" => Signal_priority <= "0001111"; + when "0001111" => Signal_priority <= "1111000"; + when others => Signal_priority <= "1111000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER4_4.VHD.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER4_4.VHD.bak (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER4_4.VHD.bak (revision 138) @@ -0,0 +1,311 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler4_4 is + Port ( Req : in STD_LOGIC_VECTOR (16 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (4 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (4 downto 1); + port_grant : out STD_LOGIC_VECTOR (16 downto 1)); +end Scheduler4_4; + +architecture Behavioral of Scheduler4_4 is +--déclaration de constantes +Constant NB_IO : positive:=4; --le nombre de ports d'entrée/sortie +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(7 downto 1) of STD_LOGIC_VECTOR(NB_IO downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues + +constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S + +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (7 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(NB_IO2 downto 1); + signal priority_rotation_en : std_logic; +signal Grant,request,req_grant,Grant_bak : std_logic_vector(NB_IO2 downto 1):=(others=>'0'); + signal Mreq : std_logic_vector(NB_IO2 downto 1):=(others=>'1'); + + begin + +--validation de la rotation de priorité lorsque aucun port n'emet + req_grant<=(req and grant ); + priority_rotation_en <= '1' when unsigned(priority_rotation) = 2**NB_IO-1 else '0'; +request<=req and mreq; +--latch qui memorise le signal grant pendant la transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + Fifo_out_full<=(others => '0'); + elsif priority_rotation_en = '1' or unsigned(req_grant)=0 then + grant_latch <= Grant; + Fifo_out_full<=fifo_full; + else + grant_latch <= Grant; + Fifo_out_full<=fifo_full; + end if; + end if; + + end process; + def_mreq: process(grant_latch,fifo_full) + +variable t:std_logic_vector(NB_IO2 downto 1):=(others=>'0'); +begin + + for i in 0 to NB_IO2-1 loop + t(i+1):='0'; + --sur le front montant de fifo_full sauver l'état Grant courant + if fifo_full(i mod NB_IO+1)='1' and fifo_out_full(i mod NB_IO+1)='0' then + Grant_bak(i+1)<= grant_latch(i+1); + elsif fifo_full(i mod NB_IO+1)='0' and fifo_out_full(i mod NB_IO+1)='0' then + Grant_bak(i+1)<='0'; + end if; + for j in 0 to NB_IO-1 loop + t(i+1):=t(i+1) or grant_latch(j*NB_IO+1+i mod NB_IO) or fifo_out_full(i mod NB_IO+1); + + end loop; + mreq(i+1)<=not(t(i+1) ) or grant_latch(i+1)or grant_bak(i+1); + end loop; +end process; + port_grant <= grant; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(5)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(6)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(7)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) ; -- Grant(1,4) +Grant(5) <= Signal_grant(2)(1) or Signal_grant(6)(1); -- Grant(2,1) +Grant(6) <= Signal_grant(3)(2) or Signal_grant(7)(2); -- Grant(2,2) +Grant(7) <= Signal_grant(4)(3) ; -- Grant(2,3) +Grant(8) <= Signal_grant(1)(4) or Signal_grant(5)(4); -- Grant(2,4) +Grant(9) <= Signal_grant(3)(1) or Signal_grant(7)(1); -- Grant(3,1) +Grant(10) <= Signal_grant(4)(2) ; -- Grant(3,2) +Grant(11) <= Signal_grant(1)(3) or Signal_grant(5)(3); -- Grant(3,3) +Grant(12) <= Signal_grant(2)(4) or Signal_grant(6)(4); -- Grant(3,4) +Grant(13) <= Signal_grant(4)(1) ; -- Grant(4,1) +Grant(14) <= Signal_grant(1)(2) or Signal_grant(5)(2); -- Grant(4,2) +Grant(15) <= Signal_grant(2)(3) or Signal_grant(6)(3); -- Grant(4,3) +Grant(16) <= Signal_grant(3)(4) or Signal_grant(7)(4); -- Grant(4,4) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(14), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(11), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(8), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(1)(1), West => east_2_west(1)(4), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(2)(1), West => east_2_west(2)(4), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(3)(1), West => east_2_west(3)(4), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(4)(1), West => east_2_west(4)(4), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(5)(1), West => east_2_west(5)(4), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(6)(1), West => east_2_west(6)(4), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "1111000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "1111000" => Signal_priority <= "0111100"; + when "0111100" => Signal_priority <= "0011110"; + when "0011110" => Signal_priority <= "0001111"; + when "0001111" => Signal_priority <= "1111000"; + when others => Signal_priority <= "1111000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER5_5.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER5_5.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER5_5.VHD (revision 138) @@ -0,0 +1,378 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler5_5 is + Port ( Request : in STD_LOGIC_VECTOR (25 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (5 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (5 downto 1); + port_grant : out STD_LOGIC_VECTOR (25 downto 1)); +end Scheduler5_5; + +architecture Behavioral of Scheduler5_5 is +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(9 downto 1) of STD_LOGIC_VECTOR(5 downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (9 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(25 downto 1); + signal priority_rotation_en : std_logic; + signal Grant ,req_grant: std_logic_vector(25 downto 1); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet + req_grant<=(request and grant_latch); + priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 31 else '0'; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + elsif priority_rotation_en = '1' then + grant_latch <= Grant; + end if; + end if; + end process; + port_grant <= grant_latch; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(6)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(7)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(8)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) or Signal_grant(9)(4); -- Grant(1,4) +Grant(5) <= Signal_grant(5)(5) ; -- Grant(1,5) +Grant(6) <= Signal_grant(2)(1) or Signal_grant(7)(1); -- Grant(2,1) +Grant(7) <= Signal_grant(3)(2) or Signal_grant(8)(2); -- Grant(2,2) +Grant(8) <= Signal_grant(4)(3) or Signal_grant(9)(3); -- Grant(2,3) +Grant(9) <= Signal_grant(5)(4) ; -- Grant(2,4) +Grant(10) <= Signal_grant(1)(5) or Signal_grant(6)(5); -- Grant(2,5) +Grant(11) <= Signal_grant(3)(1) or Signal_grant(8)(1); -- Grant(3,1) +Grant(12) <= Signal_grant(4)(2) or Signal_grant(9)(2); -- Grant(3,2) +Grant(13) <= Signal_grant(5)(3) ; -- Grant(3,3) +Grant(14) <= Signal_grant(1)(4) or Signal_grant(6)(4); -- Grant(3,4) +Grant(15) <= Signal_grant(2)(5) or Signal_grant(7)(5); -- Grant(3,5) +Grant(16) <= Signal_grant(4)(1) or Signal_grant(9)(1); -- Grant(4,1) +Grant(17) <= Signal_grant(5)(2) ; -- Grant(4,2) +Grant(18) <= Signal_grant(1)(3) or Signal_grant(6)(3); -- Grant(4,3) +Grant(19) <= Signal_grant(2)(4) or Signal_grant(7)(4); -- Grant(4,4) +Grant(20) <= Signal_grant(3)(5) or Signal_grant(8)(5); -- Grant(4,5) +Grant(21) <= Signal_grant(5)(1) ; -- Grant(5,1) +Grant(22) <= Signal_grant(1)(2) or Signal_grant(6)(2); -- Grant(5,2) +Grant(23) <= Signal_grant(2)(3) or Signal_grant(7)(3); -- Grant(5,3) +Grant(24) <= Signal_grant(3)(4) or Signal_grant(8)(4); -- Grant(5,4) +Grant(25) <= Signal_grant(4)(5) or Signal_grant(9)(5); -- Grant(5,5) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(22), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(18), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(14), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +Arbiter_1_5 : Arbiter + +PORT MAP (Request => Request(10), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(5), +South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(1)(1), West => east_2_west(1)(5), P => Signal_priority(8), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +Arbiter_2_5 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5), +South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(2)(1), West => east_2_west(2)(5), P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +Arbiter_3_5 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5), +South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(3)(1), West => east_2_west(3)(5), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +Arbiter_4_5 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5), +South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(4)(1), West => east_2_west(4)(5), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +Arbiter_5_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5), +South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(5)(1), West => east_2_west(5)(5), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +Arbiter_6_5 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5), +South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(6)(1), West => east_2_west(6)(5), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + +Arbiter_7_5 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5), +South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); + +-------------------------- Diagonale n° 8 + + +Arbiter_8_1 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(7)(1), West => east_2_west(7)(5), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); + +Arbiter_8_2 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); + +Arbiter_8_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); + +Arbiter_8_4 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); + +Arbiter_8_5 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5), +South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); + +-------------------------- Diagonale n° 9 + + +Arbiter_9_1 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(8)(1), West => east_2_west(8)(5), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); + +Arbiter_9_2 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); + +Arbiter_9_3 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); + +Arbiter_9_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); + +Arbiter_9_5 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5), +South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "111110000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "111110000" => Signal_priority <= "011111000"; + when "011111000" => Signal_priority <= "001111100"; + when "001111100" => Signal_priority <= "000111110"; + when "000111110" => Signal_priority <= "000011111"; + when "000011111" => Signal_priority <= "111110000"; + when others => Signal_priority <= "111110000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER6_6.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER6_6.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER6_6.VHD (revision 138) @@ -0,0 +1,501 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler6_6 is + Port ( Request : in STD_LOGIC_VECTOR (36 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (6 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (6 downto 1); + port_grant : out STD_LOGIC_VECTOR (36 downto 1)); +end Scheduler6_6; + +architecture Behavioral of Scheduler6_6 is +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(11 downto 1) of STD_LOGIC_VECTOR(6 downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (11 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(36 downto 1); + signal priority_rotation_en : std_logic; + signal Grant,req_grant : std_logic_vector(36 downto 1); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet + req_grant<=(request and grant_latch); + priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 63 else '0'; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + elsif priority_rotation_en = '1' then + grant_latch <= Grant; + end if; + end if; + end process; + port_grant <= grant_latch; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(7)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(8)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(9)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) or Signal_grant(10)(4); -- Grant(1,4) +Grant(5) <= Signal_grant(5)(5) or Signal_grant(11)(5); -- Grant(1,5) +Grant(6) <= Signal_grant(6)(6) ; -- Grant(1,6) +Grant(7) <= Signal_grant(2)(1) or Signal_grant(8)(1); -- Grant(2,1) +Grant(8) <= Signal_grant(3)(2) or Signal_grant(9)(2); -- Grant(2,2) +Grant(9) <= Signal_grant(4)(3) or Signal_grant(10)(3); -- Grant(2,3) +Grant(10) <= Signal_grant(5)(4) or Signal_grant(11)(4); -- Grant(2,4) +Grant(11) <= Signal_grant(6)(5) ; -- Grant(2,5) +Grant(12) <= Signal_grant(1)(6) or Signal_grant(7)(6); -- Grant(2,6) +Grant(13) <= Signal_grant(3)(1) or Signal_grant(9)(1); -- Grant(3,1) +Grant(14) <= Signal_grant(4)(2) or Signal_grant(10)(2); -- Grant(3,2) +Grant(15) <= Signal_grant(5)(3) or Signal_grant(11)(3); -- Grant(3,3) +Grant(16) <= Signal_grant(6)(4) ; -- Grant(3,4) +Grant(17) <= Signal_grant(1)(5) or Signal_grant(7)(5); -- Grant(3,5) +Grant(18) <= Signal_grant(2)(6) or Signal_grant(8)(6); -- Grant(3,6) +Grant(19) <= Signal_grant(4)(1) or Signal_grant(10)(1); -- Grant(4,1) +Grant(20) <= Signal_grant(5)(2) or Signal_grant(11)(2); -- Grant(4,2) +Grant(21) <= Signal_grant(6)(3) ; -- Grant(4,3) +Grant(22) <= Signal_grant(1)(4) or Signal_grant(7)(4); -- Grant(4,4) +Grant(23) <= Signal_grant(2)(5) or Signal_grant(8)(5); -- Grant(4,5) +Grant(24) <= Signal_grant(3)(6) or Signal_grant(9)(6); -- Grant(4,6) +Grant(25) <= Signal_grant(5)(1) or Signal_grant(11)(1); -- Grant(5,1) +Grant(26) <= Signal_grant(6)(2) ; -- Grant(5,2) +Grant(27) <= Signal_grant(1)(3) or Signal_grant(7)(3); -- Grant(5,3) +Grant(28) <= Signal_grant(2)(4) or Signal_grant(8)(4); -- Grant(5,4) +Grant(29) <= Signal_grant(3)(5) or Signal_grant(9)(5); -- Grant(5,5) +Grant(30) <= Signal_grant(4)(6) or Signal_grant(10)(6); -- Grant(5,6) +Grant(31) <= Signal_grant(6)(1) ; -- Grant(6,1) +Grant(32) <= Signal_grant(1)(2) or Signal_grant(7)(2); -- Grant(6,2) +Grant(33) <= Signal_grant(2)(3) or Signal_grant(8)(3); -- Grant(6,3) +Grant(34) <= Signal_grant(3)(4) or Signal_grant(9)(4); -- Grant(6,4) +Grant(35) <= Signal_grant(4)(5) or Signal_grant(10)(5); -- Grant(6,5) +Grant(36) <= Signal_grant(5)(6) or Signal_grant(11)(6); -- Grant(6,6) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(32), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(27), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(22), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +Arbiter_1_5 : Arbiter + +PORT MAP (Request => Request(17), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(5), +South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); + +Arbiter_1_6 : Arbiter + +PORT MAP (Request => Request(12), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(6), +South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(1)(1), West => east_2_west(1)(6), P => Signal_priority(10), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +Arbiter_2_5 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5), +South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); + +Arbiter_2_6 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6), +South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(2)(1), West => east_2_west(2)(6), P => Signal_priority(9), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +Arbiter_3_5 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5), +South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); + +Arbiter_3_6 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6), +South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(3)(1), West => east_2_west(3)(6), P => Signal_priority(8), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +Arbiter_4_5 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5), +South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); + +Arbiter_4_6 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6), +South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(4)(1), West => east_2_west(4)(6), P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +Arbiter_5_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5), +South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); + +Arbiter_5_6 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6), +South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(5)(1), West => east_2_west(5)(6), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +Arbiter_6_5 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5), +South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); + +Arbiter_6_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6), +South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(6)(1), West => east_2_west(6)(6), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + +Arbiter_7_5 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5), +South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); + +Arbiter_7_6 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6), +South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); + +-------------------------- Diagonale n° 8 + + +Arbiter_8_1 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(7)(1), West => east_2_west(7)(6), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); + +Arbiter_8_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); + +Arbiter_8_3 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); + +Arbiter_8_4 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); + +Arbiter_8_5 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5), +South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); + +Arbiter_8_6 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6), +South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); + +-------------------------- Diagonale n° 9 + + +Arbiter_9_1 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(8)(1), West => east_2_west(8)(6), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); + +Arbiter_9_2 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); + +Arbiter_9_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); + +Arbiter_9_4 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); + +Arbiter_9_5 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5), +South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); + +Arbiter_9_6 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6), +South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); + +-------------------------- Diagonale n° 10 + + +Arbiter_10_1 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(9)(1), West => east_2_west(9)(6), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); + +Arbiter_10_2 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); + +Arbiter_10_3 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); + +Arbiter_10_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); + +Arbiter_10_5 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5), +South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); + +Arbiter_10_6 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6), +South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); + +-------------------------- Diagonale n° 11 + + +Arbiter_11_1 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(10)(1), West => east_2_west(10)(6), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); + +Arbiter_11_2 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); + +Arbiter_11_3 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); + +Arbiter_11_4 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); + +Arbiter_11_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5), +South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); + +Arbiter_11_6 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6), +South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "11111100000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "11111100000" => Signal_priority <= "01111110000"; + when "01111110000" => Signal_priority <= "00111111000"; + when "00111111000" => Signal_priority <= "00011111100"; + when "00011111100" => Signal_priority <= "00001111110"; + when "00001111110" => Signal_priority <= "00000111111"; + when "00000111111" => Signal_priority <= "11111100000"; + when others => Signal_priority <= "11111100000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER7_7.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER7_7.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER7_7.VHD (revision 138) @@ -0,0 +1,646 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler7_7 is + Port ( Request : in STD_LOGIC_VECTOR (49 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (7 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (7 downto 1); + port_grant : out STD_LOGIC_VECTOR (49 downto 1)); +end Scheduler7_7; + +architecture Behavioral of Scheduler7_7 is +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(13 downto 1) of STD_LOGIC_VECTOR(7 downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (13 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(49 downto 1); + signal priority_rotation_en : std_logic; + signal Grant,req_grant : std_logic_vector(49 downto 1); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet + req_grant<=(request and grant_latch); + priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 127 else '0'; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + elsif priority_rotation_en = '1' then + grant_latch <= Grant; + end if; + end if; + end process; + port_grant <= grant_latch; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(8)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(9)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(10)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) or Signal_grant(11)(4); -- Grant(1,4) +Grant(5) <= Signal_grant(5)(5) or Signal_grant(12)(5); -- Grant(1,5) +Grant(6) <= Signal_grant(6)(6) or Signal_grant(13)(6); -- Grant(1,6) +Grant(7) <= Signal_grant(7)(7) ; -- Grant(1,7) +Grant(8) <= Signal_grant(2)(1) or Signal_grant(9)(1); -- Grant(2,1) +Grant(9) <= Signal_grant(3)(2) or Signal_grant(10)(2); -- Grant(2,2) +Grant(10) <= Signal_grant(4)(3) or Signal_grant(11)(3); -- Grant(2,3) +Grant(11) <= Signal_grant(5)(4) or Signal_grant(12)(4); -- Grant(2,4) +Grant(12) <= Signal_grant(6)(5) or Signal_grant(13)(5); -- Grant(2,5) +Grant(13) <= Signal_grant(7)(6) ; -- Grant(2,6) +Grant(14) <= Signal_grant(1)(7) or Signal_grant(8)(7); -- Grant(2,7) +Grant(15) <= Signal_grant(3)(1) or Signal_grant(10)(1); -- Grant(3,1) +Grant(16) <= Signal_grant(4)(2) or Signal_grant(11)(2); -- Grant(3,2) +Grant(17) <= Signal_grant(5)(3) or Signal_grant(12)(3); -- Grant(3,3) +Grant(18) <= Signal_grant(6)(4) or Signal_grant(13)(4); -- Grant(3,4) +Grant(19) <= Signal_grant(7)(5) ; -- Grant(3,5) +Grant(20) <= Signal_grant(1)(6) or Signal_grant(8)(6); -- Grant(3,6) +Grant(21) <= Signal_grant(2)(7) or Signal_grant(9)(7); -- Grant(3,7) +Grant(22) <= Signal_grant(4)(1) or Signal_grant(11)(1); -- Grant(4,1) +Grant(23) <= Signal_grant(5)(2) or Signal_grant(12)(2); -- Grant(4,2) +Grant(24) <= Signal_grant(6)(3) or Signal_grant(13)(3); -- Grant(4,3) +Grant(25) <= Signal_grant(7)(4) ; -- Grant(4,4) +Grant(26) <= Signal_grant(1)(5) or Signal_grant(8)(5); -- Grant(4,5) +Grant(27) <= Signal_grant(2)(6) or Signal_grant(9)(6); -- Grant(4,6) +Grant(28) <= Signal_grant(3)(7) or Signal_grant(10)(7); -- Grant(4,7) +Grant(29) <= Signal_grant(5)(1) or Signal_grant(12)(1); -- Grant(5,1) +Grant(30) <= Signal_grant(6)(2) or Signal_grant(13)(2); -- Grant(5,2) +Grant(31) <= Signal_grant(7)(3) ; -- Grant(5,3) +Grant(32) <= Signal_grant(1)(4) or Signal_grant(8)(4); -- Grant(5,4) +Grant(33) <= Signal_grant(2)(5) or Signal_grant(9)(5); -- Grant(5,5) +Grant(34) <= Signal_grant(3)(6) or Signal_grant(10)(6); -- Grant(5,6) +Grant(35) <= Signal_grant(4)(7) or Signal_grant(11)(7); -- Grant(5,7) +Grant(36) <= Signal_grant(6)(1) or Signal_grant(13)(1); -- Grant(6,1) +Grant(37) <= Signal_grant(7)(2) ; -- Grant(6,2) +Grant(38) <= Signal_grant(1)(3) or Signal_grant(8)(3); -- Grant(6,3) +Grant(39) <= Signal_grant(2)(4) or Signal_grant(9)(4); -- Grant(6,4) +Grant(40) <= Signal_grant(3)(5) or Signal_grant(10)(5); -- Grant(6,5) +Grant(41) <= Signal_grant(4)(6) or Signal_grant(11)(6); -- Grant(6,6) +Grant(42) <= Signal_grant(5)(7) or Signal_grant(12)(7); -- Grant(6,7) +Grant(43) <= Signal_grant(7)(1) ; -- Grant(7,1) +Grant(44) <= Signal_grant(1)(2) or Signal_grant(8)(2); -- Grant(7,2) +Grant(45) <= Signal_grant(2)(3) or Signal_grant(9)(3); -- Grant(7,3) +Grant(46) <= Signal_grant(3)(4) or Signal_grant(10)(4); -- Grant(7,4) +Grant(47) <= Signal_grant(4)(5) or Signal_grant(11)(5); -- Grant(7,5) +Grant(48) <= Signal_grant(5)(6) or Signal_grant(12)(6); -- Grant(7,6) +Grant(49) <= Signal_grant(6)(7) or Signal_grant(13)(7); -- Grant(7,7) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(44), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(38), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(32), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +Arbiter_1_5 : Arbiter + +PORT MAP (Request => Request(26), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(5), +South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); + +Arbiter_1_6 : Arbiter + +PORT MAP (Request => Request(20), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(6), +South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); + +Arbiter_1_7 : Arbiter + +PORT MAP (Request => Request(14), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(7), +South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(1)(1), West => east_2_west(1)(7), P => Signal_priority(12), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +Arbiter_2_5 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5), +South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); + +Arbiter_2_6 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6), +South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); + +Arbiter_2_7 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7), +South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(2)(1), West => east_2_west(2)(7), P => Signal_priority(11), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +Arbiter_3_5 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5), +South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); + +Arbiter_3_6 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6), +South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); + +Arbiter_3_7 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7), +South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(3)(1), West => east_2_west(3)(7), P => Signal_priority(10), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +Arbiter_4_5 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5), +South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); + +Arbiter_4_6 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6), +South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); + +Arbiter_4_7 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7), +South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(4)(1), West => east_2_west(4)(7), P => Signal_priority(9), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +Arbiter_5_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5), +South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); + +Arbiter_5_6 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6), +South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); + +Arbiter_5_7 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7), +South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(5)(1), West => east_2_west(5)(7), P => Signal_priority(8), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +Arbiter_6_5 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5), +South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); + +Arbiter_6_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6), +South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); + +Arbiter_6_7 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7), +South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(6)(1), West => east_2_west(6)(7), P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + +Arbiter_7_5 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5), +South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); + +Arbiter_7_6 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6), +South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); + +Arbiter_7_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7), +South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); + +-------------------------- Diagonale n° 8 + + +Arbiter_8_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(7)(1), West => east_2_west(7)(7), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); + +Arbiter_8_2 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); + +Arbiter_8_3 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); + +Arbiter_8_4 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); + +Arbiter_8_5 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5), +South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); + +Arbiter_8_6 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6), +South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); + +Arbiter_8_7 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7), +South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); + +-------------------------- Diagonale n° 9 + + +Arbiter_9_1 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(8)(1), West => east_2_west(8)(7), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); + +Arbiter_9_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); + +Arbiter_9_3 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); + +Arbiter_9_4 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); + +Arbiter_9_5 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5), +South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); + +Arbiter_9_6 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6), +South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); + +Arbiter_9_7 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7), +South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); + +-------------------------- Diagonale n° 10 + + +Arbiter_10_1 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(9)(1), West => east_2_west(9)(7), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); + +Arbiter_10_2 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); + +Arbiter_10_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); + +Arbiter_10_4 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); + +Arbiter_10_5 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5), +South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); + +Arbiter_10_6 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6), +South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); + +Arbiter_10_7 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7), +South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); + +-------------------------- Diagonale n° 11 + + +Arbiter_11_1 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(10)(1), West => east_2_west(10)(7), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); + +Arbiter_11_2 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); + +Arbiter_11_3 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); + +Arbiter_11_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); + +Arbiter_11_5 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5), +South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); + +Arbiter_11_6 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6), +South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); + +Arbiter_11_7 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7), +South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); + +-------------------------- Diagonale n° 12 + + +Arbiter_12_1 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(11)(1), West => east_2_west(11)(7), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); + +Arbiter_12_2 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); + +Arbiter_12_3 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); + +Arbiter_12_4 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); + +Arbiter_12_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5), +South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); + +Arbiter_12_6 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6), +South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); + +Arbiter_12_7 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7), +South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); + +-------------------------- Diagonale n° 13 + + +Arbiter_13_1 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(12)(1), West => east_2_west(12)(7), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); + +Arbiter_13_2 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); + +Arbiter_13_3 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); + +Arbiter_13_4 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); + +Arbiter_13_5 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5), +South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); + +Arbiter_13_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6), +South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); + +Arbiter_13_7 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7), +South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "1111111000000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "1111111000000" => Signal_priority <= "0111111100000"; + when "0111111100000" => Signal_priority <= "0011111110000"; + when "0011111110000" => Signal_priority <= "0001111111000"; + when "0001111111000" => Signal_priority <= "0000111111100"; + when "0000111111100" => Signal_priority <= "0000011111110"; + when "0000011111110" => Signal_priority <= "0000001111111"; + when "0000001111111" => Signal_priority <= "1111111000000"; + when others => Signal_priority <= "1111111000000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER8_8.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER8_8.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER8_8.VHD (revision 138) @@ -0,0 +1,847 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler8_8 is + Port ( Req : in STD_LOGIC_VECTOR (64 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (8 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (8 downto 1); + port_grant : out STD_LOGIC_VECTOR (64 downto 1)); +end Scheduler8_8; + +architecture Behavioral of Scheduler8_8 is +--déclaration de constantes +Constant NB_IO : positive:=8; --le nombre de ports d'entrée/sortie +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(15 downto 1) of STD_LOGIC_VECTOR(NB_IO downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues + +constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +Signal Fifo_out_full : STD_LOGIC_VECTOR (NB_IO downto 1); +SIGNAL Signal_priority : STD_LOGIC_VECTOR (15 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(NB_IO2 downto 1); + signal priority_rotation_en : std_logic; + signal Grant,request,req_grant,Grant_bak : std_logic_vector(NB_IO2 downto 1):=(others=>'0'); + signal Mreq : std_logic_vector(NB_IO2 downto 1):=(others=>'1'); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet + req_grant<=(req and grant ); + priority_rotation_en <= '1' when unsigned(priority_rotation) = 2**NB_IO-1 else '0'; +request<=req and mreq; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + Fifo_out_full<=(others => '0'); + elsif priority_rotation_en = '1' or unsigned(req_grant)=0 then + grant_latch <= Grant; + Fifo_out_full<=fifo_full; + else + grant_latch <= Grant; + Fifo_out_full<=fifo_full; + end if; + end if; + end process; + +def_mreq: process(grant_latch,fifo_full) + +variable t:std_logic_vector(NB_IO2 downto 1):=(others=>'0'); +begin + + + for i in 0 to NB_IO2-1 loop + t(i+1):='0'; + --sur le front montant de fifo_full sauver l'état Grant courant + if fifo_full(i mod NB_IO+1)='1' and fifo_out_full(i mod NB_IO+1)='0' then + Grant_bak(i+1)<= grant_latch(i+1); + elsif fifo_full(i mod NB_IO+1)='0' and fifo_out_full(i mod NB_IO+1)='0' then + Grant_bak(i+1)<='0'; + end if; + for j in 0 to NB_IO-1 loop + t(i+1):=t(i+1) or grant_latch(j*NB_IO+1+i mod NB_IO) or fifo_out_full(i mod NB_IO+1); + + end loop; + mreq(i+1)<=not(t(i+1) ) or grant_latch(i+1)or grant_bak(i+1); + end loop; +end process; + port_grant <= grant; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(9)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(10)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(11)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) or Signal_grant(12)(4); -- Grant(1,4) +Grant(5) <= Signal_grant(5)(5) or Signal_grant(13)(5); -- Grant(1,5) +Grant(6) <= Signal_grant(6)(6) or Signal_grant(14)(6); -- Grant(1,6) +Grant(7) <= Signal_grant(7)(7) or Signal_grant(15)(7); -- Grant(1,7) +Grant(8) <= Signal_grant(8)(8) ; -- Grant(1,8) +Grant(9) <= Signal_grant(2)(1) or Signal_grant(10)(1); -- Grant(2,1) +Grant(10) <= Signal_grant(3)(2) or Signal_grant(11)(2); -- Grant(2,2) +Grant(11) <= Signal_grant(4)(3) or Signal_grant(12)(3); -- Grant(2,3) +Grant(12) <= Signal_grant(5)(4) or Signal_grant(13)(4); -- Grant(2,4) +Grant(13) <= Signal_grant(6)(5) or Signal_grant(14)(5); -- Grant(2,5) +Grant(14) <= Signal_grant(7)(6) or Signal_grant(15)(6); -- Grant(2,6) +Grant(15) <= Signal_grant(8)(7) ; -- Grant(2,7) +Grant(16) <= Signal_grant(1)(8) or Signal_grant(9)(8); -- Grant(2,8) +Grant(17) <= Signal_grant(3)(1) or Signal_grant(11)(1); -- Grant(3,1) +Grant(18) <= Signal_grant(4)(2) or Signal_grant(12)(2); -- Grant(3,2) +Grant(19) <= Signal_grant(5)(3) or Signal_grant(13)(3); -- Grant(3,3) +Grant(20) <= Signal_grant(6)(4) or Signal_grant(14)(4); -- Grant(3,4) +Grant(21) <= Signal_grant(7)(5) or Signal_grant(15)(5); -- Grant(3,5) +Grant(22) <= Signal_grant(8)(6) ; -- Grant(3,6) +Grant(23) <= Signal_grant(1)(7) or Signal_grant(9)(7); -- Grant(3,7) +Grant(24) <= Signal_grant(2)(8) or Signal_grant(10)(8); -- Grant(3,8) +Grant(25) <= Signal_grant(4)(1) or Signal_grant(12)(1); -- Grant(4,1) +Grant(26) <= Signal_grant(5)(2) or Signal_grant(13)(2); -- Grant(4,2) +Grant(27) <= Signal_grant(6)(3) or Signal_grant(14)(3); -- Grant(4,3) +Grant(28) <= Signal_grant(7)(4) or Signal_grant(15)(4); -- Grant(4,4) +Grant(29) <= Signal_grant(8)(5) ; -- Grant(4,5) +Grant(30) <= Signal_grant(1)(6) or Signal_grant(9)(6); -- Grant(4,6) +Grant(31) <= Signal_grant(2)(7) or Signal_grant(10)(7); -- Grant(4,7) +Grant(32) <= Signal_grant(3)(8) or Signal_grant(11)(8); -- Grant(4,8) +Grant(33) <= Signal_grant(5)(1) or Signal_grant(13)(1); -- Grant(5,1) +Grant(34) <= Signal_grant(6)(2) or Signal_grant(14)(2); -- Grant(5,2) +Grant(35) <= Signal_grant(7)(3) or Signal_grant(15)(3); -- Grant(5,3) +Grant(36) <= Signal_grant(8)(4) ; -- Grant(5,4) +Grant(37) <= Signal_grant(1)(5) or Signal_grant(9)(5); -- Grant(5,5) +Grant(38) <= Signal_grant(2)(6) or Signal_grant(10)(6); -- Grant(5,6) +Grant(39) <= Signal_grant(3)(7) or Signal_grant(11)(7); -- Grant(5,7) +Grant(40) <= Signal_grant(4)(8) or Signal_grant(12)(8); -- Grant(5,8) +Grant(41) <= Signal_grant(6)(1) or Signal_grant(14)(1); -- Grant(6,1) +Grant(42) <= Signal_grant(7)(2) or Signal_grant(15)(2); -- Grant(6,2) +Grant(43) <= Signal_grant(8)(3) ; -- Grant(6,3) +Grant(44) <= Signal_grant(1)(4) or Signal_grant(9)(4); -- Grant(6,4) +Grant(45) <= Signal_grant(2)(5) or Signal_grant(10)(5); -- Grant(6,5) +Grant(46) <= Signal_grant(3)(6) or Signal_grant(11)(6); -- Grant(6,6) +Grant(47) <= Signal_grant(4)(7) or Signal_grant(12)(7); -- Grant(6,7) +Grant(48) <= Signal_grant(5)(8) or Signal_grant(13)(8); -- Grant(6,8) +Grant(49) <= Signal_grant(7)(1) or Signal_grant(15)(1); -- Grant(7,1) +Grant(50) <= Signal_grant(8)(2) ; -- Grant(7,2) +Grant(51) <= Signal_grant(1)(3) or Signal_grant(9)(3); -- Grant(7,3) +Grant(52) <= Signal_grant(2)(4) or Signal_grant(10)(4); -- Grant(7,4) +Grant(53) <= Signal_grant(3)(5) or Signal_grant(11)(5); -- Grant(7,5) +Grant(54) <= Signal_grant(4)(6) or Signal_grant(12)(6); -- Grant(7,6) +Grant(55) <= Signal_grant(5)(7) or Signal_grant(13)(7); -- Grant(7,7) +Grant(56) <= Signal_grant(6)(8) or Signal_grant(14)(8); -- Grant(7,8) +Grant(57) <= Signal_grant(8)(1) ; -- Grant(8,1) +Grant(58) <= Signal_grant(1)(2) or Signal_grant(9)(2); -- Grant(8,2) +Grant(59) <= Signal_grant(2)(3) or Signal_grant(10)(3); -- Grant(8,3) +Grant(60) <= Signal_grant(3)(4) or Signal_grant(11)(4); -- Grant(8,4) +Grant(61) <= Signal_grant(4)(5) or Signal_grant(12)(5); -- Grant(8,5) +Grant(62) <= Signal_grant(5)(6) or Signal_grant(13)(6); -- Grant(8,6) +Grant(63) <= Signal_grant(6)(7) or Signal_grant(14)(7); -- Grant(8,7) +Grant(64) <= Signal_grant(7)(8) or Signal_grant(15)(8); -- Grant(8,8) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(58), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(51), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(44), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +Arbiter_1_5 : Arbiter + +PORT MAP (Request => Request(37), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(5), +South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); + +Arbiter_1_6 : Arbiter + +PORT MAP (Request => Request(30), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(6), +South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); + +Arbiter_1_7 : Arbiter + +PORT MAP (Request => Request(23), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(7), +South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); + +Arbiter_1_8 : Arbiter + +PORT MAP (Request => Request(16), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(8), +South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(1)(1), West => east_2_west(1)(8), P => Signal_priority(14), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +Arbiter_2_5 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5), +South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); + +Arbiter_2_6 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6), +South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); + +Arbiter_2_7 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7), +South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); + +Arbiter_2_8 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8), +South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(2)(1), West => east_2_west(2)(8), P => Signal_priority(13), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +Arbiter_3_5 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5), +South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); + +Arbiter_3_6 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6), +South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); + +Arbiter_3_7 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7), +South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); + +Arbiter_3_8 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8), +South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(3)(1), West => east_2_west(3)(8), P => Signal_priority(12), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +Arbiter_4_5 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5), +South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); + +Arbiter_4_6 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6), +South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); + +Arbiter_4_7 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7), +South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); + +Arbiter_4_8 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8), +South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(4)(1), West => east_2_west(4)(8), P => Signal_priority(11), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +Arbiter_5_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5), +South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); + +Arbiter_5_6 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6), +South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); + +Arbiter_5_7 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7), +South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); + +Arbiter_5_8 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8), +South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(5)(1), West => east_2_west(5)(8), P => Signal_priority(10), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +Arbiter_6_5 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5), +South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); + +Arbiter_6_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6), +South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); + +Arbiter_6_7 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7), +South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); + +Arbiter_6_8 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8), +South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(6)(1), West => east_2_west(6)(8), P => Signal_priority(9), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + +Arbiter_7_5 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5), +South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); + +Arbiter_7_6 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6), +South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); + +Arbiter_7_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7), +South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); + +Arbiter_7_8 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8), +South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); + +-------------------------- Diagonale n° 8 + + +Arbiter_8_1 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(7)(1), West => east_2_west(7)(8), P => Signal_priority(8), Fifo_full => Fifo_full(1), +South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); + +Arbiter_8_2 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2), +South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); + +Arbiter_8_3 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3), +South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); + +Arbiter_8_4 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4), +South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); + +Arbiter_8_5 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5), +South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); + +Arbiter_8_6 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6), +South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); + +Arbiter_8_7 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7), +South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); + +Arbiter_8_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8), +South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); + +-------------------------- Diagonale n° 9 + + +Arbiter_9_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(8)(1), West => east_2_west(8)(8), P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); + +Arbiter_9_2 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); + +Arbiter_9_3 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); + +Arbiter_9_4 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); + +Arbiter_9_5 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5), +South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); + +Arbiter_9_6 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6), +South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); + +Arbiter_9_7 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7), +South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); + +Arbiter_9_8 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8), +South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); + +-------------------------- Diagonale n° 10 + + +Arbiter_10_1 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(9)(1), West => east_2_west(9)(8), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); + +Arbiter_10_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); + +Arbiter_10_3 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); + +Arbiter_10_4 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); + +Arbiter_10_5 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5), +South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); + +Arbiter_10_6 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6), +South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); + +Arbiter_10_7 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7), +South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); + +Arbiter_10_8 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8), +South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); + +-------------------------- Diagonale n° 11 + + +Arbiter_11_1 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(10)(1), West => east_2_west(10)(8), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); + +Arbiter_11_2 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); + +Arbiter_11_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); + +Arbiter_11_4 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); + +Arbiter_11_5 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5), +South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); + +Arbiter_11_6 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6), +South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); + +Arbiter_11_7 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7), +South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); + +Arbiter_11_8 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8), +South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); + +-------------------------- Diagonale n° 12 + + +Arbiter_12_1 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(11)(1), West => east_2_west(11)(8), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); + +Arbiter_12_2 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); + +Arbiter_12_3 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); + +Arbiter_12_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); + +Arbiter_12_5 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5), +South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); + +Arbiter_12_6 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6), +South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); + +Arbiter_12_7 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7), +South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); + +Arbiter_12_8 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8), +South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); + +-------------------------- Diagonale n° 13 + + +Arbiter_13_1 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(12)(1), West => east_2_west(12)(8), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); + +Arbiter_13_2 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); + +Arbiter_13_3 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); + +Arbiter_13_4 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); + +Arbiter_13_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5), +South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); + +Arbiter_13_6 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6), +South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); + +Arbiter_13_7 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7), +South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); + +Arbiter_13_8 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8), +South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); + +-------------------------- Diagonale n° 14 + + +Arbiter_14_1 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(13)(1), West => east_2_west(13)(8), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); + +Arbiter_14_2 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); + +Arbiter_14_3 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); + +Arbiter_14_4 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); + +Arbiter_14_5 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5), +South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); + +Arbiter_14_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6), +South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); + +Arbiter_14_7 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7), +South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); + +Arbiter_14_8 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8), +South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); + +-------------------------- Diagonale n° 15 + + +Arbiter_15_1 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(14)(1), West => east_2_west(14)(8), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); + +Arbiter_15_2 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); + +Arbiter_15_3 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); + +Arbiter_15_4 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); + +Arbiter_15_5 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5), +South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); + +Arbiter_15_6 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6), +South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); + +Arbiter_15_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7), +South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); + +Arbiter_15_8 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8), +South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "111111110000000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "111111110000000" => Signal_priority <= "011111111000000"; + when "011111111000000" => Signal_priority <= "001111111100000"; + when "001111111100000" => Signal_priority <= "000111111110000"; + when "000111111110000" => Signal_priority <= "000011111111000"; + when "000011111111000" => Signal_priority <= "000001111111100"; + when "000001111111100" => Signal_priority <= "000000111111110"; + when "000000111111110" => Signal_priority <= "000000011111111"; + when "000000011111111" => Signal_priority <= "111111110000000"; + when others => Signal_priority <= "111111110000000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER8_8.VHD.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER8_8.VHD.bak (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER8_8.VHD.bak (revision 138) @@ -0,0 +1,845 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler8_8 is + Port ( Req : in STD_LOGIC_VECTOR (64 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (8 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (8 downto 1); + port_grant : out STD_LOGIC_VECTOR (64 downto 1)); +end Scheduler8_8; + +architecture Behavioral of Scheduler8_8 is +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(15 downto 1) of STD_LOGIC_VECTOR(8 downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +Constant NB_IO : positive:=8; --le nombre de ports d'entrée/sortie +constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +Signal Fifo_out_full : STD_LOGIC_VECTOR (NB_IO downto 1); +SIGNAL Signal_priority : STD_LOGIC_VECTOR (15 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(NB_IO2 downto 1); + signal priority_rotation_en : std_logic; + signal Grant,request,req_grant,Grant_bak : std_logic_vector(NB_IO2 downto 1):=(others=>'0'); + signal Mreq : std_logic_vector(NB_IO2 downto 1):=(others=>'1'); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet + req_grant<=(req and grant ); + priority_rotation_en <= '1' when unsigned(priority_rotation) = 2**NB_IO-1 else '0'; +request<=req and mreq; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + Fifo_out_full<=(others => '0'); + elsif priority_rotation_en = '1' or unsigned(req_grant)=0 then + grant_latch <= Grant; + Fifo_out_full<=fifo_full; + else + grant_latch <= Grant; + Fifo_out_full<=fifo_full; + end if; + end if; + end process; + +def_mreq: process(grant_latch,fifo_full) + +variable t:std_logic_vector(NB_IO2 downto 1):=(others=>'0'); +begin + + + for i in 0 to NB_IO2-1 loop + t(i+1):='0'; + --sur le front montant de fifo_full sauver l'état Grant courant + if fifo_full(i mod NB_IO+1)='1' and fifo_out_full(i mod NB_IO+1)='0' then + Grant_bak(i+1)<= grant_latch(i+1); + elsif fifo_full(i mod NB_IO+1)='0' and fifo_out_full(i mod NB_IO+1)='0' then + Grant_bak(i+1)<='0'; + end if; + for j in 0 to NB_IO-1 loop + t(i+1):=t(i+1) or grant_latch(j*NB_IO+1+i mod NB_IO) or fifo_out_full(i mod NB_IO+1); + + end loop; + mreq(i+1)<=not(t(i+1) ) or grant_latch(i+1)or grant_bak(i+1); + end loop; +end process; + port_grant <= grant; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(9)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(10)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(11)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) or Signal_grant(12)(4); -- Grant(1,4) +Grant(5) <= Signal_grant(5)(5) or Signal_grant(13)(5); -- Grant(1,5) +Grant(6) <= Signal_grant(6)(6) or Signal_grant(14)(6); -- Grant(1,6) +Grant(7) <= Signal_grant(7)(7) or Signal_grant(15)(7); -- Grant(1,7) +Grant(8) <= Signal_grant(8)(8) ; -- Grant(1,8) +Grant(9) <= Signal_grant(2)(1) or Signal_grant(10)(1); -- Grant(2,1) +Grant(10) <= Signal_grant(3)(2) or Signal_grant(11)(2); -- Grant(2,2) +Grant(11) <= Signal_grant(4)(3) or Signal_grant(12)(3); -- Grant(2,3) +Grant(12) <= Signal_grant(5)(4) or Signal_grant(13)(4); -- Grant(2,4) +Grant(13) <= Signal_grant(6)(5) or Signal_grant(14)(5); -- Grant(2,5) +Grant(14) <= Signal_grant(7)(6) or Signal_grant(15)(6); -- Grant(2,6) +Grant(15) <= Signal_grant(8)(7) ; -- Grant(2,7) +Grant(16) <= Signal_grant(1)(8) or Signal_grant(9)(8); -- Grant(2,8) +Grant(17) <= Signal_grant(3)(1) or Signal_grant(11)(1); -- Grant(3,1) +Grant(18) <= Signal_grant(4)(2) or Signal_grant(12)(2); -- Grant(3,2) +Grant(19) <= Signal_grant(5)(3) or Signal_grant(13)(3); -- Grant(3,3) +Grant(20) <= Signal_grant(6)(4) or Signal_grant(14)(4); -- Grant(3,4) +Grant(21) <= Signal_grant(7)(5) or Signal_grant(15)(5); -- Grant(3,5) +Grant(22) <= Signal_grant(8)(6) ; -- Grant(3,6) +Grant(23) <= Signal_grant(1)(7) or Signal_grant(9)(7); -- Grant(3,7) +Grant(24) <= Signal_grant(2)(8) or Signal_grant(10)(8); -- Grant(3,8) +Grant(25) <= Signal_grant(4)(1) or Signal_grant(12)(1); -- Grant(4,1) +Grant(26) <= Signal_grant(5)(2) or Signal_grant(13)(2); -- Grant(4,2) +Grant(27) <= Signal_grant(6)(3) or Signal_grant(14)(3); -- Grant(4,3) +Grant(28) <= Signal_grant(7)(4) or Signal_grant(15)(4); -- Grant(4,4) +Grant(29) <= Signal_grant(8)(5) ; -- Grant(4,5) +Grant(30) <= Signal_grant(1)(6) or Signal_grant(9)(6); -- Grant(4,6) +Grant(31) <= Signal_grant(2)(7) or Signal_grant(10)(7); -- Grant(4,7) +Grant(32) <= Signal_grant(3)(8) or Signal_grant(11)(8); -- Grant(4,8) +Grant(33) <= Signal_grant(5)(1) or Signal_grant(13)(1); -- Grant(5,1) +Grant(34) <= Signal_grant(6)(2) or Signal_grant(14)(2); -- Grant(5,2) +Grant(35) <= Signal_grant(7)(3) or Signal_grant(15)(3); -- Grant(5,3) +Grant(36) <= Signal_grant(8)(4) ; -- Grant(5,4) +Grant(37) <= Signal_grant(1)(5) or Signal_grant(9)(5); -- Grant(5,5) +Grant(38) <= Signal_grant(2)(6) or Signal_grant(10)(6); -- Grant(5,6) +Grant(39) <= Signal_grant(3)(7) or Signal_grant(11)(7); -- Grant(5,7) +Grant(40) <= Signal_grant(4)(8) or Signal_grant(12)(8); -- Grant(5,8) +Grant(41) <= Signal_grant(6)(1) or Signal_grant(14)(1); -- Grant(6,1) +Grant(42) <= Signal_grant(7)(2) or Signal_grant(15)(2); -- Grant(6,2) +Grant(43) <= Signal_grant(8)(3) ; -- Grant(6,3) +Grant(44) <= Signal_grant(1)(4) or Signal_grant(9)(4); -- Grant(6,4) +Grant(45) <= Signal_grant(2)(5) or Signal_grant(10)(5); -- Grant(6,5) +Grant(46) <= Signal_grant(3)(6) or Signal_grant(11)(6); -- Grant(6,6) +Grant(47) <= Signal_grant(4)(7) or Signal_grant(12)(7); -- Grant(6,7) +Grant(48) <= Signal_grant(5)(8) or Signal_grant(13)(8); -- Grant(6,8) +Grant(49) <= Signal_grant(7)(1) or Signal_grant(15)(1); -- Grant(7,1) +Grant(50) <= Signal_grant(8)(2) ; -- Grant(7,2) +Grant(51) <= Signal_grant(1)(3) or Signal_grant(9)(3); -- Grant(7,3) +Grant(52) <= Signal_grant(2)(4) or Signal_grant(10)(4); -- Grant(7,4) +Grant(53) <= Signal_grant(3)(5) or Signal_grant(11)(5); -- Grant(7,5) +Grant(54) <= Signal_grant(4)(6) or Signal_grant(12)(6); -- Grant(7,6) +Grant(55) <= Signal_grant(5)(7) or Signal_grant(13)(7); -- Grant(7,7) +Grant(56) <= Signal_grant(6)(8) or Signal_grant(14)(8); -- Grant(7,8) +Grant(57) <= Signal_grant(8)(1) ; -- Grant(8,1) +Grant(58) <= Signal_grant(1)(2) or Signal_grant(9)(2); -- Grant(8,2) +Grant(59) <= Signal_grant(2)(3) or Signal_grant(10)(3); -- Grant(8,3) +Grant(60) <= Signal_grant(3)(4) or Signal_grant(11)(4); -- Grant(8,4) +Grant(61) <= Signal_grant(4)(5) or Signal_grant(12)(5); -- Grant(8,5) +Grant(62) <= Signal_grant(5)(6) or Signal_grant(13)(6); -- Grant(8,6) +Grant(63) <= Signal_grant(6)(7) or Signal_grant(14)(7); -- Grant(8,7) +Grant(64) <= Signal_grant(7)(8) or Signal_grant(15)(8); -- Grant(8,8) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(58), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(51), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(44), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +Arbiter_1_5 : Arbiter + +PORT MAP (Request => Request(37), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(5), +South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); + +Arbiter_1_6 : Arbiter + +PORT MAP (Request => Request(30), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(6), +South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); + +Arbiter_1_7 : Arbiter + +PORT MAP (Request => Request(23), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(7), +South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); + +Arbiter_1_8 : Arbiter + +PORT MAP (Request => Request(16), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(8), +South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(1)(1), West => east_2_west(1)(8), P => Signal_priority(14), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +Arbiter_2_5 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5), +South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); + +Arbiter_2_6 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6), +South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); + +Arbiter_2_7 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7), +South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); + +Arbiter_2_8 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8), +South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(2)(1), West => east_2_west(2)(8), P => Signal_priority(13), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +Arbiter_3_5 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5), +South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); + +Arbiter_3_6 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6), +South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); + +Arbiter_3_7 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7), +South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); + +Arbiter_3_8 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8), +South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(3)(1), West => east_2_west(3)(8), P => Signal_priority(12), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +Arbiter_4_5 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5), +South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); + +Arbiter_4_6 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6), +South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); + +Arbiter_4_7 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7), +South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); + +Arbiter_4_8 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8), +South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(4)(1), West => east_2_west(4)(8), P => Signal_priority(11), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +Arbiter_5_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5), +South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); + +Arbiter_5_6 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6), +South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); + +Arbiter_5_7 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7), +South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); + +Arbiter_5_8 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8), +South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(5)(1), West => east_2_west(5)(8), P => Signal_priority(10), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +Arbiter_6_5 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5), +South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); + +Arbiter_6_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6), +South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); + +Arbiter_6_7 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7), +South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); + +Arbiter_6_8 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8), +South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(6)(1), West => east_2_west(6)(8), P => Signal_priority(9), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + +Arbiter_7_5 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5), +South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); + +Arbiter_7_6 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6), +South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); + +Arbiter_7_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7), +South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); + +Arbiter_7_8 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8), +South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); + +-------------------------- Diagonale n° 8 + + +Arbiter_8_1 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(7)(1), West => east_2_west(7)(8), P => Signal_priority(8), Fifo_full => Fifo_full(1), +South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); + +Arbiter_8_2 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2), +South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); + +Arbiter_8_3 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3), +South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); + +Arbiter_8_4 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4), +South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); + +Arbiter_8_5 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5), +South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); + +Arbiter_8_6 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6), +South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); + +Arbiter_8_7 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7), +South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); + +Arbiter_8_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8), +South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); + +-------------------------- Diagonale n° 9 + + +Arbiter_9_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(8)(1), West => east_2_west(8)(8), P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); + +Arbiter_9_2 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); + +Arbiter_9_3 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); + +Arbiter_9_4 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); + +Arbiter_9_5 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5), +South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); + +Arbiter_9_6 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6), +South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); + +Arbiter_9_7 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7), +South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); + +Arbiter_9_8 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8), +South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); + +-------------------------- Diagonale n° 10 + + +Arbiter_10_1 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(9)(1), West => east_2_west(9)(8), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); + +Arbiter_10_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); + +Arbiter_10_3 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); + +Arbiter_10_4 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); + +Arbiter_10_5 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5), +South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); + +Arbiter_10_6 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6), +South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); + +Arbiter_10_7 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7), +South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); + +Arbiter_10_8 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8), +South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); + +-------------------------- Diagonale n° 11 + + +Arbiter_11_1 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(10)(1), West => east_2_west(10)(8), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); + +Arbiter_11_2 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); + +Arbiter_11_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); + +Arbiter_11_4 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); + +Arbiter_11_5 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5), +South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); + +Arbiter_11_6 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6), +South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); + +Arbiter_11_7 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7), +South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); + +Arbiter_11_8 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8), +South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); + +-------------------------- Diagonale n° 12 + + +Arbiter_12_1 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(11)(1), West => east_2_west(11)(8), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); + +Arbiter_12_2 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); + +Arbiter_12_3 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); + +Arbiter_12_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); + +Arbiter_12_5 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5), +South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); + +Arbiter_12_6 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6), +South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); + +Arbiter_12_7 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7), +South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); + +Arbiter_12_8 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8), +South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); + +-------------------------- Diagonale n° 13 + + +Arbiter_13_1 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(12)(1), West => east_2_west(12)(8), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); + +Arbiter_13_2 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); + +Arbiter_13_3 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); + +Arbiter_13_4 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); + +Arbiter_13_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5), +South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); + +Arbiter_13_6 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6), +South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); + +Arbiter_13_7 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7), +South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); + +Arbiter_13_8 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8), +South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); + +-------------------------- Diagonale n° 14 + + +Arbiter_14_1 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(13)(1), West => east_2_west(13)(8), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); + +Arbiter_14_2 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); + +Arbiter_14_3 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); + +Arbiter_14_4 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); + +Arbiter_14_5 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5), +South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); + +Arbiter_14_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6), +South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); + +Arbiter_14_7 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7), +South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); + +Arbiter_14_8 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8), +South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); + +-------------------------- Diagonale n° 15 + + +Arbiter_15_1 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(14)(1), West => east_2_west(14)(8), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); + +Arbiter_15_2 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); + +Arbiter_15_3 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); + +Arbiter_15_4 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); + +Arbiter_15_5 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5), +South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); + +Arbiter_15_6 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6), +South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); + +Arbiter_15_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7), +South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); + +Arbiter_15_8 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8), +South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "111111110000000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "111111110000000" => Signal_priority <= "011111111000000"; + when "011111111000000" => Signal_priority <= "001111111100000"; + when "001111111100000" => Signal_priority <= "000111111110000"; + when "000111111110000" => Signal_priority <= "000011111111000"; + when "000011111111000" => Signal_priority <= "000001111111100"; + when "000001111111100" => Signal_priority <= "000000111111110"; + when "000000111111110" => Signal_priority <= "000000011111111"; + when "000000011111111" => Signal_priority <= "111111110000000"; + when others => Signal_priority <= "111111110000000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER9_9.VHD =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER9_9.VHD (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SCHEDULER9_9.VHD (revision 138) @@ -0,0 +1,1001 @@ +--------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 03:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisée est le DPA (diagonal propagation arbiter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Scheduler9_9 is + Port ( Request : in STD_LOGIC_VECTOR (81 downto 1); + Fifo_full : in STD_LOGIC_VECTOR (9 downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (9 downto 1); + port_grant : out STD_LOGIC_VECTOR (81 downto 1)); +end Scheduler9_9; + +architecture Behavioral of Scheduler9_9 is +--Declaration du types +--tableau de signaux de connexion des cellules arbitres +TYPE C_Bar_Signal_Array IS ARRAY(17 downto 1) of STD_LOGIC_VECTOR(9 downto 1); +-- declaration du composant cellule d'arbitrage +Component Arbiter + PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; + Grant,East,South : out STD_LOGIC ); +End Component;--Signaux de connexion des cellues +SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north +SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west +SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité +SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation +SIGNAL Signal_priority : STD_LOGIC_VECTOR (17 DOWNTO 1);--signal pour la connection des vecteur de priorité +SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest + signal grant_latch : std_logic_vector(81 downto 1); + signal priority_rotation_en : std_logic; + signal Grant : std_logic_vector(81 downto 1); + begin + +--validation de la rotation de priorité lorsque aucun port n'emet + priority_rotation_en <= '1' when unsigned(priority_rotation) = 511 else '0'; +--latch servant qui memorise le signal grant pendant a transmission +grant_latch_process : process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + grant_latch <= (others => '0'); + elsif priority_rotation_en = '1' then + grant_latch <= Grant; + end if; + end if; + end process; + port_grant <= Grant and grant_latch; + Grant(1) <= Signal_grant(1)(1) or Signal_grant(10)(1); -- Grant(1,1) +Grant(2) <= Signal_grant(2)(2) or Signal_grant(11)(2); -- Grant(1,2) +Grant(3) <= Signal_grant(3)(3) or Signal_grant(12)(3); -- Grant(1,3) +Grant(4) <= Signal_grant(4)(4) or Signal_grant(13)(4); -- Grant(1,4) +Grant(5) <= Signal_grant(5)(5) or Signal_grant(14)(5); -- Grant(1,5) +Grant(6) <= Signal_grant(6)(6) or Signal_grant(15)(6); -- Grant(1,6) +Grant(7) <= Signal_grant(7)(7) or Signal_grant(16)(7); -- Grant(1,7) +Grant(8) <= Signal_grant(8)(8) or Signal_grant(17)(8); -- Grant(1,8) +Grant(9) <= Signal_grant(9)(9) ; -- Grant(1,9) +Grant(10) <= Signal_grant(2)(1) or Signal_grant(11)(1); -- Grant(2,1) +Grant(11) <= Signal_grant(3)(2) or Signal_grant(12)(2); -- Grant(2,2) +Grant(12) <= Signal_grant(4)(3) or Signal_grant(13)(3); -- Grant(2,3) +Grant(13) <= Signal_grant(5)(4) or Signal_grant(14)(4); -- Grant(2,4) +Grant(14) <= Signal_grant(6)(5) or Signal_grant(15)(5); -- Grant(2,5) +Grant(15) <= Signal_grant(7)(6) or Signal_grant(16)(6); -- Grant(2,6) +Grant(16) <= Signal_grant(8)(7) or Signal_grant(17)(7); -- Grant(2,7) +Grant(17) <= Signal_grant(9)(8) ; -- Grant(2,8) +Grant(18) <= Signal_grant(1)(9) or Signal_grant(10)(9); -- Grant(2,9) +Grant(19) <= Signal_grant(3)(1) or Signal_grant(12)(1); -- Grant(3,1) +Grant(20) <= Signal_grant(4)(2) or Signal_grant(13)(2); -- Grant(3,2) +Grant(21) <= Signal_grant(5)(3) or Signal_grant(14)(3); -- Grant(3,3) +Grant(22) <= Signal_grant(6)(4) or Signal_grant(15)(4); -- Grant(3,4) +Grant(23) <= Signal_grant(7)(5) or Signal_grant(16)(5); -- Grant(3,5) +Grant(24) <= Signal_grant(8)(6) or Signal_grant(17)(6); -- Grant(3,6) +Grant(25) <= Signal_grant(9)(7) ; -- Grant(3,7) +Grant(26) <= Signal_grant(1)(8) or Signal_grant(10)(8); -- Grant(3,8) +Grant(27) <= Signal_grant(2)(9) or Signal_grant(11)(9); -- Grant(3,9) +Grant(28) <= Signal_grant(4)(1) or Signal_grant(13)(1); -- Grant(4,1) +Grant(29) <= Signal_grant(5)(2) or Signal_grant(14)(2); -- Grant(4,2) +Grant(30) <= Signal_grant(6)(3) or Signal_grant(15)(3); -- Grant(4,3) +Grant(31) <= Signal_grant(7)(4) or Signal_grant(16)(4); -- Grant(4,4) +Grant(32) <= Signal_grant(8)(5) or Signal_grant(17)(5); -- Grant(4,5) +Grant(33) <= Signal_grant(9)(6) ; -- Grant(4,6) +Grant(34) <= Signal_grant(1)(7) or Signal_grant(10)(7); -- Grant(4,7) +Grant(35) <= Signal_grant(2)(8) or Signal_grant(11)(8); -- Grant(4,8) +Grant(36) <= Signal_grant(3)(9) or Signal_grant(12)(9); -- Grant(4,9) +Grant(37) <= Signal_grant(5)(1) or Signal_grant(14)(1); -- Grant(5,1) +Grant(38) <= Signal_grant(6)(2) or Signal_grant(15)(2); -- Grant(5,2) +Grant(39) <= Signal_grant(7)(3) or Signal_grant(16)(3); -- Grant(5,3) +Grant(40) <= Signal_grant(8)(4) or Signal_grant(17)(4); -- Grant(5,4) +Grant(41) <= Signal_grant(9)(5) ; -- Grant(5,5) +Grant(42) <= Signal_grant(1)(6) or Signal_grant(10)(6); -- Grant(5,6) +Grant(43) <= Signal_grant(2)(7) or Signal_grant(11)(7); -- Grant(5,7) +Grant(44) <= Signal_grant(3)(8) or Signal_grant(12)(8); -- Grant(5,8) +Grant(45) <= Signal_grant(4)(9) or Signal_grant(13)(9); -- Grant(5,9) +Grant(46) <= Signal_grant(6)(1) or Signal_grant(15)(1); -- Grant(6,1) +Grant(47) <= Signal_grant(7)(2) or Signal_grant(16)(2); -- Grant(6,2) +Grant(48) <= Signal_grant(8)(3) or Signal_grant(17)(3); -- Grant(6,3) +Grant(49) <= Signal_grant(9)(4) ; -- Grant(6,4) +Grant(50) <= Signal_grant(1)(5) or Signal_grant(10)(5); -- Grant(6,5) +Grant(51) <= Signal_grant(2)(6) or Signal_grant(11)(6); -- Grant(6,6) +Grant(52) <= Signal_grant(3)(7) or Signal_grant(12)(7); -- Grant(6,7) +Grant(53) <= Signal_grant(4)(8) or Signal_grant(13)(8); -- Grant(6,8) +Grant(54) <= Signal_grant(5)(9) or Signal_grant(14)(9); -- Grant(6,9) +Grant(55) <= Signal_grant(7)(1) or Signal_grant(16)(1); -- Grant(7,1) +Grant(56) <= Signal_grant(8)(2) or Signal_grant(17)(2); -- Grant(7,2) +Grant(57) <= Signal_grant(9)(3) ; -- Grant(7,3) +Grant(58) <= Signal_grant(1)(4) or Signal_grant(10)(4); -- Grant(7,4) +Grant(59) <= Signal_grant(2)(5) or Signal_grant(11)(5); -- Grant(7,5) +Grant(60) <= Signal_grant(3)(6) or Signal_grant(12)(6); -- Grant(7,6) +Grant(61) <= Signal_grant(4)(7) or Signal_grant(13)(7); -- Grant(7,7) +Grant(62) <= Signal_grant(5)(8) or Signal_grant(14)(8); -- Grant(7,8) +Grant(63) <= Signal_grant(6)(9) or Signal_grant(15)(9); -- Grant(7,9) +Grant(64) <= Signal_grant(8)(1) or Signal_grant(17)(1); -- Grant(8,1) +Grant(65) <= Signal_grant(9)(2) ; -- Grant(8,2) +Grant(66) <= Signal_grant(1)(3) or Signal_grant(10)(3); -- Grant(8,3) +Grant(67) <= Signal_grant(2)(4) or Signal_grant(11)(4); -- Grant(8,4) +Grant(68) <= Signal_grant(3)(5) or Signal_grant(12)(5); -- Grant(8,5) +Grant(69) <= Signal_grant(4)(6) or Signal_grant(13)(6); -- Grant(8,6) +Grant(70) <= Signal_grant(5)(7) or Signal_grant(14)(7); -- Grant(8,7) +Grant(71) <= Signal_grant(6)(8) or Signal_grant(15)(8); -- Grant(8,8) +Grant(72) <= Signal_grant(7)(9) or Signal_grant(16)(9); -- Grant(8,9) +Grant(73) <= Signal_grant(9)(1) ; -- Grant(9,1) +Grant(74) <= Signal_grant(1)(2) or Signal_grant(10)(2); -- Grant(9,2) +Grant(75) <= Signal_grant(2)(3) or Signal_grant(11)(3); -- Grant(9,3) +Grant(76) <= Signal_grant(3)(4) or Signal_grant(12)(4); -- Grant(9,4) +Grant(77) <= Signal_grant(4)(5) or Signal_grant(13)(5); -- Grant(9,5) +Grant(78) <= Signal_grant(5)(6) or Signal_grant(14)(6); -- Grant(9,6) +Grant(79) <= Signal_grant(6)(7) or Signal_grant(15)(7); -- Grant(9,7) +Grant(80) <= Signal_grant(7)(8) or Signal_grant(16)(8); -- Grant(9,8) +Grant(81) <= Signal_grant(8)(9) or Signal_grant(17)(9); -- Grant(9,9) +High <= '1'; + +----instantiations des cellules arbitres et interconnection + +-------------------------- Diagonale n° 1 + + +Arbiter_1_1 : Arbiter + +PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(1), +South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); + +Arbiter_1_2 : Arbiter + +PORT MAP (Request => Request(74), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(2), +South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); + +Arbiter_1_3 : Arbiter + +PORT MAP (Request => Request(66), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(3), +South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); + +Arbiter_1_4 : Arbiter + +PORT MAP (Request => Request(58), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(4), +South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); + +Arbiter_1_5 : Arbiter + +PORT MAP (Request => Request(50), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(5), +South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); + +Arbiter_1_6 : Arbiter + +PORT MAP (Request => Request(42), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(6), +South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); + +Arbiter_1_7 : Arbiter + +PORT MAP (Request => Request(34), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(7), +South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); + +Arbiter_1_8 : Arbiter + +PORT MAP (Request => Request(26), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(8), +South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); + +Arbiter_1_9 : Arbiter + +PORT MAP (Request => Request(18), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(9), +South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); + +-------------------------- Diagonale n° 2 + + +Arbiter_2_1 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(1)(1), West => east_2_west(1)(9), P => Signal_priority(16), Fifo_full => Fifo_full(1), +South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); + +Arbiter_2_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2), +South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); + +Arbiter_2_3 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3), +South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); + +Arbiter_2_4 : Arbiter + +PORT MAP (Request => Request(67), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4), +South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); + +Arbiter_2_5 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5), +South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); + +Arbiter_2_6 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6), +South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); + +Arbiter_2_7 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7), +South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); + +Arbiter_2_8 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8), +South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); + +Arbiter_2_9 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9), +South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); + +-------------------------- Diagonale n° 3 + + +Arbiter_3_1 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(2)(1), West => east_2_west(2)(9), P => Signal_priority(15), Fifo_full => Fifo_full(1), +South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); + +Arbiter_3_2 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2), +South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); + +Arbiter_3_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3), +South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); + +Arbiter_3_4 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4), +South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); + +Arbiter_3_5 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5), +South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); + +Arbiter_3_6 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6), +South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); + +Arbiter_3_7 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7), +South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); + +Arbiter_3_8 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8), +South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); + +Arbiter_3_9 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9), +South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); + +-------------------------- Diagonale n° 4 + + +Arbiter_4_1 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(3)(1), West => east_2_west(3)(9), P => Signal_priority(14), Fifo_full => Fifo_full(1), +South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); + +Arbiter_4_2 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2), +South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); + +Arbiter_4_3 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3), +South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); + +Arbiter_4_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4), +South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); + +Arbiter_4_5 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5), +South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); + +Arbiter_4_6 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6), +South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); + +Arbiter_4_7 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7), +South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); + +Arbiter_4_8 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8), +South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); + +Arbiter_4_9 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9), +South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); + +-------------------------- Diagonale n° 5 + + +Arbiter_5_1 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(4)(1), West => east_2_west(4)(9), P => Signal_priority(13), Fifo_full => Fifo_full(1), +South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); + +Arbiter_5_2 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2), +South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); + +Arbiter_5_3 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3), +South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); + +Arbiter_5_4 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4), +South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); + +Arbiter_5_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5), +South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); + +Arbiter_5_6 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6), +South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); + +Arbiter_5_7 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7), +South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); + +Arbiter_5_8 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8), +South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); + +Arbiter_5_9 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9), +South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); + +-------------------------- Diagonale n° 6 + + +Arbiter_6_1 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(5)(1), West => east_2_west(5)(9), P => Signal_priority(12), Fifo_full => Fifo_full(1), +South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); + +Arbiter_6_2 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2), +South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); + +Arbiter_6_3 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3), +South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); + +Arbiter_6_4 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4), +South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); + +Arbiter_6_5 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5), +South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); + +Arbiter_6_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6), +South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); + +Arbiter_6_7 : Arbiter + +PORT MAP (Request => Request(79), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7), +South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); + +Arbiter_6_8 : Arbiter + +PORT MAP (Request => Request(71), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8), +South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); + +Arbiter_6_9 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9), +South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); + +-------------------------- Diagonale n° 7 + + +Arbiter_7_1 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(6)(1), West => east_2_west(6)(9), P => Signal_priority(11), Fifo_full => Fifo_full(1), +South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); + +Arbiter_7_2 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2), +South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); + +Arbiter_7_3 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3), +South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); + +Arbiter_7_4 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4), +South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); + +Arbiter_7_5 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5), +South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); + +Arbiter_7_6 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6), +South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); + +Arbiter_7_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7), +South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); + +Arbiter_7_8 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8), +South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); + +Arbiter_7_9 : Arbiter + +PORT MAP (Request => Request(72), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9), +South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); + +-------------------------- Diagonale n° 8 + + +Arbiter_8_1 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(7)(1), West => east_2_west(7)(9), P => Signal_priority(10), Fifo_full => Fifo_full(1), +South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); + +Arbiter_8_2 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2), +South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); + +Arbiter_8_3 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3), +South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); + +Arbiter_8_4 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4), +South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); + +Arbiter_8_5 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5), +South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); + +Arbiter_8_6 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6), +South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); + +Arbiter_8_7 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7), +South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); + +Arbiter_8_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8), +South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); + +Arbiter_8_9 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9), +South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); + +-------------------------- Diagonale n° 9 + + +Arbiter_9_1 : Arbiter + +PORT MAP (Request => Request(73), North => south_2_north(8)(1), West => east_2_west(8)(9), P => Signal_priority(9), Fifo_full => Fifo_full(1), +South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); + +Arbiter_9_2 : Arbiter + +PORT MAP (Request => Request(65), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2), +South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); + +Arbiter_9_3 : Arbiter + +PORT MAP (Request => Request(57), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3), +South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); + +Arbiter_9_4 : Arbiter + +PORT MAP (Request => Request(49), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4), +South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); + +Arbiter_9_5 : Arbiter + +PORT MAP (Request => Request(41), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5), +South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); + +Arbiter_9_6 : Arbiter + +PORT MAP (Request => Request(33), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6), +South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); + +Arbiter_9_7 : Arbiter + +PORT MAP (Request => Request(25), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7), +South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); + +Arbiter_9_8 : Arbiter + +PORT MAP (Request => Request(17), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8), +South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); + +Arbiter_9_9 : Arbiter + +PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9), +South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); + +-------------------------- Diagonale n° 10 + + +Arbiter_10_1 : Arbiter + +PORT MAP (Request => Request(1), North => south_2_north(9)(1), West => east_2_west(9)(9), P => Signal_priority(8), Fifo_full => Fifo_full(1), +South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); + +Arbiter_10_2 : Arbiter + +PORT MAP (Request => Request(74), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2), +South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); + +Arbiter_10_3 : Arbiter + +PORT MAP (Request => Request(66), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3), +South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); + +Arbiter_10_4 : Arbiter + +PORT MAP (Request => Request(58), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4), +South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); + +Arbiter_10_5 : Arbiter + +PORT MAP (Request => Request(50), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5), +South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); + +Arbiter_10_6 : Arbiter + +PORT MAP (Request => Request(42), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6), +South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); + +Arbiter_10_7 : Arbiter + +PORT MAP (Request => Request(34), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7), +South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); + +Arbiter_10_8 : Arbiter + +PORT MAP (Request => Request(26), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8), +South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); + +Arbiter_10_9 : Arbiter + +PORT MAP (Request => Request(18), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9), +South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); + +-------------------------- Diagonale n° 11 + + +Arbiter_11_1 : Arbiter + +PORT MAP (Request => Request(10), North => south_2_north(10)(1), West => east_2_west(10)(9), P => Signal_priority(7), Fifo_full => Fifo_full(1), +South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); + +Arbiter_11_2 : Arbiter + +PORT MAP (Request => Request(2), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2), +South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); + +Arbiter_11_3 : Arbiter + +PORT MAP (Request => Request(75), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3), +South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); + +Arbiter_11_4 : Arbiter + +PORT MAP (Request => Request(67), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4), +South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); + +Arbiter_11_5 : Arbiter + +PORT MAP (Request => Request(59), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5), +South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); + +Arbiter_11_6 : Arbiter + +PORT MAP (Request => Request(51), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6), +South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); + +Arbiter_11_7 : Arbiter + +PORT MAP (Request => Request(43), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7), +South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); + +Arbiter_11_8 : Arbiter + +PORT MAP (Request => Request(35), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8), +South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); + +Arbiter_11_9 : Arbiter + +PORT MAP (Request => Request(27), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9), +South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); + +-------------------------- Diagonale n° 12 + + +Arbiter_12_1 : Arbiter + +PORT MAP (Request => Request(19), North => south_2_north(11)(1), West => east_2_west(11)(9), P => Signal_priority(6), Fifo_full => Fifo_full(1), +South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); + +Arbiter_12_2 : Arbiter + +PORT MAP (Request => Request(11), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), +South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); + +Arbiter_12_3 : Arbiter + +PORT MAP (Request => Request(3), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), +South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); + +Arbiter_12_4 : Arbiter + +PORT MAP (Request => Request(76), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), +South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); + +Arbiter_12_5 : Arbiter + +PORT MAP (Request => Request(68), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5), +South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); + +Arbiter_12_6 : Arbiter + +PORT MAP (Request => Request(60), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6), +South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); + +Arbiter_12_7 : Arbiter + +PORT MAP (Request => Request(52), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7), +South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); + +Arbiter_12_8 : Arbiter + +PORT MAP (Request => Request(44), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8), +South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); + +Arbiter_12_9 : Arbiter + +PORT MAP (Request => Request(36), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9), +South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); + +-------------------------- Diagonale n° 13 + + +Arbiter_13_1 : Arbiter + +PORT MAP (Request => Request(28), North => south_2_north(12)(1), West => east_2_west(12)(9), P => Signal_priority(5), Fifo_full => Fifo_full(1), +South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); + +Arbiter_13_2 : Arbiter + +PORT MAP (Request => Request(20), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), +South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); + +Arbiter_13_3 : Arbiter + +PORT MAP (Request => Request(12), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), +South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); + +Arbiter_13_4 : Arbiter + +PORT MAP (Request => Request(4), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), +South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); + +Arbiter_13_5 : Arbiter + +PORT MAP (Request => Request(77), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5), +South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); + +Arbiter_13_6 : Arbiter + +PORT MAP (Request => Request(69), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6), +South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); + +Arbiter_13_7 : Arbiter + +PORT MAP (Request => Request(61), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7), +South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); + +Arbiter_13_8 : Arbiter + +PORT MAP (Request => Request(53), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8), +South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); + +Arbiter_13_9 : Arbiter + +PORT MAP (Request => Request(45), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9), +South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); + +-------------------------- Diagonale n° 14 + + +Arbiter_14_1 : Arbiter + +PORT MAP (Request => Request(37), North => south_2_north(13)(1), West => east_2_west(13)(9), P => Signal_priority(4), Fifo_full => Fifo_full(1), +South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); + +Arbiter_14_2 : Arbiter + +PORT MAP (Request => Request(29), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), +South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); + +Arbiter_14_3 : Arbiter + +PORT MAP (Request => Request(21), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), +South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); + +Arbiter_14_4 : Arbiter + +PORT MAP (Request => Request(13), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), +South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); + +Arbiter_14_5 : Arbiter + +PORT MAP (Request => Request(5), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5), +South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); + +Arbiter_14_6 : Arbiter + +PORT MAP (Request => Request(78), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6), +South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); + +Arbiter_14_7 : Arbiter + +PORT MAP (Request => Request(70), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7), +South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); + +Arbiter_14_8 : Arbiter + +PORT MAP (Request => Request(62), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8), +South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); + +Arbiter_14_9 : Arbiter + +PORT MAP (Request => Request(54), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9), +South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); + +-------------------------- Diagonale n° 15 + + +Arbiter_15_1 : Arbiter + +PORT MAP (Request => Request(46), North => south_2_north(14)(1), West => east_2_west(14)(9), P => Signal_priority(3), Fifo_full => Fifo_full(1), +South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); + +Arbiter_15_2 : Arbiter + +PORT MAP (Request => Request(38), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), +South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); + +Arbiter_15_3 : Arbiter + +PORT MAP (Request => Request(30), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), +South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); + +Arbiter_15_4 : Arbiter + +PORT MAP (Request => Request(22), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), +South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); + +Arbiter_15_5 : Arbiter + +PORT MAP (Request => Request(14), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5), +South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); + +Arbiter_15_6 : Arbiter + +PORT MAP (Request => Request(6), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6), +South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); + +Arbiter_15_7 : Arbiter + +PORT MAP (Request => Request(79), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7), +South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); + +Arbiter_15_8 : Arbiter + +PORT MAP (Request => Request(71), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8), +South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); + +Arbiter_15_9 : Arbiter + +PORT MAP (Request => Request(63), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9), +South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); + +-------------------------- Diagonale n° 16 + + +Arbiter_16_1 : Arbiter + +PORT MAP (Request => Request(55), North => south_2_north(15)(1), West => east_2_west(15)(9), P => Signal_priority(2), Fifo_full => Fifo_full(1), +South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); + +Arbiter_16_2 : Arbiter + +PORT MAP (Request => Request(47), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), +South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); + +Arbiter_16_3 : Arbiter + +PORT MAP (Request => Request(39), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), +South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); + +Arbiter_16_4 : Arbiter + +PORT MAP (Request => Request(31), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), +South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); + +Arbiter_16_5 : Arbiter + +PORT MAP (Request => Request(23), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5), +South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); + +Arbiter_16_6 : Arbiter + +PORT MAP (Request => Request(15), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6), +South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); + +Arbiter_16_7 : Arbiter + +PORT MAP (Request => Request(7), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7), +South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); + +Arbiter_16_8 : Arbiter + +PORT MAP (Request => Request(80), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8), +South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); + +Arbiter_16_9 : Arbiter + +PORT MAP (Request => Request(72), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9), +South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); + +-------------------------- Diagonale n° 17 + + +Arbiter_17_1 : Arbiter + +PORT MAP (Request => Request(64), North => south_2_north(16)(1), West => east_2_west(16)(9), P => Signal_priority(1), Fifo_full => Fifo_full(1), +South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); + +Arbiter_17_2 : Arbiter + +PORT MAP (Request => Request(56), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), +South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); + +Arbiter_17_3 : Arbiter + +PORT MAP (Request => Request(48), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), +South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); + +Arbiter_17_4 : Arbiter + +PORT MAP (Request => Request(40), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), +South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); + +Arbiter_17_5 : Arbiter + +PORT MAP (Request => Request(32), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5), +South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); + +Arbiter_17_6 : Arbiter + +PORT MAP (Request => Request(24), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6), +South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); + +Arbiter_17_7 : Arbiter + +PORT MAP (Request => Request(16), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7), +South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); + +Arbiter_17_8 : Arbiter + +PORT MAP (Request => Request(8), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8), +South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); + +Arbiter_17_9 : Arbiter + +PORT MAP (Request => Request(81), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9), +South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); + + +--processus permettant de roter la priorité des diagonales à chaque front d'horloge + -- rotation round robin + round_robin : process(clk) + begin + if rising_edge(clk) then + if reset ='1' then + Signal_priority <= "11111111100000000"; + elsif priority_rotation_en = '1' then + case Signal_priority is + when "11111111100000000" => Signal_priority <= "01111111110000000"; + when "01111111110000000" => Signal_priority <= "00111111111000000"; + when "00111111111000000" => Signal_priority <= "00011111111100000"; + when "00011111111100000" => Signal_priority <= "00001111111110000"; + when "00001111111110000" => Signal_priority <= "00000111111111000"; + when "00000111111111000" => Signal_priority <= "00000011111111100"; + when "00000011111111100" => Signal_priority <= "00000001111111110"; + when "00000001111111110" => Signal_priority <= "00000000111111111"; + when "00000000111111111" => Signal_priority <= "11111111100000000"; + when others => Signal_priority <= "11111111100000000"; + end case; + end if; + end if; + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SWITCH_GEN.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SWITCH_GEN.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SWITCH_GEN.vhd (revision 138) @@ -0,0 +1,7364 @@ +---------------------------------------------------------------------------------- +-- Company: ENSET 2011 +-- Engineer: GAMOM NGOUNOU +-- +-- Create Date: 03:40:47 11/19/2011 +-- Design Name: +-- Module Name: SWITCH_GEN - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- fichier principal du switch générique; en fonction du parametre generique le +-- les directive de generation conditionnelle permettent de ne générer et synthétiser uniquement la logique +-- nécessaire à l'implémentation du switch de la dimension voulue +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use work.Coretypes.all ; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity SWITCH_GEN is + --type portio is array(positive range) of std_logic_vector (7 downto 0); + generic(number_of_ports : positive := 8); + port( + -- ports d'entree + Port_in : in typ_portIO(1 to number_of_ports) ; + + + -- port de sortie + Port_out : out typ_portIO(1 to number_of_ports); + + -- signaux de controle + data_in_en : in std_logic_vector(number_of_ports downto 1); + cmd_in_en : in std_logic_vector(number_of_ports downto 1); + data_out_en : in std_logic_vector(number_of_ports downto 1); + fifo_in_full : out std_logic_vector(number_of_ports downto 1); + fifo_in_empty : out std_logic_vector(number_of_ports downto 1); + data_available : out std_logic_vector(number_of_ports downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC); +end SWITCH_GEN; + +architecture Behavioral of SWITCH_GEN is +-- declaration des modules du switch generique +-- le module de gestion des ports d'entrée + +COMPONENT INPUT_PORT_MODULE + generic(number_of_ports : positive := 8; + Port_num: natural); + Port ( data_in : in STD_LOGIC_VECTOR (7 downto 0); + data_in_en : in STD_LOGIC; + cmd_in_en : in STD_LOGIC; + reset : in STD_LOGIC; + clk : in STD_LOGIC; + request : out STD_LOGIC_VECTOR (number_of_ports downto 1); + grant : in STD_LOGIC_VECTOR (number_of_ports downto 1); + fifo_full : out STD_LOGIC; + fifo_empty : out STD_LOGIC; + priority_rotation : out std_logic; + data_out : out STD_LOGIC_VECTOR (7 downto 0); + data_out_pulse : out std_logic); +END COMPONENT; + +-- le module des ports de sortie + +COMPONENT OUTPUT_PORT_MODULE + PORT( + data_in : IN std_logic_vector(7 downto 0); + reset : IN std_logic; + clk : IN std_logic; + wr_en : IN std_logic; + rd_out_en : IN std_logic; + data_out : OUT std_logic_vector(7 downto 0); + fifo_full : OUT std_logic; + data_avalaible : OUT std_logic + ); +END COMPONENT; + +-- le module du crossbar +COMPONENT Crossbar + generic + ( + number_of_crossbar_ports: positive := 4 + ); + Port ( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + Port1_in : in STD_LOGIC_VECTOR (7 downto 0); + Port2_in : in STD_LOGIC_VECTOR (7 downto 0); + Port3_in : in STD_LOGIC_VECTOR (7 downto 0); + Port4_in : in STD_LOGIC_VECTOR (7 downto 0); + Port5_in : in STD_LOGIC_VECTOR (7 downto 0); + Port6_in : in STD_LOGIC_VECTOR (7 downto 0); + Port7_in : in STD_LOGIC_VECTOR (7 downto 0); + Port8_in : in STD_LOGIC_VECTOR (7 downto 0); + Port9_in : in STD_LOGIC_VECTOR (7 downto 0); + Port10_in : in STD_LOGIC_VECTOR (7 downto 0); + Port11_in : in STD_LOGIC_VECTOR (7 downto 0); + Port12_in : in STD_LOGIC_VECTOR (7 downto 0); + Port13_in : in STD_LOGIC_VECTOR (7 downto 0); + Port14_in : in STD_LOGIC_VECTOR (7 downto 0); + Port15_in : in STD_LOGIC_VECTOR (7 downto 0); + Port16_in : in STD_LOGIC_VECTOR (7 downto 0); + + --Port_pulse_in : in std_logic_vector(1 to number_of_ports); + Port1_pulse_in : in std_logic; + Port2_pulse_in : in std_logic; + Port3_pulse_in : in std_logic; + Port4_pulse_in : in std_logic; + Port5_pulse_in : in std_logic; + Port6_pulse_in : in std_logic; + Port7_pulse_in : in std_logic; + Port8_pulse_in : in std_logic; + Port9_pulse_in : in std_logic; + Port10_pulse_in : in std_logic; + Port11_pulse_in : in std_logic; + Port12_pulse_in : in std_logic; + Port13_pulse_in : in std_logic; + Port14_pulse_in : in std_logic; + Port15_pulse_in : in std_logic; + Port16_pulse_in : in std_logic; + + --Port_pulse_out : in std_logic_vector(1 to number_of_ports); + Port1_pulse_out : out std_logic; + Port2_pulse_out : out std_logic; + Port3_pulse_out : out std_logic; + Port4_pulse_out : out std_logic; + Port5_pulse_out : out std_logic; + Port6_pulse_out : out std_logic; + Port7_pulse_out : out std_logic; + Port8_pulse_out : out std_logic; + Port9_pulse_out : out std_logic; + Port10_pulse_out : out std_logic; + Port11_pulse_out : out std_logic; + Port12_pulse_out : out std_logic; + Port13_pulse_out : out std_logic; + Port14_pulse_out : out std_logic; + Port15_pulse_out : out std_logic; + Port16_pulse_out : out std_logic; + + --Port_out : out Typ_PortIO(1 to number_of_crossbar_ports); + Port1_out : out STD_LOGIC_VECTOR (7 downto 0); + Port2_out : out STD_LOGIC_VECTOR (7 downto 0); + Port3_out : out STD_LOGIC_VECTOR (7 downto 0); + Port4_out : out STD_LOGIC_VECTOR (7 downto 0); + Port5_out : out STD_LOGIC_VECTOR (7 downto 0); + Port6_out : out STD_LOGIC_VECTOR (7 downto 0); + Port7_out : out STD_LOGIC_VECTOR (7 downto 0); + Port8_out : out STD_LOGIC_VECTOR (7 downto 0); + Port9_out : out STD_LOGIC_VECTOR (7 downto 0); + Port10_out : out STD_LOGIC_VECTOR (7 downto 0); + Port11_out : out STD_LOGIC_VECTOR (7 downto 0); + Port12_out : out STD_LOGIC_VECTOR (7 downto 0); + Port13_out : out STD_LOGIC_VECTOR (7 downto 0); + Port14_out : out STD_LOGIC_VECTOR (7 downto 0); + Port15_out : out STD_LOGIC_VECTOR (7 downto 0); + Port16_out : out STD_LOGIC_VECTOR (7 downto 0); + + Ctrl : in STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1) + ); + END COMPONENT; + +-- déclaration du scheduler +COMPONENT Scheduler + generic(number_of_ports : positive := 4); + Port ( Request : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1); + Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (number_of_ports downto 1); + port_grant : out STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1)); +END COMPONENT; + +--declaration des signaux de connection entre les modules du switch + +Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1); +Signal grant_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1); +Signal priority_rotation_signal : STD_LOGIC_VECTOR(number_of_ports downto 1); +signal fifo_out_full_signal : std_logic_vector(number_of_ports downto 1); + +signal crossbar_in_port : Typ_PortIO(1 to number_of_ports); + + + +signal crossbar_out_port : Typ_PortIO(1 to number_of_ports); + + +signal crossbar_in_pulse : std_logic_vector(number_of_ports downto 1); + + +signal crossbar_out_pulse : std_logic_vector(number_of_ports downto 1); + + + +begin +-- intstanciation et connexion des modules du switch en fonction du nombre de ports +-- le circuit genere depend du parametre generique nombre de ports +-- switch 2 ports +switch2x2 : if number_of_ports = 2 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>2,Port_num=>1) +PORT MAP( + data_in => Port_in(1), + data_in_en => data_in_en(1), + cmd_in_en => cmd_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port(1), + data_out_pulse =>crossbar_in_pulse(1), + request(1) =>request_signal(1), + request(2) =>request_signal(2) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>2,Port_num=>2) +PORT MAP( + data_in => Port_in(2), + data_in_en => data_in_en(2), + cmd_in_en => cmd_in_en(2), + reset => reset, + clk =>clk, + grant(1) => grant_signal(3), + grant(2) => grant_signal(4), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port(2), + data_out_pulse =>crossbar_in_pulse(2), + request(1) =>request_signal(3), + request(2) =>request_signal(4) +); + +end generate switch2x2; + + +-- switch 3 ports +switch3x3 : if number_of_ports = 3 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>3,Port_num=>1) +PORT MAP( + data_in => Port_in(1), + data_in_en => data_in_en(1), + cmd_in_en => cmd_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port(1), + data_out_pulse =>crossbar_in_pulse(1), + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>3,Port_num=>2) +PORT MAP( + data_in => Port_in(2), + data_in_en => data_in_en(2), + cmd_in_en => cmd_in_en(2), + reset => reset, + clk =>clk, + grant(4) => grant_signal(4), + grant(5) => grant_signal(5), + grant(6) => grant_signal(6), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port(2), + data_out_pulse =>crossbar_in_pulse(2), + request(4) =>request_signal(4), + request(5) =>request_signal(5), + request(6) =>request_signal(6) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>3,Port_num=>3) +PORT MAP( + data_in => Port_in(3), + data_in_en => data_in_en(3), + cmd_in_en => cmd_in_en(3), + reset => reset, + clk =>clk, + grant(7) => grant_signal(7), + grant(8) => grant_signal(8), + grant(9) => grant_signal(9), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port(3), + data_out_pulse =>crossbar_in_pulse(3), + request(7) =>request_signal(7), + request(8) =>request_signal(8), + request(9) =>request_signal(9) +); + +end generate switch3x3; + + +-- switch 4 à 7 ports +switch4x4_7x7 : if number_of_ports >= 4 and number_of_ports <=7 generate + +switch_4x4_7x7:for i in 1 to number_of_ports generate + +constant j: natural:=number_of_ports*(i-1); +begin +--j=number_of_ports*(i-1); +PORTx4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>number_of_ports,Port_num=>i) +PORT MAP( + data_in => Port_in(i), + data_in_en => data_in_en(i), + cmd_in_en => cmd_in_en(i), + reset => reset, + clk =>clk, + grant =>grant_signal(j+NUMBER_OF_PORTS downto j+1), + + fifo_full =>fifo_in_full(i), + priority_rotation => priority_rotation_signal(i), + fifo_empty => fifo_in_empty(i), + data_out =>crossbar_in_port(i), + data_out_pulse =>crossbar_in_pulse(i), + request =>request_signal(j+NUMBER_OF_PORTS downto j+1) + +); +end generate switch_4x4_7x7; +end generate switch4x4_7x7; + + +---- switch 5 ports +--switch5x5 : if number_of_ports = 5 generate +-- +--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>5) +--PORT MAP( +-- data_in => Port_in(1), +-- data_in_en => data_in_en(1), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(1), +-- grant(2) => grant_signal(2), +-- grant(3) => grant_signal(3), +-- grant(4) => grant_signal(4), +-- grant(5) => grant_signal(5), +-- fifo_full =>fifo_in_full(1), +-- priority_rotation => priority_rotation_signal(1), +-- fifo_empty => fifo_in_empty(1), +-- data_out =>crossbar_in_port(1), +-- data_out_pulse =>crossbar_in_pulse(1), +-- request(1) =>request_signal(1), +-- request(2) =>request_signal(2), +-- request(3) =>request_signal(3), +-- request(4) =>request_signal(4), +-- request(5) =>request_signal(5) +--); +-- +--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>5) +--PORT MAP( +-- data_in => Port_in(2), +-- data_in_en => data_in_en(2), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(6), +-- grant(2) => grant_signal(7), +-- grant(3) => grant_signal(8), +-- grant(4) => grant_signal(9), +-- grant(5) => grant_signal(10), +-- fifo_full =>fifo_in_full(2), +-- priority_rotation => priority_rotation_signal(2), +-- fifo_empty => fifo_in_empty(2), +-- data_out =>crossbar_in_port(2), +-- data_out_pulse =>crossbar_in_pulse(2), +-- request(6) =>request_signal(6), +-- request(7) =>request_signal(7), +-- request(8) =>request_signal(8), +-- request(9) =>request_signal(9), +-- request(10) =>request_signal(10) +--); +-- +--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>5) +--PORT MAP( +-- data_in => Port_in(3), +-- data_in_en => data_in_en(3), +-- reset => reset, +-- clk =>clk, +-- grant(11) => grant_signal(11), +-- grant(12) => grant_signal(12), +-- grant(13) => grant_signal(13), +-- grant(14) => grant_signal(14), +-- grant(15) => grant_signal(15), +-- fifo_full =>fifo_in_full(3), +-- priority_rotation => priority_rotation_signal(3), +-- fifo_empty => fifo_in_empty(3), +-- data_out =>crossbar_in_port(3), +-- data_out_pulse =>crossbar_in_pulse(3), +-- request(11) =>request_signal(11), +-- request(12) =>request_signal(12), +-- request(13) =>request_signal(13), +-- request(14) =>request_signal(14), +-- request(15) =>request_signal(15) +--); +-- +--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>5) +--PORT MAP( +-- data_in => Port_in(4), +-- data_in_en => data_in_en(4), +-- reset => reset, +-- clk =>clk, +-- grant(16) => grant_signal(16), +-- grant(17) => grant_signal(17), +-- grant(18) => grant_signal(18), +-- grant(19) => grant_signal(19), +-- grant(20) => grant_signal(20), +-- fifo_full =>fifo_in_full(4), +-- priority_rotation => priority_rotation_signal(4), +-- fifo_empty => fifo_in_empty(4), +-- data_out =>crossbar_in_port(4), +-- data_out_pulse =>crossbar_in_pulse(4), +-- request(16) =>request_signal(16), +-- request(17) =>request_signal(17), +-- request(18) =>request_signal(18), +-- request(19) =>request_signal(19), +-- request(20) =>request_signal(20) +--); +-- +--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>5) +--PORT MAP( +-- data_in => Port_in(5), +-- data_in_en => data_in_en(5), +-- reset => reset, +-- clk =>clk, +-- grant(21) => grant_signal(21), +-- grant(22) => grant_signal(22), +-- grant(23) => grant_signal(23), +-- grant(24) => grant_signal(24), +-- grant(25) => grant_signal(25), +-- fifo_full =>fifo_in_full(5), +-- priority_rotation => priority_rotation_signal(5), +-- fifo_empty => fifo_in_empty(5), +-- data_out =>crossbar_in_port(5), +-- data_out_pulse =>crossbar_in_pulse(5), +-- request(21) =>request_signal(21), +-- request(22) =>request_signal(22), +-- request(23) =>request_signal(23), +-- request(24) =>request_signal(24), +-- request(25) =>request_signal(25) +--); +-- +--end generate switch5x5; +-- +-- +---- switch 6 ports +--switch6x6 : if number_of_ports = 6 generate +-- +--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>6) +--PORT MAP( +-- data_in => Port_in(1), +-- data_in_en => data_in_en(1), +-- cmd_in_en => cmd_in_en(1), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(1), +-- grant(2) => grant_signal(2), +-- grant(3) => grant_signal(3), +-- grant(4) => grant_signal(4), +-- grant(5) => grant_signal(5), +-- grant(6) => grant_signal(6), +-- fifo_full =>fifo_in_full(1), +-- priority_rotation => priority_rotation_signal(1), +-- fifo_empty => fifo_in_empty(1), +-- data_out =>crossbar_in_port(1), +-- data_out_pulse =>crossbar_in_pulse(1), +-- request(1) =>request_signal(1), +-- request(2) =>request_signal(2), +-- request(3) =>request_signal(3), +-- request(4) =>request_signal(4), +-- request(5) =>request_signal(5), +-- request(6) =>request_signal(6) +--); +-- +--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>6) +--PORT MAP( +-- data_in => Port_in(2), +-- data_in_en => data_in_en(2), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(7), +-- grant(2) => grant_signal(8), +-- grant(3) => grant_signal(9), +-- grant(4) => grant_signal(10), +-- grant(5) => grant_signal(11), +-- grant(6) => grant_signal(12), +-- fifo_full =>fifo_in_full(2), +-- priority_rotation => priority_rotation_signal(2), +-- fifo_empty => fifo_in_empty(2), +-- data_out =>crossbar_in_port(2), +-- data_out_pulse =>crossbar_in_pulse(2), +-- request(1) =>request_signal(7), +-- request(2) =>request_signal(8), +-- request(3) =>request_signal(9), +-- request(4) =>request_signal(10), +-- request(5) =>request_signal(11), +-- request(6) =>request_signal(12) +--); +-- +--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>6) +--PORT MAP( +-- data_in => Port_in(3), +-- data_in_en => data_in_en(3), +-- reset => reset, +-- clk =>clk, +-- grant(13) => grant_signal(13), +-- grant(14) => grant_signal(14), +-- grant(15) => grant_signal(15), +-- grant(16) => grant_signal(16), +-- grant(17) => grant_signal(17), +-- grant(18) => grant_signal(18), +-- fifo_full =>fifo_in_full(3), +-- priority_rotation => priority_rotation_signal(3), +-- fifo_empty => fifo_in_empty(3), +-- data_out =>crossbar_in_port(3), +-- data_out_pulse =>crossbar_in_pulse(3), +-- request(13) =>request_signal(13), +-- request(14) =>request_signal(14), +-- request(15) =>request_signal(15), +-- request(16) =>request_signal(16), +-- request(17) =>request_signal(17), +-- request(18) =>request_signal(18) +--); +-- +--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>6) +--PORT MAP( +-- data_in => Port_in(4), +-- data_in_en => data_in_en(4), +-- cmd_in_en => cmd_in_en(4), +-- reset => reset, +-- clk =>clk, +-- grant(19) => grant_signal(19), +-- grant(20) => grant_signal(20), +-- grant(21) => grant_signal(21), +-- grant(22) => grant_signal(22), +-- grant(23) => grant_signal(23), +-- grant(24) => grant_signal(24), +-- fifo_full =>fifo_in_full(4), +-- priority_rotation => priority_rotation_signal(4), +-- fifo_empty => fifo_in_empty(4), +-- data_out =>crossbar_in_port(4), +-- data_out_pulse =>crossbar_in_pulse(4), +-- request(19) =>request_signal(19), +-- request(20) =>request_signal(20), +-- request(21) =>request_signal(21), +-- request(22) =>request_signal(22), +-- request(23) =>request_signal(23), +-- request(24) =>request_signal(24) +--); +-- +--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>6) +--PORT MAP( +-- data_in => Port_in(5), +-- data_in_en => data_in_en(5), +-- cmd_in_en => cmd_in_en(5), +-- reset => reset, +-- clk =>clk, +-- grant(25) => grant_signal(25), +-- grant(26) => grant_signal(26), +-- grant(27) => grant_signal(27), +-- grant(28) => grant_signal(28), +-- grant(29) => grant_signal(29), +-- grant(30) => grant_signal(30), +-- fifo_full =>fifo_in_full(5), +-- priority_rotation => priority_rotation_signal(5), +-- fifo_empty => fifo_in_empty(5), +-- data_out =>crossbar_in_port(5), +-- data_out_pulse =>crossbar_in_pulse(5), +-- request(25) =>request_signal(25), +-- request(26) =>request_signal(26), +-- request(27) =>request_signal(27), +-- request(28) =>request_signal(28), +-- request(29) =>request_signal(29), +-- request(30) =>request_signal(30) +--); +-- +--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>6) +--PORT MAP( +-- data_in => Port_in(6), +-- data_in_en => data_in_en(6), +-- reset => reset, +-- clk =>clk, +-- grant(31) => grant_signal(31), +-- grant(32) => grant_signal(32), +-- grant(33) => grant_signal(33), +-- grant(34) => grant_signal(34), +-- grant(35) => grant_signal(35), +-- grant(36) => grant_signal(36), +-- fifo_full =>fifo_in_full(6), +-- priority_rotation => priority_rotation_signal(6), +-- fifo_empty => fifo_in_empty(6), +-- data_out =>crossbar_in_port(6), +-- data_out_pulse =>crossbar_in_pulse(6), +-- request(31) =>request_signal(31), +-- request(32) =>request_signal(32), +-- request(33) =>request_signal(33), +-- request(34) =>request_signal(34), +-- request(35) =>request_signal(35), +-- request(36) =>request_signal(36) +--); +-- +--end generate switch6x6; +-- +-- +---- switch 7 ports +--switch7x7 : if number_of_ports = 7 generate +-- +--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>7) +--PORT MAP( +-- data_in => Port_in(1), +-- data_in_en => data_in_en(1), +-- cmd_in_en => cmd_in_en(1), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(1), +-- grant(2) => grant_signal(2), +-- grant(3) => grant_signal(3), +-- grant(4) => grant_signal(4), +-- grant(5) => grant_signal(5), +-- grant(6) => grant_signal(6), +-- grant(7) => grant_signal(7), +-- fifo_full =>fifo_in_full(1), +-- priority_rotation => priority_rotation_signal(1), +-- fifo_empty => fifo_in_empty(1), +-- data_out =>crossbar_in_port(1), +-- data_out_pulse =>crossbar_in_pulse(1), +-- request(1) =>request_signal(1), +-- request(2) =>request_signal(2), +-- request(3) =>request_signal(3), +-- request(4) =>request_signal(4), +-- request(5) =>request_signal(5), +-- request(6) =>request_signal(6), +-- request(7) =>request_signal(7) +--); +-- +--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>7) +--PORT MAP( +-- data_in => Port_in(2), +-- data_in_en => data_in_en(2), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(8), +-- grant(2) => grant_signal(9), +-- grant(3) => grant_signal(10), +-- grant(4) => grant_signal(11), +-- grant(5) => grant_signal(12), +-- grant(6) => grant_signal(13), +-- grant(7) => grant_signal(14), +-- fifo_full =>fifo_in_full(2), +-- priority_rotation => priority_rotation_signal(2), +-- fifo_empty => fifo_in_empty(2), +-- data_out =>crossbar_in_port(2), +-- data_out_pulse =>crossbar_in_pulse(2), +-- request(8) =>request_signal(8), +-- request(9) =>request_signal(9), +-- request(10) =>request_signal(10), +-- request(11) =>request_signal(11), +-- request(12) =>request_signal(12), +-- request(13) =>request_signal(13), +-- request(14) =>request_signal(14) +--); +-- +--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>7) +--PORT MAP( +-- data_in => Port_in(3), +-- data_in_en => data_in_en(3), +-- reset => reset, +-- clk =>clk, +-- grant(15) => grant_signal(15), +-- grant(16) => grant_signal(16), +-- grant(17) => grant_signal(17), +-- grant(18) => grant_signal(18), +-- grant(19) => grant_signal(19), +-- grant(20) => grant_signal(20), +-- grant(21) => grant_signal(21), +-- fifo_full =>fifo_in_full(3), +-- priority_rotation => priority_rotation_signal(3), +-- fifo_empty => fifo_in_empty(3), +-- data_out =>crossbar_in_port(3), +-- data_out_pulse =>crossbar_in_pulse(3), +-- request(15) =>request_signal(15), +-- request(16) =>request_signal(16), +-- request(17) =>request_signal(17), +-- request(18) =>request_signal(18), +-- request(19) =>request_signal(19), +-- request(20) =>request_signal(20), +-- request(21) =>request_signal(21) +--); +-- +--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>7) +--PORT MAP( +-- data_in => Port_in(4), +-- data_in_en => data_in_en(4), +-- reset => reset, +-- clk =>clk, +-- grant(22) => grant_signal(22), +-- grant(23) => grant_signal(23), +-- grant(24) => grant_signal(24), +-- grant(25) => grant_signal(25), +-- grant(26) => grant_signal(26), +-- grant(27) => grant_signal(27), +-- grant(28) => grant_signal(28), +-- fifo_full =>fifo_in_full(4), +-- priority_rotation => priority_rotation_signal(4), +-- fifo_empty => fifo_in_empty(4), +-- data_out =>crossbar_in_port(4), +-- data_out_pulse =>crossbar_in_pulse(4), +-- request(22) =>request_signal(22), +-- request(23) =>request_signal(23), +-- request(24) =>request_signal(24), +-- request(25) =>request_signal(25), +-- request(26) =>request_signal(26), +-- request(27) =>request_signal(27), +-- request(28) =>request_signal(28) +--); +-- +--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>7) +--PORT MAP( +-- data_in => Port_in(5), +-- data_in_en => data_in_en(5), +-- reset => reset, +-- clk =>clk, +-- grant(29) => grant_signal(29), +-- grant(30) => grant_signal(30), +-- grant(31) => grant_signal(31), +-- grant(32) => grant_signal(32), +-- grant(33) => grant_signal(33), +-- grant(34) => grant_signal(34), +-- grant(35) => grant_signal(35), +-- fifo_full =>fifo_in_full(5), +-- priority_rotation => priority_rotation_signal(5), +-- fifo_empty => fifo_in_empty(5), +-- data_out =>crossbar_in_port(5), +-- data_out_pulse =>crossbar_in_pulse(5), +-- request(29) =>request_signal(29), +-- request(30) =>request_signal(30), +-- request(31) =>request_signal(31), +-- request(32) =>request_signal(32), +-- request(33) =>request_signal(33), +-- request(34) =>request_signal(34), +-- request(35) =>request_signal(35) +--); +-- +--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>7) +--PORT MAP( +-- data_in => Port_in(6), +-- data_in_en => data_in_en(6), +-- reset => reset, +-- clk =>clk, +-- grant(36) => grant_signal(36), +-- grant(37) => grant_signal(37), +-- grant(38) => grant_signal(38), +-- grant(39) => grant_signal(39), +-- grant(40) => grant_signal(40), +-- grant(41) => grant_signal(41), +-- grant(42) => grant_signal(42), +-- fifo_full =>fifo_in_full(6), +-- priority_rotation => priority_rotation_signal(6), +-- fifo_empty => fifo_in_empty(6), +-- data_out =>crossbar_in_port(6), +-- data_out_pulse =>crossbar_in_pulse(6), +-- request(36) =>request_signal(36), +-- request(37) =>request_signal(37), +-- request(38) =>request_signal(38), +-- request(39) =>request_signal(39), +-- request(40) =>request_signal(40), +-- request(41) =>request_signal(41), +-- request(42) =>request_signal(42) +--); +-- +--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>7) +--PORT MAP( +-- data_in => Port_in(7), +-- data_in_en => data_in_en(7), +-- reset => reset, +-- clk =>clk, +-- grant(43) => grant_signal(43), +-- grant(44) => grant_signal(44), +-- grant(45) => grant_signal(45), +-- grant(46) => grant_signal(46), +-- grant(47) => grant_signal(47), +-- grant(48) => grant_signal(48), +-- grant(49) => grant_signal(49), +-- fifo_full =>fifo_in_full(7), +-- priority_rotation => priority_rotation_signal(7), +-- fifo_empty => fifo_in_empty(7), +-- data_out =>crossbar_in_port(8), +-- data_out_pulse =>crossbar_in_pulse(7), +-- request(43) =>request_signal(43), +-- request(44) =>request_signal(44), +-- request(45) =>request_signal(45), +-- request(46) =>request_signal(46), +-- request(47) =>request_signal(47), +-- request(48) =>request_signal(48), +-- request(49) =>request_signal(49) +--); +-- +--end generate switch7x7; + + +-- switch 8 ports +switch8x8 : if number_of_ports = 8 generate +switch_8x8:for i in 1 to number_of_ports generate +constant j: natural:=number_of_ports*(i-1); +begin +--j<=number_of_ports*(i-1); +PORTx8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>8,Port_num=>i) +PORT MAP( + data_in => Port_in(i), + data_in_en => data_in_en(i), + cmd_in_en => cmd_in_en(i), + reset => reset, + clk =>clk, + grant =>grant_signal(j+NUMBER_OF_PORTS downto j+1), + fifo_full =>fifo_in_full(i), + priority_rotation => priority_rotation_signal(i), + fifo_empty => fifo_in_empty(i), + data_out =>crossbar_in_port(i), + data_out_pulse =>crossbar_in_pulse(i), + + request =>request_signal(j+NUMBER_OF_PORTS downto j+1) +); +end generate switch_8x8; +end generate switch8x8; + +-- switch 9 ports +switch9x9_to_15 : if (number_of_ports >= 9)and (number_of_ports <= 15) generate + +switch_9x9_to_15:for i in 1 to number_of_ports generate + +constant j: natural:=number_of_ports*(i-1); +begin + +PORTx9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>NUMBER_OF_PORTS,Port_num=>i) +PORT MAP( + data_in => Port_in(i), + data_in_en => data_in_en(i), + cmd_in_en => cmd_in_en(i), + reset => reset, + clk =>clk, + grant => grant_signal(j+NUMBER_OF_PORTS downto j+1), + fifo_full =>fifo_in_full(i), + priority_rotation => priority_rotation_signal(i), + fifo_empty => fifo_in_empty(i), + data_out =>crossbar_in_port(i), + data_out_pulse =>crossbar_in_pulse(i), + + request =>request_signal(j+NUMBER_OF_PORTS downto j+1) +); +end generate switch_9x9_to_15; +end generate switch9x9_to_15; + + + +-- switch 10 ports +--switch10x10 : if number_of_ports = 10 generate +-- +--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>10) +--PORT MAP( +-- data_in => Port_in(1), +-- data_in_en => data_in_en(1), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(1), +-- grant(2) => grant_signal(2), +-- grant(3) => grant_signal(3), +-- grant(4) => grant_signal(4), +-- grant(5) => grant_signal(5), +-- grant(6) => grant_signal(6), +-- grant(7) => grant_signal(7), +-- grant(8) => grant_signal(8), +-- grant(9) => grant_signal(9), +-- grant(10) => grant_signal(10), +-- fifo_full =>fifo_in_full(1), +-- priority_rotation => priority_rotation_signal(1), +-- fifo_empty => fifo_in_empty(1), +-- data_out =>crossbar_in_port(1), +-- data_out_pulse =>crossbar_in_pulse(1), +-- request(1) =>request_signal(1), +-- request(2) =>request_signal(2), +-- request(3) =>request_signal(3), +-- request(4) =>request_signal(4), +-- request(5) =>request_signal(5), +-- request(6) =>request_signal(6), +-- request(7) =>request_signal(7), +-- request(8) =>request_signal(8), +-- request(9) =>request_signal(9), +-- request(10) =>request_signal(10) +--); +-- +--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>10) +--PORT MAP( +-- data_in => Port_in(2), +-- data_in_en => data_in_en(2), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(11), +-- grant(2) => grant_signal(12), +-- grant(3) => grant_signal(13), +-- grant(4) => grant_signal(14), +-- grant(5) => grant_signal(15), +-- grant(6) => grant_signal(16), +-- grant(7) => grant_signal(17), +-- grant(8) => grant_signal(18), +-- grant(9) => grant_signal(19), +-- grant(10) => grant_signal(20), +-- fifo_full =>fifo_in_full(2), +-- priority_rotation => priority_rotation_signal(2), +-- fifo_empty => fifo_in_empty(2), +-- data_out =>crossbar_in_port(2), +-- data_out_pulse =>crossbar_in_pulse(2), +-- request(1) =>request_signal(11), +-- request(2) =>request_signal(12), +-- request(3) =>request_signal(13), +-- request(4) =>request_signal(14), +-- request(5) =>request_signal(15), +-- request(6) =>request_signal(16), +-- request(7) =>request_signal(17), +-- request(8) =>request_signal(18), +-- request(9) =>request_signal(19), +-- request(10) =>request_signal(20) +--); +-- +--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>10) +--PORT MAP( +-- data_in => Port_in(3), +-- data_in_en => data_in_en(3), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(21), +-- grant(2) => grant_signal(22), +-- grant(3) => grant_signal(23), +-- grant(4) => grant_signal(24), +-- grant(5) => grant_signal(25), +-- grant(6) => grant_signal(26), +-- grant(7) => grant_signal(27), +-- grant(8) => grant_signal(28), +-- grant(9) => grant_signal(29), +-- grant(10) => grant_signal(30), +-- fifo_full =>fifo_in_full(3), +-- priority_rotation => priority_rotation_signal(3), +-- fifo_empty => fifo_in_empty(3), +-- data_out =>crossbar_in_port(3), +-- data_out_pulse =>crossbar_in_pulse(3), +-- request(1) =>request_signal(21), +-- request(2) =>request_signal(22), +-- request(3) =>request_signal(23), +-- request(4) =>request_signal(24), +-- request(5) =>request_signal(25), +-- request(6) =>request_signal(26), +-- request(7) =>request_signal(27), +-- request(8) =>request_signal(28), +-- request(9) =>request_signal(29), +-- request(10) =>request_signal(30) +--); +-- +--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>10) +--PORT MAP( +-- data_in => Port_in(4), +-- data_in_en => data_in_en(4), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(31), +-- grant(2) => grant_signal(32), +-- grant(3) => grant_signal(33), +-- grant(4) => grant_signal(34), +-- grant(5) => grant_signal(35), +-- grant(6) => grant_signal(36), +-- grant(7) => grant_signal(37), +-- grant(8) => grant_signal(38), +-- grant(9) => grant_signal(39), +-- grant(10) => grant_signal(40), +-- fifo_full =>fifo_in_full(4), +-- priority_rotation => priority_rotation_signal(4), +-- fifo_empty => fifo_in_empty(4), +-- data_out =>crossbar_in_port(4), +-- data_out_pulse =>crossbar_in_pulse(4), +-- request(1) =>request_signal(31), +-- request(2) =>request_signal(32), +-- request(3) =>request_signal(33), +-- request(4) =>request_signal(34), +-- request(5) =>request_signal(35), +-- request(6) =>request_signal(36), +-- request(7) =>request_signal(37), +-- request(8) =>request_signal(38), +-- request(9) =>request_signal(39), +-- request(10) =>request_signal(40) +--); +-- +--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>10) +--PORT MAP( +-- data_in => Port_in(5), +-- data_in_en => data_in_en(5), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(41), +-- grant(2) => grant_signal(42), +-- grant(3) => grant_signal(43), +-- grant(4) => grant_signal(44), +-- grant(5) => grant_signal(45), +-- grant(6) => grant_signal(46), +-- grant(7) => grant_signal(47), +-- grant(8) => grant_signal(48), +-- grant(9) => grant_signal(49), +-- grant(10) => grant_signal(50), +-- fifo_full =>fifo_in_full(5), +-- priority_rotation => priority_rotation_signal(5), +-- fifo_empty => fifo_in_empty(5), +-- data_out =>crossbar_in_port(5), +-- data_out_pulse =>crossbar_in_pulse(5), +-- request(1) =>request_signal(41), +-- request(2) =>request_signal(42), +-- request(3) =>request_signal(43), +-- request(4) =>request_signal(44), +-- request(5) =>request_signal(45), +-- request(6) =>request_signal(46), +-- request(7) =>request_signal(47), +-- request(8) =>request_signal(48), +-- request(9) =>request_signal(49), +-- request(10) =>request_signal(50) +--); +-- +--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>10) +--PORT MAP( +-- data_in => Port_in(6), +-- data_in_en => data_in_en(6), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(51), +-- grant(2) => grant_signal(52), +-- grant(3) => grant_signal(53), +-- grant(4) => grant_signal(54), +-- grant(5) => grant_signal(55), +-- grant(6) => grant_signal(56), +-- grant(7) => grant_signal(57), +-- grant(8) => grant_signal(58), +-- grant(9) => grant_signal(59), +-- grant(10) => grant_signal(60), +-- fifo_full =>fifo_in_full(6), +-- priority_rotation => priority_rotation_signal(6), +-- fifo_empty => fifo_in_empty(6), +-- data_out =>crossbar_in_port(6), +-- data_out_pulse =>crossbar_in_pulse(6), +-- request(1) =>request_signal(51), +-- request(2) =>request_signal(52), +-- request(3) =>request_signal(53), +-- request(4) =>request_signal(54), +-- request(5) =>request_signal(55), +-- request(6) =>request_signal(56), +-- request(7) =>request_signal(57), +-- request(8) =>request_signal(58), +-- request(9) =>request_signal(59), +-- request(10) =>request_signal(60) +--); +-- +--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>10) +--PORT MAP( +-- data_in => Port_in(7), +-- data_in_en => data_in_en(7), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(61), +-- grant(2) => grant_signal(62), +-- grant(3) => grant_signal(63), +-- grant(4) => grant_signal(64), +-- grant(5) => grant_signal(65), +-- grant(6) => grant_signal(66), +-- grant(7) => grant_signal(67), +-- grant(8) => grant_signal(68), +-- grant(9) => grant_signal(69), +-- grant(10) => grant_signal(70), +-- fifo_full =>fifo_in_full(7), +-- priority_rotation => priority_rotation_signal(7), +-- fifo_empty => fifo_in_empty(7), +-- data_out =>crossbar_in_port(7), +-- data_out_pulse =>crossbar_in_pulse(7), +-- request(1) =>request_signal(61), +-- request(2) =>request_signal(62), +-- request(3) =>request_signal(63), +-- request(4) =>request_signal(64), +-- request(5) =>request_signal(65), +-- request(6) =>request_signal(66), +-- request(7) =>request_signal(67), +-- request(8) =>request_signal(68), +-- request(9) =>request_signal(69), +-- request(10) =>request_signal(70) +--); +-- +--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>10) +--PORT MAP( +-- data_in => Port_in(8), +-- data_in_en => data_in_en(8), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(71), +-- grant(2) => grant_signal(72), +-- grant(3) => grant_signal(73), +-- grant(4) => grant_signal(74), +-- grant(5) => grant_signal(75), +-- grant(6) => grant_signal(76), +-- grant(7) => grant_signal(77), +-- grant(8) => grant_signal(78), +-- grant(9) => grant_signal(79), +-- grant(10) => grant_signal(80), +-- fifo_full =>fifo_in_full(8), +-- priority_rotation => priority_rotation_signal(8), +-- fifo_empty => fifo_in_empty(8), +-- data_out =>crossbar_in_port(8), +-- data_out_pulse =>crossbar_in_pulse(8), +-- request(1) =>request_signal(71), +-- request(2) =>request_signal(72), +-- request(3) =>request_signal(73), +-- request(4) =>request_signal(74), +-- request(5) =>request_signal(75), +-- request(6) =>request_signal(76), +-- request(7) =>request_signal(77), +-- request(8) =>request_signal(78), +-- request(9) =>request_signal(79), +-- request(10) =>request_signal(80) +--); +-- +--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>10) +--PORT MAP( +-- data_in => Port_in(9), +-- data_in_en => data_in_en(9), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(81), +-- grant(2) => grant_signal(82), +-- grant(3) => grant_signal(83), +-- grant(4) => grant_signal(84), +-- grant(5) => grant_signal(85), +-- grant(6) => grant_signal(86), +-- grant(7) => grant_signal(87), +-- grant(8) => grant_signal(88), +-- grant(9) => grant_signal(89), +-- grant(10) => grant_signal(90), +-- fifo_full =>fifo_in_full(9), +-- priority_rotation => priority_rotation_signal(9), +-- fifo_empty => fifo_in_empty(9), +-- data_out =>crossbar_in_port(9), +-- data_out_pulse =>crossbar_in_pulse(9), +-- request(1) =>request_signal(81), +-- request(2) =>request_signal(82), +-- request(3) =>request_signal(83), +-- request(4) =>request_signal(84), +-- request(5) =>request_signal(85), +-- request(6) =>request_signal(86), +-- request(7) =>request_signal(87), +-- request(8) =>request_signal(88), +-- request(9) =>request_signal(89), +-- request(10) =>request_signal(90) +--); +-- +--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>10) +--PORT MAP( +-- data_in => Port_in(10), +-- data_in_en => data_in_en(10), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(91), +-- grant(2) => grant_signal(92), +-- grant(3) => grant_signal(93), +-- grant(4) => grant_signal(94), +-- grant(5) => grant_signal(95), +-- grant(6) => grant_signal(96), +-- grant(7) => grant_signal(97), +-- grant(8) => grant_signal(98), +-- grant(9) => grant_signal(99), +-- grant(10) => grant_signal(100), +-- fifo_full =>fifo_in_full(10), +-- priority_rotation => priority_rotation_signal(10), +-- fifo_empty => fifo_in_empty(10), +-- data_out =>crossbar_in_port(10), +-- data_out_pulse =>crossbar_in_pulse(10), +-- request(1) =>request_signal(91), +-- request(2) =>request_signal(92), +-- request(3) =>request_signal(93), +-- request(4) =>request_signal(94), +-- request(5) =>request_signal(95), +-- request(6) =>request_signal(96), +-- request(7) =>request_signal(97), +-- request(8) =>request_signal(98), +-- request(9) =>request_signal(99), +-- request(10) =>request_signal(100) +--); +-- +--end generate switch10x10; +-- +-- +---- switch 11 ports +--switch11x11 : if number_of_ports = 11 generate +-- +--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>11) +--PORT MAP( +-- data_in => Port_in(1), +-- data_in_en => data_in_en(1), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(1), +-- grant(2) => grant_signal(2), +-- grant(3) => grant_signal(3), +-- grant(4) => grant_signal(4), +-- grant(5) => grant_signal(5), +-- grant(6) => grant_signal(6), +-- grant(7) => grant_signal(7), +-- grant(8) => grant_signal(8), +-- grant(9) => grant_signal(9), +-- grant(10) => grant_signal(10), +-- grant(11) => grant_signal(11), +-- fifo_full =>fifo_in_full(1), +-- priority_rotation => priority_rotation_signal(1), +-- fifo_empty => fifo_in_empty(1), +-- data_out =>crossbar_in_port(1), +-- data_out_pulse =>crossbar_in_pulse(1), +-- request(1) =>request_signal(1), +-- request(2) =>request_signal(2), +-- request(3) =>request_signal(3), +-- request(4) =>request_signal(4), +-- request(5) =>request_signal(5), +-- request(6) =>request_signal(6), +-- request(7) =>request_signal(7), +-- request(8) =>request_signal(8), +-- request(9) =>request_signal(9), +-- request(10) =>request_signal(10), +-- request(11) =>request_signal(11) +--); +-- +--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>11) +--PORT MAP( +-- data_in => Port_in(2), +-- data_in_en => data_in_en(2), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(12), +-- grant(02) => grant_signal(13), +-- grant(03) => grant_signal(14), +-- grant(04) => grant_signal(15), +-- grant(05) => grant_signal(16), +-- grant(06) => grant_signal(17), +-- grant(07) => grant_signal(18), +-- grant(08) => grant_signal(19), +-- grant(09) => grant_signal(20), +-- grant(10) => grant_signal(21), +-- grant(11) => grant_signal(22), +-- fifo_full =>fifo_in_full(2), +-- priority_rotation => priority_rotation_signal(2), +-- fifo_empty => fifo_in_empty(2), +-- data_out =>crossbar_in_port(2), +-- data_out_pulse =>crossbar_in_pulse(2), +-- request(01) =>request_signal(12), +-- request(02) =>request_signal(13), +-- request(03) =>request_signal(14), +-- request(04) =>request_signal(15), +-- request(05) =>request_signal(16), +-- request(06) =>request_signal(17), +-- request(07) =>request_signal(18), +-- request(08) =>request_signal(19), +-- request(09) =>request_signal(20), +-- request(10) =>request_signal(21), +-- request(11) =>request_signal(22) +--); +-- +--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>11) +--PORT MAP( +-- data_in => Port_in(3), +-- data_in_en => data_in_en(3), +-- reset => reset, +-- clk =>clk, +-- grant(01) => grant_signal(23), +-- grant(02) => grant_signal(24), +-- grant(03) => grant_signal(25), +-- grant(04) => grant_signal(26), +-- grant(05) => grant_signal(27), +-- grant(06) => grant_signal(28), +-- grant(07) => grant_signal(29), +-- grant(08) => grant_signal(30), +-- grant(09) => grant_signal(31), +-- grant(10) => grant_signal(32), +-- grant(11) => grant_signal(33), +-- fifo_full =>fifo_in_full(3), +-- priority_rotation => priority_rotation_signal(3), +-- fifo_empty => fifo_in_empty(3), +-- data_out =>crossbar_in_port(3), +-- data_out_pulse =>crossbar_in_pulse(3), +-- request(01) =>request_signal(23), +-- request(02) =>request_signal(24), +-- request(03) =>request_signal(25), +-- request(04) =>request_signal(26), +-- request(05) =>request_signal(27), +-- request(06) =>request_signal(28), +-- request(07) =>request_signal(29), +-- request(08) =>request_signal(30), +-- request(09) =>request_signal(31), +-- request(10) =>request_signal(32), +-- request(11) =>request_signal(33) +--); +-- +--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>11) +--PORT MAP( +-- data_in => Port_in(4), +-- data_in_en => data_in_en(4), +-- reset => reset, +-- clk =>clk, +-- grant(01) => grant_signal(34), +-- grant(02) => grant_signal(35), +-- grant(03) => grant_signal(36), +-- grant(04) => grant_signal(37), +-- grant(05) => grant_signal(38), +-- grant(06) => grant_signal(39), +-- grant(07) => grant_signal(40), +-- grant(08) => grant_signal(41), +-- grant(09) => grant_signal(42), +-- grant(10) => grant_signal(43), +-- grant(11) => grant_signal(44), +-- fifo_full =>fifo_in_full(4), +-- priority_rotation => priority_rotation_signal(4), +-- fifo_empty => fifo_in_empty(4), +-- data_out =>crossbar_in_port(4), +-- data_out_pulse =>crossbar_in_pulse(4), +-- request(01) =>request_signal(34), +-- request(02) =>request_signal(35), +-- request(03) =>request_signal(36), +-- request(04) =>request_signal(37), +-- request(05) =>request_signal(38), +-- request(06) =>request_signal(39), +-- request(07) =>request_signal(40), +-- request(08) =>request_signal(41), +-- request(09) =>request_signal(42), +-- request(10) =>request_signal(43), +-- request(11) =>request_signal(44) +--); +-- +--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>11) +--PORT MAP( +-- data_in => Port_in(5), +-- data_in_en => data_in_en(5), +-- reset => reset, +-- clk =>clk, +-- grant(45) => grant_signal(45), +-- grant(46) => grant_signal(46), +-- grant(47) => grant_signal(47), +-- grant(48) => grant_signal(48), +-- grant(49) => grant_signal(49), +-- grant(50) => grant_signal(50), +-- grant(51) => grant_signal(51), +-- grant(52) => grant_signal(52), +-- grant(53) => grant_signal(53), +-- grant(54) => grant_signal(54), +-- grant(55) => grant_signal(55), +-- fifo_full =>fifo_in_full(5), +-- priority_rotation => priority_rotation_signal(5), +-- fifo_empty => fifo_in_empty(5), +-- data_out =>crossbar_in_port(5), +-- data_out_pulse =>crossbar_in_pulse(5), +-- request(45) =>request_signal(45), +-- request(46) =>request_signal(46), +-- request(47) =>request_signal(47), +-- request(48) =>request_signal(48), +-- request(49) =>request_signal(49), +-- request(50) =>request_signal(50), +-- request(51) =>request_signal(51), +-- request(52) =>request_signal(52), +-- request(53) =>request_signal(53), +-- request(54) =>request_signal(54), +-- request(55) =>request_signal(55) +--); +-- +--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>11) +--PORT MAP( +-- data_in => Port_in(6), +-- data_in_en => data_in_en(6), +-- reset => reset, +-- clk =>clk, +-- grant(56) => grant_signal(56), +-- grant(57) => grant_signal(57), +-- grant(58) => grant_signal(58), +-- grant(59) => grant_signal(59), +-- grant(60) => grant_signal(60), +-- grant(61) => grant_signal(61), +-- grant(62) => grant_signal(62), +-- grant(63) => grant_signal(63), +-- grant(64) => grant_signal(64), +-- grant(65) => grant_signal(65), +-- grant(66) => grant_signal(66), +-- fifo_full =>fifo_in_full(6), +-- priority_rotation => priority_rotation_signal(6), +-- fifo_empty => fifo_in_empty(6), +-- data_out =>crossbar_in_port(6), +-- data_out_pulse =>crossbar_in_pulse(6), +-- request(56) =>request_signal(56), +-- request(57) =>request_signal(57), +-- request(58) =>request_signal(58), +-- request(59) =>request_signal(59), +-- request(60) =>request_signal(60), +-- request(61) =>request_signal(61), +-- request(62) =>request_signal(62), +-- request(63) =>request_signal(63), +-- request(64) =>request_signal(64), +-- request(65) =>request_signal(65), +-- request(66) =>request_signal(66) +--); +-- +--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>11) +--PORT MAP( +-- data_in => Port_in(7), +-- data_in_en => data_in_en(7), +-- reset => reset, +-- clk =>clk, +-- grant(67) => grant_signal(67), +-- grant(68) => grant_signal(68), +-- grant(69) => grant_signal(69), +-- grant(70) => grant_signal(70), +-- grant(71) => grant_signal(71), +-- grant(72) => grant_signal(72), +-- grant(73) => grant_signal(73), +-- grant(74) => grant_signal(74), +-- grant(75) => grant_signal(75), +-- grant(76) => grant_signal(76), +-- grant(77) => grant_signal(77), +-- fifo_full =>fifo_in_full(7), +-- priority_rotation => priority_rotation_signal(7), +-- fifo_empty => fifo_in_empty(7), +-- data_out =>crossbar_in_port(8), +-- data_out_pulse =>crossbar_in_pulse(7), +-- request(67) =>request_signal(67), +-- request(68) =>request_signal(68), +-- request(69) =>request_signal(69), +-- request(70) =>request_signal(70), +-- request(71) =>request_signal(71), +-- request(72) =>request_signal(72), +-- request(73) =>request_signal(73), +-- request(74) =>request_signal(74), +-- request(75) =>request_signal(75), +-- request(76) =>request_signal(76), +-- request(77) =>request_signal(77) +--); +-- +--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>11) +--PORT MAP( +-- data_in => Port_in(8), +-- data_in_en => data_in_en(8), +-- reset => reset, +-- clk =>clk, +-- grant(78) => grant_signal(78), +-- grant(79) => grant_signal(79), +-- grant(80) => grant_signal(80), +-- grant(81) => grant_signal(81), +-- grant(82) => grant_signal(82), +-- grant(83) => grant_signal(83), +-- grant(84) => grant_signal(84), +-- grant(85) => grant_signal(85), +-- grant(86) => grant_signal(86), +-- grant(87) => grant_signal(87), +-- grant(88) => grant_signal(88), +-- fifo_full =>fifo_in_full(8), +-- priority_rotation => priority_rotation_signal(8), +-- fifo_empty => fifo_in_empty(8), +-- data_out =>crossbar_in_port(8), +-- data_out_pulse =>crossbar_in_pulse(8), +-- request(78) =>request_signal(78), +-- request(79) =>request_signal(79), +-- request(80) =>request_signal(80), +-- request(81) =>request_signal(81), +-- request(82) =>request_signal(82), +-- request(83) =>request_signal(83), +-- request(84) =>request_signal(84), +-- request(85) =>request_signal(85), +-- request(86) =>request_signal(86), +-- request(87) =>request_signal(87), +-- request(88) =>request_signal(88) +--); +-- +--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>11) +--PORT MAP( +-- data_in => Port_in(9), +-- data_in_en => data_in_en(9), +-- reset => reset, +-- clk =>clk, +-- grant(89) => grant_signal(89), +-- grant(90) => grant_signal(90), +-- grant(91) => grant_signal(91), +-- grant(92) => grant_signal(92), +-- grant(93) => grant_signal(93), +-- grant(94) => grant_signal(94), +-- grant(95) => grant_signal(95), +-- grant(96) => grant_signal(96), +-- grant(97) => grant_signal(97), +-- grant(98) => grant_signal(98), +-- grant(99) => grant_signal(99), +-- fifo_full =>fifo_in_full(9), +-- priority_rotation => priority_rotation_signal(9), +-- fifo_empty => fifo_in_empty(9), +-- data_out =>crossbar_in_port(9), +-- data_out_pulse =>crossbar_in_pulse(9), +-- request(89) =>request_signal(89), +-- request(90) =>request_signal(90), +-- request(91) =>request_signal(91), +-- request(92) =>request_signal(92), +-- request(93) =>request_signal(93), +-- request(94) =>request_signal(94), +-- request(95) =>request_signal(95), +-- request(96) =>request_signal(96), +-- request(97) =>request_signal(97), +-- request(98) =>request_signal(98), +-- request(99) =>request_signal(99) +--); +-- +--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>11) +--PORT MAP( +-- data_in => Port_in(10), +-- data_in_en => data_in_en(10), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(100), +-- grant(2) => grant_signal(101), +-- grant(3) => grant_signal(102), +-- grant(4) => grant_signal(103), +-- grant(5) => grant_signal(104), +-- grant(6) => grant_signal(105), +-- grant(7) => grant_signal(106), +-- grant(8) => grant_signal(107), +-- grant(9) => grant_signal(108), +-- grant(10) => grant_signal(109), +-- grant(11) => grant_signal(110), +-- fifo_full =>fifo_in_full(10), +-- priority_rotation => priority_rotation_signal(10), +-- fifo_empty => fifo_in_empty(10), +-- data_out =>crossbar_in_port(10), +-- data_out_pulse =>crossbar_in_pulse(10), +-- request(1) =>request_signal(100), +-- request(2) =>request_signal(101), +-- request(3) =>request_signal(102), +-- request(4) =>request_signal(103), +-- request(5) =>request_signal(104), +-- request(6) =>request_signal(105), +-- request(7) =>request_signal(106), +-- request(8) =>request_signal(107), +-- request(9) =>request_signal(108), +-- request(10) =>request_signal(109), +-- request(11) =>request_signal(110) +--); +-- +--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>11) +--PORT MAP( +-- data_in => Port_in(11), +-- data_in_en => data_in_en(11), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(111), +-- grant(2) => grant_signal(112), +-- grant(3) => grant_signal(113), +-- grant(4) => grant_signal(114), +-- grant(5) => grant_signal(115), +-- grant(6) => grant_signal(116), +-- grant(7) => grant_signal(117), +-- grant(8) => grant_signal(118), +-- grant(9) => grant_signal(119), +-- grant(10) => grant_signal(120), +-- grant(11) => grant_signal(121), +-- fifo_full =>fifo_in_full(11), +-- priority_rotation => priority_rotation_signal(11), +-- fifo_empty => fifo_in_empty(11), +-- data_out =>crossbar_in_port(11), +-- data_out_pulse =>crossbar_in_pulse(11), +-- request(1) =>request_signal(111), +-- request(2) =>request_signal(112), +-- request(3) =>request_signal(113), +-- request(4) =>request_signal(114), +-- request(5) =>request_signal(115), +-- request(6) =>request_signal(116), +-- request(7) =>request_signal(117), +-- request(8) =>request_signal(118), +-- request(9) =>request_signal(119), +-- request(10) =>request_signal(120), +-- request(11) =>request_signal(121) +--); +-- +--end generate switch11x11; +-- +-- +---- switch 12 ports +--switch12x12 : if number_of_ports = 12 generate +-- +--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>12) +--PORT MAP( +-- data_in => Port_in(1), +-- data_in_en => data_in_en(1), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(1), +-- grant(2) => grant_signal(2), +-- grant(3) => grant_signal(3), +-- grant(4) => grant_signal(4), +-- grant(5) => grant_signal(5), +-- grant(6) => grant_signal(6), +-- grant(7) => grant_signal(7), +-- grant(8) => grant_signal(8), +-- grant(9) => grant_signal(9), +-- grant(10) => grant_signal(10), +-- grant(11) => grant_signal(11), +-- grant(12) => grant_signal(12), +-- fifo_full =>fifo_in_full(1), +-- priority_rotation => priority_rotation_signal(1), +-- fifo_empty => fifo_in_empty(1), +-- data_out =>crossbar_in_port(1), +-- data_out_pulse =>crossbar_in_pulse(1), +-- request(1) =>request_signal(1), +-- request(2) =>request_signal(2), +-- request(3) =>request_signal(3), +-- request(4) =>request_signal(4), +-- request(5) =>request_signal(5), +-- request(6) =>request_signal(6), +-- request(7) =>request_signal(7), +-- request(8) =>request_signal(8), +-- request(9) =>request_signal(9), +-- request(10) =>request_signal(10), +-- request(11) =>request_signal(11), +-- request(12) =>request_signal(12) +--); +-- +--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>12) +--PORT MAP( +-- data_in => Port_in(2), +-- data_in_en => data_in_en(2), +-- reset => reset, +-- clk =>clk, +-- grant(13) => grant_signal(13), +-- grant(14) => grant_signal(14), +-- grant(15) => grant_signal(15), +-- grant(16) => grant_signal(16), +-- grant(17) => grant_signal(17), +-- grant(18) => grant_signal(18), +-- grant(19) => grant_signal(19), +-- grant(20) => grant_signal(20), +-- grant(21) => grant_signal(21), +-- grant(22) => grant_signal(22), +-- grant(23) => grant_signal(23), +-- grant(24) => grant_signal(24), +-- fifo_full =>fifo_in_full(2), +-- priority_rotation => priority_rotation_signal(2), +-- fifo_empty => fifo_in_empty(2), +-- data_out =>crossbar_in_port(2), +-- data_out_pulse =>crossbar_in_pulse(2), +-- request(13) =>request_signal(13), +-- request(14) =>request_signal(14), +-- request(15) =>request_signal(15), +-- request(16) =>request_signal(16), +-- request(17) =>request_signal(17), +-- request(18) =>request_signal(18), +-- request(19) =>request_signal(19), +-- request(20) =>request_signal(20), +-- request(21) =>request_signal(21), +-- request(22) =>request_signal(22), +-- request(23) =>request_signal(23), +-- request(24) =>request_signal(24) +--); +-- +--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>12) +--PORT MAP( +-- data_in => Port_in(3), +-- data_in_en => data_in_en(3), +-- reset => reset, +-- clk =>clk, +-- grant(25) => grant_signal(25), +-- grant(26) => grant_signal(26), +-- grant(27) => grant_signal(27), +-- grant(28) => grant_signal(28), +-- grant(29) => grant_signal(29), +-- grant(30) => grant_signal(30), +-- grant(31) => grant_signal(31), +-- grant(32) => grant_signal(32), +-- grant(33) => grant_signal(33), +-- grant(34) => grant_signal(34), +-- grant(35) => grant_signal(35), +-- grant(36) => grant_signal(36), +-- fifo_full =>fifo_in_full(3), +-- priority_rotation => priority_rotation_signal(3), +-- fifo_empty => fifo_in_empty(3), +-- data_out =>crossbar_in_port(3), +-- data_out_pulse =>crossbar_in_pulse(3), +-- request(25) =>request_signal(25), +-- request(26) =>request_signal(26), +-- request(27) =>request_signal(27), +-- request(28) =>request_signal(28), +-- request(29) =>request_signal(29), +-- request(30) =>request_signal(30), +-- request(31) =>request_signal(31), +-- request(32) =>request_signal(32), +-- request(33) =>request_signal(33), +-- request(34) =>request_signal(34), +-- request(35) =>request_signal(35), +-- request(36) =>request_signal(36) +--); +-- +--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>12) +--PORT MAP( +-- data_in => Port_in(4), +-- data_in_en => data_in_en(4), +-- reset => reset, +-- clk =>clk, +-- grant(37) => grant_signal(37), +-- grant(38) => grant_signal(38), +-- grant(39) => grant_signal(39), +-- grant(40) => grant_signal(40), +-- grant(41) => grant_signal(41), +-- grant(42) => grant_signal(42), +-- grant(43) => grant_signal(43), +-- grant(44) => grant_signal(44), +-- grant(45) => grant_signal(45), +-- grant(46) => grant_signal(46), +-- grant(47) => grant_signal(47), +-- grant(48) => grant_signal(48), +-- fifo_full =>fifo_in_full(4), +-- priority_rotation => priority_rotation_signal(4), +-- fifo_empty => fifo_in_empty(4), +-- data_out =>crossbar_in_port(4), +-- data_out_pulse =>crossbar_in_pulse(4), +-- request(37) =>request_signal(37), +-- request(38) =>request_signal(38), +-- request(39) =>request_signal(39), +-- request(40) =>request_signal(40), +-- request(41) =>request_signal(41), +-- request(42) =>request_signal(42), +-- request(43) =>request_signal(43), +-- request(44) =>request_signal(44), +-- request(45) =>request_signal(45), +-- request(46) =>request_signal(46), +-- request(47) =>request_signal(47), +-- request(48) =>request_signal(48) +--); +-- +--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>12) +--PORT MAP( +-- data_in => Port_in(5), +-- data_in_en => data_in_en(5), +-- reset => reset, +-- clk =>clk, +-- grant(49) => grant_signal(49), +-- grant(50) => grant_signal(50), +-- grant(51) => grant_signal(51), +-- grant(52) => grant_signal(52), +-- grant(53) => grant_signal(53), +-- grant(54) => grant_signal(54), +-- grant(55) => grant_signal(55), +-- grant(56) => grant_signal(56), +-- grant(57) => grant_signal(57), +-- grant(58) => grant_signal(58), +-- grant(59) => grant_signal(59), +-- grant(60) => grant_signal(60), +-- fifo_full =>fifo_in_full(5), +-- priority_rotation => priority_rotation_signal(5), +-- fifo_empty => fifo_in_empty(5), +-- data_out =>crossbar_in_port(5), +-- data_out_pulse =>crossbar_in_pulse(5), +-- request(49) =>request_signal(49), +-- request(50) =>request_signal(50), +-- request(51) =>request_signal(51), +-- request(52) =>request_signal(52), +-- request(53) =>request_signal(53), +-- request(54) =>request_signal(54), +-- request(55) =>request_signal(55), +-- request(56) =>request_signal(56), +-- request(57) =>request_signal(57), +-- request(58) =>request_signal(58), +-- request(59) =>request_signal(59), +-- request(60) =>request_signal(60) +--); +-- +--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>12) +--PORT MAP( +-- data_in => Port_in(6), +-- data_in_en => data_in_en(6), +-- reset => reset, +-- clk =>clk, +-- grant(61) => grant_signal(61), +-- grant(62) => grant_signal(62), +-- grant(63) => grant_signal(63), +-- grant(64) => grant_signal(64), +-- grant(65) => grant_signal(65), +-- grant(66) => grant_signal(66), +-- grant(67) => grant_signal(67), +-- grant(68) => grant_signal(68), +-- grant(69) => grant_signal(69), +-- grant(70) => grant_signal(70), +-- grant(71) => grant_signal(71), +-- grant(72) => grant_signal(72), +-- fifo_full =>fifo_in_full(6), +-- priority_rotation => priority_rotation_signal(6), +-- fifo_empty => fifo_in_empty(6), +-- data_out =>crossbar_in_port(6), +-- data_out_pulse =>crossbar_in_pulse(6), +-- request(61) =>request_signal(61), +-- request(62) =>request_signal(62), +-- request(63) =>request_signal(63), +-- request(64) =>request_signal(64), +-- request(65) =>request_signal(65), +-- request(66) =>request_signal(66), +-- request(67) =>request_signal(67), +-- request(68) =>request_signal(68), +-- request(69) =>request_signal(69), +-- request(70) =>request_signal(70), +-- request(71) =>request_signal(71), +-- request(72) =>request_signal(72) +--); +-- +--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>12) +--PORT MAP( +-- data_in => Port_in(7), +-- data_in_en => data_in_en(7), +-- reset => reset, +-- clk =>clk, +-- grant(73) => grant_signal(73), +-- grant(74) => grant_signal(74), +-- grant(75) => grant_signal(75), +-- grant(76) => grant_signal(76), +-- grant(77) => grant_signal(77), +-- grant(78) => grant_signal(78), +-- grant(79) => grant_signal(79), +-- grant(80) => grant_signal(80), +-- grant(81) => grant_signal(81), +-- grant(82) => grant_signal(82), +-- grant(83) => grant_signal(83), +-- grant(84) => grant_signal(84), +-- fifo_full =>fifo_in_full(7), +-- priority_rotation => priority_rotation_signal(7), +-- fifo_empty => fifo_in_empty(7), +-- data_out =>crossbar_in_port(7), +-- data_out_pulse =>crossbar_in_pulse(7), +-- request(73) =>request_signal(73), +-- request(74) =>request_signal(74), +-- request(75) =>request_signal(75), +-- request(76) =>request_signal(76), +-- request(77) =>request_signal(77), +-- request(78) =>request_signal(78), +-- request(79) =>request_signal(79), +-- request(80) =>request_signal(80), +-- request(81) =>request_signal(81), +-- request(82) =>request_signal(82), +-- request(83) =>request_signal(83), +-- request(84) =>request_signal(84) +--); +-- +--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>12) +--PORT MAP( +-- data_in => Port_in(8), +-- data_in_en => data_in_en(8), +-- reset => reset, +-- clk =>clk, +-- grant(85) => grant_signal(85), +-- grant(86) => grant_signal(86), +-- grant(87) => grant_signal(87), +-- grant(88) => grant_signal(88), +-- grant(89) => grant_signal(89), +-- grant(90) => grant_signal(90), +-- grant(91) => grant_signal(91), +-- grant(92) => grant_signal(92), +-- grant(93) => grant_signal(93), +-- grant(94) => grant_signal(94), +-- grant(95) => grant_signal(95), +-- grant(96) => grant_signal(96), +-- fifo_full =>fifo_in_full(8), +-- priority_rotation => priority_rotation_signal(8), +-- fifo_empty => fifo_in_empty(8), +-- data_out =>crossbar_in_port(8), +-- data_out_pulse =>crossbar_in_pulse(8), +-- request(85) =>request_signal(85), +-- request(86) =>request_signal(86), +-- request(87) =>request_signal(87), +-- request(88) =>request_signal(88), +-- request(89) =>request_signal(89), +-- request(90) =>request_signal(90), +-- request(91) =>request_signal(91), +-- request(92) =>request_signal(92), +-- request(93) =>request_signal(93), +-- request(94) =>request_signal(94), +-- request(95) =>request_signal(95), +-- request(96) =>request_signal(96) +--); +-- +--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>12) +--PORT MAP( +-- data_in => Port_in(9), +-- data_in_en => data_in_en(9), +-- reset => reset, +-- clk =>clk, +-- grant(97) => grant_signal(97), +-- grant(98) => grant_signal(98), +-- grant(99) => grant_signal(99), +-- grant(100) => grant_signal(100), +-- grant(101) => grant_signal(101), +-- grant(102) => grant_signal(102), +-- grant(103) => grant_signal(103), +-- grant(104) => grant_signal(104), +-- grant(105) => grant_signal(105), +-- grant(106) => grant_signal(106), +-- grant(107) => grant_signal(107), +-- grant(108) => grant_signal(108), +-- fifo_full =>fifo_in_full(9), +-- priority_rotation => priority_rotation_signal(9), +-- fifo_empty => fifo_in_empty(9), +-- data_out =>crossbar_in_port(9), +-- data_out_pulse =>crossbar_in_pulse(9), +-- request(97) =>request_signal(97), +-- request(98) =>request_signal(98), +-- request(99) =>request_signal(99), +-- request(100) =>request_signal(100), +-- request(101) =>request_signal(101), +-- request(102) =>request_signal(102), +-- request(103) =>request_signal(103), +-- request(104) =>request_signal(104), +-- request(105) =>request_signal(105), +-- request(106) =>request_signal(106), +-- request(107) =>request_signal(107), +-- request(108) =>request_signal(108) +--); +-- +--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>12) +--PORT MAP( +-- data_in => Port_in(10), +-- data_in_en => data_in_en(10), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(109), +-- grant(2) => grant_signal(110), +-- grant(3) => grant_signal(111), +-- grant(4) => grant_signal(112), +-- grant(5) => grant_signal(113), +-- grant(6) => grant_signal(114), +-- grant(7) => grant_signal(115), +-- grant(8) => grant_signal(116), +-- grant(9) => grant_signal(117), +-- grant(10) => grant_signal(118), +-- grant(11) => grant_signal(119), +-- grant(12) => grant_signal(120), +-- fifo_full =>fifo_in_full(10), +-- priority_rotation => priority_rotation_signal(10), +-- fifo_empty => fifo_in_empty(10), +-- data_out =>crossbar_in_port(10), +-- data_out_pulse =>crossbar_in_pulse(10), +-- request(109) =>request_signal(109), +-- request(110) =>request_signal(110), +-- request(111) =>request_signal(111), +-- request(112) =>request_signal(112), +-- request(113) =>request_signal(113), +-- request(114) =>request_signal(114), +-- request(115) =>request_signal(115), +-- request(116) =>request_signal(116), +-- request(117) =>request_signal(117), +-- request(118) =>request_signal(118), +-- request(119) =>request_signal(119), +-- request(120) =>request_signal(120) +--); +-- +--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>12) +--PORT MAP( +-- data_in => Port_in(11), +-- data_in_en => data_in_en(11), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(121), +-- grant(2) => grant_signal(122), +-- grant(3) => grant_signal(123), +-- grant(4) => grant_signal(124), +-- grant(5) => grant_signal(125), +-- grant(6) => grant_signal(126), +-- grant(7) => grant_signal(127), +-- grant(8) => grant_signal(128), +-- grant(9) => grant_signal(129), +-- grant(10) => grant_signal(130), +-- grant(11) => grant_signal(131), +-- grant(12) => grant_signal(132), +-- fifo_full =>fifo_in_full(11), +-- priority_rotation => priority_rotation_signal(11), +-- fifo_empty => fifo_in_empty(11), +-- data_out =>crossbar_in_port(11), +-- data_out_pulse =>crossbar_in_pulse(11), +-- request(121) =>request_signal(121), +-- request(122) =>request_signal(122), +-- request(123) =>request_signal(123), +-- request(124) =>request_signal(124), +-- request(125) =>request_signal(125), +-- request(126) =>request_signal(126), +-- request(127) =>request_signal(127), +-- request(128) =>request_signal(128), +-- request(129) =>request_signal(129), +-- request(130) =>request_signal(130), +-- request(131) =>request_signal(131), +-- request(132) =>request_signal(132) +--); +-- +--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>12) +--PORT MAP( +-- data_in => Port_in(12), +-- data_in_en => data_in_en(12), +-- reset => reset, +-- clk =>clk, +-- grant(133) => grant_signal(133), +-- grant(134) => grant_signal(134), +-- grant(135) => grant_signal(135), +-- grant(136) => grant_signal(136), +-- grant(137) => grant_signal(137), +-- grant(138) => grant_signal(138), +-- grant(139) => grant_signal(139), +-- grant(140) => grant_signal(140), +-- grant(141) => grant_signal(141), +-- grant(142) => grant_signal(142), +-- grant(143) => grant_signal(143), +-- grant(144) => grant_signal(144), +-- fifo_full =>fifo_in_full(12), +-- priority_rotation => priority_rotation_signal(12), +-- fifo_empty => fifo_in_empty(12), +-- data_out =>crossbar_in_port(12), +-- data_out_pulse =>crossbar_in_pulse(12), +-- request(133) =>request_signal(133), +-- request(134) =>request_signal(134), +-- request(135) =>request_signal(135), +-- request(136) =>request_signal(136), +-- request(137) =>request_signal(137), +-- request(138) =>request_signal(138), +-- request(139) =>request_signal(139), +-- request(140) =>request_signal(140), +-- request(141) =>request_signal(141), +-- request(142) =>request_signal(142), +-- request(143) =>request_signal(143), +-- request(144) =>request_signal(144) +--); +-- +--end generate switch12x12; +-- +-- +---- switch 13 ports +--switch13x13 : if number_of_ports = 13 generate +-- +--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>13) +--PORT MAP( +-- data_in => Port_in(1), +-- data_in_en => data_in_en(1), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(1), +-- grant(2) => grant_signal(2), +-- grant(3) => grant_signal(3), +-- grant(4) => grant_signal(4), +-- grant(5) => grant_signal(5), +-- grant(6) => grant_signal(6), +-- grant(7) => grant_signal(7), +-- grant(8) => grant_signal(8), +-- grant(9) => grant_signal(9), +-- grant(10) => grant_signal(10), +-- grant(11) => grant_signal(11), +-- grant(12) => grant_signal(12), +-- grant(13) => grant_signal(13), +-- fifo_full =>fifo_in_full(1), +-- priority_rotation => priority_rotation_signal(1), +-- fifo_empty => fifo_in_empty(1), +-- data_out =>crossbar_in_port(1), +-- data_out_pulse =>crossbar_in_pulse(1), +-- request(1) =>request_signal(1), +-- request(2) =>request_signal(2), +-- request(3) =>request_signal(3), +-- request(4) =>request_signal(4), +-- request(5) =>request_signal(5), +-- request(6) =>request_signal(6), +-- request(7) =>request_signal(7), +-- request(8) =>request_signal(8), +-- request(9) =>request_signal(9), +-- request(10) =>request_signal(10), +-- request(11) =>request_signal(11), +-- request(12) =>request_signal(12), +-- request(13) =>request_signal(13) +--); +-- +--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>13) +--PORT MAP( +-- data_in => Port_in(2), +-- data_in_en => data_in_en(2), +-- reset => reset, +-- clk =>clk, +-- grant(14) => grant_signal(14), +-- grant(15) => grant_signal(15), +-- grant(16) => grant_signal(16), +-- grant(17) => grant_signal(17), +-- grant(18) => grant_signal(18), +-- grant(19) => grant_signal(19), +-- grant(20) => grant_signal(20), +-- grant(21) => grant_signal(21), +-- grant(22) => grant_signal(22), +-- grant(23) => grant_signal(23), +-- grant(24) => grant_signal(24), +-- grant(25) => grant_signal(25), +-- grant(26) => grant_signal(26), +-- fifo_full =>fifo_in_full(2), +-- priority_rotation => priority_rotation_signal(2), +-- fifo_empty => fifo_in_empty(2), +-- data_out =>crossbar_in_port(2), +-- data_out_pulse =>crossbar_in_pulse(2), +-- request(14) =>request_signal(14), +-- request(15) =>request_signal(15), +-- request(16) =>request_signal(16), +-- request(17) =>request_signal(17), +-- request(18) =>request_signal(18), +-- request(19) =>request_signal(19), +-- request(20) =>request_signal(20), +-- request(21) =>request_signal(21), +-- request(22) =>request_signal(22), +-- request(23) =>request_signal(23), +-- request(24) =>request_signal(24), +-- request(25) =>request_signal(25), +-- request(26) =>request_signal(26) +--); + +--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>13) +--PORT MAP( +-- data_in => Port_in(3), +-- data_in_en => data_in_en(3), +-- reset => reset, +-- clk =>clk, +-- grant(27) => grant_signal(27), +-- grant(28) => grant_signal(28), +-- grant(29) => grant_signal(29), +-- grant(30) => grant_signal(30), +-- grant(31) => grant_signal(31), +-- grant(32) => grant_signal(32), +-- grant(33) => grant_signal(33), +-- grant(34) => grant_signal(34), +-- grant(35) => grant_signal(35), +-- grant(36) => grant_signal(36), +-- grant(37) => grant_signal(37), +-- grant(38) => grant_signal(38), +-- grant(39) => grant_signal(39), +-- fifo_full =>fifo_in_full(3), +-- priority_rotation => priority_rotation_signal(3), +-- fifo_empty => fifo_in_empty(3), +-- data_out =>crossbar_in_port(3), +-- data_out_pulse =>crossbar_in_pulse(3), +-- request(27) =>request_signal(27), +-- request(28) =>request_signal(28), +-- request(29) =>request_signal(29), +-- request(30) =>request_signal(30), +-- request(31) =>request_signal(31), +-- request(32) =>request_signal(32), +-- request(33) =>request_signal(33), +-- request(34) =>request_signal(34), +-- request(35) =>request_signal(35), +-- request(36) =>request_signal(36), +-- request(37) =>request_signal(37), +-- request(38) =>request_signal(38), +-- request(39) =>request_signal(39) +--); +-- +--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>13) +--PORT MAP( +-- data_in => Port_in(4), +-- data_in_en => data_in_en(4), +-- reset => reset, +-- clk =>clk, +-- grant(40) => grant_signal(40), +-- grant(41) => grant_signal(41), +-- grant(42) => grant_signal(42), +-- grant(43) => grant_signal(43), +-- grant(44) => grant_signal(44), +-- grant(45) => grant_signal(45), +-- grant(46) => grant_signal(46), +-- grant(47) => grant_signal(47), +-- grant(48) => grant_signal(48), +-- grant(49) => grant_signal(49), +-- grant(50) => grant_signal(50), +-- grant(51) => grant_signal(51), +-- grant(52) => grant_signal(52), +-- fifo_full =>fifo_in_full(4), +-- priority_rotation => priority_rotation_signal(4), +-- fifo_empty => fifo_in_empty(4), +-- data_out =>crossbar_in_port(4), +-- data_out_pulse =>crossbar_in_pulse(4), +-- request(40) =>request_signal(40), +-- request(41) =>request_signal(41), +-- request(42) =>request_signal(42), +-- request(43) =>request_signal(43), +-- request(44) =>request_signal(44), +-- request(45) =>request_signal(45), +-- request(46) =>request_signal(46), +-- request(47) =>request_signal(47), +-- request(48) =>request_signal(48), +-- request(49) =>request_signal(49), +-- request(50) =>request_signal(50), +-- request(51) =>request_signal(51), +-- request(52) =>request_signal(52) +--); +-- +--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>13) +--PORT MAP( +-- data_in => Port_in(5), +-- data_in_en => data_in_en(5), +-- reset => reset, +-- clk =>clk, +-- grant(53) => grant_signal(53), +-- grant(54) => grant_signal(54), +-- grant(55) => grant_signal(55), +-- grant(56) => grant_signal(56), +-- grant(57) => grant_signal(57), +-- grant(58) => grant_signal(58), +-- grant(59) => grant_signal(59), +-- grant(60) => grant_signal(60), +-- grant(61) => grant_signal(61), +-- grant(62) => grant_signal(62), +-- grant(63) => grant_signal(63), +-- grant(64) => grant_signal(64), +-- grant(65) => grant_signal(65), +-- fifo_full =>fifo_in_full(5), +-- priority_rotation => priority_rotation_signal(5), +-- fifo_empty => fifo_in_empty(5), +-- data_out =>crossbar_in_port(5), +-- data_out_pulse =>crossbar_in_pulse(5), +-- request(53) =>request_signal(53), +-- request(54) =>request_signal(54), +-- request(55) =>request_signal(55), +-- request(56) =>request_signal(56), +-- request(57) =>request_signal(57), +-- request(58) =>request_signal(58), +-- request(59) =>request_signal(59), +-- request(60) =>request_signal(60), +-- request(61) =>request_signal(61), +-- request(62) =>request_signal(62), +-- request(63) =>request_signal(63), +-- request(64) =>request_signal(64), +-- request(65) =>request_signal(65) +--); +-- +--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>13) +--PORT MAP( +-- data_in => Port_in(6), +-- data_in_en => data_in_en(6), +-- reset => reset, +-- clk =>clk, +-- grant(66) => grant_signal(66), +-- grant(67) => grant_signal(67), +-- grant(68) => grant_signal(68), +-- grant(69) => grant_signal(69), +-- grant(70) => grant_signal(70), +-- grant(71) => grant_signal(71), +-- grant(72) => grant_signal(72), +-- grant(73) => grant_signal(73), +-- grant(74) => grant_signal(74), +-- grant(75) => grant_signal(75), +-- grant(76) => grant_signal(76), +-- grant(77) => grant_signal(77), +-- grant(78) => grant_signal(78), +-- fifo_full =>fifo_in_full(6), +-- priority_rotation => priority_rotation_signal(6), +-- fifo_empty => fifo_in_empty(6), +-- data_out =>crossbar_in_port(6), +-- data_out_pulse =>crossbar_in_pulse(6), +-- request(66) =>request_signal(66), +-- request(67) =>request_signal(67), +-- request(68) =>request_signal(68), +-- request(69) =>request_signal(69), +-- request(70) =>request_signal(70), +-- request(71) =>request_signal(71), +-- request(72) =>request_signal(72), +-- request(73) =>request_signal(73), +-- request(74) =>request_signal(74), +-- request(75) =>request_signal(75), +-- request(76) =>request_signal(76), +-- request(77) =>request_signal(77), +-- request(78) =>request_signal(78) +--); +-- +--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>13) +--PORT MAP( +-- data_in => Port_in(7), +-- data_in_en => data_in_en(7), +-- reset => reset, +-- clk =>clk, +-- grant(79) => grant_signal(79), +-- grant(80) => grant_signal(80), +-- grant(81) => grant_signal(81), +-- grant(82) => grant_signal(82), +-- grant(83) => grant_signal(83), +-- grant(84) => grant_signal(84), +-- grant(85) => grant_signal(85), +-- grant(86) => grant_signal(86), +-- grant(87) => grant_signal(87), +-- grant(88) => grant_signal(88), +-- grant(89) => grant_signal(89), +-- grant(90) => grant_signal(90), +-- grant(91) => grant_signal(91), +-- fifo_full =>fifo_in_full(7), +-- priority_rotation => priority_rotation_signal(7), +-- fifo_empty => fifo_in_empty(7), +-- data_out =>crossbar_in_port(7), +-- data_out_pulse =>crossbar_in_pulse(7), +-- request(79) =>request_signal(79), +-- request(80) =>request_signal(80), +-- request(81) =>request_signal(81), +-- request(82) =>request_signal(82), +-- request(83) =>request_signal(83), +-- request(84) =>request_signal(84), +-- request(85) =>request_signal(85), +-- request(86) =>request_signal(86), +-- request(87) =>request_signal(87), +-- request(88) =>request_signal(88), +-- request(89) =>request_signal(89), +-- request(90) =>request_signal(90), +-- request(91) =>request_signal(91) +--); +-- +--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>13) +--PORT MAP( +-- data_in => Port_in(8), +-- data_in_en => data_in_en(8), +-- reset => reset, +-- clk =>clk, +-- grant(92) => grant_signal(92), +-- grant(93) => grant_signal(93), +-- grant(94) => grant_signal(94), +-- grant(95) => grant_signal(95), +-- grant(96) => grant_signal(96), +-- grant(97) => grant_signal(97), +-- grant(98) => grant_signal(98), +-- grant(99) => grant_signal(99), +-- grant(100) => grant_signal(100), +-- grant(101) => grant_signal(101), +-- grant(102) => grant_signal(102), +-- grant(103) => grant_signal(103), +-- grant(104) => grant_signal(104), +-- fifo_full =>fifo_in_full(8), +-- priority_rotation => priority_rotation_signal(8), +-- fifo_empty => fifo_in_empty(8), +-- data_out =>crossbar_in_port(8), +-- data_out_pulse =>crossbar_in_pulse(8), +-- request(92) =>request_signal(92), +-- request(93) =>request_signal(93), +-- request(94) =>request_signal(94), +-- request(95) =>request_signal(95), +-- request(96) =>request_signal(96), +-- request(97) =>request_signal(97), +-- request(98) =>request_signal(98), +-- request(99) =>request_signal(99), +-- request(100) =>request_signal(100), +-- request(101) =>request_signal(101), +-- request(102) =>request_signal(102), +-- request(103) =>request_signal(103), +-- request(104) =>request_signal(104) +--); +-- +--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>13) +--PORT MAP( +-- data_in => Port_in(9), +-- data_in_en => data_in_en(9), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(105), +-- grant(2) => grant_signal(106), +-- grant(3) => grant_signal(107), +-- grant(4) => grant_signal(108), +-- grant(5) => grant_signal(109), +-- grant(6) => grant_signal(110), +-- grant(7) => grant_signal(111), +-- grant(8) => grant_signal(112), +-- grant(9) => grant_signal(113), +-- grant(10) => grant_signal(114), +-- grant(11) => grant_signal(115), +-- grant(12) => grant_signal(116), +-- grant(13) => grant_signal(117), +-- fifo_full =>fifo_in_full(9), +-- priority_rotation => priority_rotation_signal(9), +-- fifo_empty => fifo_in_empty(9), +-- data_out =>crossbar_in_port(9), +-- data_out_pulse =>crossbar_in_pulse(9), +-- request(105) =>request_signal(105), +-- request(106) =>request_signal(106), +-- request(107) =>request_signal(107), +-- request(108) =>request_signal(108), +-- request(109) =>request_signal(109), +-- request(110) =>request_signal(110), +-- request(111) =>request_signal(111), +-- request(112) =>request_signal(112), +-- request(113) =>request_signal(113), +-- request(114) =>request_signal(114), +-- request(115) =>request_signal(115), +-- request(116) =>request_signal(116), +-- request(117) =>request_signal(117) +--); +-- +--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>13) +--PORT MAP( +-- data_in => Port_in(10), +-- data_in_en => data_in_en(10), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(118), +-- grant(2) => grant_signal(119), +-- grant(3) => grant_signal(120), +-- grant(4) => grant_signal(121), +-- grant(5) => grant_signal(122), +-- grant(6) => grant_signal(123), +-- grant(7) => grant_signal(124), +-- grant(8) => grant_signal(125), +-- grant(9) => grant_signal(126), +-- grant(10) => grant_signal(127), +-- grant(11) => grant_signal(128), +-- grant(12) => grant_signal(129), +-- grant(13) => grant_signal(130), +-- fifo_full =>fifo_in_full(10), +-- priority_rotation => priority_rotation_signal(10), +-- fifo_empty => fifo_in_empty(10), +-- data_out =>crossbar_in_port(10), +-- data_out_pulse =>crossbar_in_pulse(10), +-- request(1) =>request_signal(118), +-- request(2) =>request_signal(119), +-- request(3) =>request_signal(120), +-- request(4) =>request_signal(121), +-- request(5) =>request_signal(122), +-- request(6) =>request_signal(123), +-- request(7) =>request_signal(124), +-- request(8) =>request_signal(125), +-- request(9) =>request_signal(126), +-- request(10) =>request_signal(127), +-- request(11) =>request_signal(128), +-- request(12) =>request_signal(129), +-- request(13) =>request_signal(130) +--); +-- +--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>13) +--PORT MAP( +-- data_in => Port_in(11), +-- data_in_en => data_in_en(11), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(131), +-- grant(2) => grant_signal(132), +-- grant(3) => grant_signal(133), +-- grant(4) => grant_signal(134), +-- grant(5) => grant_signal(135), +-- grant(6) => grant_signal(136), +-- grant(7) => grant_signal(137), +-- grant(8) => grant_signal(138), +-- grant(9) => grant_signal(139), +-- grant(10) => grant_signal(140), +-- grant(11) => grant_signal(141), +-- grant(12) => grant_signal(142), +-- grant(13) => grant_signal(143), +-- fifo_full =>fifo_in_full(11), +-- priority_rotation => priority_rotation_signal(11), +-- fifo_empty => fifo_in_empty(11), +-- data_out =>crossbar_in_port(11), +-- data_out_pulse =>crossbar_in_pulse(11), +-- request(1) =>request_signal(131), +-- request(2) =>request_signal(132), +-- request(3) =>request_signal(133), +-- request(4) =>request_signal(134), +-- request(5) =>request_signal(135), +-- request(6) =>request_signal(136), +-- request(7) =>request_signal(137), +-- request(8) =>request_signal(138), +-- request(9) =>request_signal(139), +-- request(10) =>request_signal(140), +-- request(11) =>request_signal(141), +-- request(12) =>request_signal(142), +-- request(13) =>request_signal(143) +--); +-- +--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>13) +--PORT MAP( +-- data_in => Port_in(12), +-- data_in_en => data_in_en(12), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(144), +-- grant(2) => grant_signal(145), +-- grant(3) => grant_signal(146), +-- grant(4) => grant_signal(147), +-- grant(5) => grant_signal(148), +-- grant(6) => grant_signal(149), +-- grant(7) => grant_signal(150), +-- grant(8) => grant_signal(151), +-- grant(9) => grant_signal(152), +-- grant(10) => grant_signal(153), +-- grant(11) => grant_signal(154), +-- grant(12) => grant_signal(155), +-- grant(13) => grant_signal(156), +-- fifo_full =>fifo_in_full(12), +-- priority_rotation => priority_rotation_signal(12), +-- fifo_empty => fifo_in_empty(12), +-- data_out =>crossbar_in_port(12), +-- data_out_pulse =>crossbar_in_pulse(12), +-- request(1) =>request_signal(144), +-- request(2) =>request_signal(145), +-- request(3) =>request_signal(146), +-- request(4) =>request_signal(147), +-- request(5) =>request_signal(148), +-- request(6) =>request_signal(149), +-- request(7) =>request_signal(150), +-- request(8) =>request_signal(151), +-- request(9) =>request_signal(152), +-- request(10) =>request_signal(153), +-- request(11) =>request_signal(154), +-- request(12) =>request_signal(155), +-- request(13) =>request_signal(156) +--); +-- +--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>13) +--PORT MAP( +-- data_in => Port_in(13), +-- data_in_en => data_in_en(13), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(157), +-- grant(2) => grant_signal(158), +-- grant(3) => grant_signal(159), +-- grant(4) => grant_signal(160), +-- grant(5) => grant_signal(161), +-- grant(6) => grant_signal(162), +-- grant(7) => grant_signal(163), +-- grant(8) => grant_signal(164), +-- grant(9) => grant_signal(165), +-- grant(10) => grant_signal(166), +-- grant(11) => grant_signal(167), +-- grant(12) => grant_signal(168), +-- grant(13) => grant_signal(169), +-- fifo_full =>fifo_in_full(13), +-- priority_rotation => priority_rotation_signal(13), +-- fifo_empty => fifo_in_empty(13), +-- data_out =>crossbar_in_port(13), +-- data_out_pulse =>crossbar_in_pulse(13), +-- request(1) =>request_signal(157), +-- request(2) =>request_signal(158), +-- request(3) =>request_signal(159), +-- request(4) =>request_signal(160), +-- request(5) =>request_signal(161), +-- request(6) =>request_signal(162), +-- request(7) =>request_signal(163), +-- request(8) =>request_signal(164), +-- request(9) =>request_signal(165), +-- request(10) =>request_signal(166), +-- request(11) =>request_signal(167), +-- request(12) =>request_signal(168), +-- request(13) =>request_signal(169) +--); +-- +--end generate switch13x13; +-- +-- +---- switch 14 ports +--switch14x14 : if number_of_ports = 14 generate +-- +--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>14) +--PORT MAP( +-- data_in => Port_in(1), +-- data_in_en => data_in_en(1), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(1), +-- grant(2) => grant_signal(2), +-- grant(3) => grant_signal(3), +-- grant(4) => grant_signal(4), +-- grant(5) => grant_signal(5), +-- grant(6) => grant_signal(6), +-- grant(7) => grant_signal(7), +-- grant(8) => grant_signal(8), +-- grant(9) => grant_signal(9), +-- grant(10) => grant_signal(10), +-- grant(11) => grant_signal(11), +-- grant(12) => grant_signal(12), +-- grant(13) => grant_signal(13), +-- grant(14) => grant_signal(14), +-- fifo_full =>fifo_in_full(1), +-- priority_rotation => priority_rotation_signal(1), +-- fifo_empty => fifo_in_empty(1), +-- data_out =>crossbar_in_port(1), +-- data_out_pulse =>crossbar_in_pulse(1), +-- request(1) =>request_signal(1), +-- request(2) =>request_signal(2), +-- request(3) =>request_signal(3), +-- request(4) =>request_signal(4), +-- request(5) =>request_signal(5), +-- request(6) =>request_signal(6), +-- request(7) =>request_signal(7), +-- request(8) =>request_signal(8), +-- request(9) =>request_signal(9), +-- request(10) =>request_signal(10), +-- request(11) =>request_signal(11), +-- request(12) =>request_signal(12), +-- request(13) =>request_signal(13), +-- request(14) =>request_signal(14) +--); +-- +--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>14) +--PORT MAP( +-- data_in => Port_in(2), +-- data_in_en => data_in_en(2), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(15), +-- grant(2) => grant_signal(16), +-- grant(3) => grant_signal(17), +-- grant(4) => grant_signal(18), +-- grant(5) => grant_signal(19), +-- grant(6) => grant_signal(20), +-- grant(7) => grant_signal(21), +-- grant(8) => grant_signal(22), +-- grant(9) => grant_signal(23), +-- grant(10) => grant_signal(24), +-- grant(11) => grant_signal(25), +-- grant(12) => grant_signal(26), +-- grant(13) => grant_signal(27), +-- grant(14) => grant_signal(28), +-- fifo_full =>fifo_in_full(2), +-- priority_rotation => priority_rotation_signal(2), +-- fifo_empty => fifo_in_empty(2), +-- data_out =>crossbar_in_port(2), +-- data_out_pulse =>crossbar_in_pulse(2), +-- request(1) =>request_signal(15), +-- request(2) =>request_signal(16), +-- request(3) =>request_signal(17), +-- request(4) =>request_signal(18), +-- request(5) =>request_signal(19), +-- request(6) =>request_signal(20), +-- request(7) =>request_signal(21), +-- request(8) =>request_signal(22), +-- request(9) =>request_signal(23), +-- request(10) =>request_signal(24), +-- request(11) =>request_signal(25), +-- request(12) =>request_signal(26), +-- request(13) =>request_signal(27), +-- request(14) =>request_signal(28) +--); +-- +--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>14) +--PORT MAP( +-- data_in => Port_in(3), +-- data_in_en => data_in_en(3), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(29), +-- grant(2) => grant_signal(30), +-- grant(3) => grant_signal(31), +-- grant(4) => grant_signal(32), +-- grant(5) => grant_signal(33), +-- grant(6) => grant_signal(34), +-- grant(7) => grant_signal(35), +-- grant(8) => grant_signal(36), +-- grant(9) => grant_signal(37), +-- grant(10)=> grant_signal(38), +-- grant(11) => grant_signal(39), +-- grant(12) => grant_signal(40), +-- grant(13) => grant_signal(41), +-- grant(14) => grant_signal(42), +-- fifo_full =>fifo_in_full(3), +-- priority_rotation => priority_rotation_signal(3), +-- fifo_empty => fifo_in_empty(3), +-- data_out =>crossbar_in_port(3), +-- data_out_pulse =>crossbar_in_pulse(3), +-- request(01) =>request_signal(29), +-- request(02) =>request_signal(30), +-- request(03) =>request_signal(31), +-- request(04) =>request_signal(32), +-- request(05) =>request_signal(33), +-- request(06) =>request_signal(34), +-- request(07) =>request_signal(35), +-- request(08) =>request_signal(36), +-- request(09) =>request_signal(37), +-- request(10) =>request_signal(38), +-- request(11) =>request_signal(39), +-- request(12) =>request_signal(40), +-- request(13) =>request_signal(41), +-- request(14) =>request_signal(42) +--); +-- +--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>14) +--PORT MAP( +-- data_in => Port_in(4), +-- data_in_en => data_in_en(4), +-- reset => reset, +-- clk =>clk, +-- grant(01) => grant_signal(43), +-- grant(02) => grant_signal(44), +-- grant(03) => grant_signal(45), +-- grant(04) => grant_signal(46), +-- grant(05) => grant_signal(47), +-- grant(06) => grant_signal(48), +-- grant(07) => grant_signal(49), +-- grant(08) => grant_signal(50), +-- grant(09) => grant_signal(51), +-- grant(10) => grant_signal(52), +-- grant(11) => grant_signal(53), +-- grant(12) => grant_signal(54), +-- grant(13) => grant_signal(55), +-- grant(14) => grant_signal(56), +-- fifo_full =>fifo_in_full(4), +-- priority_rotation => priority_rotation_signal(4), +-- fifo_empty => fifo_in_empty(4), +-- data_out =>crossbar_in_port(4), +-- data_out_pulse =>crossbar_in_pulse(4), +-- request(01) =>request_signal(43), +-- request(02) =>request_signal(44), +-- request(03) =>request_signal(45), +-- request(04) =>request_signal(46), +-- request(05) =>request_signal(47), +-- request(06) =>request_signal(48), +-- request(07) =>request_signal(49), +-- request(08) =>request_signal(50), +-- request(09) =>request_signal(51), +-- request(10) =>request_signal(52), +-- request(11) =>request_signal(53), +-- request(12) =>request_signal(54), +-- request(13) =>request_signal(55), +-- request(14) =>request_signal(56) +--); +-- +--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>14) +--PORT MAP( +-- data_in => Port_in(5), +-- data_in_en => data_in_en(5), +-- reset => reset, +-- clk =>clk, +-- grant(01) => grant_signal(57), +-- grant(02) => grant_signal(58), +-- grant(03) => grant_signal(59), +-- grant(04) => grant_signal(60), +-- grant(05) => grant_signal(61), +-- grant(06) => grant_signal(62), +-- grant(07) => grant_signal(63), +-- grant(08) => grant_signal(64), +-- grant(09) => grant_signal(65), +-- grant(10) => grant_signal(66), +-- grant(11) => grant_signal(67), +-- grant(12) => grant_signal(68), +-- grant(13) => grant_signal(69), +-- grant(14) => grant_signal(70), +-- fifo_full =>fifo_in_full(5), +-- priority_rotation => priority_rotation_signal(5), +-- fifo_empty => fifo_in_empty(5), +-- data_out =>crossbar_in_port(5), +-- data_out_pulse =>crossbar_in_pulse(5), +-- request(01) =>request_signal(57), +-- request(02) =>request_signal(58), +-- request(03) =>request_signal(59), +-- request(04) =>request_signal(60), +-- request(05) =>request_signal(61), +-- request(06) =>request_signal(62), +-- request(07) =>request_signal(63), +-- request(08) =>request_signal(64), +-- request(09) =>request_signal(65), +-- request(10) =>request_signal(66), +-- request(11) =>request_signal(67), +-- request(12) =>request_signal(68), +-- request(13) =>request_signal(69), +-- request(14) =>request_signal(70) +--); +-- +--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>14) +--PORT MAP( +-- data_in => Port_in(6), +-- data_in_en => data_in_en(6), +-- reset => reset, +-- clk =>clk, +-- grant(01) => grant_signal(71), +-- grant(02) => grant_signal(72), +-- grant(03) => grant_signal(73), +-- grant(04) => grant_signal(74), +-- grant(05) => grant_signal(75), +-- grant(06) => grant_signal(76), +-- grant(07) => grant_signal(77), +-- grant(08) => grant_signal(78), +-- grant(09) => grant_signal(79), +-- grant(10) => grant_signal(80), +-- grant(11) => grant_signal(81), +-- grant(12) => grant_signal(82), +-- grant(13) => grant_signal(83), +-- grant(14) => grant_signal(84), +-- fifo_full =>fifo_in_full(6), +-- priority_rotation => priority_rotation_signal(6), +-- fifo_empty => fifo_in_empty(6), +-- data_out =>crossbar_in_port(6), +-- data_out_pulse =>crossbar_in_pulse(6), +-- request(01) =>request_signal(71), +-- request(02) =>request_signal(72), +-- request(03) =>request_signal(73), +-- request(04) =>request_signal(74), +-- request(05) =>request_signal(75), +-- request(06) =>request_signal(76), +-- request(07) =>request_signal(77), +-- request(08) =>request_signal(78), +-- request(09) =>request_signal(79), +-- request(10) =>request_signal(80), +-- request(11) =>request_signal(81), +-- request(12) =>request_signal(82), +-- request(13) =>request_signal(83), +-- request(14) =>request_signal(84) +--); +-- +--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>14) +--PORT MAP( +-- data_in => Port_in(7), +-- data_in_en => data_in_en(7), +-- reset => reset, +-- clk =>clk, +-- grant(01) => grant_signal(85), +-- grant(02) => grant_signal(86), +-- grant(03) => grant_signal(87), +-- grant(04) => grant_signal(88), +-- grant(05) => grant_signal(89), +-- grant(06) => grant_signal(90), +-- grant(07) => grant_signal(91), +-- grant(08) => grant_signal(92), +-- grant(09) => grant_signal(93), +-- grant(10) => grant_signal(94), +-- grant(11) => grant_signal(95), +-- grant(12) => grant_signal(96), +-- grant(13) => grant_signal(97), +-- grant(14) => grant_signal(98), +-- fifo_full =>fifo_in_full(7), +-- priority_rotation => priority_rotation_signal(7), +-- fifo_empty => fifo_in_empty(7), +-- data_out =>crossbar_in_port(7), +-- data_out_pulse =>crossbar_in_pulse(7), +-- request(01) =>request_signal(85), +-- request(02) =>request_signal(86), +-- request(03) =>request_signal(87), +-- request(04) =>request_signal(88), +-- request(05) =>request_signal(89), +-- request(06) =>request_signal(90), +-- request(07) =>request_signal(91), +-- request(08) =>request_signal(92), +-- request(09) =>request_signal(93), +-- request(10) =>request_signal(94), +-- request(11) =>request_signal(95), +-- request(12) =>request_signal(96), +-- request(13) =>request_signal(97), +-- request(14) =>request_signal(98) +--); +-- +--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>14) +--PORT MAP( +-- data_in => Port_in(8), +-- data_in_en => data_in_en(8), +-- reset => reset, +-- clk =>clk, +-- grant(01) => grant_signal(99), +-- grant(02) => grant_signal(100), +-- grant(03) => grant_signal(101), +-- grant(04) => grant_signal(102), +-- grant(05) => grant_signal(103), +-- grant(06) => grant_signal(104), +-- grant(07) => grant_signal(105), +-- grant(08) => grant_signal(106), +-- grant(09) => grant_signal(107), +-- grant(10) => grant_signal(108), +-- grant(11) => grant_signal(109), +-- grant(12) => grant_signal(110), +-- grant(13) => grant_signal(111), +-- grant(14) => grant_signal(112), +-- fifo_full =>fifo_in_full(8), +-- priority_rotation => priority_rotation_signal(8), +-- fifo_empty => fifo_in_empty(8), +-- data_out =>crossbar_in_port(8), +-- data_out_pulse =>crossbar_in_pulse(8), +-- request(1) =>request_signal(99), +-- request(2) =>request_signal(100), +-- request(3) =>request_signal(101), +-- request(4) =>request_signal(102), +-- request(5) =>request_signal(103), +-- request(6) =>request_signal(104), +-- request(7) =>request_signal(105), +-- request(8) =>request_signal(106), +-- request(9) =>request_signal(107), +-- request(10) =>request_signal(108), +-- request(11) =>request_signal(109), +-- request(12) =>request_signal(110), +-- request(13) =>request_signal(111), +-- request(14) =>request_signal(112) +--); +-- +--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>14) +--PORT MAP( +-- data_in => Port_in(9), +-- data_in_en => data_in_en(9), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(113), +-- grant(2) => grant_signal(114), +-- grant(3) => grant_signal(115), +-- grant(4) => grant_signal(116), +-- grant(5) => grant_signal(117), +-- grant(6) => grant_signal(118), +-- grant(7) => grant_signal(119), +-- grant(8) => grant_signal(120), +-- grant(9) => grant_signal(121), +-- grant(10) => grant_signal(122), +-- grant(11) => grant_signal(123), +-- grant(12) => grant_signal(124), +-- grant(13) => grant_signal(125), +-- grant(14) => grant_signal(126), +-- fifo_full =>fifo_in_full(9), +-- priority_rotation => priority_rotation_signal(9), +-- fifo_empty => fifo_in_empty(9), +-- data_out =>crossbar_in_port(9), +-- data_out_pulse =>crossbar_in_pulse(9), +-- request(1) =>request_signal(113), +-- request(2) =>request_signal(114), +-- request(3) =>request_signal(115), +-- request(4) =>request_signal(116), +-- request(5) =>request_signal(117), +-- request(6) =>request_signal(118), +-- request(7) =>request_signal(119), +-- request(8) =>request_signal(120), +-- request(9) =>request_signal(121), +-- request(10) =>request_signal(122), +-- request(11) =>request_signal(123), +-- request(12) =>request_signal(124), +-- request(13) =>request_signal(125), +-- request(14) =>request_signal(126) +--); +-- +--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>14) +--PORT MAP( +-- data_in => Port_in(10), +-- data_in_en => data_in_en(10), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(127), +-- grant(2) => grant_signal(128), +-- grant(3) => grant_signal(129), +-- grant(4) => grant_signal(130), +-- grant(5) => grant_signal(131), +-- grant(6) => grant_signal(132), +-- grant(7) => grant_signal(133), +-- grant(8) => grant_signal(134), +-- grant(9) => grant_signal(135), +-- grant(10) => grant_signal(136), +-- grant(11) => grant_signal(137), +-- grant(12) => grant_signal(138), +-- grant(13) => grant_signal(139), +-- grant(14) => grant_signal(140), +-- fifo_full =>fifo_in_full(10), +-- priority_rotation => priority_rotation_signal(10), +-- fifo_empty => fifo_in_empty(10), +-- data_out =>crossbar_in_port(10), +-- data_out_pulse =>crossbar_in_pulse(10), +-- request(1) =>request_signal(127), +-- request(2) =>request_signal(128), +-- request(3) =>request_signal(129), +-- request(4) =>request_signal(130), +-- request(5) =>request_signal(131), +-- request(6) =>request_signal(132), +-- request(7) =>request_signal(133), +-- request(8) =>request_signal(134), +-- request(9) =>request_signal(135), +-- request(10) =>request_signal(136), +-- request(11) =>request_signal(137), +-- request(12) =>request_signal(138), +-- request(13) =>request_signal(139), +-- request(14) =>request_signal(140) +--); +-- +--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>14) +--PORT MAP( +-- data_in => Port_in(11), +-- data_in_en => data_in_en(11), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(141), +-- grant(2) => grant_signal(142), +-- grant(3) => grant_signal(143), +-- grant(4) => grant_signal(144), +-- grant(5) => grant_signal(145), +-- grant(6) => grant_signal(146), +-- grant(7) => grant_signal(147), +-- grant(8) => grant_signal(148), +-- grant(9) => grant_signal(149), +-- grant(10) => grant_signal(150), +-- grant(11) => grant_signal(151), +-- grant(12) => grant_signal(152), +-- grant(13) => grant_signal(153), +-- grant(14) => grant_signal(154), +-- fifo_full =>fifo_in_full(11), +-- priority_rotation => priority_rotation_signal(11), +-- fifo_empty => fifo_in_empty(11), +-- data_out =>crossbar_in_port(11), +-- data_out_pulse =>crossbar_in_pulse(11), +-- request(1) =>request_signal(141), +-- request(2) =>request_signal(142), +-- request(3) =>request_signal(143), +-- request(4) =>request_signal(144), +-- request(5) =>request_signal(145), +-- request(6) =>request_signal(146), +-- request(7) =>request_signal(147), +-- request(8) =>request_signal(148), +-- request(9) =>request_signal(149), +-- request(10) =>request_signal(150), +-- request(11) =>request_signal(151), +-- request(12) =>request_signal(152), +-- request(13) =>request_signal(153), +-- request(14) =>request_signal(154) +--); +-- +--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>14) +--PORT MAP( +-- data_in => Port_in(12), +-- data_in_en => data_in_en(12), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(155), +-- grant(2) => grant_signal(156), +-- grant(3) => grant_signal(157), +-- grant(4) => grant_signal(158), +-- grant(5) => grant_signal(159), +-- grant(6) => grant_signal(160), +-- grant(7) => grant_signal(161), +-- grant(8) => grant_signal(162), +-- grant(9) => grant_signal(163), +-- grant(10) => grant_signal(164), +-- grant(11) => grant_signal(165), +-- grant(12) => grant_signal(166), +-- grant(13) => grant_signal(167), +-- grant(14) => grant_signal(168), +-- fifo_full =>fifo_in_full(12), +-- priority_rotation => priority_rotation_signal(12), +-- fifo_empty => fifo_in_empty(12), +-- data_out =>crossbar_in_port(12), +-- data_out_pulse =>crossbar_in_pulse(12), +-- request(1) =>request_signal(155), +-- request(2) =>request_signal(156), +-- request(3) =>request_signal(157), +-- request(4) =>request_signal(158), +-- request(5) =>request_signal(159), +-- request(6) =>request_signal(160), +-- request(7) =>request_signal(161), +-- request(8) =>request_signal(162), +-- request(9) =>request_signal(163), +-- request(10) =>request_signal(164), +-- request(11) =>request_signal(165), +-- request(12) =>request_signal(166), +-- request(13) =>request_signal(167), +-- request(14) =>request_signal(168) +--); +-- +--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>14) +--PORT MAP( +-- data_in => Port_in(13), +-- data_in_en => data_in_en(13), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(169), +-- grant(2) => grant_signal(170), +-- grant(3) => grant_signal(171), +-- grant(4) => grant_signal(172), +-- grant(5) => grant_signal(173), +-- grant(6) => grant_signal(174), +-- grant(7) => grant_signal(175), +-- grant(8) => grant_signal(176), +-- grant(9) => grant_signal(177), +-- grant(10) => grant_signal(178), +-- grant(11) => grant_signal(179), +-- grant(12) => grant_signal(180), +-- grant(13) => grant_signal(181), +-- grant(14) => grant_signal(182), +-- fifo_full =>fifo_in_full(13), +-- priority_rotation => priority_rotation_signal(13), +-- fifo_empty => fifo_in_empty(13), +-- data_out =>crossbar_in_port(13), +-- data_out_pulse =>crossbar_in_pulse(13), +-- request(1) =>request_signal(169), +-- request(2) =>request_signal(170), +-- request(3) =>request_signal(171), +-- request(4) =>request_signal(172), +-- request(5) =>request_signal(173), +-- request(6) =>request_signal(174), +-- request(7) =>request_signal(175), +-- request(8) =>request_signal(176), +-- request(9) =>request_signal(177), +-- request(10) =>request_signal(178), +-- request(11) =>request_signal(179), +-- request(12) =>request_signal(180), +-- request(13) =>request_signal(181), +-- request(14) =>request_signal(182) +--); +-- +--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>14) +--PORT MAP( +-- data_in => Port_in(14), +-- data_in_en => data_in_en(14), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(183), +-- grant(2) => grant_signal(184), +-- grant(3) => grant_signal(185), +-- grant(4) => grant_signal(186), +-- grant(5) => grant_signal(187), +-- grant(6) => grant_signal(188), +-- grant(7) => grant_signal(189), +-- grant(8) => grant_signal(190), +-- grant(9) => grant_signal(191), +-- grant(10) => grant_signal(192), +-- grant(11) => grant_signal(193), +-- grant(12) => grant_signal(194), +-- grant(13) => grant_signal(195), +-- grant(14) => grant_signal(196), +-- fifo_full =>fifo_in_full(14), +-- priority_rotation => priority_rotation_signal(14), +-- fifo_empty => fifo_in_empty(14), +-- data_out =>crossbar_in_port(14), +-- data_out_pulse =>crossbar_in_pulse(14), +-- request(1) =>request_signal(183), +-- request(2) =>request_signal(184), +-- request(3) =>request_signal(185), +-- request(4) =>request_signal(186), +-- request(5) =>request_signal(187), +-- request(6) =>request_signal(188), +-- request(7) =>request_signal(189), +-- request(8) =>request_signal(190), +-- request(9) =>request_signal(191), +-- request(10) =>request_signal(192), +-- request(11) =>request_signal(193), +-- request(12) =>request_signal(194), +-- request(13) =>request_signal(195), +-- request(14) =>request_signal(196) +--); +-- +--end generate switch14x14; +-- +-- +---- switch 15 ports +--switch15x15 : if number_of_ports = 15 generate +-- +--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(1), +-- data_in_en => data_in_en(1), +-- reset => reset, +-- clk =>clk, +-- grant(1) => grant_signal(1), +-- grant(2) => grant_signal(2), +-- grant(3) => grant_signal(3), +-- grant(4) => grant_signal(4), +-- grant(5) => grant_signal(5), +-- grant(6) => grant_signal(6), +-- grant(7) => grant_signal(7), +-- grant(8) => grant_signal(8), +-- grant(9) => grant_signal(9), +-- grant(10) => grant_signal(10), +-- grant(11) => grant_signal(11), +-- grant(12) => grant_signal(12), +-- grant(13) => grant_signal(13), +-- grant(14) => grant_signal(14), +-- grant(15) => grant_signal(15), +-- fifo_full =>fifo_in_full(1), +-- priority_rotation => priority_rotation_signal(1), +-- fifo_empty => fifo_in_empty(1), +-- data_out =>crossbar_in_port(1), +-- data_out_pulse =>crossbar_in_pulse(1), +-- request(1) =>request_signal(1), +-- request(2) =>request_signal(2), +-- request(3) =>request_signal(3), +-- request(4) =>request_signal(4), +-- request(5) =>request_signal(5), +-- request(6) =>request_signal(6), +-- request(7) =>request_signal(7), +-- request(8) =>request_signal(8), +-- request(9) =>request_signal(9), +-- request(10) =>request_signal(10), +-- request(11) =>request_signal(11), +-- request(12) =>request_signal(12), +-- request(13) =>request_signal(13), +-- request(14) =>request_signal(14), +-- request(15) =>request_signal(15) +--); +-- +--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(2), +-- data_in_en => data_in_en(2), +-- reset => reset, +-- clk =>clk, +-- grant(16) => grant_signal(16), +-- grant(17) => grant_signal(17), +-- grant(18) => grant_signal(18), +-- grant(19) => grant_signal(19), +-- grant(20) => grant_signal(20), +-- grant(21) => grant_signal(21), +-- grant(22) => grant_signal(22), +-- grant(23) => grant_signal(23), +-- grant(24) => grant_signal(24), +-- grant(25) => grant_signal(25), +-- grant(26) => grant_signal(26), +-- grant(27) => grant_signal(27), +-- grant(28) => grant_signal(28), +-- grant(29) => grant_signal(29), +-- grant(30) => grant_signal(30), +-- fifo_full =>fifo_in_full(2), +-- priority_rotation => priority_rotation_signal(2), +-- fifo_empty => fifo_in_empty(2), +-- data_out =>crossbar_in_port(2), +-- data_out_pulse =>crossbar_in_pulse(2), +-- request(16) =>request_signal(16), +-- request(17) =>request_signal(17), +-- request(18) =>request_signal(18), +-- request(19) =>request_signal(19), +-- request(20) =>request_signal(20), +-- request(21) =>request_signal(21), +-- request(22) =>request_signal(22), +-- request(23) =>request_signal(23), +-- request(24) =>request_signal(24), +-- request(25) =>request_signal(25), +-- request(26) =>request_signal(26), +-- request(27) =>request_signal(27), +-- request(28) =>request_signal(28), +-- request(29) =>request_signal(29), +-- request(30) =>request_signal(30) +--); +-- +--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(3), +-- data_in_en => data_in_en(3), +-- reset => reset, +-- clk =>clk, +-- grant(31) => grant_signal(31), +-- grant(32) => grant_signal(32), +-- grant(33) => grant_signal(33), +-- grant(34) => grant_signal(34), +-- grant(35) => grant_signal(35), +-- grant(36) => grant_signal(36), +-- grant(37) => grant_signal(37), +-- grant(38) => grant_signal(38), +-- grant(39) => grant_signal(39), +-- grant(40) => grant_signal(40), +-- grant(41) => grant_signal(41), +-- grant(42) => grant_signal(42), +-- grant(43) => grant_signal(43), +-- grant(44) => grant_signal(44), +-- grant(45) => grant_signal(45), +-- fifo_full =>fifo_in_full(3), +-- priority_rotation => priority_rotation_signal(3), +-- fifo_empty => fifo_in_empty(3), +-- data_out =>crossbar_in_port(3), +-- data_out_pulse =>crossbar_in_pulse(3), +-- request(31) =>request_signal(31), +-- request(32) =>request_signal(32), +-- request(33) =>request_signal(33), +-- request(34) =>request_signal(34), +-- request(35) =>request_signal(35), +-- request(36) =>request_signal(36), +-- request(37) =>request_signal(37), +-- request(38) =>request_signal(38), +-- request(39) =>request_signal(39), +-- request(40) =>request_signal(40), +-- request(41) =>request_signal(41), +-- request(42) =>request_signal(42), +-- request(43) =>request_signal(43), +-- request(44) =>request_signal(44), +-- request(45) =>request_signal(45) +--); +-- +--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(4), +-- data_in_en => data_in_en(4), +-- reset => reset, +-- clk =>clk, +-- grant(46) => grant_signal(46), +-- grant(47) => grant_signal(47), +-- grant(48) => grant_signal(48), +-- grant(49) => grant_signal(49), +-- grant(50) => grant_signal(50), +-- grant(51) => grant_signal(51), +-- grant(52) => grant_signal(52), +-- grant(53) => grant_signal(53), +-- grant(54) => grant_signal(54), +-- grant(55) => grant_signal(55), +-- grant(56) => grant_signal(56), +-- grant(57) => grant_signal(57), +-- grant(58) => grant_signal(58), +-- grant(59) => grant_signal(59), +-- grant(60) => grant_signal(60), +-- fifo_full =>fifo_in_full(4), +-- priority_rotation => priority_rotation_signal(4), +-- fifo_empty => fifo_in_empty(4), +-- data_out =>crossbar_in_port(4), +-- data_out_pulse =>crossbar_in_pulse(4), +-- request(46) =>request_signal(46), +-- request(47) =>request_signal(47), +-- request(48) =>request_signal(48), +-- request(49) =>request_signal(49), +-- request(50) =>request_signal(50), +-- request(51) =>request_signal(51), +-- request(52) =>request_signal(52), +-- request(53) =>request_signal(53), +-- request(54) =>request_signal(54), +-- request(55) =>request_signal(55), +-- request(56) =>request_signal(56), +-- request(57) =>request_signal(57), +-- request(58) =>request_signal(58), +-- request(59) =>request_signal(59), +-- request(60) =>request_signal(60) +--); +-- +--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(5), +-- data_in_en => data_in_en(5), +-- reset => reset, +-- clk =>clk, +-- grant(61) => grant_signal(61), +-- grant(62) => grant_signal(62), +-- grant(63) => grant_signal(63), +-- grant(64) => grant_signal(64), +-- grant(65) => grant_signal(65), +-- grant(66) => grant_signal(66), +-- grant(67) => grant_signal(67), +-- grant(68) => grant_signal(68), +-- grant(69) => grant_signal(69), +-- grant(70) => grant_signal(70), +-- grant(71) => grant_signal(71), +-- grant(72) => grant_signal(72), +-- grant(73) => grant_signal(73), +-- grant(74) => grant_signal(74), +-- grant(75) => grant_signal(75), +-- fifo_full =>fifo_in_full(5), +-- priority_rotation => priority_rotation_signal(5), +-- fifo_empty => fifo_in_empty(5), +-- data_out =>crossbar_in_port(5), +-- data_out_pulse =>crossbar_in_pulse(5), +-- request(61) =>request_signal(61), +-- request(62) =>request_signal(62), +-- request(63) =>request_signal(63), +-- request(64) =>request_signal(64), +-- request(65) =>request_signal(65), +-- request(66) =>request_signal(66), +-- request(67) =>request_signal(67), +-- request(68) =>request_signal(68), +-- request(69) =>request_signal(69), +-- request(70) =>request_signal(70), +-- request(71) =>request_signal(71), +-- request(72) =>request_signal(72), +-- request(73) =>request_signal(73), +-- request(74) =>request_signal(74), +-- request(75) =>request_signal(75) +--); +-- +--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(6), +-- data_in_en => data_in_en(6), +-- reset => reset, +-- clk =>clk, +-- grant(76) => grant_signal(76), +-- grant(77) => grant_signal(77), +-- grant(78) => grant_signal(78), +-- grant(79) => grant_signal(79), +-- grant(80) => grant_signal(80), +-- grant(81) => grant_signal(81), +-- grant(82) => grant_signal(82), +-- grant(83) => grant_signal(83), +-- grant(84) => grant_signal(84), +-- grant(85) => grant_signal(85), +-- grant(86) => grant_signal(86), +-- grant(87) => grant_signal(87), +-- grant(88) => grant_signal(88), +-- grant(89) => grant_signal(89), +-- grant(90) => grant_signal(90), +-- fifo_full =>fifo_in_full(6), +-- priority_rotation => priority_rotation_signal(6), +-- fifo_empty => fifo_in_empty(6), +-- data_out =>crossbar_in_port(6), +-- data_out_pulse =>crossbar_in_pulse(6), +-- request(76) =>request_signal(76), +-- request(77) =>request_signal(77), +-- request(78) =>request_signal(78), +-- request(79) =>request_signal(79), +-- request(80) =>request_signal(80), +-- request(81) =>request_signal(81), +-- request(82) =>request_signal(82), +-- request(83) =>request_signal(83), +-- request(84) =>request_signal(84), +-- request(85) =>request_signal(85), +-- request(86) =>request_signal(86), +-- request(87) =>request_signal(87), +-- request(88) =>request_signal(88), +-- request(89) =>request_signal(89), +-- request(90) =>request_signal(90) +--); +-- +--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(7), +-- data_in_en => data_in_en(7), +-- reset => reset, +-- clk =>clk, +-- grant(91) => grant_signal(91), +-- grant(92) => grant_signal(92), +-- grant(93) => grant_signal(93), +-- grant(94) => grant_signal(94), +-- grant(95) => grant_signal(95), +-- grant(96) => grant_signal(96), +-- grant(97) => grant_signal(97), +-- grant(98) => grant_signal(98), +-- grant(99) => grant_signal(99), +-- grant(100) => grant_signal(100), +-- grant(101) => grant_signal(101), +-- grant(102) => grant_signal(102), +-- grant(103) => grant_signal(103), +-- grant(104) => grant_signal(104), +-- grant(105) => grant_signal(105), +-- fifo_full =>fifo_in_full(7), +-- priority_rotation => priority_rotation_signal(7), +-- fifo_empty => fifo_in_empty(7), +-- data_out =>crossbar_in_port(7), +-- data_out_pulse =>crossbar_in_pulse(7), +-- request(91) =>request_signal(91), +-- request(92) =>request_signal(92), +-- request(93) =>request_signal(93), +-- request(94) =>request_signal(94), +-- request(95) =>request_signal(95), +-- request(96) =>request_signal(96), +-- request(97) =>request_signal(97), +-- request(98) =>request_signal(98), +-- request(99) =>request_signal(99), +-- request(100) =>request_signal(100), +-- request(101) =>request_signal(101), +-- request(102) =>request_signal(102), +-- request(103) =>request_signal(103), +-- request(104) =>request_signal(104), +-- request(105) =>request_signal(105) +--); +-- +--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(8), +-- data_in_en => data_in_en(8), +-- reset => reset, +-- clk =>clk, +-- grant(106) => grant_signal(106), +-- grant(107) => grant_signal(107), +-- grant(108) => grant_signal(108), +-- grant(109) => grant_signal(109), +-- grant(110) => grant_signal(110), +-- grant(111) => grant_signal(111), +-- grant(112) => grant_signal(112), +-- grant(113) => grant_signal(113), +-- grant(114) => grant_signal(114), +-- grant(115) => grant_signal(115), +-- grant(116) => grant_signal(116), +-- grant(117) => grant_signal(117), +-- grant(118) => grant_signal(118), +-- grant(119) => grant_signal(119), +-- grant(120) => grant_signal(120), +-- fifo_full =>fifo_in_full(8), +-- priority_rotation => priority_rotation_signal(8), +-- fifo_empty => fifo_in_empty(8), +-- data_out =>crossbar_in_port(8), +-- data_out_pulse =>crossbar_in_pulse(8), +-- request(106) =>request_signal(106), +-- request(107) =>request_signal(107), +-- request(108) =>request_signal(108), +-- request(109) =>request_signal(109), +-- request(110) =>request_signal(110), +-- request(111) =>request_signal(111), +-- request(112) =>request_signal(112), +-- request(113) =>request_signal(113), +-- request(114) =>request_signal(114), +-- request(115) =>request_signal(115), +-- request(116) =>request_signal(116), +-- request(117) =>request_signal(117), +-- request(118) =>request_signal(118), +-- request(119) =>request_signal(119), +-- request(120) =>request_signal(120) +--); +-- +--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(9), +-- data_in_en => data_in_en(9), +-- reset => reset, +-- clk =>clk, +-- grant(121) => grant_signal(121), +-- grant(122) => grant_signal(122), +-- grant(123) => grant_signal(123), +-- grant(124) => grant_signal(124), +-- grant(125) => grant_signal(125), +-- grant(126) => grant_signal(126), +-- grant(127) => grant_signal(127), +-- grant(128) => grant_signal(128), +-- grant(129) => grant_signal(129), +-- grant(130) => grant_signal(130), +-- grant(131) => grant_signal(131), +-- grant(132) => grant_signal(132), +-- grant(133) => grant_signal(133), +-- grant(134) => grant_signal(134), +-- grant(135) => grant_signal(135), +-- fifo_full =>fifo_in_full(9), +-- priority_rotation => priority_rotation_signal(9), +-- fifo_empty => fifo_in_empty(9), +-- data_out =>crossbar_in_port(9), +-- data_out_pulse =>crossbar_in_pulse(9), +-- request(121) =>request_signal(121), +-- request(122) =>request_signal(122), +-- request(123) =>request_signal(123), +-- request(124) =>request_signal(124), +-- request(125) =>request_signal(125), +-- request(126) =>request_signal(126), +-- request(127) =>request_signal(127), +-- request(128) =>request_signal(128), +-- request(129) =>request_signal(129), +-- request(130) =>request_signal(130), +-- request(131) =>request_signal(131), +-- request(132) =>request_signal(132), +-- request(133) =>request_signal(133), +-- request(134) =>request_signal(134), +-- request(135) =>request_signal(135) +--); +-- +--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(10), +-- data_in_en => data_in_en(10), +-- reset => reset, +-- clk =>clk, +-- grant(136) => grant_signal(136), +-- grant(137) => grant_signal(137), +-- grant(138) => grant_signal(138), +-- grant(139) => grant_signal(139), +-- grant(140) => grant_signal(140), +-- grant(141) => grant_signal(141), +-- grant(142) => grant_signal(142), +-- grant(143) => grant_signal(143), +-- grant(144) => grant_signal(144), +-- grant(145) => grant_signal(145), +-- grant(146) => grant_signal(146), +-- grant(147) => grant_signal(147), +-- grant(148) => grant_signal(148), +-- grant(149) => grant_signal(149), +-- grant(150) => grant_signal(150), +-- fifo_full =>fifo_in_full(10), +-- priority_rotation => priority_rotation_signal(10), +-- fifo_empty => fifo_in_empty(10), +-- data_out =>crossbar_in_port(10), +-- data_out_pulse =>crossbar_in_pulse(10), +-- request(136) =>request_signal(136), +-- request(137) =>request_signal(137), +-- request(138) =>request_signal(138), +-- request(139) =>request_signal(139), +-- request(140) =>request_signal(140), +-- request(141) =>request_signal(141), +-- request(142) =>request_signal(142), +-- request(143) =>request_signal(143), +-- request(144) =>request_signal(144), +-- request(145) =>request_signal(145), +-- request(146) =>request_signal(146), +-- request(147) =>request_signal(147), +-- request(148) =>request_signal(148), +-- request(149) =>request_signal(149), +-- request(150) =>request_signal(150) +--); +-- +--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(11), +-- data_in_en => data_in_en(11), +-- reset => reset, +-- clk =>clk, +-- grant(151) => grant_signal(151), +-- grant(152) => grant_signal(152), +-- grant(153) => grant_signal(153), +-- grant(154) => grant_signal(154), +-- grant(155) => grant_signal(155), +-- grant(156) => grant_signal(156), +-- grant(157) => grant_signal(157), +-- grant(158) => grant_signal(158), +-- grant(159) => grant_signal(159), +-- grant(160) => grant_signal(160), +-- grant(161) => grant_signal(161), +-- grant(162) => grant_signal(162), +-- grant(163) => grant_signal(163), +-- grant(164) => grant_signal(164), +-- grant(165) => grant_signal(165), +-- fifo_full =>fifo_in_full(11), +-- priority_rotation => priority_rotation_signal(11), +-- fifo_empty => fifo_in_empty(11), +-- data_out =>crossbar_in_port(11), +-- data_out_pulse =>crossbar_in_pulse(11), +-- request(151) =>request_signal(151), +-- request(152) =>request_signal(152), +-- request(153) =>request_signal(153), +-- request(154) =>request_signal(154), +-- request(155) =>request_signal(155), +-- request(156) =>request_signal(156), +-- request(157) =>request_signal(157), +-- request(158) =>request_signal(158), +-- request(159) =>request_signal(159), +-- request(160) =>request_signal(160), +-- request(161) =>request_signal(161), +-- request(162) =>request_signal(162), +-- request(163) =>request_signal(163), +-- request(164) =>request_signal(164), +-- request(165) =>request_signal(165) +--); +-- +--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(12), +-- data_in_en => data_in_en(12), +-- reset => reset, +-- clk =>clk, +-- grant(166) => grant_signal(166), +-- grant(167) => grant_signal(167), +-- grant(168) => grant_signal(168), +-- grant(169) => grant_signal(169), +-- grant(170) => grant_signal(170), +-- grant(171) => grant_signal(171), +-- grant(172) => grant_signal(172), +-- grant(173) => grant_signal(173), +-- grant(174) => grant_signal(174), +-- grant(175) => grant_signal(175), +-- grant(176) => grant_signal(176), +-- grant(177) => grant_signal(177), +-- grant(178) => grant_signal(178), +-- grant(179) => grant_signal(179), +-- grant(180) => grant_signal(180), +-- fifo_full =>fifo_in_full(12), +-- priority_rotation => priority_rotation_signal(12), +-- fifo_empty => fifo_in_empty(12), +-- data_out =>crossbar_in_port(12), +-- data_out_pulse =>crossbar_in_pulse(12), +-- request(166) =>request_signal(166), +-- request(167) =>request_signal(167), +-- request(168) =>request_signal(168), +-- request(169) =>request_signal(169), +-- request(170) =>request_signal(170), +-- request(171) =>request_signal(171), +-- request(172) =>request_signal(172), +-- request(173) =>request_signal(173), +-- request(174) =>request_signal(174), +-- request(175) =>request_signal(175), +-- request(176) =>request_signal(176), +-- request(177) =>request_signal(177), +-- request(178) =>request_signal(178), +-- request(179) =>request_signal(179), +-- request(180) =>request_signal(180) +--); +-- +--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(13), +-- data_in_en => data_in_en(13), +-- reset => reset, +-- clk =>clk, +-- grant(181) => grant_signal(181), +-- grant(182) => grant_signal(182), +-- grant(183) => grant_signal(183), +-- grant(184) => grant_signal(184), +-- grant(185) => grant_signal(185), +-- grant(186) => grant_signal(186), +-- grant(187) => grant_signal(187), +-- grant(188) => grant_signal(188), +-- grant(189) => grant_signal(189), +-- grant(190) => grant_signal(190), +-- grant(191) => grant_signal(191), +-- grant(192) => grant_signal(192), +-- grant(193) => grant_signal(193), +-- grant(194) => grant_signal(194), +-- grant(195) => grant_signal(195), +-- fifo_full =>fifo_in_full(13), +-- priority_rotation => priority_rotation_signal(13), +-- fifo_empty => fifo_in_empty(13), +-- data_out =>crossbar_in_port(13), +-- data_out_pulse =>crossbar_in_pulse(13), +-- request(181) =>request_signal(181), +-- request(182) =>request_signal(182), +-- request(183) =>request_signal(183), +-- request(184) =>request_signal(184), +-- request(185) =>request_signal(185), +-- request(186) =>request_signal(186), +-- request(187) =>request_signal(187), +-- request(188) =>request_signal(188), +-- request(189) =>request_signal(189), +-- request(190) =>request_signal(190), +-- request(191) =>request_signal(191), +-- request(192) =>request_signal(192), +-- request(193) =>request_signal(193), +-- request(194) =>request_signal(194), +-- request(195) =>request_signal(195) +--); +-- +--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(14), +-- data_in_en => data_in_en(14), +-- reset => reset, +-- clk =>clk, +-- grant(196) => grant_signal(196), +-- grant(197) => grant_signal(197), +-- grant(198) => grant_signal(198), +-- grant(199) => grant_signal(199), +-- grant(200) => grant_signal(200), +-- grant(201) => grant_signal(201), +-- grant(202) => grant_signal(202), +-- grant(203) => grant_signal(203), +-- grant(204) => grant_signal(204), +-- grant(205) => grant_signal(205), +-- grant(206) => grant_signal(206), +-- grant(207) => grant_signal(207), +-- grant(208) => grant_signal(208), +-- grant(209) => grant_signal(209), +-- grant(210) => grant_signal(210), +-- fifo_full =>fifo_in_full(14), +-- priority_rotation => priority_rotation_signal(14), +-- fifo_empty => fifo_in_empty(14), +-- data_out =>crossbar_in_port(14), +-- data_out_pulse =>crossbar_in_pulse(14), +-- request(196) =>request_signal(196), +-- request(197) =>request_signal(197), +-- request(198) =>request_signal(198), +-- request(199) =>request_signal(199), +-- request(200) =>request_signal(200), +-- request(201) =>request_signal(201), +-- request(202) =>request_signal(202), +-- request(203) =>request_signal(203), +-- request(204) =>request_signal(204), +-- request(205) =>request_signal(205), +-- request(206) =>request_signal(206), +-- request(207) =>request_signal(207), +-- request(208) =>request_signal(208), +-- request(209) =>request_signal(209), +-- request(210) =>request_signal(210) +--); +-- +--PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>15) +--PORT MAP( +-- data_in => Port_in(15), +-- data_in_en => data_in_en(15), +-- reset => reset, +-- clk =>clk, +-- grant(211) => grant_signal(211), +-- grant(212) => grant_signal(212), +-- grant(213) => grant_signal(213), +-- grant(214) => grant_signal(214), +-- grant(215) => grant_signal(215), +-- grant(216) => grant_signal(216), +-- grant(217) => grant_signal(217), +-- grant(218) => grant_signal(218), +-- grant(219) => grant_signal(219), +-- grant(220) => grant_signal(220), +-- grant(221) => grant_signal(221), +-- grant(222) => grant_signal(222), +-- grant(223) => grant_signal(223), +-- grant(224) => grant_signal(224), +-- grant(225) => grant_signal(225), +-- fifo_full =>fifo_in_full(15), +-- priority_rotation => priority_rotation_signal(15), +-- fifo_empty => fifo_in_empty(15), +-- data_out =>crossbar_in_port(15), +-- data_out_pulse =>crossbar_in_pulse(15), +-- request(211) =>request_signal(211), +-- request(212) =>request_signal(212), +-- request(213) =>request_signal(213), +-- request(214) =>request_signal(214), +-- request(215) =>request_signal(215), +-- request(216) =>request_signal(216), +-- request(217) =>request_signal(217), +-- request(218) =>request_signal(218), +-- request(219) =>request_signal(219), +-- request(220) =>request_signal(220), +-- request(221) =>request_signal(221), +-- request(222) =>request_signal(222), +-- request(223) =>request_signal(223), +-- request(224) =>request_signal(224), +-- request(225) =>request_signal(225) +--); +-- +--end generate switch15x15; + + +-- switch 16 ports +switch16x16 : if number_of_ports = 16 generate +switch_16x16 :for i in 1 to number_of_ports generate +Constant j : natural:=number_of_ports*(i-1); +begin +--j<=number_of_ports*(i-1); +PORTx16_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16,port_num=>i) +PORT MAP( + data_in => Port_in(i), + data_in_en => data_in_en(i), + cmd_in_en => cmd_in_en(i), + reset => reset, + clk =>clk, + grant(1) => grant_signal(j+1), + grant(2) => grant_signal(j+2), + grant(3) => grant_signal(j+3), + grant(4) => grant_signal(j+4), + grant(5) => grant_signal(j+5), + grant(6) => grant_signal(j+6), + grant(7) => grant_signal(j+7), + grant(8) => grant_signal(j+8), + grant(9) => grant_signal(j+9), + grant(10) => grant_signal(j+10), + grant(11) => grant_signal(j+11), + grant(12) => grant_signal(j+12), + grant(13) => grant_signal(j+13), + grant(14) => grant_signal(j+14), + grant(15) => grant_signal(j+15), + grant(16) => grant_signal(j+16), + fifo_full =>fifo_in_full(i), + priority_rotation => priority_rotation_signal(i), + fifo_empty => fifo_in_empty(i), + data_out =>crossbar_in_port(i), + data_out_pulse =>crossbar_in_pulse(i), + request(1) =>request_signal(j+1), + request(2) =>request_signal(j+2), + request(3) =>request_signal(j+3), + request(4) =>request_signal(j+4), + request(5) =>request_signal(j+5), + request(6) =>request_signal(j+6), + request(7) =>request_signal(j+7), + request(8) =>request_signal(j+8), + request(9) =>request_signal(j+9), + request(10) =>request_signal(j+10), + request(11) =>request_signal(j+11), + request(12) =>request_signal(j+12), + request(13) =>request_signal(j+13), + request(14) =>request_signal(j+14), + request(15) =>request_signal(j+15), + request(16) =>request_signal(j+16) +); +end generate switch_16x16; +end generate switch16x16; +--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(2), +-- data_in_en => data_in_en(2), +-- reset => reset, +-- clk =>clk, +-- grant(17) => grant_signal(17), +-- grant(18) => grant_signal(18), +-- grant(19) => grant_signal(19), +-- grant(20) => grant_signal(20), +-- grant(21) => grant_signal(21), +-- grant(22) => grant_signal(22), +-- grant(23) => grant_signal(23), +-- grant(24) => grant_signal(24), +-- grant(25) => grant_signal(25), +-- grant(26) => grant_signal(26), +-- grant(27) => grant_signal(27), +-- grant(28) => grant_signal(28), +-- grant(29) => grant_signal(29), +-- grant(30) => grant_signal(30), +-- grant(31) => grant_signal(31), +-- grant(32) => grant_signal(32), +-- fifo_full =>fifo_in_full(2), +-- priority_rotation => priority_rotation_signal(2), +-- fifo_empty => fifo_in_empty(2), +-- data_out =>crossbar_in_port2, +-- data_out_pulse =>crossbar_in_pulse(2, +-- request(17) =>request_signal(17), +-- request(18) =>request_signal(18), +-- request(19) =>request_signal(19), +-- request(20) =>request_signal(20), +-- request(21) =>request_signal(21), +-- request(22) =>request_signal(22), +-- request(23) =>request_signal(23), +-- request(24) =>request_signal(24), +-- request(25) =>request_signal(25), +-- request(26) =>request_signal(26), +-- request(27) =>request_signal(27), +-- request(28) =>request_signal(28), +-- request(29) =>request_signal(29), +-- request(30) =>request_signal(30), +-- request(31) =>request_signal(31), +-- request(32) =>request_signal(32) +--); +-- +--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(3), +-- data_in_en => data_in_en(3), +-- reset => reset, +-- clk =>clk, +-- grant(33) => grant_signal(33), +-- grant(34) => grant_signal(34), +-- grant(35) => grant_signal(35), +-- grant(36) => grant_signal(36), +-- grant(37) => grant_signal(37), +-- grant(38) => grant_signal(38), +-- grant(39) => grant_signal(39), +-- grant(40) => grant_signal(40), +-- grant(41) => grant_signal(41), +-- grant(42) => grant_signal(42), +-- grant(43) => grant_signal(43), +-- grant(44) => grant_signal(44), +-- grant(45) => grant_signal(45), +-- grant(46) => grant_signal(46), +-- grant(47) => grant_signal(47), +-- grant(48) => grant_signal(48), +-- fifo_full =>fifo_in_full(3), +-- priority_rotation => priority_rotation_signal(3), +-- fifo_empty => fifo_in_empty(3), +-- data_out =>crossbar_in_port3, +-- data_out_pulse =>crossbar_in_pulse(3, +-- request(33) =>request_signal(33), +-- request(34) =>request_signal(34), +-- request(35) =>request_signal(35), +-- request(36) =>request_signal(36), +-- request(37) =>request_signal(37), +-- request(38) =>request_signal(38), +-- request(39) =>request_signal(39), +-- request(40) =>request_signal(40), +-- request(41) =>request_signal(41), +-- request(42) =>request_signal(42), +-- request(43) =>request_signal(43), +-- request(44) =>request_signal(44), +-- request(45) =>request_signal(45), +-- request(46) =>request_signal(46), +-- request(47) =>request_signal(47), +-- request(48) =>request_signal(48) +--); +-- +--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(4), +-- data_in_en => data_in_en(4), +-- reset => reset, +-- clk =>clk, +-- grant(49) => grant_signal(49), +-- grant(50) => grant_signal(50), +-- grant(51) => grant_signal(51), +-- grant(52) => grant_signal(52), +-- grant(53) => grant_signal(53), +-- grant(54) => grant_signal(54), +-- grant(55) => grant_signal(55), +-- grant(56) => grant_signal(56), +-- grant(57) => grant_signal(57), +-- grant(58) => grant_signal(58), +-- grant(59) => grant_signal(59), +-- grant(60) => grant_signal(60), +-- grant(61) => grant_signal(61), +-- grant(62) => grant_signal(62), +-- grant(63) => grant_signal(63), +-- grant(64) => grant_signal(64), +-- fifo_full =>fifo_in_full(4), +-- priority_rotation => priority_rotation_signal(4), +-- fifo_empty => fifo_in_empty(4), +-- data_out =>crossbar_in_port(4), +-- data_out_pulse =>crossbar_in_pulse(4, +-- request(49) =>request_signal(49), +-- request(50) =>request_signal(50), +-- request(51) =>request_signal(51), +-- request(52) =>request_signal(52), +-- request(53) =>request_signal(53), +-- request(54) =>request_signal(54), +-- request(55) =>request_signal(55), +-- request(56) =>request_signal(56), +-- request(57) =>request_signal(57), +-- request(58) =>request_signal(58), +-- request(59) =>request_signal(59), +-- request(60) =>request_signal(60), +-- request(61) =>request_signal(61), +-- request(62) =>request_signal(62), +-- request(63) =>request_signal(63), +-- request(64) =>request_signal(64) +--); +-- +--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(5), +-- data_in_en => data_in_en(5), +-- reset => reset, +-- clk =>clk, +-- grant(65) => grant_signal(65), +-- grant(66) => grant_signal(66), +-- grant(67) => grant_signal(67), +-- grant(68) => grant_signal(68), +-- grant(69) => grant_signal(69), +-- grant(70) => grant_signal(70), +-- grant(71) => grant_signal(71), +-- grant(72) => grant_signal(72), +-- grant(73) => grant_signal(73), +-- grant(74) => grant_signal(74), +-- grant(75) => grant_signal(75), +-- grant(76) => grant_signal(76), +-- grant(77) => grant_signal(77), +-- grant(78) => grant_signal(78), +-- grant(79) => grant_signal(79), +-- grant(80) => grant_signal(80), +-- fifo_full =>fifo_in_full(5), +-- priority_rotation => priority_rotation_signal(5), +-- fifo_empty => fifo_in_empty(5), +-- data_out =>crossbar_in_port(5), +-- data_out_pulse =>crossbar_in_pulse(5, +-- request(65) =>request_signal(65), +-- request(66) =>request_signal(66), +-- request(67) =>request_signal(67), +-- request(68) =>request_signal(68), +-- request(69) =>request_signal(69), +-- request(70) =>request_signal(70), +-- request(71) =>request_signal(71), +-- request(72) =>request_signal(72), +-- request(73) =>request_signal(73), +-- request(74) =>request_signal(74), +-- request(75) =>request_signal(75), +-- request(76) =>request_signal(76), +-- request(77) =>request_signal(77), +-- request(78) =>request_signal(78), +-- request(79) =>request_signal(79), +-- request(80) =>request_signal(80) +--); +-- +--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(6), +-- data_in_en => data_in_en(6), +-- reset => reset, +-- clk =>clk, +-- grant(81) => grant_signal(81), +-- grant(82) => grant_signal(82), +-- grant(83) => grant_signal(83), +-- grant(84) => grant_signal(84), +-- grant(85) => grant_signal(85), +-- grant(86) => grant_signal(86), +-- grant(87) => grant_signal(87), +-- grant(88) => grant_signal(88), +-- grant(89) => grant_signal(89), +-- grant(90) => grant_signal(90), +-- grant(91) => grant_signal(91), +-- grant(92) => grant_signal(92), +-- grant(93) => grant_signal(93), +-- grant(94) => grant_signal(94), +-- grant(95) => grant_signal(95), +-- grant(96) => grant_signal(96), +-- fifo_full =>fifo_in_full(6), +-- priority_rotation => priority_rotation_signal(6), +-- fifo_empty => fifo_in_empty(6), +-- data_out =>crossbar_in_port(6), +-- data_out_pulse =>crossbar_in_pulse(6, +-- request(81) =>request_signal(81), +-- request(82) =>request_signal(82), +-- request(83) =>request_signal(83), +-- request(84) =>request_signal(84), +-- request(85) =>request_signal(85), +-- request(86) =>request_signal(86), +-- request(87) =>request_signal(87), +-- request(88) =>request_signal(88), +-- request(89) =>request_signal(89), +-- request(90) =>request_signal(90), +-- request(91) =>request_signal(91), +-- request(92) =>request_signal(92), +-- request(93) =>request_signal(93), +-- request(94) =>request_signal(94), +-- request(95) =>request_signal(95), +-- request(96) =>request_signal(96) +--); +-- +--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(7), +-- data_in_en => data_in_en(7), +-- reset => reset, +-- clk =>clk, +-- grant(97) => grant_signal(97), +-- grant(98) => grant_signal(98), +-- grant(99) => grant_signal(99), +-- grant(0) => grant_signal(100), +-- grant(1) => grant_signal(101), +-- grant(2) => grant_signal(102), +-- grant(3) => grant_signal(103), +-- grant(4) => grant_signal(104), +-- grant(5) => grant_signal(105), +-- grant(6) => grant_signal(106), +-- grant(7) => grant_signal(107), +-- grant(8) => grant_signal(108), +-- grant(9) => grant_signal(109), +-- grant(110) => grant_signal(110), +-- grant(111) => grant_signal(111), +-- grant(112) => grant_signal(112), +-- fifo_full =>fifo_in_full(7), +-- priority_rotation => priority_rotation_signal(7), +-- fifo_empty => fifo_in_empty(7), +-- data_out =>crossbar_in_port(8), +-- data_out_pulse =>crossbar_in_pulse(7, +-- request(97) =>request_signal(97), +-- request(98) =>request_signal(98), +-- request(99) =>request_signal(99), +-- request(100) =>request_signal(100), +-- request(101) =>request_signal(101), +-- request(102) =>request_signal(102), +-- request(103) =>request_signal(103), +-- request(104) =>request_signal(104), +-- request(105) =>request_signal(105), +-- request(106) =>request_signal(106), +-- request(107) =>request_signal(107), +-- request(108) =>request_signal(108), +-- request(109) =>request_signal(109), +-- request(110) =>request_signal(110), +-- request(111) =>request_signal(111), +-- request(112) =>request_signal(112) +--); +-- +--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(8), +-- data_in_en => data_in_en(8), +-- reset => reset, +-- clk =>clk, +-- grant(113) => grant_signal(113), +-- grant(114) => grant_signal(114), +-- grant(115) => grant_signal(115), +-- grant(116) => grant_signal(116), +-- grant(117) => grant_signal(117), +-- grant(118) => grant_signal(118), +-- grant(119) => grant_signal(119), +-- grant(120) => grant_signal(120), +-- grant(121) => grant_signal(121), +-- grant(122) => grant_signal(122), +-- grant(123) => grant_signal(123), +-- grant(124) => grant_signal(124), +-- grant(125) => grant_signal(125), +-- grant(126) => grant_signal(126), +-- grant(127) => grant_signal(127), +-- grant(128) => grant_signal(128), +-- fifo_full =>fifo_in_full(8), +-- priority_rotation => priority_rotation_signal(8), +-- fifo_empty => fifo_in_empty(8), +-- data_out =>crossbar_in_port8, +-- data_out_pulse =>crossbar_in_pulse(8, +-- request(113) =>request_signal(113), +-- request(114) =>request_signal(114), +-- request(115) =>request_signal(115), +-- request(116) =>request_signal(116), +-- request(117) =>request_signal(117), +-- request(118) =>request_signal(118), +-- request(119) =>request_signal(119), +-- request(120) =>request_signal(120), +-- request(121) =>request_signal(121), +-- request(122) =>request_signal(122), +-- request(123) =>request_signal(123), +-- request(124) =>request_signal(124), +-- request(125) =>request_signal(125), +-- request(126) =>request_signal(126), +-- request(127) =>request_signal(127), +-- request(128) =>request_signal(128) +--); +-- +--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(9), +-- data_in_en => data_in_en(9), +-- reset => reset, +-- clk =>clk, +-- grant(129) => grant_signal(129), +-- grant(130) => grant_signal(130), +-- grant(131) => grant_signal(131), +-- grant(132) => grant_signal(132), +-- grant(133) => grant_signal(133), +-- grant(134) => grant_signal(134), +-- grant(135) => grant_signal(135), +-- grant(136) => grant_signal(136), +-- grant(137) => grant_signal(137), +-- grant(138) => grant_signal(138), +-- grant(139) => grant_signal(139), +-- grant(140) => grant_signal(140), +-- grant(141) => grant_signal(141), +-- grant(142) => grant_signal(142), +-- grant(143) => grant_signal(143), +-- grant(144) => grant_signal(144), +-- fifo_full =>fifo_in_full(9), +-- priority_rotation => priority_rotation_signal(9), +-- fifo_empty => fifo_in_empty(9), +-- data_out =>crossbar_in_port9, +-- data_out_pulse =>crossbar_in_pulse(9), +-- request(129) =>request_signal(129), +-- request(130) =>request_signal(130), +-- request(131) =>request_signal(131), +-- request(132) =>request_signal(132), +-- request(133) =>request_signal(133), +-- request(134) =>request_signal(134), +-- request(135) =>request_signal(135), +-- request(136) =>request_signal(136), +-- request(137) =>request_signal(137), +-- request(138) =>request_signal(138), +-- request(139) =>request_signal(139), +-- request(140) =>request_signal(140), +-- request(141) =>request_signal(141), +-- request(142) =>request_signal(142), +-- request(143) =>request_signal(143), +-- request(144) =>request_signal(144) +--); +-- +--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(10), +-- data_in_en => data_in_en(10), +-- reset => reset, +-- clk =>clk, +-- grant(145) => grant_signal(145), +-- grant(146) => grant_signal(146), +-- grant(147) => grant_signal(147), +-- grant(148) => grant_signal(148), +-- grant(149) => grant_signal(149), +-- grant(150) => grant_signal(150), +-- grant(151) => grant_signal(151), +-- grant(152) => grant_signal(152), +-- grant(153) => grant_signal(153), +-- grant(154) => grant_signal(154), +-- grant(155) => grant_signal(155), +-- grant(156) => grant_signal(156), +-- grant(157) => grant_signal(157), +-- grant(158) => grant_signal(158), +-- grant(159) => grant_signal(159), +-- grant(160) => grant_signal(160), +-- fifo_full =>fifo_in_full(10), +-- priority_rotation => priority_rotation_signal(10), +-- fifo_empty => fifo_in_empty(10), +-- data_out =>crossbar_in_port(10), +-- data_out_pulse =>crossbar_in_pulse(10), +-- request(145) =>request_signal(145), +-- request(146) =>request_signal(146), +-- request(147) =>request_signal(147), +-- request(148) =>request_signal(148), +-- request(149) =>request_signal(149), +-- request(150) =>request_signal(150), +-- request(151) =>request_signal(151), +-- request(152) =>request_signal(152), +-- request(153) =>request_signal(153), +-- request(154) =>request_signal(154), +-- request(155) =>request_signal(155), +-- request(156) =>request_signal(156), +-- request(157) =>request_signal(157), +-- request(158) =>request_signal(158), +-- request(159) =>request_signal(159), +-- request(160) =>request_signal(160) +--); +-- +--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(11), +-- data_in_en => data_in_en(11), +-- reset => reset, +-- clk =>clk, +-- grant(161) => grant_signal(161), +-- grant(162) => grant_signal(162), +-- grant(163) => grant_signal(163), +-- grant(164) => grant_signal(164), +-- grant(165) => grant_signal(165), +-- grant(166) => grant_signal(166), +-- grant(167) => grant_signal(167), +-- grant(168) => grant_signal(168), +-- grant(169) => grant_signal(169), +-- grant(170) => grant_signal(170), +-- grant(171) => grant_signal(171), +-- grant(172) => grant_signal(172), +-- grant(173) => grant_signal(173), +-- grant(174) => grant_signal(174), +-- grant(175) => grant_signal(175), +-- grant(176) => grant_signal(176), +-- fifo_full =>fifo_in_full(11), +-- priority_rotation => priority_rotation_signal(11), +-- fifo_empty => fifo_in_empty(11), +-- data_out =>crossbar_in_port(11), +-- data_out_pulse =>crossbar_in_pulse(11), +-- request(161) =>request_signal(161), +-- request(162) =>request_signal(162), +-- request(163) =>request_signal(163), +-- request(164) =>request_signal(164), +-- request(165) =>request_signal(165), +-- request(166) =>request_signal(166), +-- request(167) =>request_signal(167), +-- request(168) =>request_signal(168), +-- request(169) =>request_signal(169), +-- request(170) =>request_signal(170), +-- request(171) =>request_signal(171), +-- request(172) =>request_signal(172), +-- request(173) =>request_signal(173), +-- request(174) =>request_signal(174), +-- request(175) =>request_signal(175), +-- request(176) =>request_signal(176) +--); +-- +--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(12), +-- data_in_en => data_in_en(12), +-- reset => reset, +-- clk =>clk, +-- grant(177) => grant_signal(177), +-- grant(178) => grant_signal(178), +-- grant(179) => grant_signal(179), +-- grant(180) => grant_signal(180), +-- grant(181) => grant_signal(181), +-- grant(182) => grant_signal(182), +-- grant(183) => grant_signal(183), +-- grant(184) => grant_signal(184), +-- grant(185) => grant_signal(185), +-- grant(186) => grant_signal(186), +-- grant(187) => grant_signal(187), +-- grant(188) => grant_signal(188), +-- grant(189) => grant_signal(189), +-- grant(190) => grant_signal(190), +-- grant(191) => grant_signal(191), +-- grant(192) => grant_signal(192), +-- fifo_full =>fifo_in_full(12), +-- priority_rotation => priority_rotation_signal(12), +-- fifo_empty => fifo_in_empty(12), +-- data_out =>crossbar_in_port(12), +-- data_out_pulse =>crossbar_in_pulse(12), +-- request(177) =>request_signal(177), +-- request(178) =>request_signal(178), +-- request(179) =>request_signal(179), +-- request(180) =>request_signal(180), +-- request(181) =>request_signal(181), +-- request(182) =>request_signal(182), +-- request(183) =>request_signal(183), +-- request(184) =>request_signal(184), +-- request(185) =>request_signal(185), +-- request(186) =>request_signal(186), +-- request(187) =>request_signal(187), +-- request(188) =>request_signal(188), +-- request(189) =>request_signal(189), +-- request(190) =>request_signal(190), +-- request(191) =>request_signal(191), +-- request(192) =>request_signal(192) +--); +-- +--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(13), +-- data_in_en => data_in_en(13), +-- reset => reset, +-- clk =>clk, +-- grant(193) => grant_signal(193), +-- grant(194) => grant_signal(194), +-- grant(195) => grant_signal(195), +-- grant(196) => grant_signal(196), +-- grant(197) => grant_signal(197), +-- grant(198) => grant_signal(198), +-- grant(199) => grant_signal(199), +-- grant(200) => grant_signal(200), +-- grant(201) => grant_signal(201), +-- grant(202) => grant_signal(202), +-- grant(203) => grant_signal(203), +-- grant(204) => grant_signal(204), +-- grant(205) => grant_signal(205), +-- grant(206) => grant_signal(206), +-- grant(207) => grant_signal(207), +-- grant(208) => grant_signal(208), +-- fifo_full =>fifo_in_full(13), +-- priority_rotation => priority_rotation_signal(13), +-- fifo_empty => fifo_in_empty(13), +-- data_out =>crossbar_in_port13, +-- data_out_pulse =>crossbar_in_pulse(13, +-- request(193) =>request_signal(193), +-- request(194) =>request_signal(194), +-- request(195) =>request_signal(195), +-- request(196) =>request_signal(196), +-- request(197) =>request_signal(197), +-- request(198) =>request_signal(198), +-- request(199) =>request_signal(199), +-- request(200) =>request_signal(200), +-- request(201) =>request_signal(201), +-- request(202) =>request_signal(202), +-- request(203) =>request_signal(203), +-- request(204) =>request_signal(204), +-- request(205) =>request_signal(205), +-- request(206) =>request_signal(206), +-- request(207) =>request_signal(207), +-- request(208) =>request_signal(208) +--); +-- +--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(14), +-- data_in_en => data_in_en(14), +-- reset => reset, +-- clk =>clk, +-- grant(209) => grant_signal(209), +-- grant(210) => grant_signal(210), +-- grant(211) => grant_signal(211), +-- grant(212) => grant_signal(212), +-- grant(213) => grant_signal(213), +-- grant(214) => grant_signal(214), +-- grant(215) => grant_signal(215), +-- grant(216) => grant_signal(216), +-- grant(217) => grant_signal(217), +-- grant(218) => grant_signal(218), +-- grant(219) => grant_signal(219), +-- grant(220) => grant_signal(220), +-- grant(221) => grant_signal(221), +-- grant(222) => grant_signal(222), +-- grant(223) => grant_signal(223), +-- grant(224) => grant_signal(224), +-- fifo_full =>fifo_in_full(14), +-- priority_rotation => priority_rotation_signal(14), +-- fifo_empty => fifo_in_empty(14), +-- data_out =>crossbar_in_port(14), +-- data_out_pulse =>crossbar_in_pulse(14), +-- request(209) =>request_signal(209), +-- request(210) =>request_signal(210), +-- request(211) =>request_signal(211), +-- request(212) =>request_signal(212), +-- request(213) =>request_signal(213), +-- request(214) =>request_signal(214), +-- request(215) =>request_signal(215), +-- request(216) =>request_signal(216), +-- request(217) =>request_signal(217), +-- request(218) =>request_signal(218), +-- request(219) =>request_signal(219), +-- request(220) =>request_signal(220), +-- request(221) =>request_signal(221), +-- request(222) =>request_signal(222), +-- request(223) =>request_signal(223), +-- request(224) =>request_signal(224) +--); +-- +--PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(15), +-- data_in_en => data_in_en(15), +-- reset => reset, +-- clk =>clk, +-- grant(225) => grant_signal(225), +-- grant(226) => grant_signal(226), +-- grant(227) => grant_signal(227), +-- grant(228) => grant_signal(228), +-- grant(229) => grant_signal(229), +-- grant(230) => grant_signal(230), +-- grant(231) => grant_signal(231), +-- grant(232) => grant_signal(232), +-- grant(233) => grant_signal(233), +-- grant(234) => grant_signal(234), +-- grant(235) => grant_signal(235), +-- grant(236) => grant_signal(236), +-- grant(237) => grant_signal(237), +-- grant(238) => grant_signal(238), +-- grant(239) => grant_signal(239), +-- grant(240) => grant_signal(240), +-- fifo_full =>fifo_in_full(15), +-- priority_rotation => priority_rotation_signal(15), +-- fifo_empty => fifo_in_empty(15), +-- data_out =>crossbar_in_port(15), +-- data_out_pulse =>crossbar_in_pulse(15), +-- request(225) =>request_signal(225), +-- request(226) =>request_signal(226), +-- request(227) =>request_signal(227), +-- request(228) =>request_signal(228), +-- request(229) =>request_signal(229), +-- request(230) =>request_signal(230), +-- request(231) =>request_signal(231), +-- request(232) =>request_signal(232), +-- request(233) =>request_signal(233), +-- request(234) =>request_signal(234), +-- request(235) =>request_signal(235), +-- request(236) =>request_signal(236), +-- request(237) =>request_signal(237), +-- request(238) =>request_signal(238), +-- request(239) =>request_signal(239), +-- request(240) =>request_signal(240) +--); +-- +--PORT16_INPUT_PORT_MODULE: INPUT_PORT_MODULE +--GENERIC MAP(number_of_ports =>16) +--PORT MAP( +-- data_in => Port_in(16), +-- data_in_en => data_in_en(16), +-- reset => reset, +-- clk =>clk, +-- grant(241) => grant_signal(241), +-- grant(242) => grant_signal(242), +-- grant(243) => grant_signal(243), +-- grant(244) => grant_signal(244), +-- grant(245) => grant_signal(245), +-- grant(246) => grant_signal(246), +-- grant(247) => grant_signal(247), +-- grant(248) => grant_signal(248), +-- grant(249) => grant_signal(249), +-- grant(250) => grant_signal(250), +-- grant(251) => grant_signal(251), +-- grant(252) => grant_signal(252), +-- grant(253) => grant_signal(253), +-- grant(254) => grant_signal(254), +-- grant(255) => grant_signal(255), +-- grant(256) => grant_signal(256), +-- fifo_full =>fifo_in_full(16), +-- priority_rotation => priority_rotation_signal(16), +-- fifo_empty => fifo_in_empty(16), +-- data_out =>crossbar_in_port(16), +-- data_out_pulse =>crossbar_in_pulse(16), +-- request(241) =>request_signal(241), +-- request(242) =>request_signal(242), +-- request(243) =>request_signal(243), +-- request(244) =>request_signal(244), +-- request(245) =>request_signal(245), +-- request(246) =>request_signal(246), +-- request(247) =>request_signal(247), +-- request(248) =>request_signal(248), +-- request(249) =>request_signal(249), +-- request(250) =>request_signal(250), +-- request(251) =>request_signal(251), +-- request(252) =>request_signal(252), +-- request(253) =>request_signal(253), +-- request(254) =>request_signal(254), +-- request(255) =>request_signal(255), +-- request(256) =>request_signal(256) +--); +-- +--end generate switch16x16; +-- intstanciation et connexion des modules des ports de sorties fonction du nombre de ports +-- le circuit genere depend du parametre generique nombre de ports +-- switch 2 ports +port_out_switch2x2 : if number_of_ports = 2 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(1), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(1), + data_out =>Port_out(1), + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(2), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(2), + data_out =>Port_out(2), + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +end generate port_out_switch2x2; + + +-- switch 3 ports +port_out_switch3x3 : if number_of_ports = 3 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(1), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(1), + data_out =>Port_out(1), + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(2), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(2), + data_out =>Port_out(2), + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(3), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(3), + data_out =>Port_out(3), + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +end generate port_out_switch3x3; + + +-- switch 4 ports +port_out_switch4x4 : if number_of_ports = 4 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(1), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(1), + data_out =>Port_out(1), + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(2), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(2), + data_out =>Port_out(2), + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(3), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(3), + data_out =>Port_out(3), + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(4), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(4), + data_out =>Port_out(4), + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +end generate port_out_switch4x4; + + +-- switch 5 ports +port_out_switch5x5 : if number_of_ports = 5 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(1), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(1), + data_out =>Port_out(1), + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(2), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(2), + data_out =>Port_out(2), + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(3), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(3), + data_out =>Port_out(3), + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(4), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(4), + data_out =>Port_out(4), + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(5), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(5), + data_out =>Port_out(5), + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +end generate port_out_switch5x5; + + +-- switch 6 ports +port_out_switch6x6 : if number_of_ports = 6 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(1), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(1), + data_out =>Port_out(1), + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(2), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(2), + data_out =>Port_out(2), + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(3), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(3), + data_out =>Port_out(3), + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(4), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(4), + data_out =>Port_out(4), + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(5), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(5), + data_out =>Port_out(5), + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(6), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(6), + data_out =>Port_out(6), + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +end generate port_out_switch6x6; + + +-- switch 7 ports +port_out_switch7x7 : if number_of_ports = 7 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(1), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(1), + data_out =>Port_out(1), + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(2), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(2), + data_out =>Port_out(2), + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(3), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(3), + data_out =>Port_out(3), + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(4), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(4), + data_out =>Port_out(4), + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(5), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(5), + data_out =>Port_out(5), + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(6), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(6), + data_out =>Port_out(6), + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(7), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(7), + data_out =>Port_out(7), + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +end generate port_out_switch7x7; + + +-- switch 8 ports +port_out_switch8x8 : if number_of_ports = 8 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(1), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(1), + data_out =>Port_out(1), + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(2), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(2), + data_out =>Port_out(2), + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(3), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(3), + data_out =>Port_out(3), + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(4), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(4), + data_out =>Port_out(4), + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(5), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(5), + data_out =>Port_out(5), + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(6), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(6), + data_out =>Port_out(6), + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(7), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(7), + data_out =>Port_out(7), + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(8), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(8), + data_out =>Port_out(8), + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +end generate port_out_switch8x8; + + +-- switch 9 ports +port_out_switch9x9 : if number_of_ports = 9 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(1), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(1), + data_out =>Port_out(1), + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(2), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(2), + data_out =>Port_out(2), + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(3), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(3), + data_out =>Port_out(3), + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(4), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(4), + data_out =>Port_out(4), + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(5), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(5), + data_out =>Port_out(5), + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(6), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(6), + data_out =>Port_out(6), + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(7), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(7), + data_out =>Port_out(7), + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(8), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(8), + data_out =>Port_out(8), + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(9), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(9), + data_out =>Port_out(9), + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +end generate port_out_switch9x9; + + +-- switch 10 ports +port_out_switch10x10 : if number_of_ports = 10 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(1), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(1), + data_out =>Port_out(1), + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(2), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(2), + data_out =>Port_out(2), + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(3), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(3), + data_out =>Port_out(3), + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(4), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(4), + data_out =>Port_out(4), + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(5), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(5), + data_out =>Port_out(5), + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(6), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(6), + data_out =>Port_out(6), + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(7), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(7), + data_out =>Port_out(7), + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(8), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(8), + data_out =>Port_out(8), + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(9), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(9), + data_out =>Port_out(9), + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(10), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(10), + data_out =>Port_out(10), + fifo_full =>fifo_out_full_signal(10), + data_avalaible => data_available(10), + rd_out_en => data_out_en(10) + ); + +end generate port_out_switch10x10; + + +-- switch 11 ports +port_out_switch11x11 : if number_of_ports = 11 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(1), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(1), + data_out =>Port_out(1), + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(2), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(2), + data_out =>Port_out(2), + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(3), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(3), + data_out =>Port_out(3), + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(4), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(4), + data_out =>Port_out(4), + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(5), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(5), + data_out =>Port_out(5), + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(6), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(6), + data_out =>Port_out(6), + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(7), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(7), + data_out =>Port_out(7), + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(8), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(8), + data_out =>Port_out(8), + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(9), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(9), + data_out =>Port_out(9), + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(10), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(10), + data_out =>Port_out(10), + fifo_full =>fifo_out_full_signal(10), + data_avalaible => data_available(10), + rd_out_en => data_out_en(10) + ); + +PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(11), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(11), + data_out =>Port_out(11), + fifo_full =>fifo_out_full_signal(11), + data_avalaible => data_available(11), + rd_out_en => data_out_en(11) + ); + +end generate port_out_switch11x11; + + +-- switch 12 ports +port_out_switch12x12 : if number_of_ports = 12 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(1), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(1), + data_out =>Port_out(1), + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(2), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(2), + data_out =>Port_out(2), + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(3), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(3), + data_out =>Port_out(3), + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(4), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(4), + data_out =>Port_out(4), + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(5), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(5), + data_out =>Port_out(5), + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(6), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(6), + data_out =>Port_out(6), + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(7), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(7), + data_out =>Port_out(7), + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(8), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(8), + data_out =>Port_out(8), + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(9), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(9), + data_out =>Port_out(9), + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(10), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(10), + data_out =>Port_out(10), + fifo_full =>fifo_out_full_signal(10), + data_avalaible => data_available(10), + rd_out_en => data_out_en(10) + ); + +PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(11), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(11), + data_out =>Port_out(11), + fifo_full =>fifo_out_full_signal(11), + data_avalaible => data_available(11), + rd_out_en => data_out_en(11) + ); + +PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(12), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(12), + data_out =>Port_out(12), + fifo_full =>fifo_out_full_signal(12), + data_avalaible => data_available(12), + rd_out_en => data_out_en(12) + ); + +end generate port_out_switch12x12; + + +-- switch 13 ports +port_out_switch13x13 : if number_of_ports = 13 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(1), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(1), + data_out =>Port_out(1), + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(2), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(2), + data_out =>Port_out(2), + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(3), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(3), + data_out =>Port_out(3), + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(4), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(4), + data_out =>Port_out(4), + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(5), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(5), + data_out =>Port_out(5), + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(6), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(6), + data_out =>Port_out(6), + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(7), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(7), + data_out =>Port_out(7), + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(8), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(8), + data_out =>Port_out(8), + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(9), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(9), + data_out =>Port_out(9), + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(10), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(10), + data_out =>Port_out(10), + fifo_full =>fifo_out_full_signal(10), + data_avalaible => data_available(10), + rd_out_en => data_out_en(10) + ); + +PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(11), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(11), + data_out =>Port_out(11), + fifo_full =>fifo_out_full_signal(11), + data_avalaible => data_available(11), + rd_out_en => data_out_en(11) + ); + +PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(12), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(12), + data_out =>Port_out(12), + fifo_full =>fifo_out_full_signal(12), + data_avalaible => data_available(12), + rd_out_en => data_out_en(12) + ); + +PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(13), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(13), + data_out =>Port_out(13), + fifo_full =>fifo_out_full_signal(13), + data_avalaible => data_available(13), + rd_out_en => data_out_en(13) + ); + +end generate port_out_switch13x13; + + +-- switch 14 ports +port_out_switch14x14 : if number_of_ports = 14 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(1), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(1), + data_out =>Port_out(1), + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(2), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(2), + data_out =>Port_out(2), + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(3), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(3), + data_out =>Port_out(3), + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(4), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(4), + data_out =>Port_out(4), + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(5), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(5), + data_out =>Port_out(5), + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(6), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(6), + data_out =>Port_out(6), + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(7), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(7), + data_out =>Port_out(7), + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(8), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(8), + data_out =>Port_out(8), + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(9), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(9), + data_out =>Port_out(9), + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(10), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(10), + data_out =>Port_out(10), + fifo_full =>fifo_out_full_signal(10), + data_avalaible => data_available(10), + rd_out_en => data_out_en(10) + ); + +PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(11), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(11), + data_out =>Port_out(11), + fifo_full =>fifo_out_full_signal(11), + data_avalaible => data_available(11), + rd_out_en => data_out_en(11) + ); + +PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(12), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(12), + data_out =>Port_out(12), + fifo_full =>fifo_out_full_signal(12), + data_avalaible => data_available(12), + rd_out_en => data_out_en(12) + ); + +PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(13), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(13), + data_out =>Port_out(13), + fifo_full =>fifo_out_full_signal(13), + data_avalaible => data_available(13), + rd_out_en => data_out_en(13) + ); + +PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(14), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(14), + data_out =>Port_out(14), + fifo_full =>fifo_out_full_signal(14), + data_avalaible => data_available(14), + rd_out_en => data_out_en(14) + ); + +end generate port_out_switch14x14; + + +-- switch 15 ports +port_out_switch15x15 : if number_of_ports = 15 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(1), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(1), + data_out =>Port_out(1), + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(2), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(2), + data_out =>Port_out(2), + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(3), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(3), + data_out =>Port_out(3), + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(4), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(4), + data_out =>Port_out(4), + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(5), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(5), + data_out =>Port_out(5), + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(6), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(6), + data_out =>Port_out(6), + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(7), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(7), + data_out =>Port_out(7), + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(8), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(8), + data_out =>Port_out(8), + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(9), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(9), + data_out =>Port_out(9), + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(10), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(10), + data_out =>Port_out(10), + fifo_full =>fifo_out_full_signal(10), + data_avalaible => data_available(10), + rd_out_en => data_out_en(10) + ); + +PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(11), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(11), + data_out =>Port_out(11), + fifo_full =>fifo_out_full_signal(11), + data_avalaible => data_available(11), + rd_out_en => data_out_en(11) + ); + +PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(12), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(12), + data_out =>Port_out(12), + fifo_full =>fifo_out_full_signal(12), + data_avalaible => data_available(12), + rd_out_en => data_out_en(12) + ); + +PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(13), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(13), + data_out =>Port_out(13), + fifo_full =>fifo_out_full_signal(13), + data_avalaible => data_available(13), + rd_out_en => data_out_en(13) + ); + +PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(14), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(14), + data_out =>Port_out(14), + fifo_full =>fifo_out_full_signal(14), + data_avalaible => data_available(14), + rd_out_en => data_out_en(14) + ); + +PORT15_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(15), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(15), + data_out =>Port_out(15), + fifo_full =>fifo_out_full_signal(15), + data_avalaible => data_available(15), + rd_out_en => data_out_en(15) + ); + +end generate port_out_switch15x15; + + +-- switch 16 ports +port_out_switch16x16 : if number_of_ports = 16 generate +port_out_switch_16x16:for i in 1 to number_of_ports generate + begin + PORTx16_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port(i), + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse(i), + data_out =>Port_out(i), + fifo_full =>fifo_out_full_signal(i), + data_avalaible => data_available(i), + rd_out_en => data_out_en(i) + ); +end generate port_out_switch_16x16; + +end generate port_out_switch16x16; + +-- intstanciation et connexion des crossbars du switch en fonction du nombre de ports +-- le circuit genere depend du parametre generique nombre de ports +-- switch 2 ports +crossbar_switch2x2 : if number_of_ports = 2 generate + +Switch_Crossbar2_2: Crossbar +GENERIC MAP(number_of_crossbar_ports =>2) + PORT MAP( + reset => reset, + clk => clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => "00000000", + Port4_in => "00000000", + Port5_in => "00000000", + Port6_in => "00000000", + Port7_in => "00000000", + Port8_in => "00000000", + Port9_in => "00000000", + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in =>'0' , + Port4_pulse_in =>'0' , + Port5_pulse_in =>'0' , + Port6_pulse_in =>'0' , + Port7_pulse_in =>'0' , + Port8_pulse_in =>'0' , + Port9_pulse_in =>'0' , + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Ctrl => Grant_signal); +end generate crossbar_switch2x2; + + +-- switch 3 ports +crossbar_switch3x3 : if number_of_ports = 3 generate + +Switch_Crossbar3_3: Crossbar +GENERIC MAP(number_of_crossbar_ports =>3) + PORT MAP( + reset => reset, + clk => clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => crossbar_in_port(3), + Port4_in => "00000000", + Port5_in => "00000000", + Port6_in => "00000000", + Port7_in => "00000000", + Port8_in => "00000000", + Port9_in => "00000000", + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in => crossbar_in_pulse(3), + Port4_pulse_in =>'0' , + Port5_pulse_in =>'0' , + Port6_pulse_in =>'0' , + Port7_pulse_in =>'0' , + Port8_pulse_in =>'0' , + Port9_pulse_in =>'0' , + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port3_pulse_out => crossbar_out_pulse(3), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Port3_out => crossbar_out_port(3), + Ctrl => Grant_signal); +end generate crossbar_switch3x3; + + +-- switch 4 ports +crossbar_switch4x4 : if number_of_ports = 4 generate + +Switch_Crossbar4_4: Crossbar +GENERIC MAP(number_of_crossbar_ports =>4) + PORT MAP( + reset => reset, + clk => clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => crossbar_in_port(3), + Port4_in => crossbar_in_port(4), + Port5_in => "00000000", + Port6_in => "00000000", + Port7_in => "00000000", + Port8_in => "00000000", + Port9_in => "00000000", + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in => crossbar_in_pulse(3), + Port4_pulse_in => crossbar_in_pulse(4), + Port5_pulse_in =>'0' , + Port6_pulse_in =>'0' , + Port7_pulse_in =>'0' , + Port8_pulse_in =>'0' , + Port9_pulse_in =>'0' , + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port3_pulse_out => crossbar_out_pulse(3), + Port4_pulse_out => crossbar_out_pulse(4), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Port3_out => crossbar_out_port(3), + Port4_out => crossbar_out_port(4), + Ctrl => Grant_signal); +end generate crossbar_switch4x4; + + +-- switch 5 ports +crossbar_switch5x5 : if number_of_ports = 5 generate + +Switch_Crossbar5_5: Crossbar +GENERIC MAP(number_of_crossbar_ports =>5) + PORT MAP( + reset => reset, + clk => clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => crossbar_in_port(3), + Port4_in => crossbar_in_port(4), + Port5_in => crossbar_in_port(5), + Port6_in => "00000000", + Port7_in => "00000000", + Port8_in => "00000000", + Port9_in => "00000000", + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in => crossbar_in_pulse(3), + Port4_pulse_in => crossbar_in_pulse(4), + Port5_pulse_in => crossbar_in_pulse(5), + Port6_pulse_in =>'0' , + Port7_pulse_in =>'0' , + Port8_pulse_in =>'0' , + Port9_pulse_in =>'0' , + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port3_pulse_out => crossbar_out_pulse(3), + Port4_pulse_out => crossbar_out_pulse(4), + Port5_pulse_out => crossbar_out_pulse(5), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Port3_out => crossbar_out_port(3), + Port4_out => crossbar_out_port(4), + Port5_out => crossbar_out_port(5), + Ctrl => Grant_signal); +end generate crossbar_switch5x5; + + +-- switch 6 ports +crossbar_switch6x6 : if number_of_ports = 6 generate + +Switch_Crossbar6_6: Crossbar +GENERIC MAP(number_of_crossbar_ports =>6) + PORT MAP( + + reset => reset, + clk => clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => crossbar_in_port(3), + Port4_in => crossbar_in_port(4), + Port5_in => crossbar_in_port(5), + Port6_in => crossbar_in_port(6), + Port7_in => "00000000", + Port8_in => "00000000", + Port9_in => "00000000", + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in => crossbar_in_pulse(3), + Port4_pulse_in => crossbar_in_pulse(4), + Port5_pulse_in => crossbar_in_pulse(5), + Port6_pulse_in => crossbar_in_pulse(6), + Port7_pulse_in =>'0' , + Port8_pulse_in =>'0' , + Port9_pulse_in =>'0' , + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port3_pulse_out => crossbar_out_pulse(3), + Port4_pulse_out => crossbar_out_pulse(4), + Port5_pulse_out => crossbar_out_pulse(5), + Port6_pulse_out => crossbar_out_pulse(6), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Port3_out => crossbar_out_port(3), + Port4_out => crossbar_out_port(4), + Port5_out => crossbar_out_port(5), + Port6_out => crossbar_out_port(6), + Ctrl => Grant_signal); +end generate crossbar_switch6x6; + + +-- switch 7 ports +crossbar_switch7x7 : if number_of_ports = 7 generate + +Switch_Crossbar7_7: Crossbar +GENERIC MAP(number_of_crossbar_ports =>7) + PORT MAP( + reset => reset, + clk => clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => crossbar_in_port(3), + Port4_in => crossbar_in_port(4), + Port5_in => crossbar_in_port(5), + Port6_in => crossbar_in_port(6), + Port7_in => crossbar_in_port(7), + Port8_in => "00000000", + Port9_in => "00000000", + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in => crossbar_in_pulse(3), + Port4_pulse_in => crossbar_in_pulse(4), + Port5_pulse_in => crossbar_in_pulse(5), + Port6_pulse_in => crossbar_in_pulse(6), + Port7_pulse_in => crossbar_in_pulse(7), + Port8_pulse_in =>'0' , + Port9_pulse_in =>'0' , + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port3_pulse_out => crossbar_out_pulse(3), + Port4_pulse_out => crossbar_out_pulse(4), + Port5_pulse_out => crossbar_out_pulse(5), + Port6_pulse_out => crossbar_out_pulse(6), + Port7_pulse_out => crossbar_out_pulse(7), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Port3_out => crossbar_out_port(3), + Port4_out => crossbar_out_port(4), + Port5_out => crossbar_out_port(5), + Port6_out => crossbar_out_port(6), + Port7_out => crossbar_out_port(7), + Ctrl => Grant_signal); +end generate crossbar_switch7x7; + + +-- switch 8 ports +crossbar_switch8x8 : if number_of_ports = 8 generate + +Switch_Crossbar8_8: Crossbar +GENERIC MAP(number_of_crossbar_ports =>8) + PORT MAP( + reset => reset, + clk =>clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => crossbar_in_port(3), + Port4_in => crossbar_in_port(4), + Port5_in => crossbar_in_port(5), + Port6_in => crossbar_in_port(6), + Port7_in => crossbar_in_port(7), + Port8_in => crossbar_in_port(8), + Port9_in => "00000000", + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in => crossbar_in_pulse(3), + Port4_pulse_in => crossbar_in_pulse(4), + Port5_pulse_in => crossbar_in_pulse(5), + Port6_pulse_in => crossbar_in_pulse(6), + Port7_pulse_in => crossbar_in_pulse(7), + Port8_pulse_in => crossbar_in_pulse(8), + Port9_pulse_in =>'0' , + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port3_pulse_out => crossbar_out_pulse(3), + Port4_pulse_out => crossbar_out_pulse(4), + Port5_pulse_out => crossbar_out_pulse(5), + Port6_pulse_out => crossbar_out_pulse(6), + Port7_pulse_out => crossbar_out_pulse(7), + Port8_pulse_out => crossbar_out_pulse(8), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Port3_out => crossbar_out_port(3), + Port4_out => crossbar_out_port(4), + Port5_out => crossbar_out_port(5), + Port6_out => crossbar_out_port(6), + Port7_out => crossbar_out_port(7), + Port8_out => crossbar_out_port(8), + Ctrl => Grant_signal); +end generate crossbar_switch8x8; + + +-- switch 9 ports +crossbar_switch9x9 : if number_of_ports = 9 generate + +Switch_Crossbar9_9: Crossbar +GENERIC MAP(number_of_crossbar_ports =>9) + PORT MAP( + reset => reset, + clk => clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => crossbar_in_port(3), + Port4_in => crossbar_in_port(4), + Port5_in => crossbar_in_port(5), + Port6_in => crossbar_in_port(6), + Port7_in => crossbar_in_port(7), + Port8_in => crossbar_in_port(8), + Port9_in => crossbar_in_port(9), + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in => crossbar_in_pulse(3), + Port4_pulse_in => crossbar_in_pulse(4), + Port5_pulse_in => crossbar_in_pulse(5), + Port6_pulse_in => crossbar_in_pulse(6), + Port7_pulse_in => crossbar_in_pulse(7), + Port8_pulse_in => crossbar_in_pulse(8), + Port9_pulse_in => crossbar_in_pulse(9), + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port3_pulse_out => crossbar_out_pulse(3), + Port4_pulse_out => crossbar_out_pulse(4), + Port5_pulse_out => crossbar_out_pulse(5), + Port6_pulse_out => crossbar_out_pulse(6), + Port7_pulse_out => crossbar_out_pulse(7), + Port8_pulse_out => crossbar_out_pulse(8), + Port9_pulse_out => crossbar_out_pulse(9), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Port3_out => crossbar_out_port(3), + Port4_out => crossbar_out_port(4), + Port5_out => crossbar_out_port(5), + Port6_out => crossbar_out_port(6), + Port7_out => crossbar_out_port(7), + Port8_out => crossbar_out_port(8), + Port9_out => crossbar_out_port(9), + Ctrl => Grant_signal); +end generate crossbar_switch9x9; + + +-- switch 10 ports +crossbar_switch10x10 : if number_of_ports = 10 generate + +Switch_Crossbar10_10: Crossbar +GENERIC MAP(number_of_crossbar_ports =>10) + PORT MAP( + reset => reset, + clk => clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => crossbar_in_port(3), + Port4_in => crossbar_in_port(4), + Port5_in => crossbar_in_port(5), + Port6_in => crossbar_in_port(6), + Port7_in => crossbar_in_port(7), + Port8_in => crossbar_in_port(8), + Port9_in => crossbar_in_port(9), + Port10_in => crossbar_in_port(10), + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in => crossbar_in_pulse(3), + Port4_pulse_in => crossbar_in_pulse(4), + Port5_pulse_in => crossbar_in_pulse(5), + Port6_pulse_in => crossbar_in_pulse(6), + Port7_pulse_in => crossbar_in_pulse(7), + Port8_pulse_in => crossbar_in_pulse(8), + Port9_pulse_in => crossbar_in_pulse(9), + Port10_pulse_in => crossbar_in_pulse(10), + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port3_pulse_out => crossbar_out_pulse(3), + Port4_pulse_out => crossbar_out_pulse(4), + Port5_pulse_out => crossbar_out_pulse(5), + Port6_pulse_out => crossbar_out_pulse(6), + Port7_pulse_out => crossbar_out_pulse(7), + Port8_pulse_out => crossbar_out_pulse(8), + Port9_pulse_out => crossbar_out_pulse(9), + Port10_pulse_out => crossbar_out_pulse(10), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Port3_out => crossbar_out_port(3), + Port4_out => crossbar_out_port(4), + Port5_out => crossbar_out_port(5), + Port6_out => crossbar_out_port(6), + Port7_out => crossbar_out_port(7), + Port8_out => crossbar_out_port(8), + Port9_out => crossbar_out_port(9), + Port10_out => crossbar_out_port(10), + Ctrl => Grant_signal); +end generate crossbar_switch10x10; + + +-- switch 11 ports +crossbar_switch11x11 : if number_of_ports = 11 generate + +Switch_Crossbar11_11: Crossbar +GENERIC MAP(number_of_crossbar_ports =>11) + PORT MAP( + reset => reset, + clk => clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => crossbar_in_port(3), + Port4_in => crossbar_in_port(4), + Port5_in => crossbar_in_port(5), + Port6_in => crossbar_in_port(6), + Port7_in => crossbar_in_port(7), + Port8_in => crossbar_in_port(8), + Port9_in => crossbar_in_port(9), + Port10_in => crossbar_in_port(10), + Port11_in => crossbar_in_port(11), + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in => crossbar_in_pulse(3), + Port4_pulse_in => crossbar_in_pulse(4), + Port5_pulse_in => crossbar_in_pulse(5), + Port6_pulse_in => crossbar_in_pulse(6), + Port7_pulse_in => crossbar_in_pulse(7), + Port8_pulse_in => crossbar_in_pulse(8), + Port9_pulse_in => crossbar_in_pulse(9), + Port10_pulse_in => crossbar_in_pulse(10), + Port11_pulse_in => crossbar_in_pulse(11), + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port3_pulse_out => crossbar_out_pulse(3), + Port4_pulse_out => crossbar_out_pulse(4), + Port5_pulse_out => crossbar_out_pulse(5), + Port6_pulse_out => crossbar_out_pulse(6), + Port7_pulse_out => crossbar_out_pulse(7), + Port8_pulse_out => crossbar_out_pulse(8), + Port9_pulse_out => crossbar_out_pulse(9), + Port10_pulse_out => crossbar_out_pulse(10), + Port11_pulse_out => crossbar_out_pulse(11), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Port3_out => crossbar_out_port(3), + Port4_out => crossbar_out_port(4), + Port5_out => crossbar_out_port(5), + Port6_out => crossbar_out_port(6), + Port7_out => crossbar_out_port(7), + Port8_out => crossbar_out_port(8), + Port9_out => crossbar_out_port(9), + Port10_out => crossbar_out_port(10), + Port11_out => crossbar_out_port(11), + Ctrl => Grant_signal); +end generate crossbar_switch11x11; + + +-- switch 12 ports +crossbar_switch12x12 : if number_of_ports = 12 generate + +Switch_Crossbar12_12: Crossbar +GENERIC MAP(number_of_crossbar_ports =>12) + PORT MAP( + reset => reset, + clk => clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => crossbar_in_port(3), + Port4_in => crossbar_in_port(4), + Port5_in => crossbar_in_port(5), + Port6_in => crossbar_in_port(6), + Port7_in => crossbar_in_port(7), + Port8_in => crossbar_in_port(8), + Port9_in => crossbar_in_port(9), + Port10_in => crossbar_in_port(10), + Port11_in => crossbar_in_port(11), + Port12_in => crossbar_in_port(12), + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in => crossbar_in_pulse(3), + Port4_pulse_in => crossbar_in_pulse(4), + Port5_pulse_in => crossbar_in_pulse(5), + Port6_pulse_in => crossbar_in_pulse(6), + Port7_pulse_in => crossbar_in_pulse(7), + Port8_pulse_in => crossbar_in_pulse(8), + Port9_pulse_in => crossbar_in_pulse(9), + Port10_pulse_in => crossbar_in_pulse(10), + Port11_pulse_in => crossbar_in_pulse(11), + Port12_pulse_in => crossbar_in_pulse(12), + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port3_pulse_out => crossbar_out_pulse(3), + Port4_pulse_out => crossbar_out_pulse(4), + Port5_pulse_out => crossbar_out_pulse(5), + Port6_pulse_out => crossbar_out_pulse(6), + Port7_pulse_out => crossbar_out_pulse(7), + Port8_pulse_out => crossbar_out_pulse(8), + Port9_pulse_out => crossbar_out_pulse(9), + Port10_pulse_out => crossbar_out_pulse(10), + Port11_pulse_out => crossbar_out_pulse(11), + Port12_pulse_out => crossbar_out_pulse(12), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Port3_out => crossbar_out_port(3), + Port4_out => crossbar_out_port(4), + Port5_out => crossbar_out_port(5), + Port6_out => crossbar_out_port(6), + Port7_out => crossbar_out_port(7), + Port8_out => crossbar_out_port(8), + Port9_out => crossbar_out_port(9), + Port10_out => crossbar_out_port(10), + Port11_out => crossbar_out_port(11), + Port12_out => crossbar_out_port(12), + Ctrl => Grant_signal); +end generate crossbar_switch12x12; + + +-- switch 13 ports +crossbar_switch13x13 : if number_of_ports = 13 generate + +Switch_Crossbar13_13: Crossbar +GENERIC MAP(number_of_crossbar_ports =>13) + PORT MAP( + reset => reset, + clk => clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => crossbar_in_port(3), + Port4_in => crossbar_in_port(4), + Port5_in => crossbar_in_port(5), + Port6_in => crossbar_in_port(6), + Port7_in => crossbar_in_port(7), + Port8_in => crossbar_in_port(8), + Port9_in => crossbar_in_port(9), + Port10_in => crossbar_in_port(10), + Port11_in => crossbar_in_port(11), + Port12_in => crossbar_in_port(12), + Port13_in => crossbar_in_port(13), + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in => crossbar_in_pulse(3), + Port4_pulse_in => crossbar_in_pulse(4), + Port5_pulse_in => crossbar_in_pulse(5), + Port6_pulse_in => crossbar_in_pulse(6), + Port7_pulse_in => crossbar_in_pulse(7), + Port8_pulse_in => crossbar_in_pulse(8), + Port9_pulse_in => crossbar_in_pulse(9), + Port10_pulse_in => crossbar_in_pulse(10), + Port11_pulse_in => crossbar_in_pulse(11), + Port12_pulse_in => crossbar_in_pulse(12), + Port13_pulse_in => crossbar_in_pulse(13), + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port3_pulse_out => crossbar_out_pulse(3), + Port4_pulse_out => crossbar_out_pulse(4), + Port5_pulse_out => crossbar_out_pulse(5), + Port6_pulse_out => crossbar_out_pulse(6), + Port7_pulse_out => crossbar_out_pulse(7), + Port8_pulse_out => crossbar_out_pulse(8), + Port9_pulse_out => crossbar_out_pulse(9), + Port10_pulse_out => crossbar_out_pulse(10), + Port11_pulse_out => crossbar_out_pulse(11), + Port12_pulse_out => crossbar_out_pulse(12), + Port13_pulse_out => crossbar_out_pulse(13), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Port3_out => crossbar_out_port(3), + Port4_out => crossbar_out_port(4), + Port5_out => crossbar_out_port(5), + Port6_out => crossbar_out_port(6), + Port7_out => crossbar_out_port(7), + Port8_out => crossbar_out_port(8), + Port9_out => crossbar_out_port(9), + Port10_out => crossbar_out_port(10), + Port11_out => crossbar_out_port(11), + Port12_out => crossbar_out_port(12), + Port13_out => crossbar_out_port(13), + Ctrl => Grant_signal); +end generate crossbar_switch13x13; + + +-- switch 14 ports +crossbar_switch14x14 : if number_of_ports = 14 generate + +Switch_Crossbar14_14: Crossbar +GENERIC MAP(number_of_crossbar_ports =>14) + PORT MAP( + reset => reset, + clk => clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => crossbar_in_port(3), + Port4_in => crossbar_in_port(4), + Port5_in => crossbar_in_port(5), + Port6_in => crossbar_in_port(6), + Port7_in => crossbar_in_port(7), + Port8_in => crossbar_in_port(8), + Port9_in => crossbar_in_port(9), + Port10_in => crossbar_in_port(10), + Port11_in => crossbar_in_port(11), + Port12_in => crossbar_in_port(12), + Port13_in => crossbar_in_port(13), + Port14_in => crossbar_in_port(14), + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in => crossbar_in_pulse(3), + Port4_pulse_in => crossbar_in_pulse(4), + Port5_pulse_in => crossbar_in_pulse(5), + Port6_pulse_in => crossbar_in_pulse(6), + Port7_pulse_in => crossbar_in_pulse(7), + Port8_pulse_in => crossbar_in_pulse(8), + Port9_pulse_in => crossbar_in_pulse(9), + Port10_pulse_in => crossbar_in_pulse(10), + Port11_pulse_in => crossbar_in_pulse(11), + Port12_pulse_in => crossbar_in_pulse(12), + Port13_pulse_in => crossbar_in_pulse(13), + Port14_pulse_in => crossbar_in_pulse(14), + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port3_pulse_out => crossbar_out_pulse(3), + Port4_pulse_out => crossbar_out_pulse(4), + Port5_pulse_out => crossbar_out_pulse(5), + Port6_pulse_out => crossbar_out_pulse(6), + Port7_pulse_out => crossbar_out_pulse(7), + Port8_pulse_out => crossbar_out_pulse(8), + Port9_pulse_out => crossbar_out_pulse(9), + Port10_pulse_out => crossbar_out_pulse(10), + Port11_pulse_out => crossbar_out_pulse(11), + Port12_pulse_out => crossbar_out_pulse(12), + Port13_pulse_out => crossbar_out_pulse(13), + Port14_pulse_out => crossbar_out_pulse(14), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Port3_out => crossbar_out_port(3), + Port4_out => crossbar_out_port(4), + Port5_out => crossbar_out_port(5), + Port6_out => crossbar_out_port(6), + Port7_out => crossbar_out_port(7), + Port8_out => crossbar_out_port(8), + Port9_out => crossbar_out_port(9), + Port10_out => crossbar_out_port(10), + Port11_out => crossbar_out_port(11), + Port12_out => crossbar_out_port(12), + Port13_out => crossbar_out_port(13), + Port14_out => crossbar_out_port(14), + Ctrl => Grant_signal); +end generate crossbar_switch14x14; + + +-- switch 15 ports +crossbar_switch15x15 : if number_of_ports = 15 generate + +Switch_Crossbar15_15: Crossbar +GENERIC MAP(number_of_crossbar_ports =>15) + PORT MAP( + reset => reset, + clk => clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => crossbar_in_port(3), + Port4_in => crossbar_in_port(4), + Port5_in => crossbar_in_port(5), + Port6_in => crossbar_in_port(6), + Port7_in => crossbar_in_port(7), + Port8_in => crossbar_in_port(8), + Port9_in => crossbar_in_port(9), + Port10_in => crossbar_in_port(10), + Port11_in => crossbar_in_port(11), + Port12_in => crossbar_in_port(12), + Port13_in => crossbar_in_port(13), + Port14_in => crossbar_in_port(14), + Port15_in => crossbar_in_port(15), + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in => crossbar_in_pulse(3), + Port4_pulse_in => crossbar_in_pulse(4), + Port5_pulse_in => crossbar_in_pulse(5), + Port6_pulse_in => crossbar_in_pulse(6), + Port7_pulse_in => crossbar_in_pulse(7), + Port8_pulse_in => crossbar_in_pulse(8), + Port9_pulse_in => crossbar_in_pulse(9), + Port10_pulse_in => crossbar_in_pulse(10), + Port11_pulse_in => crossbar_in_pulse(11), + Port12_pulse_in => crossbar_in_pulse(12), + Port13_pulse_in => crossbar_in_pulse(13), + Port14_pulse_in => crossbar_in_pulse(14), + Port15_pulse_in => crossbar_in_pulse(15), + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port3_pulse_out => crossbar_out_pulse(3), + Port4_pulse_out => crossbar_out_pulse(4), + Port5_pulse_out => crossbar_out_pulse(5), + Port6_pulse_out => crossbar_out_pulse(6), + Port7_pulse_out => crossbar_out_pulse(7), + Port8_pulse_out => crossbar_out_pulse(8), + Port9_pulse_out => crossbar_out_pulse(9), + Port10_pulse_out => crossbar_out_pulse(10), + Port11_pulse_out => crossbar_out_pulse(11), + Port12_pulse_out => crossbar_out_pulse(12), + Port13_pulse_out => crossbar_out_pulse(13), + Port14_pulse_out => crossbar_out_pulse(14), + Port15_pulse_out => crossbar_out_pulse(15), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Port3_out => crossbar_out_port(3), + Port4_out => crossbar_out_port(4), + Port5_out => crossbar_out_port(5), + Port6_out => crossbar_out_port(6), + Port7_out => crossbar_out_port(7), + Port8_out => crossbar_out_port(8), + Port9_out => crossbar_out_port(9), + Port10_out => crossbar_out_port(10), + Port11_out => crossbar_out_port(11), + Port12_out => crossbar_out_port(12), + Port13_out => crossbar_out_port(13), + Port14_out => crossbar_out_port(14), + Port15_out => crossbar_out_port(15), + Ctrl => Grant_signal); +end generate crossbar_switch15x15; + + +-- switch 16 ports +crossbar_switch16x16 : if number_of_ports = 16 generate + +Switch_Crossbar16_16: Crossbar +GENERIC MAP(number_of_crossbar_ports =>16) + PORT MAP( + reset => reset, + clk => clk, + Port1_in => crossbar_in_port(1), + Port2_in => crossbar_in_port(2), + Port3_in => crossbar_in_port(3), + Port4_in => crossbar_in_port(4), + Port5_in => crossbar_in_port(5), + Port6_in => crossbar_in_port(6), + Port7_in => crossbar_in_port(7), + Port8_in => crossbar_in_port(8), + Port9_in => crossbar_in_port(9), + Port10_in => crossbar_in_port(10), + Port11_in => crossbar_in_port(11), + Port12_in => crossbar_in_port(12), + Port13_in => crossbar_in_port(13), + Port14_in => crossbar_in_port(14), + Port15_in => crossbar_in_port(15), + Port16_in => crossbar_in_port(16), + Port1_pulse_in => crossbar_in_pulse(1), + Port2_pulse_in => crossbar_in_pulse(2), + Port3_pulse_in => crossbar_in_pulse(3), + Port4_pulse_in => crossbar_in_pulse(4), + Port5_pulse_in => crossbar_in_pulse(5), + Port6_pulse_in => crossbar_in_pulse(6), + Port7_pulse_in => crossbar_in_pulse(7), + Port8_pulse_in => crossbar_in_pulse(8), + Port9_pulse_in => crossbar_in_pulse(9), + Port10_pulse_in => crossbar_in_pulse(10), + Port11_pulse_in => crossbar_in_pulse(11), + Port12_pulse_in => crossbar_in_pulse(12), + Port13_pulse_in => crossbar_in_pulse(13), + Port14_pulse_in => crossbar_in_pulse(14), + Port15_pulse_in => crossbar_in_pulse(15), + Port16_pulse_in => crossbar_in_pulse(16), + Port1_pulse_out => crossbar_out_pulse(1), + Port2_pulse_out => crossbar_out_pulse(2), + Port3_pulse_out => crossbar_out_pulse(3), + Port4_pulse_out => crossbar_out_pulse(4), + Port5_pulse_out => crossbar_out_pulse(5), + Port6_pulse_out => crossbar_out_pulse(6), + Port7_pulse_out => crossbar_out_pulse(7), + Port8_pulse_out => crossbar_out_pulse(8), + Port9_pulse_out => crossbar_out_pulse(9), + Port10_pulse_out => crossbar_out_pulse(10), + Port11_pulse_out => crossbar_out_pulse(11), + Port12_pulse_out => crossbar_out_pulse(12), + Port13_pulse_out => crossbar_out_pulse(13), + Port14_pulse_out => crossbar_out_pulse(14), + Port15_pulse_out => crossbar_out_pulse(15), + Port16_pulse_out => crossbar_out_pulse(16), + Port1_out => crossbar_out_port(1), + Port2_out => crossbar_out_port(2), + Port3_out => crossbar_out_port(3), + Port4_out => crossbar_out_port(4), + Port5_out => crossbar_out_port(5), + Port6_out => crossbar_out_port(6), + Port7_out => crossbar_out_port(7), + Port8_out => crossbar_out_port(8), + Port9_out => crossbar_out_port(9), + Port10_out => crossbar_out_port(10), + Port11_out => crossbar_out_port(11), + Port12_out => crossbar_out_port(12), + Port13_out => crossbar_out_port(13), + Port14_out => crossbar_out_port(14), + Port15_out => crossbar_out_port(15), + Port16_out => crossbar_out_port(16), + Ctrl => Grant_signal); +end generate crossbar_switch16x16; +-- intstanciation et connexion du scheduler en fonction du nombre de ports +-- le circuit genere depend du parametre generique nombre de ports +-- switch 2 ports +scheduler_switch2x2 : if number_of_ports = 2 generate + +Scheduler2_2: Scheduler + GENERIC MAP(number_of_ports => 2 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch2x2; + + +-- switch 3 ports +scheduler_switch3x3 : if number_of_ports = 3 generate + +Scheduler3_3: Scheduler + GENERIC MAP(number_of_ports => 3 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch3x3; + + +-- switch 4 ports +scheduler_switch4x4 : if number_of_ports = 4 generate + +Scheduler4_4: Scheduler + GENERIC MAP(number_of_ports => 4 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch4x4; + + +-- switch 5 ports +scheduler_switch5x5 : if number_of_ports = 5 generate + +Scheduler5_5: Scheduler + GENERIC MAP(number_of_ports => 5 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch5x5; + + +-- switch 6 ports +scheduler_switch6x6 : if number_of_ports = 6 generate + +Scheduler6_6: Scheduler + GENERIC MAP(number_of_ports => 6 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch6x6; + + +-- switch 7 ports +scheduler_switch7x7 : if number_of_ports = 7 generate + +Scheduler7_7: Scheduler + GENERIC MAP(number_of_ports => 7 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch7x7; + + +-- switch 8 ports +scheduler_switch8x8 : if number_of_ports = 8 generate + +Scheduler8_8: Scheduler + GENERIC MAP(number_of_ports => 8 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch8x8; + + +-- switch 9 ports +scheduler_switch9x9 : if number_of_ports = 9 generate + +Scheduler9_9: Scheduler + GENERIC MAP(number_of_ports => 9 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch9x9; + + +-- switch 10 ports +scheduler_switch10x10 : if number_of_ports = 10 generate + +Scheduler10_10: Scheduler + GENERIC MAP(number_of_ports => 10 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch10x10; + + +-- switch 11 ports +scheduler_switch11x11 : if number_of_ports = 11 generate + +Scheduler11_11: Scheduler + GENERIC MAP(number_of_ports => 11 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch11x11; + + +-- switch 12 ports +scheduler_switch12x12 : if number_of_ports = 12 generate + +Scheduler12_12: Scheduler + GENERIC MAP(number_of_ports => 12 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch12x12; + + +-- switch 13 ports +scheduler_switch13x13 : if number_of_ports = 13 generate + +Scheduler13_13: Scheduler + GENERIC MAP(number_of_ports => 13 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch13x13; + + +-- switch 14 ports +scheduler_switch14x14 : if number_of_ports = 14 generate + +Scheduler14_14: Scheduler + GENERIC MAP(number_of_ports => 14 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch14x14; + + +-- switch 15 ports +scheduler_switch15x15 : if number_of_ports = 15 generate + +Scheduler15_15: Scheduler + GENERIC MAP(number_of_ports => 15 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch15x15; + + +-- switch 16 ports +scheduler_switch16x16 : if number_of_ports = 16 generate + +Scheduler16_16: Scheduler + GENERIC MAP(number_of_ports => 16 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch16x16; + + +end Behavioral; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SWITCH_GENERIQUE.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SWITCH_GENERIQUE.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/SWITCH_GENERIQUE.vhd (revision 138) @@ -0,0 +1,8134 @@ +---------------------------------------------------------------------------------- +-- Company: ENSET 2011 +-- Engineer: GAMOM NGOUNOU ET KIEGAING EMMANUEL ET TAGNE FRANKLIN EN 5 +-- +-- Create Date: 03:40:47 06/18/2011 +-- Design Name: +-- Module Name: SWITCH_GENERIQUE - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- fichier principal du switch générique; en fonction du parametre generique le +-- les directive de generation conditionnelle permettent de ne générer et synthétiser uniquement la logique +-- nécessaire à l'implémentation du switch de la dimension voulue +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity SWITCH_GENERIQUE is + generic(number_of_ports : positive := 8); + port( + -- ports d'entree + Port1_in : in STD_LOGIC_VECTOR (7 downto 0); + Port2_in : in STD_LOGIC_VECTOR (7 downto 0); + Port3_in : in STD_LOGIC_VECTOR (7 downto 0); + Port4_in : in STD_LOGIC_VECTOR (7 downto 0); + Port5_in : in STD_LOGIC_VECTOR (7 downto 0); + Port6_in : in STD_LOGIC_VECTOR (7 downto 0); + Port7_in : in STD_LOGIC_VECTOR (7 downto 0); + Port8_in : in STD_LOGIC_VECTOR (7 downto 0); + Port9_in : in STD_LOGIC_VECTOR (7 downto 0); + Port10_in : in STD_LOGIC_VECTOR (7 downto 0); + Port11_in : in STD_LOGIC_VECTOR (7 downto 0); + Port12_in : in STD_LOGIC_VECTOR (7 downto 0); + Port13_in : in STD_LOGIC_VECTOR (7 downto 0); + Port14_in : in STD_LOGIC_VECTOR (7 downto 0); + Port15_in : in STD_LOGIC_VECTOR (7 downto 0); + Port16_in : in STD_LOGIC_VECTOR (7 downto 0); + + -- port de sortie + Port1_out : out STD_LOGIC_VECTOR (7 downto 0); + Port2_out : out STD_LOGIC_VECTOR (7 downto 0); + Port3_out : out STD_LOGIC_VECTOR (7 downto 0); + Port4_out : out STD_LOGIC_VECTOR (7 downto 0); + Port5_out : out STD_LOGIC_VECTOR (7 downto 0); + Port6_out : out STD_LOGIC_VECTOR (7 downto 0); + Port7_out : out STD_LOGIC_VECTOR (7 downto 0); + Port8_out : out STD_LOGIC_VECTOR (7 downto 0); + Port9_out : out STD_LOGIC_VECTOR (7 downto 0); + Port10_out : out STD_LOGIC_VECTOR (7 downto 0); + Port11_out : out STD_LOGIC_VECTOR (7 downto 0); + Port12_out : out STD_LOGIC_VECTOR (7 downto 0); + Port13_out : out STD_LOGIC_VECTOR (7 downto 0); + Port14_out : out STD_LOGIC_VECTOR (7 downto 0); + Port15_out : out STD_LOGIC_VECTOR (7 downto 0); + Port16_out : out STD_LOGIC_VECTOR (7 downto 0); + -- signaux de controle + data_in_en : in std_logic_vector(number_of_ports downto 1); + data_out_en : in std_logic_vector(number_of_ports downto 1); + fifo_in_full : out std_logic_vector(number_of_ports downto 1); + fifo_in_empty : out std_logic_vector(number_of_ports downto 1); + data_available : out std_logic_vector(number_of_ports downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC); +end SWITCH_GENERIQUE; + +architecture Behavioral of SWITCH_GENERIQUE is +-- declaration des modules du switch generique +-- le module de gestion des ports d'entrée + +COMPONENT INPUT_PORT_MODULE + generic(number_of_ports : positive := 4); + Port ( data_in : in STD_LOGIC_VECTOR (7 downto 0); + data_in_en : in STD_LOGIC; + reset : in STD_LOGIC; + clk : in STD_LOGIC; + request : out STD_LOGIC_VECTOR (number_of_ports downto 1); + grant : in STD_LOGIC_VECTOR (number_of_ports downto 1); + fifo_full : out STD_LOGIC; + fifo_empty : out STD_LOGIC; + priority_rotation : out std_logic; + data_out : out STD_LOGIC_VECTOR (7 downto 0); + data_out_pulse : out std_logic); +END COMPONENT; + +-- le module des ports de sortie + +COMPONENT OUTPUT_PORT_MODULE + PORT( + data_in : IN std_logic_vector(7 downto 0); + reset : IN std_logic; + clk : IN std_logic; + wr_en : IN std_logic; + rd_out_en : IN std_logic; + data_out : OUT std_logic_vector(7 downto 0); + fifo_full : OUT std_logic; + data_avalaible : OUT std_logic + ); +END COMPONENT; + +-- le module du crossbar +COMPONENT Crossbar + generic + ( + number_of_crossbar_ports: positive := 4 + ); + Port ( Port1_in : in STD_LOGIC_VECTOR (7 downto 0); + Port2_in : in STD_LOGIC_VECTOR (7 downto 0); + Port3_in : in STD_LOGIC_VECTOR (7 downto 0); + Port4_in : in STD_LOGIC_VECTOR (7 downto 0); + Port5_in : in STD_LOGIC_VECTOR (7 downto 0); + Port6_in : in STD_LOGIC_VECTOR (7 downto 0); + Port7_in : in STD_LOGIC_VECTOR (7 downto 0); + Port8_in : in STD_LOGIC_VECTOR (7 downto 0); + Port9_in : in STD_LOGIC_VECTOR (7 downto 0); + Port10_in : in STD_LOGIC_VECTOR (7 downto 0); + Port11_in : in STD_LOGIC_VECTOR (7 downto 0); + Port12_in : in STD_LOGIC_VECTOR (7 downto 0); + Port13_in : in STD_LOGIC_VECTOR (7 downto 0); + Port14_in : in STD_LOGIC_VECTOR (7 downto 0); + Port15_in : in STD_LOGIC_VECTOR (7 downto 0); + Port16_in : in STD_LOGIC_VECTOR (7 downto 0); + + Port1_pulse_in : in std_logic; + Port2_pulse_in : in std_logic; + Port3_pulse_in : in std_logic; + Port4_pulse_in : in std_logic; + Port5_pulse_in : in std_logic; + Port6_pulse_in : in std_logic; + Port7_pulse_in : in std_logic; + Port8_pulse_in : in std_logic; + Port9_pulse_in : in std_logic; + Port10_pulse_in : in std_logic; + Port11_pulse_in : in std_logic; + Port12_pulse_in : in std_logic; + Port13_pulse_in : in std_logic; + Port14_pulse_in : in std_logic; + Port15_pulse_in : in std_logic; + Port16_pulse_in : in std_logic; + + Port1_pulse_out : out std_logic; + Port2_pulse_out : out std_logic; + Port3_pulse_out : out std_logic; + Port4_pulse_out : out std_logic; + Port5_pulse_out : out std_logic; + Port6_pulse_out : out std_logic; + Port7_pulse_out : out std_logic; + Port8_pulse_out : out std_logic; + Port9_pulse_out : out std_logic; + Port10_pulse_out : out std_logic; + Port11_pulse_out : out std_logic; + Port12_pulse_out : out std_logic; + Port13_pulse_out : out std_logic; + Port14_pulse_out : out std_logic; + Port15_pulse_out : out std_logic; + Port16_pulse_out : out std_logic; + + Port1_out : out STD_LOGIC_VECTOR (7 downto 0); + Port2_out : out STD_LOGIC_VECTOR (7 downto 0); + Port3_out : out STD_LOGIC_VECTOR (7 downto 0); + Port4_out : out STD_LOGIC_VECTOR (7 downto 0); + Port5_out : out STD_LOGIC_VECTOR (7 downto 0); + Port6_out : out STD_LOGIC_VECTOR (7 downto 0); + Port7_out : out STD_LOGIC_VECTOR (7 downto 0); + Port8_out : out STD_LOGIC_VECTOR (7 downto 0); + Port9_out : out STD_LOGIC_VECTOR (7 downto 0); + Port10_out : out STD_LOGIC_VECTOR (7 downto 0); + Port11_out : out STD_LOGIC_VECTOR (7 downto 0); + Port12_out : out STD_LOGIC_VECTOR (7 downto 0); + Port13_out : out STD_LOGIC_VECTOR (7 downto 0); + Port14_out : out STD_LOGIC_VECTOR (7 downto 0); + Port15_out : out STD_LOGIC_VECTOR (7 downto 0); + Port16_out : out STD_LOGIC_VECTOR (7 downto 0); + + Ctrl : in STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1) + ); + END COMPONENT; + +-- déclaration du scheduler +COMPONENT Scheduler + generic(number_of_ports : positive := 4); + Port ( Request : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1); + Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (number_of_ports downto 1); + port_grant : out STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1)); +END COMPONENT; + +--declaration des signaux de connection entre les modules du switch +--type port_connection_type is array(16 downto 1) of std_logic_vector(7 downto 1); +--signal crossbar_port_in_connetion : port_connection_type; +--signal crossbar_port_out_connetion :port_connection_type; +--signal request_connection : std_logic_vector(number_of_ports*number_of_ports downto 1); +--signal grant_connection : std_logic_vector(number_of_ports*number_of_ports downto 1); +--signal priority_rotation_connection : std_logic_vector(number_of_ports downto 1); +--signal fifo_out_full_connection : std_logic_vector(1 to number_of_ports); +--signal crossbar_in_pulse_connection : std_logic_vector(number_of_ports downto 1); +--signal crossbar_out_pulse_connection : std_logic_vector(number_of_ports downto 1); + +Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1); +Signal grant_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1); +Signal priority_rotation_signal : STD_LOGIC_VECTOR(number_of_ports downto 1); +signal fifo_out_full_signal : std_logic_vector(number_of_ports downto 1); +signal crossbar_in_port1 : std_logic_vector(7 downto 0); +signal crossbar_in_port2 : std_logic_vector(7 downto 0); +signal crossbar_in_port3 : std_logic_vector(7 downto 0); +signal crossbar_in_port4 : std_logic_vector(7 downto 0); +signal crossbar_in_port5 : std_logic_vector(7 downto 0); +signal crossbar_in_port6 : std_logic_vector(7 downto 0); +signal crossbar_in_port7 : std_logic_vector(7 downto 0); +signal crossbar_in_port8 : std_logic_vector(7 downto 0); +signal crossbar_in_port9 : std_logic_vector(7 downto 0); +signal crossbar_in_port10 : std_logic_vector(7 downto 0); +signal crossbar_in_port11 : std_logic_vector(7 downto 0); +signal crossbar_in_port12 : std_logic_vector(7 downto 0); +signal crossbar_in_port13 : std_logic_vector(7 downto 0); +signal crossbar_in_port14 : std_logic_vector(7 downto 0); +signal crossbar_in_port15 : std_logic_vector(7 downto 0); +signal crossbar_in_port16: std_logic_vector(7 downto 0); + +signal crossbar_out_port1 : std_logic_vector(7 downto 0); +signal crossbar_out_port2 : std_logic_vector(7 downto 0); +signal crossbar_out_port3 : std_logic_vector(7 downto 0); +signal crossbar_out_port4 : std_logic_vector(7 downto 0); +signal crossbar_out_port5 : std_logic_vector(7 downto 0); +signal crossbar_out_port6 : std_logic_vector(7 downto 0); +signal crossbar_out_port7 : std_logic_vector(7 downto 0); +signal crossbar_out_port8 : std_logic_vector(7 downto 0); +signal crossbar_out_port9 : std_logic_vector(7 downto 0); +signal crossbar_out_port10 : std_logic_vector(7 downto 0); +signal crossbar_out_port11 : std_logic_vector(7 downto 0); +signal crossbar_out_port12 : std_logic_vector(7 downto 0); +signal crossbar_out_port13 : std_logic_vector(7 downto 0); +signal crossbar_out_port14 : std_logic_vector(7 downto 0); +signal crossbar_out_port15 : std_logic_vector(7 downto 0); +signal crossbar_out_port16 : std_logic_vector(7 downto 0); + +signal crossbar_in_pulse1 : std_logic; +signal crossbar_in_pulse2 : std_logic; +signal crossbar_in_pulse3 : std_logic; +signal crossbar_in_pulse4 : std_logic; +signal crossbar_in_pulse5 : std_logic; +signal crossbar_in_pulse6 : std_logic; +signal crossbar_in_pulse7 : std_logic; +signal crossbar_in_pulse8 : std_logic; +signal crossbar_in_pulse9 : std_logic; +signal crossbar_in_pulse10 : std_logic; +signal crossbar_in_pulse11 : std_logic; +signal crossbar_in_pulse12 : std_logic; +signal crossbar_in_pulse13 : std_logic; +signal crossbar_in_pulse14 : std_logic; +signal crossbar_in_pulse15 : std_logic; +signal crossbar_in_pulse16 : std_logic; + + +signal crossbar_out_pulse1 : std_logic; +signal crossbar_out_pulse2 : std_logic; +signal crossbar_out_pulse3 : std_logic; +signal crossbar_out_pulse4 : std_logic; +signal crossbar_out_pulse5 : std_logic; +signal crossbar_out_pulse6 : std_logic; +signal crossbar_out_pulse7 : std_logic; +signal crossbar_out_pulse8 : std_logic; +signal crossbar_out_pulse9 : std_logic; +signal crossbar_out_pulse10 : std_logic; +signal crossbar_out_pulse11 : std_logic; +signal crossbar_out_pulse12 : std_logic; +signal crossbar_out_pulse13 : std_logic; +signal crossbar_out_pulse14 : std_logic; +signal crossbar_out_pulse15 : std_logic; +signal crossbar_out_pulse16 : std_logic; + + +begin +-- intstanciation et connexion des modules du switch en fonction du nombre de ports +-- le circuit genere depend du parametre generique nombre de ports +-- switch 2 ports +switch2x2 : if number_of_ports = 2 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>2) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>2) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(3) => grant_signal(3), + grant(4) => grant_signal(4), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(3) =>request_signal(3), + request(4) =>request_signal(4) +); + +end generate switch2x2; + + +-- switch 3 ports +switch3x3 : if number_of_ports = 3 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>3) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>3) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(4) => grant_signal(4), + grant(5) => grant_signal(5), + grant(6) => grant_signal(6), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(4) =>request_signal(4), + request(5) =>request_signal(5), + request(6) =>request_signal(6) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>3) +PORT MAP( + data_in => Port3_in, + data_in_en => data_in_en(3), + reset => reset, + clk =>clk, + grant(7) => grant_signal(7), + grant(8) => grant_signal(8), + grant(9) => grant_signal(9), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port3, + data_out_pulse =>crossbar_in_pulse3, + request(7) =>request_signal(7), + request(8) =>request_signal(8), + request(9) =>request_signal(9) +); + +end generate switch3x3; + + +-- switch 4 ports +switch4x4 : if number_of_ports = 4 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>4) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + grant(4) => grant_signal(4), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3), + request(4) =>request_signal(4) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>4) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(5) => grant_signal(5), + grant(6) => grant_signal(6), + grant(7) => grant_signal(7), + grant(8) => grant_signal(8), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(5) =>request_signal(5), + request(6) =>request_signal(6), + request(7) =>request_signal(7), + request(8) =>request_signal(8) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>4) +PORT MAP( + data_in => Port3_in, + data_in_en => data_in_en(3), + reset => reset, + clk =>clk, + grant(9) => grant_signal(9), + grant(10) => grant_signal(10), + grant(11) => grant_signal(11), + grant(12) => grant_signal(12), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port3, + data_out_pulse =>crossbar_in_pulse3, + request(9) =>request_signal(9), + request(10) =>request_signal(10), + request(11) =>request_signal(11), + request(12) =>request_signal(12) +); + +PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>4) +PORT MAP( + data_in => Port4_in, + data_in_en => data_in_en(4), + reset => reset, + clk =>clk, + grant(13) => grant_signal(13), + grant(14) => grant_signal(14), + grant(15) => grant_signal(15), + grant(16) => grant_signal(16), + fifo_full =>fifo_in_full(4), + priority_rotation => priority_rotation_signal(4), + fifo_empty => fifo_in_empty(4), + data_out =>crossbar_in_port4, + data_out_pulse =>crossbar_in_pulse4, + request(13) =>request_signal(13), + request(14) =>request_signal(14), + request(15) =>request_signal(15), + request(16) =>request_signal(16) +); + +end generate switch4x4; + + +-- switch 5 ports +switch5x5 : if number_of_ports = 5 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>5) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + grant(4) => grant_signal(4), + grant(5) => grant_signal(5), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3), + request(4) =>request_signal(4), + request(5) =>request_signal(5) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>5) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(6) => grant_signal(6), + grant(7) => grant_signal(7), + grant(8) => grant_signal(8), + grant(9) => grant_signal(9), + grant(10) => grant_signal(10), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(6) =>request_signal(6), + request(7) =>request_signal(7), + request(8) =>request_signal(8), + request(9) =>request_signal(9), + request(10) =>request_signal(10) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>5) +PORT MAP( + data_in => Port3_in, + data_in_en => data_in_en(3), + reset => reset, + clk =>clk, + grant(11) => grant_signal(11), + grant(12) => grant_signal(12), + grant(13) => grant_signal(13), + grant(14) => grant_signal(14), + grant(15) => grant_signal(15), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port3, + data_out_pulse =>crossbar_in_pulse3, + request(11) =>request_signal(11), + request(12) =>request_signal(12), + request(13) =>request_signal(13), + request(14) =>request_signal(14), + request(15) =>request_signal(15) +); + +PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>5) +PORT MAP( + data_in => Port4_in, + data_in_en => data_in_en(4), + reset => reset, + clk =>clk, + grant(16) => grant_signal(16), + grant(17) => grant_signal(17), + grant(18) => grant_signal(18), + grant(19) => grant_signal(19), + grant(20) => grant_signal(20), + fifo_full =>fifo_in_full(4), + priority_rotation => priority_rotation_signal(4), + fifo_empty => fifo_in_empty(4), + data_out =>crossbar_in_port4, + data_out_pulse =>crossbar_in_pulse4, + request(16) =>request_signal(16), + request(17) =>request_signal(17), + request(18) =>request_signal(18), + request(19) =>request_signal(19), + request(20) =>request_signal(20) +); + +PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>5) +PORT MAP( + data_in => Port5_in, + data_in_en => data_in_en(5), + reset => reset, + clk =>clk, + grant(21) => grant_signal(21), + grant(22) => grant_signal(22), + grant(23) => grant_signal(23), + grant(24) => grant_signal(24), + grant(25) => grant_signal(25), + fifo_full =>fifo_in_full(5), + priority_rotation => priority_rotation_signal(5), + fifo_empty => fifo_in_empty(5), + data_out =>crossbar_in_port5, + data_out_pulse =>crossbar_in_pulse5, + request(21) =>request_signal(21), + request(22) =>request_signal(22), + request(23) =>request_signal(23), + request(24) =>request_signal(24), + request(25) =>request_signal(25) +); + +end generate switch5x5; + + +-- switch 6 ports +switch6x6 : if number_of_ports = 6 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>6) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + grant(4) => grant_signal(4), + grant(5) => grant_signal(5), + grant(6) => grant_signal(6), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3), + request(4) =>request_signal(4), + request(5) =>request_signal(5), + request(6) =>request_signal(6) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>6) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(7) => grant_signal(7), + grant(8) => grant_signal(8), + grant(9) => grant_signal(9), + grant(10) => grant_signal(10), + grant(11) => grant_signal(11), + grant(12) => grant_signal(12), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(7) =>request_signal(7), + request(8) =>request_signal(8), + request(9) =>request_signal(9), + request(10) =>request_signal(10), + request(11) =>request_signal(11), + request(12) =>request_signal(12) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>6) +PORT MAP( + data_in => Port3_in, + data_in_en => data_in_en(3), + reset => reset, + clk =>clk, + grant(13) => grant_signal(13), + grant(14) => grant_signal(14), + grant(15) => grant_signal(15), + grant(16) => grant_signal(16), + grant(17) => grant_signal(17), + grant(18) => grant_signal(18), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port3, + data_out_pulse =>crossbar_in_pulse3, + request(13) =>request_signal(13), + request(14) =>request_signal(14), + request(15) =>request_signal(15), + request(16) =>request_signal(16), + request(17) =>request_signal(17), + request(18) =>request_signal(18) +); + +PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>6) +PORT MAP( + data_in => Port4_in, + data_in_en => data_in_en(4), + reset => reset, + clk =>clk, + grant(19) => grant_signal(19), + grant(20) => grant_signal(20), + grant(21) => grant_signal(21), + grant(22) => grant_signal(22), + grant(23) => grant_signal(23), + grant(24) => grant_signal(24), + fifo_full =>fifo_in_full(4), + priority_rotation => priority_rotation_signal(4), + fifo_empty => fifo_in_empty(4), + data_out =>crossbar_in_port4, + data_out_pulse =>crossbar_in_pulse4, + request(19) =>request_signal(19), + request(20) =>request_signal(20), + request(21) =>request_signal(21), + request(22) =>request_signal(22), + request(23) =>request_signal(23), + request(24) =>request_signal(24) +); + +PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>6) +PORT MAP( + data_in => Port5_in, + data_in_en => data_in_en(5), + reset => reset, + clk =>clk, + grant(25) => grant_signal(25), + grant(26) => grant_signal(26), + grant(27) => grant_signal(27), + grant(28) => grant_signal(28), + grant(29) => grant_signal(29), + grant(30) => grant_signal(30), + fifo_full =>fifo_in_full(5), + priority_rotation => priority_rotation_signal(5), + fifo_empty => fifo_in_empty(5), + data_out =>crossbar_in_port5, + data_out_pulse =>crossbar_in_pulse5, + request(25) =>request_signal(25), + request(26) =>request_signal(26), + request(27) =>request_signal(27), + request(28) =>request_signal(28), + request(29) =>request_signal(29), + request(30) =>request_signal(30) +); + +PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>6) +PORT MAP( + data_in => Port6_in, + data_in_en => data_in_en(6), + reset => reset, + clk =>clk, + grant(31) => grant_signal(31), + grant(32) => grant_signal(32), + grant(33) => grant_signal(33), + grant(34) => grant_signal(34), + grant(35) => grant_signal(35), + grant(36) => grant_signal(36), + fifo_full =>fifo_in_full(6), + priority_rotation => priority_rotation_signal(6), + fifo_empty => fifo_in_empty(6), + data_out =>crossbar_in_port6, + data_out_pulse =>crossbar_in_pulse6, + request(31) =>request_signal(31), + request(32) =>request_signal(32), + request(33) =>request_signal(33), + request(34) =>request_signal(34), + request(35) =>request_signal(35), + request(36) =>request_signal(36) +); + +end generate switch6x6; + + +-- switch 7 ports +switch7x7 : if number_of_ports = 7 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>7) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + grant(4) => grant_signal(4), + grant(5) => grant_signal(5), + grant(6) => grant_signal(6), + grant(7) => grant_signal(7), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3), + request(4) =>request_signal(4), + request(5) =>request_signal(5), + request(6) =>request_signal(6), + request(7) =>request_signal(7) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>7) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(8) => grant_signal(8), + grant(9) => grant_signal(9), + grant(10) => grant_signal(10), + grant(11) => grant_signal(11), + grant(12) => grant_signal(12), + grant(13) => grant_signal(13), + grant(14) => grant_signal(14), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(8) =>request_signal(8), + request(9) =>request_signal(9), + request(10) =>request_signal(10), + request(11) =>request_signal(11), + request(12) =>request_signal(12), + request(13) =>request_signal(13), + request(14) =>request_signal(14) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>7) +PORT MAP( + data_in => Port3_in, + data_in_en => data_in_en(3), + reset => reset, + clk =>clk, + grant(15) => grant_signal(15), + grant(16) => grant_signal(16), + grant(17) => grant_signal(17), + grant(18) => grant_signal(18), + grant(19) => grant_signal(19), + grant(20) => grant_signal(20), + grant(21) => grant_signal(21), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port3, + data_out_pulse =>crossbar_in_pulse3, + request(15) =>request_signal(15), + request(16) =>request_signal(16), + request(17) =>request_signal(17), + request(18) =>request_signal(18), + request(19) =>request_signal(19), + request(20) =>request_signal(20), + request(21) =>request_signal(21) +); + +PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>7) +PORT MAP( + data_in => Port4_in, + data_in_en => data_in_en(4), + reset => reset, + clk =>clk, + grant(22) => grant_signal(22), + grant(23) => grant_signal(23), + grant(24) => grant_signal(24), + grant(25) => grant_signal(25), + grant(26) => grant_signal(26), + grant(27) => grant_signal(27), + grant(28) => grant_signal(28), + fifo_full =>fifo_in_full(4), + priority_rotation => priority_rotation_signal(4), + fifo_empty => fifo_in_empty(4), + data_out =>crossbar_in_port4, + data_out_pulse =>crossbar_in_pulse4, + request(22) =>request_signal(22), + request(23) =>request_signal(23), + request(24) =>request_signal(24), + request(25) =>request_signal(25), + request(26) =>request_signal(26), + request(27) =>request_signal(27), + request(28) =>request_signal(28) +); + +PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>7) +PORT MAP( + data_in => Port5_in, + data_in_en => data_in_en(5), + reset => reset, + clk =>clk, + grant(29) => grant_signal(29), + grant(30) => grant_signal(30), + grant(31) => grant_signal(31), + grant(32) => grant_signal(32), + grant(33) => grant_signal(33), + grant(34) => grant_signal(34), + grant(35) => grant_signal(35), + fifo_full =>fifo_in_full(5), + priority_rotation => priority_rotation_signal(5), + fifo_empty => fifo_in_empty(5), + data_out =>crossbar_in_port5, + data_out_pulse =>crossbar_in_pulse5, + request(29) =>request_signal(29), + request(30) =>request_signal(30), + request(31) =>request_signal(31), + request(32) =>request_signal(32), + request(33) =>request_signal(33), + request(34) =>request_signal(34), + request(35) =>request_signal(35) +); + +PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>7) +PORT MAP( + data_in => Port6_in, + data_in_en => data_in_en(6), + reset => reset, + clk =>clk, + grant(36) => grant_signal(36), + grant(37) => grant_signal(37), + grant(38) => grant_signal(38), + grant(39) => grant_signal(39), + grant(40) => grant_signal(40), + grant(41) => grant_signal(41), + grant(42) => grant_signal(42), + fifo_full =>fifo_in_full(6), + priority_rotation => priority_rotation_signal(6), + fifo_empty => fifo_in_empty(6), + data_out =>crossbar_in_port6, + data_out_pulse =>crossbar_in_pulse6, + request(36) =>request_signal(36), + request(37) =>request_signal(37), + request(38) =>request_signal(38), + request(39) =>request_signal(39), + request(40) =>request_signal(40), + request(41) =>request_signal(41), + request(42) =>request_signal(42) +); + +PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>7) +PORT MAP( + data_in => Port7_in, + data_in_en => data_in_en(7), + reset => reset, + clk =>clk, + grant(43) => grant_signal(43), + grant(44) => grant_signal(44), + grant(45) => grant_signal(45), + grant(46) => grant_signal(46), + grant(47) => grant_signal(47), + grant(48) => grant_signal(48), + grant(49) => grant_signal(49), + fifo_full =>fifo_in_full(7), + priority_rotation => priority_rotation_signal(7), + fifo_empty => fifo_in_empty(7), + data_out =>crossbar_in_port7, + data_out_pulse =>crossbar_in_pulse7, + request(43) =>request_signal(43), + request(44) =>request_signal(44), + request(45) =>request_signal(45), + request(46) =>request_signal(46), + request(47) =>request_signal(47), + request(48) =>request_signal(48), + request(49) =>request_signal(49) +); + +end generate switch7x7; + + +-- switch 8 ports +switch8x8 : if number_of_ports = 8 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>8) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + grant(4) => grant_signal(4), + grant(5) => grant_signal(5), + grant(6) => grant_signal(6), + grant(7) => grant_signal(7), + grant(8) => grant_signal(8), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3), + request(4) =>request_signal(4), + request(5) =>request_signal(5), + request(6) =>request_signal(6), + request(7) =>request_signal(7), + request(8) =>request_signal(8) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>8) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(1) => grant_signal(9), + grant(2) => grant_signal(10), + grant(3) => grant_signal(11), + grant(4) => grant_signal(12), + grant(5) => grant_signal(13), + grant(6) => grant_signal(14), + grant(7) => grant_signal(15), + grant(8) => grant_signal(16), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(1) =>request_signal(9), + request(2) =>request_signal(10), + request(3) =>request_signal(11), + request(4) =>request_signal(12), + request(5) =>request_signal(13), + request(6) =>request_signal(14), + request(7) =>request_signal(15), + request(8) =>request_signal(16) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>8) +PORT MAP( + data_in => Port3_in, + data_in_en => data_in_en(3), + reset => reset, + clk =>clk, + grant(1) => grant_signal(17), + grant(2) => grant_signal(18), + grant(3) => grant_signal(19), + grant(4) => grant_signal(20), + grant(5) => grant_signal(21), + grant(6) => grant_signal(22), + grant(7) => grant_signal(23), + grant(8) => grant_signal(24), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port3, + data_out_pulse =>crossbar_in_pulse3, + request(1) =>request_signal(17), + request(2) =>request_signal(18), + request(3) =>request_signal(19), + request(4) =>request_signal(20), + request(5) =>request_signal(21), + request(6) =>request_signal(22), + request(7) =>request_signal(23), + request(8) =>request_signal(24) +); + +PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>8) +PORT MAP( + data_in => Port4_in, + data_in_en => data_in_en(4), + reset => reset, + clk =>clk, + grant(1) => grant_signal(25), + grant(2) => grant_signal(26), + grant(3) => grant_signal(27), + grant(4) => grant_signal(28), + grant(5) => grant_signal(29), + grant(6) => grant_signal(30), + grant(7) => grant_signal(31), + grant(8) => grant_signal(32), + fifo_full =>fifo_in_full(4), + priority_rotation => priority_rotation_signal(4), + fifo_empty => fifo_in_empty(4), + data_out =>crossbar_in_port4, + data_out_pulse =>crossbar_in_pulse4, + request(1) =>request_signal(25), + request(2) =>request_signal(26), + request(3) =>request_signal(27), + request(4) =>request_signal(28), + request(5) =>request_signal(29), + request(6) =>request_signal(30), + request(7) =>request_signal(31), + request(8) =>request_signal(32) +); + +PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>8) +PORT MAP( + data_in => Port5_in, + data_in_en => data_in_en(5), + reset => reset, + clk =>clk, + grant(1) => grant_signal(33), + grant(2) => grant_signal(34), + grant(3) => grant_signal(35), + grant(4) => grant_signal(36), + grant(5) => grant_signal(37), + grant(6) => grant_signal(38), + grant(7) => grant_signal(39), + grant(8) => grant_signal(40), + fifo_full =>fifo_in_full(5), + priority_rotation => priority_rotation_signal(5), + fifo_empty => fifo_in_empty(5), + data_out =>crossbar_in_port5, + data_out_pulse =>crossbar_in_pulse5, + request(1) =>request_signal(33), + request(2) =>request_signal(34), + request(3) =>request_signal(35), + request(4) =>request_signal(36), + request(5) =>request_signal(37), + request(6) =>request_signal(38), + request(7) =>request_signal(39), + request(8) =>request_signal(40) +); + +PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>8) +PORT MAP( + data_in => Port6_in, + data_in_en => data_in_en(6), + reset => reset, + clk =>clk, + grant(1) => grant_signal(41), + grant(2) => grant_signal(42), + grant(3) => grant_signal(43), + grant(4) => grant_signal(44), + grant(5) => grant_signal(45), + grant(6) => grant_signal(46), + grant(7) => grant_signal(47), + grant(8) => grant_signal(48), + fifo_full =>fifo_in_full(6), + priority_rotation => priority_rotation_signal(6), + fifo_empty => fifo_in_empty(6), + data_out =>crossbar_in_port6, + data_out_pulse =>crossbar_in_pulse6, + request(1) =>request_signal(41), + request(2) =>request_signal(42), + request(3) =>request_signal(43), + request(4) =>request_signal(44), + request(5) =>request_signal(45), + request(6) =>request_signal(46), + request(7) =>request_signal(47), + request(8) =>request_signal(48) +); + +PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>8) +PORT MAP( + data_in => Port7_in, + data_in_en => data_in_en(7), + reset => reset, + clk =>clk, + grant(1) => grant_signal(49), + grant(2) => grant_signal(50), + grant(3) => grant_signal(51), + grant(4) => grant_signal(52), + grant(5) => grant_signal(53), + grant(6) => grant_signal(54), + grant(7) => grant_signal(55), + grant(8) => grant_signal(56), + fifo_full =>fifo_in_full(7), + priority_rotation => priority_rotation_signal(7), + fifo_empty => fifo_in_empty(7), + data_out =>crossbar_in_port7, + data_out_pulse =>crossbar_in_pulse7, + request(1) =>request_signal(49), + request(2) =>request_signal(50), + request(3) =>request_signal(51), + request(4) =>request_signal(52), + request(5) =>request_signal(53), + request(6) =>request_signal(54), + request(7) =>request_signal(55), + request(8) =>request_signal(56) +); + +PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>8) +PORT MAP( + data_in => Port8_in, + data_in_en => data_in_en(8), + reset => reset, + clk =>clk, + grant(1) => grant_signal(57), + grant(2) => grant_signal(58), + grant(3) => grant_signal(59), + grant(4) => grant_signal(60), + grant(5) => grant_signal(61), + grant(6) => grant_signal(62), + grant(7) => grant_signal(63), + grant(8) => grant_signal(64), + fifo_full =>fifo_in_full(8), + priority_rotation => priority_rotation_signal(8), + fifo_empty => fifo_in_empty(8), + data_out =>crossbar_in_port8, + data_out_pulse =>crossbar_in_pulse8, + request(1) =>request_signal(57), + request(2) =>request_signal(58), + request(3) =>request_signal(59), + request(4) =>request_signal(60), + request(5) =>request_signal(61), + request(6) =>request_signal(62), + request(7) =>request_signal(63), + request(8) =>request_signal(64) +); + +end generate switch8x8; + + +-- switch 9 ports +switch9x9 : if number_of_ports = 9 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>9) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + grant(4) => grant_signal(4), + grant(5) => grant_signal(5), + grant(6) => grant_signal(6), + grant(7) => grant_signal(7), + grant(8) => grant_signal(8), + grant(9) => grant_signal(9), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3), + request(4) =>request_signal(4), + request(5) =>request_signal(5), + request(6) =>request_signal(6), + request(7) =>request_signal(7), + request(8) =>request_signal(8), + request(9) =>request_signal(9) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>9) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(10) => grant_signal(10), + grant(11) => grant_signal(11), + grant(12) => grant_signal(12), + grant(13) => grant_signal(13), + grant(14) => grant_signal(14), + grant(15) => grant_signal(15), + grant(16) => grant_signal(16), + grant(17) => grant_signal(17), + grant(18) => grant_signal(18), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(10) =>request_signal(10), + request(11) =>request_signal(11), + request(12) =>request_signal(12), + request(13) =>request_signal(13), + request(14) =>request_signal(14), + request(15) =>request_signal(15), + request(16) =>request_signal(16), + request(17) =>request_signal(17), + request(18) =>request_signal(18) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>9) +PORT MAP( + data_in => Port3_in, + data_in_en => data_in_en(3), + reset => reset, + clk =>clk, + grant(19) => grant_signal(19), + grant(20) => grant_signal(20), + grant(21) => grant_signal(21), + grant(22) => grant_signal(22), + grant(23) => grant_signal(23), + grant(24) => grant_signal(24), + grant(25) => grant_signal(25), + grant(26) => grant_signal(26), + grant(27) => grant_signal(27), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port3, + data_out_pulse =>crossbar_in_pulse3, + request(19) =>request_signal(19), + request(20) =>request_signal(20), + request(21) =>request_signal(21), + request(22) =>request_signal(22), + request(23) =>request_signal(23), + request(24) =>request_signal(24), + request(25) =>request_signal(25), + request(26) =>request_signal(26), + request(27) =>request_signal(27) +); + +PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>9) +PORT MAP( + data_in => Port4_in, + data_in_en => data_in_en(4), + reset => reset, + clk =>clk, + grant(28) => grant_signal(28), + grant(29) => grant_signal(29), + grant(30) => grant_signal(30), + grant(31) => grant_signal(31), + grant(32) => grant_signal(32), + grant(33) => grant_signal(33), + grant(34) => grant_signal(34), + grant(35) => grant_signal(35), + grant(36) => grant_signal(36), + fifo_full =>fifo_in_full(4), + priority_rotation => priority_rotation_signal(4), + fifo_empty => fifo_in_empty(4), + data_out =>crossbar_in_port4, + data_out_pulse =>crossbar_in_pulse4, + request(28) =>request_signal(28), + request(29) =>request_signal(29), + request(30) =>request_signal(30), + request(31) =>request_signal(31), + request(32) =>request_signal(32), + request(33) =>request_signal(33), + request(34) =>request_signal(34), + request(35) =>request_signal(35), + request(36) =>request_signal(36) +); + +PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>9) +PORT MAP( + data_in => Port5_in, + data_in_en => data_in_en(5), + reset => reset, + clk =>clk, + grant(37) => grant_signal(37), + grant(38) => grant_signal(38), + grant(39) => grant_signal(39), + grant(40) => grant_signal(40), + grant(41) => grant_signal(41), + grant(42) => grant_signal(42), + grant(43) => grant_signal(43), + grant(44) => grant_signal(44), + grant(45) => grant_signal(45), + fifo_full =>fifo_in_full(5), + priority_rotation => priority_rotation_signal(5), + fifo_empty => fifo_in_empty(5), + data_out =>crossbar_in_port5, + data_out_pulse =>crossbar_in_pulse5, + request(37) =>request_signal(37), + request(38) =>request_signal(38), + request(39) =>request_signal(39), + request(40) =>request_signal(40), + request(41) =>request_signal(41), + request(42) =>request_signal(42), + request(43) =>request_signal(43), + request(44) =>request_signal(44), + request(45) =>request_signal(45) +); + +PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>9) +PORT MAP( + data_in => Port6_in, + data_in_en => data_in_en(6), + reset => reset, + clk =>clk, + grant(46) => grant_signal(46), + grant(47) => grant_signal(47), + grant(48) => grant_signal(48), + grant(49) => grant_signal(49), + grant(50) => grant_signal(50), + grant(51) => grant_signal(51), + grant(52) => grant_signal(52), + grant(53) => grant_signal(53), + grant(54) => grant_signal(54), + fifo_full =>fifo_in_full(6), + priority_rotation => priority_rotation_signal(6), + fifo_empty => fifo_in_empty(6), + data_out =>crossbar_in_port6, + data_out_pulse =>crossbar_in_pulse6, + request(46) =>request_signal(46), + request(47) =>request_signal(47), + request(48) =>request_signal(48), + request(49) =>request_signal(49), + request(50) =>request_signal(50), + request(51) =>request_signal(51), + request(52) =>request_signal(52), + request(53) =>request_signal(53), + request(54) =>request_signal(54) +); + +PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>9) +PORT MAP( + data_in => Port7_in, + data_in_en => data_in_en(7), + reset => reset, + clk =>clk, + grant(55) => grant_signal(55), + grant(56) => grant_signal(56), + grant(57) => grant_signal(57), + grant(58) => grant_signal(58), + grant(59) => grant_signal(59), + grant(60) => grant_signal(60), + grant(61) => grant_signal(61), + grant(62) => grant_signal(62), + grant(63) => grant_signal(63), + fifo_full =>fifo_in_full(7), + priority_rotation => priority_rotation_signal(7), + fifo_empty => fifo_in_empty(7), + data_out =>crossbar_in_port7, + data_out_pulse =>crossbar_in_pulse7, + request(55) =>request_signal(55), + request(56) =>request_signal(56), + request(57) =>request_signal(57), + request(58) =>request_signal(58), + request(59) =>request_signal(59), + request(60) =>request_signal(60), + request(61) =>request_signal(61), + request(62) =>request_signal(62), + request(63) =>request_signal(63) +); + +PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>9) +PORT MAP( + data_in => Port8_in, + data_in_en => data_in_en(8), + reset => reset, + clk =>clk, + grant(64) => grant_signal(64), + grant(65) => grant_signal(65), + grant(66) => grant_signal(66), + grant(67) => grant_signal(67), + grant(68) => grant_signal(68), + grant(69) => grant_signal(69), + grant(70) => grant_signal(70), + grant(71) => grant_signal(71), + grant(72) => grant_signal(72), + fifo_full =>fifo_in_full(8), + priority_rotation => priority_rotation_signal(8), + fifo_empty => fifo_in_empty(8), + data_out =>crossbar_in_port8, + data_out_pulse =>crossbar_in_pulse8, + request(64) =>request_signal(64), + request(65) =>request_signal(65), + request(66) =>request_signal(66), + request(67) =>request_signal(67), + request(68) =>request_signal(68), + request(69) =>request_signal(69), + request(70) =>request_signal(70), + request(71) =>request_signal(71), + request(72) =>request_signal(72) +); + +PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>9) +PORT MAP( + data_in => Port9_in, + data_in_en => data_in_en(9), + reset => reset, + clk =>clk, + grant(73) => grant_signal(73), + grant(74) => grant_signal(74), + grant(75) => grant_signal(75), + grant(76) => grant_signal(76), + grant(77) => grant_signal(77), + grant(78) => grant_signal(78), + grant(79) => grant_signal(79), + grant(80) => grant_signal(80), + grant(81) => grant_signal(81), + fifo_full =>fifo_in_full(9), + priority_rotation => priority_rotation_signal(9), + fifo_empty => fifo_in_empty(9), + data_out =>crossbar_in_port9, + data_out_pulse =>crossbar_in_pulse9, + request(73) =>request_signal(73), + request(74) =>request_signal(74), + request(75) =>request_signal(75), + request(76) =>request_signal(76), + request(77) =>request_signal(77), + request(78) =>request_signal(78), + request(79) =>request_signal(79), + request(80) =>request_signal(80), + request(81) =>request_signal(81) +); + +end generate switch9x9; + + +-- switch 10 ports +switch10x10 : if number_of_ports = 10 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>10) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + grant(4) => grant_signal(4), + grant(5) => grant_signal(5), + grant(6) => grant_signal(6), + grant(7) => grant_signal(7), + grant(8) => grant_signal(8), + grant(9) => grant_signal(9), + grant(10) => grant_signal(10), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3), + request(4) =>request_signal(4), + request(5) =>request_signal(5), + request(6) =>request_signal(6), + request(7) =>request_signal(7), + request(8) =>request_signal(8), + request(9) =>request_signal(9), + request(10) =>request_signal(10) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>10) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(11) => grant_signal(11), + grant(12) => grant_signal(12), + grant(13) => grant_signal(13), + grant(14) => grant_signal(14), + grant(15) => grant_signal(15), + grant(16) => grant_signal(16), + grant(17) => grant_signal(17), + grant(18) => grant_signal(18), + grant(19) => grant_signal(19), + grant(20) => grant_signal(20), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(11) =>request_signal(11), + request(12) =>request_signal(12), + request(13) =>request_signal(13), + request(14) =>request_signal(14), + request(15) =>request_signal(15), + request(16) =>request_signal(16), + request(17) =>request_signal(17), + request(18) =>request_signal(18), + request(19) =>request_signal(19), + request(20) =>request_signal(20) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>10) +PORT MAP( + data_in => Port3_in, + data_in_en => data_in_en(3), + reset => reset, + clk =>clk, + grant(21) => grant_signal(21), + grant(22) => grant_signal(22), + grant(23) => grant_signal(23), + grant(24) => grant_signal(24), + grant(25) => grant_signal(25), + grant(26) => grant_signal(26), + grant(27) => grant_signal(27), + grant(28) => grant_signal(28), + grant(29) => grant_signal(29), + grant(30) => grant_signal(30), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port3, + data_out_pulse =>crossbar_in_pulse3, + request(21) =>request_signal(21), + request(22) =>request_signal(22), + request(23) =>request_signal(23), + request(24) =>request_signal(24), + request(25) =>request_signal(25), + request(26) =>request_signal(26), + request(27) =>request_signal(27), + request(28) =>request_signal(28), + request(29) =>request_signal(29), + request(30) =>request_signal(30) +); + +PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>10) +PORT MAP( + data_in => Port4_in, + data_in_en => data_in_en(4), + reset => reset, + clk =>clk, + grant(31) => grant_signal(31), + grant(32) => grant_signal(32), + grant(33) => grant_signal(33), + grant(34) => grant_signal(34), + grant(35) => grant_signal(35), + grant(36) => grant_signal(36), + grant(37) => grant_signal(37), + grant(38) => grant_signal(38), + grant(39) => grant_signal(39), + grant(40) => grant_signal(40), + fifo_full =>fifo_in_full(4), + priority_rotation => priority_rotation_signal(4), + fifo_empty => fifo_in_empty(4), + data_out =>crossbar_in_port4, + data_out_pulse =>crossbar_in_pulse4, + request(31) =>request_signal(31), + request(32) =>request_signal(32), + request(33) =>request_signal(33), + request(34) =>request_signal(34), + request(35) =>request_signal(35), + request(36) =>request_signal(36), + request(37) =>request_signal(37), + request(38) =>request_signal(38), + request(39) =>request_signal(39), + request(40) =>request_signal(40) +); + +PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>10) +PORT MAP( + data_in => Port5_in, + data_in_en => data_in_en(5), + reset => reset, + clk =>clk, + grant(41) => grant_signal(41), + grant(42) => grant_signal(42), + grant(43) => grant_signal(43), + grant(44) => grant_signal(44), + grant(45) => grant_signal(45), + grant(46) => grant_signal(46), + grant(47) => grant_signal(47), + grant(48) => grant_signal(48), + grant(49) => grant_signal(49), + grant(50) => grant_signal(50), + fifo_full =>fifo_in_full(5), + priority_rotation => priority_rotation_signal(5), + fifo_empty => fifo_in_empty(5), + data_out =>crossbar_in_port5, + data_out_pulse =>crossbar_in_pulse5, + request(41) =>request_signal(41), + request(42) =>request_signal(42), + request(43) =>request_signal(43), + request(44) =>request_signal(44), + request(45) =>request_signal(45), + request(46) =>request_signal(46), + request(47) =>request_signal(47), + request(48) =>request_signal(48), + request(49) =>request_signal(49), + request(50) =>request_signal(50) +); + +PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>10) +PORT MAP( + data_in => Port6_in, + data_in_en => data_in_en(6), + reset => reset, + clk =>clk, + grant(51) => grant_signal(51), + grant(52) => grant_signal(52), + grant(53) => grant_signal(53), + grant(54) => grant_signal(54), + grant(55) => grant_signal(55), + grant(56) => grant_signal(56), + grant(57) => grant_signal(57), + grant(58) => grant_signal(58), + grant(59) => grant_signal(59), + grant(60) => grant_signal(60), + fifo_full =>fifo_in_full(6), + priority_rotation => priority_rotation_signal(6), + fifo_empty => fifo_in_empty(6), + data_out =>crossbar_in_port6, + data_out_pulse =>crossbar_in_pulse6, + request(51) =>request_signal(51), + request(52) =>request_signal(52), + request(53) =>request_signal(53), + request(54) =>request_signal(54), + request(55) =>request_signal(55), + request(56) =>request_signal(56), + request(57) =>request_signal(57), + request(58) =>request_signal(58), + request(59) =>request_signal(59), + request(60) =>request_signal(60) +); + +PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>10) +PORT MAP( + data_in => Port7_in, + data_in_en => data_in_en(7), + reset => reset, + clk =>clk, + grant(61) => grant_signal(61), + grant(62) => grant_signal(62), + grant(63) => grant_signal(63), + grant(64) => grant_signal(64), + grant(65) => grant_signal(65), + grant(66) => grant_signal(66), + grant(67) => grant_signal(67), + grant(68) => grant_signal(68), + grant(69) => grant_signal(69), + grant(70) => grant_signal(70), + fifo_full =>fifo_in_full(7), + priority_rotation => priority_rotation_signal(7), + fifo_empty => fifo_in_empty(7), + data_out =>crossbar_in_port7, + data_out_pulse =>crossbar_in_pulse7, + request(61) =>request_signal(61), + request(62) =>request_signal(62), + request(63) =>request_signal(63), + request(64) =>request_signal(64), + request(65) =>request_signal(65), + request(66) =>request_signal(66), + request(67) =>request_signal(67), + request(68) =>request_signal(68), + request(69) =>request_signal(69), + request(70) =>request_signal(70) +); + +PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>10) +PORT MAP( + data_in => Port8_in, + data_in_en => data_in_en(8), + reset => reset, + clk =>clk, + grant(71) => grant_signal(71), + grant(72) => grant_signal(72), + grant(73) => grant_signal(73), + grant(74) => grant_signal(74), + grant(75) => grant_signal(75), + grant(76) => grant_signal(76), + grant(77) => grant_signal(77), + grant(78) => grant_signal(78), + grant(79) => grant_signal(79), + grant(80) => grant_signal(80), + fifo_full =>fifo_in_full(8), + priority_rotation => priority_rotation_signal(8), + fifo_empty => fifo_in_empty(8), + data_out =>crossbar_in_port8, + data_out_pulse =>crossbar_in_pulse8, + request(71) =>request_signal(71), + request(72) =>request_signal(72), + request(73) =>request_signal(73), + request(74) =>request_signal(74), + request(75) =>request_signal(75), + request(76) =>request_signal(76), + request(77) =>request_signal(77), + request(78) =>request_signal(78), + request(79) =>request_signal(79), + request(80) =>request_signal(80) +); + +PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>10) +PORT MAP( + data_in => Port9_in, + data_in_en => data_in_en(9), + reset => reset, + clk =>clk, + grant(81) => grant_signal(81), + grant(82) => grant_signal(82), + grant(83) => grant_signal(83), + grant(84) => grant_signal(84), + grant(85) => grant_signal(85), + grant(86) => grant_signal(86), + grant(87) => grant_signal(87), + grant(88) => grant_signal(88), + grant(89) => grant_signal(89), + grant(90) => grant_signal(90), + fifo_full =>fifo_in_full(9), + priority_rotation => priority_rotation_signal(9), + fifo_empty => fifo_in_empty(9), + data_out =>crossbar_in_port9, + data_out_pulse =>crossbar_in_pulse9, + request(81) =>request_signal(81), + request(82) =>request_signal(82), + request(83) =>request_signal(83), + request(84) =>request_signal(84), + request(85) =>request_signal(85), + request(86) =>request_signal(86), + request(87) =>request_signal(87), + request(88) =>request_signal(88), + request(89) =>request_signal(89), + request(90) =>request_signal(90) +); + +PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>10) +PORT MAP( + data_in => Port10_in, + data_in_en => data_in_en(10), + reset => reset, + clk =>clk, + grant(91) => grant_signal(91), + grant(92) => grant_signal(92), + grant(93) => grant_signal(93), + grant(94) => grant_signal(94), + grant(95) => grant_signal(95), + grant(96) => grant_signal(96), + grant(97) => grant_signal(97), + grant(98) => grant_signal(98), + grant(99) => grant_signal(99), + grant(100) => grant_signal(100), + fifo_full =>fifo_in_full(10), + priority_rotation => priority_rotation_signal(10), + fifo_empty => fifo_in_empty(10), + data_out =>crossbar_in_port10, + data_out_pulse =>crossbar_in_pulse10, + request(91) =>request_signal(91), + request(92) =>request_signal(92), + request(93) =>request_signal(93), + request(94) =>request_signal(94), + request(95) =>request_signal(95), + request(96) =>request_signal(96), + request(97) =>request_signal(97), + request(98) =>request_signal(98), + request(99) =>request_signal(99), + request(100) =>request_signal(100) +); + +end generate switch10x10; + + +-- switch 11 ports +switch11x11 : if number_of_ports = 11 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>11) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + grant(4) => grant_signal(4), + grant(5) => grant_signal(5), + grant(6) => grant_signal(6), + grant(7) => grant_signal(7), + grant(8) => grant_signal(8), + grant(9) => grant_signal(9), + grant(10) => grant_signal(10), + grant(11) => grant_signal(11), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3), + request(4) =>request_signal(4), + request(5) =>request_signal(5), + request(6) =>request_signal(6), + request(7) =>request_signal(7), + request(8) =>request_signal(8), + request(9) =>request_signal(9), + request(10) =>request_signal(10), + request(11) =>request_signal(11) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>11) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(12) => grant_signal(12), + grant(13) => grant_signal(13), + grant(14) => grant_signal(14), + grant(15) => grant_signal(15), + grant(16) => grant_signal(16), + grant(17) => grant_signal(17), + grant(18) => grant_signal(18), + grant(19) => grant_signal(19), + grant(20) => grant_signal(20), + grant(21) => grant_signal(21), + grant(22) => grant_signal(22), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(12) =>request_signal(12), + request(13) =>request_signal(13), + request(14) =>request_signal(14), + request(15) =>request_signal(15), + request(16) =>request_signal(16), + request(17) =>request_signal(17), + request(18) =>request_signal(18), + request(19) =>request_signal(19), + request(20) =>request_signal(20), + request(21) =>request_signal(21), + request(22) =>request_signal(22) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>11) +PORT MAP( + data_in => Port3_in, + data_in_en => data_in_en(3), + reset => reset, + clk =>clk, + grant(23) => grant_signal(23), + grant(24) => grant_signal(24), + grant(25) => grant_signal(25), + grant(26) => grant_signal(26), + grant(27) => grant_signal(27), + grant(28) => grant_signal(28), + grant(29) => grant_signal(29), + grant(30) => grant_signal(30), + grant(31) => grant_signal(31), + grant(32) => grant_signal(32), + grant(33) => grant_signal(33), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port3, + data_out_pulse =>crossbar_in_pulse3, + request(23) =>request_signal(23), + request(24) =>request_signal(24), + request(25) =>request_signal(25), + request(26) =>request_signal(26), + request(27) =>request_signal(27), + request(28) =>request_signal(28), + request(29) =>request_signal(29), + request(30) =>request_signal(30), + request(31) =>request_signal(31), + request(32) =>request_signal(32), + request(33) =>request_signal(33) +); + +PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>11) +PORT MAP( + data_in => Port4_in, + data_in_en => data_in_en(4), + reset => reset, + clk =>clk, + grant(34) => grant_signal(34), + grant(35) => grant_signal(35), + grant(36) => grant_signal(36), + grant(37) => grant_signal(37), + grant(38) => grant_signal(38), + grant(39) => grant_signal(39), + grant(40) => grant_signal(40), + grant(41) => grant_signal(41), + grant(42) => grant_signal(42), + grant(43) => grant_signal(43), + grant(44) => grant_signal(44), + fifo_full =>fifo_in_full(4), + priority_rotation => priority_rotation_signal(4), + fifo_empty => fifo_in_empty(4), + data_out =>crossbar_in_port4, + data_out_pulse =>crossbar_in_pulse4, + request(34) =>request_signal(34), + request(35) =>request_signal(35), + request(36) =>request_signal(36), + request(37) =>request_signal(37), + request(38) =>request_signal(38), + request(39) =>request_signal(39), + request(40) =>request_signal(40), + request(41) =>request_signal(41), + request(42) =>request_signal(42), + request(43) =>request_signal(43), + request(44) =>request_signal(44) +); + +PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>11) +PORT MAP( + data_in => Port5_in, + data_in_en => data_in_en(5), + reset => reset, + clk =>clk, + grant(45) => grant_signal(45), + grant(46) => grant_signal(46), + grant(47) => grant_signal(47), + grant(48) => grant_signal(48), + grant(49) => grant_signal(49), + grant(50) => grant_signal(50), + grant(51) => grant_signal(51), + grant(52) => grant_signal(52), + grant(53) => grant_signal(53), + grant(54) => grant_signal(54), + grant(55) => grant_signal(55), + fifo_full =>fifo_in_full(5), + priority_rotation => priority_rotation_signal(5), + fifo_empty => fifo_in_empty(5), + data_out =>crossbar_in_port5, + data_out_pulse =>crossbar_in_pulse5, + request(45) =>request_signal(45), + request(46) =>request_signal(46), + request(47) =>request_signal(47), + request(48) =>request_signal(48), + request(49) =>request_signal(49), + request(50) =>request_signal(50), + request(51) =>request_signal(51), + request(52) =>request_signal(52), + request(53) =>request_signal(53), + request(54) =>request_signal(54), + request(55) =>request_signal(55) +); + +PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>11) +PORT MAP( + data_in => Port6_in, + data_in_en => data_in_en(6), + reset => reset, + clk =>clk, + grant(56) => grant_signal(56), + grant(57) => grant_signal(57), + grant(58) => grant_signal(58), + grant(59) => grant_signal(59), + grant(60) => grant_signal(60), + grant(61) => grant_signal(61), + grant(62) => grant_signal(62), + grant(63) => grant_signal(63), + grant(64) => grant_signal(64), + grant(65) => grant_signal(65), + grant(66) => grant_signal(66), + fifo_full =>fifo_in_full(6), + priority_rotation => priority_rotation_signal(6), + fifo_empty => fifo_in_empty(6), + data_out =>crossbar_in_port6, + data_out_pulse =>crossbar_in_pulse6, + request(56) =>request_signal(56), + request(57) =>request_signal(57), + request(58) =>request_signal(58), + request(59) =>request_signal(59), + request(60) =>request_signal(60), + request(61) =>request_signal(61), + request(62) =>request_signal(62), + request(63) =>request_signal(63), + request(64) =>request_signal(64), + request(65) =>request_signal(65), + request(66) =>request_signal(66) +); + +PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>11) +PORT MAP( + data_in => Port7_in, + data_in_en => data_in_en(7), + reset => reset, + clk =>clk, + grant(67) => grant_signal(67), + grant(68) => grant_signal(68), + grant(69) => grant_signal(69), + grant(70) => grant_signal(70), + grant(71) => grant_signal(71), + grant(72) => grant_signal(72), + grant(73) => grant_signal(73), + grant(74) => grant_signal(74), + grant(75) => grant_signal(75), + grant(76) => grant_signal(76), + grant(77) => grant_signal(77), + fifo_full =>fifo_in_full(7), + priority_rotation => priority_rotation_signal(7), + fifo_empty => fifo_in_empty(7), + data_out =>crossbar_in_port7, + data_out_pulse =>crossbar_in_pulse7, + request(67) =>request_signal(67), + request(68) =>request_signal(68), + request(69) =>request_signal(69), + request(70) =>request_signal(70), + request(71) =>request_signal(71), + request(72) =>request_signal(72), + request(73) =>request_signal(73), + request(74) =>request_signal(74), + request(75) =>request_signal(75), + request(76) =>request_signal(76), + request(77) =>request_signal(77) +); + +PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>11) +PORT MAP( + data_in => Port8_in, + data_in_en => data_in_en(8), + reset => reset, + clk =>clk, + grant(78) => grant_signal(78), + grant(79) => grant_signal(79), + grant(80) => grant_signal(80), + grant(81) => grant_signal(81), + grant(82) => grant_signal(82), + grant(83) => grant_signal(83), + grant(84) => grant_signal(84), + grant(85) => grant_signal(85), + grant(86) => grant_signal(86), + grant(87) => grant_signal(87), + grant(88) => grant_signal(88), + fifo_full =>fifo_in_full(8), + priority_rotation => priority_rotation_signal(8), + fifo_empty => fifo_in_empty(8), + data_out =>crossbar_in_port8, + data_out_pulse =>crossbar_in_pulse8, + request(78) =>request_signal(78), + request(79) =>request_signal(79), + request(80) =>request_signal(80), + request(81) =>request_signal(81), + request(82) =>request_signal(82), + request(83) =>request_signal(83), + request(84) =>request_signal(84), + request(85) =>request_signal(85), + request(86) =>request_signal(86), + request(87) =>request_signal(87), + request(88) =>request_signal(88) +); + +PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>11) +PORT MAP( + data_in => Port9_in, + data_in_en => data_in_en(9), + reset => reset, + clk =>clk, + grant(89) => grant_signal(89), + grant(90) => grant_signal(90), + grant(91) => grant_signal(91), + grant(92) => grant_signal(92), + grant(93) => grant_signal(93), + grant(94) => grant_signal(94), + grant(95) => grant_signal(95), + grant(96) => grant_signal(96), + grant(97) => grant_signal(97), + grant(98) => grant_signal(98), + grant(99) => grant_signal(99), + fifo_full =>fifo_in_full(9), + priority_rotation => priority_rotation_signal(9), + fifo_empty => fifo_in_empty(9), + data_out =>crossbar_in_port9, + data_out_pulse =>crossbar_in_pulse9, + request(89) =>request_signal(89), + request(90) =>request_signal(90), + request(91) =>request_signal(91), + request(92) =>request_signal(92), + request(93) =>request_signal(93), + request(94) =>request_signal(94), + request(95) =>request_signal(95), + request(96) =>request_signal(96), + request(97) =>request_signal(97), + request(98) =>request_signal(98), + request(99) =>request_signal(99) +); + +PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>11) +PORT MAP( + data_in => Port10_in, + data_in_en => data_in_en(10), + reset => reset, + clk =>clk, + grant(100) => grant_signal(100), + grant(101) => grant_signal(101), + grant(102) => grant_signal(102), + grant(103) => grant_signal(103), + grant(104) => grant_signal(104), + grant(105) => grant_signal(105), + grant(106) => grant_signal(106), + grant(107) => grant_signal(107), + grant(108) => grant_signal(108), + grant(109) => grant_signal(109), + grant(110) => grant_signal(110), + fifo_full =>fifo_in_full(10), + priority_rotation => priority_rotation_signal(10), + fifo_empty => fifo_in_empty(10), + data_out =>crossbar_in_port10, + data_out_pulse =>crossbar_in_pulse10, + request(100) =>request_signal(100), + request(101) =>request_signal(101), + request(102) =>request_signal(102), + request(103) =>request_signal(103), + request(104) =>request_signal(104), + request(105) =>request_signal(105), + request(106) =>request_signal(106), + request(107) =>request_signal(107), + request(108) =>request_signal(108), + request(109) =>request_signal(109), + request(110) =>request_signal(110) +); + +PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>11) +PORT MAP( + data_in => Port11_in, + data_in_en => data_in_en(11), + reset => reset, + clk =>clk, + grant(111) => grant_signal(111), + grant(112) => grant_signal(112), + grant(113) => grant_signal(113), + grant(114) => grant_signal(114), + grant(115) => grant_signal(115), + grant(116) => grant_signal(116), + grant(117) => grant_signal(117), + grant(118) => grant_signal(118), + grant(119) => grant_signal(119), + grant(120) => grant_signal(120), + grant(121) => grant_signal(121), + fifo_full =>fifo_in_full(11), + priority_rotation => priority_rotation_signal(11), + fifo_empty => fifo_in_empty(11), + data_out =>crossbar_in_port11, + data_out_pulse =>crossbar_in_pulse11, + request(111) =>request_signal(111), + request(112) =>request_signal(112), + request(113) =>request_signal(113), + request(114) =>request_signal(114), + request(115) =>request_signal(115), + request(116) =>request_signal(116), + request(117) =>request_signal(117), + request(118) =>request_signal(118), + request(119) =>request_signal(119), + request(120) =>request_signal(120), + request(121) =>request_signal(121) +); + +end generate switch11x11; + + +-- switch 12 ports +switch12x12 : if number_of_ports = 12 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>12) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + grant(4) => grant_signal(4), + grant(5) => grant_signal(5), + grant(6) => grant_signal(6), + grant(7) => grant_signal(7), + grant(8) => grant_signal(8), + grant(9) => grant_signal(9), + grant(10) => grant_signal(10), + grant(11) => grant_signal(11), + grant(12) => grant_signal(12), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3), + request(4) =>request_signal(4), + request(5) =>request_signal(5), + request(6) =>request_signal(6), + request(7) =>request_signal(7), + request(8) =>request_signal(8), + request(9) =>request_signal(9), + request(10) =>request_signal(10), + request(11) =>request_signal(11), + request(12) =>request_signal(12) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>12) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(13) => grant_signal(13), + grant(14) => grant_signal(14), + grant(15) => grant_signal(15), + grant(16) => grant_signal(16), + grant(17) => grant_signal(17), + grant(18) => grant_signal(18), + grant(19) => grant_signal(19), + grant(20) => grant_signal(20), + grant(21) => grant_signal(21), + grant(22) => grant_signal(22), + grant(23) => grant_signal(23), + grant(24) => grant_signal(24), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(13) =>request_signal(13), + request(14) =>request_signal(14), + request(15) =>request_signal(15), + request(16) =>request_signal(16), + request(17) =>request_signal(17), + request(18) =>request_signal(18), + request(19) =>request_signal(19), + request(20) =>request_signal(20), + request(21) =>request_signal(21), + request(22) =>request_signal(22), + request(23) =>request_signal(23), + request(24) =>request_signal(24) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>12) +PORT MAP( + data_in => Port3_in, + data_in_en => data_in_en(3), + reset => reset, + clk =>clk, + grant(25) => grant_signal(25), + grant(26) => grant_signal(26), + grant(27) => grant_signal(27), + grant(28) => grant_signal(28), + grant(29) => grant_signal(29), + grant(30) => grant_signal(30), + grant(31) => grant_signal(31), + grant(32) => grant_signal(32), + grant(33) => grant_signal(33), + grant(34) => grant_signal(34), + grant(35) => grant_signal(35), + grant(36) => grant_signal(36), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port3, + data_out_pulse =>crossbar_in_pulse3, + request(25) =>request_signal(25), + request(26) =>request_signal(26), + request(27) =>request_signal(27), + request(28) =>request_signal(28), + request(29) =>request_signal(29), + request(30) =>request_signal(30), + request(31) =>request_signal(31), + request(32) =>request_signal(32), + request(33) =>request_signal(33), + request(34) =>request_signal(34), + request(35) =>request_signal(35), + request(36) =>request_signal(36) +); + +PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>12) +PORT MAP( + data_in => Port4_in, + data_in_en => data_in_en(4), + reset => reset, + clk =>clk, + grant(37) => grant_signal(37), + grant(38) => grant_signal(38), + grant(39) => grant_signal(39), + grant(40) => grant_signal(40), + grant(41) => grant_signal(41), + grant(42) => grant_signal(42), + grant(43) => grant_signal(43), + grant(44) => grant_signal(44), + grant(45) => grant_signal(45), + grant(46) => grant_signal(46), + grant(47) => grant_signal(47), + grant(48) => grant_signal(48), + fifo_full =>fifo_in_full(4), + priority_rotation => priority_rotation_signal(4), + fifo_empty => fifo_in_empty(4), + data_out =>crossbar_in_port4, + data_out_pulse =>crossbar_in_pulse4, + request(37) =>request_signal(37), + request(38) =>request_signal(38), + request(39) =>request_signal(39), + request(40) =>request_signal(40), + request(41) =>request_signal(41), + request(42) =>request_signal(42), + request(43) =>request_signal(43), + request(44) =>request_signal(44), + request(45) =>request_signal(45), + request(46) =>request_signal(46), + request(47) =>request_signal(47), + request(48) =>request_signal(48) +); + +PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>12) +PORT MAP( + data_in => Port5_in, + data_in_en => data_in_en(5), + reset => reset, + clk =>clk, + grant(49) => grant_signal(49), + grant(50) => grant_signal(50), + grant(51) => grant_signal(51), + grant(52) => grant_signal(52), + grant(53) => grant_signal(53), + grant(54) => grant_signal(54), + grant(55) => grant_signal(55), + grant(56) => grant_signal(56), + grant(57) => grant_signal(57), + grant(58) => grant_signal(58), + grant(59) => grant_signal(59), + grant(60) => grant_signal(60), + fifo_full =>fifo_in_full(5), + priority_rotation => priority_rotation_signal(5), + fifo_empty => fifo_in_empty(5), + data_out =>crossbar_in_port5, + data_out_pulse =>crossbar_in_pulse5, + request(49) =>request_signal(49), + request(50) =>request_signal(50), + request(51) =>request_signal(51), + request(52) =>request_signal(52), + request(53) =>request_signal(53), + request(54) =>request_signal(54), + request(55) =>request_signal(55), + request(56) =>request_signal(56), + request(57) =>request_signal(57), + request(58) =>request_signal(58), + request(59) =>request_signal(59), + request(60) =>request_signal(60) +); + +PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>12) +PORT MAP( + data_in => Port6_in, + data_in_en => data_in_en(6), + reset => reset, + clk =>clk, + grant(61) => grant_signal(61), + grant(62) => grant_signal(62), + grant(63) => grant_signal(63), + grant(64) => grant_signal(64), + grant(65) => grant_signal(65), + grant(66) => grant_signal(66), + grant(67) => grant_signal(67), + grant(68) => grant_signal(68), + grant(69) => grant_signal(69), + grant(70) => grant_signal(70), + grant(71) => grant_signal(71), + grant(72) => grant_signal(72), + fifo_full =>fifo_in_full(6), + priority_rotation => priority_rotation_signal(6), + fifo_empty => fifo_in_empty(6), + data_out =>crossbar_in_port6, + data_out_pulse =>crossbar_in_pulse6, + request(61) =>request_signal(61), + request(62) =>request_signal(62), + request(63) =>request_signal(63), + request(64) =>request_signal(64), + request(65) =>request_signal(65), + request(66) =>request_signal(66), + request(67) =>request_signal(67), + request(68) =>request_signal(68), + request(69) =>request_signal(69), + request(70) =>request_signal(70), + request(71) =>request_signal(71), + request(72) =>request_signal(72) +); + +PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>12) +PORT MAP( + data_in => Port7_in, + data_in_en => data_in_en(7), + reset => reset, + clk =>clk, + grant(73) => grant_signal(73), + grant(74) => grant_signal(74), + grant(75) => grant_signal(75), + grant(76) => grant_signal(76), + grant(77) => grant_signal(77), + grant(78) => grant_signal(78), + grant(79) => grant_signal(79), + grant(80) => grant_signal(80), + grant(81) => grant_signal(81), + grant(82) => grant_signal(82), + grant(83) => grant_signal(83), + grant(84) => grant_signal(84), + fifo_full =>fifo_in_full(7), + priority_rotation => priority_rotation_signal(7), + fifo_empty => fifo_in_empty(7), + data_out =>crossbar_in_port7, + data_out_pulse =>crossbar_in_pulse7, + request(73) =>request_signal(73), + request(74) =>request_signal(74), + request(75) =>request_signal(75), + request(76) =>request_signal(76), + request(77) =>request_signal(77), + request(78) =>request_signal(78), + request(79) =>request_signal(79), + request(80) =>request_signal(80), + request(81) =>request_signal(81), + request(82) =>request_signal(82), + request(83) =>request_signal(83), + request(84) =>request_signal(84) +); + +PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>12) +PORT MAP( + data_in => Port8_in, + data_in_en => data_in_en(8), + reset => reset, + clk =>clk, + grant(85) => grant_signal(85), + grant(86) => grant_signal(86), + grant(87) => grant_signal(87), + grant(88) => grant_signal(88), + grant(89) => grant_signal(89), + grant(90) => grant_signal(90), + grant(91) => grant_signal(91), + grant(92) => grant_signal(92), + grant(93) => grant_signal(93), + grant(94) => grant_signal(94), + grant(95) => grant_signal(95), + grant(96) => grant_signal(96), + fifo_full =>fifo_in_full(8), + priority_rotation => priority_rotation_signal(8), + fifo_empty => fifo_in_empty(8), + data_out =>crossbar_in_port8, + data_out_pulse =>crossbar_in_pulse8, + request(85) =>request_signal(85), + request(86) =>request_signal(86), + request(87) =>request_signal(87), + request(88) =>request_signal(88), + request(89) =>request_signal(89), + request(90) =>request_signal(90), + request(91) =>request_signal(91), + request(92) =>request_signal(92), + request(93) =>request_signal(93), + request(94) =>request_signal(94), + request(95) =>request_signal(95), + request(96) =>request_signal(96) +); + +PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>12) +PORT MAP( + data_in => Port9_in, + data_in_en => data_in_en(9), + reset => reset, + clk =>clk, + grant(97) => grant_signal(97), + grant(98) => grant_signal(98), + grant(99) => grant_signal(99), + grant(100) => grant_signal(100), + grant(101) => grant_signal(101), + grant(102) => grant_signal(102), + grant(103) => grant_signal(103), + grant(104) => grant_signal(104), + grant(105) => grant_signal(105), + grant(106) => grant_signal(106), + grant(107) => grant_signal(107), + grant(108) => grant_signal(108), + fifo_full =>fifo_in_full(9), + priority_rotation => priority_rotation_signal(9), + fifo_empty => fifo_in_empty(9), + data_out =>crossbar_in_port9, + data_out_pulse =>crossbar_in_pulse9, + request(97) =>request_signal(97), + request(98) =>request_signal(98), + request(99) =>request_signal(99), + request(100) =>request_signal(100), + request(101) =>request_signal(101), + request(102) =>request_signal(102), + request(103) =>request_signal(103), + request(104) =>request_signal(104), + request(105) =>request_signal(105), + request(106) =>request_signal(106), + request(107) =>request_signal(107), + request(108) =>request_signal(108) +); + +PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>12) +PORT MAP( + data_in => Port10_in, + data_in_en => data_in_en(10), + reset => reset, + clk =>clk, + grant(109) => grant_signal(109), + grant(110) => grant_signal(110), + grant(111) => grant_signal(111), + grant(112) => grant_signal(112), + grant(113) => grant_signal(113), + grant(114) => grant_signal(114), + grant(115) => grant_signal(115), + grant(116) => grant_signal(116), + grant(117) => grant_signal(117), + grant(118) => grant_signal(118), + grant(119) => grant_signal(119), + grant(120) => grant_signal(120), + fifo_full =>fifo_in_full(10), + priority_rotation => priority_rotation_signal(10), + fifo_empty => fifo_in_empty(10), + data_out =>crossbar_in_port10, + data_out_pulse =>crossbar_in_pulse10, + request(109) =>request_signal(109), + request(110) =>request_signal(110), + request(111) =>request_signal(111), + request(112) =>request_signal(112), + request(113) =>request_signal(113), + request(114) =>request_signal(114), + request(115) =>request_signal(115), + request(116) =>request_signal(116), + request(117) =>request_signal(117), + request(118) =>request_signal(118), + request(119) =>request_signal(119), + request(120) =>request_signal(120) +); + +PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>12) +PORT MAP( + data_in => Port11_in, + data_in_en => data_in_en(11), + reset => reset, + clk =>clk, + grant(121) => grant_signal(121), + grant(122) => grant_signal(122), + grant(123) => grant_signal(123), + grant(124) => grant_signal(124), + grant(125) => grant_signal(125), + grant(126) => grant_signal(126), + grant(127) => grant_signal(127), + grant(128) => grant_signal(128), + grant(129) => grant_signal(129), + grant(130) => grant_signal(130), + grant(131) => grant_signal(131), + grant(132) => grant_signal(132), + fifo_full =>fifo_in_full(11), + priority_rotation => priority_rotation_signal(11), + fifo_empty => fifo_in_empty(11), + data_out =>crossbar_in_port11, + data_out_pulse =>crossbar_in_pulse11, + request(121) =>request_signal(121), + request(122) =>request_signal(122), + request(123) =>request_signal(123), + request(124) =>request_signal(124), + request(125) =>request_signal(125), + request(126) =>request_signal(126), + request(127) =>request_signal(127), + request(128) =>request_signal(128), + request(129) =>request_signal(129), + request(130) =>request_signal(130), + request(131) =>request_signal(131), + request(132) =>request_signal(132) +); + +PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>12) +PORT MAP( + data_in => Port12_in, + data_in_en => data_in_en(12), + reset => reset, + clk =>clk, + grant(133) => grant_signal(133), + grant(134) => grant_signal(134), + grant(135) => grant_signal(135), + grant(136) => grant_signal(136), + grant(137) => grant_signal(137), + grant(138) => grant_signal(138), + grant(139) => grant_signal(139), + grant(140) => grant_signal(140), + grant(141) => grant_signal(141), + grant(142) => grant_signal(142), + grant(143) => grant_signal(143), + grant(144) => grant_signal(144), + fifo_full =>fifo_in_full(12), + priority_rotation => priority_rotation_signal(12), + fifo_empty => fifo_in_empty(12), + data_out =>crossbar_in_port12, + data_out_pulse =>crossbar_in_pulse12, + request(133) =>request_signal(133), + request(134) =>request_signal(134), + request(135) =>request_signal(135), + request(136) =>request_signal(136), + request(137) =>request_signal(137), + request(138) =>request_signal(138), + request(139) =>request_signal(139), + request(140) =>request_signal(140), + request(141) =>request_signal(141), + request(142) =>request_signal(142), + request(143) =>request_signal(143), + request(144) =>request_signal(144) +); + +end generate switch12x12; + + +-- switch 13 ports +switch13x13 : if number_of_ports = 13 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>13) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + grant(4) => grant_signal(4), + grant(5) => grant_signal(5), + grant(6) => grant_signal(6), + grant(7) => grant_signal(7), + grant(8) => grant_signal(8), + grant(9) => grant_signal(9), + grant(10) => grant_signal(10), + grant(11) => grant_signal(11), + grant(12) => grant_signal(12), + grant(13) => grant_signal(13), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3), + request(4) =>request_signal(4), + request(5) =>request_signal(5), + request(6) =>request_signal(6), + request(7) =>request_signal(7), + request(8) =>request_signal(8), + request(9) =>request_signal(9), + request(10) =>request_signal(10), + request(11) =>request_signal(11), + request(12) =>request_signal(12), + request(13) =>request_signal(13) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>13) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(14) => grant_signal(14), + grant(15) => grant_signal(15), + grant(16) => grant_signal(16), + grant(17) => grant_signal(17), + grant(18) => grant_signal(18), + grant(19) => grant_signal(19), + grant(20) => grant_signal(20), + grant(21) => grant_signal(21), + grant(22) => grant_signal(22), + grant(23) => grant_signal(23), + grant(24) => grant_signal(24), + grant(25) => grant_signal(25), + grant(26) => grant_signal(26), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(14) =>request_signal(14), + request(15) =>request_signal(15), + request(16) =>request_signal(16), + request(17) =>request_signal(17), + request(18) =>request_signal(18), + request(19) =>request_signal(19), + request(20) =>request_signal(20), + request(21) =>request_signal(21), + request(22) =>request_signal(22), + request(23) =>request_signal(23), + request(24) =>request_signal(24), + request(25) =>request_signal(25), + request(26) =>request_signal(26) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>13) +PORT MAP( + data_in => Port3_in, + data_in_en => data_in_en(3), + reset => reset, + clk =>clk, + grant(27) => grant_signal(27), + grant(28) => grant_signal(28), + grant(29) => grant_signal(29), + grant(30) => grant_signal(30), + grant(31) => grant_signal(31), + grant(32) => grant_signal(32), + grant(33) => grant_signal(33), + grant(34) => grant_signal(34), + grant(35) => grant_signal(35), + grant(36) => grant_signal(36), + grant(37) => grant_signal(37), + grant(38) => grant_signal(38), + grant(39) => grant_signal(39), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port3, + data_out_pulse =>crossbar_in_pulse3, + request(27) =>request_signal(27), + request(28) =>request_signal(28), + request(29) =>request_signal(29), + request(30) =>request_signal(30), + request(31) =>request_signal(31), + request(32) =>request_signal(32), + request(33) =>request_signal(33), + request(34) =>request_signal(34), + request(35) =>request_signal(35), + request(36) =>request_signal(36), + request(37) =>request_signal(37), + request(38) =>request_signal(38), + request(39) =>request_signal(39) +); + +PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>13) +PORT MAP( + data_in => Port4_in, + data_in_en => data_in_en(4), + reset => reset, + clk =>clk, + grant(40) => grant_signal(40), + grant(41) => grant_signal(41), + grant(42) => grant_signal(42), + grant(43) => grant_signal(43), + grant(44) => grant_signal(44), + grant(45) => grant_signal(45), + grant(46) => grant_signal(46), + grant(47) => grant_signal(47), + grant(48) => grant_signal(48), + grant(49) => grant_signal(49), + grant(50) => grant_signal(50), + grant(51) => grant_signal(51), + grant(52) => grant_signal(52), + fifo_full =>fifo_in_full(4), + priority_rotation => priority_rotation_signal(4), + fifo_empty => fifo_in_empty(4), + data_out =>crossbar_in_port4, + data_out_pulse =>crossbar_in_pulse4, + request(40) =>request_signal(40), + request(41) =>request_signal(41), + request(42) =>request_signal(42), + request(43) =>request_signal(43), + request(44) =>request_signal(44), + request(45) =>request_signal(45), + request(46) =>request_signal(46), + request(47) =>request_signal(47), + request(48) =>request_signal(48), + request(49) =>request_signal(49), + request(50) =>request_signal(50), + request(51) =>request_signal(51), + request(52) =>request_signal(52) +); + +PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>13) +PORT MAP( + data_in => Port5_in, + data_in_en => data_in_en(5), + reset => reset, + clk =>clk, + grant(53) => grant_signal(53), + grant(54) => grant_signal(54), + grant(55) => grant_signal(55), + grant(56) => grant_signal(56), + grant(57) => grant_signal(57), + grant(58) => grant_signal(58), + grant(59) => grant_signal(59), + grant(60) => grant_signal(60), + grant(61) => grant_signal(61), + grant(62) => grant_signal(62), + grant(63) => grant_signal(63), + grant(64) => grant_signal(64), + grant(65) => grant_signal(65), + fifo_full =>fifo_in_full(5), + priority_rotation => priority_rotation_signal(5), + fifo_empty => fifo_in_empty(5), + data_out =>crossbar_in_port5, + data_out_pulse =>crossbar_in_pulse5, + request(53) =>request_signal(53), + request(54) =>request_signal(54), + request(55) =>request_signal(55), + request(56) =>request_signal(56), + request(57) =>request_signal(57), + request(58) =>request_signal(58), + request(59) =>request_signal(59), + request(60) =>request_signal(60), + request(61) =>request_signal(61), + request(62) =>request_signal(62), + request(63) =>request_signal(63), + request(64) =>request_signal(64), + request(65) =>request_signal(65) +); + +PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>13) +PORT MAP( + data_in => Port6_in, + data_in_en => data_in_en(6), + reset => reset, + clk =>clk, + grant(66) => grant_signal(66), + grant(67) => grant_signal(67), + grant(68) => grant_signal(68), + grant(69) => grant_signal(69), + grant(70) => grant_signal(70), + grant(71) => grant_signal(71), + grant(72) => grant_signal(72), + grant(73) => grant_signal(73), + grant(74) => grant_signal(74), + grant(75) => grant_signal(75), + grant(76) => grant_signal(76), + grant(77) => grant_signal(77), + grant(78) => grant_signal(78), + fifo_full =>fifo_in_full(6), + priority_rotation => priority_rotation_signal(6), + fifo_empty => fifo_in_empty(6), + data_out =>crossbar_in_port6, + data_out_pulse =>crossbar_in_pulse6, + request(66) =>request_signal(66), + request(67) =>request_signal(67), + request(68) =>request_signal(68), + request(69) =>request_signal(69), + request(70) =>request_signal(70), + request(71) =>request_signal(71), + request(72) =>request_signal(72), + request(73) =>request_signal(73), + request(74) =>request_signal(74), + request(75) =>request_signal(75), + request(76) =>request_signal(76), + request(77) =>request_signal(77), + request(78) =>request_signal(78) +); + +PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>13) +PORT MAP( + data_in => Port7_in, + data_in_en => data_in_en(7), + reset => reset, + clk =>clk, + grant(79) => grant_signal(79), + grant(80) => grant_signal(80), + grant(81) => grant_signal(81), + grant(82) => grant_signal(82), + grant(83) => grant_signal(83), + grant(84) => grant_signal(84), + grant(85) => grant_signal(85), + grant(86) => grant_signal(86), + grant(87) => grant_signal(87), + grant(88) => grant_signal(88), + grant(89) => grant_signal(89), + grant(90) => grant_signal(90), + grant(91) => grant_signal(91), + fifo_full =>fifo_in_full(7), + priority_rotation => priority_rotation_signal(7), + fifo_empty => fifo_in_empty(7), + data_out =>crossbar_in_port7, + data_out_pulse =>crossbar_in_pulse7, + request(79) =>request_signal(79), + request(80) =>request_signal(80), + request(81) =>request_signal(81), + request(82) =>request_signal(82), + request(83) =>request_signal(83), + request(84) =>request_signal(84), + request(85) =>request_signal(85), + request(86) =>request_signal(86), + request(87) =>request_signal(87), + request(88) =>request_signal(88), + request(89) =>request_signal(89), + request(90) =>request_signal(90), + request(91) =>request_signal(91) +); + +PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>13) +PORT MAP( + data_in => Port8_in, + data_in_en => data_in_en(8), + reset => reset, + clk =>clk, + grant(92) => grant_signal(92), + grant(93) => grant_signal(93), + grant(94) => grant_signal(94), + grant(95) => grant_signal(95), + grant(96) => grant_signal(96), + grant(97) => grant_signal(97), + grant(98) => grant_signal(98), + grant(99) => grant_signal(99), + grant(100) => grant_signal(100), + grant(101) => grant_signal(101), + grant(102) => grant_signal(102), + grant(103) => grant_signal(103), + grant(104) => grant_signal(104), + fifo_full =>fifo_in_full(8), + priority_rotation => priority_rotation_signal(8), + fifo_empty => fifo_in_empty(8), + data_out =>crossbar_in_port8, + data_out_pulse =>crossbar_in_pulse8, + request(92) =>request_signal(92), + request(93) =>request_signal(93), + request(94) =>request_signal(94), + request(95) =>request_signal(95), + request(96) =>request_signal(96), + request(97) =>request_signal(97), + request(98) =>request_signal(98), + request(99) =>request_signal(99), + request(100) =>request_signal(100), + request(101) =>request_signal(101), + request(102) =>request_signal(102), + request(103) =>request_signal(103), + request(104) =>request_signal(104) +); + +PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>13) +PORT MAP( + data_in => Port9_in, + data_in_en => data_in_en(9), + reset => reset, + clk =>clk, + grant(105) => grant_signal(105), + grant(106) => grant_signal(106), + grant(107) => grant_signal(107), + grant(108) => grant_signal(108), + grant(109) => grant_signal(109), + grant(110) => grant_signal(110), + grant(111) => grant_signal(111), + grant(112) => grant_signal(112), + grant(113) => grant_signal(113), + grant(114) => grant_signal(114), + grant(115) => grant_signal(115), + grant(116) => grant_signal(116), + grant(117) => grant_signal(117), + fifo_full =>fifo_in_full(9), + priority_rotation => priority_rotation_signal(9), + fifo_empty => fifo_in_empty(9), + data_out =>crossbar_in_port9, + data_out_pulse =>crossbar_in_pulse9, + request(105) =>request_signal(105), + request(106) =>request_signal(106), + request(107) =>request_signal(107), + request(108) =>request_signal(108), + request(109) =>request_signal(109), + request(110) =>request_signal(110), + request(111) =>request_signal(111), + request(112) =>request_signal(112), + request(113) =>request_signal(113), + request(114) =>request_signal(114), + request(115) =>request_signal(115), + request(116) =>request_signal(116), + request(117) =>request_signal(117) +); + +PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>13) +PORT MAP( + data_in => Port10_in, + data_in_en => data_in_en(10), + reset => reset, + clk =>clk, + grant(118) => grant_signal(118), + grant(119) => grant_signal(119), + grant(120) => grant_signal(120), + grant(121) => grant_signal(121), + grant(122) => grant_signal(122), + grant(123) => grant_signal(123), + grant(124) => grant_signal(124), + grant(125) => grant_signal(125), + grant(126) => grant_signal(126), + grant(127) => grant_signal(127), + grant(128) => grant_signal(128), + grant(129) => grant_signal(129), + grant(130) => grant_signal(130), + fifo_full =>fifo_in_full(10), + priority_rotation => priority_rotation_signal(10), + fifo_empty => fifo_in_empty(10), + data_out =>crossbar_in_port10, + data_out_pulse =>crossbar_in_pulse10, + request(118) =>request_signal(118), + request(119) =>request_signal(119), + request(120) =>request_signal(120), + request(121) =>request_signal(121), + request(122) =>request_signal(122), + request(123) =>request_signal(123), + request(124) =>request_signal(124), + request(125) =>request_signal(125), + request(126) =>request_signal(126), + request(127) =>request_signal(127), + request(128) =>request_signal(128), + request(129) =>request_signal(129), + request(130) =>request_signal(130) +); + +PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>13) +PORT MAP( + data_in => Port11_in, + data_in_en => data_in_en(11), + reset => reset, + clk =>clk, + grant(131) => grant_signal(131), + grant(132) => grant_signal(132), + grant(133) => grant_signal(133), + grant(134) => grant_signal(134), + grant(135) => grant_signal(135), + grant(136) => grant_signal(136), + grant(137) => grant_signal(137), + grant(138) => grant_signal(138), + grant(139) => grant_signal(139), + grant(140) => grant_signal(140), + grant(141) => grant_signal(141), + grant(142) => grant_signal(142), + grant(143) => grant_signal(143), + fifo_full =>fifo_in_full(11), + priority_rotation => priority_rotation_signal(11), + fifo_empty => fifo_in_empty(11), + data_out =>crossbar_in_port11, + data_out_pulse =>crossbar_in_pulse11, + request(131) =>request_signal(131), + request(132) =>request_signal(132), + request(133) =>request_signal(133), + request(134) =>request_signal(134), + request(135) =>request_signal(135), + request(136) =>request_signal(136), + request(137) =>request_signal(137), + request(138) =>request_signal(138), + request(139) =>request_signal(139), + request(140) =>request_signal(140), + request(141) =>request_signal(141), + request(142) =>request_signal(142), + request(143) =>request_signal(143) +); + +PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>13) +PORT MAP( + data_in => Port12_in, + data_in_en => data_in_en(12), + reset => reset, + clk =>clk, + grant(144) => grant_signal(144), + grant(145) => grant_signal(145), + grant(146) => grant_signal(146), + grant(147) => grant_signal(147), + grant(148) => grant_signal(148), + grant(149) => grant_signal(149), + grant(150) => grant_signal(150), + grant(151) => grant_signal(151), + grant(152) => grant_signal(152), + grant(153) => grant_signal(153), + grant(154) => grant_signal(154), + grant(155) => grant_signal(155), + grant(156) => grant_signal(156), + fifo_full =>fifo_in_full(12), + priority_rotation => priority_rotation_signal(12), + fifo_empty => fifo_in_empty(12), + data_out =>crossbar_in_port12, + data_out_pulse =>crossbar_in_pulse12, + request(144) =>request_signal(144), + request(145) =>request_signal(145), + request(146) =>request_signal(146), + request(147) =>request_signal(147), + request(148) =>request_signal(148), + request(149) =>request_signal(149), + request(150) =>request_signal(150), + request(151) =>request_signal(151), + request(152) =>request_signal(152), + request(153) =>request_signal(153), + request(154) =>request_signal(154), + request(155) =>request_signal(155), + request(156) =>request_signal(156) +); + +PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>13) +PORT MAP( + data_in => Port13_in, + data_in_en => data_in_en(13), + reset => reset, + clk =>clk, + grant(157) => grant_signal(157), + grant(158) => grant_signal(158), + grant(159) => grant_signal(159), + grant(160) => grant_signal(160), + grant(161) => grant_signal(161), + grant(162) => grant_signal(162), + grant(163) => grant_signal(163), + grant(164) => grant_signal(164), + grant(165) => grant_signal(165), + grant(166) => grant_signal(166), + grant(167) => grant_signal(167), + grant(168) => grant_signal(168), + grant(169) => grant_signal(169), + fifo_full =>fifo_in_full(13), + priority_rotation => priority_rotation_signal(13), + fifo_empty => fifo_in_empty(13), + data_out =>crossbar_in_port13, + data_out_pulse =>crossbar_in_pulse13, + request(157) =>request_signal(157), + request(158) =>request_signal(158), + request(159) =>request_signal(159), + request(160) =>request_signal(160), + request(161) =>request_signal(161), + request(162) =>request_signal(162), + request(163) =>request_signal(163), + request(164) =>request_signal(164), + request(165) =>request_signal(165), + request(166) =>request_signal(166), + request(167) =>request_signal(167), + request(168) =>request_signal(168), + request(169) =>request_signal(169) +); + +end generate switch13x13; + + +-- switch 14 ports +switch14x14 : if number_of_ports = 14 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>14) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + grant(4) => grant_signal(4), + grant(5) => grant_signal(5), + grant(6) => grant_signal(6), + grant(7) => grant_signal(7), + grant(8) => grant_signal(8), + grant(9) => grant_signal(9), + grant(10) => grant_signal(10), + grant(11) => grant_signal(11), + grant(12) => grant_signal(12), + grant(13) => grant_signal(13), + grant(14) => grant_signal(14), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3), + request(4) =>request_signal(4), + request(5) =>request_signal(5), + request(6) =>request_signal(6), + request(7) =>request_signal(7), + request(8) =>request_signal(8), + request(9) =>request_signal(9), + request(10) =>request_signal(10), + request(11) =>request_signal(11), + request(12) =>request_signal(12), + request(13) =>request_signal(13), + request(14) =>request_signal(14) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>14) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(15) => grant_signal(15), + grant(16) => grant_signal(16), + grant(17) => grant_signal(17), + grant(18) => grant_signal(18), + grant(19) => grant_signal(19), + grant(20) => grant_signal(20), + grant(21) => grant_signal(21), + grant(22) => grant_signal(22), + grant(23) => grant_signal(23), + grant(24) => grant_signal(24), + grant(25) => grant_signal(25), + grant(26) => grant_signal(26), + grant(27) => grant_signal(27), + grant(28) => grant_signal(28), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(15) =>request_signal(15), + request(16) =>request_signal(16), + request(17) =>request_signal(17), + request(18) =>request_signal(18), + request(19) =>request_signal(19), + request(20) =>request_signal(20), + request(21) =>request_signal(21), + request(22) =>request_signal(22), + request(23) =>request_signal(23), + request(24) =>request_signal(24), + request(25) =>request_signal(25), + request(26) =>request_signal(26), + request(27) =>request_signal(27), + request(28) =>request_signal(28) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>14) +PORT MAP( + data_in => Port3_in, + data_in_en => data_in_en(3), + reset => reset, + clk =>clk, + grant(29) => grant_signal(29), + grant(30) => grant_signal(30), + grant(31) => grant_signal(31), + grant(32) => grant_signal(32), + grant(33) => grant_signal(33), + grant(34) => grant_signal(34), + grant(35) => grant_signal(35), + grant(36) => grant_signal(36), + grant(37) => grant_signal(37), + grant(38) => grant_signal(38), + grant(39) => grant_signal(39), + grant(40) => grant_signal(40), + grant(41) => grant_signal(41), + grant(42) => grant_signal(42), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port3, + data_out_pulse =>crossbar_in_pulse3, + request(29) =>request_signal(29), + request(30) =>request_signal(30), + request(31) =>request_signal(31), + request(32) =>request_signal(32), + request(33) =>request_signal(33), + request(34) =>request_signal(34), + request(35) =>request_signal(35), + request(36) =>request_signal(36), + request(37) =>request_signal(37), + request(38) =>request_signal(38), + request(39) =>request_signal(39), + request(40) =>request_signal(40), + request(41) =>request_signal(41), + request(42) =>request_signal(42) +); + +PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>14) +PORT MAP( + data_in => Port4_in, + data_in_en => data_in_en(4), + reset => reset, + clk =>clk, + grant(43) => grant_signal(43), + grant(44) => grant_signal(44), + grant(45) => grant_signal(45), + grant(46) => grant_signal(46), + grant(47) => grant_signal(47), + grant(48) => grant_signal(48), + grant(49) => grant_signal(49), + grant(50) => grant_signal(50), + grant(51) => grant_signal(51), + grant(52) => grant_signal(52), + grant(53) => grant_signal(53), + grant(54) => grant_signal(54), + grant(55) => grant_signal(55), + grant(56) => grant_signal(56), + fifo_full =>fifo_in_full(4), + priority_rotation => priority_rotation_signal(4), + fifo_empty => fifo_in_empty(4), + data_out =>crossbar_in_port4, + data_out_pulse =>crossbar_in_pulse4, + request(43) =>request_signal(43), + request(44) =>request_signal(44), + request(45) =>request_signal(45), + request(46) =>request_signal(46), + request(47) =>request_signal(47), + request(48) =>request_signal(48), + request(49) =>request_signal(49), + request(50) =>request_signal(50), + request(51) =>request_signal(51), + request(52) =>request_signal(52), + request(53) =>request_signal(53), + request(54) =>request_signal(54), + request(55) =>request_signal(55), + request(56) =>request_signal(56) +); + +PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>14) +PORT MAP( + data_in => Port5_in, + data_in_en => data_in_en(5), + reset => reset, + clk =>clk, + grant(57) => grant_signal(57), + grant(58) => grant_signal(58), + grant(59) => grant_signal(59), + grant(60) => grant_signal(60), + grant(61) => grant_signal(61), + grant(62) => grant_signal(62), + grant(63) => grant_signal(63), + grant(64) => grant_signal(64), + grant(65) => grant_signal(65), + grant(66) => grant_signal(66), + grant(67) => grant_signal(67), + grant(68) => grant_signal(68), + grant(69) => grant_signal(69), + grant(70) => grant_signal(70), + fifo_full =>fifo_in_full(5), + priority_rotation => priority_rotation_signal(5), + fifo_empty => fifo_in_empty(5), + data_out =>crossbar_in_port5, + data_out_pulse =>crossbar_in_pulse5, + request(57) =>request_signal(57), + request(58) =>request_signal(58), + request(59) =>request_signal(59), + request(60) =>request_signal(60), + request(61) =>request_signal(61), + request(62) =>request_signal(62), + request(63) =>request_signal(63), + request(64) =>request_signal(64), + request(65) =>request_signal(65), + request(66) =>request_signal(66), + request(67) =>request_signal(67), + request(68) =>request_signal(68), + request(69) =>request_signal(69), + request(70) =>request_signal(70) +); + +PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>14) +PORT MAP( + data_in => Port6_in, + data_in_en => data_in_en(6), + reset => reset, + clk =>clk, + grant(71) => grant_signal(71), + grant(72) => grant_signal(72), + grant(73) => grant_signal(73), + grant(74) => grant_signal(74), + grant(75) => grant_signal(75), + grant(76) => grant_signal(76), + grant(77) => grant_signal(77), + grant(78) => grant_signal(78), + grant(79) => grant_signal(79), + grant(80) => grant_signal(80), + grant(81) => grant_signal(81), + grant(82) => grant_signal(82), + grant(83) => grant_signal(83), + grant(84) => grant_signal(84), + fifo_full =>fifo_in_full(6), + priority_rotation => priority_rotation_signal(6), + fifo_empty => fifo_in_empty(6), + data_out =>crossbar_in_port6, + data_out_pulse =>crossbar_in_pulse6, + request(71) =>request_signal(71), + request(72) =>request_signal(72), + request(73) =>request_signal(73), + request(74) =>request_signal(74), + request(75) =>request_signal(75), + request(76) =>request_signal(76), + request(77) =>request_signal(77), + request(78) =>request_signal(78), + request(79) =>request_signal(79), + request(80) =>request_signal(80), + request(81) =>request_signal(81), + request(82) =>request_signal(82), + request(83) =>request_signal(83), + request(84) =>request_signal(84) +); + +PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>14) +PORT MAP( + data_in => Port7_in, + data_in_en => data_in_en(7), + reset => reset, + clk =>clk, + grant(85) => grant_signal(85), + grant(86) => grant_signal(86), + grant(87) => grant_signal(87), + grant(88) => grant_signal(88), + grant(89) => grant_signal(89), + grant(90) => grant_signal(90), + grant(91) => grant_signal(91), + grant(92) => grant_signal(92), + grant(93) => grant_signal(93), + grant(94) => grant_signal(94), + grant(95) => grant_signal(95), + grant(96) => grant_signal(96), + grant(97) => grant_signal(97), + grant(98) => grant_signal(98), + fifo_full =>fifo_in_full(7), + priority_rotation => priority_rotation_signal(7), + fifo_empty => fifo_in_empty(7), + data_out =>crossbar_in_port7, + data_out_pulse =>crossbar_in_pulse7, + request(85) =>request_signal(85), + request(86) =>request_signal(86), + request(87) =>request_signal(87), + request(88) =>request_signal(88), + request(89) =>request_signal(89), + request(90) =>request_signal(90), + request(91) =>request_signal(91), + request(92) =>request_signal(92), + request(93) =>request_signal(93), + request(94) =>request_signal(94), + request(95) =>request_signal(95), + request(96) =>request_signal(96), + request(97) =>request_signal(97), + request(98) =>request_signal(98) +); + +PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>14) +PORT MAP( + data_in => Port8_in, + data_in_en => data_in_en(8), + reset => reset, + clk =>clk, + grant(99) => grant_signal(99), + grant(100) => grant_signal(100), + grant(101) => grant_signal(101), + grant(102) => grant_signal(102), + grant(103) => grant_signal(103), + grant(104) => grant_signal(104), + grant(105) => grant_signal(105), + grant(106) => grant_signal(106), + grant(107) => grant_signal(107), + grant(108) => grant_signal(108), + grant(109) => grant_signal(109), + grant(110) => grant_signal(110), + grant(111) => grant_signal(111), + grant(112) => grant_signal(112), + fifo_full =>fifo_in_full(8), + priority_rotation => priority_rotation_signal(8), + fifo_empty => fifo_in_empty(8), + data_out =>crossbar_in_port8, + data_out_pulse =>crossbar_in_pulse8, + request(99) =>request_signal(99), + request(100) =>request_signal(100), + request(101) =>request_signal(101), + request(102) =>request_signal(102), + request(103) =>request_signal(103), + request(104) =>request_signal(104), + request(105) =>request_signal(105), + request(106) =>request_signal(106), + request(107) =>request_signal(107), + request(108) =>request_signal(108), + request(109) =>request_signal(109), + request(110) =>request_signal(110), + request(111) =>request_signal(111), + request(112) =>request_signal(112) +); + +PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>14) +PORT MAP( + data_in => Port9_in, + data_in_en => data_in_en(9), + reset => reset, + clk =>clk, + grant(113) => grant_signal(113), + grant(114) => grant_signal(114), + grant(115) => grant_signal(115), + grant(116) => grant_signal(116), + grant(117) => grant_signal(117), + grant(118) => grant_signal(118), + grant(119) => grant_signal(119), + grant(120) => grant_signal(120), + grant(121) => grant_signal(121), + grant(122) => grant_signal(122), + grant(123) => grant_signal(123), + grant(124) => grant_signal(124), + grant(125) => grant_signal(125), + grant(126) => grant_signal(126), + fifo_full =>fifo_in_full(9), + priority_rotation => priority_rotation_signal(9), + fifo_empty => fifo_in_empty(9), + data_out =>crossbar_in_port9, + data_out_pulse =>crossbar_in_pulse9, + request(113) =>request_signal(113), + request(114) =>request_signal(114), + request(115) =>request_signal(115), + request(116) =>request_signal(116), + request(117) =>request_signal(117), + request(118) =>request_signal(118), + request(119) =>request_signal(119), + request(120) =>request_signal(120), + request(121) =>request_signal(121), + request(122) =>request_signal(122), + request(123) =>request_signal(123), + request(124) =>request_signal(124), + request(125) =>request_signal(125), + request(126) =>request_signal(126) +); + +PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>14) +PORT MAP( + data_in => Port10_in, + data_in_en => data_in_en(10), + reset => reset, + clk =>clk, + grant(127) => grant_signal(127), + grant(128) => grant_signal(128), + grant(129) => grant_signal(129), + grant(130) => grant_signal(130), + grant(131) => grant_signal(131), + grant(132) => grant_signal(132), + grant(133) => grant_signal(133), + grant(134) => grant_signal(134), + grant(135) => grant_signal(135), + grant(136) => grant_signal(136), + grant(137) => grant_signal(137), + grant(138) => grant_signal(138), + grant(139) => grant_signal(139), + grant(140) => grant_signal(140), + fifo_full =>fifo_in_full(10), + priority_rotation => priority_rotation_signal(10), + fifo_empty => fifo_in_empty(10), + data_out =>crossbar_in_port10, + data_out_pulse =>crossbar_in_pulse10, + request(127) =>request_signal(127), + request(128) =>request_signal(128), + request(129) =>request_signal(129), + request(130) =>request_signal(130), + request(131) =>request_signal(131), + request(132) =>request_signal(132), + request(133) =>request_signal(133), + request(134) =>request_signal(134), + request(135) =>request_signal(135), + request(136) =>request_signal(136), + request(137) =>request_signal(137), + request(138) =>request_signal(138), + request(139) =>request_signal(139), + request(140) =>request_signal(140) +); + +PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>14) +PORT MAP( + data_in => Port11_in, + data_in_en => data_in_en(11), + reset => reset, + clk =>clk, + grant(141) => grant_signal(141), + grant(142) => grant_signal(142), + grant(143) => grant_signal(143), + grant(144) => grant_signal(144), + grant(145) => grant_signal(145), + grant(146) => grant_signal(146), + grant(147) => grant_signal(147), + grant(148) => grant_signal(148), + grant(149) => grant_signal(149), + grant(150) => grant_signal(150), + grant(151) => grant_signal(151), + grant(152) => grant_signal(152), + grant(153) => grant_signal(153), + grant(154) => grant_signal(154), + fifo_full =>fifo_in_full(11), + priority_rotation => priority_rotation_signal(11), + fifo_empty => fifo_in_empty(11), + data_out =>crossbar_in_port11, + data_out_pulse =>crossbar_in_pulse11, + request(141) =>request_signal(141), + request(142) =>request_signal(142), + request(143) =>request_signal(143), + request(144) =>request_signal(144), + request(145) =>request_signal(145), + request(146) =>request_signal(146), + request(147) =>request_signal(147), + request(148) =>request_signal(148), + request(149) =>request_signal(149), + request(150) =>request_signal(150), + request(151) =>request_signal(151), + request(152) =>request_signal(152), + request(153) =>request_signal(153), + request(154) =>request_signal(154) +); + +PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>14) +PORT MAP( + data_in => Port12_in, + data_in_en => data_in_en(12), + reset => reset, + clk =>clk, + grant(155) => grant_signal(155), + grant(156) => grant_signal(156), + grant(157) => grant_signal(157), + grant(158) => grant_signal(158), + grant(159) => grant_signal(159), + grant(160) => grant_signal(160), + grant(161) => grant_signal(161), + grant(162) => grant_signal(162), + grant(163) => grant_signal(163), + grant(164) => grant_signal(164), + grant(165) => grant_signal(165), + grant(166) => grant_signal(166), + grant(167) => grant_signal(167), + grant(168) => grant_signal(168), + fifo_full =>fifo_in_full(12), + priority_rotation => priority_rotation_signal(12), + fifo_empty => fifo_in_empty(12), + data_out =>crossbar_in_port12, + data_out_pulse =>crossbar_in_pulse12, + request(155) =>request_signal(155), + request(156) =>request_signal(156), + request(157) =>request_signal(157), + request(158) =>request_signal(158), + request(159) =>request_signal(159), + request(160) =>request_signal(160), + request(161) =>request_signal(161), + request(162) =>request_signal(162), + request(163) =>request_signal(163), + request(164) =>request_signal(164), + request(165) =>request_signal(165), + request(166) =>request_signal(166), + request(167) =>request_signal(167), + request(168) =>request_signal(168) +); + +PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>14) +PORT MAP( + data_in => Port13_in, + data_in_en => data_in_en(13), + reset => reset, + clk =>clk, + grant(169) => grant_signal(169), + grant(170) => grant_signal(170), + grant(171) => grant_signal(171), + grant(172) => grant_signal(172), + grant(173) => grant_signal(173), + grant(174) => grant_signal(174), + grant(175) => grant_signal(175), + grant(176) => grant_signal(176), + grant(177) => grant_signal(177), + grant(178) => grant_signal(178), + grant(179) => grant_signal(179), + grant(180) => grant_signal(180), + grant(181) => grant_signal(181), + grant(182) => grant_signal(182), + fifo_full =>fifo_in_full(13), + priority_rotation => priority_rotation_signal(13), + fifo_empty => fifo_in_empty(13), + data_out =>crossbar_in_port13, + data_out_pulse =>crossbar_in_pulse13, + request(169) =>request_signal(169), + request(170) =>request_signal(170), + request(171) =>request_signal(171), + request(172) =>request_signal(172), + request(173) =>request_signal(173), + request(174) =>request_signal(174), + request(175) =>request_signal(175), + request(176) =>request_signal(176), + request(177) =>request_signal(177), + request(178) =>request_signal(178), + request(179) =>request_signal(179), + request(180) =>request_signal(180), + request(181) =>request_signal(181), + request(182) =>request_signal(182) +); + +PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>14) +PORT MAP( + data_in => Port14_in, + data_in_en => data_in_en(14), + reset => reset, + clk =>clk, + grant(183) => grant_signal(183), + grant(184) => grant_signal(184), + grant(185) => grant_signal(185), + grant(186) => grant_signal(186), + grant(187) => grant_signal(187), + grant(188) => grant_signal(188), + grant(189) => grant_signal(189), + grant(190) => grant_signal(190), + grant(191) => grant_signal(191), + grant(192) => grant_signal(192), + grant(193) => grant_signal(193), + grant(194) => grant_signal(194), + grant(195) => grant_signal(195), + grant(196) => grant_signal(196), + fifo_full =>fifo_in_full(14), + priority_rotation => priority_rotation_signal(14), + fifo_empty => fifo_in_empty(14), + data_out =>crossbar_in_port14, + data_out_pulse =>crossbar_in_pulse14, + request(183) =>request_signal(183), + request(184) =>request_signal(184), + request(185) =>request_signal(185), + request(186) =>request_signal(186), + request(187) =>request_signal(187), + request(188) =>request_signal(188), + request(189) =>request_signal(189), + request(190) =>request_signal(190), + request(191) =>request_signal(191), + request(192) =>request_signal(192), + request(193) =>request_signal(193), + request(194) =>request_signal(194), + request(195) =>request_signal(195), + request(196) =>request_signal(196) +); + +end generate switch14x14; + + +-- switch 15 ports +switch15x15 : if number_of_ports = 15 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + grant(4) => grant_signal(4), + grant(5) => grant_signal(5), + grant(6) => grant_signal(6), + grant(7) => grant_signal(7), + grant(8) => grant_signal(8), + grant(9) => grant_signal(9), + grant(10) => grant_signal(10), + grant(11) => grant_signal(11), + grant(12) => grant_signal(12), + grant(13) => grant_signal(13), + grant(14) => grant_signal(14), + grant(15) => grant_signal(15), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3), + request(4) =>request_signal(4), + request(5) =>request_signal(5), + request(6) =>request_signal(6), + request(7) =>request_signal(7), + request(8) =>request_signal(8), + request(9) =>request_signal(9), + request(10) =>request_signal(10), + request(11) =>request_signal(11), + request(12) =>request_signal(12), + request(13) =>request_signal(13), + request(14) =>request_signal(14), + request(15) =>request_signal(15) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(16) => grant_signal(16), + grant(17) => grant_signal(17), + grant(18) => grant_signal(18), + grant(19) => grant_signal(19), + grant(20) => grant_signal(20), + grant(21) => grant_signal(21), + grant(22) => grant_signal(22), + grant(23) => grant_signal(23), + grant(24) => grant_signal(24), + grant(25) => grant_signal(25), + grant(26) => grant_signal(26), + grant(27) => grant_signal(27), + grant(28) => grant_signal(28), + grant(29) => grant_signal(29), + grant(30) => grant_signal(30), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(16) =>request_signal(16), + request(17) =>request_signal(17), + request(18) =>request_signal(18), + request(19) =>request_signal(19), + request(20) =>request_signal(20), + request(21) =>request_signal(21), + request(22) =>request_signal(22), + request(23) =>request_signal(23), + request(24) =>request_signal(24), + request(25) =>request_signal(25), + request(26) =>request_signal(26), + request(27) =>request_signal(27), + request(28) =>request_signal(28), + request(29) =>request_signal(29), + request(30) =>request_signal(30) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port3_in, + data_in_en => data_in_en(3), + reset => reset, + clk =>clk, + grant(31) => grant_signal(31), + grant(32) => grant_signal(32), + grant(33) => grant_signal(33), + grant(34) => grant_signal(34), + grant(35) => grant_signal(35), + grant(36) => grant_signal(36), + grant(37) => grant_signal(37), + grant(38) => grant_signal(38), + grant(39) => grant_signal(39), + grant(40) => grant_signal(40), + grant(41) => grant_signal(41), + grant(42) => grant_signal(42), + grant(43) => grant_signal(43), + grant(44) => grant_signal(44), + grant(45) => grant_signal(45), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port3, + data_out_pulse =>crossbar_in_pulse3, + request(31) =>request_signal(31), + request(32) =>request_signal(32), + request(33) =>request_signal(33), + request(34) =>request_signal(34), + request(35) =>request_signal(35), + request(36) =>request_signal(36), + request(37) =>request_signal(37), + request(38) =>request_signal(38), + request(39) =>request_signal(39), + request(40) =>request_signal(40), + request(41) =>request_signal(41), + request(42) =>request_signal(42), + request(43) =>request_signal(43), + request(44) =>request_signal(44), + request(45) =>request_signal(45) +); + +PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port4_in, + data_in_en => data_in_en(4), + reset => reset, + clk =>clk, + grant(46) => grant_signal(46), + grant(47) => grant_signal(47), + grant(48) => grant_signal(48), + grant(49) => grant_signal(49), + grant(50) => grant_signal(50), + grant(51) => grant_signal(51), + grant(52) => grant_signal(52), + grant(53) => grant_signal(53), + grant(54) => grant_signal(54), + grant(55) => grant_signal(55), + grant(56) => grant_signal(56), + grant(57) => grant_signal(57), + grant(58) => grant_signal(58), + grant(59) => grant_signal(59), + grant(60) => grant_signal(60), + fifo_full =>fifo_in_full(4), + priority_rotation => priority_rotation_signal(4), + fifo_empty => fifo_in_empty(4), + data_out =>crossbar_in_port4, + data_out_pulse =>crossbar_in_pulse4, + request(46) =>request_signal(46), + request(47) =>request_signal(47), + request(48) =>request_signal(48), + request(49) =>request_signal(49), + request(50) =>request_signal(50), + request(51) =>request_signal(51), + request(52) =>request_signal(52), + request(53) =>request_signal(53), + request(54) =>request_signal(54), + request(55) =>request_signal(55), + request(56) =>request_signal(56), + request(57) =>request_signal(57), + request(58) =>request_signal(58), + request(59) =>request_signal(59), + request(60) =>request_signal(60) +); + +PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port5_in, + data_in_en => data_in_en(5), + reset => reset, + clk =>clk, + grant(61) => grant_signal(61), + grant(62) => grant_signal(62), + grant(63) => grant_signal(63), + grant(64) => grant_signal(64), + grant(65) => grant_signal(65), + grant(66) => grant_signal(66), + grant(67) => grant_signal(67), + grant(68) => grant_signal(68), + grant(69) => grant_signal(69), + grant(70) => grant_signal(70), + grant(71) => grant_signal(71), + grant(72) => grant_signal(72), + grant(73) => grant_signal(73), + grant(74) => grant_signal(74), + grant(75) => grant_signal(75), + fifo_full =>fifo_in_full(5), + priority_rotation => priority_rotation_signal(5), + fifo_empty => fifo_in_empty(5), + data_out =>crossbar_in_port5, + data_out_pulse =>crossbar_in_pulse5, + request(61) =>request_signal(61), + request(62) =>request_signal(62), + request(63) =>request_signal(63), + request(64) =>request_signal(64), + request(65) =>request_signal(65), + request(66) =>request_signal(66), + request(67) =>request_signal(67), + request(68) =>request_signal(68), + request(69) =>request_signal(69), + request(70) =>request_signal(70), + request(71) =>request_signal(71), + request(72) =>request_signal(72), + request(73) =>request_signal(73), + request(74) =>request_signal(74), + request(75) =>request_signal(75) +); + +PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port6_in, + data_in_en => data_in_en(6), + reset => reset, + clk =>clk, + grant(76) => grant_signal(76), + grant(77) => grant_signal(77), + grant(78) => grant_signal(78), + grant(79) => grant_signal(79), + grant(80) => grant_signal(80), + grant(81) => grant_signal(81), + grant(82) => grant_signal(82), + grant(83) => grant_signal(83), + grant(84) => grant_signal(84), + grant(85) => grant_signal(85), + grant(86) => grant_signal(86), + grant(87) => grant_signal(87), + grant(88) => grant_signal(88), + grant(89) => grant_signal(89), + grant(90) => grant_signal(90), + fifo_full =>fifo_in_full(6), + priority_rotation => priority_rotation_signal(6), + fifo_empty => fifo_in_empty(6), + data_out =>crossbar_in_port6, + data_out_pulse =>crossbar_in_pulse6, + request(76) =>request_signal(76), + request(77) =>request_signal(77), + request(78) =>request_signal(78), + request(79) =>request_signal(79), + request(80) =>request_signal(80), + request(81) =>request_signal(81), + request(82) =>request_signal(82), + request(83) =>request_signal(83), + request(84) =>request_signal(84), + request(85) =>request_signal(85), + request(86) =>request_signal(86), + request(87) =>request_signal(87), + request(88) =>request_signal(88), + request(89) =>request_signal(89), + request(90) =>request_signal(90) +); + +PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port7_in, + data_in_en => data_in_en(7), + reset => reset, + clk =>clk, + grant(91) => grant_signal(91), + grant(92) => grant_signal(92), + grant(93) => grant_signal(93), + grant(94) => grant_signal(94), + grant(95) => grant_signal(95), + grant(96) => grant_signal(96), + grant(97) => grant_signal(97), + grant(98) => grant_signal(98), + grant(99) => grant_signal(99), + grant(100) => grant_signal(100), + grant(101) => grant_signal(101), + grant(102) => grant_signal(102), + grant(103) => grant_signal(103), + grant(104) => grant_signal(104), + grant(105) => grant_signal(105), + fifo_full =>fifo_in_full(7), + priority_rotation => priority_rotation_signal(7), + fifo_empty => fifo_in_empty(7), + data_out =>crossbar_in_port7, + data_out_pulse =>crossbar_in_pulse7, + request(91) =>request_signal(91), + request(92) =>request_signal(92), + request(93) =>request_signal(93), + request(94) =>request_signal(94), + request(95) =>request_signal(95), + request(96) =>request_signal(96), + request(97) =>request_signal(97), + request(98) =>request_signal(98), + request(99) =>request_signal(99), + request(100) =>request_signal(100), + request(101) =>request_signal(101), + request(102) =>request_signal(102), + request(103) =>request_signal(103), + request(104) =>request_signal(104), + request(105) =>request_signal(105) +); + +PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port8_in, + data_in_en => data_in_en(8), + reset => reset, + clk =>clk, + grant(106) => grant_signal(106), + grant(107) => grant_signal(107), + grant(108) => grant_signal(108), + grant(109) => grant_signal(109), + grant(110) => grant_signal(110), + grant(111) => grant_signal(111), + grant(112) => grant_signal(112), + grant(113) => grant_signal(113), + grant(114) => grant_signal(114), + grant(115) => grant_signal(115), + grant(116) => grant_signal(116), + grant(117) => grant_signal(117), + grant(118) => grant_signal(118), + grant(119) => grant_signal(119), + grant(120) => grant_signal(120), + fifo_full =>fifo_in_full(8), + priority_rotation => priority_rotation_signal(8), + fifo_empty => fifo_in_empty(8), + data_out =>crossbar_in_port8, + data_out_pulse =>crossbar_in_pulse8, + request(106) =>request_signal(106), + request(107) =>request_signal(107), + request(108) =>request_signal(108), + request(109) =>request_signal(109), + request(110) =>request_signal(110), + request(111) =>request_signal(111), + request(112) =>request_signal(112), + request(113) =>request_signal(113), + request(114) =>request_signal(114), + request(115) =>request_signal(115), + request(116) =>request_signal(116), + request(117) =>request_signal(117), + request(118) =>request_signal(118), + request(119) =>request_signal(119), + request(120) =>request_signal(120) +); + +PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port9_in, + data_in_en => data_in_en(9), + reset => reset, + clk =>clk, + grant(121) => grant_signal(121), + grant(122) => grant_signal(122), + grant(123) => grant_signal(123), + grant(124) => grant_signal(124), + grant(125) => grant_signal(125), + grant(126) => grant_signal(126), + grant(127) => grant_signal(127), + grant(128) => grant_signal(128), + grant(129) => grant_signal(129), + grant(130) => grant_signal(130), + grant(131) => grant_signal(131), + grant(132) => grant_signal(132), + grant(133) => grant_signal(133), + grant(134) => grant_signal(134), + grant(135) => grant_signal(135), + fifo_full =>fifo_in_full(9), + priority_rotation => priority_rotation_signal(9), + fifo_empty => fifo_in_empty(9), + data_out =>crossbar_in_port9, + data_out_pulse =>crossbar_in_pulse9, + request(121) =>request_signal(121), + request(122) =>request_signal(122), + request(123) =>request_signal(123), + request(124) =>request_signal(124), + request(125) =>request_signal(125), + request(126) =>request_signal(126), + request(127) =>request_signal(127), + request(128) =>request_signal(128), + request(129) =>request_signal(129), + request(130) =>request_signal(130), + request(131) =>request_signal(131), + request(132) =>request_signal(132), + request(133) =>request_signal(133), + request(134) =>request_signal(134), + request(135) =>request_signal(135) +); + +PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port10_in, + data_in_en => data_in_en(10), + reset => reset, + clk =>clk, + grant(136) => grant_signal(136), + grant(137) => grant_signal(137), + grant(138) => grant_signal(138), + grant(139) => grant_signal(139), + grant(140) => grant_signal(140), + grant(141) => grant_signal(141), + grant(142) => grant_signal(142), + grant(143) => grant_signal(143), + grant(144) => grant_signal(144), + grant(145) => grant_signal(145), + grant(146) => grant_signal(146), + grant(147) => grant_signal(147), + grant(148) => grant_signal(148), + grant(149) => grant_signal(149), + grant(150) => grant_signal(150), + fifo_full =>fifo_in_full(10), + priority_rotation => priority_rotation_signal(10), + fifo_empty => fifo_in_empty(10), + data_out =>crossbar_in_port10, + data_out_pulse =>crossbar_in_pulse10, + request(136) =>request_signal(136), + request(137) =>request_signal(137), + request(138) =>request_signal(138), + request(139) =>request_signal(139), + request(140) =>request_signal(140), + request(141) =>request_signal(141), + request(142) =>request_signal(142), + request(143) =>request_signal(143), + request(144) =>request_signal(144), + request(145) =>request_signal(145), + request(146) =>request_signal(146), + request(147) =>request_signal(147), + request(148) =>request_signal(148), + request(149) =>request_signal(149), + request(150) =>request_signal(150) +); + +PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port11_in, + data_in_en => data_in_en(11), + reset => reset, + clk =>clk, + grant(151) => grant_signal(151), + grant(152) => grant_signal(152), + grant(153) => grant_signal(153), + grant(154) => grant_signal(154), + grant(155) => grant_signal(155), + grant(156) => grant_signal(156), + grant(157) => grant_signal(157), + grant(158) => grant_signal(158), + grant(159) => grant_signal(159), + grant(160) => grant_signal(160), + grant(161) => grant_signal(161), + grant(162) => grant_signal(162), + grant(163) => grant_signal(163), + grant(164) => grant_signal(164), + grant(165) => grant_signal(165), + fifo_full =>fifo_in_full(11), + priority_rotation => priority_rotation_signal(11), + fifo_empty => fifo_in_empty(11), + data_out =>crossbar_in_port11, + data_out_pulse =>crossbar_in_pulse11, + request(151) =>request_signal(151), + request(152) =>request_signal(152), + request(153) =>request_signal(153), + request(154) =>request_signal(154), + request(155) =>request_signal(155), + request(156) =>request_signal(156), + request(157) =>request_signal(157), + request(158) =>request_signal(158), + request(159) =>request_signal(159), + request(160) =>request_signal(160), + request(161) =>request_signal(161), + request(162) =>request_signal(162), + request(163) =>request_signal(163), + request(164) =>request_signal(164), + request(165) =>request_signal(165) +); + +PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port12_in, + data_in_en => data_in_en(12), + reset => reset, + clk =>clk, + grant(166) => grant_signal(166), + grant(167) => grant_signal(167), + grant(168) => grant_signal(168), + grant(169) => grant_signal(169), + grant(170) => grant_signal(170), + grant(171) => grant_signal(171), + grant(172) => grant_signal(172), + grant(173) => grant_signal(173), + grant(174) => grant_signal(174), + grant(175) => grant_signal(175), + grant(176) => grant_signal(176), + grant(177) => grant_signal(177), + grant(178) => grant_signal(178), + grant(179) => grant_signal(179), + grant(180) => grant_signal(180), + fifo_full =>fifo_in_full(12), + priority_rotation => priority_rotation_signal(12), + fifo_empty => fifo_in_empty(12), + data_out =>crossbar_in_port12, + data_out_pulse =>crossbar_in_pulse12, + request(166) =>request_signal(166), + request(167) =>request_signal(167), + request(168) =>request_signal(168), + request(169) =>request_signal(169), + request(170) =>request_signal(170), + request(171) =>request_signal(171), + request(172) =>request_signal(172), + request(173) =>request_signal(173), + request(174) =>request_signal(174), + request(175) =>request_signal(175), + request(176) =>request_signal(176), + request(177) =>request_signal(177), + request(178) =>request_signal(178), + request(179) =>request_signal(179), + request(180) =>request_signal(180) +); + +PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port13_in, + data_in_en => data_in_en(13), + reset => reset, + clk =>clk, + grant(181) => grant_signal(181), + grant(182) => grant_signal(182), + grant(183) => grant_signal(183), + grant(184) => grant_signal(184), + grant(185) => grant_signal(185), + grant(186) => grant_signal(186), + grant(187) => grant_signal(187), + grant(188) => grant_signal(188), + grant(189) => grant_signal(189), + grant(190) => grant_signal(190), + grant(191) => grant_signal(191), + grant(192) => grant_signal(192), + grant(193) => grant_signal(193), + grant(194) => grant_signal(194), + grant(195) => grant_signal(195), + fifo_full =>fifo_in_full(13), + priority_rotation => priority_rotation_signal(13), + fifo_empty => fifo_in_empty(13), + data_out =>crossbar_in_port13, + data_out_pulse =>crossbar_in_pulse13, + request(181) =>request_signal(181), + request(182) =>request_signal(182), + request(183) =>request_signal(183), + request(184) =>request_signal(184), + request(185) =>request_signal(185), + request(186) =>request_signal(186), + request(187) =>request_signal(187), + request(188) =>request_signal(188), + request(189) =>request_signal(189), + request(190) =>request_signal(190), + request(191) =>request_signal(191), + request(192) =>request_signal(192), + request(193) =>request_signal(193), + request(194) =>request_signal(194), + request(195) =>request_signal(195) +); + +PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port14_in, + data_in_en => data_in_en(14), + reset => reset, + clk =>clk, + grant(196) => grant_signal(196), + grant(197) => grant_signal(197), + grant(198) => grant_signal(198), + grant(199) => grant_signal(199), + grant(200) => grant_signal(200), + grant(201) => grant_signal(201), + grant(202) => grant_signal(202), + grant(203) => grant_signal(203), + grant(204) => grant_signal(204), + grant(205) => grant_signal(205), + grant(206) => grant_signal(206), + grant(207) => grant_signal(207), + grant(208) => grant_signal(208), + grant(209) => grant_signal(209), + grant(210) => grant_signal(210), + fifo_full =>fifo_in_full(14), + priority_rotation => priority_rotation_signal(14), + fifo_empty => fifo_in_empty(14), + data_out =>crossbar_in_port14, + data_out_pulse =>crossbar_in_pulse14, + request(196) =>request_signal(196), + request(197) =>request_signal(197), + request(198) =>request_signal(198), + request(199) =>request_signal(199), + request(200) =>request_signal(200), + request(201) =>request_signal(201), + request(202) =>request_signal(202), + request(203) =>request_signal(203), + request(204) =>request_signal(204), + request(205) =>request_signal(205), + request(206) =>request_signal(206), + request(207) =>request_signal(207), + request(208) =>request_signal(208), + request(209) =>request_signal(209), + request(210) =>request_signal(210) +); + +PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>15) +PORT MAP( + data_in => Port15_in, + data_in_en => data_in_en(15), + reset => reset, + clk =>clk, + grant(211) => grant_signal(211), + grant(212) => grant_signal(212), + grant(213) => grant_signal(213), + grant(214) => grant_signal(214), + grant(215) => grant_signal(215), + grant(216) => grant_signal(216), + grant(217) => grant_signal(217), + grant(218) => grant_signal(218), + grant(219) => grant_signal(219), + grant(220) => grant_signal(220), + grant(221) => grant_signal(221), + grant(222) => grant_signal(222), + grant(223) => grant_signal(223), + grant(224) => grant_signal(224), + grant(225) => grant_signal(225), + fifo_full =>fifo_in_full(15), + priority_rotation => priority_rotation_signal(15), + fifo_empty => fifo_in_empty(15), + data_out =>crossbar_in_port15, + data_out_pulse =>crossbar_in_pulse15, + request(211) =>request_signal(211), + request(212) =>request_signal(212), + request(213) =>request_signal(213), + request(214) =>request_signal(214), + request(215) =>request_signal(215), + request(216) =>request_signal(216), + request(217) =>request_signal(217), + request(218) =>request_signal(218), + request(219) =>request_signal(219), + request(220) =>request_signal(220), + request(221) =>request_signal(221), + request(222) =>request_signal(222), + request(223) =>request_signal(223), + request(224) =>request_signal(224), + request(225) =>request_signal(225) +); + +end generate switch15x15; + + +-- switch 16 ports +switch16x16 : if number_of_ports = 16 generate + +PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port1_in, + data_in_en => data_in_en(1), + reset => reset, + clk =>clk, + grant(1) => grant_signal(1), + grant(2) => grant_signal(2), + grant(3) => grant_signal(3), + grant(4) => grant_signal(4), + grant(5) => grant_signal(5), + grant(6) => grant_signal(6), + grant(7) => grant_signal(7), + grant(8) => grant_signal(8), + grant(9) => grant_signal(9), + grant(10) => grant_signal(10), + grant(11) => grant_signal(11), + grant(12) => grant_signal(12), + grant(13) => grant_signal(13), + grant(14) => grant_signal(14), + grant(15) => grant_signal(15), + grant(16) => grant_signal(16), + fifo_full =>fifo_in_full(1), + priority_rotation => priority_rotation_signal(1), + fifo_empty => fifo_in_empty(1), + data_out =>crossbar_in_port1, + data_out_pulse =>crossbar_in_pulse1, + request(1) =>request_signal(1), + request(2) =>request_signal(2), + request(3) =>request_signal(3), + request(4) =>request_signal(4), + request(5) =>request_signal(5), + request(6) =>request_signal(6), + request(7) =>request_signal(7), + request(8) =>request_signal(8), + request(9) =>request_signal(9), + request(10) =>request_signal(10), + request(11) =>request_signal(11), + request(12) =>request_signal(12), + request(13) =>request_signal(13), + request(14) =>request_signal(14), + request(15) =>request_signal(15), + request(16) =>request_signal(16) +); + +PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port2_in, + data_in_en => data_in_en(2), + reset => reset, + clk =>clk, + grant(17) => grant_signal(17), + grant(18) => grant_signal(18), + grant(19) => grant_signal(19), + grant(20) => grant_signal(20), + grant(21) => grant_signal(21), + grant(22) => grant_signal(22), + grant(23) => grant_signal(23), + grant(24) => grant_signal(24), + grant(25) => grant_signal(25), + grant(26) => grant_signal(26), + grant(27) => grant_signal(27), + grant(28) => grant_signal(28), + grant(29) => grant_signal(29), + grant(30) => grant_signal(30), + grant(31) => grant_signal(31), + grant(32) => grant_signal(32), + fifo_full =>fifo_in_full(2), + priority_rotation => priority_rotation_signal(2), + fifo_empty => fifo_in_empty(2), + data_out =>crossbar_in_port2, + data_out_pulse =>crossbar_in_pulse2, + request(17) =>request_signal(17), + request(18) =>request_signal(18), + request(19) =>request_signal(19), + request(20) =>request_signal(20), + request(21) =>request_signal(21), + request(22) =>request_signal(22), + request(23) =>request_signal(23), + request(24) =>request_signal(24), + request(25) =>request_signal(25), + request(26) =>request_signal(26), + request(27) =>request_signal(27), + request(28) =>request_signal(28), + request(29) =>request_signal(29), + request(30) =>request_signal(30), + request(31) =>request_signal(31), + request(32) =>request_signal(32) +); + +PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port3_in, + data_in_en => data_in_en(3), + reset => reset, + clk =>clk, + grant(33) => grant_signal(33), + grant(34) => grant_signal(34), + grant(35) => grant_signal(35), + grant(36) => grant_signal(36), + grant(37) => grant_signal(37), + grant(38) => grant_signal(38), + grant(39) => grant_signal(39), + grant(40) => grant_signal(40), + grant(41) => grant_signal(41), + grant(42) => grant_signal(42), + grant(43) => grant_signal(43), + grant(44) => grant_signal(44), + grant(45) => grant_signal(45), + grant(46) => grant_signal(46), + grant(47) => grant_signal(47), + grant(48) => grant_signal(48), + fifo_full =>fifo_in_full(3), + priority_rotation => priority_rotation_signal(3), + fifo_empty => fifo_in_empty(3), + data_out =>crossbar_in_port3, + data_out_pulse =>crossbar_in_pulse3, + request(33) =>request_signal(33), + request(34) =>request_signal(34), + request(35) =>request_signal(35), + request(36) =>request_signal(36), + request(37) =>request_signal(37), + request(38) =>request_signal(38), + request(39) =>request_signal(39), + request(40) =>request_signal(40), + request(41) =>request_signal(41), + request(42) =>request_signal(42), + request(43) =>request_signal(43), + request(44) =>request_signal(44), + request(45) =>request_signal(45), + request(46) =>request_signal(46), + request(47) =>request_signal(47), + request(48) =>request_signal(48) +); + +PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port4_in, + data_in_en => data_in_en(4), + reset => reset, + clk =>clk, + grant(49) => grant_signal(49), + grant(50) => grant_signal(50), + grant(51) => grant_signal(51), + grant(52) => grant_signal(52), + grant(53) => grant_signal(53), + grant(54) => grant_signal(54), + grant(55) => grant_signal(55), + grant(56) => grant_signal(56), + grant(57) => grant_signal(57), + grant(58) => grant_signal(58), + grant(59) => grant_signal(59), + grant(60) => grant_signal(60), + grant(61) => grant_signal(61), + grant(62) => grant_signal(62), + grant(63) => grant_signal(63), + grant(64) => grant_signal(64), + fifo_full =>fifo_in_full(4), + priority_rotation => priority_rotation_signal(4), + fifo_empty => fifo_in_empty(4), + data_out =>crossbar_in_port4, + data_out_pulse =>crossbar_in_pulse4, + request(49) =>request_signal(49), + request(50) =>request_signal(50), + request(51) =>request_signal(51), + request(52) =>request_signal(52), + request(53) =>request_signal(53), + request(54) =>request_signal(54), + request(55) =>request_signal(55), + request(56) =>request_signal(56), + request(57) =>request_signal(57), + request(58) =>request_signal(58), + request(59) =>request_signal(59), + request(60) =>request_signal(60), + request(61) =>request_signal(61), + request(62) =>request_signal(62), + request(63) =>request_signal(63), + request(64) =>request_signal(64) +); + +PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port5_in, + data_in_en => data_in_en(5), + reset => reset, + clk =>clk, + grant(65) => grant_signal(65), + grant(66) => grant_signal(66), + grant(67) => grant_signal(67), + grant(68) => grant_signal(68), + grant(69) => grant_signal(69), + grant(70) => grant_signal(70), + grant(71) => grant_signal(71), + grant(72) => grant_signal(72), + grant(73) => grant_signal(73), + grant(74) => grant_signal(74), + grant(75) => grant_signal(75), + grant(76) => grant_signal(76), + grant(77) => grant_signal(77), + grant(78) => grant_signal(78), + grant(79) => grant_signal(79), + grant(80) => grant_signal(80), + fifo_full =>fifo_in_full(5), + priority_rotation => priority_rotation_signal(5), + fifo_empty => fifo_in_empty(5), + data_out =>crossbar_in_port5, + data_out_pulse =>crossbar_in_pulse5, + request(65) =>request_signal(65), + request(66) =>request_signal(66), + request(67) =>request_signal(67), + request(68) =>request_signal(68), + request(69) =>request_signal(69), + request(70) =>request_signal(70), + request(71) =>request_signal(71), + request(72) =>request_signal(72), + request(73) =>request_signal(73), + request(74) =>request_signal(74), + request(75) =>request_signal(75), + request(76) =>request_signal(76), + request(77) =>request_signal(77), + request(78) =>request_signal(78), + request(79) =>request_signal(79), + request(80) =>request_signal(80) +); + +PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port6_in, + data_in_en => data_in_en(6), + reset => reset, + clk =>clk, + grant(81) => grant_signal(81), + grant(82) => grant_signal(82), + grant(83) => grant_signal(83), + grant(84) => grant_signal(84), + grant(85) => grant_signal(85), + grant(86) => grant_signal(86), + grant(87) => grant_signal(87), + grant(88) => grant_signal(88), + grant(89) => grant_signal(89), + grant(90) => grant_signal(90), + grant(91) => grant_signal(91), + grant(92) => grant_signal(92), + grant(93) => grant_signal(93), + grant(94) => grant_signal(94), + grant(95) => grant_signal(95), + grant(96) => grant_signal(96), + fifo_full =>fifo_in_full(6), + priority_rotation => priority_rotation_signal(6), + fifo_empty => fifo_in_empty(6), + data_out =>crossbar_in_port6, + data_out_pulse =>crossbar_in_pulse6, + request(81) =>request_signal(81), + request(82) =>request_signal(82), + request(83) =>request_signal(83), + request(84) =>request_signal(84), + request(85) =>request_signal(85), + request(86) =>request_signal(86), + request(87) =>request_signal(87), + request(88) =>request_signal(88), + request(89) =>request_signal(89), + request(90) =>request_signal(90), + request(91) =>request_signal(91), + request(92) =>request_signal(92), + request(93) =>request_signal(93), + request(94) =>request_signal(94), + request(95) =>request_signal(95), + request(96) =>request_signal(96) +); + +PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port7_in, + data_in_en => data_in_en(7), + reset => reset, + clk =>clk, + grant(97) => grant_signal(97), + grant(98) => grant_signal(98), + grant(99) => grant_signal(99), + grant(100) => grant_signal(100), + grant(101) => grant_signal(101), + grant(102) => grant_signal(102), + grant(103) => grant_signal(103), + grant(104) => grant_signal(104), + grant(105) => grant_signal(105), + grant(106) => grant_signal(106), + grant(107) => grant_signal(107), + grant(108) => grant_signal(108), + grant(109) => grant_signal(109), + grant(110) => grant_signal(110), + grant(111) => grant_signal(111), + grant(112) => grant_signal(112), + fifo_full =>fifo_in_full(7), + priority_rotation => priority_rotation_signal(7), + fifo_empty => fifo_in_empty(7), + data_out =>crossbar_in_port7, + data_out_pulse =>crossbar_in_pulse7, + request(97) =>request_signal(97), + request(98) =>request_signal(98), + request(99) =>request_signal(99), + request(100) =>request_signal(100), + request(101) =>request_signal(101), + request(102) =>request_signal(102), + request(103) =>request_signal(103), + request(104) =>request_signal(104), + request(105) =>request_signal(105), + request(106) =>request_signal(106), + request(107) =>request_signal(107), + request(108) =>request_signal(108), + request(109) =>request_signal(109), + request(110) =>request_signal(110), + request(111) =>request_signal(111), + request(112) =>request_signal(112) +); + +PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port8_in, + data_in_en => data_in_en(8), + reset => reset, + clk =>clk, + grant(113) => grant_signal(113), + grant(114) => grant_signal(114), + grant(115) => grant_signal(115), + grant(116) => grant_signal(116), + grant(117) => grant_signal(117), + grant(118) => grant_signal(118), + grant(119) => grant_signal(119), + grant(120) => grant_signal(120), + grant(121) => grant_signal(121), + grant(122) => grant_signal(122), + grant(123) => grant_signal(123), + grant(124) => grant_signal(124), + grant(125) => grant_signal(125), + grant(126) => grant_signal(126), + grant(127) => grant_signal(127), + grant(128) => grant_signal(128), + fifo_full =>fifo_in_full(8), + priority_rotation => priority_rotation_signal(8), + fifo_empty => fifo_in_empty(8), + data_out =>crossbar_in_port8, + data_out_pulse =>crossbar_in_pulse8, + request(113) =>request_signal(113), + request(114) =>request_signal(114), + request(115) =>request_signal(115), + request(116) =>request_signal(116), + request(117) =>request_signal(117), + request(118) =>request_signal(118), + request(119) =>request_signal(119), + request(120) =>request_signal(120), + request(121) =>request_signal(121), + request(122) =>request_signal(122), + request(123) =>request_signal(123), + request(124) =>request_signal(124), + request(125) =>request_signal(125), + request(126) =>request_signal(126), + request(127) =>request_signal(127), + request(128) =>request_signal(128) +); + +PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port9_in, + data_in_en => data_in_en(9), + reset => reset, + clk =>clk, + grant(129) => grant_signal(129), + grant(130) => grant_signal(130), + grant(131) => grant_signal(131), + grant(132) => grant_signal(132), + grant(133) => grant_signal(133), + grant(134) => grant_signal(134), + grant(135) => grant_signal(135), + grant(136) => grant_signal(136), + grant(137) => grant_signal(137), + grant(138) => grant_signal(138), + grant(139) => grant_signal(139), + grant(140) => grant_signal(140), + grant(141) => grant_signal(141), + grant(142) => grant_signal(142), + grant(143) => grant_signal(143), + grant(144) => grant_signal(144), + fifo_full =>fifo_in_full(9), + priority_rotation => priority_rotation_signal(9), + fifo_empty => fifo_in_empty(9), + data_out =>crossbar_in_port9, + data_out_pulse =>crossbar_in_pulse9, + request(129) =>request_signal(129), + request(130) =>request_signal(130), + request(131) =>request_signal(131), + request(132) =>request_signal(132), + request(133) =>request_signal(133), + request(134) =>request_signal(134), + request(135) =>request_signal(135), + request(136) =>request_signal(136), + request(137) =>request_signal(137), + request(138) =>request_signal(138), + request(139) =>request_signal(139), + request(140) =>request_signal(140), + request(141) =>request_signal(141), + request(142) =>request_signal(142), + request(143) =>request_signal(143), + request(144) =>request_signal(144) +); + +PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port10_in, + data_in_en => data_in_en(10), + reset => reset, + clk =>clk, + grant(145) => grant_signal(145), + grant(146) => grant_signal(146), + grant(147) => grant_signal(147), + grant(148) => grant_signal(148), + grant(149) => grant_signal(149), + grant(150) => grant_signal(150), + grant(151) => grant_signal(151), + grant(152) => grant_signal(152), + grant(153) => grant_signal(153), + grant(154) => grant_signal(154), + grant(155) => grant_signal(155), + grant(156) => grant_signal(156), + grant(157) => grant_signal(157), + grant(158) => grant_signal(158), + grant(159) => grant_signal(159), + grant(160) => grant_signal(160), + fifo_full =>fifo_in_full(10), + priority_rotation => priority_rotation_signal(10), + fifo_empty => fifo_in_empty(10), + data_out =>crossbar_in_port10, + data_out_pulse =>crossbar_in_pulse10, + request(145) =>request_signal(145), + request(146) =>request_signal(146), + request(147) =>request_signal(147), + request(148) =>request_signal(148), + request(149) =>request_signal(149), + request(150) =>request_signal(150), + request(151) =>request_signal(151), + request(152) =>request_signal(152), + request(153) =>request_signal(153), + request(154) =>request_signal(154), + request(155) =>request_signal(155), + request(156) =>request_signal(156), + request(157) =>request_signal(157), + request(158) =>request_signal(158), + request(159) =>request_signal(159), + request(160) =>request_signal(160) +); + +PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port11_in, + data_in_en => data_in_en(11), + reset => reset, + clk =>clk, + grant(161) => grant_signal(161), + grant(162) => grant_signal(162), + grant(163) => grant_signal(163), + grant(164) => grant_signal(164), + grant(165) => grant_signal(165), + grant(166) => grant_signal(166), + grant(167) => grant_signal(167), + grant(168) => grant_signal(168), + grant(169) => grant_signal(169), + grant(170) => grant_signal(170), + grant(171) => grant_signal(171), + grant(172) => grant_signal(172), + grant(173) => grant_signal(173), + grant(174) => grant_signal(174), + grant(175) => grant_signal(175), + grant(176) => grant_signal(176), + fifo_full =>fifo_in_full(11), + priority_rotation => priority_rotation_signal(11), + fifo_empty => fifo_in_empty(11), + data_out =>crossbar_in_port11, + data_out_pulse =>crossbar_in_pulse11, + request(161) =>request_signal(161), + request(162) =>request_signal(162), + request(163) =>request_signal(163), + request(164) =>request_signal(164), + request(165) =>request_signal(165), + request(166) =>request_signal(166), + request(167) =>request_signal(167), + request(168) =>request_signal(168), + request(169) =>request_signal(169), + request(170) =>request_signal(170), + request(171) =>request_signal(171), + request(172) =>request_signal(172), + request(173) =>request_signal(173), + request(174) =>request_signal(174), + request(175) =>request_signal(175), + request(176) =>request_signal(176) +); + +PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port12_in, + data_in_en => data_in_en(12), + reset => reset, + clk =>clk, + grant(177) => grant_signal(177), + grant(178) => grant_signal(178), + grant(179) => grant_signal(179), + grant(180) => grant_signal(180), + grant(181) => grant_signal(181), + grant(182) => grant_signal(182), + grant(183) => grant_signal(183), + grant(184) => grant_signal(184), + grant(185) => grant_signal(185), + grant(186) => grant_signal(186), + grant(187) => grant_signal(187), + grant(188) => grant_signal(188), + grant(189) => grant_signal(189), + grant(190) => grant_signal(190), + grant(191) => grant_signal(191), + grant(192) => grant_signal(192), + fifo_full =>fifo_in_full(12), + priority_rotation => priority_rotation_signal(12), + fifo_empty => fifo_in_empty(12), + data_out =>crossbar_in_port12, + data_out_pulse =>crossbar_in_pulse12, + request(177) =>request_signal(177), + request(178) =>request_signal(178), + request(179) =>request_signal(179), + request(180) =>request_signal(180), + request(181) =>request_signal(181), + request(182) =>request_signal(182), + request(183) =>request_signal(183), + request(184) =>request_signal(184), + request(185) =>request_signal(185), + request(186) =>request_signal(186), + request(187) =>request_signal(187), + request(188) =>request_signal(188), + request(189) =>request_signal(189), + request(190) =>request_signal(190), + request(191) =>request_signal(191), + request(192) =>request_signal(192) +); + +PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port13_in, + data_in_en => data_in_en(13), + reset => reset, + clk =>clk, + grant(193) => grant_signal(193), + grant(194) => grant_signal(194), + grant(195) => grant_signal(195), + grant(196) => grant_signal(196), + grant(197) => grant_signal(197), + grant(198) => grant_signal(198), + grant(199) => grant_signal(199), + grant(200) => grant_signal(200), + grant(201) => grant_signal(201), + grant(202) => grant_signal(202), + grant(203) => grant_signal(203), + grant(204) => grant_signal(204), + grant(205) => grant_signal(205), + grant(206) => grant_signal(206), + grant(207) => grant_signal(207), + grant(208) => grant_signal(208), + fifo_full =>fifo_in_full(13), + priority_rotation => priority_rotation_signal(13), + fifo_empty => fifo_in_empty(13), + data_out =>crossbar_in_port13, + data_out_pulse =>crossbar_in_pulse13, + request(193) =>request_signal(193), + request(194) =>request_signal(194), + request(195) =>request_signal(195), + request(196) =>request_signal(196), + request(197) =>request_signal(197), + request(198) =>request_signal(198), + request(199) =>request_signal(199), + request(200) =>request_signal(200), + request(201) =>request_signal(201), + request(202) =>request_signal(202), + request(203) =>request_signal(203), + request(204) =>request_signal(204), + request(205) =>request_signal(205), + request(206) =>request_signal(206), + request(207) =>request_signal(207), + request(208) =>request_signal(208) +); + +PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port14_in, + data_in_en => data_in_en(14), + reset => reset, + clk =>clk, + grant(209) => grant_signal(209), + grant(210) => grant_signal(210), + grant(211) => grant_signal(211), + grant(212) => grant_signal(212), + grant(213) => grant_signal(213), + grant(214) => grant_signal(214), + grant(215) => grant_signal(215), + grant(216) => grant_signal(216), + grant(217) => grant_signal(217), + grant(218) => grant_signal(218), + grant(219) => grant_signal(219), + grant(220) => grant_signal(220), + grant(221) => grant_signal(221), + grant(222) => grant_signal(222), + grant(223) => grant_signal(223), + grant(224) => grant_signal(224), + fifo_full =>fifo_in_full(14), + priority_rotation => priority_rotation_signal(14), + fifo_empty => fifo_in_empty(14), + data_out =>crossbar_in_port14, + data_out_pulse =>crossbar_in_pulse14, + request(209) =>request_signal(209), + request(210) =>request_signal(210), + request(211) =>request_signal(211), + request(212) =>request_signal(212), + request(213) =>request_signal(213), + request(214) =>request_signal(214), + request(215) =>request_signal(215), + request(216) =>request_signal(216), + request(217) =>request_signal(217), + request(218) =>request_signal(218), + request(219) =>request_signal(219), + request(220) =>request_signal(220), + request(221) =>request_signal(221), + request(222) =>request_signal(222), + request(223) =>request_signal(223), + request(224) =>request_signal(224) +); + +PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port15_in, + data_in_en => data_in_en(15), + reset => reset, + clk =>clk, + grant(225) => grant_signal(225), + grant(226) => grant_signal(226), + grant(227) => grant_signal(227), + grant(228) => grant_signal(228), + grant(229) => grant_signal(229), + grant(230) => grant_signal(230), + grant(231) => grant_signal(231), + grant(232) => grant_signal(232), + grant(233) => grant_signal(233), + grant(234) => grant_signal(234), + grant(235) => grant_signal(235), + grant(236) => grant_signal(236), + grant(237) => grant_signal(237), + grant(238) => grant_signal(238), + grant(239) => grant_signal(239), + grant(240) => grant_signal(240), + fifo_full =>fifo_in_full(15), + priority_rotation => priority_rotation_signal(15), + fifo_empty => fifo_in_empty(15), + data_out =>crossbar_in_port15, + data_out_pulse =>crossbar_in_pulse15, + request(225) =>request_signal(225), + request(226) =>request_signal(226), + request(227) =>request_signal(227), + request(228) =>request_signal(228), + request(229) =>request_signal(229), + request(230) =>request_signal(230), + request(231) =>request_signal(231), + request(232) =>request_signal(232), + request(233) =>request_signal(233), + request(234) =>request_signal(234), + request(235) =>request_signal(235), + request(236) =>request_signal(236), + request(237) =>request_signal(237), + request(238) =>request_signal(238), + request(239) =>request_signal(239), + request(240) =>request_signal(240) +); + +PORT16_INPUT_PORT_MODULE: INPUT_PORT_MODULE +GENERIC MAP(number_of_ports =>16) +PORT MAP( + data_in => Port16_in, + data_in_en => data_in_en(16), + reset => reset, + clk =>clk, + grant(241) => grant_signal(241), + grant(242) => grant_signal(242), + grant(243) => grant_signal(243), + grant(244) => grant_signal(244), + grant(245) => grant_signal(245), + grant(246) => grant_signal(246), + grant(247) => grant_signal(247), + grant(248) => grant_signal(248), + grant(249) => grant_signal(249), + grant(250) => grant_signal(250), + grant(251) => grant_signal(251), + grant(252) => grant_signal(252), + grant(253) => grant_signal(253), + grant(254) => grant_signal(254), + grant(255) => grant_signal(255), + grant(256) => grant_signal(256), + fifo_full =>fifo_in_full(16), + priority_rotation => priority_rotation_signal(16), + fifo_empty => fifo_in_empty(16), + data_out =>crossbar_in_port16, + data_out_pulse =>crossbar_in_pulse16, + request(241) =>request_signal(241), + request(242) =>request_signal(242), + request(243) =>request_signal(243), + request(244) =>request_signal(244), + request(245) =>request_signal(245), + request(246) =>request_signal(246), + request(247) =>request_signal(247), + request(248) =>request_signal(248), + request(249) =>request_signal(249), + request(250) =>request_signal(250), + request(251) =>request_signal(251), + request(252) =>request_signal(252), + request(253) =>request_signal(253), + request(254) =>request_signal(254), + request(255) =>request_signal(255), + request(256) =>request_signal(256) +); + +end generate switch16x16; +-- intstanciation et connexion des modules des ports de sorties fonction du nombre de ports +-- le circuit genere depend du parametre generique nombre de ports +-- switch 2 ports +port_out_switch2x2 : if number_of_ports = 2 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +end generate port_out_switch2x2; + + +-- switch 3 ports +port_out_switch3x3 : if number_of_ports = 3 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port3, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse3, + data_out =>Port3_out, + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +end generate port_out_switch3x3; + + +-- switch 4 ports +port_out_switch4x4 : if number_of_ports = 4 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port3, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse3, + data_out =>Port3_out, + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port4, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse4, + data_out =>Port4_out, + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +end generate port_out_switch4x4; + + +-- switch 5 ports +port_out_switch5x5 : if number_of_ports = 5 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port3, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse3, + data_out =>Port3_out, + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port4, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse4, + data_out =>Port4_out, + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port5, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse5, + data_out =>Port5_out, + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +end generate port_out_switch5x5; + + +-- switch 6 ports +port_out_switch6x6 : if number_of_ports = 6 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port3, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse3, + data_out =>Port3_out, + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port4, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse4, + data_out =>Port4_out, + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port5, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse5, + data_out =>Port5_out, + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port6, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse6, + data_out =>Port6_out, + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +end generate port_out_switch6x6; + + +-- switch 7 ports +port_out_switch7x7 : if number_of_ports = 7 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port3, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse3, + data_out =>Port3_out, + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port4, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse4, + data_out =>Port4_out, + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port5, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse5, + data_out =>Port5_out, + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port6, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse6, + data_out =>Port6_out, + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port7, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse7, + data_out =>Port7_out, + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +end generate port_out_switch7x7; + + +-- switch 8 ports +port_out_switch8x8 : if number_of_ports = 8 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port3, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse3, + data_out =>Port3_out, + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port4, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse4, + data_out =>Port4_out, + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port5, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse5, + data_out =>Port5_out, + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port6, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse6, + data_out =>Port6_out, + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port7, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse7, + data_out =>Port7_out, + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port8, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse8, + data_out =>Port8_out, + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +end generate port_out_switch8x8; + + +-- switch 9 ports +port_out_switch9x9 : if number_of_ports = 9 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port3, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse3, + data_out =>Port3_out, + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port4, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse4, + data_out =>Port4_out, + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port5, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse5, + data_out =>Port5_out, + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port6, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse6, + data_out =>Port6_out, + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port7, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse7, + data_out =>Port7_out, + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port8, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse8, + data_out =>Port8_out, + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port9, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse9, + data_out =>Port9_out, + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +end generate port_out_switch9x9; + + +-- switch 10 ports +port_out_switch10x10 : if number_of_ports = 10 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port3, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse3, + data_out =>Port3_out, + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port4, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse4, + data_out =>Port4_out, + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port5, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse5, + data_out =>Port5_out, + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port6, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse6, + data_out =>Port6_out, + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port7, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse7, + data_out =>Port7_out, + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port8, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse8, + data_out =>Port8_out, + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port9, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse9, + data_out =>Port9_out, + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port10, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse10, + data_out =>Port10_out, + fifo_full =>fifo_out_full_signal(10), + data_avalaible => data_available(10), + rd_out_en => data_out_en(10) + ); + +end generate port_out_switch10x10; + + +-- switch 11 ports +port_out_switch11x11 : if number_of_ports = 11 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port3, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse3, + data_out =>Port3_out, + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port4, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse4, + data_out =>Port4_out, + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port5, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse5, + data_out =>Port5_out, + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port6, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse6, + data_out =>Port6_out, + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port7, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse7, + data_out =>Port7_out, + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port8, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse8, + data_out =>Port8_out, + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port9, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse9, + data_out =>Port9_out, + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port10, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse10, + data_out =>Port10_out, + fifo_full =>fifo_out_full_signal(10), + data_avalaible => data_available(10), + rd_out_en => data_out_en(10) + ); + +PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port11, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse11, + data_out =>Port11_out, + fifo_full =>fifo_out_full_signal(11), + data_avalaible => data_available(11), + rd_out_en => data_out_en(11) + ); + +end generate port_out_switch11x11; + + +-- switch 12 ports +port_out_switch12x12 : if number_of_ports = 12 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port3, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse3, + data_out =>Port3_out, + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port4, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse4, + data_out =>Port4_out, + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port5, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse5, + data_out =>Port5_out, + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port6, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse6, + data_out =>Port6_out, + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port7, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse7, + data_out =>Port7_out, + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port8, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse8, + data_out =>Port8_out, + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port9, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse9, + data_out =>Port9_out, + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port10, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse10, + data_out =>Port10_out, + fifo_full =>fifo_out_full_signal(10), + data_avalaible => data_available(10), + rd_out_en => data_out_en(10) + ); + +PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port11, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse11, + data_out =>Port11_out, + fifo_full =>fifo_out_full_signal(11), + data_avalaible => data_available(11), + rd_out_en => data_out_en(11) + ); + +PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port12, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse12, + data_out =>Port12_out, + fifo_full =>fifo_out_full_signal(12), + data_avalaible => data_available(12), + rd_out_en => data_out_en(12) + ); + +end generate port_out_switch12x12; + + +-- switch 13 ports +port_out_switch13x13 : if number_of_ports = 13 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port3, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse3, + data_out =>Port3_out, + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port4, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse4, + data_out =>Port4_out, + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port5, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse5, + data_out =>Port5_out, + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port6, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse6, + data_out =>Port6_out, + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port7, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse7, + data_out =>Port7_out, + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port8, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse8, + data_out =>Port8_out, + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port9, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse9, + data_out =>Port9_out, + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port10, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse10, + data_out =>Port10_out, + fifo_full =>fifo_out_full_signal(10), + data_avalaible => data_available(10), + rd_out_en => data_out_en(10) + ); + +PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port11, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse11, + data_out =>Port11_out, + fifo_full =>fifo_out_full_signal(11), + data_avalaible => data_available(11), + rd_out_en => data_out_en(11) + ); + +PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port12, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse12, + data_out =>Port12_out, + fifo_full =>fifo_out_full_signal(12), + data_avalaible => data_available(12), + rd_out_en => data_out_en(12) + ); + +PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port13, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse13, + data_out =>Port13_out, + fifo_full =>fifo_out_full_signal(13), + data_avalaible => data_available(13), + rd_out_en => data_out_en(13) + ); + +end generate port_out_switch13x13; + + +-- switch 14 ports +port_out_switch14x14 : if number_of_ports = 14 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port3, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse3, + data_out =>Port3_out, + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port4, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse4, + data_out =>Port4_out, + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port5, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse5, + data_out =>Port5_out, + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port6, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse6, + data_out =>Port6_out, + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port7, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse7, + data_out =>Port7_out, + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port8, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse8, + data_out =>Port8_out, + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port9, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse9, + data_out =>Port9_out, + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port10, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse10, + data_out =>Port10_out, + fifo_full =>fifo_out_full_signal(10), + data_avalaible => data_available(10), + rd_out_en => data_out_en(10) + ); + +PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port11, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse11, + data_out =>Port11_out, + fifo_full =>fifo_out_full_signal(11), + data_avalaible => data_available(11), + rd_out_en => data_out_en(11) + ); + +PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port12, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse12, + data_out =>Port12_out, + fifo_full =>fifo_out_full_signal(12), + data_avalaible => data_available(12), + rd_out_en => data_out_en(12) + ); + +PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port13, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse13, + data_out =>Port13_out, + fifo_full =>fifo_out_full_signal(13), + data_avalaible => data_available(13), + rd_out_en => data_out_en(13) + ); + +PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port14, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse14, + data_out =>Port14_out, + fifo_full =>fifo_out_full_signal(14), + data_avalaible => data_available(14), + rd_out_en => data_out_en(14) + ); + +end generate port_out_switch14x14; + + +-- switch 15 ports +port_out_switch15x15 : if number_of_ports = 15 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port3, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse3, + data_out =>Port3_out, + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port4, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse4, + data_out =>Port4_out, + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port5, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse5, + data_out =>Port5_out, + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port6, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse6, + data_out =>Port6_out, + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port7, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse7, + data_out =>Port7_out, + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port8, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse8, + data_out =>Port8_out, + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port9, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse9, + data_out =>Port9_out, + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port10, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse10, + data_out =>Port10_out, + fifo_full =>fifo_out_full_signal(10), + data_avalaible => data_available(10), + rd_out_en => data_out_en(10) + ); + +PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port11, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse11, + data_out =>Port11_out, + fifo_full =>fifo_out_full_signal(11), + data_avalaible => data_available(11), + rd_out_en => data_out_en(11) + ); + +PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port12, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse12, + data_out =>Port12_out, + fifo_full =>fifo_out_full_signal(12), + data_avalaible => data_available(12), + rd_out_en => data_out_en(12) + ); + +PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port13, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse13, + data_out =>Port13_out, + fifo_full =>fifo_out_full_signal(13), + data_avalaible => data_available(13), + rd_out_en => data_out_en(13) + ); + +PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port14, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse14, + data_out =>Port14_out, + fifo_full =>fifo_out_full_signal(14), + data_avalaible => data_available(14), + rd_out_en => data_out_en(14) + ); + +PORT15_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port15, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse15, + data_out =>Port15_out, + fifo_full =>fifo_out_full_signal(15), + data_avalaible => data_available(15), + rd_out_en => data_out_en(15) + ); + +end generate port_out_switch15x15; + + +-- switch 16 ports +port_out_switch16x16 : if number_of_ports = 16 generate + +PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port1, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse1, + data_out =>Port1_out, + fifo_full =>fifo_out_full_signal(1), + data_avalaible => data_available(1), + rd_out_en => data_out_en(1) + ); + +PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port2, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse2, + data_out =>Port2_out, + fifo_full =>fifo_out_full_signal(2), + data_avalaible => data_available(2), + rd_out_en => data_out_en(2) + ); + +PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port3, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse3, + data_out =>Port3_out, + fifo_full =>fifo_out_full_signal(3), + data_avalaible => data_available(3), + rd_out_en => data_out_en(3) + ); + +PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port4, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse4, + data_out =>Port4_out, + fifo_full =>fifo_out_full_signal(4), + data_avalaible => data_available(4), + rd_out_en => data_out_en(4) + ); + +PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port5, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse5, + data_out =>Port5_out, + fifo_full =>fifo_out_full_signal(5), + data_avalaible => data_available(5), + rd_out_en => data_out_en(5) + ); + +PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port6, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse6, + data_out =>Port6_out, + fifo_full =>fifo_out_full_signal(6), + data_avalaible => data_available(6), + rd_out_en => data_out_en(6) + ); + +PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port7, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse7, + data_out =>Port7_out, + fifo_full =>fifo_out_full_signal(7), + data_avalaible => data_available(7), + rd_out_en => data_out_en(7) + ); + +PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port8, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse8, + data_out =>Port8_out, + fifo_full =>fifo_out_full_signal(8), + data_avalaible => data_available(8), + rd_out_en => data_out_en(8) + ); + +PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port9, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse9, + data_out =>Port9_out, + fifo_full =>fifo_out_full_signal(9), + data_avalaible => data_available(9), + rd_out_en => data_out_en(9) + ); + +PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port10, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse10, + data_out =>Port10_out, + fifo_full =>fifo_out_full_signal(10), + data_avalaible => data_available(10), + rd_out_en => data_out_en(10) + ); + +PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port11, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse11, + data_out =>Port11_out, + fifo_full =>fifo_out_full_signal(11), + data_avalaible => data_available(11), + rd_out_en => data_out_en(11) + ); + +PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port12, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse12, + data_out =>Port12_out, + fifo_full =>fifo_out_full_signal(12), + data_avalaible => data_available(12), + rd_out_en => data_out_en(12) + ); + +PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port13, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse13, + data_out =>Port13_out, + fifo_full =>fifo_out_full_signal(13), + data_avalaible => data_available(13), + rd_out_en => data_out_en(13) + ); + +PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port14, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse14, + data_out =>Port14_out, + fifo_full =>fifo_out_full_signal(14), + data_avalaible => data_available(14), + rd_out_en => data_out_en(14) + ); + +PORT15_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port15, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse15, + data_out =>Port15_out, + fifo_full =>fifo_out_full_signal(15), + data_avalaible => data_available(15), + rd_out_en => data_out_en(15) + ); + +PORT16_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE + PORT MAP( + data_in => crossbar_out_port16, + reset => reset, + clk => clk, + wr_en =>crossbar_out_pulse16, + data_out =>Port16_out, + fifo_full =>fifo_out_full_signal(16), + data_avalaible => data_available(16), + rd_out_en => data_out_en(16) + ); + +end generate port_out_switch16x16; + +-- intstanciation et connexion des crossbars du switch en fonction du nombre de ports +-- le circuit genere depend du parametre generique nombre de ports +-- switch 2 ports +crossbar_switch2x2 : if number_of_ports = 2 generate + +Switch_Crossbar2_2: Crossbar +GENERIC MAP(number_of_crossbar_ports =>2) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => "00000000", + Port4_in => "00000000", + Port5_in => "00000000", + Port6_in => "00000000", + Port7_in => "00000000", + Port8_in => "00000000", + Port9_in => "00000000", + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in =>'0' , + Port4_pulse_in =>'0' , + Port5_pulse_in =>'0' , + Port6_pulse_in =>'0' , + Port7_pulse_in =>'0' , + Port8_pulse_in =>'0' , + Port9_pulse_in =>'0' , + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Ctrl => Grant_signal); +end generate crossbar_switch2x2; + + +-- switch 3 ports +crossbar_switch3x3 : if number_of_ports = 3 generate + +Switch_Crossbar3_3: Crossbar +GENERIC MAP(number_of_crossbar_ports =>3) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => crossbar_in_port3, + Port4_in => "00000000", + Port5_in => "00000000", + Port6_in => "00000000", + Port7_in => "00000000", + Port8_in => "00000000", + Port9_in => "00000000", + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in => crossbar_in_pulse3, + Port4_pulse_in =>'0' , + Port5_pulse_in =>'0' , + Port6_pulse_in =>'0' , + Port7_pulse_in =>'0' , + Port8_pulse_in =>'0' , + Port9_pulse_in =>'0' , + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port3_pulse_out => crossbar_out_pulse3, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Port3_out => crossbar_out_port3, + Ctrl => Grant_signal); +end generate crossbar_switch3x3; + + +-- switch 4 ports +crossbar_switch4x4 : if number_of_ports = 4 generate + +Switch_Crossbar4_4: Crossbar +GENERIC MAP(number_of_crossbar_ports =>4) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => crossbar_in_port3, + Port4_in => crossbar_in_port4, + Port5_in => "00000000", + Port6_in => "00000000", + Port7_in => "00000000", + Port8_in => "00000000", + Port9_in => "00000000", + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in => crossbar_in_pulse3, + Port4_pulse_in => crossbar_in_pulse4, + Port5_pulse_in =>'0' , + Port6_pulse_in =>'0' , + Port7_pulse_in =>'0' , + Port8_pulse_in =>'0' , + Port9_pulse_in =>'0' , + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port3_pulse_out => crossbar_out_pulse3, + Port4_pulse_out => crossbar_out_pulse4, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Port3_out => crossbar_out_port3, + Port4_out => crossbar_out_port4, + Ctrl => Grant_signal); +end generate crossbar_switch4x4; + + +-- switch 5 ports +crossbar_switch5x5 : if number_of_ports = 5 generate + +Switch_Crossbar5_5: Crossbar +GENERIC MAP(number_of_crossbar_ports =>5) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => crossbar_in_port3, + Port4_in => crossbar_in_port4, + Port5_in => crossbar_in_port5, + Port6_in => "00000000", + Port7_in => "00000000", + Port8_in => "00000000", + Port9_in => "00000000", + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in => crossbar_in_pulse3, + Port4_pulse_in => crossbar_in_pulse4, + Port5_pulse_in => crossbar_in_pulse5, + Port6_pulse_in =>'0' , + Port7_pulse_in =>'0' , + Port8_pulse_in =>'0' , + Port9_pulse_in =>'0' , + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port3_pulse_out => crossbar_out_pulse3, + Port4_pulse_out => crossbar_out_pulse4, + Port5_pulse_out => crossbar_out_pulse5, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Port3_out => crossbar_out_port3, + Port4_out => crossbar_out_port4, + Port5_out => crossbar_out_port5, + Ctrl => Grant_signal); +end generate crossbar_switch5x5; + + +-- switch 6 ports +crossbar_switch6x6 : if number_of_ports = 6 generate + +Switch_Crossbar6_6: Crossbar +GENERIC MAP(number_of_crossbar_ports =>6) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => crossbar_in_port3, + Port4_in => crossbar_in_port4, + Port5_in => crossbar_in_port5, + Port6_in => crossbar_in_port6, + Port7_in => "00000000", + Port8_in => "00000000", + Port9_in => "00000000", + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in => crossbar_in_pulse3, + Port4_pulse_in => crossbar_in_pulse4, + Port5_pulse_in => crossbar_in_pulse5, + Port6_pulse_in => crossbar_in_pulse6, + Port7_pulse_in =>'0' , + Port8_pulse_in =>'0' , + Port9_pulse_in =>'0' , + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port3_pulse_out => crossbar_out_pulse3, + Port4_pulse_out => crossbar_out_pulse4, + Port5_pulse_out => crossbar_out_pulse5, + Port6_pulse_out => crossbar_out_pulse6, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Port3_out => crossbar_out_port3, + Port4_out => crossbar_out_port4, + Port5_out => crossbar_out_port5, + Port6_out => crossbar_out_port6, + Ctrl => Grant_signal); +end generate crossbar_switch6x6; + + +-- switch 7 ports +crossbar_switch7x7 : if number_of_ports = 7 generate + +Switch_Crossbar7_7: Crossbar +GENERIC MAP(number_of_crossbar_ports =>7) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => crossbar_in_port3, + Port4_in => crossbar_in_port4, + Port5_in => crossbar_in_port5, + Port6_in => crossbar_in_port6, + Port7_in => crossbar_in_port7, + Port8_in => "00000000", + Port9_in => "00000000", + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in => crossbar_in_pulse3, + Port4_pulse_in => crossbar_in_pulse4, + Port5_pulse_in => crossbar_in_pulse5, + Port6_pulse_in => crossbar_in_pulse6, + Port7_pulse_in => crossbar_in_pulse7, + Port8_pulse_in =>'0' , + Port9_pulse_in =>'0' , + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port3_pulse_out => crossbar_out_pulse3, + Port4_pulse_out => crossbar_out_pulse4, + Port5_pulse_out => crossbar_out_pulse5, + Port6_pulse_out => crossbar_out_pulse6, + Port7_pulse_out => crossbar_out_pulse7, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Port3_out => crossbar_out_port3, + Port4_out => crossbar_out_port4, + Port5_out => crossbar_out_port5, + Port6_out => crossbar_out_port6, + Port7_out => crossbar_out_port7, + Ctrl => Grant_signal); +end generate crossbar_switch7x7; + + +-- switch 8 ports +crossbar_switch8x8 : if number_of_ports = 8 generate + +Switch_Crossbar8_8: Crossbar +GENERIC MAP(number_of_crossbar_ports =>8) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => crossbar_in_port3, + Port4_in => crossbar_in_port4, + Port5_in => crossbar_in_port5, + Port6_in => crossbar_in_port6, + Port7_in => crossbar_in_port7, + Port8_in => crossbar_in_port8, + Port9_in => "00000000", + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in => crossbar_in_pulse3, + Port4_pulse_in => crossbar_in_pulse4, + Port5_pulse_in => crossbar_in_pulse5, + Port6_pulse_in => crossbar_in_pulse6, + Port7_pulse_in => crossbar_in_pulse7, + Port8_pulse_in => crossbar_in_pulse8, + Port9_pulse_in =>'0' , + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port3_pulse_out => crossbar_out_pulse3, + Port4_pulse_out => crossbar_out_pulse4, + Port5_pulse_out => crossbar_out_pulse5, + Port6_pulse_out => crossbar_out_pulse6, + Port7_pulse_out => crossbar_out_pulse7, + Port8_pulse_out => crossbar_out_pulse8, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Port3_out => crossbar_out_port3, + Port4_out => crossbar_out_port4, + Port5_out => crossbar_out_port5, + Port6_out => crossbar_out_port6, + Port7_out => crossbar_out_port7, + Port8_out => crossbar_out_port8, + Ctrl => Grant_signal); +end generate crossbar_switch8x8; + + +-- switch 9 ports +crossbar_switch9x9 : if number_of_ports = 9 generate + +Switch_Crossbar9_9: Crossbar +GENERIC MAP(number_of_crossbar_ports =>9) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => crossbar_in_port3, + Port4_in => crossbar_in_port4, + Port5_in => crossbar_in_port5, + Port6_in => crossbar_in_port6, + Port7_in => crossbar_in_port7, + Port8_in => crossbar_in_port8, + Port9_in => crossbar_in_port9, + Port10_in => "00000000", + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in => crossbar_in_pulse3, + Port4_pulse_in => crossbar_in_pulse4, + Port5_pulse_in => crossbar_in_pulse5, + Port6_pulse_in => crossbar_in_pulse6, + Port7_pulse_in => crossbar_in_pulse7, + Port8_pulse_in => crossbar_in_pulse8, + Port9_pulse_in => crossbar_in_pulse9, + Port10_pulse_in =>'0' , + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port3_pulse_out => crossbar_out_pulse3, + Port4_pulse_out => crossbar_out_pulse4, + Port5_pulse_out => crossbar_out_pulse5, + Port6_pulse_out => crossbar_out_pulse6, + Port7_pulse_out => crossbar_out_pulse7, + Port8_pulse_out => crossbar_out_pulse8, + Port9_pulse_out => crossbar_out_pulse9, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Port3_out => crossbar_out_port3, + Port4_out => crossbar_out_port4, + Port5_out => crossbar_out_port5, + Port6_out => crossbar_out_port6, + Port7_out => crossbar_out_port7, + Port8_out => crossbar_out_port8, + Port9_out => crossbar_out_port9, + Ctrl => Grant_signal); +end generate crossbar_switch9x9; + + +-- switch 10 ports +crossbar_switch10x10 : if number_of_ports = 10 generate + +Switch_Crossbar10_10: Crossbar +GENERIC MAP(number_of_crossbar_ports =>10) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => crossbar_in_port3, + Port4_in => crossbar_in_port4, + Port5_in => crossbar_in_port5, + Port6_in => crossbar_in_port6, + Port7_in => crossbar_in_port7, + Port8_in => crossbar_in_port8, + Port9_in => crossbar_in_port9, + Port10_in => crossbar_in_port10, + Port11_in => "00000000", + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in => crossbar_in_pulse3, + Port4_pulse_in => crossbar_in_pulse4, + Port5_pulse_in => crossbar_in_pulse5, + Port6_pulse_in => crossbar_in_pulse6, + Port7_pulse_in => crossbar_in_pulse7, + Port8_pulse_in => crossbar_in_pulse8, + Port9_pulse_in => crossbar_in_pulse9, + Port10_pulse_in => crossbar_in_pulse10, + Port11_pulse_in =>'0' , + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port3_pulse_out => crossbar_out_pulse3, + Port4_pulse_out => crossbar_out_pulse4, + Port5_pulse_out => crossbar_out_pulse5, + Port6_pulse_out => crossbar_out_pulse6, + Port7_pulse_out => crossbar_out_pulse7, + Port8_pulse_out => crossbar_out_pulse8, + Port9_pulse_out => crossbar_out_pulse9, + Port10_pulse_out => crossbar_out_pulse10, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Port3_out => crossbar_out_port3, + Port4_out => crossbar_out_port4, + Port5_out => crossbar_out_port5, + Port6_out => crossbar_out_port6, + Port7_out => crossbar_out_port7, + Port8_out => crossbar_out_port8, + Port9_out => crossbar_out_port9, + Port10_out => crossbar_out_port10, + Ctrl => Grant_signal); +end generate crossbar_switch10x10; + + +-- switch 11 ports +crossbar_switch11x11 : if number_of_ports = 11 generate + +Switch_Crossbar11_11: Crossbar +GENERIC MAP(number_of_crossbar_ports =>11) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => crossbar_in_port3, + Port4_in => crossbar_in_port4, + Port5_in => crossbar_in_port5, + Port6_in => crossbar_in_port6, + Port7_in => crossbar_in_port7, + Port8_in => crossbar_in_port8, + Port9_in => crossbar_in_port9, + Port10_in => crossbar_in_port10, + Port11_in => crossbar_in_port11, + Port12_in => "00000000", + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in => crossbar_in_pulse3, + Port4_pulse_in => crossbar_in_pulse4, + Port5_pulse_in => crossbar_in_pulse5, + Port6_pulse_in => crossbar_in_pulse6, + Port7_pulse_in => crossbar_in_pulse7, + Port8_pulse_in => crossbar_in_pulse8, + Port9_pulse_in => crossbar_in_pulse9, + Port10_pulse_in => crossbar_in_pulse10, + Port11_pulse_in => crossbar_in_pulse11, + Port12_pulse_in =>'0' , + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port3_pulse_out => crossbar_out_pulse3, + Port4_pulse_out => crossbar_out_pulse4, + Port5_pulse_out => crossbar_out_pulse5, + Port6_pulse_out => crossbar_out_pulse6, + Port7_pulse_out => crossbar_out_pulse7, + Port8_pulse_out => crossbar_out_pulse8, + Port9_pulse_out => crossbar_out_pulse9, + Port10_pulse_out => crossbar_out_pulse10, + Port11_pulse_out => crossbar_out_pulse11, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Port3_out => crossbar_out_port3, + Port4_out => crossbar_out_port4, + Port5_out => crossbar_out_port5, + Port6_out => crossbar_out_port6, + Port7_out => crossbar_out_port7, + Port8_out => crossbar_out_port8, + Port9_out => crossbar_out_port9, + Port10_out => crossbar_out_port10, + Port11_out => crossbar_out_port11, + Ctrl => Grant_signal); +end generate crossbar_switch11x11; + + +-- switch 12 ports +crossbar_switch12x12 : if number_of_ports = 12 generate + +Switch_Crossbar12_12: Crossbar +GENERIC MAP(number_of_crossbar_ports =>12) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => crossbar_in_port3, + Port4_in => crossbar_in_port4, + Port5_in => crossbar_in_port5, + Port6_in => crossbar_in_port6, + Port7_in => crossbar_in_port7, + Port8_in => crossbar_in_port8, + Port9_in => crossbar_in_port9, + Port10_in => crossbar_in_port10, + Port11_in => crossbar_in_port11, + Port12_in => crossbar_in_port12, + Port13_in => "00000000", + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in => crossbar_in_pulse3, + Port4_pulse_in => crossbar_in_pulse4, + Port5_pulse_in => crossbar_in_pulse5, + Port6_pulse_in => crossbar_in_pulse6, + Port7_pulse_in => crossbar_in_pulse7, + Port8_pulse_in => crossbar_in_pulse8, + Port9_pulse_in => crossbar_in_pulse9, + Port10_pulse_in => crossbar_in_pulse10, + Port11_pulse_in => crossbar_in_pulse11, + Port12_pulse_in => crossbar_in_pulse12, + Port13_pulse_in =>'0' , + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port3_pulse_out => crossbar_out_pulse3, + Port4_pulse_out => crossbar_out_pulse4, + Port5_pulse_out => crossbar_out_pulse5, + Port6_pulse_out => crossbar_out_pulse6, + Port7_pulse_out => crossbar_out_pulse7, + Port8_pulse_out => crossbar_out_pulse8, + Port9_pulse_out => crossbar_out_pulse9, + Port10_pulse_out => crossbar_out_pulse10, + Port11_pulse_out => crossbar_out_pulse11, + Port12_pulse_out => crossbar_out_pulse12, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Port3_out => crossbar_out_port3, + Port4_out => crossbar_out_port4, + Port5_out => crossbar_out_port5, + Port6_out => crossbar_out_port6, + Port7_out => crossbar_out_port7, + Port8_out => crossbar_out_port8, + Port9_out => crossbar_out_port9, + Port10_out => crossbar_out_port10, + Port11_out => crossbar_out_port11, + Port12_out => crossbar_out_port12, + Ctrl => Grant_signal); +end generate crossbar_switch12x12; + + +-- switch 13 ports +crossbar_switch13x13 : if number_of_ports = 13 generate + +Switch_Crossbar13_13: Crossbar +GENERIC MAP(number_of_crossbar_ports =>13) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => crossbar_in_port3, + Port4_in => crossbar_in_port4, + Port5_in => crossbar_in_port5, + Port6_in => crossbar_in_port6, + Port7_in => crossbar_in_port7, + Port8_in => crossbar_in_port8, + Port9_in => crossbar_in_port9, + Port10_in => crossbar_in_port10, + Port11_in => crossbar_in_port11, + Port12_in => crossbar_in_port12, + Port13_in => crossbar_in_port13, + Port14_in => "00000000", + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in => crossbar_in_pulse3, + Port4_pulse_in => crossbar_in_pulse4, + Port5_pulse_in => crossbar_in_pulse5, + Port6_pulse_in => crossbar_in_pulse6, + Port7_pulse_in => crossbar_in_pulse7, + Port8_pulse_in => crossbar_in_pulse8, + Port9_pulse_in => crossbar_in_pulse9, + Port10_pulse_in => crossbar_in_pulse10, + Port11_pulse_in => crossbar_in_pulse11, + Port12_pulse_in => crossbar_in_pulse12, + Port13_pulse_in => crossbar_in_pulse13, + Port14_pulse_in =>'0' , + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port3_pulse_out => crossbar_out_pulse3, + Port4_pulse_out => crossbar_out_pulse4, + Port5_pulse_out => crossbar_out_pulse5, + Port6_pulse_out => crossbar_out_pulse6, + Port7_pulse_out => crossbar_out_pulse7, + Port8_pulse_out => crossbar_out_pulse8, + Port9_pulse_out => crossbar_out_pulse9, + Port10_pulse_out => crossbar_out_pulse10, + Port11_pulse_out => crossbar_out_pulse11, + Port12_pulse_out => crossbar_out_pulse12, + Port13_pulse_out => crossbar_out_pulse13, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Port3_out => crossbar_out_port3, + Port4_out => crossbar_out_port4, + Port5_out => crossbar_out_port5, + Port6_out => crossbar_out_port6, + Port7_out => crossbar_out_port7, + Port8_out => crossbar_out_port8, + Port9_out => crossbar_out_port9, + Port10_out => crossbar_out_port10, + Port11_out => crossbar_out_port11, + Port12_out => crossbar_out_port12, + Port13_out => crossbar_out_port13, + Ctrl => Grant_signal); +end generate crossbar_switch13x13; + + +-- switch 14 ports +crossbar_switch14x14 : if number_of_ports = 14 generate + +Switch_Crossbar14_14: Crossbar +GENERIC MAP(number_of_crossbar_ports =>14) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => crossbar_in_port3, + Port4_in => crossbar_in_port4, + Port5_in => crossbar_in_port5, + Port6_in => crossbar_in_port6, + Port7_in => crossbar_in_port7, + Port8_in => crossbar_in_port8, + Port9_in => crossbar_in_port9, + Port10_in => crossbar_in_port10, + Port11_in => crossbar_in_port11, + Port12_in => crossbar_in_port12, + Port13_in => crossbar_in_port13, + Port14_in => crossbar_in_port14, + Port15_in => "00000000", + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in => crossbar_in_pulse3, + Port4_pulse_in => crossbar_in_pulse4, + Port5_pulse_in => crossbar_in_pulse5, + Port6_pulse_in => crossbar_in_pulse6, + Port7_pulse_in => crossbar_in_pulse7, + Port8_pulse_in => crossbar_in_pulse8, + Port9_pulse_in => crossbar_in_pulse9, + Port10_pulse_in => crossbar_in_pulse10, + Port11_pulse_in => crossbar_in_pulse11, + Port12_pulse_in => crossbar_in_pulse12, + Port13_pulse_in => crossbar_in_pulse13, + Port14_pulse_in => crossbar_in_pulse14, + Port15_pulse_in =>'0' , + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port3_pulse_out => crossbar_out_pulse3, + Port4_pulse_out => crossbar_out_pulse4, + Port5_pulse_out => crossbar_out_pulse5, + Port6_pulse_out => crossbar_out_pulse6, + Port7_pulse_out => crossbar_out_pulse7, + Port8_pulse_out => crossbar_out_pulse8, + Port9_pulse_out => crossbar_out_pulse9, + Port10_pulse_out => crossbar_out_pulse10, + Port11_pulse_out => crossbar_out_pulse11, + Port12_pulse_out => crossbar_out_pulse12, + Port13_pulse_out => crossbar_out_pulse13, + Port14_pulse_out => crossbar_out_pulse14, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Port3_out => crossbar_out_port3, + Port4_out => crossbar_out_port4, + Port5_out => crossbar_out_port5, + Port6_out => crossbar_out_port6, + Port7_out => crossbar_out_port7, + Port8_out => crossbar_out_port8, + Port9_out => crossbar_out_port9, + Port10_out => crossbar_out_port10, + Port11_out => crossbar_out_port11, + Port12_out => crossbar_out_port12, + Port13_out => crossbar_out_port13, + Port14_out => crossbar_out_port14, + Ctrl => Grant_signal); +end generate crossbar_switch14x14; + + +-- switch 15 ports +crossbar_switch15x15 : if number_of_ports = 15 generate + +Switch_Crossbar15_15: Crossbar +GENERIC MAP(number_of_crossbar_ports =>15) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => crossbar_in_port3, + Port4_in => crossbar_in_port4, + Port5_in => crossbar_in_port5, + Port6_in => crossbar_in_port6, + Port7_in => crossbar_in_port7, + Port8_in => crossbar_in_port8, + Port9_in => crossbar_in_port9, + Port10_in => crossbar_in_port10, + Port11_in => crossbar_in_port11, + Port12_in => crossbar_in_port12, + Port13_in => crossbar_in_port13, + Port14_in => crossbar_in_port14, + Port15_in => crossbar_in_port15, + Port16_in => "00000000", + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in => crossbar_in_pulse3, + Port4_pulse_in => crossbar_in_pulse4, + Port5_pulse_in => crossbar_in_pulse5, + Port6_pulse_in => crossbar_in_pulse6, + Port7_pulse_in => crossbar_in_pulse7, + Port8_pulse_in => crossbar_in_pulse8, + Port9_pulse_in => crossbar_in_pulse9, + Port10_pulse_in => crossbar_in_pulse10, + Port11_pulse_in => crossbar_in_pulse11, + Port12_pulse_in => crossbar_in_pulse12, + Port13_pulse_in => crossbar_in_pulse13, + Port14_pulse_in => crossbar_in_pulse14, + Port15_pulse_in => crossbar_in_pulse15, + Port16_pulse_in =>'0' , + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port3_pulse_out => crossbar_out_pulse3, + Port4_pulse_out => crossbar_out_pulse4, + Port5_pulse_out => crossbar_out_pulse5, + Port6_pulse_out => crossbar_out_pulse6, + Port7_pulse_out => crossbar_out_pulse7, + Port8_pulse_out => crossbar_out_pulse8, + Port9_pulse_out => crossbar_out_pulse9, + Port10_pulse_out => crossbar_out_pulse10, + Port11_pulse_out => crossbar_out_pulse11, + Port12_pulse_out => crossbar_out_pulse12, + Port13_pulse_out => crossbar_out_pulse13, + Port14_pulse_out => crossbar_out_pulse14, + Port15_pulse_out => crossbar_out_pulse15, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Port3_out => crossbar_out_port3, + Port4_out => crossbar_out_port4, + Port5_out => crossbar_out_port5, + Port6_out => crossbar_out_port6, + Port7_out => crossbar_out_port7, + Port8_out => crossbar_out_port8, + Port9_out => crossbar_out_port9, + Port10_out => crossbar_out_port10, + Port11_out => crossbar_out_port11, + Port12_out => crossbar_out_port12, + Port13_out => crossbar_out_port13, + Port14_out => crossbar_out_port14, + Port15_out => crossbar_out_port15, + Ctrl => Grant_signal); +end generate crossbar_switch15x15; + + +-- switch 16 ports +crossbar_switch16x16 : if number_of_ports = 16 generate + +Switch_Crossbar16_16: Crossbar +GENERIC MAP(number_of_crossbar_ports =>16) + PORT MAP( + Port1_in => crossbar_in_port1, + Port2_in => crossbar_in_port2, + Port3_in => crossbar_in_port3, + Port4_in => crossbar_in_port4, + Port5_in => crossbar_in_port5, + Port6_in => crossbar_in_port6, + Port7_in => crossbar_in_port7, + Port8_in => crossbar_in_port8, + Port9_in => crossbar_in_port9, + Port10_in => crossbar_in_port10, + Port11_in => crossbar_in_port11, + Port12_in => crossbar_in_port12, + Port13_in => crossbar_in_port13, + Port14_in => crossbar_in_port14, + Port15_in => crossbar_in_port15, + Port16_in => crossbar_in_port16, + Port1_pulse_in => crossbar_in_pulse1, + Port2_pulse_in => crossbar_in_pulse2, + Port3_pulse_in => crossbar_in_pulse3, + Port4_pulse_in => crossbar_in_pulse4, + Port5_pulse_in => crossbar_in_pulse5, + Port6_pulse_in => crossbar_in_pulse6, + Port7_pulse_in => crossbar_in_pulse7, + Port8_pulse_in => crossbar_in_pulse8, + Port9_pulse_in => crossbar_in_pulse9, + Port10_pulse_in => crossbar_in_pulse10, + Port11_pulse_in => crossbar_in_pulse11, + Port12_pulse_in => crossbar_in_pulse12, + Port13_pulse_in => crossbar_in_pulse13, + Port14_pulse_in => crossbar_in_pulse14, + Port15_pulse_in => crossbar_in_pulse15, + Port16_pulse_in => crossbar_in_pulse16, + Port1_pulse_out => crossbar_out_pulse1, + Port2_pulse_out => crossbar_out_pulse2, + Port3_pulse_out => crossbar_out_pulse3, + Port4_pulse_out => crossbar_out_pulse4, + Port5_pulse_out => crossbar_out_pulse5, + Port6_pulse_out => crossbar_out_pulse6, + Port7_pulse_out => crossbar_out_pulse7, + Port8_pulse_out => crossbar_out_pulse8, + Port9_pulse_out => crossbar_out_pulse9, + Port10_pulse_out => crossbar_out_pulse10, + Port11_pulse_out => crossbar_out_pulse11, + Port12_pulse_out => crossbar_out_pulse12, + Port13_pulse_out => crossbar_out_pulse13, + Port14_pulse_out => crossbar_out_pulse14, + Port15_pulse_out => crossbar_out_pulse15, + Port16_pulse_out => crossbar_out_pulse16, + Port1_out => crossbar_out_port1, + Port2_out => crossbar_out_port2, + Port3_out => crossbar_out_port3, + Port4_out => crossbar_out_port4, + Port5_out => crossbar_out_port5, + Port6_out => crossbar_out_port6, + Port7_out => crossbar_out_port7, + Port8_out => crossbar_out_port8, + Port9_out => crossbar_out_port9, + Port10_out => crossbar_out_port10, + Port11_out => crossbar_out_port11, + Port12_out => crossbar_out_port12, + Port13_out => crossbar_out_port13, + Port14_out => crossbar_out_port14, + Port15_out => crossbar_out_port15, + Port16_out => crossbar_out_port16, + Ctrl => Grant_signal); +end generate crossbar_switch16x16; +-- intstanciation et connexion du scheduler en fonction du nombre de ports +-- le circuit genere depend du parametre generique nombre de ports +-- switch 2 ports +scheduler_switch2x2 : if number_of_ports = 2 generate + +Scheduler2_2: Scheduler + GENERIC MAP(number_of_ports => 2 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch2x2; + + +-- switch 3 ports +scheduler_switch3x3 : if number_of_ports = 3 generate + +Scheduler3_3: Scheduler + GENERIC MAP(number_of_ports => 3 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch3x3; + + +-- switch 4 ports +scheduler_switch4x4 : if number_of_ports = 4 generate + +Scheduler4_4: Scheduler + GENERIC MAP(number_of_ports => 4 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch4x4; + + +-- switch 5 ports +scheduler_switch5x5 : if number_of_ports = 5 generate + +Scheduler5_5: Scheduler + GENERIC MAP(number_of_ports => 5 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch5x5; + + +-- switch 6 ports +scheduler_switch6x6 : if number_of_ports = 6 generate + +Scheduler6_6: Scheduler + GENERIC MAP(number_of_ports => 6 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch6x6; + + +-- switch 7 ports +scheduler_switch7x7 : if number_of_ports = 7 generate + +Scheduler7_7: Scheduler + GENERIC MAP(number_of_ports => 7 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch7x7; + + +-- switch 8 ports +scheduler_switch8x8 : if number_of_ports = 8 generate + +Scheduler8_8: Scheduler + GENERIC MAP(number_of_ports => 8 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch8x8; + + +-- switch 9 ports +scheduler_switch9x9 : if number_of_ports = 9 generate + +Scheduler9_9: Scheduler + GENERIC MAP(number_of_ports => 9 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch9x9; + + +-- switch 10 ports +scheduler_switch10x10 : if number_of_ports = 10 generate + +Scheduler10_10: Scheduler + GENERIC MAP(number_of_ports => 10 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch10x10; + + +-- switch 11 ports +scheduler_switch11x11 : if number_of_ports = 11 generate + +Scheduler11_11: Scheduler + GENERIC MAP(number_of_ports => 11 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch11x11; + + +-- switch 12 ports +scheduler_switch12x12 : if number_of_ports = 12 generate + +Scheduler12_12: Scheduler + GENERIC MAP(number_of_ports => 12 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch12x12; + + +-- switch 13 ports +scheduler_switch13x13 : if number_of_ports = 13 generate + +Scheduler13_13: Scheduler + GENERIC MAP(number_of_ports => 13 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch13x13; + + +-- switch 14 ports +scheduler_switch14x14 : if number_of_ports = 14 generate + +Scheduler14_14: Scheduler + GENERIC MAP(number_of_ports => 14 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch14x14; + + +-- switch 15 ports +scheduler_switch15x15 : if number_of_ports = 15 generate + +Scheduler15_15: Scheduler + GENERIC MAP(number_of_ports => 15 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch15x15; + + +-- switch 16 ports +scheduler_switch16x16 : if number_of_ports = 16 generate + +Scheduler16_16: Scheduler + GENERIC MAP(number_of_ports => 16 ) + PORT MAP( + Request => Request_signal, + Fifo_full => fifo_out_full_signal, + clk => clk, + priority_rotation =>priority_rotation_signal, + reset => reset, + port_grant => grant_signal + ); + +end generate scheduler_switch16x16; + + + + + + + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Scheduler.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Scheduler.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Scheduler.vhd (revision 138) @@ -0,0 +1,447 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 19:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisé est le DPA (diagonal propagation arbiter) +-- intencie un scheduler particulier en fonction du nombre de port +-- Dependencies: +-- +-- Revision: 1.0 +-- reconstruction du dpa +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Scheduler is + generic(number_of_ports : positive := 4); + Port ( Request : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1); + Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (number_of_ports downto 1); + port_grant : out STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1)); + end Scheduler; + +architecture Behavioral of Scheduler is +-- signaux pour le pipeline; +signal Request_latch :STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1):=(others=>'0'); +signal Fifo_full_latch : STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'0'); +signal priority_rotation_latch : STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'1'); + +-- composants du scheduler +COMPONENT Scheduler2_2 + PORT( + Request : IN std_logic_vector(4 downto 1); + Fifo_full : IN std_logic_vector(2 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(4 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (2 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler3_3 + PORT( + Request : IN std_logic_vector(9 downto 1); + Fifo_full : IN std_logic_vector(3 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(9 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (3 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler4_4 + PORT( + Req : IN std_logic_vector(16 downto 1); + Fifo_full : IN std_logic_vector(4 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(16 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (4 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler5_5 + PORT( + Request : IN std_logic_vector(25 downto 1); + Fifo_full : IN std_logic_vector(5 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(25 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (5 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler6_6 + PORT( + Request : IN std_logic_vector(36 downto 1); + Fifo_full : IN std_logic_vector(6 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(36 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (6 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler7_7 + PORT( + Request : IN std_logic_vector(49 downto 1); + Fifo_full : IN std_logic_vector(7 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(49 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (7 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler8_8 + PORT( + Req : IN std_logic_vector(64 downto 1); + Fifo_full : IN std_logic_vector(8 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(64 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (8 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler9_9 + PORT( + Request : IN std_logic_vector(81 downto 1); + Fifo_full : IN std_logic_vector(9 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(81 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (9 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler10_10 + PORT( + Request : IN std_logic_vector(100 downto 1); + Fifo_full : IN std_logic_vector(10 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(100 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (10 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler11_11 + PORT( + Request : IN std_logic_vector(121 downto 1); + Fifo_full : IN std_logic_vector(11 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(121 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (11 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler12_12 + PORT( + Request : IN std_logic_vector(144 downto 1); + Fifo_full : IN std_logic_vector(12 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(144 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (12 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler13_13 + PORT( + Request : IN std_logic_vector(169 downto 1); + Fifo_full : IN std_logic_vector(13 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(169 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (13 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler14_14 + PORT( + Request : IN std_logic_vector(196 downto 1); + Fifo_full : IN std_logic_vector(14 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(196 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (14 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler15_15 + PORT( + Request : IN std_logic_vector(225 downto 1); + Fifo_full : IN std_logic_vector(15 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(225 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (15 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler16_16 + PORT( + Request : IN std_logic_vector(256 downto 1); + Fifo_full : IN std_logic_vector(16 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(256 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (16 downto 1) + ); + END COMPONENT; + + +-- instanciation des scheduler +--======================scheduler 2 ports======================= + +begin + +-- instanciation des scheduler +--======================scheduler 2 ports======================= + +scheduler2x2 : if number_of_ports = 2 generate + + Inst_Scheduler2_2 : Scheduler2_2 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler2x2; + +--======================scheduler 3 ports======================= + +scheduler3x3 : if number_of_ports = 3 generate + + Inst_Scheduler3_3 : Scheduler3_3 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler3x3; + +--======================scheduler 4 ports======================= + +scheduler4x4 : if number_of_ports = 4 generate + + Inst_Scheduler4_4 : Scheduler4_4 + PORT MAP( + Req => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler4x4; + +--======================scheduler 5 ports======================= + +scheduler5x5 : if number_of_ports = 5 generate + + Inst_Scheduler5_5 : Scheduler5_5 + PORT MAP( + Request => Request, + Fifo_full => Fifo_full, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation, + port_grant =>port_grant); +end generate scheduler5x5; + +--======================scheduler 6 ports======================= + +scheduler6x6 : if number_of_ports = 6 generate + + Inst_Scheduler6_6 : Scheduler6_6 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler6x6; + +--======================scheduler 7 ports======================= + +scheduler7x7 : if number_of_ports = 7 generate + + Inst_Scheduler7_7 : Scheduler7_7 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler7x7; + +--======================scheduler 8 ports======================= + +scheduler8x8 : if number_of_ports = 8 generate + + Inst_Scheduler8_8 : Scheduler8_8 + PORT MAP( + Req => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler8x8; + +--======================scheduler 9 ports======================= + +scheduler9x9 : if number_of_ports = 9 generate + + Inst_Scheduler9_9 : Scheduler9_9 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler9x9; + +--======================scheduler 10 ports======================= + +scheduler10x10 : if number_of_ports = 10 generate + + Inst_Scheduler10_10 : Scheduler10_10 + PORT MAP( + Request => Request, + Fifo_full => Fifo_full, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation, + port_grant =>port_grant); +end generate scheduler10x10; + +--======================scheduler 11 ports======================= + +scheduler11x11 : if number_of_ports = 11 generate + + Inst_Scheduler11_11 : Scheduler11_11 + PORT MAP( + Request => Request, + Fifo_full => Fifo_full, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation, + port_grant =>port_grant); +end generate scheduler11x11; + +--======================scheduler 12 ports======================= + +scheduler12x12 : if number_of_ports = 12 generate + + Inst_Scheduler12_12 : Scheduler12_12 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler12x12; + +--======================scheduler 13 ports======================= + +scheduler13x13 : if number_of_ports = 13 generate + + Inst_Scheduler13_13 : Scheduler13_13 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler13x13; + +--======================scheduler 14 ports======================= + +scheduler14x14 : if number_of_ports = 14 generate + + Inst_Scheduler14_14 : Scheduler14_14 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler14x14; + +--======================scheduler 15 ports======================= + +scheduler15x15 : if number_of_ports = 15 generate + + Inst_Scheduler15_15 : Scheduler15_15 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler15x15; + +--======================scheduler 16 ports======================= + +scheduler16x16 : if number_of_ports = 16 generate + + Inst_Scheduler16_16 : Scheduler16_16 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler16x16; +Sched:process (clk,reset) +begin +if rising_edge(clk) then + if reset='1' then + request_latch<=(others=>'0'); + --Fifo_full_latch<=(others=>'0'); + priority_rotation_latch<=(others=>'1'); + else + request_latch<=request; + -- Fifo_full_latch<=fifo_full; + priority_rotation_latch<=priority_rotation; + end if; +end if; +end process sched; +Fifo_full_latch<=fifo_full; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Scheduler.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Scheduler.vhd.bak (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/Scheduler.vhd.bak (revision 138) @@ -0,0 +1,447 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 19:56:34 05/06/2011 +-- Design Name: +-- Module Name: Sheduler - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Module de l'ordonnanceur du switch crossbar +-- l'algorithme utilisé est le DPA (diagonal propagation arbiter) +-- intencie un scheduler particulier en fonction du nombre de port +-- Dependencies: +-- +-- Revision: 1.0 +-- reconstruction du dpa +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--use Work.Sheduler_package.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Scheduler is + generic(number_of_ports : positive := 4); + Port ( Request : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1); + Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC_VECTOR (number_of_ports downto 1); + port_grant : out STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1)); + end Scheduler; + +architecture Behavioral of Scheduler is +-- signaux pour le pipeline; +signal Request_latch :STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1):=(others=>'0'); +signal Fifo_full_latch : STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'0'); +signal priority_rotation_latch : STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'1'); + +-- composants du scheduler +COMPONENT Scheduler2_2 + PORT( + Request : IN std_logic_vector(4 downto 1); + Fifo_full : IN std_logic_vector(2 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(4 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (2 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler3_3 + PORT( + Request : IN std_logic_vector(9 downto 1); + Fifo_full : IN std_logic_vector(3 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(9 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (3 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler4_4 + PORT( + Request : IN std_logic_vector(16 downto 1); + Fifo_full : IN std_logic_vector(4 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(16 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (4 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler5_5 + PORT( + Request : IN std_logic_vector(25 downto 1); + Fifo_full : IN std_logic_vector(5 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(25 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (5 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler6_6 + PORT( + Request : IN std_logic_vector(36 downto 1); + Fifo_full : IN std_logic_vector(6 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(36 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (6 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler7_7 + PORT( + Request : IN std_logic_vector(49 downto 1); + Fifo_full : IN std_logic_vector(7 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(49 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (7 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler8_8 + PORT( + Req : IN std_logic_vector(64 downto 1); + Fifo_full : IN std_logic_vector(8 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(64 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (8 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler9_9 + PORT( + Request : IN std_logic_vector(81 downto 1); + Fifo_full : IN std_logic_vector(9 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(81 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (9 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler10_10 + PORT( + Request : IN std_logic_vector(100 downto 1); + Fifo_full : IN std_logic_vector(10 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(100 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (10 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler11_11 + PORT( + Request : IN std_logic_vector(121 downto 1); + Fifo_full : IN std_logic_vector(11 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(121 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (11 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler12_12 + PORT( + Request : IN std_logic_vector(144 downto 1); + Fifo_full : IN std_logic_vector(12 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(144 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (12 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler13_13 + PORT( + Request : IN std_logic_vector(169 downto 1); + Fifo_full : IN std_logic_vector(13 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(169 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (13 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler14_14 + PORT( + Request : IN std_logic_vector(196 downto 1); + Fifo_full : IN std_logic_vector(14 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(196 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (14 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler15_15 + PORT( + Request : IN std_logic_vector(225 downto 1); + Fifo_full : IN std_logic_vector(15 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(225 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (15 downto 1) + ); + END COMPONENT; + +COMPONENT Scheduler16_16 + PORT( + Request : IN std_logic_vector(256 downto 1); + Fifo_full : IN std_logic_vector(16 downto 1); + clk : IN std_logic; + reset : IN std_logic; + port_grant : OUT std_logic_vector(256 downto 1); + priority_rotation : in STD_LOGIC_VECTOR (16 downto 1) + ); + END COMPONENT; + + +-- instanciation des scheduler +--======================scheduler 2 ports======================= + +begin + +-- instanciation des scheduler +--======================scheduler 2 ports======================= + +scheduler2x2 : if number_of_ports = 2 generate + + Inst_Scheduler2_2 : Scheduler2_2 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler2x2; + +--======================scheduler 3 ports======================= + +scheduler3x3 : if number_of_ports = 3 generate + + Inst_Scheduler3_3 : Scheduler3_3 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler3x3; + +--======================scheduler 4 ports======================= + +scheduler4x4 : if number_of_ports = 4 generate + + Inst_Scheduler4_4 : Scheduler4_4 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler4x4; + +--======================scheduler 5 ports======================= + +scheduler5x5 : if number_of_ports = 5 generate + + Inst_Scheduler5_5 : Scheduler5_5 + PORT MAP( + Request => Request, + Fifo_full => Fifo_full, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation, + port_grant =>port_grant); +end generate scheduler5x5; + +--======================scheduler 6 ports======================= + +scheduler6x6 : if number_of_ports = 6 generate + + Inst_Scheduler6_6 : Scheduler6_6 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler6x6; + +--======================scheduler 7 ports======================= + +scheduler7x7 : if number_of_ports = 7 generate + + Inst_Scheduler7_7 : Scheduler7_7 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler7x7; + +--======================scheduler 8 ports======================= + +scheduler8x8 : if number_of_ports = 8 generate + + Inst_Scheduler8_8 : Scheduler8_8 + PORT MAP( + Req => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler8x8; + +--======================scheduler 9 ports======================= + +scheduler9x9 : if number_of_ports = 9 generate + + Inst_Scheduler9_9 : Scheduler9_9 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler9x9; + +--======================scheduler 10 ports======================= + +scheduler10x10 : if number_of_ports = 10 generate + + Inst_Scheduler10_10 : Scheduler10_10 + PORT MAP( + Request => Request, + Fifo_full => Fifo_full, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation, + port_grant =>port_grant); +end generate scheduler10x10; + +--======================scheduler 11 ports======================= + +scheduler11x11 : if number_of_ports = 11 generate + + Inst_Scheduler11_11 : Scheduler11_11 + PORT MAP( + Request => Request, + Fifo_full => Fifo_full, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation, + port_grant =>port_grant); +end generate scheduler11x11; + +--======================scheduler 12 ports======================= + +scheduler12x12 : if number_of_ports = 12 generate + + Inst_Scheduler12_12 : Scheduler12_12 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler12x12; + +--======================scheduler 13 ports======================= + +scheduler13x13 : if number_of_ports = 13 generate + + Inst_Scheduler13_13 : Scheduler13_13 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler13x13; + +--======================scheduler 14 ports======================= + +scheduler14x14 : if number_of_ports = 14 generate + + Inst_Scheduler14_14 : Scheduler14_14 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler14x14; + +--======================scheduler 15 ports======================= + +scheduler15x15 : if number_of_ports = 15 generate + + Inst_Scheduler15_15 : Scheduler15_15 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler15x15; + +--======================scheduler 16 ports======================= + +scheduler16x16 : if number_of_ports = 16 generate + + Inst_Scheduler16_16 : Scheduler16_16 + PORT MAP( + Request => Request_latch, + Fifo_full => Fifo_full_latch, + clk => clk , + reset =>reset, + priority_rotation =>priority_rotation_latch, + port_grant =>port_grant); +end generate scheduler16x16; +Sched:process (clk,reset) +begin +if rising_edge(clk) then + if reset='1' then + request_latch<=(others=>'0'); + --Fifo_full_latch<=(others=>'0'); + priority_rotation_latch<=(others=>'1'); + else + request_latch<=request; + -- Fifo_full_latch<=fifo_full; + priority_rotation_latch<=priority_rotation; + end if; +end if; +end process sched; +Fifo_full_latch<=fifo_full; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/conv.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/conv.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/conv.vhd (revision 138) @@ -0,0 +1,72 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package conversions is + + + -- type is + -- record + -- : std_logic_vector( 7 downto 0); + -- : std_logic; + --end record; + +-- Declare constants + + --constant : time := ns; + --constant : integer := ; + +-- Declare functions and procedure + + function to_uint ( a: in std_ulogic_vector) return integer; + function to_vector (size: integer; val: integer) return std_ulogic_vector; + +end conversions; + + +package body conversions is + + -- Convert a std_ulogic_vector to an unsigned integer + -- + function to_uint (a: std_ulogic_vector) return integer is + alias av: std_ulogic_vector (1 to a'length) is a; + variable val: integer := 0; + variable b: integer := 1; + begin + for i in a'length downto 1 loop + if (av(i) = '1') then -- if LSB is '1', + val := val + b; -- add value for current bit position + end if; + b := b * 2; -- Shift left 1 bit + end loop; + + return val; + end to_uint; + +-------------------------------------------------------- + -- Convert an integer to a std_ulogic_vector + -- + function to_vector (size: integer; val: integer) return std_ulogic_vector is + variable vec: std_ulogic_vector (1 to size); + variable a: integer; + begin + a := val; + for i in size downto 1 loop + if ((a mod 2) = 1) then + vec(i) := '1'; + else + vec(i) := '0'; + end if; + a := a / 2; + end loop; + return vec; + end to_vector; + + + +end conversions; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/proto_send.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/proto_send.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/proto_send.vhd (revision 138) @@ -0,0 +1,183 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 18:01:21 10/23/2012 +-- Design Name: +-- Module Name: proto_send - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +use work.CoreTypes.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity proto_send is +generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée + fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie + fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie + fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée + fifo_in_data_out : in std_logic_vector(Word-1 downto 0); + fifo_out_data_in : out std_logic_vector(Word-1 downto 0); + packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet + copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo + snd_start : in std_logic; --début de la réception + snd_ack :in std_logic; -- acquittement de la réception + snd_comp : out std_logic; -- fin de la réception + mem :in memory(0 to sizemem-1)); --données à copier vers le fifo + +end proto_send; + +architecture Behavioral of proto_send is +type typ_send is (s_head,s_len,s_len2,s_data,s_pulse,s_end); + signal etsnd : typ_send; + signal snd_state,next_snd_state:natural range 0 to 7:=0; + signal p_len,p_len_i : natural range 0 to 255; + signal n,n_i:natural range 0 to 7; + signal wr_ok,rd_ok:std_logic:='0'; + signal wr_ok_i,rd_ok_i:std_logic:='0'; + signal sfifo_in,Data_to_send,Data_to_send_i : std_logic_vector(Word-1 downto 0); + signal spush : std_logic:='0'; + signal err : std_logic_vector(Word-1 downto 0):=(others =>'0'); +begin + +Fifo_copy_sync:process(clk,reset) + +begin + + + if reset='1' then + n<=0; + Snd_state<=0; + P_len<=0; + Data_to_send<=(others=>'0'); +else + if rising_edge(clk) then + Snd_state<=Next_Snd_state; + n<=n_i; + p_len<=P_len_i; + Data_to_send<=Data_to_send_i; + wr_ok<=wr_ok_i; + rd_ok<=rd_ok_i; +end if; +end if; +end process fifo_copy_sync; + -- affectation concurentes + Fifo_copy_val:process (Snd_state,Etsnd,copy_mode,data_to_send,rd_ok,wr_ok,spush) +begin + fifo_out_wr_en<='0'; + fifo_in_rd_en<='0'; + fifo_out_data_in<=data_to_send; + if copy_mode='0' then + fifo_out_wr_en<=wr_ok; + fifo_out_data_in<=data_to_send; + fifo_in_rd_en<='0'; +else + if (Snd_state=1) or (snd_state=2) then + fifo_out_wr_en<=wr_ok; + fifo_in_rd_en<=rd_ok; + fifo_out_data_in<=data_to_send; + end if; +end if; +end process fifo_copy_val; + -- process qui envoie des données en provenance d'un Fifo vers un Fifo + FIfo_to_fifo:process(snd_state,copy_mode,snd_start,snd_ack,fifo_in_empty, + fifo_out_full,Fifo_in_data_out,p_len,n,mem,wr_ok,rd_ok,packet_len) + variable onepop:std_logic:='0'; + begin + Next_snd_state<=snd_state; --valeur par defaut + Data_To_Send_i<=Data_to_send; + wr_ok_i<=wr_ok; + rd_ok_i<=rd_ok; + n_i<=n; + p_len_i<=p_len; + snd_comp<='0'; + case snd_state is + + when 0 => if snd_start='1' then + P_len_i<=to_integer(unsigned(packet_len)); + next_snd_state<=1; + n_i<=0; + end if; + wr_ok_i<='0';rd_ok_i<='0';onepop:='0'; + snd_comp<='0'; + when 1=> --placer la première donnée sur le bus + if copy_mode='1' then + if fifo_in_empty='0' then + data_to_send_i <=fifo_in_data_out ; + end if; + else + data_to_send_i<=mem(n); + end if; + next_snd_state<=2; + when 2=> if P_len>0 then + if copy_mode='1' then + if fifo_in_empty='0' and onepop='0' then + data_to_send_i <=fifo_in_data_out ; + rd_Ok_i<='1'; + onepop:='1'; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok_i<='0'; + end if; + else + onepop:='1';rd_ok_i<='0'; --pas besoin de signal de lecture ici + data_to_send_i<=mem(n); + end if; + + if (fifo_out_full = '0') and onepop='1' then + wr_ok_i<='1'; + onepop:='0'; + p_len_i<=p_len-1; + n_i<=n+1; + else + wr_Ok_i<='0'; + end if; + else + rd_ok_i<='0'; + wr_ok_i<='0'; + next_snd_state<=3; + snd_comp<='1'; + end if; + when 3 => --fin de la copie + if snd_ack='1' then + + next_snd_state<=4; + end if; + wr_ok_i<='0';rd_ok_i<='0'; + snd_comp<='1'; + + when 4 =>next_snd_state<=0; + snd_comp<='0'; + +when others => next_snd_state<=0; + snd_comp<='0'; + rd_ok_i<='0'; + wr_ok_i<='0'; + data_to_send_i <=(others=>'U'); + end case; + end process FIfo_to_fifo; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/stimuli1.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/stimuli1.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/stimuli1.vhd (revision 138) @@ -0,0 +1,50 @@ +-- GENERATEUR DE STIMILUS POUR LE TEST DU SWITCH CROSSBAR + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use IEEE.STD_LOGIC_ARITH.ALL; + +entity stimuli45 is +port (clk : in std_logic; + reset : in std_logic; + wr_en : out std_logic; + data : out std_logic_vector(7 downto 0)); +end stimuli45; + +architecture behavioral of stimuli45 is +type rom_type is array (0 to 69) of std_logic_vector (7 downto 0); +signal ROM : rom_type:= ( + X"55", X"28", X"00" ,X"01" ,X"02" ,X"03" , + X"04" ,X"05" ,X"06" ,X"07" ,X"08" ,X"09" , + X"0a" ,X"0b" ,X"0c" ,X"0d" ,X"0e" ,X"0f" , + X"10" ,X"11" ,X"12" ,X"13" ,X"14" ,X"15" , + X"16" ,X"17" ,X"18" ,X"19" ,X"1a" ,X"1b" , + X"1c" ,X"1d" ,X"1e" ,X"1f" ,X"20" ,X"21" , + X"22" ,X"23" ,X"24" ,X"25" ,X"52", X"1e", + X"00" ,X"01" ,X"02" ,X"03" ,X"04" ,X"05" , + X"06" ,X"07" ,X"08" ,X"09" ,X"0a" ,X"0b" , + X"0c" ,X"0d" ,X"0e" ,X"0f" ,X"10" ,X"11" , + X"12" ,X"13" ,X"14" ,X"15" ,X"16" ,X"17" , + X"18" ,X"19" ,X"1a" ,X"1b" ); + +constant max_address : std_logic_vector(6 downto 0) :="1000101"; +signal address_counter : std_logic_vector(6 downto 0) := (others => '0'); +begin + +data <= ROM(conv_integer(address_counter)); +process (clk) + begin + if rising_edge(clk) then + if reset = '1' then + wr_en <='1'; + address_counter <= (others=>'0'); + elsif address_counter < max_address then + wr_en <='1'; + address_counter <= address_counter +1; + else + wr_en <='0'; + end if; + end if; + end process; +end behavioral; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/test_xbar_8x8.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/test_xbar_8x8.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/NOC/test_xbar_8x8.vhd (revision 138) @@ -0,0 +1,716 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM NGOUNOU +-- +-- Create Date: 19:03:05 07/11/2011 +-- Design Name: +-- Module Name: C:/Xilinx/SWITCH_GENERIC_16_16/test_xbar_8x8.vhd +-- Project Name: GENERIC_16_16 +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: SWITCH_GENERIQUE +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +--use IEEE.std_logic_textio.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +USE ieee.numeric_std.ALL; +use work.Coretypes.all; + + +ENTITY test_xbar_8x8 IS +END test_xbar_8x8; + +ARCHITECTURE behavior OF test_xbar_8x8 IS + CONSTANT MAXPORT :natural:=8; + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT SWITCH_GEN + GENERIC (number_of_ports : positive := MAXPORT); + PORT( + clk : IN std_logic; + reset : IN std_logic; + + Port_in : in typ_portIO(1 to MAXPORT) ; + Port_out : out typ_portIO(1 to MAXPORT); + + cmd_in_en : IN std_logic_vector(MAXPORT downto 1); + data_in_en : IN std_logic_vector(MAXPORT downto 1); + data_out_en : IN std_logic_vector(MAXPORT downto 1); + fifo_in_full : OUT std_logic_vector(MAXPORT downto 1); + fifo_in_empty : OUT std_logic_vector(MAXPORT downto 1); + data_available : OUT std_logic_vector(MAXPORT downto 1) + + ); + END COMPONENT; + COMPONENT Stimport5 + port ( + clk : in std_logic; + reset : in std_logic; + clk_en : in std_logic; + wr_en : out std_logic; + data : out std_logic_vector (7 downto 0) + ); + + END COMPONENT; + type naturel is array (natural range <>) of natural range 0 to 511; + type typ_send is (s_head,s_len,s_len2,s_data,s_end); + type typ_receiv is (r_wait,r_head,r_dlen,r_glen,r_start,r_end); + type typ_cmd is (cmdstart,cmdpost,cmdpostidle,cmdread,cmdlen,cmdglen,cmddata,cmdend,cmdtimeout); + + signal etsnd1,etsnd2,etsnd3 : typ_send; + signal etrec:typ_receiv; --pour la machine à état de réception + signal etcmd :typ_cmd; --pour la machine à état de commande + --Inputs + signal PortIn : Typ_portio (1 to MAXPORT); + --Outputs + signal portOut : Typ_portio(1 to maxport); + + signal data_in_en : std_logic_vector(MAXPORT downto 1) := (others => '0'); + signal cmd_in_en : std_logic_vector(MAXPORT downto 1) := (others => '0'); + signal data_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0'); + signal rdata_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0'); + signal rcount : naturel(1 to MAXPORT) ; + + signal cdata_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0'); + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal din1,din2,din3,din4: std_logic_vector(MAXPORT downto 1):= (others => '0'); + --signaux utiliser pour la mise à jour des MAE + signal sdestport,rdestport,rorigport:natural range 0 to 15; + signal csend1,csend2,csend3,csend4:natural; + signal sorigport :natural range 0 to 15:=1; + + + signal fifo_in_full : std_logic_vector(MAXPORT downto 1); + signal fifo_in_empty : std_logic_vector(MAXPORT downto 1); + signal data_available : std_logic_vector(MAXPORT downto 1); + + -- Clock period definitions + constant clk_period : time := 10 ns; + -- autres signaux de simulation + -- ici nous mettons les signaux permettant de gérer le processus de simulation + signal time_out:std_logic_vector(8 downto 1); + signal header : std_logic_vector(7 downto 0); + signal tosend1,tosend2,tosend3,tosend4 : std_logic_vector(7 downto 0); + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: SWITCH_GEN generic map (MAXPORT) PORT MAP ( + Port_In => PortIn, + Port_Out =>PortOut, + + --signaux de contrôle de la lecture des ports + data_in_en => data_in_en, + cmd_in_en =>cmd_in_en, + data_out_en => data_out_en, + fifo_in_full => fifo_in_full, + fifo_in_empty => fifo_in_empty, + data_available => data_available, + clk => clk, + reset => reset + ); +--Utilisation de la ROM pour envoyer des stimulis +--stimport: stimport5 port map (clk,reset,not (fifo_in_full(5)),din3(5),port5_in); +data_in_en<=din1 or din2 or din3 or din4; +data_out_en<=rdata_out_en or cdata_out_en; + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + init_process:process (reset) + + variable i: natural range 0 to 15; + begin + if reset='1' then + for i in 1 to maxport + loop + --Portin(i)<=(others=>'0'); +end loop ; +end if ; +end process init_process; + psend1:process(clk,reset) + --génération des paquets à partir du premier port + variable pactype :natural range 0 to 15; + variable origport,destport : natural range 0 to 15; + variable datalen,i,i_pair : natural range 0 to 255; + + + + begin + if reset='1' then + etsnd1<=s_head; + + else --reset ='0' + origport:=6; + if rising_edge(clk) then -- le process s'exécute sur chaque front + -- montant de l'horloge + case etsnd1 is + when s_head => -- construction et envoie de l'en-tête + pactype:=5;-- fonction put + destport:=6; -- le port de destination + datalen :=4; + header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4)); + tosend1<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4)); + din1(origport)<='1'; -- en fait data_in_en(origport) + i:=1;i_pair:=i /2; + etsnd1<=s_len; -- passer à l'état suivant + --port1_in<=tosend1; + when s_len => + --tosend1<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8))); + tosend1<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4)); + + din1(origport)<='1'; + + --port1_in<=tosend1; --copie directe sur le port + etsnd1<=s_len2; + when s_len2 => + tosend1<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8))); + din1(origport)<='1'; + + --port1_in<=tosend1; --copie directe sur le port + etsnd1<=s_data; + when s_data => + + if (fifo_in_full(origport)='0') then + din1(origport)<='1'; + i_pair:=i_pair *2; + if i=i_pair then -- modulo + tosend1<=(STD_LOGIC_VECTOR(to_unsigned(i,8))); + --port1_in<="00001101"; --origport=1 + else + --tosend1<="00001111"; + tosend1<=(STD_LOGIC_VECTOR(to_unsigned(i,8))); + --port1_in<="00001111"; --origport=1 + end if; + i:=i+1;i_pair:=i / 2; + if i>datalen then + etsnd1<=s_end; + din1(origport)<='0'; + end if; + else + din1(origport)<='1'; + end if; + when s_end => + tosend1<="--------"; + din1(origport)<='0'; + if fifo_in_empty(origport)='1' then + etsnd1<=s_head; + else + etsnd1<=s_end; + end if; + end case; + + end if; + + + + end if; --reset='1' + end process psend1; + + Portin(6)<=tosend1 when reset='0'; + Portin(2)<=tosend2 when reset='0'; + Portin(4)<=tosend3 when reset='0'; + Portin(1)<=tosend4 when reset='0'; + psend2:process(clk,reset) + --génération des paquets à partir du premier port + variable pactype :natural range 0 to 15; + variable origport,destport : natural range 0 to 15; + variable datalen,i,i_pair : natural range 0 to 255; + + + + begin + if reset='1' then + etsnd2<=s_head; + + else --reset ='0' + origport:=2; + if rising_edge(clk) then -- le process s'exécute sur chaque front + -- montant de l'horloge + case etsnd2 is + when s_head => -- construction et envoie de l'en-tête + pactype:=5;-- fonction put + destport:=2; -- le port de destination + datalen :=9; + header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4)); + tosend2<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4)); + din2(origport)<='1'; + i:=1;i_pair:=i /2; + etsnd2<=s_len; -- passer à l'état suivant + + when s_len => + --tosend2<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8))); + tosend2<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4)); + + din2(origport)<='1'; + + --port2_in<=tosend2; --copie directe sur le port + etsnd2<=s_len2; + when s_len2 => + tosend2<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8))); + din2(origport)<='1'; + + --port1_in<=tosend1; --copie directe sur le port + etsnd2<=s_data; + when s_data => + + if (fifo_in_full(origport)='0') then + din2(origport)<='1'; + i_pair:=i_pair * 2; + if i=i_pair then -- modulo + --tosend2<="00000001"; + tosend2<=(STD_LOGIC_VECTOR(to_unsigned(i,8))); + --port2_in<="00000001"; --origport=1 + else + --tosend2<="00000010"; + tosend2<=(STD_LOGIC_VECTOR(to_unsigned(i,8))); + --port2_in<="00000001"; --origport=1 + end if; + i:=i+1;i_pair:=i / 2; + if i>datalen then + etsnd2<=s_end; + din2(origport)<='0'; + else + din2(origport)<='1'; + end if; + else + din2(origport)<='0'; + end if; + when s_end => + tosend2<="--------"; + din2(origport)<='0'; + if fifo_in_empty(origport)='1' then + etsnd2<=s_head; + else + etsnd2<=s_end; + end if; + end case; + + end if; + + + + end if; --reset='1' + end process psend2; + + psend3:process(clk,reset) + --génération des paquets à partir du premier port + variable pactype :natural range 0 to 15; + variable origport,destport : natural range 0 to 15; + variable datalen,i,i_pair : natural range 0 to 255; + + + + begin + if reset='1' then + etsnd3<=s_head; + + else --reset ='0' + origport:=4; --attention à régler tosend3 =Portin(....) !!!!!!! + if rising_edge(clk) then -- le process s'exécute sur chaque front + -- montant de l'horloge + case etsnd3 is + when s_head => -- construction et envoie de l'en-tête + pactype:=5;-- fonction put + destport:=MAXPORT; -- le port de destination + datalen :=4; + --header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4)); + tosend3<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4)); + din3(origport)<='1'; -- en fait data_in_en(origport) + i:=1;i_pair:=i /2; + etsnd3<=s_len; -- passer à l'état suivant + --port1_in<=tosend1; + when s_len => + --tosend3<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8))); + din3(origport)<='1'; + tosend3<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4)); + + --port1_in<=tosend1; --copie directe sur le port + etsnd3<=s_len2; + when s_len2 => + tosend3<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8))); + din3(origport)<='1'; + + --port1_in<=tosend1; --copie directe sur le port + etsnd3<=s_data; + when s_data => + + if (fifo_in_full(origport)='0') then + din3(origport)<='1'; + i_pair:=i_pair * 2; + if i=i_pair then -- modulo + tosend3<=(STD_LOGIC_VECTOR(to_unsigned(i,8))); + --tosend3<="00001100"; + --port1_in<="00001101"; --origport=1 + else + tosend3<=(STD_LOGIC_VECTOR(to_unsigned(i,8))); + --tosend3<="00000110"; + --port1_in<="00001111"; --origport=1 + end if; + i:=i+1;i_pair:=i / 2; + if i>datalen then + din3(origport)<='0'; + etsnd3<=s_end; + else + din3(origport)<='1'; + end if; + else + din3(origport)<='0'; + end if; + when s_end => + tosend3<="--------"; + din3(origport)<='0'; + if fifo_in_empty(origport)='1' then + etsnd3<=s_head; + else + etsnd3<=s_end; + end if; + end case; + + end if; + + end if; --reset='1' + end process psend3; + + preceiv:process(clk,reset) + + variable origport,ptype : natural range 0 to 15; + variable datalen,dcount ,timeout:natural range 0 to 255; + variable destport : natural range 0 to 15:=1; + begin + + if reset='1' then + etrec<=r_wait; + destport:=1; + timeout:=0; + elsif rising_edge(clk) then + case etrec is + when r_wait => + if destport=0 then + destport:=1; + end if; + timeout:=0; + time_out(destport)<='0'; + if data_available(destport)='1' and cmd_in_en(destport)='0' then + rdata_out_en(destport)<='1'; + etrec<=r_head; + else + if destport>=MAXPORT then + destport:=1; + else + destport:=destport+1; + end if; + etrec<=r_wait; + end if; + when r_head => + + ptype:=to_integer(unsigned(portout(destport)(7 downto 4))); + origport:=to_integer(unsigned(portout(destport)(3 downto 0))); + rdata_out_en(destport)<='1'; + if ptype=5 then -- + etrec<=r_Dlen;--identification de la signature d'en tête valide + else + etrec<=r_wait; + end if; + + + + + + when r_Dlen => --positionnement du mot de longueur des données + if data_available(destport)='1' then + + rdata_out_en(destport)<='1'; + etrec<=r_glen; + timeout:=0; + else + timeout:=timeout+1; + if timeout>=30 then + time_out(destport)<='1'; + etrec<=r_end; -- données pas prêtes + end if; + + + end if; + when r_glen => --lecture effective de la longueur des données + if data_available(destport)='1' then + datalen:=to_integer(unsigned(portout(destport)(7 downto 0)))-3; + rdata_out_en(destport)<='1'; + etrec<=r_start; + dcount:=1; -- initialisation du compteur de reception + else + timeout:=timeout+1; + if timeout>=30 then + time_out(destport)<='1'; + etrec<=r_end; -- données pas prêtes + end if; + + end if; + + when r_start => + if data_available(destport)='1' then + + dcount:=dcount+1; + assert true report "Donnée lue :"; --& string(unsigned(port4_out(7 downto 0))) + rdata_out_en(destport)<='1'; + + --severity note; + if datalen<=dcount then + etrec<=r_end; + + elsif dcount=255 then --dépassement de la capacité + etrec<=r_end; + end if; + else + timeout:=timeout+1; + if timeout>=30 then + time_out(destport)<='1'; + etrec<=r_end; -- données pas prêtes + end if; + + + end if; + when r_end => + + + rdata_out_en(destport)<='0'; + rcount(destport)<=rcount(destport)+1; + etrec<=r_wait; + if destport>=MAXPORT then -- provoquer le passage au prochain port de réception + destport:=1; + else + destport:=destport+1; + end if; + end case; + end if; --reset='1' + end process preceiv; + + pcmd:process(clk,reset) + + variable origport,destport,pid,mport : natural range 0 to 15; + variable datalen,dcount ,timeout:natural range 0 to 255; + begin + + if reset='1' then + etcmd<=cmdstart; + destport:=0; + timeout:=0; + origport:=1; + sorigport<=origport; + elsif rising_edge(clk) then + case etcmd is + when cmdstart => + if fifo_in_empty(origport)='1' then + + + + + etcmd<=cmdpost; + end if; + when cmdpost => + if fifo_in_empty(origport)='1' then + ---assignations de l'état + --din4(origport)<='1'; + --tosend4<="00000001"; ---code pour getportid + etcmd<=cmdpostidle; + end if; + when cmdpostidle => --permet juste la prise en compte de la commande + if data_available(origport)='1' then + etcmd<=cmdread; + end if; + when cmdread => + + + timeout:=0; + --time_out(destport)<='0'; + if data_available(origport)='1' then + mport:=to_integer(unsigned(portout(origport)(7 downto 4))); + pid:=to_integer(unsigned(portout(origport)(3 downto 0)))+1; + --cdata_out_en(origport)<='1'; + if pid=origport then --le port a été bien identifié + etcmd<=cmdglen; -- + else + etcmd<=cmdtimeout; + end if; + else +-- if destport>=MAXPORT then +-- destport:=1; +-- else +-- destport:=destport+1; +-- end if; + etcmd<=cmdread; + end if; + + + when cmdlen => --positionnement du mot de longueur des données + if data_available(origport)='1' then + + --cdata_out_en(origport)<='1'; + etcmd<=cmdglen; + timeout:=0; + else + timeout:=timeout+1; + if timeout>=30 then + --time_out(destport)<='1'; + etcmd<=cmdtimeout; -- données pas prêtes + end if; + + + end if; + when cmdglen => --lecture effective de la longueur des données + if data_available(origport)='1' then + datalen:=to_integer(unsigned(portout(origport)(7 downto 0)))-3; + + etcmd<=cmddata; + dcount:=0; -- initialisation du compteur de reception + else + timeout:=timeout+1; + if timeout>=30 then + --time_out(destport)<='1'; + etcmd<=cmdtimeout; -- données pas prêtes + end if; + + end if; + + when cmddata => + if data_available(origport)='1' and timeout<30 then + + --cdata_out_en(origport)<='1'; + mport:=to_integer(unsigned(portout(origport)(7 downto 4))); + --attention les ports sont numérotés à partir de 0 + pid:=to_integer(unsigned(portout(origport)(3 downto 0)))+1; + + --severity note; + if Pid=origport then + etcmd<=cmdend; + + else --dépassement de la capacité + + timeout:=timeout+1; + if timeout>=30 then + etcmd<=cmdtimeout; + end if; + + end if; + else + + if timeout>=30 then + time_out(origport)<='1'; + etcmd<=cmdtimeout; -- données pas prêtes + end if; + timeout:=timeout+1; + + end if; + when cmdend => + + + --cdata_out_en(origport)<='0'; + +-- if origport>=mport then -- provoquer le passage au prochain port de réception +-- origport:=1; +-- else +-- origport:=origport+1; +-- end if; + etcmd<=cmdstart; + --cmd_in_en(origport)<='0'; + when cmdtimeout => + etcmd<=cmdtimeout; + --cmd_in_en(origport)<='0'; + etcmd<=cmdstart; + end case; + sorigport<=origport; + end if; --reset='1' + + end process pcmd; + +majetcmd:process (etcmd) +variable origport : natural:=1;-- =sorigport ; + begin + case etcmd is + when cmdstart => + + cmd_in_en(origport)<='1'; + + when cmdpost => + din4(origport)<='1'; + tosend4<="00000001"; ---code pour getportid + cmd_in_en(origport)<='1'; + cdata_out_en(origport)<='0'; + when cmdpostidle => + din4(origport)<='0'; + cdata_out_en(origport)<=data_available(origport); + cmd_in_en(origport)<='1'; + + when cmdread => + din4(origport)<='0'; + cdata_out_en(origport)<=data_available(origport); + cmd_in_en(origport)<='1'; + + when cmdlen |cmdglen => --positionnement du mot de longueur des données + + din4(origport)<='0'; + cdata_out_en(origport)<=data_available(origport); + cmd_in_en(origport)<='1'; + + when cmddata => + + din4(origport)<='0'; + cdata_out_en(origport)<=data_available(origport); + cmd_in_en(origport)<='1'; + + + when cmdend => + + din4(origport)<='0'; + cdata_out_en(origport)<='0'; + cmd_in_en(origport)<='0'; + + when cmdtimeout => + din4(origport)<='0'; + cdata_out_en(origport)<='0'; + cmd_in_en(origport)<='0'; + + end case; + +end process majetcmd ; + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + reset<='1'; + wait for 1 ns; + reset<='1'; + wait for clk_period*10; + reset<='0'; + wait; + -- insert stimulus here + + + + + end process; + +END; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/PE.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/PE.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/PE.vhd (revision 138) @@ -0,0 +1,299 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM Roland Christian +-- +-- Create Date: 21:20:54 07/16/2012 +-- Design Name: +-- Module Name: PE - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Ce module permet d'encapsuler une tâche matérielle +-- et lui donne la possiblité de communiquer à l'aide des fonctions MPI-2 RMA +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library NocLib ; +library Std; +--use IEEE.STD_LOGIC_ARITH.ALL; +--use IEEE.STD_LOGIC_UNSIGNED.ALL; +Library MPI_HCL; +use NocLib.CoreTypes.all; +use MPI_HCL.Packet_type.all; +use MPI_HCL.MPI_RMA.all; +-- synthesis translate_off +use std.textio.all; +-- synthesis translate_on +use IEEE.NUMERIC_STD.ALL; + + +entity PE is + Generic (DestId : natural:=0 ); + Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : out STD_LOGIC; + Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + CE : in STD_LOGIC; -- Active le PE après sa synthèse + Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_WE : in STD_LOGIC; + Core_RAM_EN : in STD_LOGIC; + --Core_RAM_ENB : in STD_LOGIC; + Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_Hold_req : in STD_LOGIC; + Core_Hold_Ack : out STD_LOGIC); +end PE; + +architecture Behavioral of PE is +COMPONENT RAM_v + generic (width : positive;size :positive); + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector; + addrb : IN std_logic_vector; + dia : IN std_logic_vector; + dob : OUT std_logic_vector + ); + END COMPONENT; +COMPONENT mem8k8 + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + clkb : IN STD_LOGIC; + enb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; +COMPONENT HT_process is + generic (Task_Id : natural); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + en : in std_logic; -- active la tâche + Interf_i : in core_i; --signaux pour l'interface I + Interf_o : out core_o; --signaux pour l'interface IO + mem_i : in typ_dpram_i; -- signaux pour l'accès à la mémoire + mem_o : out typ_dpram_o -- signaux pour l'accès à la mémoire + ); +end COMPONENT HT_process; + +COMPONENT Hold_FSM is + + Port ( Hold_Req : in STD_LOGIC; + Ram_busy : in STD_LOGIC; + Clk : in STD_LOGIC; + Reset : in STD_LOGIC; + Ramsel : out STD_LOGIC; + Hold_Ack : out STD_LOGIC); +end COMPONENT Hold_FSM; +--données du programme PE + --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_we ,ram_ena,ram_enb,ramsel_i: std_logic:='0'; + signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic; + signal pe_instr_en,pe_hold_ack: std_logic:='0'; + signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal sram : typ_dpram; + signal clk_ht : std_logic; + signal MyGroup:mpi_group; + signal MyWin : mpi_win; + signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0); + signal dpid,dpid_i : natural range 0 to 15:=DestId; + signal MyRank :std_logic_vector(3 downto 0); + signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque + signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée + signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO + signal Lib_Init : std_logic; -- l'initialisation est terminée + signal Lib_Enable : std_logic:='0'; + signal Ex1_run,Ex4_run : std_logic:='0'; --indique que ces modules sont en fin d'exécution + signal Hold_Ack : std_logic; + signal en_task : std_logic; + signal ht_reset :std_logic; + --signaux pour la gestion de la MAE + type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinStart, putdata,getdata,WinCompleted,finalize,st_timeout); + type typ_Hld is (Ht_Lock,Core_Lock,Ht_free); +signal dcount : natural range 0 to 255:=0; +signal wea : std_logic_vector (0 downto 0); +signal count,count_i : natural range 0 to 15:=0; + + + signal RunState : typ_mae; + signal Hld_state :typ_hld; + signal Ram_busy :std_logic:='0'; +begin +--Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN) +-- PORT MAP( +-- clka =>clk , +-- clkb => clk , +-- wea => ram_we, +-- ena => ram_ena, +-- enb => ram_enb, +-- addra => ram_addra, +-- addrb =>ram_addrb, +-- dia => ram_din, +-- dob => ram_do +-- ); + wea(0)<=ram_we; + Ram8k8 : mem8k8 + PORT MAP ( + clka => clk, + ena => ram_ena, + wea => wea, + addra => ram_addra(12 downto 0), + dina => ram_din, + clkb => clk, + enb => ram_enb, + addrb => ram_addrb(12 downto 0), + doutb => ram_do + ); + HT_task:HT_process generic map(Task_id =>DestId) + port map ( + clk=>clk, + reset=>ht_reset, + en=>en_task, + Interf_i =>Libr.i, + Interf_o=>Libr.o, + mem_i =>sram.i, + mem_o =>sram.o ); + +--================================================================ + --MUX de la RAM + +Ram_mux: process (clk,ramsel_i,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr, + Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do, + Pe_ram_din,Pe_ram_we ) + begin + case ramsel_i is + + when '1' => + ram_addra <= Core_ram_address_wr ; + ram_addrb <= Core_ram_address_rd ; + ram_ena <= Core_ram_en; + ram_enb <= Core_ram_en; + ram_we<= Core_ram_we; + ram_din <= Core_ram_data_in; + pe_ram_do<=(others=>'U'); + Core_ram_data_out<=ram_do; + + when others => + ram_addra <= pe_ram_addra; + ram_addrb <= pe_ram_addrb; + ram_ena <= pe_ram_ena; + ram_enb <= pe_ram_enb; + ram_we<= pe_ram_we; + ram_din <=pe_ram_din; + Core_ram_data_out<=(others=>'U'); + pe_ram_do<=ram_do; +end case ; +end process ; + + + +Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --********A changer ********** +--=== !!!!! attention la suppression de la ligne ci-dessous empêche ce +-- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!! +--instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8)); + +dpid<=dpid_i; +en_task<= CE or Lib_enable; --l'activation d'une HT peut être directe ou commandée +Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié +Lib_init<=Core_Pushout(4); -- Initialized +Lib_Enable<=Core_Pushout(6);-- HT activée par la Librairie. +Ex1_Run<=Core_Pushout(5); -- fin de l'exécution de Ex1 +Ex4_Run<=Core_pushout(7); -- fin de l'exécution de Ex4 pour Spawn +horloge_ht:process (reset,en_task,clk) +begin +if reset='1' then +clk_ht<='0'; +count<=0; +Ht_reset<='1'; +else +if en_task='1' then + clk_ht<=clk; + if count=10 then --circuit de reset pour la HT + ht_reset<='0'; + else + if rising_edge(clk) then + count<=count+1; + end if; + ht_reset<='1'; + end if; +else + count<=0; + clk_ht<='0'; + Ht_reset<='1'; +end if; +end if; +end process horloge_ht; + +Hold1: Hold_fsm port map ( +clk=>clk , +reset =>reset, +Ram_Busy=>Ram_busy, +Hold_Ack=>Hold_Ack, +Hold_req =>Core_Hold_Req, +RamSel => RamSel_i); +Core_Hold_Ack<=Hold_Ack; + +--================RAM signals ====================== +sram.I.data_out<=PE_ram_do; +pe_Ram_addra<=sram.O.addr_wr; +pe_Ram_addrb<=sram.O.addr_rd ; +PE_Ram_we<=sram.O.we; +PE_Ram_ena<=sram.O.ena; +PE_Ram_enb<=sram.O.enb; +PE_ram_din<=sram.O.data_in; +--==========MPI HCL signals ============================ + +affect:process (clk,en_task,Lib_enable,Core_hold_req,RamSel_i,Core_pushout,Libr.O) +begin + --if (clk'event and clk='1') then +if en_task='1' then +Instruction<=Libr.O.Instruction; + Ram_busy<=Libr.O.membusy; +PE_Instr_EN<=Libr.O.instr_en; +else --si le HT n'est pas activé ces valeurs sont à 0 ! + Instruction<=(others=>'0'); + Ram_busy<='0'; + PE_Instr_EN<='0'; +end if; +Libr.I.Instr_ack<=Core_pushout(0); +Libr.I.InitOk<=Core_pushout(4); +if Lib_enable='1' then +Libr.I.Spawned<='1'; +else + Libr.I.Spawned<='0'; +end if; +Libr.I.Hold_Req<=Core_Hold_req; +--Libr.I.Hold_Ack<=Hold_Ack; +Libr.I.RamSel<=RamSel_i; +--end if; +assert not(Lib_enable='1') +report "Spawn Activé" +severity WARNING ; + +end process affect; +--======================================================================= +--MAE du PE +--======================================================================= + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/Test_Timer.gise =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/Test_Timer.gise (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/Test_Timer.gise (revision 138) @@ -0,0 +1,196 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/Test_Timer.xise =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/Test_Timer.xise (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/Test_Timer.xise (revision 138) @@ -0,0 +1,754 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/_xmsgs/cg.xmsgs =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/_xmsgs/cg.xmsgs (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/_xmsgs/cg.xmsgs (revision 138) @@ -0,0 +1,24 @@ + + + +Generating component instance 'mem8k8' of 'xilinx.com:ip:blk_mem_gen:6.2' from 'C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml'. + + +A core named 'mem8k8' already exists in the project. Output products for this core may be overwritten. + + +Pre-processing HDL files for 'mem8k8'... + + +Finished generation of ASY schematic symbol. + + +Finished FLIST file generation. + + + + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/_xmsgs/pn_parser.xmsgs =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/_xmsgs/pn_parser.xmsgs (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/_xmsgs/pn_parser.xmsgs (revision 138) @@ -0,0 +1,15 @@ + + + + + + + + + + +Parsing VHDL file "D:/MPI_HCL/Test_Timer/ipcore_dir/mem8k8.vhd" into library work + + + + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.ucf =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.ucf (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.ucf (revision 138) @@ -0,0 +1,61 @@ +################################################################################ +# +# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Tx Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +NET "CLKA" TNM_NET = "CLKA"; + +NET "CLKB" TNM_NET = "CLKB"; + +TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ; + +TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ; + +################################################################################ Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.vhd (revision 138) @@ -0,0 +1,178 @@ +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v6.2 Core - Top-level core wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_wrapper.vhd +-- +-- Description: +-- This is the actual BMG core wrapper. +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY blk_mem_gen_v6_2_top IS + PORT ( + --Inputs - Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + CLKA : IN STD_LOGIC; + + + --Inputs - Port B + ENB : IN STD_LOGIC; --opt port + ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + CLKB : IN STD_LOGIC + + ); + +END blk_mem_gen_v6_2_top; + + +ARCHITECTURE xilinx OF blk_mem_gen_v6_2_top IS + + COMPONENT BUFG IS + PORT ( + I : IN STD_ULOGIC; + O : OUT STD_ULOGIC + ); + END COMPONENT; + + COMPONENT blk_mem_gen_v6_2 IS + PORT ( + --Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + + CLKA : IN STD_LOGIC; + + + --Port B + ENB : IN STD_LOGIC; --opt port + ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + CLKB : IN STD_LOGIC + + + ); + END COMPONENT; + + SIGNAL CLKA_buf : STD_LOGIC; + SIGNAL CLKB_buf : STD_LOGIC; + SIGNAL S_ACLK_buf : STD_LOGIC; + +BEGIN + + bufg_A : BUFG + PORT MAP ( + I => CLKA, + O => CLKA_buf + ); + + bufg_B : BUFG + PORT MAP ( + I => CLKB, + O => CLKB_buf + ); + + + bmg0 : blk_mem_gen_v6_2 + PORT MAP ( + --Port A + ENA => ENA, + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + CLKA => CLKA_buf, + + + --Port B + ENB => ENB, + ADDRB => ADDRB, + DOUTB => DOUTB, + CLKB => CLKB_buf + + ); + +END xilinx; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.xdc =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.xdc (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/blk_mem_gen_v6_2_top.xdc (revision 138) @@ -0,0 +1,56 @@ +################################################################################ +# +# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ] + +create_clock -name "TS_CLKB" -period 20.0 [ get_ports CLKB ] +################################################################################ Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/bmg_wrapper.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/bmg_wrapper.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/example_design/bmg_wrapper.vhd (revision 138) @@ -0,0 +1,269 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v6.2 Core - Top-level wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_wrapper.vhd +-- +-- Description: +-- This is the top-level BMG wrapper (over BMG core). +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-- Configured Core Parameter Values: +-- (Refer to the SIM Parameters table in the datasheet for more information on +-- the these parameters.) +-- C_FAMILY : spartan6 +-- C_XDEVICEFAMILY : spartan6 +-- C_INTERFACE_TYPE : 0 +-- C_AXI_TYPE : 1 +-- C_AXI_SLAVE_TYPE : 0 +-- C_AXI_ID_WIDTH : 4 +-- C_MEM_TYPE : 1 +-- C_BYTE_SIZE : 8 +-- C_ALGORITHM : 1 +-- C_PRIM_TYPE : 1 +-- C_LOAD_INIT_FILE : 0 +-- C_INIT_FILE_NAME : no_coe_file_loaded +-- C_USE_DEFAULT_DATA : 0 +-- C_DEFAULT_DATA : 0 +-- C_RST_TYPE : SYNC +-- C_HAS_RSTA : 0 +-- C_RST_PRIORITY_A : CE +-- C_RSTRAM_A : 0 +-- C_INITA_VAL : 0 +-- C_HAS_ENA : 1 +-- C_HAS_REGCEA : 0 +-- C_USE_BYTE_WEA : 1 +-- C_WEA_WIDTH : 1 +-- C_WRITE_MODE_A : WRITE_FIRST +-- C_WRITE_WIDTH_A : 8 +-- C_READ_WIDTH_A : 8 +-- C_WRITE_DEPTH_A : 8192 +-- C_READ_DEPTH_A : 8192 +-- C_ADDRA_WIDTH : 13 +-- C_HAS_RSTB : 0 +-- C_RST_PRIORITY_B : CE +-- C_RSTRAM_B : 0 +-- C_INITB_VAL : 0 +-- C_HAS_ENB : 1 +-- C_HAS_REGCEB : 0 +-- C_USE_BYTE_WEB : 1 +-- C_WEB_WIDTH : 1 +-- C_WRITE_MODE_B : WRITE_FIRST +-- C_WRITE_WIDTH_B : 8 +-- C_READ_WIDTH_B : 8 +-- C_WRITE_DEPTH_B : 8192 +-- C_READ_DEPTH_B : 8192 +-- C_ADDRB_WIDTH : 13 +-- C_HAS_MEM_OUTPUT_REGS_A : 0 +-- C_HAS_MEM_OUTPUT_REGS_B : 0 +-- C_HAS_MUX_OUTPUT_REGS_A : 0 +-- C_HAS_MUX_OUTPUT_REGS_B : 0 +-- C_HAS_SOFTECC_INPUT_REGS_A : 0 +-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0 +-- C_MUX_PIPELINE_STAGES : 0 +-- C_USE_ECC : 0 +-- C_USE_SOFTECC : 0 +-- C_HAS_INJECTERR : 0 +-- C_SIM_COLLISION_CHECK : ALL +-- C_COMMON_CLK : 0 +-- C_DISABLE_WARN_BHV_COLL : 0 +-- C_DISABLE_WARN_BHV_RANGE : 0 + +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY bmg_wrapper IS + PORT ( + --Port A + CLKA : IN STD_LOGIC; + RSTA : IN STD_LOGIC; --opt port + ENA : IN STD_LOGIC; --optional port + REGCEA : IN STD_LOGIC; --optional port + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + + --Port B + CLKB : IN STD_LOGIC; + RSTB : IN STD_LOGIC; --opt port + ENB : IN STD_LOGIC; --optional port + REGCEB : IN STD_LOGIC; --optional port + WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + + --ECC + INJECTSBITERR : IN STD_LOGIC; --optional port + INJECTDBITERR : IN STD_LOGIC; --optional port + SBITERR : OUT STD_LOGIC; --optional port + DBITERR : OUT STD_LOGIC; --optional port + RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port + -- AXI BMG Input and Output Port Declarations + + -- AXI Global Signals + S_ACLK : IN STD_LOGIC; + S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_AWVALID : IN STD_LOGIC; + S_AXI_AWREADY : OUT STD_LOGIC; + S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + S_AXI_WLAST : IN STD_LOGIC; + S_AXI_WVALID : IN STD_LOGIC; + S_AXI_WREADY : OUT STD_LOGIC; + S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_BVALID : OUT STD_LOGIC; + S_AXI_BREADY : IN STD_LOGIC; + + -- AXI Full/Lite Slave Read (Write side) + S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_ARVALID : IN STD_LOGIC; + S_AXI_ARREADY : OUT STD_LOGIC; + S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_RLAST : OUT STD_LOGIC; + S_AXI_RVALID : OUT STD_LOGIC; + S_AXI_RREADY : IN STD_LOGIC; + + -- AXI Full/Lite Sideband Signals + S_AXI_INJECTSBITERR : IN STD_LOGIC; + S_AXI_INJECTDBITERR : IN STD_LOGIC; + S_AXI_SBITERR : OUT STD_LOGIC; + S_AXI_DBITERR : OUT STD_LOGIC; + S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); + S_ARESETN : IN STD_LOGIC + + + ); + +END bmg_wrapper; + + +ARCHITECTURE xilinx OF bmg_wrapper IS + + COMPONENT blk_mem_gen_v6_2_top IS + PORT ( + --Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + + CLKA : IN STD_LOGIC; + + + --Port B + ENB : IN STD_LOGIC; --opt port + ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + CLKB : IN STD_LOGIC + + + ); + END COMPONENT; + +BEGIN + + bmg0 : blk_mem_gen_v6_2_top + PORT MAP ( + --Port A + ENA => ENA, + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + CLKA => CLKA, + + --Port B + ENB => ENB, + ADDRB => ADDRB, + DOUTB => DOUTB, + CLKB => CLKB + + + ); +END xilinx; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/implement.bat =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/implement.bat (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/implement.bat (revision 138) @@ -0,0 +1,41 @@ + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy blk_mem_gen_v6_2_top.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\blk_mem_gen_v6_2.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\blk_mem_gen_v6_2_top.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc6slx45-csg324-3 blk_mem_gen_v6_2_top + +echo 'Running map' +map blk_mem_gen_v6_2_top -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level VHDL model' +netgen -ofmt vhdl -sim -tm blk_mem_gen_v6_2_top -pcf mapped.pcf -w routed.ncd routed.vhd Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/implement.sh =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/implement.sh (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/implement.sh (revision 138) @@ -0,0 +1,40 @@ +#!/bin/sh + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files +echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp blk_mem_gen_v6_2_top.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../blk_mem_gen_v6_2.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/blk_mem_gen_v6_2_top.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc6slx45-csg324-3 blk_mem_gen_v6_2_top + +echo 'Running map' +map blk_mem_gen_v6_2_top -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level VHDL model' +netgen -ofmt vhdl -sim -tm blk_mem_gen_v6_2_top -pcf mapped.pcf -w routed.ncd routed.vhd Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.bat =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.bat (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.bat (revision 138) @@ -0,0 +1,55 @@ +#!/bin/sh +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\tmp\blk_mem_gen_v6_2.edf . +planAhead -mode batch -source ..\planAhead_rdn.tcl Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.sh =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.sh (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.sh (revision 138) @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../tmp/blk_mem_gen_v6_2.edf . +planAhead -mode batch -source ../planAhead_rdn.tcl Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.tcl =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.tcl (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.tcl (revision 138) @@ -0,0 +1,68 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc6slx45csg324-3 +set projName blk_mem_gen_v6_2 +set design blk_mem_gen_v6_2 +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module blk_mem_gen_v6_2_top +add_files -norecurse {../../example_design/blk_mem_gen_v6_2_top.vhd} +add_files -norecurse {./blk_mem_gen_v6_2.edf} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/blk_mem_gen_v6_2_top.xdc} +set_property top blk_mem_gen_v6_2_top [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +set_param sta.dlyMediator true +write_sdf -rename_top_module blk_mem_gen_v6_2_top -file routed.sdf +write_verilog -nolib -mode sim -sdf_anno false -rename_top_module blk_mem_gen_v6_2_top routed.vhd +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file routed.drc +#write_bitstream Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/xst.prj =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/xst.prj (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/xst.prj (revision 138) @@ -0,0 +1,1 @@ +work ../example_design/blk_mem_gen_v6_2_top.vhd Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/xst.scr =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/xst.scr (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/xst.scr (revision 138) @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent blk_mem_gen_v6_2_top +-p xc6slx45-csg324-3 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn blk_mem_gen_v6_2_top +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8.vhd (revision 138) @@ -0,0 +1,152 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2014 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file mem8k8.vhd when simulating +-- the core, mem8k8. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY mem8k8 IS + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + clkb : IN STD_LOGIC; + enb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END mem8k8; + +ARCHITECTURE mem8k8_a OF mem8k8 IS +-- synthesis translate_off +COMPONENT wrapped_mem8k8 + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + clkb : IN STD_LOGIC; + enb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_mem8k8 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral) + GENERIC MAP ( + c_addra_width => 13, + c_addrb_width => 13, + c_algorithm => 1, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 9, + c_common_clk => 0, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_family => "artix7", + c_has_axi_id => 0, + c_has_ena => 1, + c_has_enb => 1, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 0, + c_has_rstb => 0, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file_name => "no_coe_file_loaded", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 0, + c_mem_type => 1, + c_mux_pipeline_stages => 0, + c_prim_type => 1, + c_read_depth_a => 8191, + c_read_depth_b => 8191, + c_read_width_a => 8, + c_read_width_b => 8, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_byte_wea => 0, + c_use_byte_web => 0, + c_use_default_data => 0, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 8191, + c_write_depth_b => 8191, + c_write_mode_a => "WRITE_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 8, + c_write_width_b => 8, + c_xdevicefamily => "artix7" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_mem8k8 + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + clkb => clkb, + enb => enb, + addrb => addrb, + doutb => doutb + ); +-- synthesis translate_on + +END mem8k8_a; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8.xco =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8.xco (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8.xco (revision 138) @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.3 +# Date: Wed Apr 09 13:43:42 2014 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc7a100t +SET devicefamily = artix7 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=mem8k8 +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Use_ENA_Pin +CSET enable_b=Use_ENB_Pin +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=8191 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-03-11T08:24:14.000Z +# END Extra information +GENERATE +# CRC: 7a5cdcc Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8.xise =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8.xise (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8.xise (revision 138) @@ -0,0 +1,72 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/example_design/bmg_wrapper.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/example_design/bmg_wrapper.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/example_design/bmg_wrapper.vhd (revision 138) @@ -0,0 +1,269 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v6.2 Core - Top-level wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_wrapper.vhd +-- +-- Description: +-- This is the top-level BMG wrapper (over BMG core). +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-- Configured Core Parameter Values: +-- (Refer to the SIM Parameters table in the datasheet for more information on +-- the these parameters.) +-- C_FAMILY : artix7 +-- C_XDEVICEFAMILY : artix7 +-- C_INTERFACE_TYPE : 0 +-- C_AXI_TYPE : 1 +-- C_AXI_SLAVE_TYPE : 0 +-- C_AXI_ID_WIDTH : 4 +-- C_MEM_TYPE : 1 +-- C_BYTE_SIZE : 9 +-- C_ALGORITHM : 1 +-- C_PRIM_TYPE : 1 +-- C_LOAD_INIT_FILE : 0 +-- C_INIT_FILE_NAME : no_coe_file_loaded +-- C_USE_DEFAULT_DATA : 0 +-- C_DEFAULT_DATA : 0 +-- C_RST_TYPE : SYNC +-- C_HAS_RSTA : 0 +-- C_RST_PRIORITY_A : CE +-- C_RSTRAM_A : 0 +-- C_INITA_VAL : 0 +-- C_HAS_ENA : 1 +-- C_HAS_REGCEA : 0 +-- C_USE_BYTE_WEA : 0 +-- C_WEA_WIDTH : 1 +-- C_WRITE_MODE_A : WRITE_FIRST +-- C_WRITE_WIDTH_A : 8 +-- C_READ_WIDTH_A : 8 +-- C_WRITE_DEPTH_A : 8191 +-- C_READ_DEPTH_A : 8191 +-- C_ADDRA_WIDTH : 13 +-- C_HAS_RSTB : 0 +-- C_RST_PRIORITY_B : CE +-- C_RSTRAM_B : 0 +-- C_INITB_VAL : 0 +-- C_HAS_ENB : 1 +-- C_HAS_REGCEB : 0 +-- C_USE_BYTE_WEB : 0 +-- C_WEB_WIDTH : 1 +-- C_WRITE_MODE_B : WRITE_FIRST +-- C_WRITE_WIDTH_B : 8 +-- C_READ_WIDTH_B : 8 +-- C_WRITE_DEPTH_B : 8191 +-- C_READ_DEPTH_B : 8191 +-- C_ADDRB_WIDTH : 13 +-- C_HAS_MEM_OUTPUT_REGS_A : 0 +-- C_HAS_MEM_OUTPUT_REGS_B : 0 +-- C_HAS_MUX_OUTPUT_REGS_A : 0 +-- C_HAS_MUX_OUTPUT_REGS_B : 0 +-- C_HAS_SOFTECC_INPUT_REGS_A : 0 +-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0 +-- C_MUX_PIPELINE_STAGES : 0 +-- C_USE_ECC : 0 +-- C_USE_SOFTECC : 0 +-- C_HAS_INJECTERR : 0 +-- C_SIM_COLLISION_CHECK : ALL +-- C_COMMON_CLK : 0 +-- C_DISABLE_WARN_BHV_COLL : 0 +-- C_DISABLE_WARN_BHV_RANGE : 0 + +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY bmg_wrapper IS + PORT ( + --Port A + CLKA : IN STD_LOGIC; + RSTA : IN STD_LOGIC; --opt port + ENA : IN STD_LOGIC; --optional port + REGCEA : IN STD_LOGIC; --optional port + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + + --Port B + CLKB : IN STD_LOGIC; + RSTB : IN STD_LOGIC; --opt port + ENB : IN STD_LOGIC; --optional port + REGCEB : IN STD_LOGIC; --optional port + WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + + --ECC + INJECTSBITERR : IN STD_LOGIC; --optional port + INJECTDBITERR : IN STD_LOGIC; --optional port + SBITERR : OUT STD_LOGIC; --optional port + DBITERR : OUT STD_LOGIC; --optional port + RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port + -- AXI BMG Input and Output Port Declarations + + -- AXI Global Signals + S_ACLK : IN STD_LOGIC; + S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_AWVALID : IN STD_LOGIC; + S_AXI_AWREADY : OUT STD_LOGIC; + S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + S_AXI_WLAST : IN STD_LOGIC; + S_AXI_WVALID : IN STD_LOGIC; + S_AXI_WREADY : OUT STD_LOGIC; + S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_BVALID : OUT STD_LOGIC; + S_AXI_BREADY : IN STD_LOGIC; + + -- AXI Full/Lite Slave Read (Write side) + S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_ARVALID : IN STD_LOGIC; + S_AXI_ARREADY : OUT STD_LOGIC; + S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_RLAST : OUT STD_LOGIC; + S_AXI_RVALID : OUT STD_LOGIC; + S_AXI_RREADY : IN STD_LOGIC; + + -- AXI Full/Lite Sideband Signals + S_AXI_INJECTSBITERR : IN STD_LOGIC; + S_AXI_INJECTDBITERR : IN STD_LOGIC; + S_AXI_SBITERR : OUT STD_LOGIC; + S_AXI_DBITERR : OUT STD_LOGIC; + S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); + S_ARESETN : IN STD_LOGIC + + + ); + +END bmg_wrapper; + + +ARCHITECTURE xilinx OF bmg_wrapper IS + + COMPONENT mem8k8_top IS + PORT ( + --Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + + CLKA : IN STD_LOGIC; + + + --Port B + ENB : IN STD_LOGIC; --opt port + ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + CLKB : IN STD_LOGIC + + + ); + END COMPONENT; + +BEGIN + + bmg0 : mem8k8_top + PORT MAP ( + --Port A + ENA => ENA, + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + CLKA => CLKA, + + --Port B + ENB => ENB, + ADDRB => ADDRB, + DOUTB => DOUTB, + CLKB => CLKB + + + ); +END xilinx; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.ucf =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.ucf (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.ucf (revision 138) @@ -0,0 +1,61 @@ +################################################################################ +# +# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Tx Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +NET "CLKA" TNM_NET = "CLKA"; + +NET "CLKB" TNM_NET = "CLKB"; + +TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ; + +TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ; + +################################################################################ Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.vhd (revision 138) @@ -0,0 +1,178 @@ +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v6.2 Core - Top-level core wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_wrapper.vhd +-- +-- Description: +-- This is the actual BMG core wrapper. +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY mem8k8_top IS + PORT ( + --Inputs - Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + CLKA : IN STD_LOGIC; + + + --Inputs - Port B + ENB : IN STD_LOGIC; --opt port + ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + CLKB : IN STD_LOGIC + + ); + +END mem8k8_top; + + +ARCHITECTURE xilinx OF mem8k8_top IS + + COMPONENT BUFG IS + PORT ( + I : IN STD_ULOGIC; + O : OUT STD_ULOGIC + ); + END COMPONENT; + + COMPONENT mem8k8 IS + PORT ( + --Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + + CLKA : IN STD_LOGIC; + + + --Port B + ENB : IN STD_LOGIC; --opt port + ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + CLKB : IN STD_LOGIC + + + ); + END COMPONENT; + + SIGNAL CLKA_buf : STD_LOGIC; + SIGNAL CLKB_buf : STD_LOGIC; + SIGNAL S_ACLK_buf : STD_LOGIC; + +BEGIN + + bufg_A : BUFG + PORT MAP ( + I => CLKA, + O => CLKA_buf + ); + + bufg_B : BUFG + PORT MAP ( + I => CLKB, + O => CLKB_buf + ); + + + bmg0 : mem8k8 + PORT MAP ( + --Port A + ENA => ENA, + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + CLKA => CLKA_buf, + + + --Port B + ENB => ENB, + ADDRB => ADDRB, + DOUTB => DOUTB, + CLKB => CLKB_buf + + ); + +END xilinx; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.xdc =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.xdc (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/example_design/mem8k8_top.xdc (revision 138) @@ -0,0 +1,56 @@ +################################################################################ +# +# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ] + +create_clock -name "TS_CLKB" -period 20.0 [ get_ports CLKB ] +################################################################################ Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/implement.bat =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/implement.bat (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/implement.bat (revision 138) @@ -0,0 +1,41 @@ + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy mem8k8_top.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\mem8k8.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\mem8k8_top.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc7a100t-csg324-3 mem8k8_top + +echo 'Running map' +map mem8k8_top -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level VHDL model' +netgen -ofmt vhdl -sim -tm mem8k8_top -pcf mapped.pcf -w routed.ncd routed.vhd Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/implement.sh =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/implement.sh (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/implement.sh (revision 138) @@ -0,0 +1,40 @@ +#!/bin/sh + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files +echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp mem8k8_top.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../mem8k8.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/mem8k8_top.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc7a100t-csg324-3 mem8k8_top + +echo 'Running map' +map mem8k8_top -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level VHDL model' +netgen -ofmt vhdl -sim -tm mem8k8_top -pcf mapped.pcf -w routed.ncd routed.vhd Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.bat =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.bat (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.bat (revision 138) @@ -0,0 +1,55 @@ +#!/bin/sh +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\tmp\mem8k8.edf . +planAhead -mode batch -source ..\planAhead_rdn.tcl Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.sh =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.sh (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.sh (revision 138) @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../tmp/mem8k8.edf . +planAhead -mode batch -source ../planAhead_rdn.tcl Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.tcl =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.tcl (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/planAhead_rdn.tcl (revision 138) @@ -0,0 +1,68 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc7a100tcsg324-3 +set projName mem8k8 +set design mem8k8 +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module mem8k8_top +add_files -norecurse {../../example_design/mem8k8_top.vhd} +add_files -norecurse {./mem8k8.edf} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/mem8k8_top.xdc} +set_property top mem8k8_top [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +set_param sta.dlyMediator true +write_sdf -rename_top_module mem8k8_top -file routed.sdf +write_verilog -nolib -mode sim -sdf_anno false -rename_top_module mem8k8_top routed.vhd +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file routed.drc +#write_bitstream Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/xst.prj =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/xst.prj (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/xst.prj (revision 138) @@ -0,0 +1,1 @@ +work ../example_design/mem8k8_top.vhd Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/xst.scr =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/xst.scr (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem8k8_ste/implement/xst.scr (revision 138) @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent mem8k8_top +-p xc7a100t-csg324-3 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn mem8k8_top +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8.vhd (revision 138) @@ -0,0 +1,152 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2014 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file mem_4k8.vhd when simulating +-- the core, mem_4k8. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY mem_4k8 IS + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + clkb : IN STD_LOGIC; + enb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END mem_4k8; + +ARCHITECTURE mem_4k8_a OF mem_4k8 IS +-- synthesis translate_off +COMPONENT wrapped_mem_4k8 + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + clkb : IN STD_LOGIC; + enb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_mem_4k8 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral) + GENERIC MAP ( + c_addra_width => 12, + c_addrb_width => 12, + c_algorithm => 1, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 8, + c_common_clk => 0, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_family => "spartan6", + c_has_axi_id => 0, + c_has_ena => 1, + c_has_enb => 1, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 0, + c_has_rstb => 0, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file_name => "no_coe_file_loaded", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 0, + c_mem_type => 1, + c_mux_pipeline_stages => 0, + c_prim_type => 1, + c_read_depth_a => 4096, + c_read_depth_b => 4096, + c_read_width_a => 8, + c_read_width_b => 8, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_byte_wea => 1, + c_use_byte_web => 1, + c_use_default_data => 0, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 4096, + c_write_depth_b => 4096, + c_write_mode_a => "WRITE_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 8, + c_write_width_b => 8, + c_xdevicefamily => "spartan6" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_mem_4k8 + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + clkb => clkb, + enb => enb, + addrb => addrb, + doutb => doutb + ); +-- synthesis translate_on + +END mem_4k8_a; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8.xco =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8.xco (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8.xco (revision 138) @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.3 +# Date: Mon Mar 03 07:15:50 2014 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=8 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=mem_4k8 +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Use_ENA_Pin +CSET enable_b=Use_ENB_Pin +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=true +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=4096 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-03-11T08:24:14.000Z +# END Extra information +GENERATE +# CRC: 7d184c03 Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8.xise =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8.xise (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8.xise (revision 138) @@ -0,0 +1,72 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/bmg_wrapper.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/bmg_wrapper.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/bmg_wrapper.vhd (revision 138) @@ -0,0 +1,269 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v6.2 Core - Top-level wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_wrapper.vhd +-- +-- Description: +-- This is the top-level BMG wrapper (over BMG core). +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-- Configured Core Parameter Values: +-- (Refer to the SIM Parameters table in the datasheet for more information on +-- the these parameters.) +-- C_FAMILY : spartan6 +-- C_XDEVICEFAMILY : spartan6 +-- C_INTERFACE_TYPE : 0 +-- C_AXI_TYPE : 1 +-- C_AXI_SLAVE_TYPE : 0 +-- C_AXI_ID_WIDTH : 4 +-- C_MEM_TYPE : 1 +-- C_BYTE_SIZE : 8 +-- C_ALGORITHM : 1 +-- C_PRIM_TYPE : 1 +-- C_LOAD_INIT_FILE : 0 +-- C_INIT_FILE_NAME : no_coe_file_loaded +-- C_USE_DEFAULT_DATA : 0 +-- C_DEFAULT_DATA : 0 +-- C_RST_TYPE : SYNC +-- C_HAS_RSTA : 0 +-- C_RST_PRIORITY_A : CE +-- C_RSTRAM_A : 0 +-- C_INITA_VAL : 0 +-- C_HAS_ENA : 1 +-- C_HAS_REGCEA : 0 +-- C_USE_BYTE_WEA : 1 +-- C_WEA_WIDTH : 1 +-- C_WRITE_MODE_A : WRITE_FIRST +-- C_WRITE_WIDTH_A : 8 +-- C_READ_WIDTH_A : 8 +-- C_WRITE_DEPTH_A : 4096 +-- C_READ_DEPTH_A : 4096 +-- C_ADDRA_WIDTH : 12 +-- C_HAS_RSTB : 0 +-- C_RST_PRIORITY_B : CE +-- C_RSTRAM_B : 0 +-- C_INITB_VAL : 0 +-- C_HAS_ENB : 1 +-- C_HAS_REGCEB : 0 +-- C_USE_BYTE_WEB : 1 +-- C_WEB_WIDTH : 1 +-- C_WRITE_MODE_B : WRITE_FIRST +-- C_WRITE_WIDTH_B : 8 +-- C_READ_WIDTH_B : 8 +-- C_WRITE_DEPTH_B : 4096 +-- C_READ_DEPTH_B : 4096 +-- C_ADDRB_WIDTH : 12 +-- C_HAS_MEM_OUTPUT_REGS_A : 0 +-- C_HAS_MEM_OUTPUT_REGS_B : 0 +-- C_HAS_MUX_OUTPUT_REGS_A : 0 +-- C_HAS_MUX_OUTPUT_REGS_B : 0 +-- C_HAS_SOFTECC_INPUT_REGS_A : 0 +-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0 +-- C_MUX_PIPELINE_STAGES : 0 +-- C_USE_ECC : 0 +-- C_USE_SOFTECC : 0 +-- C_HAS_INJECTERR : 0 +-- C_SIM_COLLISION_CHECK : ALL +-- C_COMMON_CLK : 0 +-- C_DISABLE_WARN_BHV_COLL : 0 +-- C_DISABLE_WARN_BHV_RANGE : 0 + +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY bmg_wrapper IS + PORT ( + --Port A + CLKA : IN STD_LOGIC; + RSTA : IN STD_LOGIC; --opt port + ENA : IN STD_LOGIC; --optional port + REGCEA : IN STD_LOGIC; --optional port + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + + --Port B + CLKB : IN STD_LOGIC; + RSTB : IN STD_LOGIC; --opt port + ENB : IN STD_LOGIC; --optional port + REGCEB : IN STD_LOGIC; --optional port + WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + + --ECC + INJECTSBITERR : IN STD_LOGIC; --optional port + INJECTDBITERR : IN STD_LOGIC; --optional port + SBITERR : OUT STD_LOGIC; --optional port + DBITERR : OUT STD_LOGIC; --optional port + RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --optional port + -- AXI BMG Input and Output Port Declarations + + -- AXI Global Signals + S_ACLK : IN STD_LOGIC; + S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_AWVALID : IN STD_LOGIC; + S_AXI_AWREADY : OUT STD_LOGIC; + S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + S_AXI_WLAST : IN STD_LOGIC; + S_AXI_WVALID : IN STD_LOGIC; + S_AXI_WREADY : OUT STD_LOGIC; + S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_BVALID : OUT STD_LOGIC; + S_AXI_BREADY : IN STD_LOGIC; + + -- AXI Full/Lite Slave Read (Write side) + S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_ARVALID : IN STD_LOGIC; + S_AXI_ARREADY : OUT STD_LOGIC; + S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_RLAST : OUT STD_LOGIC; + S_AXI_RVALID : OUT STD_LOGIC; + S_AXI_RREADY : IN STD_LOGIC; + + -- AXI Full/Lite Sideband Signals + S_AXI_INJECTSBITERR : IN STD_LOGIC; + S_AXI_INJECTDBITERR : IN STD_LOGIC; + S_AXI_SBITERR : OUT STD_LOGIC; + S_AXI_DBITERR : OUT STD_LOGIC; + S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + S_ARESETN : IN STD_LOGIC + + + ); + +END bmg_wrapper; + + +ARCHITECTURE xilinx OF bmg_wrapper IS + + COMPONENT mem_4k8_top IS + PORT ( + --Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + + CLKA : IN STD_LOGIC; + + + --Port B + ENB : IN STD_LOGIC; --opt port + ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + CLKB : IN STD_LOGIC + + + ); + END COMPONENT; + +BEGIN + + bmg0 : mem_4k8_top + PORT MAP ( + --Port A + ENA => ENA, + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + CLKA => CLKA, + + --Port B + ENB => ENB, + ADDRB => ADDRB, + DOUTB => DOUTB, + CLKB => CLKB + + + ); +END xilinx; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.ucf =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.ucf (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.ucf (revision 138) @@ -0,0 +1,61 @@ +################################################################################ +# +# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Tx Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +NET "CLKA" TNM_NET = "CLKA"; + +NET "CLKB" TNM_NET = "CLKB"; + +TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ; + +TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ; + +################################################################################ Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.vhd (revision 138) @@ -0,0 +1,178 @@ +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v6.2 Core - Top-level core wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_wrapper.vhd +-- +-- Description: +-- This is the actual BMG core wrapper. +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY mem_4k8_top IS + PORT ( + --Inputs - Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + CLKA : IN STD_LOGIC; + + + --Inputs - Port B + ENB : IN STD_LOGIC; --opt port + ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + CLKB : IN STD_LOGIC + + ); + +END mem_4k8_top; + + +ARCHITECTURE xilinx OF mem_4k8_top IS + + COMPONENT BUFG IS + PORT ( + I : IN STD_ULOGIC; + O : OUT STD_ULOGIC + ); + END COMPONENT; + + COMPONENT mem_4k8 IS + PORT ( + --Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + + CLKA : IN STD_LOGIC; + + + --Port B + ENB : IN STD_LOGIC; --opt port + ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + CLKB : IN STD_LOGIC + + + ); + END COMPONENT; + + SIGNAL CLKA_buf : STD_LOGIC; + SIGNAL CLKB_buf : STD_LOGIC; + SIGNAL S_ACLK_buf : STD_LOGIC; + +BEGIN + + bufg_A : BUFG + PORT MAP ( + I => CLKA, + O => CLKA_buf + ); + + bufg_B : BUFG + PORT MAP ( + I => CLKB, + O => CLKB_buf + ); + + + bmg0 : mem_4k8 + PORT MAP ( + --Port A + ENA => ENA, + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + CLKA => CLKA_buf, + + + --Port B + ENB => ENB, + ADDRB => ADDRB, + DOUTB => DOUTB, + CLKB => CLKB_buf + + ); + +END xilinx; Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.xdc =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.xdc (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/example_design/mem_4k8_top.xdc (revision 138) @@ -0,0 +1,56 @@ +################################################################################ +# +# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ] + +create_clock -name "TS_CLKB" -period 20.0 [ get_ports CLKB ] +################################################################################ Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/implement.bat =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/implement.bat (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/implement.bat (revision 138) @@ -0,0 +1,41 @@ + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy mem_4k8_top.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\mem_4k8.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\mem_4k8_top.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc6slx45-csg324-3 mem_4k8_top + +echo 'Running map' +map mem_4k8_top -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level VHDL model' +netgen -ofmt vhdl -sim -tm mem_4k8_top -pcf mapped.pcf -w routed.ncd routed.vhd Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/implement.sh =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/implement.sh (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/implement.sh (revision 138) @@ -0,0 +1,40 @@ +#!/bin/sh + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files +echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp mem_4k8_top.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../mem_4k8.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/mem_4k8_top.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc6slx45-csg324-3 mem_4k8_top + +echo 'Running map' +map mem_4k8_top -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level VHDL model' +netgen -ofmt vhdl -sim -tm mem_4k8_top -pcf mapped.pcf -w routed.ncd routed.vhd Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.bat =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.bat (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.bat (revision 138) @@ -0,0 +1,55 @@ +#!/bin/sh +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\tmp\mem_4k8.edf . +planAhead -mode batch -source ..\planAhead_rdn.tcl Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.sh =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.sh (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.sh (revision 138) @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../tmp/mem_4k8.edf . +planAhead -mode batch -source ../planAhead_rdn.tcl Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.tcl =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.tcl (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/planAhead_rdn.tcl (revision 138) @@ -0,0 +1,68 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc6slx45csg324-3 +set projName mem_4k8 +set design mem_4k8 +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module mem_4k8_top +add_files -norecurse {../../example_design/mem_4k8_top.vhd} +add_files -norecurse {./mem_4k8.edf} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/mem_4k8_top.xdc} +set_property top mem_4k8_top [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +set_param sta.dlyMediator true +write_sdf -rename_top_module mem_4k8_top -file routed.sdf +write_verilog -nolib -mode sim -sdf_anno false -rename_top_module mem_4k8_top routed.vhd +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file routed.drc +#write_bitstream Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/xst.prj =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/xst.prj (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/xst.prj (revision 138) @@ -0,0 +1,1 @@ +work ../example_design/mem_4k8_top.vhd Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/xst.scr =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/xst.scr (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/mem_4k8_ste/implement/xst.scr (revision 138) @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent mem_4k8_top +-p xc6slx45-csg324-3 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn mem_4k8_top +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_cg/_dbg/xil_444.in =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_cg/_dbg/xil_444.in (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_cg/_dbg/xil_444.in (revision 138) @@ -0,0 +1,92 @@ +SET_FLAG DEBUG FALSE +SET_FLAG MODE INTERACTIVE +SET_FLAG STANDALONE_MODE FALSE +SET_PREFERENCE devicefamily spartan6 +SET_PREFERENCE device xc6slx45 +SET_PREFERENCE speedgrade -3 +SET_PREFERENCE package csg324 +SET_PREFERENCE verilogsim false +SET_PREFERENCE vhdlsim true +SET_PREFERENCE simulationfiles Behavioral +SET_PREFERENCE busformat BusFormatAngleBracketNotRipped +SET_PREFERENCE outputdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/ +SET_PREFERENCE workingdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/ +SET_PREFERENCE subworkingdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/_cg/ +SET_PREFERENCE transientdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/_cg/_dbg/ +SET_PREFERENCE designentry VHDL +SET_PREFERENCE flowvendor Other +SET_PREFERENCE addpads false +SET_PREFERENCE projectname coregen +SET_PREFERENCE formalverification false +SET_PREFERENCE asysymbol false +SET_PREFERENCE implementationfiletype Ngc +SET_PREFERENCE foundationsym false +SET_PREFERENCE createndf false +SET_PREFERENCE removerpms false +SET_PARAMETER Component_Name mem_4k8 +SET_PARAMETER Interface_Type Native +SET_PARAMETER AXI_Type AXI4_Full +SET_PARAMETER AXI_Slave_Type Memory_Slave +SET_PARAMETER Use_AXI_ID false +SET_PARAMETER AXI_ID_Width 4 +SET_PARAMETER Memory_Type Simple_Dual_Port_RAM +SET_PARAMETER ecctype No_ECC +SET_PARAMETER ECC false +SET_PARAMETER softecc false +SET_PARAMETER Use_Error_Injection_Pins false +SET_PARAMETER Error_Injection_Type Single_Bit_Error_Injection +SET_PARAMETER Use_Byte_Write_Enable true +SET_PARAMETER Byte_Size 8 +SET_PARAMETER Algorithm Minimum_Area +SET_PARAMETER Primitive 8kx2 +SET_PARAMETER Assume_Synchronous_Clk false +SET_PARAMETER Write_Width_A 8 +SET_PARAMETER Write_Depth_A 4096 +SET_PARAMETER Read_Width_A 8 +SET_PARAMETER Operating_Mode_A WRITE_FIRST +SET_PARAMETER Enable_A Use_ENA_Pin +SET_PARAMETER Write_Width_B 8 +SET_PARAMETER Read_Width_B 8 +SET_PARAMETER Operating_Mode_B WRITE_FIRST +SET_PARAMETER Enable_B Use_ENB_Pin +SET_PARAMETER Register_PortA_Output_of_Memory_Primitives false +SET_PARAMETER Register_PortA_Output_of_Memory_Core false +SET_PARAMETER Use_REGCEA_Pin false +SET_PARAMETER Register_PortB_Output_of_Memory_Primitives false +SET_PARAMETER Register_PortB_Output_of_Memory_Core false +SET_PARAMETER Use_REGCEB_Pin false +SET_PARAMETER register_porta_input_of_softecc false +SET_PARAMETER register_portb_output_of_softecc false +SET_PARAMETER Pipeline_Stages 0 +SET_PARAMETER Load_Init_File false +SET_PARAMETER Coe_File no_coe_file_loaded +SET_PARAMETER Fill_Remaining_Memory_Locations false +SET_PARAMETER Remaining_Memory_Locations 0 +SET_PARAMETER Use_RSTA_Pin false +SET_PARAMETER Reset_Memory_Latch_A false +SET_PARAMETER Reset_Priority_A CE +SET_PARAMETER Output_Reset_Value_A 0 +SET_PARAMETER Use_RSTB_Pin false +SET_PARAMETER Reset_Memory_Latch_B false +SET_PARAMETER Reset_Priority_B CE +SET_PARAMETER Output_Reset_Value_B 0 +SET_PARAMETER Reset_Type SYNC +SET_PARAMETER Additional_Inputs_for_Power_Estimation false +SET_PARAMETER Port_A_Clock 100 +SET_PARAMETER Port_A_Write_Rate 50 +SET_PARAMETER Port_B_Clock 100 +SET_PARAMETER Port_B_Write_Rate 0 +SET_PARAMETER Port_A_Enable_Rate 100 +SET_PARAMETER Port_B_Enable_Rate 100 +SET_PARAMETER Collision_Warnings ALL +SET_PARAMETER Disable_Collision_Warnings false +SET_PARAMETER Disable_Out_of_Range_Warnings false +SET_CORE_NAME Block Memory Generator +SET_CORE_VERSION 6.2 +SET_CORE_VLNV xilinx.com:ip:blk_mem_gen:6.2 +SET_CORE_CLASS com.xilinx.ip.blk_mem_gen_v6_2.blk_mem_gen_v6_2 +SET_CORE_PATH C:/Xilinx/13.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2 +SET_CORE_GUIPATH C:/Xilinx/13.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2/gui/blk_mem_gen_v6_2.tcl +SET_CORE_DATASHEET C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_ds512.pdf +ADD_CORE_DOCUMENT +ADD_CORE_DOCUMENT Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_cg/_dbg/xil_444.out =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_cg/_dbg/xil_444.out (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_cg/_dbg/xil_444.out (revision 138) @@ -0,0 +1,61 @@ +SET_PARAMETER use_rstb_pin false +SET_PARAMETER pipeline_stages 0 +SET_PARAMETER assume_synchronous_clk false +SET_PARAMETER use_regcea_pin false +SET_PARAMETER axi_id_width 4 +SET_PARAMETER softecc false +SET_PARAMETER load_init_file false +SET_PARAMETER port_a_write_rate 50 +SET_PARAMETER disable_collision_warnings false +SET_PARAMETER use_byte_write_enable true +SET_PARAMETER ecc false +SET_PARAMETER primitive 8kx2 +SET_PARAMETER port_b_clock 100 +SET_PARAMETER remaining_memory_locations 0 +SET_PARAMETER memory_type Simple_Dual_Port_RAM +SET_PARAMETER register_porta_input_of_softecc false +SET_PARAMETER port_a_clock 100 +SET_PARAMETER read_width_a 8 +SET_PARAMETER disable_out_of_range_warnings false +SET_PARAMETER read_width_b 8 +SET_PARAMETER register_portb_output_of_softecc false +SET_PARAMETER byte_size 8 +SET_PARAMETER register_portb_output_of_memory_core false +SET_PARAMETER use_regceb_pin false +SET_PARAMETER register_porta_output_of_memory_core false +SET_PARAMETER reset_memory_latch_a false +SET_PARAMETER reset_memory_latch_b false +SET_PARAMETER register_porta_output_of_memory_primitives false +SET_PARAMETER use_error_injection_pins false +SET_PARAMETER enable_a Use_ENA_Pin +SET_PARAMETER enable_b Use_ENB_Pin +SET_PARAMETER port_a_enable_rate 100 +SET_PARAMETER use_axi_id false +SET_PARAMETER write_depth_a 4096 +SET_PARAMETER algorithm Minimum_Area +SET_PARAMETER output_reset_value_a 0 +SET_PARAMETER output_reset_value_b 0 +SET_PARAMETER error_injection_type Single_Bit_Error_Injection +SET_PARAMETER port_b_write_rate 0 +SET_PARAMETER ecctype No_ECC +SET_PARAMETER write_width_a 8 +SET_PARAMETER write_width_b 8 +SET_PARAMETER component_name mem_4k8 +SET_PARAMETER reset_priority_a CE +SET_PARAMETER reset_priority_b CE +SET_PARAMETER operating_mode_a WRITE_FIRST +SET_PARAMETER additional_inputs_for_power_estimation false +SET_PARAMETER operating_mode_b WRITE_FIRST +SET_PARAMETER interface_type Native +SET_PARAMETER reset_type SYNC +SET_PARAMETER register_portb_output_of_memory_primitives false +SET_PARAMETER use_rsta_pin false +SET_PARAMETER port_b_enable_rate 100 +SET_PARAMETER coe_file no_coe_file_loaded +SET_PARAMETER fill_remaining_memory_locations false +SET_PARAMETER axi_slave_type Memory_Slave +SET_PARAMETER axi_type AXI4_Full +SET_PARAMETER collision_warnings ALL +SET_ERROR_CODE 2 +SET_ERROR_MSG CANCEL: Customization cancelled. +SET_ERROR_TEXT Finished initializing IP model. Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_cg/summary.log =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_cg/summary.log (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_cg/summary.log (revision 138) @@ -0,0 +1,19 @@ + +User Configuration +------------------------------------- +Algorithm : Minimum_Area +Memory Type : Simple_Dual_Port_RAM +Port A Write Width : 8 +Port B Read Width : 8 +Memory Depth : 4096 +-------------------------------------------------------------- + +Block RAM resource(s) (9K BRAMs) : 0 +Block RAM resource(s) (18K BRAMs) : 2 +-------------------------------------------------------------- +Clock A Frequency : 100 +Port A Enable Rate : 100 +Port A Write Rate : 50 +---------------------------------------------------------- +Estimated Power for IP : 3.303411 mW +---------------------------------------------------------- Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs (revision 138) @@ -0,0 +1,9 @@ + + + + + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs (revision 138) @@ -0,0 +1,15 @@ + + + + + + + + + + +Parsing VHDL file "D:/MPI_HCL/Test_Timer/ipcore_dir/mem8k8.vhd" into library work + + + + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_xmsgs/xst.xmsgs =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_xmsgs/xst.xmsgs (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/_xmsgs/xst.xmsgs (revision 138) @@ -0,0 +1,351 @@ + + + +Message file "usenglish/ip.msg" wasn't found. + + +0: (0,0) : 4x8192 u:4 + + +1: (4,0) : 4x8192 u:4 + + +0: (0,0) : 4x8192 u:4 + + +1: (4,0) : 4x8192 u:4 + + +"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 977: Range is empty (null range) + + +"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 977: Assignment ignored + + +"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 978: Range is empty (null range) + + +"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 978: Assignment ignored + + +"D:\MPI_HCL\Test_Timer\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_wrapper_v6.vhd" Line 510: Net <douta_i[3]> does not have a driver. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <douta> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <rdaddrecc> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <s_axi_bid> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <s_axi_bresp> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <s_axi_rid> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <s_axi_rdata> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <s_axi_rresp> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <s_axi_rdaddrecc> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <sbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <dbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <s_axi_awready> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <s_axi_wready> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <s_axi_bvalid> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <s_axi_arready> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <s_axi_rlast> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <s_axi_rvalid> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <s_axi_sbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/mem8k8.vhd" line 160: Output port <s_axi_dbiterr> of the instance <U0> is unconnected or connected to loadless signal. + + +Input <S_AXI_AWID<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWADDR<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWLEN<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWSIZE<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWBURST<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WDATA<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WSTRB<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARID<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARADDR<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARLEN<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARSIZE<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARBURST<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_ARESETN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_AWVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WLAST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_WVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_BREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_ARVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_RREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <S_AXI_INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'S_AXI_BID', unconnected in block 'blk_mem_gen_v6_2_xst', is tied to its initial value (0000). + + +Signal <S_AXI_BRESP> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal 'S_AXI_RID', unconnected in block 'blk_mem_gen_v6_2_xst', is tied to its initial value (0000). + + +Signal <S_AXI_RDATA> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RRESP> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_AWREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_WREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_BVALID> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_ARREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RLAST> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_RVALID> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <S_AXI_DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <WEB<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <RSTA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <RSTB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <INJECTDBITERR_I> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <INJECTSBITERR_I> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <REGCEA<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEB<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <SBITERR> of the instance <ramloop[0].ram.r> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <DBITERR> of the instance <ramloop[0].ram.r> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <SBITERR> of the instance <ramloop[1].ram.r> is unconnected or connected to loadless signal. + + +"d:/mpi_hcl/test_timer/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <DBITERR> of the instance <ramloop[1].ram.r> is unconnected or connected to loadless signal. + + +Signal <RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <WEB<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <SSRA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <SSRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'douta_i', unconnected in block 'blk_mem_gen_prim_wrapper_v6_1', is tied to its initial value (0000). + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <WEB<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DINB<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <SSRA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <SSRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal 'douta_i', unconnected in block 'blk_mem_gen_prim_wrapper_v6_2', is tied to its initial value (0000). + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <DOUTA_I<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <RDADDRECC_I<12:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <SBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <DBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + + + + Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/blk_mem_gen_v6_2.lso =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/blk_mem_gen_v6_2.lso (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/blk_mem_gen_v6_2.lso (revision 138) @@ -0,0 +1,1 @@ +work Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/mem8k8.lso =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/mem8k8.lso (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/mem8k8.lso (revision 138) @@ -0,0 +1,1 @@ +work Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/mem_4k8.lso =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/mem_4k8.lso (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/ipcore_dir/tmp/mem_4k8.lso (revision 138) @@ -0,0 +1,1 @@ +work Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/mpi_test_wave.fdo =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/mpi_test_wave.fdo (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/mpi_test_wave.fdo (revision 138) @@ -0,0 +1,11 @@ +###################################################################### +## +## Filename: mpi_test_wave.fdo +## Created on: Mon Feb 03 17:58:39 Europe de l’Ouest 2014 +## +## Auto generated by Project Navigator for Post-Behavioral Simulation +## +## You may want to edit this file to control your simulation windows. +## +###################################################################### +add wave * Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/wave.do =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/wave.do (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/wave.do (revision 138) @@ -0,0 +1,146 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /mpi_test/clk +add wave -noupdate /mpi_test/reset +add wave -noupdate /mpi_test/result +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_in +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_out +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_rd +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_wr +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ram_address +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_in +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_out +add wave -noupdate /mpi_test/clk +add wave -noupdate /mpi_test/reset +add wave -noupdate /mpi_test/result +add wave -noupdate /mpi_test/clk +add wave -noupdate /mpi_test/reset +add wave -noupdate /mpi_test/result +add wave -noupdate /mpi_test/clk +add wave -noupdate /mpi_test/reset +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/src_address +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_data +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_wr_en +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/dma_rd_grant +add wave -noupdate /mpi_test/result +add wave -noupdate /mpi_test/clk +add wave -noupdate /mpi_test/reset +add wave -noupdate /mpi_test/result +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_rd +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_wr +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_whole +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_done +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_BitMask +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_BitVal +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_address +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_in +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_out +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_rd +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_wr +add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/RunState +add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/ct_state +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/ex1_state +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_data +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/fifo_src +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ex2_state +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/Snd_Start +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/Snd_Start +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/stInit2 +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/etcmd +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/etrec +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/port_out_data +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/port_out_data_available +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/snd_start_i +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_data +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/n +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_wr_en +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/fifo_data_out +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/p_len +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/fifo_rd_en +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/fifo_empty +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ex2_state +add wave -noupdate -radix unsigned /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/P_len +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_data_available +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/dest_address +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/P_len +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/n +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ex2_state +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/State +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_in +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_out +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/n +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/n_i +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/P_len +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/P_len_i +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_wr_request +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_wr_grant +add wave -noupdate /mpi_test/result +add wave -noupdate -expand -subitemconfig {/mpi_test/uut/PE_s(1)/S/HT_task/sram.O {-height 18 -childformat {{/mpi_test/uut/PE_s(1)/S/HT_task/sram.O.addr_wr -radix hexadecimal} {/mpi_test/uut/PE_s(1)/S/HT_task/sram.O.addr_rd -radix hexadecimal} {/mpi_test/uut/PE_s(1)/S/HT_task/sram.O.data_in -radix hexadecimal}} -expand} /mpi_test/uut/PE_s(1)/S/HT_task/sram.O.addr_wr {-height 18 -radix hexadecimal} /mpi_test/uut/PE_s(1)/S/HT_task/sram.O.addr_rd {-height 18 -radix hexadecimal} /mpi_test/uut/PE_s(1)/S/HT_task/sram.O.data_in {-height 18 -radix hexadecimal} /mpi_test/uut/PE_s(1)/S/HT_task/sram.I -expand} /mpi_test/uut/PE_s(1)/S/HT_task/sram +add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/Libr +add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/RunState +add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/ct_state +add wave -noupdate /mpi_test/uut/PE_s(2)/S/HT_task/RunState +add wave -noupdate /mpi_test/uut/PE_s(2)/S/HT_task/ct_state +add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/HT_task/sram.O.addr_rd +add wave -noupdate /mpi_test/uut/PE_s(2)/S/HT_task/sram.I.data_out +add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Ram8k8/addra +add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Ram8k8/addrb +add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/doutb +add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/dina +add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/wea(0) +add wave -noupdate /mpi_test/uut/dyn_HT/PE_D(3)/D/HT_task/RunState +add wave -noupdate /mpi_test/uut/dyn_HT/PE_D(4)/D/HT_task/RunState +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ex2_state +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/GPost +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Rec_WPost +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Received_get +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/GPost_Set +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Waited_Get(0) +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/GComp +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ex2_state +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/n +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/ex1_state +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/fifo_data_out +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/n +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_address +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_rd_grant +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_wr_grant +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dest_address +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/WBUSY +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Rec_WPost +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Received_get +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Set_Wbusy +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Waited_Get(0) +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/GPost +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/GComp +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/GPost_Set +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_data_available +add wave -noupdate /mpi_test/clk +add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/enb +add wave -noupdate /mpi_test/uut/PE_s(2)/S/Ram8k8/wea(0) +add wave -noupdate -radix binary /mpi_test/uut/PE_s(2)/S/Ram8k8/doutb +add wave -noupdate -radix binary /mpi_test/uut/PE_s(2)/S/Ram8k8/dina +add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Ram8k8/addrb +add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Ram8k8/addra +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {13042 ps} 0} {{Cursor 2} {31415000 ps} 0} {{Cursor 3} {100265000 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 165 +configure wave -valuecolwidth 135 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {74096 ps} Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/wave4.do =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/wave4.do (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/Test_Timer/wave4.do (revision 138) @@ -0,0 +1,130 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /mpi_test/clk +add wave -noupdate /mpi_test/reset +add wave -noupdate /mpi_test/result +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/State +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/whole +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_in +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_out +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/setbit1/ram_wr +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_rd +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_wr +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ram_address +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_in +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_out +add wave -noupdate /mpi_test/clk +add wave -noupdate /mpi_test/reset +add wave -noupdate /mpi_test/result +add wave -noupdate /mpi_test/clk +add wave -noupdate /mpi_test/reset +add wave -noupdate /mpi_test/result +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ex2_state +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ack_state +add wave -noupdate /mpi_test/clk +add wave -noupdate /mpi_test/reset +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/ex1_state +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/src_address +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_data +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_wr_en +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/dma_rd_grant +add wave -noupdate /mpi_test/result +add wave -noupdate /mpi_test/clk +add wave -noupdate /mpi_test/reset +add wave -noupdate /mpi_test/result +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_rd +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_ram_wr +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_whole +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_done +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_BitMask +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/sb_BitVal +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_address +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_in +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/Ram_data_out +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_rd +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ram_wr +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/dma_rd_request +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/dma_wr_request +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/dma_rd_grant +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/dma_wr_grant +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/ex1_state +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/Snd_Start +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/Snd_Start +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/stInit2 +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX4_FSM/snd_start_i +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_data +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/n +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/switch_port_in_wr_en +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/fifo_data_out +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/p_len +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/fifo_rd_en +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX1_FSM/fifo_empty +add wave -noupdate /mpi_test/clk +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ex2_state +add wave -noupdate -radix unsigned /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/P_len +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/switch_data_available +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX1_FSM/dest_address +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/P_len +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/n +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ex2_state +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/State +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/ram_rd +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/ram_wr +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_in +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/setbit1/Ram_data_out +add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Inst_RAM_v/addra +add wave -noupdate -radix hexadecimal /mpi_test/uut/PE_s(2)/S/Inst_RAM_v/addrb +add wave -noupdate /mpi_test/uut/PE_s(2)/S/Inst_RAM_v/dia +add wave -noupdate /mpi_test/uut/PE_s(2)/S/Inst_RAM_v/dob +add wave -noupdate /mpi_test/uut/PE_s(2)/S/Inst_RAM_v/wea +add wave -noupdate /mpi_test/uut/PE_s(2)/S/Inst_RAM_v/ena +add wave -noupdate /mpi_test/uut/PE_s(2)/S/Inst_RAM_v/enb +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/switch_port_out_data +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/n +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/n_i +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/P_len +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/P_len_i +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/ex2_fsm_logic/delai +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_wr_request +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(2)/hardmpi/MPI_CORE_EX2_FSM/dma_wr_grant +add wave -noupdate /mpi_test/result +add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/sram +add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/Libr +add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/RunState +add wave -noupdate /mpi_test/uut/PE_s(1)/S/HT_task/ct_state +add wave -noupdate /mpi_test/uut/PE_s(2)/S/HT_task/RunState +add wave -noupdate /mpi_test/uut/PE_s(2)/S/HT_task/ct_state +add wave -noupdate /mpi_test/uut/dyn_HT/PE_D(3)/D/HT_task/RunState +add wave -noupdate /mpi_test/uut/dyn_HT/PE_D(4)/D/HT_task/RunState +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ex2_state +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/ack_state +add wave -noupdate /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/pop_state +add wave -noupdate -radix unsigned /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/data_counter +add wave -noupdate /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/fifo_read_signal +add wave -noupdate /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/pipeline_latch_en +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/fifo_out_signal +add wave -noupdate /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/fifo_empty_signal +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/data_out +add wave -noupdate /mpi_test/uut/Xbar/Socsyst/sw_gen1/switch4x4_7x7/switch_4x4_7x7(1)/PORTx4_INPUT_PORT_MODULE/data_out_pulse +add wave -noupdate -radix hexadecimal /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/fifo_data +add wave -noupdate /mpi_test/uut/Xbar/HCL_c(1)/hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en +TreeUpdate [SetDefaultTree] +quietly WaveActivateNextPane +WaveRestoreCursors {{Cursor 7} {32545000 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 179 +configure wave -valuecolwidth 155 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {32512840 ps} {32577160 ps} Index: /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/mpi_test.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/mpi_test.vhd (revision 138) +++ /PROJECT_CORE_MPI/MPI_HCL/TAG/v1.0/mpi_test.vhd (revision 138) @@ -0,0 +1,89 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07:29:14 03/26/2013 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/mpi_test.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: MultiMPITest +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY mpi_test IS +END mpi_test; + +ARCHITECTURE behavior OF mpi_test IS + signal clk,reset : std_logic:='0'; + signal result : std_logic_vector(7 downto 0); + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT MultiMPITest + + port (clkm : in std_logic; + reset : in std_logic; + result : out std_logic_vector(7 downto 0)); + + END COMPONENT; + + -- No clocks detected in port list. Replace below with + -- appropriate port name + + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: MultiMPITest PORT MAP ( + clkm=>clk, + reset=>reset, + result=>result + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + reset<='1'; + wait for clk_period*10; + reset<='0'; + wait ; + + -- insert stimulus here + + wait; + end process; + +END;