Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Crossbar.vhd
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/Crossbar.vhd	(revision 101)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Crossbar.vhd	(revision 139)
@@ -38,20 +38,20 @@
     Port ( clk : in  STD_LOGIC;
 			  reset : in  STD_LOGIC; --pour gérer le pipeline
-			  Port1_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port2_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port3_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port4_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-			  Port5_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port6_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port7_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port8_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-			  Port9_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port10_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port11_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port12_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-			  Port13_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port14_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port15_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port16_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+			  Port1_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port2_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port3_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port4_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port5_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port6_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port7_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port8_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port9_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port10_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port13_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_in : in  STD_LOGIC_VECTOR (7 downto 0);
 			  
 			  Port1_pulse_in : in std_logic;
@@ -89,20 +89,20 @@
 			  Port16_pulse_out : out std_logic;
 			  
-			  Port1_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port2_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port3_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port4_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
-			  Port5_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port6_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port7_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port8_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
-			  Port9_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port10_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port11_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port12_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
-			  Port13_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port14_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port15_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port16_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
+			  Port1_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port2_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port3_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port4_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port5_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port6_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port7_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port8_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port9_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port10_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port13_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_out : out  STD_LOGIC_VECTOR (7 downto 0); 
 			  
            Ctrl : in  STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1)
