Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/CoreTypes.vhd
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/CoreTypes.vhd	(revision 101)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/CoreTypes.vhd	(revision 139)
@@ -9,5 +9,5 @@
 use IEEE.numeric_std.all;
 package CoreTypes is
-CONSTANT Word :POSITIVE:= 8;
+CONSTANT Word :POSITIVE:= 16;
 CONSTANT ADRLEN:POSITIVE:=16;
 CONSTANT LZFILL :std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0');--indique le nombre de zero à utiliser pour completer le bus de données lorsque la longueur restante du bus d'adresse est inférueure à la largeur du bus de données
@@ -37,4 +37,6 @@
    array(natural range <>) of std_logic_vector( Word-1 downto 0);
 	
+	type Typ_PortIO8 is
+   array(natural range <>) of std_logic_vector( 7 downto 0);
 	type memory is 
 	array (natural range <>) of std_logic_vector(word-1 downto 0);
@@ -176,5 +178,7 @@
 end component SWITCH_GEN;
 -- déclaration des fonctions utilisées
- 
+ function wor (din : std_logic_vector) return std_logic;
+subtype resolved_or is wor std_logic;
+
  FUNCTION all_ones(s1:std_logic_vector) return std_logic; 
   --This function returns if the input vector has all ones and no zeros
@@ -330,5 +334,5 @@
 variable bit_image: String(1 to 3) := std_logic'image(L);
 begin
-return(bit_image(1 to 1));
+return(bit_image(2 to 2));
 end function image;
 
@@ -355,3 +359,13 @@
 return(RetVal);
 end function image;
+function wor (din : std_logic_vector) return std_logic is
+begin
+for i in din'range loop
+if (din(i)='1') then
+return din(i);
+end if;
+end loop;
+return '0';
+end function wor;
+
 end CoreTypes;
Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Crossbar.vhd
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/Crossbar.vhd	(revision 101)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Crossbar.vhd	(revision 139)
@@ -38,20 +38,20 @@
     Port ( clk : in  STD_LOGIC;
 			  reset : in  STD_LOGIC; --pour gérer le pipeline
-			  Port1_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port2_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port3_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port4_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-			  Port5_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port6_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port7_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port8_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-			  Port9_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port10_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port11_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port12_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-			  Port13_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port14_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port15_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port16_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+			  Port1_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port2_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port3_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port4_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port5_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port6_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port7_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port8_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port9_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port10_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port13_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_in : in  STD_LOGIC_VECTOR (7 downto 0);
 			  
 			  Port1_pulse_in : in std_logic;
@@ -89,20 +89,20 @@
 			  Port16_pulse_out : out std_logic;
 			  
-			  Port1_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port2_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port3_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port4_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
-			  Port5_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port6_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port7_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port8_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
-			  Port9_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port10_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port11_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port12_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
-			  Port13_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port14_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port15_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
-           Port16_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
+			  Port1_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port2_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port3_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port4_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port5_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port6_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port7_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port8_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port9_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port10_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port13_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_out : out  STD_LOGIC_VECTOR (7 downto 0); 
 			  
            Ctrl : in  STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1)
Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Def_Request.vhd
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Def_Request.vhd	(revision 139)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Def_Request.vhd	(revision 139)
@@ -0,0 +1,95 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    17:58:09 04/07/2014 
+-- Design Name: 
+-- Module Name:    Def_Request - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Def_Request is
+generic (NB_IO :positive:=4);
+    Port ( Req : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+			  fifo_full : in STD_LOGIC_VECTOR (NB_IO downto 1);
+           priority_rotation : in  STD_LOGIC_VECTOR (NB_IO downto 1);
+           grant : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
+           request : out  STD_LOGIC_VECTOR (NB_IO**2 downto 1));
+end Def_Request;
+
+architecture Behavioral of Def_Request is
+constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S
+ Signal Fifo_out_full :  STD_LOGIC_VECTOR (NB_IO downto 1);
+ signal grant_latch : std_logic_vector(NB_IO2 downto 1); 
+ signal priority_rotation_en : std_logic; 
+signal req_grant,Grant_bak :  std_logic_vector(NB_IO2 downto 1):=(others=>'0');
+ signal Mreq :  std_logic_vector(NB_IO2 downto 1):=(others=>'1');
+
+begin
+ Req_grant<=(req and grant );
+ priority_rotation_en <= '1' when   unsigned(priority_rotation) = 2**NB_IO-1 else 	'0'; 
+ request<=req and mreq;
+--latch  qui memorise le signal grant pendant la transmission 
+ grant_latch_process : process(clk)
+  begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0');
+ 		Fifo_out_full<=(others => '0');
+ 	 elsif priority_rotation_en = '1' or unsigned(req_grant)=0 then 
+	   grant_latch <= Grant;
+	   Fifo_out_full<=fifo_full;
+  else
+    	 grant_latch <= Grant; 
+    	 Fifo_out_full<=fifo_full; 
+   end if; 
+   end if; 
+
+ end process; 
+ def_mreq: process(grant_latch,fifo_full)
+
+variable t:std_logic_vector(NB_IO2 downto 1):=(others=>'0');
+begin 
+    
+  for i in 0 to NB_IO2-1 loop
+    t(i+1):='0';
+    --sur le front montant de fifo_full sauver l'état Grant courant 
+    if fifo_full(i mod NB_IO+1)='1' and  fifo_out_full(i mod NB_IO+1)='0' then
+      Grant_bak(i+1)<= grant_latch(i+1);
+    elsif fifo_full(i mod NB_IO+1)='0' and  fifo_out_full(i mod NB_IO+1)='0'  then
+      Grant_bak(i+1)<='0';
+    end if;
+  for j in 0 to NB_IO-1 loop
+    t(i+1):=t(i+1) or grant_latch(j*NB_IO+1+i mod NB_IO) or fifo_out_full(i mod NB_IO+1);
+    
+  end loop;
+      mreq(i+1)<=not(t(i+1) ) or grant_latch(i+1)or grant_bak(i+1);    
+  end loop;
+end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/FIFO_256_FWFT.vhd
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/FIFO_256_FWFT.vhd	(revision 101)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/FIFO_256_FWFT.vhd	(revision 139)
@@ -66,11 +66,11 @@
 attribute RAM_STYLE : string;
 
-type ram_type is array (2**(MPROOF+word)-1 downto 0) of std_logic_vector (Word-1 downto 0);
+type ram_type is array (2**(MPROOF+8)-1 downto 0) of std_logic_vector (Word-1 downto 0);
 	signal RAM: ram_type;
 	attribute RAM_STYLE of RAM: signal is "BLOCK";
 -- declaration des signeaux des compteurs
-signal push_address_counter: std_logic_vector(MPROOF+Word-1 downto 0);
-signal pop_address_counter : std_logic_vector(MPROOF+Word-1 downto 0);
-signal fifo_counter : std_logic_vector(MPROOF+Word-1 downto 0);
+signal push_address_counter: std_logic_vector(MPROOF+8-1 downto 0);
+signal pop_address_counter : std_logic_vector(MPROOF+8-1 downto 0);
+signal fifo_counter : std_logic_vector(MPROOF+8-1 downto 0);
 --autre signaux
 signal empty_signal: std_logic:='1';
@@ -105,7 +105,7 @@
 wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein
 rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide
-full_signal <= '1' when unsigned(fifo_counter) = 2**(MProof+word)-1 else
+full_signal <= '1' when unsigned(fifo_counter) = 2**(MProof+8)-1 else
 				   '0';
-near_full <= '1' when unsigned(fifo_counter) >= 2**(MProof+word)-5 else
+near_full <= '1' when unsigned(fifo_counter) >= 2**(MProof+8)-5 else
 				   '0';
 --empty_signal <= '1' when fifo_counter = "000000"  else
@@ -254,5 +254,5 @@
  -- processus de comptage des octets dans le fifo
  fifo_counter_process : process(clk_signal)
-variable count : std_logic_vector(MPROOF+word-1 downto 0):= (others=>'0');
+variable count : std_logic_vector(MPROOF+8-1 downto 0):= (others=>'0');
 begin
  if rising_edge(clk_signal) then
Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/INPUT_PORT_MODULE.vhd
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/INPUT_PORT_MODULE.vhd	(revision 101)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/INPUT_PORT_MODULE.vhd	(revision 139)
@@ -40,6 +40,10 @@
 entity INPUT_PORT_MODULE is
     generic(number_of_ports : positive := 4;
-	 
-	 Port_num: natural:=1);  -- port_num est l'id du port
+				adr_mask : natural := 0;--le nombre de'1' en partant le la gauche de l'adresse
+				adr_len: positive:=10; --la taille en bit de l'adresse 10 bits --> 1024 hotes
+				tot_ports: positive :=8; --Nomnre de ports total du réseau
+				adr_sub_net : std_logic_vector(9 downto 0) := (others=>'0');--l'adresse du sous-réseau
+				Port_num: natural:=1;  -- port_num est l'id du port
+				nbyte : positive:=2); -- le nombre de Byte dans chaque mot du port par défaut 2
     Port ( data_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
            data_in_en : in  STD_LOGIC; -- signaler la présence des données en entrée
@@ -52,5 +56,5 @@
 			  fifo_empty : out  STD_LOGIC; -- le tampon d'entrée est vide
 			  priority_rotation : out std_logic;  -- reserver le canal de transmission
-           data_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); --données vers le réseau crossbar
+           data_out : out  STD_LOGIC_VECTOR (7 downto 0); --données vers le réseau crossbar
 			  data_out_pulse : out std_logic); -- permet de ...
        
@@ -73,6 +77,6 @@
 
 --definition du type etat pour les fsm
-type fsm_states is (state0, CmdOn, WaitGrant, ReqPort, state1, state2,strecover,stpulse,stateErr, state3);-- definition du type etat pour le codage des etats des fsm
-type fsm_states2 is(cmdstart,cmdwait,cmdread,cmdSetDest,cmdSetCount,cmdSetId,cmdpulse,CmdEnd);
+type fsm_states is (state0, CmdOn, WaitGrant, ReqPort,addhead,addheadn, state1,state1n, state2,state2n,strecover,stpulse,stpulsen,stateErr, state3);-- definition du type etat pour le codage des etats des fsm
+type fsm_states2 is(cmdstart,cmdwait,cmdread,cmdSetDest,cmdSetCount,cmdSetId,cmdSetDestn,cmdSetCountn,cmdSetIdn,cmdpulse,cmdpulsen,CmdEnd);
 signal pop_state : fsm_states;
 signal cmdstate : fsm_states2;
@@ -81,4 +85,10 @@
 signal dat_Err :std_logic:='0'; -- signal une erreur pendant l'exécution 
 signal wrok,readOk,CmdReadOk : std_logic:='0'; --indique s'il est possible de lire les données
+--
+signal rt_err : std_logic;--erreur sur la route
+signal route :std_logic_vector(9 downto 0);
+signal dest_port:std_logic_vector(Word/2-1 downto 0);
+signal nib,cnib:natural range 0 to 4:=1;--indique le sous-octet à traiter
+signal pulseOn :std_logic:='0';--indique que le prochain état est celui de l'impulsion 
 -- signaux utilisés dans les fsm
 signal request_decoder,req_grant : STD_LOGIC_VECTOR(number_of_ports  downto 1);
@@ -86,5 +96,5 @@
 signal request_latch : STD_LOGIC_VECTOR(4 downto 1):=(others=>'0');   -- pourquoi pas 3 downto 0 ?
 signal request_latch_en : std_logic;
-signal pipeline_latch : std_logic_vector(Word-1 downto 0);
+signal pipeline_latch : std_logic_vector(7 downto 0);
 signal pipeline_latch_en : std_logic;
 signal request_word :  std_logic_vector(5 downto 1);
@@ -110,11 +120,57 @@
 signal fifo_empty_signal : std_logic;
 signal fifo_read_signal : std_logic;
-signal fifo_out_signal,cmd_data_signal : std_logic_vector(Word-1 downto 0);
-signal push_dout : std_logic_vector(Word-1 downto 0);
+signal fifo_out_signal,fifo_out2,cmd_data_signal : std_logic_vector(Word-1 downto 0);
+signal push_dout : std_logic_vector(7 downto 0);
 signal empty_latch : std_logic ;
-signal PORT_ID :std_logic_vector(Word-1 downto 0):=STD_LOGIC_VECTOR(to_unsigned(number_of_ports-1,4))& STD_LOGIC_VECTOR(to_unsigned(port_num-1,4));
+
 -- signaux du compteur de données
 signal data_counter : std_logic_vector(Word-1 downto 0);
 
+function count_bits(param:natural) return natural is
+
+  variable p : natural range 0 to 127:=0;
+begin
+n1: for i in 0 to 127 loop
+    if param<=2**i then
+      p:=i;
+      exit n1;
+  end if;
+  end loop n1;
+  return p;
+end function;
+
+function Get_Port_ID(adr_sub_net:std_logic_vector;adr_mask:natural;n_ports:positive;numport:positive) return std_logic_vector is
+--cette fonction permet de calculer le port_id ou l'adresse de sous réseau en fonction du masque
+variable tport_id:std_logic_vector(adr_len-1 downto 0):=(others=>'0'); --
+variable p : natural range 0 to 9:=0;
+begin
+--n1: for i in 0 to 9 loop
+--    if n_ports-1<2**i then
+--      p:=i;
+--      exit n1;
+--  end if;
+--  end loop n1;
+  p:=count_bits(n_ports-1);
+    tport_id:=adr_sub_net(adr_len-1 downto p) & std_logic_vector(to_unsigned(numport-1,p));
+    return tport_id;
+end function;
+--case n_ports is 
+--when 1|2|3 =>tport_id(adr_len-1 downto adr_len-adr_mask-1):=adr_sub_net(adr_len-1 downto adr_len-adr_mask-1); 
+--tport_id(adr_len-adr_mask-2 downto adr_len-adr_mask-2):= std_logic_vector(to_unsigned(numport,1));
+--when 4|5 =>tport_id(adr_len-1 downto adr_len-adr_mask-1):=adr_sub_net(adr_len-1 downto adr_len-adr_mask-1); 
+--tport_id(adr_len-adr_mask-2 downto adr_len-adr_mask-3):= std_logic_vector(to_unsigned(numport,2));
+--when 6|9 =>tport_id(adr_len-1 downto adr_len-adr_mask-1):=adr_sub_net(adr_len-1 downto adr_len-adr_mask-1); 
+--tport_id(adr_len-adr_mask-2 downto adr_len-adr_mask-4):= std_logic_vector(to_unsigned(numport,3));
+--
+--when others => --10 to 16
+--tport_id(adr_len-1 downto adr_len-adr_mask-1):=adr_sub_net(adr_len-1 downto adr_len-adr_mask-1) ;
+--tport_id(adr_len-adr_mask-2 downto adr_len-adr_mask-5):= std_logic_vector(to_unsigned(numport,4));
+--
+--end case;
+--  return tport_id;
+--end function;
+signal PORT_ID :std_logic_vector(adr_len-1 downto 0):=GET_PORT_ID(adr_sub_net,adr_mask,number_of_ports,port_num);
+constant n_ports_bits:natural:=count_bits(number_of_ports-1);--compte le nombre de bit par port
+constant pid_bits:natural:=count_bits(tot_ports); --donne le nombre de bits utiles dans une adresse 
 begin
 -- instantiation du FIFO_256
@@ -471,26 +527,61 @@
 		  pipeline_latch <= push_dout;
 		  elsif pipeline_latch_en = '1' and cmd_exec='1' then
-		  pipeline_latch <= cmd_data_signal;
+		  pipeline_latch <= cmd_data_signal(8*cnib-1 downto 8*(cnib-1));
 	  end if;
 	end if;
 end process;
 
+
 --latch qui memorise l'adresse de destination du packet
 
 request_latch_process : process(clk)
+variable rt:std_logic_vector(9 downto 0):=(others=>'0');--route
+variable reql:std_logic_vector(4 downto 1):=(others=>'0');--request_latch
+--variable adr_e,p:natural range 0 to 15:=0;
+
 begin
 	if rising_edge(clk) then
 		if reset_signal = '1' then
-		  request_latch <= (others => '0');
+		  reql := (others => '0');
 		  elsif request_latch_en = '1' and cmd_in_en='0' then  --si la lecture de la destination est autorisée
-		  request_latch <=fifo_out_signal(3 downto 0); --fifo_out_signal(3) & fifo_out_signal(2) & fifo_out_signal(1) & fifo_out_signal(0);
-		assert (unsigned(fifo_out_signal(3 downto 0))<number_of_ports) 
-	report "Input_port_module n° " & integer'image(port_num) & " Le port sollicité n'existe pas le NoC va être bloqué !"
-	severity failure;
-		  elsif cmd_in_en='1' and request_latch_en='1' then  --c'est une commande le port de dest est le même que le port d'entrée
+		  rt:=(others=>'0');
+		 
+		  if adr_mask=0 then
+		    reql(n_ports_bits downto 1):=fifo_out_signal(pid_bits-adr_mask-1 downto pid_bits-adr_mask-n_ports_bits);
+		    request_latch(n_ports_bits downto 1)<=fifo_out_signal(pid_bits-adr_mask-1 downto pid_bits-adr_mask-n_ports_bits);
+		    report "Route racine:";
+		  else
+		  rt(pid_bits-1 downto pid_bits-adr_mask):=fifo_out_signal(pid_bits-1 downto pid_bits-adr_mask);
+		  if rt=adr_sub_net then
+		    report "Route trouvé:" & integer'image(to_integer(unsigned(rt))) & " adr_sub_net=" & integer'image(to_integer(unsigned(adr_sub_net))) & " fifo_out_sig:=" & image(fifo_out_signal) & " sur le port " & integer'image(to_integer(unsigned(port_id))+1);
+		    reql(n_ports_bits downto 1):=fifo_out_signal(pid_bits-adr_mask-1 downto pid_bits-adr_mask-n_ports_bits);
+		    request_latch(n_ports_bits downto 1)<=fifo_out_signal(pid_bits-adr_mask-1 downto pid_bits-adr_mask-n_ports_bits);
+		   
+		  else
+			 if number_of_ports=Port_num then --si c'est un paquet descendant alors le détruire
+			     report "Input_port_module n°" & integer'image(to_integer(unsigned(port_id))) & " La route sollicité n'existe pas dans ce sous réseau le paquet va être détruit ! fifo_out_sig:=" & image(fifo_out_signal);
+			     request_latch<="0000"; --à revoir il faut empêcher le routeur de se bloquer
+			     rt_err<='1'; --il faut activer la destruction du paquet
+			 else --faire monter les données vers le ports supérieur
+				  request_latch<=std_logic_vector(to_unsigned(number_of_ports-1,4));
+				  reql:=std_logic_vector(to_unsigned(number_of_ports-1,4));
+				  rt_err<='0';
+			 end if;
+		  
+		  end if;
+		 end if;
+		  report  "fifo_out=" & image(fifo_out_signal) & " pid_bits:=" & integer'image(pid_bits) & " adr_mask:=" & integer'image(adr_mask) & " rt:=" & image(rt) & " adr_sub_net=" & image(adr_sub_net) & " reql:=" & image(reql) & " sur le port "  & integer'image(to_integer(unsigned(port_id))+1);
+	  
+		        assert (unsigned(reql)<number_of_ports-1) 
+	         report "Input_port_module n° " & integer'image(port_num) & " Le port sollicité n'est pas dans la branche !"
+	         severity warning;
+		elsif cmd_in_en='1' and request_latch_en='1' then  --c'est une commande le port de dest est le même que le port d'entrée
 		   request_latch<=Port_ID(3 downto 0);  --car les ports commencent à 0
 		end if;
-	
-	end if;
+	 	end if;
+	--request_latch<=reql;
+	route<=rt; --pour le débogage uniquement pas besoin de conserver ce paramètre en principe
+
+
 end process;
 
@@ -515,4 +606,5 @@
 									pop_state <= CmdOn;
 								end if;
+								nib<=nbyte;
 			when CmdOn => if empty_latch='1' and cmd_in_en='0' then
 								pop_state <= state0;
@@ -533,7 +625,9 @@
 										--
 										pop_state <= state1;
-										
+										fifo_out2<=fifo_out_signal;
 								--end if;
-		
+			when addhead =>
+									pop_state <= addheadn;
+			when addheadn =>  pop_state <= state1;
 			when state1 => if port_granted ='1' then --lecture de la longueur des données
 										data_counter <= fifo_out_signal;
@@ -543,20 +637,32 @@
 												readOk<='1';
 										end if;
-										pop_state <= state2;
+										pop_state <= state1n;
+										nib<=nib-1;
 										wrok<='1';
 										else
 										  wrok<='0';
 							      end if;
-										
+							     
+			when state1n =>  		if nib=1 then
+												pop_state <= state2;
+												nib<=nbyte;
+										else
+											nib<=nib-1;
+										end if;
+										wrok<='1';
+										fifo_out2<=fifo_out_signal;
 			when state2 => if port_granted='1' then 
 			               wrok<='1';
 										if fifo_empty_signal ='0'  then
-										  if rd_en_signal ='1' and unsigned(data_counter)<= 3 then
+										  if rd_en_signal ='1' and unsigned(data_counter)<= 2 then
 											data_counter <= data_counter - 1;
-											pop_state <= stpulse;
+											pop_state <= state2n;
+											nib<=nib-1;
 											ReadOk<='1';
+											pulseon<='1';
 										elsif rd_en_signal ='1' then
 										  data_counter <= data_counter - 1;
-										  pop_state <= state2;
+										  pop_state <= state2n;
+										  nib<=nib-1;
 										  ReadOk<='1';
 										else --fifo_empty_signal='1' fin prématurée de la lecture
@@ -580,4 +686,17 @@
 										data_counter <= data_counter + 1;
 									end if;
+							 
+			when state2n => if nib=1 then
+			                 if pulseon='1' then
+												pop_state <= stpulse;
+												else
+												 pop_state <= state2;
+												end if;
+												nib<=nbyte;
+										else
+											nib<=nib-1;
+										end if;
+										wrok<='1';
+										 fifo_out2<=fifo_out_signal;
 			when strecover => if fifo_empty_signal='0' and port_granted='1' then
 			             pop_state<=state2;
@@ -591,9 +710,21 @@
 			            
 			when stpulse =>	if port_granted='1' then 
-											pop_state <= state3;		--pousser la dernière donnée dehors		
+											pop_state <= state3;--stpulsen;		--pousser la dernière donnée dehors		
+											--nib<=nib-1;
 											data_counter <= data_counter - 1;
 											wrok<='1';
-									end if;
-			                 wrok<='0';
+											pulseon<='0';
+									else
+											wrok<='0';
+									end if;  
+								  
+			when stpulsen => 	wrok<='0';
+									if nib=1 then
+												pop_state <= state3;
+												nib<=nbyte;
+										else
+											nib<=nib-1;
+										end if;
+										 fifo_out2<=fifo_out_signal;
 			when state3 => 	wrok<='0';
 										data_counter <= data_counter - 1;
@@ -611,5 +742,5 @@
 
 -- actions associées à chaque etat de la fsm de mealy
-pop_fsm_action : process(pop_state, fifo_out_signal,empty_latch, rd_en_signal,readok, port_granted )
+pop_fsm_action : process(pop_state, fifo_out_signal,fifo_out2,empty_latch, rd_en_signal,readok, port_granted,nib )
   begin   
 -- code fonctionnel	
@@ -623,5 +754,5 @@
 								dat_exec<='0';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal;
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
 								
 		when CmdOn =>		dat_request_latch_en <= '0';  
@@ -633,5 +764,5 @@
 								dat_exec<='0';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal;
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
 		when WaitGrant =>	
 								dat_request_latch_en <='1'; --autoriser l'identification du port de destination
@@ -643,8 +774,9 @@
 								dat_exec<='1';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0);
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
+								--push_dout<=fifo_out_signal(Word-1 downto Word/2)  & PORT_ID(Word/2-1 downto 0);
 		when ReqPort =>	
 								dat_request_latch_en <='1'; --autoriser l'identification du port de destination
-								dat_pipeline_latch_en <= '1'; --pour le transmettre à travers le réseau
+								dat_pipeline_latch_en <= '0'; --pour le transmettre à travers le réseau
 								dat_fifo_read_signal <= '1';
 								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
@@ -653,9 +785,29 @@
 								dat_exec<='1';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0);
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
+								--push_dout<=fifo_out_signal(Word-1 downto Word/2) & PORT_ID(Word/2-1 downto 0);
+		when addhead =>	
+								dat_request_latch_en <='0'; --autoriser l'identification du port de destination
+								dat_pipeline_latch_en <= '1'; --pour le transmettre à travers le réseau
+								dat_fifo_read_signal <= '0';
+								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+								dat_data_out_pulse <= '0';     --transmettre le signal pour le dernier mot
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								dat_Err<='0';
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
 							
 		when state1 =>    dat_request_latch_en <= '0';
 								dat_pipeline_latch_en <= rd_en_signal and port_granted;   
-								dat_fifo_read_signal <= rd_en_signal and port_granted;
+								dat_fifo_read_signal <= '0';--rd_en_signal and port_granted;
+								dat_request_decoder_en <= '1';
+								dat_data_out_pulse <= '0';--port_granted;
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								dat_Err<='0';
+								push_dout<=fifo_out2(8*nib-1 downto 8*(nib-1));
+		when state1n =>    dat_request_latch_en <= '0';
+								dat_pipeline_latch_en <= '1'; -- toujours actif pour cet octet
+								dat_fifo_read_signal <= '0';
 								dat_request_decoder_en <= '1';
 								dat_data_out_pulse <= port_granted;
@@ -663,5 +815,5 @@
 								dat_exec<='1';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal;
+								push_dout<=fifo_out2(8*nib-1 downto 8*(nib-1));
 								
 	  when state2 |strecover =>    dat_request_latch_en <= '0';
@@ -669,12 +821,21 @@
 								dat_fifo_read_signal <= port_granted and readok;   
 								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
-								dat_data_out_pulse <= port_granted and wrOk and not(fifo_empty_signal);
+								dat_data_out_pulse <= port_granted and wrOk ;--and not(fifo_empty_signal);
 								dat_priority_rotation <= '0';
 								dat_exec<='1';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal;
-								
-	  when stpulse =>    dat_request_latch_en <= '0'; --pousser la dernière donnée 
-								dat_pipeline_latch_en <= '0';  --autoriser la lecture du fifo en sortie
+								push_dout<=fifo_out2(8*nib-1 downto 8*(nib-1));
+		 
+		 when state2n  =>    dat_request_latch_en <= '0';
+								dat_pipeline_latch_en <= '1';  --autoriser la lecture du fifo en sortie
+								dat_fifo_read_signal <= '0';   
+								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+								dat_data_out_pulse <= port_granted and wrOk ;--and not(fifo_empty_signal);
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								dat_Err<='0';
+								push_dout<=fifo_out2(8*nib-1 downto 8*(nib-1));						
+	  when stpulse|stpulsen =>    dat_request_latch_en <= '0'; --pousser la dernière donnée 
+								dat_pipeline_latch_en <= wrok;  --autoriser la lecture du fifo en sortie
 								dat_fifo_read_signal <='0';   
 								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
@@ -683,5 +844,6 @@
 								dat_exec<='1';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal;
+								push_dout<=fifo_out2(8*nib-1 downto 8*(nib-1));
+	
 								
 		when state3 =>    dat_request_latch_en <= '0';
@@ -693,5 +855,5 @@
 								dat_exec<='0';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal;
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
 		when stateErr =>    dat_request_latch_en <= '0';
 								dat_pipeline_latch_en <= '0';
@@ -702,5 +864,5 @@
 								dat_exec<='1';
 								dat_Err<='1';
-								push_dout<=fifo_out_signal;
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
 		when others =>    dat_request_latch_en <= '0';
 								dat_pipeline_latch_en <= '0';
@@ -711,10 +873,10 @@
 								dat_exec<='0';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal;
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
 										
 		end case;
  end process; 
  -- traitement des commandes reçues par le switch
-fsm_cmd:process(clk,cmd_in_en)
+fsm_cmd:process(clk)
 variable timeout : natural:=0;
 variable cmdcode : natural range 0 to 255;
@@ -731,4 +893,5 @@
 				end if;
 				cmdReadOk<='0';
+				cnib<=nbyte;
 		when cmdwait => if port_granted='1' then  -- demande du port de sortie
 								
@@ -754,25 +917,55 @@
 --				end if;
 		when cmdsetdest =>
+				
 				if port_granted='1' then
+					cmdstate<=cmdsetdestn;
+					cnib<=cnib-1;
+				end if;
+				cmdReadOk<='0';
+		when cmdsetdestn =>  	if cnib=1 then
+												cmdstate<=cmdsetcount;
+												cnib<=nbyte;
+										else
+											cnib<=cnib-1;
+										end if;
+		when cmdsetcount =>
+				if port_granted='1' then
+					cmdstate<=cmdsetcountn;
+					cnib<=cnib-1;
+				else
 					cmdstate<=cmdsetcount;
 				end if;
 				cmdReadOk<='0';
-		when cmdsetcount =>
-				if port_granted='1' then
-					cmdstate<=cmdsetID;
-				else
-					cmdstate<=cmdsetdest;
-				end if;
-				cmdReadOk<='0';
+				
+		when cmdsetcountn =>  	if cnib=1 then
+												cmdstate<=cmdsetID;
+												cnib<=nbyte;
+										else
+											cnib<=cnib-1;
+										end if;
 		when cmdsetID=>
 			if port_granted='1' then
-			cmdstate <=cmdpulse;
+			cmdstate <=cmdsetIDn;
+			cnib<=cnib-1;
 			end if;
 			cmdReadOk<='0';
+		when cmdsetIDn =>  	if cnib=1 then
+												cmdstate<=cmdpulse;
+												cnib<=nbyte;
+										else
+											cnib<=cnib-1;
+										end if;
 		when cmdpulse =>
 			if port_granted='1' then
-			cmdstate <=cmdEnd;
+			cmdstate <=cmdpulsen;
+			cnib<=cnib-1;
 			end if;
 			cmdReadOk<='0';
+		when cmdpulsen => if cnib=1 then
+												cmdstate<=cmdEnd;
+												cnib<=nbyte;
+										else
+											cnib<=cnib-1;
+										end if;
 		when cmdend  =>
 			if cmd_in_en='0' then --éviter l'exécution en boucle
@@ -808,5 +1001,5 @@
 						cmd_data_out_pulse <= '0';
 						cmd_priority_rotation <= '1';                    --sans priorité
-						cmd_data_signal<=Port_ID;  
+						cmd_data_signal<=std_logic_vector(to_unsigned(tot_ports,Word-adr_len)) & Port_ID;  
 		when cmdwait =>
 						cmd_exec<='1';
@@ -816,5 +1009,5 @@
 						cmd_priority_rotation <= '0';    --avec priorité
 						cmd_request_decoder_en <= '1';   --demande d'émission
-						cmd_data_signal<=Port_ID;
+						cmd_data_signal<=std_logic_vector(to_unsigned(tot_ports,Word-adr_len)) & Port_ID;
 						cmd_data_out_pulse <= '0';					
 	when cmdsetdest  =>
@@ -827,6 +1020,17 @@
 						cmd_data_out_pulse <= '0';
 						cmd_priority_rotation <= '0';
-						cmd_data_signal<=Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
-	when cmdsetcount =>
+						cmd_data_signal<=std_logic_vector(to_unsigned(tot_ports,Word-adr_len)) & Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
+		when cmdsetdestn  =>
+						--cmd_request_decoder_en <= '1';
+						cmd_exec<='1';
+						cmd_pipeline_latch_en <='1'; --empiler dans le tampon de sortie la donnée
+						cmd_fifo_read_signal <='0';
+						cmd_request_latch_en<='0';
+						cmd_request_decoder_en <= '1';          --autoriser le decodeur à activer le dernier bit de request
+						cmd_data_out_pulse <= '1';
+						cmd_priority_rotation <= '0';
+						cmd_data_signal<=std_logic_vector(to_unsigned(tot_ports,Word-adr_len)) & Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
+
+	when cmdsetcount|cmdsetcountn=>
 								 
 						cmd_exec<='1';   
@@ -837,6 +1041,6 @@
 						cmd_data_out_pulse <= port_granted;
 						cmd_priority_rotation <= '0';
-						cmd_data_signal<=STD_LOGIC_VECTOR(to_unsigned(3,8));					
-	when cmdSetId =>
+						cmd_data_signal<=STD_LOGIC_VECTOR(to_unsigned(3,Word));					
+	when cmdSetId| cmdSetIdn=>
 						--cmd_request_decoder_en <= '1';
 						cmd_exec<='1';
@@ -847,8 +1051,8 @@
 						cmd_data_out_pulse <= port_granted;
 						cmd_priority_rotation <= '0';
-						cmd_data_signal<=Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
-											
+						cmd_data_signal<=std_logic_vector(to_unsigned(tot_ports,Word-adr_len)) & Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
+						report "Le nombre de port est" & integer'image(tot_ports) & " l'id du port est : " & image(port_id);					
 	when cmdpulse =>	cmd_exec<='1';
-						cmd_pipeline_latch_en <='0';
+						cmd_pipeline_latch_en <='1';
 						cmd_fifo_read_signal <='0';
 						cmd_request_latch_en<='0';
@@ -856,6 +1060,15 @@
 						cmd_data_out_pulse <= '1';--port_granted;     --s'assurer que la dernière donnée est bien lue
 						cmd_priority_rotation <= '0';
+						cmd_data_signal<=std_logic_vector(to_unsigned(tot_ports,Word-adr_len)) & Port_ID; 
+						
+	when cmdpulsen  =>	cmd_exec<='1';
+						cmd_pipeline_latch_en <='0';
+						cmd_fifo_read_signal <='0';
+						cmd_request_latch_en<='0';
+						cmd_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+						cmd_data_out_pulse <= '0';--port_granted;     --s'assurer que la dernière donnée est bien lue
+						cmd_priority_rotation <= '0';
 								--cmd_data_signal<=Port_ID ;
-						cmd_data_signal<=Port_ID; 
+						cmd_data_signal<=std_logic_vector(to_unsigned(tot_ports,Word-adr_len)) & Port_ID; 
 						
 	when cmdend =>
Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/INPUT_PORT_MODULE.vhd.bak
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/INPUT_PORT_MODULE.vhd.bak	(revision 101)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/INPUT_PORT_MODULE.vhd.bak	(revision 139)
@@ -40,6 +40,10 @@
 entity INPUT_PORT_MODULE is
     generic(number_of_ports : positive := 4;
-	 
-	 Port_num: natural:=1);  -- port_num est l'id du port
+				adr_mask : natural := 0;--le nombre de'1' en partant le la gauche de l'adresse
+				adr_len: positive:=10; --la taille en bit de l'adresse 10 bits --> 1024 hotes
+				tot_ports: positive :=8; --Nomnre de ports total du réseau
+				adr_sub_net : std_logic_vector(9 downto 0) := (others=>'0');--l'adresse du sous-réseau
+				Port_num: natural:=1;  -- port_num est l'id du port
+				nbyte : positive:=2); -- le nombre de Byte dans chaque mot du port par défaut 2
     Port ( data_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
            data_in_en : in  STD_LOGIC; -- signaler la présence des données en entrée
@@ -52,5 +56,5 @@
 			  fifo_empty : out  STD_LOGIC; -- le tampon d'entrée est vide
 			  priority_rotation : out std_logic;  -- reserver le canal de transmission
-           data_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); --données vers le réseau crossbar
+           data_out : out  STD_LOGIC_VECTOR (7 downto 0); --données vers le réseau crossbar
 			  data_out_pulse : out std_logic); -- permet de ...
        
@@ -73,6 +77,6 @@
 
 --definition du type etat pour les fsm
-type fsm_states is (state0, CmdOn, WaitGrant, ReqPort, state1, state2,strecover,stpulse,stateErr, state3);-- definition du type etat pour le codage des etats des fsm
-type fsm_states2 is(cmdstart,cmdwait,cmdread,cmdSetDest,cmdSetCount,cmdSetId,cmdpulse,CmdEnd);
+type fsm_states is (state0, CmdOn, WaitGrant, ReqPort,addhead,addheadn, state1,state1n, state2,state2n,strecover,stpulse,stpulsen,stateErr, state3);-- definition du type etat pour le codage des etats des fsm
+type fsm_states2 is(cmdstart,cmdwait,cmdread,cmdSetDest,cmdSetCount,cmdSetId,cmdSetDestn,cmdSetCountn,cmdSetIdn,cmdpulse,cmdpulsen,CmdEnd);
 signal pop_state : fsm_states;
 signal cmdstate : fsm_states2;
@@ -81,4 +85,10 @@
 signal dat_Err :std_logic:='0'; -- signal une erreur pendant l'exécution 
 signal wrok,readOk,CmdReadOk : std_logic:='0'; --indique s'il est possible de lire les données
+--
+signal rt_err : std_logic;--erreur sur la route
+signal route :std_logic_vector(9 downto 0);
+signal dest_port:std_logic_vector(Word/2-1 downto 0);
+signal nib,cnib:natural range 0 to 4:=1;--indique le sous-octet à traiter
+signal pulseOn :std_logic:='0';--indique que le prochain état est celui de l'impulsion 
 -- signaux utilisés dans les fsm
 signal request_decoder,req_grant : STD_LOGIC_VECTOR(number_of_ports  downto 1);
@@ -86,5 +96,5 @@
 signal request_latch : STD_LOGIC_VECTOR(4 downto 1):=(others=>'0');   -- pourquoi pas 3 downto 0 ?
 signal request_latch_en : std_logic;
-signal pipeline_latch : std_logic_vector(Word-1 downto 0);
+signal pipeline_latch : std_logic_vector(7 downto 0);
 signal pipeline_latch_en : std_logic;
 signal request_word :  std_logic_vector(5 downto 1);
@@ -110,11 +120,57 @@
 signal fifo_empty_signal : std_logic;
 signal fifo_read_signal : std_logic;
-signal fifo_out_signal,cmd_data_signal : std_logic_vector(Word-1 downto 0);
-signal push_dout : std_logic_vector(Word-1 downto 0);
+signal fifo_out_signal,fifo_out2,cmd_data_signal : std_logic_vector(Word-1 downto 0);
+signal push_dout : std_logic_vector(7 downto 0);
 signal empty_latch : std_logic ;
-signal PORT_ID :std_logic_vector(Word-1 downto 0):=STD_LOGIC_VECTOR(to_unsigned(number_of_ports-1,4))& STD_LOGIC_VECTOR(to_unsigned(port_num-1,4));
+
 -- signaux du compteur de données
 signal data_counter : std_logic_vector(Word-1 downto 0);
 
+function count_bits(param:natural) return natural is
+
+  variable p : natural range 0 to 127:=0;
+begin
+n1: for i in 0 to 127 loop
+    if param<=2**i then
+      p:=i;
+      exit n1;
+  end if;
+  end loop n1;
+  return p;
+end function;
+
+function Get_Port_ID(adr_sub_net:std_logic_vector;adr_mask:natural;n_ports:positive;numport:positive) return std_logic_vector is
+--cette fonction permet de calculer le port_id ou l'adresse de sous réseau en fonction du masque
+variable tport_id:std_logic_vector(adr_len-1 downto 0):=(others=>'0'); --
+variable p : natural range 0 to 9:=0;
+begin
+--n1: for i in 0 to 9 loop
+--    if n_ports-1<2**i then
+--      p:=i;
+--      exit n1;
+--  end if;
+--  end loop n1;
+  p:=count_bits(n_ports-1);
+    tport_id:=adr_sub_net(adr_len-1 downto p) & std_logic_vector(to_unsigned(numport-1,p));
+    return tport_id;
+end function;
+--case n_ports is 
+--when 1|2|3 =>tport_id(adr_len-1 downto adr_len-adr_mask-1):=adr_sub_net(adr_len-1 downto adr_len-adr_mask-1); 
+--tport_id(adr_len-adr_mask-2 downto adr_len-adr_mask-2):= std_logic_vector(to_unsigned(numport,1));
+--when 4|5 =>tport_id(adr_len-1 downto adr_len-adr_mask-1):=adr_sub_net(adr_len-1 downto adr_len-adr_mask-1); 
+--tport_id(adr_len-adr_mask-2 downto adr_len-adr_mask-3):= std_logic_vector(to_unsigned(numport,2));
+--when 6|9 =>tport_id(adr_len-1 downto adr_len-adr_mask-1):=adr_sub_net(adr_len-1 downto adr_len-adr_mask-1); 
+--tport_id(adr_len-adr_mask-2 downto adr_len-adr_mask-4):= std_logic_vector(to_unsigned(numport,3));
+--
+--when others => --10 to 16
+--tport_id(adr_len-1 downto adr_len-adr_mask-1):=adr_sub_net(adr_len-1 downto adr_len-adr_mask-1) ;
+--tport_id(adr_len-adr_mask-2 downto adr_len-adr_mask-5):= std_logic_vector(to_unsigned(numport,4));
+--
+--end case;
+--  return tport_id;
+--end function;
+signal PORT_ID :std_logic_vector(adr_len-1 downto 0):=GET_PORT_ID(adr_sub_net,adr_mask,number_of_ports,port_num);
+constant n_ports_bits:natural:=count_bits(number_of_ports-1);--compte le nombre de bit par port
+constant pid_bits:natural:=count_bits(tot_ports); --donne le nombre de bits utiles dans une adresse 
 begin
 -- instantiation du FIFO_256
@@ -145,5 +201,5 @@
 --end if;		
 end process;			 
-rd_en_signal <= fifo_empty_signal;--not(empty_latch) ;
+rd_en_signal <= not(fifo_empty_signal);--not(empty_latch) ;
 request <= request_decoder;
 reg_grant:process (request_decoder,grant)
@@ -471,26 +527,61 @@
 		  pipeline_latch <= push_dout;
 		  elsif pipeline_latch_en = '1' and cmd_exec='1' then
-		  pipeline_latch <= cmd_data_signal;
+		  pipeline_latch <= cmd_data_signal(8*cnib-1 downto 8*(cnib-1));
 	  end if;
 	end if;
 end process;
 
+
 --latch qui memorise l'adresse de destination du packet
 
 request_latch_process : process(clk)
+variable rt:std_logic_vector(9 downto 0):=(others=>'0');--route
+variable reql:std_logic_vector(4 downto 1):=(others=>'0');--request_latch
+--variable adr_e,p:natural range 0 to 15:=0;
+
 begin
 	if rising_edge(clk) then
 		if reset_signal = '1' then
-		  request_latch <= (others => '0');
+		  reql := (others => '0');
 		  elsif request_latch_en = '1' and cmd_in_en='0' then  --si la lecture de la destination est autorisée
-		  request_latch <=fifo_out_signal(3 downto 0); --fifo_out_signal(3) & fifo_out_signal(2) & fifo_out_signal(1) & fifo_out_signal(0);
-		assert (unsigned(fifo_out_signal(3 downto 0))<number_of_ports) 
-	report "Input_port_module n° " & integer'image(port_num) & " Le port sollicité n'existe pas le NoC va être bloqué !"
-	severity failure;
-		  elsif cmd_in_en='1' and request_latch_en='1' then  --c'est une commande le port de dest est le même que le port d'entrée
+		  rt:=(others=>'0');
+		 
+		  if adr_mask=0 then
+		    reql(n_ports_bits downto 1):=fifo_out_signal(pid_bits-adr_mask-1 downto pid_bits-adr_mask-n_ports_bits);
+		    request_latch(n_ports_bits downto 1)<=fifo_out_signal(pid_bits-adr_mask-1 downto pid_bits-adr_mask-n_ports_bits);
+		    report "Route racine:";
+		  else
+		  rt(pid_bits-1 downto pid_bits-adr_mask):=fifo_out_signal(pid_bits-1 downto pid_bits-adr_mask);
+		  if rt=adr_sub_net then
+		    report "Route trouvé:" & integer'image(to_integer(unsigned(rt))) & " adr_sub_net=" & integer'image(to_integer(unsigned(adr_sub_net))) & " fifo_out_sig:=" & image(fifo_out_signal) & " sur le port " & integer'image(to_integer(unsigned(port_id))+1);
+		    reql(n_ports_bits downto 1):=fifo_out_signal(pid_bits-adr_mask-1 downto pid_bits-adr_mask-n_ports_bits);
+		    request_latch(n_ports_bits downto 1)<=fifo_out_signal(pid_bits-adr_mask-1 downto pid_bits-adr_mask-n_ports_bits);
+		   
+		  else
+			 if number_of_ports=Port_num then --si c'est un paquet descendant alors le détruire
+			     report "Input_port_module n°" & integer'image(to_integer(unsigned(port_id))) & " La route sollicité n'existe pas dans ce sous réseau le paquet va être détruit ! fifo_out_sig:=" & image(fifo_out_signal);
+			     request_latch<="0000"; --à revoir il faut empêcher le routeur de se bloquer
+			     rt_err<='1'; --il faut activer la destruction du paquet
+			 else --faire monter les données vers le ports supérieur
+				  request_latch<=std_logic_vector(to_unsigned(number_of_ports-1,4));
+				  reql:=std_logic_vector(to_unsigned(number_of_ports-1,4));
+				  rt_err<='0';
+			 end if;
+		  
+		  end if;
+		 end if;
+		  report  "fifo_out=" & image(fifo_out_signal) & " pid_bits:=" & integer'image(pid_bits) & " adr_mask:=" & integer'image(adr_mask) & " rt:=" & image(rt) & " adr_sub_net=" & image(adr_sub_net) & " reql:=" & image(reql) & " sur le port "  & integer'image(to_integer(unsigned(port_id))+1);
+	  
+		        assert (unsigned(reql)<number_of_ports-1) 
+	         report "Input_port_module n° " & integer'image(port_num) & " Le port sollicité n'est pas dans la branche !"
+	         severity warning;
+		elsif cmd_in_en='1' and request_latch_en='1' then  --c'est une commande le port de dest est le même que le port d'entrée
 		   request_latch<=Port_ID(3 downto 0);  --car les ports commencent à 0
 		end if;
-	
-	end if;
+	 	end if;
+	--request_latch<=reql;
+	route<=rt; --pour le débogage uniquement pas besoin de conserver ce paramètre en principe
+
+
 end process;
 
@@ -515,4 +606,5 @@
 									pop_state <= CmdOn;
 								end if;
+								nib<=nbyte;
 			when CmdOn => if empty_latch='1' and cmd_in_en='0' then
 								pop_state <= state0;
@@ -533,7 +625,9 @@
 										--
 										pop_state <= state1;
-										
+										fifo_out2<=fifo_out_signal;
 								--end if;
-		
+			when addhead =>
+									pop_state <= addheadn;
+			when addheadn =>  pop_state <= state1;
 			when state1 => if port_granted ='1' then --lecture de la longueur des données
 										data_counter <= fifo_out_signal;
@@ -543,20 +637,32 @@
 												readOk<='1';
 										end if;
-										pop_state <= state2;
+										pop_state <= state1n;
+										nib<=nib-1;
 										wrok<='1';
 										else
 										  wrok<='0';
 							      end if;
-										
+							     
+			when state1n =>  		if nib=1 then
+												pop_state <= state2;
+												nib<=nbyte;
+										else
+											nib<=nib-1;
+										end if;
+										wrok<='1';
+										fifo_out2<=fifo_out_signal;
 			when state2 => if port_granted='1' then 
 			               wrok<='1';
 										if fifo_empty_signal ='0'  then
-										  if rd_en_signal ='1' and unsigned(data_counter)<= 3 then
+										  if rd_en_signal ='1' and unsigned(data_counter)<= 2 then
 											data_counter <= data_counter - 1;
-											pop_state <= stpulse;
+											pop_state <= state2n;
+											nib<=nib-1;
 											ReadOk<='1';
+											pulseon<='1';
 										elsif rd_en_signal ='1' then
 										  data_counter <= data_counter - 1;
-										  pop_state <= state2;
+										  pop_state <= state2n;
+										  nib<=nib-1;
 										  ReadOk<='1';
 										else --fifo_empty_signal='1' fin prématurée de la lecture
@@ -580,4 +686,17 @@
 										data_counter <= data_counter + 1;
 									end if;
+							 
+			when state2n => if nib=1 then
+			                 if pulseon='1' then
+												pop_state <= stpulse;
+												else
+												 pop_state <= state2;
+												end if;
+												nib<=nbyte;
+										else
+											nib<=nib-1;
+										end if;
+										wrok<='1';
+										 fifo_out2<=fifo_out_signal;
 			when strecover => if fifo_empty_signal='0' and port_granted='1' then
 			             pop_state<=state2;
@@ -591,9 +710,21 @@
 			            
 			when stpulse =>	if port_granted='1' then 
-											pop_state <= state3;		--pousser la dernière donnée dehors		
+											pop_state <= state3;--stpulsen;		--pousser la dernière donnée dehors		
+											--nib<=nib-1;
 											data_counter <= data_counter - 1;
 											wrok<='1';
-									end if;
-			                 wrok<='0';
+											pulseon<='0';
+									else
+											wrok<='0';
+									end if;  
+								  
+			when stpulsen => 	wrok<='0';
+									if nib=1 then
+												pop_state <= state3;
+												nib<=nbyte;
+										else
+											nib<=nib-1;
+										end if;
+										 fifo_out2<=fifo_out_signal;
 			when state3 => 	wrok<='0';
 										data_counter <= data_counter - 1;
@@ -611,5 +742,5 @@
 
 -- actions associées à chaque etat de la fsm de mealy
-pop_fsm_action : process(pop_state, fifo_out_signal,empty_latch, rd_en_signal,readok, port_granted )
+pop_fsm_action : process(pop_state, fifo_out_signal,fifo_out2,empty_latch, rd_en_signal,readok, port_granted,nib )
   begin   
 -- code fonctionnel	
@@ -623,5 +754,5 @@
 								dat_exec<='0';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal;
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
 								
 		when CmdOn =>		dat_request_latch_en <= '0';  
@@ -633,5 +764,5 @@
 								dat_exec<='0';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal;
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
 		when WaitGrant =>	
 								dat_request_latch_en <='1'; --autoriser l'identification du port de destination
@@ -643,8 +774,9 @@
 								dat_exec<='1';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0);
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
+								--push_dout<=fifo_out_signal(Word-1 downto Word/2)  & PORT_ID(Word/2-1 downto 0);
 		when ReqPort =>	
 								dat_request_latch_en <='1'; --autoriser l'identification du port de destination
-								dat_pipeline_latch_en <= '1'; --pour le transmettre à travers le réseau
+								dat_pipeline_latch_en <= '0'; --pour le transmettre à travers le réseau
 								dat_fifo_read_signal <= '1';
 								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
@@ -653,9 +785,29 @@
 								dat_exec<='1';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0);
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
+								--push_dout<=fifo_out_signal(Word-1 downto Word/2) & PORT_ID(Word/2-1 downto 0);
+		when addhead =>	
+								dat_request_latch_en <='0'; --autoriser l'identification du port de destination
+								dat_pipeline_latch_en <= '1'; --pour le transmettre à travers le réseau
+								dat_fifo_read_signal <= '0';
+								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+								dat_data_out_pulse <= '0';     --transmettre le signal pour le dernier mot
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								dat_Err<='0';
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
 							
 		when state1 =>    dat_request_latch_en <= '0';
 								dat_pipeline_latch_en <= rd_en_signal and port_granted;   
-								dat_fifo_read_signal <= rd_en_signal and port_granted;
+								dat_fifo_read_signal <= '0';--rd_en_signal and port_granted;
+								dat_request_decoder_en <= '1';
+								dat_data_out_pulse <= '0';--port_granted;
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								dat_Err<='0';
+								push_dout<=fifo_out2(8*nib-1 downto 8*(nib-1));
+		when state1n =>    dat_request_latch_en <= '0';
+								dat_pipeline_latch_en <= '1'; -- toujours actif pour cet octet
+								dat_fifo_read_signal <= '0';
 								dat_request_decoder_en <= '1';
 								dat_data_out_pulse <= port_granted;
@@ -663,5 +815,5 @@
 								dat_exec<='1';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal;
+								push_dout<=fifo_out2(8*nib-1 downto 8*(nib-1));
 								
 	  when state2 |strecover =>    dat_request_latch_en <= '0';
@@ -669,12 +821,21 @@
 								dat_fifo_read_signal <= port_granted and readok;   
 								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
-								dat_data_out_pulse <= port_granted and wrOk and not(fifo_empty_signal);
+								dat_data_out_pulse <= port_granted and wrOk ;--and not(fifo_empty_signal);
 								dat_priority_rotation <= '0';
 								dat_exec<='1';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal;
-								
-	  when stpulse =>    dat_request_latch_en <= '0'; --pousser la dernière donnée 
-								dat_pipeline_latch_en <= '0';  --autoriser la lecture du fifo en sortie
+								push_dout<=fifo_out2(8*nib-1 downto 8*(nib-1));
+		 
+		 when state2n  =>    dat_request_latch_en <= '0';
+								dat_pipeline_latch_en <= '1';  --autoriser la lecture du fifo en sortie
+								dat_fifo_read_signal <= '0';   
+								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+								dat_data_out_pulse <= port_granted and wrOk ;--and not(fifo_empty_signal);
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								dat_Err<='0';
+								push_dout<=fifo_out2(8*nib-1 downto 8*(nib-1));						
+	  when stpulse|stpulsen =>    dat_request_latch_en <= '0'; --pousser la dernière donnée 
+								dat_pipeline_latch_en <= wrok;  --autoriser la lecture du fifo en sortie
 								dat_fifo_read_signal <='0';   
 								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
@@ -683,5 +844,6 @@
 								dat_exec<='1';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal;
+								push_dout<=fifo_out2(8*nib-1 downto 8*(nib-1));
+	
 								
 		when state3 =>    dat_request_latch_en <= '0';
@@ -693,5 +855,5 @@
 								dat_exec<='0';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal;
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
 		when stateErr =>    dat_request_latch_en <= '0';
 								dat_pipeline_latch_en <= '0';
@@ -702,5 +864,5 @@
 								dat_exec<='1';
 								dat_Err<='1';
-								push_dout<=fifo_out_signal;
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
 		when others =>    dat_request_latch_en <= '0';
 								dat_pipeline_latch_en <= '0';
@@ -711,10 +873,10 @@
 								dat_exec<='0';
 								dat_Err<='0';
-								push_dout<=fifo_out_signal;
+								push_dout<=fifo_out_signal(8*nib-1 downto 8*(nib-1));
 										
 		end case;
  end process; 
  -- traitement des commandes reçues par le switch
-fsm_cmd:process(clk,cmd_in_en)
+fsm_cmd:process(clk)
 variable timeout : natural:=0;
 variable cmdcode : natural range 0 to 255;
@@ -731,4 +893,5 @@
 				end if;
 				cmdReadOk<='0';
+				cnib<=nbyte;
 		when cmdwait => if port_granted='1' then  -- demande du port de sortie
 								
@@ -754,25 +917,55 @@
 --				end if;
 		when cmdsetdest =>
+				
 				if port_granted='1' then
+					cmdstate<=cmdsetdestn;
+					cnib<=cnib-1;
+				end if;
+				cmdReadOk<='0';
+		when cmdsetdestn =>  	if cnib=1 then
+												cmdstate<=cmdsetcount;
+												cnib<=nbyte;
+										else
+											cnib<=cnib-1;
+										end if;
+		when cmdsetcount =>
+				if port_granted='1' then
+					cmdstate<=cmdsetcountn;
+					cnib<=cnib-1;
+				else
 					cmdstate<=cmdsetcount;
 				end if;
 				cmdReadOk<='0';
-		when cmdsetcount =>
-				if port_granted='1' then
-					cmdstate<=cmdsetID;
-				else
-					cmdstate<=cmdsetdest;
-				end if;
-				cmdReadOk<='0';
+				
+		when cmdsetcountn =>  	if cnib=1 then
+												cmdstate<=cmdsetID;
+												cnib<=nbyte;
+										else
+											cnib<=cnib-1;
+										end if;
 		when cmdsetID=>
 			if port_granted='1' then
-			cmdstate <=cmdpulse;
+			cmdstate <=cmdsetIDn;
+			cnib<=cnib-1;
 			end if;
 			cmdReadOk<='0';
+		when cmdsetIDn =>  	if cnib=1 then
+												cmdstate<=cmdpulse;
+												cnib<=nbyte;
+										else
+											cnib<=cnib-1;
+										end if;
 		when cmdpulse =>
 			if port_granted='1' then
-			cmdstate <=cmdEnd;
+			cmdstate <=cmdpulsen;
+			cnib<=cnib-1;
 			end if;
 			cmdReadOk<='0';
+		when cmdpulsen => if cnib=1 then
+												cmdstate<=cmdEnd;
+												cnib<=nbyte;
+										else
+											cnib<=cnib-1;
+										end if;
 		when cmdend  =>
 			if cmd_in_en='0' then --éviter l'exécution en boucle
@@ -808,5 +1001,5 @@
 						cmd_data_out_pulse <= '0';
 						cmd_priority_rotation <= '1';                    --sans priorité
-						cmd_data_signal<=Port_ID;  
+						cmd_data_signal<=std_logic_vector(to_unsigned(tot_ports,Word-adr_len)) & Port_ID;  
 		when cmdwait =>
 						cmd_exec<='1';
@@ -816,5 +1009,5 @@
 						cmd_priority_rotation <= '0';    --avec priorité
 						cmd_request_decoder_en <= '1';   --demande d'émission
-						cmd_data_signal<=Port_ID;
+						cmd_data_signal<=std_logic_vector(to_unsigned(tot_ports,Word-adr_len)) & Port_ID;
 						cmd_data_out_pulse <= '0';					
 	when cmdsetdest  =>
@@ -827,6 +1020,17 @@
 						cmd_data_out_pulse <= '0';
 						cmd_priority_rotation <= '0';
-						cmd_data_signal<=Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
-	when cmdsetcount =>
+						cmd_data_signal<=std_logic_vector(to_unsigned(tot_ports,Word-adr_len)) & Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
+		when cmdsetdestn  =>
+						--cmd_request_decoder_en <= '1';
+						cmd_exec<='1';
+						cmd_pipeline_latch_en <='1'; --empiler dans le tampon de sortie la donnée
+						cmd_fifo_read_signal <='0';
+						cmd_request_latch_en<='0';
+						cmd_request_decoder_en <= '1';          --autoriser le decodeur à activer le dernier bit de request
+						cmd_data_out_pulse <= '1';
+						cmd_priority_rotation <= '0';
+						cmd_data_signal<=std_logic_vector(to_unsigned(tot_ports,Word-adr_len)) & Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
+
+	when cmdsetcount|cmdsetcountn=>
 								 
 						cmd_exec<='1';   
@@ -837,6 +1041,6 @@
 						cmd_data_out_pulse <= port_granted;
 						cmd_priority_rotation <= '0';
-						cmd_data_signal<=STD_LOGIC_VECTOR(to_unsigned(3,8));					
-	when cmdSetId =>
+						cmd_data_signal<=STD_LOGIC_VECTOR(to_unsigned(3,Word));					
+	when cmdSetId| cmdSetIdn=>
 						--cmd_request_decoder_en <= '1';
 						cmd_exec<='1';
@@ -847,8 +1051,8 @@
 						cmd_data_out_pulse <= port_granted;
 						cmd_priority_rotation <= '0';
-						cmd_data_signal<=Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
+						cmd_data_signal<=std_logic_vector(to_unsigned(tot_ports,Word-adr_len)) & Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
 											
 	when cmdpulse =>	cmd_exec<='1';
-						cmd_pipeline_latch_en <='0';
+						cmd_pipeline_latch_en <='1';
 						cmd_fifo_read_signal <='0';
 						cmd_request_latch_en<='0';
@@ -856,6 +1060,15 @@
 						cmd_data_out_pulse <= '1';--port_granted;     --s'assurer que la dernière donnée est bien lue
 						cmd_priority_rotation <= '0';
+						cmd_data_signal<=std_logic_vector(to_unsigned(tot_ports,Word-adr_len)) & Port_ID; 
+						
+	when cmdpulsen  =>	cmd_exec<='1';
+						cmd_pipeline_latch_en <='0';
+						cmd_fifo_read_signal <='0';
+						cmd_request_latch_en<='0';
+						cmd_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+						cmd_data_out_pulse <= '0';--port_granted;     --s'assurer que la dernière donnée est bien lue
+						cmd_priority_rotation <= '0';
 								--cmd_data_signal<=Port_ID ;
-						cmd_data_signal<=Port_ID; 
+						cmd_data_signal<=std_logic_vector(to_unsigned(tot_ports,Word-adr_len)) & Port_ID; 
 						
 	when cmdend =>
Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/OUTPUT_PORT_MODULE.vhd
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/OUTPUT_PORT_MODULE.vhd	(revision 101)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/OUTPUT_PORT_MODULE.vhd	(revision 139)
@@ -19,5 +19,8 @@
 -- Additional Comments: Ajout d'un délai pour ignorer les paquets qui sont là depuis
 -- longtemps
---
+--Revision: Mai-02-2014
+-- Revision 0.01 - File 
+-- Additional Comments: Passage à la version 16 bits
+-- longtemps
 ----------------------------------------------------------------------------------
 library IEEE;
@@ -34,5 +37,7 @@
 
 entity OUTPUT_PORT_MODULE is
-    Port ( data_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+	generic(	nbyte : positive:=2); -- le nombre de Byte dans chaque mot du port par défaut 2
+  
+    Port ( data_in : in  STD_LOGIC_VECTOR (7 downto 0);
            reset : in  STD_LOGIC;
            clk : in  STD_LOGIC;
@@ -60,15 +65,18 @@
 type typ_outfsm is (Idle,waiting,dropping,reading);
 type typ_receiv is (r_wait,r_head,r_len,r_glen,r_data,r_pulse,r_end);
-
+type typ_store is (idle,accu,transf);
 signal EtRec : typ_receiv;
+signal Et_store,next_et_store: typ_store;
 signal Et_out_fsm : typ_outfsm;
-signal fifo_empty : std_logic;	
+signal fifo_empty ,fifo_wr: std_logic:='0';	
 signal sw : std_logic:='0'; -- permet de positionner le mux sur les signaux internes
 signal tlimit : natural:=0; --permet de compter les impulsions de temps
 signal n : natural:=0; --utiliser pour la mae du tampon de sortie
+signal nib : natural:=nbyte; --nombre de byte à transférer
 signal rcv_start :  std_logic; --début de la réception
 signal  rcv_ack : std_logic;   -- acquittement de la réception
 signal  rcv_comp :  std_logic; -- fin de la réception
 signal   spop,pop,rd_en,dat_avail :  std_logic:='0';
+signal fifo_in :std_logic_vector(Word-1 downto 0); --le tampon de données d'entrée
 signal  mem,fifo_out :  std_logic_vector(Word-1 downto 0); --variable tampon sans intérêt réel
 begin
@@ -77,15 +85,81 @@
 		port map (
 			clk => clk,
-			din => data_in,
+			din => fifo_in,
 			rd_en => rd_en,
 			srst => reset,
-			wr_en => wr_en,
+			wr_en => fifo_wr,
 			dout => fifo_out,
 			empty => fifo_empty,
 			full => fifo_full);
-			
+--sync_store_state:process (clk)
+--begin
+--if rising_edge(clk) then
+--		if reset='1' then
+--			et_store<=idle;
+--		else
+--			et_store<=next_et_store;
+--		end if;
+--
+--end if;
+--end process sync_store_state;			
+next_store_state:process (clk)
+begin
+if rising_edge(clk) then
+case et_store is
+when idle =>
+if wr_en='1' then
+et_store<=transf;
+nib<=nib-1;
+else
+ nib<=nbyte; 
+end if;
+
+
+when accu =>
+		
+		if nib=1 then
+		  et_store<=transf;
+		  
+		  nib<=nbyte;
+		else
+		 nib<=nib-1; 
+		end if;
+
+when transf =>
+	--next_et_store<=idle;	
+	if wr_en='1' then
+	  if nib=1 then 
+	    nib<=nbyte;
+	   else
+    	 nib<=nib-1;
+	  end if; 
+	 et_store<=accu;
+	else
+	 nib<=nbyte;
+	 et_store<=idle;
+	end if;
+end case ;
+
+end if;
+end process next_store_state;
+
+val_store_state:process (et_store,nib,data_in,wr_en)
+begin
+--case et_store is
+--when transf =>fifo_wr<='1';
+--when others => fifo_wr<='0';
+--end case;
+if nib=1 then
+  fifo_wr<='1';
+else
+  fifo_wr<='0';
+end if;
+fifo_in(8*nib-1 downto 8*(nib-1))<=data_in;
+end process val_store_state;
+
 
 outport_proc : process(clk,reset,fifo_empty)
 begin
+
 if rising_edge(clk) then
 if reset='1' then
Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SCHEDULER3_3.VHD
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/SCHEDULER3_3.VHD	(revision 101)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SCHEDULER3_3.VHD	(revision 139)
@@ -30,5 +30,5 @@
 --use UNISIM.VComponents.all;
 entity Scheduler3_3 is
-    Port ( Request : in  STD_LOGIC_VECTOR (9 downto 1);
+    Port ( Req : in  STD_LOGIC_VECTOR (9 downto 1);
 		   Fifo_full : in STD_LOGIC_VECTOR (3 downto 1);
            clk : in  STD_LOGIC;
@@ -39,4 +39,5 @@
 
 architecture Behavioral of Scheduler3_3 is
+constant NB_IO:positive:=3;
 --Declaration du types
 --tableau de signaux de connexion des cellules arbitres
@@ -46,31 +47,47 @@
   PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
         Grant,East,South : out  STD_LOGIC );
-End Component;--Signaux de connexion des cellues
+End Component;
+--
+component Def_Request is
+generic (NB_IO :positive:=3);
+    Port ( Req : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+			  fifo_full : in STD_LOGIC_VECTOR (NB_IO downto 1);
+           priority_rotation : in  STD_LOGIC_VECTOR (NB_IO downto 1);
+           grant : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
+           request : out  STD_LOGIC_VECTOR (NB_IO**2 downto 1));
+end component;
+constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S
+--Signaux de connexion des cellues
 SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
 SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
 SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
 SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
-SIGNAL Signal_priority  : STD_LOGIC_VECTOR (5 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (2*NB_IO-1 DOWNTO 1);--signal pour la connection des vecteurs de priorité
 SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
- signal grant_latch : std_logic_vector(9 downto 1); 
+
  signal priority_rotation_en : std_logic; 
- signal Grant,req_grant :  std_logic_vector(9 downto 1);
+
+  signal Grant,request :  std_logic_vector(NB_IO2 downto 1):=(others=>'0');
  begin
 
 --validation de la rotation de priorité lorsque aucun port n'emet 
- req_grant<=(request and grant_latch);
- priority_rotation_en <= '1' when unsigned(priority_rotation) = 7 else 	'0'; 
+
+ --priority_rotation_en <= '1' when unsigned(priority_rotation) = 7 else 	'0'; 
+ priority_rotation_en <= '1' when   unsigned(priority_rotation) = 2**NB_IO-1 else 	'0'; 
 --latch servant qui memorise le signal grant pendant a transmission 
-grant_latch_process : process(clk)
- begin 
-  if rising_edge(clk) then 
-   if reset = '1' then 
- 		grant_latch <= (others => '0'); 
- 	 elsif priority_rotation_en = '1' then 
-	   grant_latch <= Grant; 
-   end if; 
-   end if; 
- end process; 
- port_grant <= grant_latch; 
+--cette instance permet de déterminer le vecteur request 
+--en fonction de l'état fifo_full et de la requête initiale
+inst_defreq: def_request generic map (NB_IO)
+port map (clk=>clk,
+reset=>reset,
+req=>req,
+fifo_full=>fifo_full,
+priority_rotation=>priority_rotation,
+grant=>grant,
+request=>request
+); 
+ port_grant <= grant; 
  Grant(1)  <= Signal_grant(1)(1) or Signal_grant(4)(1); --  Grant(1,1)
 Grant(2)  <= Signal_grant(2)(2) or Signal_grant(5)(2); --  Grant(1,2)
Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SCHEDULER4_4.VHD
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/SCHEDULER4_4.VHD	(revision 101)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SCHEDULER4_4.VHD	(revision 139)
@@ -49,5 +49,14 @@
         Grant,East,South : out  STD_LOGIC );
 End Component;--Signaux de connexion des cellues
-
+component Def_Request is
+generic (NB_IO :positive:=4);
+    Port ( Req : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+			  fifo_full : in STD_LOGIC_VECTOR (NB_IO downto 1);
+           priority_rotation : in  STD_LOGIC_VECTOR (NB_IO downto 1);
+           grant : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
+           request : out  STD_LOGIC_VECTOR (NB_IO**2 downto 1));
+end component;
 constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S
 
@@ -58,53 +67,64 @@
 SIGNAL Signal_priority  : STD_LOGIC_VECTOR (7 DOWNTO 1);--signal pour la connection des vecteur de priorité
 SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
- Signal Fifo_out_full :  STD_LOGIC_VECTOR (NB_IO downto 1);
- signal grant_latch : std_logic_vector(NB_IO2 downto 1); 
+-- Signal Fifo_out_full :  STD_LOGIC_VECTOR (NB_IO downto 1);
+-- signal grant_latch : std_logic_vector(NB_IO2 downto 1); 
  signal priority_rotation_en : std_logic; 
-signal Grant,request,req_grant,Grant_bak :  std_logic_vector(NB_IO2 downto 1):=(others=>'0');
- signal Mreq :  std_logic_vector(NB_IO2 downto 1):=(others=>'1');
+signal Grant,request :  std_logic_vector(NB_IO2 downto 1):=(others=>'0');
+-- signal Mreq :  std_logic_vector(NB_IO2 downto 1):=(others=>'1');
 
  begin
 
---validation de la rotation de priorité lorsque aucun port n'emet 
- req_grant<=(req and grant );
+----validation de la rotation de priorité lorsque aucun port n'emet 
+-- req_grant<=(req and grant );
  priority_rotation_en <= '1' when   unsigned(priority_rotation) = 2**NB_IO-1 else 	'0'; 
-request<=req and mreq;
---latch  qui memorise le signal grant pendant la transmission 
-grant_latch_process : process(clk)
-  begin 
-  if rising_edge(clk) then 
-   if reset = '1' then 
- 		grant_latch <= (others => '0');
- 		Fifo_out_full<=(others => '0');
- 	 elsif priority_rotation_en = '1' or unsigned(req_grant)=0 then 
-	   grant_latch <= Grant;
-	   Fifo_out_full<=fifo_full;
-  else
-    	 grant_latch <= Grant; 
-    	 Fifo_out_full<=fifo_full; 
-   end if; 
-   end if; 
-
- end process; 
- def_mreq: process(grant_latch,fifo_full)
-
-variable t:std_logic_vector(NB_IO2 downto 1):=(others=>'0');
-begin 
-    
-  for i in 0 to NB_IO2-1 loop
-    t(i+1):='0';
-    --sur le front montant de fifo_full sauver l'état Grant courant 
-    if fifo_full(i mod NB_IO+1)='1' and  fifo_out_full(i mod NB_IO+1)='0' then
-      Grant_bak(i+1)<= grant_latch(i+1);
-    elsif fifo_full(i mod NB_IO+1)='0' and  fifo_out_full(i mod NB_IO+1)='0'  then
-      Grant_bak(i+1)<='0';
-    end if;
-  for j in 0 to NB_IO-1 loop
-    t(i+1):=t(i+1) or grant_latch(j*NB_IO+1+i mod NB_IO) or fifo_out_full(i mod NB_IO+1);
-    
-  end loop;
-      mreq(i+1)<=not(t(i+1) ) or grant_latch(i+1)or grant_bak(i+1);    
-  end loop;
-end process;
+--request<=req and mreq;
+----latch  qui memorise le signal grant pendant la transmission 
+--grant_latch_process : process(clk)
+--  begin 
+--  if rising_edge(clk) then 
+--   if reset = '1' then 
+-- 		grant_latch <= (others => '0');
+-- 		Fifo_out_full<=(others => '0');
+-- 	 elsif priority_rotation_en = '1' or unsigned(req_grant)=0 then 
+--	   grant_latch <= Grant;
+--	   Fifo_out_full<=fifo_full;
+--  else
+--    	 grant_latch <= Grant; 
+--    	 Fifo_out_full<=fifo_full; 
+--   end if; 
+--   end if; 
+--
+-- end process; 
+-- def_mreq: process(grant_latch,fifo_full)
+--
+--variable t:std_logic_vector(NB_IO2 downto 1):=(others=>'0');
+--begin 
+--    
+--  for i in 0 to NB_IO2-1 loop
+--    t(i+1):='0';
+--    --sur le front montant de fifo_full sauver l'état Grant courant 
+--    if fifo_full(i mod NB_IO+1)='1' and  fifo_out_full(i mod NB_IO+1)='0' then
+--      Grant_bak(i+1)<= grant_latch(i+1);
+--    elsif fifo_full(i mod NB_IO+1)='0' and  fifo_out_full(i mod NB_IO+1)='0'  then
+--      Grant_bak(i+1)<='0';
+--    end if;
+--  for j in 0 to NB_IO-1 loop
+--    t(i+1):=t(i+1) or grant_latch(j*NB_IO+1+i mod NB_IO) or fifo_out_full(i mod NB_IO+1);
+--    
+--  end loop;
+--      mreq(i+1)<=not(t(i+1) ) or grant_latch(i+1)or grant_bak(i+1);    
+--  end loop;
+--end process;
+--cette instance permet de déterminer le vecteur request en fonction de l'état fifo_full et de la requête initiale
+inst_defreq: def_request generic map (NB_IO=>4)
+port map (clk=>clk,
+reset=>reset,
+req=>req,
+fifo_full=>fifo_full,
+priority_rotation=>priority_rotation,
+grant=>grant,
+request=>request
+);
+
  port_grant <=  grant; 
  Grant(1)  <= Signal_grant(1)(1) or Signal_grant(5)(1); --  Grant(1,1)
Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SCHEDULER5_5.VHD
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/SCHEDULER5_5.VHD	(revision 101)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SCHEDULER5_5.VHD	(revision 139)
@@ -30,5 +30,5 @@
 --use UNISIM.VComponents.all;
 entity Scheduler5_5 is
-    Port ( Request : in  STD_LOGIC_VECTOR (25 downto 1);
+    Port ( Req : in  STD_LOGIC_VECTOR (25 downto 1);
 		   Fifo_full : in STD_LOGIC_VECTOR (5 downto 1);
            clk : in  STD_LOGIC;
@@ -41,4 +41,5 @@
 --Declaration du types
 --tableau de signaux de connexion des cellules arbitres
+constant NB_IO:positive:=5;
 TYPE C_Bar_Signal_Array IS ARRAY(9 downto 1) of STD_LOGIC_VECTOR(5 downto 1);
 -- declaration du composant cellule d'arbitrage
@@ -47,4 +48,15 @@
         Grant,East,South : out  STD_LOGIC );
 End Component;--Signaux de connexion des cellues
+component Def_Request is
+generic (NB_IO :positive:=5);
+    Port ( Req : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+			  fifo_full : in STD_LOGIC_VECTOR (NB_IO downto 1);
+           priority_rotation : in  STD_LOGIC_VECTOR (NB_IO downto 1);
+           grant : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
+           request : out  STD_LOGIC_VECTOR (NB_IO**2 downto 1));
+end component;
+constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S
 SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
 SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
@@ -53,24 +65,29 @@
 SIGNAL Signal_priority  : STD_LOGIC_VECTOR (9 DOWNTO 1);--signal pour la connection des vecteur de priorité
 SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
- signal grant_latch : std_logic_vector(25 downto 1); 
+ --signal grant_latch : std_logic_vector(25 downto 1); 
  signal priority_rotation_en : std_logic; 
- signal Grant ,req_grant:  std_logic_vector(25 downto 1);
+ --signal Grant ,req_grant:  std_logic_vector(25 downto 1);
+ signal Grant,request :  std_logic_vector(NB_IO2 downto 1):=(others=>'0');
  begin
 
 --validation de la rotation de priorité lorsque aucun port n'emet 
-  req_grant<=(request and grant_latch);
- priority_rotation_en <= '1' when   unsigned(req_grant) = 0 or unsigned(priority_rotation) = 31 else 	'0'; 
+ -- req_grant<=(request and grant_latch);
+  priority_rotation_en <= '1' when   unsigned(priority_rotation) = 2**NB_IO-1 else 	'0'; 
+ --priority_rotation_en <= '1' when   unsigned(req_grant) = 0 or unsigned(priority_rotation) = 31 else 	'0'; 
 --latch servant qui memorise le signal grant pendant a transmission 
-grant_latch_process : process(clk)
- begin 
-  if rising_edge(clk) then 
-   if reset = '1' then 
- 		grant_latch <= (others => '0'); 
- 	 elsif priority_rotation_en = '1' then 
-	   grant_latch <= Grant; 
-   end if; 
-   end if; 
- end process; 
- port_grant <= grant_latch; 
+--cette instance permet de déterminer le vecteur request 
+--en fonction de l'état fifo_full et de la requête initiale
+inst_defreq: def_request generic map (NB_IO)
+port map (clk=>clk,
+reset=>reset,
+req=>req,
+fifo_full=>fifo_full,
+priority_rotation=>priority_rotation,
+grant=>grant,
+request=>request
+);
+
+ port_grant <=  grant;
+ --port_grant <= grant_latch; 
  Grant(1)  <= Signal_grant(1)(1) or Signal_grant(6)(1); --  Grant(1,1)
 Grant(2)  <= Signal_grant(2)(2) or Signal_grant(7)(2); --  Grant(1,2)
Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SCHEDULER9_9.VHD
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/SCHEDULER9_9.VHD	(revision 101)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SCHEDULER9_9.VHD	(revision 139)
@@ -30,5 +30,5 @@
 --use UNISIM.VComponents.all;
 entity Scheduler9_9 is
-    Port ( Request : in  STD_LOGIC_VECTOR (81 downto 1);
+    Port ( Req : in  STD_LOGIC_VECTOR (81 downto 1);
 		   Fifo_full : in STD_LOGIC_VECTOR (9 downto 1);
            clk : in  STD_LOGIC;
@@ -39,12 +39,27 @@
 
 architecture Behavioral of Scheduler9_9 is
+ --déclaration de constantes 
+Constant NB_IO : positive:=9; --le nombre de ports d'entrée/sortie
 --Declaration du types
 --tableau de signaux de connexion des cellules arbitres
-TYPE C_Bar_Signal_Array IS ARRAY(17 downto 1) of STD_LOGIC_VECTOR(9 downto 1);
+TYPE C_Bar_Signal_Array IS ARRAY(NB_IO*2-1 downto 1) of STD_LOGIC_VECTOR(NB_IO downto 1);
 -- declaration du composant cellule d'arbitrage
 Component Arbiter 
   PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
         Grant,East,South : out  STD_LOGIC );
-End Component;--Signaux de connexion des cellues
+End Component;
+component Def_Request is
+generic (NB_IO :positive:=9);
+    Port ( Req : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+			  fifo_full : in STD_LOGIC_VECTOR (NB_IO downto 1);
+           priority_rotation : in  STD_LOGIC_VECTOR (NB_IO downto 1);
+           grant : in  STD_LOGIC_VECTOR (NB_IO**2 downto 1);
+           request : out  STD_LOGIC_VECTOR (NB_IO**2 downto 1));
+end component;
+constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S
+
+--Signaux de connexion des cellues
 SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
 SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
@@ -53,23 +68,24 @@
 SIGNAL Signal_priority  : STD_LOGIC_VECTOR (17 DOWNTO 1);--signal pour la connection des vecteur de priorité
 SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
- signal grant_latch : std_logic_vector(81 downto 1); 
+
  signal priority_rotation_en : std_logic; 
- signal Grant :  std_logic_vector(81 downto 1);
+signal Grant,request :  std_logic_vector(NB_IO2 downto 1):=(others=>'0');
  begin
 
 --validation de la rotation de priorité lorsque aucun port n'emet 
- priority_rotation_en <= '1' when unsigned(priority_rotation) = 511 else 	'0'; 
---latch servant qui memorise le signal grant pendant a transmission 
-grant_latch_process : process(clk)
- begin 
-  if rising_edge(clk) then 
-   if reset = '1' then 
- 		grant_latch <= (others => '0'); 
- 	 elsif priority_rotation_en = '1' then 
-	   grant_latch <= Grant; 
-   end if; 
-   end if; 
- end process; 
- port_grant <= Grant and grant_latch; 
+-- priority_rotation_en <= '1' when unsigned(priority_rotation) = 511 else 	'0';tation) = 511 else 	'0'; 
+ priority_rotation_en <= '1' when   unsigned(priority_rotation) = 2**NB_IO-1 else 	'0'; 
+--evaluation du signal request
+inst_defreq: def_request generic map (NB_IO=>9)
+port map (clk=>clk,
+reset=>reset,
+req=>req,
+fifo_full=>fifo_full,
+priority_rotation=>priority_rotation,
+grant=>grant,
+request=>request
+);
+
+ port_grant <=  grant; 
  Grant(1)  <= Signal_grant(1)(1) or Signal_grant(10)(1); --  Grant(1,1)
 Grant(2)  <= Signal_grant(2)(2) or Signal_grant(11)(2); --  Grant(1,2)
Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SWITCH_GEN.vhd
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/SWITCH_GEN.vhd	(revision 101)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/SWITCH_GEN.vhd	(revision 139)
@@ -14,5 +14,5 @@
 -- nécessaire à l'implémentation  du switch de la dimension voulue
 -- Dependencies: 
---
+-- Modifié le 28/04/1975
 -- Revision: 
 -- Revision 0.01 - File Created
@@ -32,20 +32,23 @@
 entity SWITCH_GEN is 
  --type portio is array(positive range) of std_logic_vector (7 downto 0);    
- generic(number_of_ports : positive := 8);
+ generic(n_ports : positive := 8;-- :nombre de ports E/S du NoC 2 à 16
+        tot_ports: positive :=16; -- nombre total de ports
+	 NET_ADR :std_logic_vector(9 downto 0):="0000000000";
+	 NET_MASK:natural:=0); -- Nombre de bits à un du masque en partant de la gauche
      port(
 	        -- ports d'entree
-           Port_in : in typ_portIO(1 to number_of_ports) ;
+           Port_in : in typ_portIO(1 to n_ports) ;
 
 			 
 			  -- port de sortie
-			  Port_out : out  typ_portIO(1 to number_of_ports);
+			  Port_out : out  typ_portIO(1 to n_ports);
 
 			  -- signaux de controle
-			  data_in_en : in std_logic_vector(number_of_ports downto 1);
-			  cmd_in_en :  in std_logic_vector(number_of_ports downto 1);
-			  data_out_en : in std_logic_vector(number_of_ports downto 1);
-			  fifo_in_full : out std_logic_vector(number_of_ports downto 1);
-			  fifo_in_empty : out std_logic_vector(number_of_ports downto 1);
-			  data_available : out std_logic_vector(number_of_ports downto 1);
+			  data_in_en : in std_logic_vector(n_ports downto 1);
+			  cmd_in_en :  in std_logic_vector(n_ports downto 1);
+			  data_out_en : in std_logic_vector(n_ports downto 1);
+			  fifo_in_full : out std_logic_vector(n_ports downto 1);
+			  fifo_in_empty : out std_logic_vector(n_ports downto 1);
+			  data_available : out std_logic_vector(n_ports downto 1);
 			  clk       : in   STD_LOGIC;
 			  reset     : in   STD_LOGIC);
@@ -58,16 +61,23 @@
 COMPONENT INPUT_PORT_MODULE
   generic(number_of_ports : positive := 8;
-			Port_num: natural);
-    Port ( data_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			Port_num: natural;
+			adr_mask : natural := NET_MASK;--le nombre de '1' en partant le la gauche de l'adresse
+			adr_len: positive:=NET_ADR'length; --la taille en bit de l'adresse 10 bits --> 1024 hotes
+			tot_ports: positive :=tot_ports; --Nomnre de ports total du réseau
+			adr_sub_net : std_logic_vector(9 downto 0) := NET_ADR;--l'adresse du sous-réseau
+      nbyte : positive:=2 -- le nombre de Byte dans chaque mot du port par défaut 2
+			
+			);
+    Port ( data_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
            data_in_en : in  STD_LOGIC;
 			  cmd_in_en : in  STD_LOGIC;
            reset : in  STD_LOGIC;
 			  clk   : in  STD_LOGIC;
-			  request : out  STD_LOGIC_VECTOR (number_of_ports downto 1);
-           grant : in  STD_LOGIC_VECTOR (number_of_ports  downto 1);			  
+			  request : out  STD_LOGIC_VECTOR (n_ports downto 1);
+           grant : in  STD_LOGIC_VECTOR (n_ports  downto 1);			  
            fifo_full : out  STD_LOGIC;
 			  fifo_empty : out  STD_LOGIC;
 			  priority_rotation : out std_logic;
-           data_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           data_out : out  STD_LOGIC_VECTOR (7 downto 0); -- le crossbar est fixé à 8 bits
 			  data_out_pulse : out std_logic);
 END COMPONENT;
@@ -77,10 +87,10 @@
 COMPONENT OUTPUT_PORT_MODULE
 	PORT(
-		data_in : IN std_logic_vector(7 downto 0);
+		data_in : IN std_logic_vector(7 downto 0); -- le crossbar est fixé à 8 bits
 		reset : IN std_logic;
 		clk : IN std_logic;
 		wr_en : IN std_logic;
 		rd_out_en : IN std_logic;          
-		data_out : OUT std_logic_vector(7 downto 0);
+		data_out : OUT std_logic_vector(Word-1 downto 0);
 		fifo_full : OUT std_logic;
 		data_avalaible : OUT std_logic
@@ -185,20 +195,20 @@
 --declaration des signaux de connection entre les modules du switch
 
-Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
-Signal grant_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
-Signal priority_rotation_signal : STD_LOGIC_VECTOR(number_of_ports downto 1);
-signal fifo_out_full_signal : std_logic_vector(number_of_ports downto 1);
-
-signal crossbar_in_port :  Typ_PortIO(1 to number_of_ports);
-
-
-
-signal crossbar_out_port  :  Typ_PortIO(1 to number_of_ports);
-
-
-signal crossbar_in_pulse  : std_logic_vector(number_of_ports downto 1);
-
-
-signal crossbar_out_pulse  : std_logic_vector(number_of_ports downto 1);
+Signal Request_signal : STD_LOGIC_VECTOR(n_ports*n_ports downto 1);
+Signal grant_signal : STD_LOGIC_VECTOR(n_ports*n_ports downto 1);
+Signal priority_rotation_signal : STD_LOGIC_VECTOR(n_ports downto 1);
+signal fifo_out_full_signal : std_logic_vector(n_ports downto 1);
+
+signal crossbar_in_port :  Typ_PortIO8(1 to n_ports);
+
+
+
+signal crossbar_out_port  :  Typ_PortIO8(1 to n_ports);
+
+
+signal crossbar_in_pulse  : std_logic_vector(n_ports downto 1);
+
+
+signal crossbar_out_pulse  : std_logic_vector(n_ports downto 1);
 
 
@@ -208,8 +218,13 @@
 -- le circuit genere depend du parametre generique nombre de ports
 -- switch 2 ports
-switch2x2 : if number_of_ports = 2 generate
+switch2x2 : if n_ports = 2 generate
 
 PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
-GENERIC MAP(number_of_ports =>2,Port_num=>1)
+GENERIC MAP(number_of_ports =>2,Port_num=>1,
+adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
+			adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
+			tot_ports=>tot_ports, --Nomnre de ports total du réseau
+			adr_sub_net => NET_ADR,--l'adresse du sous-réseau
+      nbyte =>WORD/8)
 PORT MAP(
    data_in => Port_in(1),
@@ -230,5 +245,10 @@
 
 PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
-GENERIC MAP(number_of_ports =>2,Port_num=>2)
+GENERIC MAP(number_of_ports =>2,Port_num=>2,
+adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
+			adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
+			tot_ports=>tot_ports, --Nomnre de ports total du réseau
+			adr_sub_net => NET_ADR,--l'adresse du sous-réseau
+      nbyte =>WORD/8)
 PORT MAP(
    data_in => Port_in(2),
@@ -252,8 +272,13 @@
 
 -- switch 3 ports
-switch3x3 : if number_of_ports = 3 generate
+switch3x3 : if n_ports = 3 generate
 
 PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
-GENERIC MAP(number_of_ports =>3,Port_num=>1)
+GENERIC MAP(number_of_ports =>3,Port_num=>1,
+adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
+			adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
+			tot_ports=>tot_ports, --Nomnre de ports total du réseau
+			adr_sub_net => NET_ADR,--l'adresse du sous-réseau
+      nbyte =>WORD/8)
 PORT MAP(
    data_in => Port_in(1),
@@ -276,5 +301,10 @@
 
 PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
-GENERIC MAP(number_of_ports =>3,Port_num=>2)
+GENERIC MAP(number_of_ports =>3,Port_num=>2,
+adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
+			adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
+			tot_ports=>tot_ports, --Nomnre de ports total du réseau
+			adr_sub_net => NET_ADR,--l'adresse du sous-réseau
+      nbyte =>WORD/8)
 PORT MAP(
    data_in => Port_in(2),
@@ -283,7 +313,7 @@
    reset => reset,
    clk =>clk,
-   grant(4) => grant_signal(4),
-   grant(5) => grant_signal(5),
-   grant(6) => grant_signal(6),
+   grant(1) => grant_signal(4),
+   grant(2) => grant_signal(5),
+   grant(3) => grant_signal(6),
    fifo_full =>fifo_in_full(2),
    priority_rotation =>  priority_rotation_signal(2),
@@ -291,11 +321,16 @@
    data_out =>crossbar_in_port(2),
    data_out_pulse =>crossbar_in_pulse(2),
-   request(4) =>request_signal(4),
-   request(5) =>request_signal(5),
-   request(6) =>request_signal(6)
+   request(1) =>request_signal(4),
+   request(2) =>request_signal(5),
+   request(3) =>request_signal(6)
 );
 
 PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
-GENERIC MAP(number_of_ports =>3,Port_num=>3)
+GENERIC MAP(number_of_ports =>3,Port_num=>3,
+adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
+			adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
+			tot_ports=>tot_ports, --Nomnre de ports total du réseau
+			adr_sub_net => NET_ADR,--l'adresse du sous-réseau
+      nbyte =>WORD/8)
 PORT MAP(
    data_in => Port_in(3),
@@ -304,7 +339,7 @@
    reset => reset,
    clk =>clk,
-   grant(7) => grant_signal(7),
-   grant(8) => grant_signal(8),
-   grant(9) => grant_signal(9),
+   grant(1) => grant_signal(7),
+   grant(2) => grant_signal(8),
+   grant(3) => grant_signal(9),
    fifo_full =>fifo_in_full(3),
    priority_rotation =>  priority_rotation_signal(3),
@@ -312,7 +347,7 @@
    data_out =>crossbar_in_port(3),
    data_out_pulse =>crossbar_in_pulse(3),
-   request(7) =>request_signal(7),
-   request(8) =>request_signal(8),
-   request(9) =>request_signal(9)
+   request(1) =>request_signal(7),
+   request(2) =>request_signal(8),
+   request(3) =>request_signal(9)
 );
 
@@ -321,13 +356,18 @@
 
 -- switch 4 à 7 ports
-switch4x4_7x7 : if number_of_ports >= 4 and number_of_ports <=7 generate
-
-switch_4x4_7x7:for i in 1 to number_of_ports generate
-
-constant j: natural:=number_of_ports*(i-1);
+switch4x4_7x7 : if n_ports >= 4 and n_ports <=7 generate
+
+switch_4x4_7x7:for i in 1 to n_ports generate
+
+constant j: natural:=n_ports*(i-1);
 begin
---j=number_of_ports*(i-1);
+--j=n_ports*(i-1);
 PORTx4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
-GENERIC MAP(number_of_ports =>number_of_ports,Port_num=>i)
+GENERIC MAP(number_of_ports =>n_ports,Port_num=>i,
+adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
+			adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
+			tot_ports=>tot_ports, --Nomnre de ports total du réseau
+			adr_sub_net => NET_ADR,--l'adresse du sous-réseau
+      nbyte =>WORD/8)
 PORT MAP(
    data_in => Port_in(i),
@@ -336,5 +376,5 @@
    reset => reset,
    clk =>clk,
-	grant =>grant_signal(j+NUMBER_OF_PORTS downto j+1),
+	grant =>grant_signal(j+n_ports downto j+1),
  
    fifo_full =>fifo_in_full(i),
@@ -343,5 +383,5 @@
    data_out =>crossbar_in_port(i),
    data_out_pulse =>crossbar_in_pulse(i),
-	request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
+	request =>request_signal(j+n_ports downto j+1)
    
 );
@@ -351,8 +391,8 @@
 
 ---- switch 5 ports
---switch5x5 : if number_of_ports = 5 generate
+--switch5x5 : if n_ports = 5 generate
 --
 --PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
---GENERIC MAP(number_of_ports =>5)
+--GENERIC MAP(n_ports =>5)
 --PORT MAP(
 --   data_in => Port_in(1),
@@ -378,5 +418,5 @@
 --
 --PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
---GENERIC MAP(number_of_ports =>5)
+--GENERIC MAP(n_ports =>5)
 --PORT MAP(
 --   data_in => Port_in(2),
@@ -402,5 +442,5 @@
 --
 --PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
---GENERIC MAP(number_of_ports =>5)
+--GENERIC MAP(n_ports =>5)
 --PORT MAP(
 --   data_in => Port_in(3),
@@ -426,5 +466,5 @@
 --
 --PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
---GENERIC MAP(number_of_ports =>5)
+--GENERIC MAP(n_ports =>5)
 --PORT MAP(
 --   data_in => Port_in(4),
@@ -450,5 +490,5 @@
 --
 --PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
---GENERIC MAP(number_of_ports =>5)
+--GENERIC MAP(n_ports =>5)
 --PORT MAP(
 --   data_in => Port_in(5),
@@ -477,8 +517,8 @@
 --
 ---- switch 6 ports
---switch6x6 : if number_of_ports = 6 generate
+--switch6x6 : if n_ports = 6 generate
 --
 --PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
---GENERIC MAP(number_of_ports =>6)
+--GENERIC MAP(n_ports =>6)
 --PORT MAP(
 --   data_in => Port_in(1),
@@ -845,11 +885,16 @@
 
 -- switch 8 ports
-switch8x8 : if number_of_ports = 8 generate
-switch_8x8:for i in 1 to number_of_ports generate
-constant j: natural:=number_of_ports*(i-1);
+switch8x8 : if n_ports = 8 generate
+switch_8x8:for i in 1 to n_ports generate
+constant j: natural:=n_ports*(i-1);
 begin
 --j<=number_of_ports*(i-1);
 PORTx8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
-GENERIC MAP(number_of_ports =>8,Port_num=>i)
+GENERIC MAP(number_of_ports =>8,Port_num=>i,
+adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
+			adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
+			tot_ports=>tot_ports, --Nomnre de ports total du réseau
+			adr_sub_net => NET_ADR,--l'adresse du sous-réseau
+      nbyte =>WORD/8)
 PORT MAP(
    data_in => Port_in(i),
@@ -858,5 +903,5 @@
    reset => reset,
    clk =>clk,
-	grant =>grant_signal(j+NUMBER_OF_PORTS downto j+1),
+	grant =>grant_signal(j+n_ports downto j+1),
    fifo_full =>fifo_in_full(i),
    priority_rotation =>  priority_rotation_signal(i),
@@ -865,5 +910,5 @@
    data_out_pulse =>crossbar_in_pulse(i),
 
-	request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
+	request =>request_signal(j+n_ports downto j+1)
 );
 end generate switch_8x8;
@@ -871,13 +916,18 @@
 
 -- switch 9 ports
-switch9x9_to_15 : if (number_of_ports >= 9)and (number_of_ports <= 15) generate
-
-switch_9x9_to_15:for i in 1 to number_of_ports generate
-
-constant j: natural:=number_of_ports*(i-1);
+switch9x9_to_15 : if (n_ports >= 9)and (n_ports <= 15) generate
+
+switch_9x9_to_15:for i in 1 to n_ports generate
+
+constant j: natural:=n_ports*(i-1);
 begin
 
 PORTx9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
-GENERIC MAP(number_of_ports =>NUMBER_OF_PORTS,Port_num=>i)
+GENERIC MAP(number_of_ports =>n_ports,Port_num=>i,
+adr_mask => NET_MASK,--le nombre de '1' en partant le la gauche de l'adresse
+			adr_len=>NET_ADR'length, --la taille en bit de l'adresse 10 bits --> 1024 hotes
+			tot_ports=>tot_ports, --Nomnre de ports total du réseau
+			adr_sub_net => NET_ADR,--l'adresse du sous-réseau
+      nbyte =>WORD/8)
 PORT MAP(
    data_in => Port_in(i),
@@ -886,5 +936,5 @@
    reset => reset,
    clk =>clk,
-   grant => grant_signal(j+NUMBER_OF_PORTS downto j+1),
+   grant => grant_signal(j+n_ports downto j+1),
    fifo_full =>fifo_in_full(i),
    priority_rotation =>  priority_rotation_signal(i),
@@ -893,5 +943,5 @@
    data_out_pulse =>crossbar_in_pulse(i),
 
-	request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
+	request =>request_signal(j+n_ports downto j+1)
 );
 end generate switch_9x9_to_15;
@@ -3897,7 +3947,7 @@
 
 -- switch 16 ports
-switch16x16 : if number_of_ports = 16 generate
-switch_16x16 :for i in 1 to number_of_ports generate
-Constant j : natural:=number_of_ports*(i-1);
+switch16x16 : if n_ports = 16 generate
+switch_16x16 :for i in 1 to n_ports generate
+Constant j : natural:=n_ports*(i-1);
 begin
 --j<=number_of_ports*(i-1);
@@ -4644,5 +4694,5 @@
 -- le circuit genere depend du parametre generique nombre de ports
 -- switch 2 ports
-port_out_switch2x2 : if number_of_ports = 2 generate
+port_out_switch2x2 : if n_ports = 2 generate
 
 PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -4674,5 +4724,5 @@
 
 -- switch 3 ports
-port_out_switch3x3 : if number_of_ports = 3 generate
+port_out_switch3x3 : if n_ports = 3 generate
 
 PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -4716,5 +4766,5 @@
 
 -- switch 4 ports
-port_out_switch4x4 : if number_of_ports = 4 generate
+port_out_switch4x4 : if n_ports = 4 generate
 
 PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -4770,5 +4820,5 @@
 
 -- switch 5 ports
-port_out_switch5x5 : if number_of_ports = 5 generate
+port_out_switch5x5 : if n_ports = 5 generate
 
 PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -4836,5 +4886,5 @@
 
 -- switch 6 ports
-port_out_switch6x6 : if number_of_ports = 6 generate
+port_out_switch6x6 : if n_ports = 6 generate
 
 PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -4914,5 +4964,5 @@
 
 -- switch 7 ports
-port_out_switch7x7 : if number_of_ports = 7 generate
+port_out_switch7x7 : if n_ports = 7 generate
 
 PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -5004,5 +5054,5 @@
 
 -- switch 8 ports
-port_out_switch8x8 : if number_of_ports = 8 generate
+port_out_switch8x8 : if n_ports = 8 generate
 
 PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -5106,5 +5156,5 @@
 
 -- switch 9 ports
-port_out_switch9x9 : if number_of_ports = 9 generate
+port_out_switch9x9 : if n_ports = 9 generate
 
 PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -5220,5 +5270,5 @@
 
 -- switch 10 ports
-port_out_switch10x10 : if number_of_ports = 10 generate
+port_out_switch10x10 : if n_ports = 10 generate
 
 PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -5346,5 +5396,5 @@
 
 -- switch 11 ports
-port_out_switch11x11 : if number_of_ports = 11 generate
+port_out_switch11x11 : if n_ports = 11 generate
 
 PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -5484,5 +5534,5 @@
 
 -- switch 12 ports
-port_out_switch12x12 : if number_of_ports = 12 generate
+port_out_switch12x12 : if n_ports = 12 generate
 
 PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -5634,5 +5684,5 @@
 
 -- switch 13 ports
-port_out_switch13x13 : if number_of_ports = 13 generate
+port_out_switch13x13 : if n_ports = 13 generate
 
 PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -5796,5 +5846,5 @@
 
 -- switch 14 ports
-port_out_switch14x14 : if number_of_ports = 14 generate
+port_out_switch14x14 : if n_ports = 14 generate
 
 PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -5970,5 +6020,5 @@
 
 -- switch 15 ports
-port_out_switch15x15 : if number_of_ports = 15 generate
+port_out_switch15x15 : if n_ports = 15 generate
 
 PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -6156,6 +6206,6 @@
 
 -- switch 16 ports
-port_out_switch16x16 : if number_of_ports = 16 generate
-port_out_switch_16x16:for i in 1 to number_of_ports generate
+port_out_switch16x16 : if n_ports = 16 generate
+port_out_switch_16x16:for i in 1 to n_ports generate
   begin
   PORTx16_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
@@ -6177,5 +6227,5 @@
 -- le circuit genere depend du parametre generique nombre de ports
 -- switch 2 ports
-crossbar_switch2x2 : if number_of_ports = 2 generate
+crossbar_switch2x2 : if n_ports = 2 generate
 
 Switch_Crossbar2_2: Crossbar 
@@ -6225,5 +6275,5 @@
 
 -- switch 3 ports
-crossbar_switch3x3 : if number_of_ports = 3 generate
+crossbar_switch3x3 : if n_ports = 3 generate
 
 Switch_Crossbar3_3: Crossbar 
@@ -6275,5 +6325,5 @@
 
 -- switch 4 ports
-crossbar_switch4x4 : if number_of_ports = 4 generate
+crossbar_switch4x4 : if n_ports = 4 generate
 
 Switch_Crossbar4_4: Crossbar 
@@ -6327,5 +6377,5 @@
 
 -- switch 5 ports
-crossbar_switch5x5 : if number_of_ports = 5 generate
+crossbar_switch5x5 : if n_ports = 5 generate
 
 Switch_Crossbar5_5: Crossbar 
@@ -6381,5 +6431,5 @@
 
 -- switch 6 ports
-crossbar_switch6x6 : if number_of_ports = 6 generate
+crossbar_switch6x6 : if n_ports = 6 generate
 
 Switch_Crossbar6_6: Crossbar 
@@ -6438,5 +6488,5 @@
 
 -- switch 7 ports
-crossbar_switch7x7 : if number_of_ports = 7 generate
+crossbar_switch7x7 : if n_ports = 7 generate
 
 Switch_Crossbar7_7: Crossbar 
@@ -6496,5 +6546,5 @@
 
 -- switch 8 ports
-crossbar_switch8x8 : if number_of_ports = 8 generate
+crossbar_switch8x8 : if n_ports = 8 generate
 
 Switch_Crossbar8_8: Crossbar 
@@ -6556,5 +6606,5 @@
 
 -- switch 9 ports
-crossbar_switch9x9 : if number_of_ports = 9 generate
+crossbar_switch9x9 : if n_ports = 9 generate
 
 Switch_Crossbar9_9: Crossbar 
@@ -6618,5 +6668,5 @@
 
 -- switch 10 ports
-crossbar_switch10x10 : if number_of_ports = 10 generate
+crossbar_switch10x10 : if n_ports = 10 generate
 
 Switch_Crossbar10_10: Crossbar 
@@ -6682,5 +6732,5 @@
 
 -- switch 11 ports
-crossbar_switch11x11 : if number_of_ports = 11 generate
+crossbar_switch11x11 : if n_ports = 11 generate
 
 Switch_Crossbar11_11: Crossbar 
@@ -6748,5 +6798,5 @@
 
 -- switch 12 ports
-crossbar_switch12x12 : if number_of_ports = 12 generate
+crossbar_switch12x12 : if n_ports = 12 generate
 
 Switch_Crossbar12_12: Crossbar 
@@ -6816,5 +6866,5 @@
 
 -- switch 13 ports
-crossbar_switch13x13 : if number_of_ports = 13 generate
+crossbar_switch13x13 : if n_ports = 13 generate
 
 Switch_Crossbar13_13: Crossbar 
@@ -6886,5 +6936,5 @@
 
 -- switch 14 ports
-crossbar_switch14x14 : if number_of_ports = 14 generate
+crossbar_switch14x14 : if n_ports = 14 generate
 
 Switch_Crossbar14_14: Crossbar 
@@ -6958,5 +7008,5 @@
 
 -- switch 15 ports
-crossbar_switch15x15 : if number_of_ports = 15 generate
+crossbar_switch15x15 : if n_ports = 15 generate
 
 Switch_Crossbar15_15: Crossbar 
@@ -7032,5 +7082,5 @@
 
 -- switch 16 ports
-crossbar_switch16x16 : if number_of_ports = 16 generate
+crossbar_switch16x16 : if n_ports = 16 generate
 
 Switch_Crossbar16_16: Crossbar 
@@ -7108,5 +7158,5 @@
 -- le circuit genere depend du parametre generique nombre de ports
 -- switch 2 ports
-scheduler_switch2x2 : if number_of_ports = 2 generate
+scheduler_switch2x2 : if n_ports = 2 generate
 
 Scheduler2_2: Scheduler 
@@ -7125,5 +7175,5 @@
 
 -- switch 3 ports
-scheduler_switch3x3 : if number_of_ports = 3 generate
+scheduler_switch3x3 : if n_ports = 3 generate
 
 Scheduler3_3: Scheduler 
@@ -7142,5 +7192,5 @@
 
 -- switch 4 ports
-scheduler_switch4x4 : if number_of_ports = 4 generate
+scheduler_switch4x4 : if n_ports = 4 generate
 
 Scheduler4_4: Scheduler 
@@ -7159,5 +7209,5 @@
 
 -- switch 5 ports
-scheduler_switch5x5 : if number_of_ports = 5 generate
+scheduler_switch5x5 : if n_ports = 5 generate
 
 Scheduler5_5: Scheduler 
@@ -7176,5 +7226,5 @@
 
 -- switch 6 ports
-scheduler_switch6x6 : if number_of_ports = 6 generate
+scheduler_switch6x6 : if n_ports = 6 generate
 
 Scheduler6_6: Scheduler 
@@ -7193,5 +7243,5 @@
 
 -- switch 7 ports
-scheduler_switch7x7 : if number_of_ports = 7 generate
+scheduler_switch7x7 : if n_ports = 7 generate
 
 Scheduler7_7: Scheduler 
@@ -7210,5 +7260,5 @@
 
 -- switch 8 ports
-scheduler_switch8x8 : if number_of_ports = 8 generate
+scheduler_switch8x8 : if n_ports = 8 generate
 
 Scheduler8_8: Scheduler 
@@ -7227,5 +7277,5 @@
 
 -- switch 9 ports
-scheduler_switch9x9 : if number_of_ports = 9 generate
+scheduler_switch9x9 : if n_ports = 9 generate
 
 Scheduler9_9: Scheduler 
@@ -7244,5 +7294,5 @@
 
 -- switch 10 ports
-scheduler_switch10x10 : if number_of_ports = 10 generate
+scheduler_switch10x10 : if n_ports = 10 generate
 
 Scheduler10_10: Scheduler 
@@ -7261,5 +7311,5 @@
 
 -- switch 11 ports
-scheduler_switch11x11 : if number_of_ports = 11 generate
+scheduler_switch11x11 : if n_ports = 11 generate
 
 Scheduler11_11: Scheduler 
@@ -7278,5 +7328,5 @@
 
 -- switch 12 ports
-scheduler_switch12x12 : if number_of_ports = 12 generate
+scheduler_switch12x12 : if n_ports = 12 generate
 
 Scheduler12_12: Scheduler 
@@ -7295,5 +7345,5 @@
 
 -- switch 13 ports
-scheduler_switch13x13 : if number_of_ports = 13 generate
+scheduler_switch13x13 : if n_ports = 13 generate
 
 Scheduler13_13: Scheduler 
@@ -7312,5 +7362,5 @@
 
 -- switch 14 ports
-scheduler_switch14x14 : if number_of_ports = 14 generate
+scheduler_switch14x14 : if n_ports = 14 generate
 
 Scheduler14_14: Scheduler 
@@ -7329,5 +7379,5 @@
 
 -- switch 15 ports
-scheduler_switch15x15 : if number_of_ports = 15 generate
+scheduler_switch15x15 : if n_ports = 15 generate
 
 Scheduler15_15: Scheduler 
@@ -7346,5 +7396,5 @@
 
 -- switch 16 ports
-scheduler_switch16x16 : if number_of_ports = 16 generate
+scheduler_switch16x16 : if n_ports = 16 generate
 
 Scheduler16_16: Scheduler 
Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Scheduler.vhd
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/Scheduler.vhd	(revision 101)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Scheduler.vhd	(revision 139)
@@ -61,5 +61,5 @@
 COMPONENT Scheduler3_3
    PORT(
-      Request : IN std_logic_vector(9 downto 1);
+      Req : IN std_logic_vector(9 downto 1);
       Fifo_full : IN std_logic_vector(3 downto 1);
       clk : IN std_logic;
@@ -83,5 +83,5 @@
 COMPONENT Scheduler5_5
    PORT(
-      Request : IN std_logic_vector(25 downto 1);
+      Req : IN std_logic_vector(25 downto 1);
       Fifo_full : IN std_logic_vector(5 downto 1);
       clk : IN std_logic;
@@ -94,5 +94,5 @@
 COMPONENT Scheduler6_6
    PORT(
-      Request : IN std_logic_vector(36 downto 1);
+      Req : IN std_logic_vector(36 downto 1);
       Fifo_full : IN std_logic_vector(6 downto 1);
       clk : IN std_logic;
@@ -105,5 +105,5 @@
 COMPONENT Scheduler7_7
    PORT(
-      Request : IN std_logic_vector(49 downto 1);
+      Req : IN std_logic_vector(49 downto 1);
       Fifo_full : IN std_logic_vector(7 downto 1);
       clk : IN std_logic;
@@ -127,5 +127,5 @@
 COMPONENT Scheduler9_9
    PORT(
-      Request : IN std_logic_vector(81 downto 1);
+      Req : IN std_logic_vector(81 downto 1);
       Fifo_full : IN std_logic_vector(9 downto 1);
       clk : IN std_logic;
@@ -240,5 +240,5 @@
   Inst_Scheduler3_3 : Scheduler3_3
    PORT MAP(
-     Request => Request_latch, 
+     Req => Request_latch, 
      Fifo_full => Fifo_full_latch,
      clk => clk ,
@@ -268,5 +268,5 @@
   Inst_Scheduler5_5 : Scheduler5_5
    PORT MAP(
-     Request => Request, 
+     Req => Request, 
      Fifo_full => Fifo_full,
      clk => clk ,
@@ -282,5 +282,5 @@
   Inst_Scheduler6_6 : Scheduler6_6
    PORT MAP(
-     Request => Request_latch, 
+     Req => Request_latch, 
      Fifo_full => Fifo_full_latch,
      clk => clk ,
@@ -296,5 +296,5 @@
   Inst_Scheduler7_7 : Scheduler7_7
    PORT MAP(
-     Request => Request_latch, 
+     Req => Request_latch, 
      Fifo_full => Fifo_full_latch,
      clk => clk ,
@@ -324,5 +324,5 @@
   Inst_Scheduler9_9 : Scheduler9_9
    PORT MAP(
-     Request => Request_latch, 
+     Req => Request_latch, 
      Fifo_full => Fifo_full_latch,
      clk => clk ,
Index: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Scheduler.vhd.bak
===================================================================
--- PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/Scheduler.vhd.bak	(revision 101)
+++ PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.0/NOC/Scheduler.vhd.bak	(revision 139)
@@ -61,5 +61,5 @@
 COMPONENT Scheduler3_3
    PORT(
-      Request : IN std_logic_vector(9 downto 1);
+      Req : IN std_logic_vector(9 downto 1);
       Fifo_full : IN std_logic_vector(3 downto 1);
       clk : IN std_logic;
@@ -72,5 +72,5 @@
 COMPONENT Scheduler4_4
    PORT(
-      Request : IN std_logic_vector(16 downto 1);
+      Req : IN std_logic_vector(16 downto 1);
       Fifo_full : IN std_logic_vector(4 downto 1);
       clk : IN std_logic;
@@ -83,5 +83,5 @@
 COMPONENT Scheduler5_5
    PORT(
-      Request : IN std_logic_vector(25 downto 1);
+      Req : IN std_logic_vector(25 downto 1);
       Fifo_full : IN std_logic_vector(5 downto 1);
       clk : IN std_logic;
@@ -94,5 +94,5 @@
 COMPONENT Scheduler6_6
    PORT(
-      Request : IN std_logic_vector(36 downto 1);
+      Req : IN std_logic_vector(36 downto 1);
       Fifo_full : IN std_logic_vector(6 downto 1);
       clk : IN std_logic;
@@ -105,5 +105,5 @@
 COMPONENT Scheduler7_7
    PORT(
-      Request : IN std_logic_vector(49 downto 1);
+      Req : IN std_logic_vector(49 downto 1);
       Fifo_full : IN std_logic_vector(7 downto 1);
       clk : IN std_logic;
@@ -240,5 +240,5 @@
   Inst_Scheduler3_3 : Scheduler3_3
    PORT MAP(
-     Request => Request_latch, 
+     Req => Request_latch, 
      Fifo_full => Fifo_full_latch,
      clk => clk ,
@@ -254,5 +254,5 @@
   Inst_Scheduler4_4 : Scheduler4_4
    PORT MAP(
-     Request => Request_latch, 
+     Req => Request_latch, 
      Fifo_full => Fifo_full_latch,
      clk => clk ,
@@ -268,5 +268,5 @@
   Inst_Scheduler5_5 : Scheduler5_5
    PORT MAP(
-     Request => Request, 
+     Req => Request, 
      Fifo_full => Fifo_full,
      clk => clk ,
@@ -282,5 +282,5 @@
   Inst_Scheduler6_6 : Scheduler6_6
    PORT MAP(
-     Request => Request_latch, 
+     Req => Request_latch, 
      Fifo_full => Fifo_full_latch,
      clk => clk ,
@@ -296,5 +296,5 @@
   Inst_Scheduler7_7 : Scheduler7_7
    PORT MAP(
-     Request => Request_latch, 
+     Req => Request_latch, 
      Fifo_full => Fifo_full_latch,
      clk => clk ,
