Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/CORE_MPI.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/CORE_MPI.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/CORE_MPI.vhd (revision 142) @@ -0,0 +1,1000 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM NGOUNOU +-- +-- Create Date: 05:52:25 06/21/2011 +-- Design Name: +-- Module Name: CORE_MPI - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +Library NocLib; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity CORE_MPI is + Port ( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + clkout : out std_logic; + instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + instruction_en : in STD_LOGIC; --valide l'instruction + instruction_fifo_full : out STD_LOGIC; + ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + barrier_completed : out STD_LOGIC; + packet_received : out STD_LOGIC; + packet_ack : in std_logic; + PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); --le resultat de l'exécution + ram_we : out STD_LOGIC; + ram_en : out STD_LOGIC; + ram_address_rd : out STD_LOGIC_VECTOR (15 downto 0); + ram_address_wr : out STD_LOGIC_VECTOR (15 downto 0); + ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + switch_port_in_cmd_en : out std_logic; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_in_wr_en : out STD_LOGIC; + switch_port_in_full : in STD_LOGIC; + switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_out_rd_en : out STD_LOGIC; + switch_port_in_empty : in STD_LOGIC; + switch_port_out_data_vailaible : in STD_LOGIC + ); + +end CORE_MPI; + +architecture Structural of CORE_MPI is +--déclaration des types +type Type_Noc is +record + port_in_cmd_en : std_logic; + port_out_data : STD_LOGIC_VECTOR (Word-1 downto 0); + port_in_wr_en : STD_LOGIC; + port_in_empty : STD_LOGIC; + port_in_full : STD_LOGIC; + port_in_data : STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_rd_en : STD_LOGIC; + port_out_data_available : STD_LOGIC; +end record; +-- déclaration des composants MPI + +COMPONENT FIFO_64_FWFT + PORT( + clk : IN std_logic; + din : IN std_logic_vector(Word-1 downto 0); + rd_en : IN std_logic; + srst : IN std_logic; + wr_en : IN std_logic; + dout : OUT std_logic_vector(Word-1 downto 0); + empty : OUT std_logic; + full : OUT std_logic + ); +END COMPONENT; +COMPONENT load_instr + Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + instruction_ack : out STD_LOGIC; + fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_wr :out std_logic; + fifo_full : in STD_LOGIC; + copying : out std_logic; + Ram_rd_en : out STD_LOGIC; + ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0)); +end component; +COMPONENT DMA_ARBITER + PORT( + + clk : IN std_logic; + reset : IN std_logic; + dma_rd_request : IN std_logic_vector(3 downto 0); + data_wr_in : IN std_logic_vector(Word-1 downto 0); + data_rd_out : out std_logic_vector(Word-1 downto 0); + address_rd : IN std_logic_vector(15 downto 0); + address_wr : IN std_logic_vector(15 downto 0); + + dma_wr_request : IN std_logic_vector(3 downto 0); + address_out_rd : OUT std_logic_vector(15 downto 0); + address_out_wr : OUT std_logic_vector(15 downto 0); + ram_en : OUT std_logic; + ram_we : OUT std_logic; + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + data_wr_mem : OUT std_logic_vector(Word-1 downto 0); + data_rd_mem : IN std_logic_vector(Word-1 downto 0); + dma_wr_grant : OUT std_logic_vector(3 downto 0); + dma_rd_grant : OUT std_logic_vector(3 downto 0) + ); +END COMPONENT; + +COMPONENT EX1_FSM + PORT( + clk : IN std_logic; + reset : IN std_logic; + + pid : in std_logic_vector (3 downto 0); --port id + nprocs : in std_logic_vector (3 downto 0); -- la taille du Noc + instruction : in std_logic_vector(Word-1 downto 0); + instruction_en : in std_logic; + fifo_empty : IN std_logic; + fifo_data_out : IN std_logic_vector(Word-1 downto 0); + fifo_rd_en : OUT std_logic; + fifo_src : IN STD_LOGIC; + ram_data_in : IN std_logic_vector(Word-1 downto 0); + ram_data_out : out std_logic_vector(Word-1 downto 0); + dma_rd_grant : IN std_logic; + dma_wr_grant : IN std_logic; + dma_wr_request : OUT std_logic; + dma_rd_request : OUT std_logic; + ram_address : OUT std_logic_vector(15 downto 0); + ram_rd,ram_wr : out std_logic; + Snd_Data : IN Typ_PortIO(0 to 3); + Snd_Start : IN std_logic; + Snd_Ack : OUT std_logic; + priority_rotation : OUT std_logic; + + switch_port_in_data : OUT std_logic_vector(Word-1 downto 0); + switch_port_in_wr_en : OUT std_logic; + switch_port_in_full : IN std_logic; + Result :out std_logic_vector(Word-1 downto 0); + Ready : out std_logic; + AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic -- état de la Lib + ); + END COMPONENT; + +COMPONENT EX2_FSM + PORT( + clk : IN std_logic; + reset : IN std_logic; + + instruction_en: in std_logic; + Initialized : in std_logic; + + switch_port_out_rd_en : OUT std_logic ; + switch_data_available : IN std_logic; + switch_port_out_data : IN std_logic_vector(Word-1 downto 0); + AppRank : in STD_LOGIC_VECTOR; + AppSize : in STD_LOGIC_VECTOR; + dma_wr_grant : IN std_logic; + dma_wr_request : OUT std_logic; + dma_rd_grant : IN std_logic; + dma_rd_request : OUT std_logic; + ram_address : OUT std_logic_vector(15 downto 0); + ram_rd,ram_wr : out std_logic; + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_full : IN std_logic; + Rec_Rdy : OUT std_logic; + Rec_Data : out Typ_PortIO(0 to 3); + Rec_Ack : IN std_logic; + fifo_data : OUT std_logic_vector(Word-1 downto 0); + fifo_wr_en : OUT std_logic; + --fifo_out : out std_logic_vector; + Result : out STD_LOGIC_VECTOR (Word-1 downto 0); + packet_received : OUT std_logic; + packet_ack : IN std_logic; + barrier_completed : OUT std_logic; + Ready : Out std_logic; + AppInitAck : in std_logic; + AppInitReq : out std_logic + ); + END COMPONENT; + + + COMPONENT EX3_FSM + PORT( + instruction : IN std_logic_vector(Word-1 downto 0); + clk : IN std_logic; + reset : IN std_logic; + Ismain :in std_logic; + ResOut : OUT std_logic_vector(Word-1 downto 0) + + ); + END COMPONENT; + + COMPONENT EX4_FSM + PORT( + Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); --permet de lire le FIFO + Instruction_En : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + ResultOut : out STD_LOGIC_VECTOR (Word-1 downto 0); + Result_En : out STD_LOGIC; + Ready : out STD_LOGIC; + NocSize : out STD_LOGIC_VECTOR; + AppRank : out STD_LOGIC_VECTOR; + AppSize : out STD_LOGIC_VECTOR; + IsMain : out STD_LOGIC; + I_fifo_full :in STD_LOGIC; + Snd_Ack : IN std_logic; + Rec_Rdy : IN std_logic; + Rec_Data : IN Typ_PortIO(0 to 3); + Snd_data : OUT Typ_PortIO(0 to 3); + Snd_Start : out std_logic; + Rec_Ack : OUT std_logic; + I_fifo_wr_en: out STD_LOGIC; + I_fifo_data_in :out STD_LOGIC_vector(Word-1 downto 0); + Initialized : out STD_LOGIC; + dma_wr_request : out std_logic; + dma_rd_request : out std_logic; + dma_wr_grant : in std_logic; + dma_rd_grant : in std_logic; + Ram_address : out STD_LOGIC_VECTOR (15 downto 0); --accès au stockage + Ram_wr : out STD_LOGIC; --activation de l'écriture en RAM + Ram_Data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);--données des ports + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + AppAck : in STD_LOGIC; + AppReq : in STD_LOGIC; + PortId : out STD_LOGIC_VECTOR(3 downto 0); + port_in_cmd_en : out STD_LOGIC; + port_in_wr_en : out STD_LOGIC; + port_in_empty : in STD_LOGIC; + port_in_full : in STD_LOGIC; + port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_rd_en : out STD_LOGIC; + port_out_data_available : in STD_LOGIC); + END COMPONENT; + + COMPONENT EX0_FSM + PORT( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + + Initialized : in STD_LOGIC; + Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + instruction_en: in STD_LOGIC; + + ClkRate : in STD_LOGIC_VECTOR ; + uTimeResult : out STD_LOGIC_VECTOR; + TickResult : out STD_LOGIC_VECTOR + ); + END COMPONENT; + + +COMPONENT MPI_CORE_SCHEDULER + PORT( + clk : IN std_logic; + reset : IN std_logic; + priority_rotation : IN std_logic; + instruction_fifo_empty : IN std_logic; + instruction_fifo_rd_en : OUT std_logic; + instruction_fifo_data : IN std_logic_vector(Word-1 downto 0); + instruction_available : OUT std_logic; + + get_request_fifo_empty : IN std_logic; + get_request_fifo_rd_en : OUT std_logic; + get_request_fifo_data : IN std_logic_vector(Word-1 downto 0); + + fifo_rd_en : IN std_logic; + fifo_empty : OUT std_logic; + fifo_selected : OUT std_logic; + + data_out : OUT std_logic_vector(Word-1 downto 0) + + + ); + END COMPONENT; + +-- declaration des signaux d'interconnexion entre les modules du coresignal fifo_sel: std_logic; -- indique l'un des deux fifos d'instructions qui sont prêts +signal fifo_instr : std_logic; -- une instruction est prête dans les fifos d'instruction + + +signal scheduler_fifo_empty : std_logic; +signal scheduler_data_out : std_logic_vector(Word-1 downto 0); +signal dma_arbiter_data_rd_out : std_logic_vector(Word-1 downto 0); + +signal scheduler_priority_rotation : std_logic; +signal scheduler_rd_en : std_logic; + +signal dma_data_rd,dma_data_wr : std_logic_vector(Word-1 downto 0); -- bus à 3 états +signal dma_rd_address,dma_rd_address1,dma_rd_address2 : std_logic_vector(15 downto 0); -- ces bus doivent être gérés en logique 3 états! +signal dma_rd_address3 : std_logic_vector(15 downto 0); +signal dma_wr_address1,dma_wr_address3 : std_logic_vector(15 downto 0); +signal dma_wr_address2,dma_wr_address4 : std_logic_vector(15 downto 0); +signal dma_wr_address : std_logic_vector(15 downto 0); +signal switch_port_in_data_signal : std_logic_vector(Word-1 downto 0); +signal ram_data_out_signal : std_logic_vector(Word-1 downto 0); +signal weram,rdram,ram_wev,ram_env :std_logic:='0'; + +signal i_fifo2_signal : std_logic_vector(Word-1 downto 0); +signal Ex_EN : std_logic_vector(4 downto 1):=(others=>'0'); --active les sous MAE permettant de décoder les instructions MPI +signal Res4_en:std_logic;--acquittement du réusltat du module n°4 +signal Ex4_en,Ex1_RDY,Ex2_RDY,EX3_RDY,EX4_RDY : std_logic:='0'; -- indique la fin de l'exécution de la MAE +signal ex1_ram_rd,ex2_ram_rd,ex4_ram_rd ,Exi_ram_rd: std_logic:='0' ; -- validation lecture des données en RAM +signal ex1_ram_wr,ex2_ram_wr,ex4_ram_wr,Exi_ram_wr : std_logic :='0'; -- validation écriture des données en RAM +signal Exi_busy : std_logic:='0'; +signal Ex1_Result,Ex2_Result,Ex4_result : std_logic_vector(Word-1 downto 0); +signal Instr_in : STD_LOGIC_VECTOR (Word-1 downto 0); +--================interface DMA avec les modules ====================================== +signal dma_data_in,Dma_data_in1,dma_data_in2,dma_data_in4 : std_logic_vector(Word-1 downto 0); +signal dma_data_out : std_logic_vector(Word-1 downto 0); +signal dma_rd_request :std_logic_vector(4 downto 1):=(others=>'0'); +signal dma_wr_request :std_logic_vector(4 downto 1):=(others=>'0'); +signal dma_wr_grant,dma_rd_grant:std_logic_vector(4 downto 1); +-- +--====================================================================================== +--connexion au switch + +signal Noc1,NOC2,NOC3 : Type_Noc; -- regroupement des signaux qui vont au Noc + +--================================================================ +--déclaration des signaux d'état du Core +signal IsMain,SizeSet,RankSet,Initialized,AppReq,AppAck:std_logic; +signal InitReq,InitReq1,InitReq2 :std_logic:='0'; -- demande d'initialisation +signal InitAck,IAck,Ilatch : std_logic:='0'; +signal MPISize,MyRank : std_logic_vector(3 downto 0); +signal LibState: std_logic_vector(Word-1 downto 0):=(others=>'0'); --ready,receiving,sending,spawning,rwaiting,swaiting,... +signal NocSize :std_logic_vector(3 downto 0):=(others=>'0'); +Signal PortId : std_logic_vector(3 downto 0); +Signal uClkRate : std_logic_vector(Word-1 downto 0):="00011010"; --50 Mhz +signal uTimeCount :std_logic_vector(31 downto 0):=(others=>'0'); +signal TickCount : std_logic_vector(31 downto 0):=(others=>'0'); +signal RankSize: std_logic_vector(Word-1 downto 0):=(others=>'0'); +--======================================================== +--déclaration des signaux permettant d'activer le module +signal AdrSelect : std_logic_vector(ADRLEN-1 downto 0); +--======================================================== +--signal PushOut_d,RankSize,TickUsOut:std_logic_vector; --résultat de l'execution des commandes mpi +--======================================================== +--connexion avec les FIFO instructions +signal fifo1_wr : std_logic; +signal fifo1_din : std_logic_vector (Word-1 downto 0); +signal fifo_sel : std_logic; --permet d'arbitrer la priorité de lecture entre les deux fifos +signal i_fifo1_rd_en : std_logic; +signal fifo1_full : std_logic; +signal i_fifo1_empty : std_logic; +signal i_fifo1_data_out : std_logic_vector(Word-1 downto 0); +signal i_fifo2_rd_en : std_logic; +signal i_fifo2_data_out : std_logic_vector(Word-1 downto 0); +signal i_fifo2_data_in : std_logic_vector(Word-1 downto 0); +signal i_fifo2_wr_en : std_logic; +signal i_fifo2_empty : std_logic; +signal i_fifo2_full : std_logic; +signal Ex2_i_fifo2_data_in : std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal Ex2_i_fifo2_wr_en : std_logic:='0'; +--signaux pour les données entre modules +signal Snd_Ack :std_logic; +signal Rec_Rdy : std_logic; +signal Rec_Data : Typ_PortIO(0 to 3); +signal Snd_data : Typ_PortIO(0 to 3); +signal Snd_Start : std_logic; +signal Rec_Ack : std_logic; +--signal i_fifo2_empty : std_logic; +--signal i_fifo2_full : std_logic; +signal Ex4_i_fifo2_data_in : std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal Ex4_i_fifo2_wr_en : std_logic:='0'; +--signal i_fifo2_empty : std_logic; +--signal i_fifo2_full : std_logic; +-- signaux pour la gestion des MAE +signal n,n_i :natural range 0 to 7:=0; +signal St_Ex1,St_Ex2,St_Ex4:natural range 0 to 7:=0; +signal Next_St_Ex1,Next_St_Ex2,Next_St_Ex4:natural range 0 to 7:=0; +--=========================================================== + +begin +--switch_port_in_data_signal <= ; +--switch_port_out_data_signal <= ; +-- istanciation des composants du core MPI +Instruction_Fifo1: FIFO_64_FWFT PORT MAP( + clk =>clk, + din =>fifo1_din, + rd_en => i_fifo1_rd_en, + srst => reset, + wr_en => fifo1_wr, + dout =>i_fifo1_data_out, + empty => i_fifo1_empty, + full => fifo1_full + ); + +Instruction_Fifo2: FIFO_64_FWFT PORT MAP( + clk =>clk, + din => i_fifo2_data_in , + rd_en =>i_fifo2_rd_en, + srst =>reset, + wr_en =>i_fifo2_wr_en, + dout =>i_fifo2_data_out, + empty =>i_fifo2_empty, + full => i_fifo2_full + ); +LD_instr:load_instr PORT MAP ( + + Instruction =>Instruction, + Instruction_en =>Instruction_en, + clk =>clk, + reset =>reset, + dma_rd_grant =>dma_rd_grant(3), + dma_rd_request =>dma_rd_request(3), + copying=> Exi_busy, + instruction_ack =>iack, --indique la fin de la copie d'une instruction dans le FIFO + fifo_din => fifo1_din, + fifo_wr => fifo1_wr, + fifo_full =>fifo1_full, + Ram_rd_en=> Exi_ram_rd, + ram_address_rd => dma_rd_address3, + ram_data =>dma_data_out --sortie DMA +); + +pushout(0)<=ILatch; +pushout(1)<=IsMain; +pushout(2)<=SizeSet; +pushout(3)<=Ex4_result(6); --Spawn in progress on main +pushout(4)<=Initialized; +pushout(5)<=Ex1_result(1); -- +pushout(6)<=LibState(3); --Spawned child +pushout(7)<=Ex4_result(7); --Spawn complete +MPI_CORE_EX0_FSM: EX0_FSM PORT MAP( + instruction => i_fifo1_data_out, + instruction_en=> '1', + uTimeResult => uTimeCount, + TickResult => TickCount, + Initialized => Initialized, -- indique si la l'appel à init a été concluant + ClkRate => uClkRate, + clk =>clk , + reset => reset + ); +MPI_CORE_EX1_FSM: EX1_FSM PORT MAP( + clk =>clk , + reset =>reset, + pid => MyRank, --port Id + nprocs=>MPISize, -- à revoir dans certains cas ou tous les PEs ne sont pas connectés + fifo_empty => scheduler_fifo_empty , + fifo_data_out =>scheduler_data_out, + fifo_rd_en =>scheduler_rd_en, + fifo_src =>fifo_sel, + priority_rotation => scheduler_priority_rotation, + + instruction_en=>Ex_en(1), --active le module + Instruction => Instruction, + switch_port_in_full =>Noc1.port_in_full, --ces signaux doivent être contrôlés en 3 state logic + switch_port_in_data =>Noc1.port_in_data, + switch_port_in_wr_en =>Noc1.Port_in_wr_en , + + Snd_Data =>Snd_Data, + Snd_Start =>Snd_start, + Snd_Ack =>Snd_ack, + Ram_rd => ex1_ram_rd, + Ram_wr =>ex1_ram_wr, + ram_data_in =>dma_data_out, + Ram_data_out =>dma_data_in1, + ram_address=>dma_wr_address1, + --ram_address =>dma_rd_address2, --la même adresse sert pour la lecture ou l'écriture + dma_rd_request =>dma_rd_request(1), + dma_wr_request =>dma_wr_request(1), + dma_rd_grant =>dma_rd_grant(1) , + dma_wr_grant =>dma_wr_grant(1) , + + AppInitReq => InitReq1, -- requête d'initialisation de l'application + AppInitAck =>Res4_En , -- Acquitement d'initialisation + Initialized=>Initialized, -- état de la Lib + Result => Ex1_Result, -- le résultat de l'exécution + Ready=> Ex1_Rdy + ); +instruction_fifo_full<=fifo1_full; +dma_rd_address1<=dma_wr_address1; --la même adresse sert pour la lecture ou l'écriture en RAM +Exi_sync :process(reset,clk) + +begin + if rising_edge(clk) then + if reset='1' then + St_Ex2<=0; + St_Ex1<=0; + St_Ex4<=0; + Ilatch<='0'; + n<=0; + else + St_Ex2<=Next_St_Ex2; + St_Ex1<=Next_St_Ex1; + St_Ex4<=Next_St_Ex4; + ILatch<=Iack; + n<=n_i; + end if; +end if; +End process Exi_sync; +-- détermination de l'activation des module +--scheduler_priority_rotation<=not(Ex1_rdy); +Ex1_Act:process(ST_Ex1,Initialized,reset,fifo_instr,n,InitReq,Ex4_rdy,Ex1_rdy,Ex2_rdy)--A qoui sert encore ce processus (26/10/12) ???? +variable c_cyl:natural range 0 to 15:=0; +begin + if reset='1' then + Next_St_ex1<=0; + c_cyl:=0; +else -- cette machie à état permet de distinguer les activations de Ex4 et Ex1 + Next_St_ex1<=ST_EX1; + case St_ex1 is + when 0 => if InitReq='1' and Initialized='0' then + Next_St_ex1<=1; + elsif Initialized='1' then + Next_St_ex1 <=2; + elsif fifo_instr='1' then --cas d'une instruction directe qui est présente + --if fifo_sel='0' then + Next_St_ex1 <=2; + --end if; + end if; + + when 1 => if Ex4_Rdy='1' then + Next_St_ex1<=4; + end if; + when 2 => if Ex1_rdy='0' then --ex1 est libre et actif + Next_St_ex1<=3; + end if; + + when 3 => if Ex1_rdy='1' and Initialized='0'then --ex1 est occupé et actif + Next_St_ex1<=0; + elsif Ex1_rdy='1' and Initialized='1' then + Next_St_ex1<=2; + end if; + + when 4 => if Ex2_rdy='0' then --s'il y a un message du réseau + --compter quelques cycles d'horloges pour attendre initreq2 + if n=4 then + Next_St_ex1<=0; + n_i<=0; + else + n_i<=n+1; + end if; + else + Next_St_ex1<=0; + end if; + + when others => + Next_St_ex1<=0; + end case; +end if; +end process ex1_Act; + +ex1_v:process(St_Ex1) + begin + case St_Ex1 is + when 0 => + Ex_en(1)<='0'; + when 1 => + Ex_en(1)<='0'; + when 2|3 => + Ex_en(1)<='1'; + when others => + Ex_en(1)<='0'; + end case; + +end process ex1_v; + +Ex2_nextState:Process(reset,st_Ex2, Ex4_rdy,Initialized,Ex2_Result,Ex2_rdy) --active la réception lorsqu' Put ou un Get ou un Init a été effectué +begin +Next_St_Ex2<=st_Ex2; +Case st_Ex2 is + +when 0 => + if Initialized='1' and Ex4_rdy='1' then --- Ex1_result(0)='1' or Ex1_result(1)='1' or Ex1_result(2)='1' then + Next_St_Ex2<=1; --active la réception des mesages sur le noeud. + + else + Next_St_Ex2<=0; + end if; +When 1 => + if Ex2_rdy='0' then + Next_St_Ex2<=2; + end if; +When 2 => + if Ex2_rdy='1' then + Next_St_Ex2<=0; + end if; +when others => + Next_St_Ex2<=0; + end case; +end process; +Ex2_val:Process(st_Ex2,Ex4_result,reset) -- + +begin +Case st_Ex2 is + +when 0 => +Ex_en(2)<='0'; +--LibState(3)<='0'; +when 1|2 => + Ex_en(2) <='1'; +when 3|4|5|6|7 => + Ex_en(2)<='0'; +when others=> + Ex_en(2)<='0'; +end case; + if rising_edge(Ex4_result(1)) then + LibState(3)<='1'; --spawn a été détecté. + elsif reset='1' then + LibState(3)<='0'; + end if; +end process; + +Ex_en_proc:process (clk,reset) +begin + if rising_edge(clk) then + if reset='1' then + Ex4_en<='0'; + else + + if Ex_en(4)='1' then + Ex4_en<='1'; --synchro + else + Ex4_en<='0'; --synchro + end if; + end if; + end if; +end process; +Ex4_Active:process (St_Ex4,initreq1,initreq2,Ex1_rdy,Initialized,Res4_en) +begin + +case St_Ex4 is + when 0 => + if (InitReq1='1') then + Next_St_Ex4<=1; + elsif InitReq2='1' then --le module 1 n'est pas actif + Next_St_Ex4<=2; + else + Next_St_Ex4<=0; + end if; + when 1 => + If Res4_en='1' then --fin de l'exécution du module + Next_St_Ex4<=3; + end if; + when 2 => + if Res4_en='1' then --Ex2_result(0)='1' + Next_St_Ex4<=4; + end if; + when 3 => + if initreq1='0' then + Next_St_Ex4<=5; + end if; + when 4 => + if initreq2='0' then + Next_St_Ex4<=5; + end if; + when 5 => + Next_St_Ex4<=0; + when others => + Next_St_Ex4<=0; + end case; + +end process Ex4_active; + +Ex4_active_val:process (st_Ex4) +begin + case St_Ex4 is + when 0 => + AppReq<='0'; + InitReq<='0';Ex_en(4)<='0'; + AppAck<='0'; + when 1 => + AppReq<='1'; + InitReq<='1'; + Ex_en(4)<='1'; + AppAck<='0'; + when 2 => + AppReq<='1'; + InitReq<='1'; + Ex_en(4)<='1'; + AppAck<='0'; + when 3 => + AppReq<='0'; + InitReq<='0'; + Ex_en(4)<='0'; + AppAck<='1'; + when 4 => + AppReq<='0'; + InitReq<='0'; + Ex_en(4)<='0'; + AppAck<='1'; + when 5 => + AppReq<='0'; + InitReq<='0';Ex_en(4)<='0'; + AppAck<='1'; + when others => + AppReq<='0'; + InitReq<='0'; + AppAck<='0'; + Ex_en(4)<='0'; + end case ; +-- Appreq<=Ex_en(4); --signal d'activation de la MAE Init +--InitReq<=(not(Initialized) and InitReq1) or InitReq2; -- deux cas permettent d'activer l'initialisation +--AppAck<=Ex1_result(0) or Ex2_result(0); -- signal init completed +end process Ex4_active_val; +--Ex_en(2)<=Initialized; --- Me pose des soucis en ce moment ??? +Ex_en(3)<='0'; +--Ex_en(4)<= '1' when InitReq='1' else '0'; + +-- soit une requête du PE soit une requête du Core + + +MPI_CORE_EX2_FSM: EX2_FSM PORT MAP( + + clk =>clk, + reset =>reset, + instruction_en=>Ex_en(2), + Ready =>Ex2_rdy, --signale que le module est disponible + fifo_full =>i_fifo2_full, + + fifo_wr_en => Ex2_i_fifo2_wr_en, + fifo_data => Ex2_i_fifo2_data_in, + + switch_port_out_rd_en => Noc2.port_out_rd_en, + switch_data_available =>Noc2.port_out_data_available, + switch_port_out_data =>Noc2.port_out_data , + + Rec_Rdy => Rec_Rdy, + Rec_Data =>Rec_Data, + Rec_Ack =>Rec_Ack, + -- il manque un signal pour valider l'accès à la RAM + dma_wr_request =>dma_wr_request(2), + dma_wr_grant =>dma_wr_grant(2), + dma_rd_request =>dma_rd_request(2), + dma_rd_grant =>dma_rd_grant(2), + ram_address =>dma_wr_address2, + Ram_rd => ex2_ram_rd, + Ram_wr =>ex2_ram_wr, + Ram_data_out=> Dma_data_out, + Ram_data_in => Dma_data_in2, + packet_received =>packet_received, + packet_ack => packet_ack, + barrier_completed =>barrier_completed, + AppRank =>MyRank, + AppSize =>MPISize, + AppInitReq => InitReq2, -- requête d'initialisation de l'application + AppInitAck =>Res4_En , -- Acquitement d'initialisation + Initialized=>Initialized, + Result => Ex2_Result -- le résultat de l'exécution + ); +Dma_rd_address2<=Dma_wr_address2; +ICI_MPI_CORE_EX3_FSM: EX3_FSM PORT MAP( + instruction => x"00", --pas utiliser + ResOut => RankSize, + clk =>clk , + IsMain=>IsMain, + reset => reset + ); +MPI_CORE_EX4_FSM :EX4_FSM PORT MAP ( + Instruction => Instr_in, --STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_En =>Ex4_en, -- ='1' lorsque ce module est sollicité + clk =>clk, + reset =>reset, + ResultOut =>Ex4_Result, --STD_LOGIC_VECTOR (Word-1 downto 0); + Result_En =>Res4_En, -- ='1' lorsque fin de l'exécution du module + Ready => Ex4_Rdy, + NocSize =>NocSize, + AppRank =>MyRank, + AppSize =>MPISize, + IsMain =>IsMain, + Rec_Rdy => Rec_Rdy, + Rec_Data =>Rec_Data, + Rec_Ack =>Rec_Ack, + Snd_Ack =>Snd_ack, + Snd_data =>Snd_data, + Snd_Start =>Snd_Start, + + I_fifo_full =>i_fifo2_full, + + I_fifo_wr_en => Ex4_i_fifo2_wr_en, + I_fifo_data_in => Ex4_i_fifo2_data_in, + Initialized =>Initialized, + Ram_data_out => Dma_data_out, + Ram_address =>dma_wr_Address4, --accès au stockage + Ram_wr =>Ex4_Ram_wr, --activation de l'écriture en RAM + Ram_data_in =>Dma_data_in4, --données à écrire en RAM + DMA_rd_Request => dma_rd_request(4), + DMA_rd_grant => dma_rd_grant(4), + DMA_wr_Request => dma_wr_request(4), + DMA_wr_grant => dma_wr_grant(4), + AppAck =>AppAck, + AppReq =>InitReq, + PortId=>PortId, + port_in_cmd_en => Noc3.port_in_cmd_en, + port_in_wr_en =>Noc3.port_in_wr_en, + port_in_empty =>Noc3.port_in_empty, + port_in_full =>Noc3.port_in_full, + port_in_data =>Noc3.port_in_data, + port_out_data =>Noc3.port_out_data, + port_out_rd_en =>Noc3.port_out_rd_en, + port_out_data_available =>Noc3.port_out_data_available + + +); +--=============Mux des signaux d'accès à la RAM========= +ram_we<='1' when (weram='1' and ram_wev ='1') else '0'; -- le contrôleur DMA contrôle directement +Ram_en<= '1' when (rdram ='1' or weram='1') else '0'; -- les signaux qui vont vers la RAM + + --dma_data_in <=dma_data_in1 or dma_data_in2; + --dma_data_out <=dma_data_out1 or dma_data_out2; + mux_ad_ram_rd:process (dma_rd_grant,dma_rd_address1,dma_rd_address2,dma_rd_address3, + ex1_ram_rd, Ex2_ram_rd, Exi_ram_rd ) +begin + case dma_rd_grant is + when "0001" => dma_rd_address <= dma_rd_address1; + rdram<= ex1_ram_rd; + when "0010" => dma_rd_address <= dma_rd_address2; + rdram<= ex2_ram_rd; + when "0100" => dma_rd_address <= dma_rd_address3; + rdram<= exi_ram_rd; +-- when "1000" => dma_rd_address <= ; + when others => dma_rd_address <= (others =>'0'); + rdram<='0'; + end case; +end process; + mux_ad_ram_wr:process (dma_wr_grant,dma_wr_address1,dma_wr_address2,dma_wr_address4,Dma_data_in1,Dma_data_in2,Dma_data_in4, + ex1_ram_wr,ex2_ram_wr,ex4_ram_wr) +begin + case dma_wr_grant is + + when "0001" => dma_wr_address <= dma_wr_address1; + weram<=ex1_ram_wr ; + Dma_data_in<=Dma_data_in1; + when "0010" => dma_wr_address <= dma_wr_address2; + weram<=ex2_ram_wr ; + Dma_data_in<=Dma_data_in2; + when "1000" => dma_wr_address <= dma_wr_address4; + weram<=ex4_ram_wr; + Dma_data_in<=Dma_data_in4; + when others => dma_wr_address <= (others =>'0'); + weram<='0'; + end case; +end process; +--====================================================== + +--=================Mux des signaux qui vont au switch============ + clkout<=clk; -- permettra le lien avec le module du switch + + NOC1.port_out_data<=switch_port_out_data; + NOC1.port_out_data_available<=switch_port_out_data_vailaible; + NOC1.port_in_empty<=switch_port_in_empty; + NOC1.port_in_full<=switch_port_in_full; + + NOC2.port_out_data<=switch_port_out_data; + NOC2.port_out_data_available<=switch_port_out_data_vailaible; + NOC2.port_in_empty<=switch_port_in_empty; + NOC2.port_in_full<=switch_port_in_full; + + NOC3.port_out_data<=switch_port_out_data; + NOC3.port_out_data_available<=switch_port_out_data_vailaible; + NOC3.port_in_empty<=switch_port_in_empty; + NOC3.port_in_full<=switch_port_in_full; + mux_Noc:process (Ex_en,Noc1,Noc2,Noc3,switch_port_out_data_vailaible,Initialized,Initreq2, + ex2_i_fifo2_wr_en,ex2_i_fifo2_data_in,ex4_i_fifo2_data_in,ex4_i_fifo2_wr_en, + instruction,ex2_result) + +begin + case Ex_en is + + when"0001" => + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC2.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + when "0010"|"0011" => + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC2.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + i_fifo2_wr_en<=ex2_i_fifo2_wr_en; + i_fifo2_data_in<=ex2_i_fifo2_data_in; + when"1011" => --ce cas pose problème car on ne sait ce qui se passe !!! + if initreq2='1' then + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + else + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC2.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + end if; + i_fifo2_wr_en<=ex2_i_fifo2_wr_en; + i_fifo2_data_in<=ex2_i_fifo2_data_in; + when "1001" => --ca où un appel à init est effectué + if initialized='0' then + switch_port_in_data <=Noc3.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC3.port_in_wr_en; + switch_port_in_cmd_en <=NOC3.port_in_cmd_en; + else + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + end if; + i_fifo2_wr_en<=ex4_i_fifo2_wr_en; + i_fifo2_data_in<=ex4_i_fifo2_data_in; + when "1010" => --ca où un appel à init est effectué + --switch_port_in_data <=Noc3.port_in_data; +-- switch_port_out_rd_en<=NOC3.port_out_rd_en; +-- switch_port_in_wr_en <=NOC3.port_in_wr_en; +-- switch_port_in_cmd_en <=NOC3.port_in_cmd_en; + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + i_fifo2_wr_en<=ex4_i_fifo2_wr_en; + i_fifo2_data_in<=ex4_i_fifo2_data_in; + when others => --permet de gérer le cas où un spawn arrive par le réseau + switch_port_in_data <=Noc3.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC3.port_in_wr_en; + switch_port_in_cmd_en <=NOC3.port_in_cmd_en; + + i_fifo2_wr_en<=ex4_i_fifo2_wr_en; + i_fifo2_data_in<=ex4_i_fifo2_data_in; + end case; + Instr_in <=Instruction ; + if initreq2='1' and Ex_en(4)='1' then + Instr_in <=Ex2_Result ; + else + Instr_in <=Instruction ; + end if; + i_fifo2_wr_en<=ex2_i_fifo2_wr_en; + i_fifo2_data_in<=ex2_i_fifo2_data_in; + end process; + + +--=============================================================== +MPI_CORE_DMA_ARBITER: DMA_ARBITER PORT MAP( + clk =>clk, + reset =>reset, + + data_wr_mem => ram_data_in, --vers RAM + + data_rd_mem => Ram_data_out, --- Vers RAM + address_rd =>dma_rd_address, + address_wr =>dma_wr_address, + address_out_rd =>ram_address_rd, + address_out_wr =>ram_address_wr, + ram_en => ram_env, --validation lecture + ram_we =>ram_wev, --validation écriture + hold_req=>hold_req,--demande de bus à l'application + hold_ack=>hold_ack, -- libération du bus RAM par l'application + + data_rd_out => Dma_data_out, --vers périphérique + data_wr_in =>Dma_data_in, --vers périphérique + dma_wr_grant =>dma_wr_grant, + dma_rd_request => dma_rd_request, + dma_rd_grant => dma_rd_grant, + dma_wr_request => dma_wr_request + ); + + +CORE_SCHEDULER: MPI_CORE_SCHEDULER PORT MAP( -- permet de sélectionner la source de l'instruction + -- qui sera exécutée par la MAE EX1 + clk => clk, + reset => reset, + priority_rotation =>scheduler_priority_rotation, + instruction_fifo_empty =>i_fifo1_empty, + get_request_fifo_empty => i_fifo2_empty, + instruction_fifo_rd_en =>i_fifo1_rd_en, + get_request_fifo_rd_en =>i_fifo2_rd_en , + instruction_fifo_data =>i_fifo1_data_out, + get_request_fifo_data =>i_fifo2_data_out, + fifo_selected =>fifo_sel, + instruction_available => fifo_instr, + fifo_empty => scheduler_fifo_empty, + fifo_rd_en =>scheduler_rd_en, + data_out => scheduler_data_out + ); + +end structural; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/CORE_MPI.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/CORE_MPI.vhd.bak (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/CORE_MPI.vhd.bak (revision 142) @@ -0,0 +1,1000 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM NGOUNOU +-- +-- Create Date: 05:52:25 06/21/2011 +-- Design Name: +-- Module Name: CORE_MPI - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +Library NocLib; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity CORE_MPI is + Port ( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + clkout : out std_logic; + instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + instruction_en : in STD_LOGIC; --valide l'instruction + instruction_fifo_full : out STD_LOGIC; + ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + barrier_completed : out STD_LOGIC; + packet_received : out STD_LOGIC; + packet_ack : in std_logic; + PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); --le resultat de l'exécution + ram_we : out STD_LOGIC; + ram_en : out STD_LOGIC; + ram_address_rd : out STD_LOGIC_VECTOR (15 downto 0); + ram_address_wr : out STD_LOGIC_VECTOR (15 downto 0); + ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + switch_port_in_cmd_en : out std_logic; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_in_wr_en : out STD_LOGIC; + switch_port_in_full : in STD_LOGIC; + switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_out_rd_en : out STD_LOGIC; + switch_port_in_empty : in STD_LOGIC; + switch_port_out_data_vailaible : in STD_LOGIC + ); + +end CORE_MPI; + +architecture Structural of CORE_MPI is +--déclaration des types +type Type_Noc is +record + port_in_cmd_en : std_logic; + port_out_data : STD_LOGIC_VECTOR (Word-1 downto 0); + port_in_wr_en : STD_LOGIC; + port_in_empty : STD_LOGIC; + port_in_full : STD_LOGIC; + port_in_data : STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_rd_en : STD_LOGIC; + port_out_data_available : STD_LOGIC; +end record; +-- déclaration des composants MPI + +COMPONENT FIFO_64_FWFT + PORT( + clk : IN std_logic; + din : IN std_logic_vector(Word-1 downto 0); + rd_en : IN std_logic; + srst : IN std_logic; + wr_en : IN std_logic; + dout : OUT std_logic_vector(Word-1 downto 0); + empty : OUT std_logic; + full : OUT std_logic + ); +END COMPONENT; +COMPONENT load_instr + Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + instruction_ack : out STD_LOGIC; + fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_wr :out std_logic; + fifo_full : in STD_LOGIC; + copying : out std_logic; + Ram_rd_en : out STD_LOGIC; + ram_address_rd : buffer STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0)); +end component; +COMPONENT DMA_ARBITER + PORT( + + clk : IN std_logic; + reset : IN std_logic; + dma_rd_request : IN std_logic_vector(3 downto 0); + data_wr_in : IN std_logic_vector(Word-1 downto 0); + data_rd_out : out std_logic_vector(Word-1 downto 0); + address_rd : IN std_logic_vector(15 downto 0); + address_wr : IN std_logic_vector(15 downto 0); + + dma_wr_request : IN std_logic_vector(3 downto 0); + address_out_rd : OUT std_logic_vector(15 downto 0); + address_out_wr : OUT std_logic_vector(15 downto 0); + ram_en : OUT std_logic; + ram_we : OUT std_logic; + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + data_wr_mem : OUT std_logic_vector(Word-1 downto 0); + data_rd_mem : IN std_logic_vector(Word-1 downto 0); + dma_wr_grant : OUT std_logic_vector(3 downto 0); + dma_rd_grant : OUT std_logic_vector(3 downto 0) + ); +END COMPONENT; + +COMPONENT EX1_FSM + PORT( + clk : IN std_logic; + reset : IN std_logic; + + pid : in std_logic_vector (3 downto 0); --port id + nprocs : in std_logic_vector (3 downto 0); -- la taille du Noc + instruction : in std_logic_vector(Word-1 downto 0); + instruction_en : in std_logic; + fifo_empty : IN std_logic; + fifo_data_out : IN std_logic_vector(Word-1 downto 0); + fifo_rd_en : OUT std_logic; + fifo_src : IN STD_LOGIC; + ram_data_in : IN std_logic_vector(Word-1 downto 0); + ram_data_out : out std_logic_vector(Word-1 downto 0); + dma_rd_grant : IN std_logic; + dma_wr_grant : IN std_logic; + dma_wr_request : OUT std_logic; + dma_rd_request : OUT std_logic; + ram_address : OUT std_logic_vector(15 downto 0); + ram_rd,ram_wr : out std_logic; + Snd_Data : IN Typ_PortIO(0 to 3); + Snd_Start : IN std_logic; + Snd_Ack : OUT std_logic; + priority_rotation : OUT std_logic; + + switch_port_in_data : OUT std_logic_vector(Word-1 downto 0); + switch_port_in_wr_en : OUT std_logic; + switch_port_in_full : IN std_logic; + Result :out std_logic_vector(Word-1 downto 0); + Ready : out std_logic; + AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic -- état de la Lib + ); + END COMPONENT; + +COMPONENT EX2_FSM + PORT( + clk : IN std_logic; + reset : IN std_logic; + + instruction_en: in std_logic; + Initialized : in std_logic; + + switch_port_out_rd_en : OUT std_logic ; + switch_data_available : IN std_logic; + switch_port_out_data : IN std_logic_vector(Word-1 downto 0); + AppRank : in STD_LOGIC_VECTOR; + AppSize : in STD_LOGIC_VECTOR; + dma_wr_grant : IN std_logic; + dma_wr_request : OUT std_logic; + dma_rd_grant : IN std_logic; + dma_rd_request : OUT std_logic; + ram_address : OUT std_logic_vector(15 downto 0); + ram_rd,ram_wr : out std_logic; + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_full : IN std_logic; + Rec_Rdy : OUT std_logic; + Rec_Data : buffer Typ_PortIO(0 to 3); + Rec_Ack : IN std_logic; + fifo_data : OUT std_logic_vector(Word-1 downto 0); + fifo_wr_en : OUT std_logic; + --fifo_out : out std_logic_vector; + Result : out STD_LOGIC_VECTOR (Word-1 downto 0); + packet_received : OUT std_logic; + packet_ack : IN std_logic; + barrier_completed : OUT std_logic; + Ready : Out std_logic; + AppInitAck : in std_logic; + AppInitReq : out std_logic + ); + END COMPONENT; + + + COMPONENT EX3_FSM + PORT( + instruction : IN std_logic_vector(Word-1 downto 0); + clk : IN std_logic; + reset : IN std_logic; + Ismain :in std_logic; + ResOut : OUT std_logic_vector(Word-1 downto 0) + + ); + END COMPONENT; + + COMPONENT EX4_FSM + PORT( + Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); --permet de lire le FIFO + Instruction_En : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + ResultOut : out STD_LOGIC_VECTOR (Word-1 downto 0); + Result_En : out STD_LOGIC; + Ready : out STD_LOGIC; + NocSize : out STD_LOGIC_VECTOR; + AppRank : out STD_LOGIC_VECTOR; + AppSize : out STD_LOGIC_VECTOR; + IsMain : out STD_LOGIC; + I_fifo_full :in STD_LOGIC; + Snd_Ack : IN std_logic; + Rec_Rdy : IN std_logic; + Rec_Data : IN Typ_PortIO(0 to 3); + Snd_data : OUT Typ_PortIO(0 to 3); + Snd_Start : buffer std_logic; + Rec_Ack : OUT std_logic; + I_fifo_wr_en: out STD_LOGIC; + I_fifo_data_in :out STD_LOGIC_vector(Word-1 downto 0); + Initialized : out STD_LOGIC; + dma_wr_request : out std_logic; + dma_rd_request : out std_logic; + dma_wr_grant : in std_logic; + dma_rd_grant : in std_logic; + Ram_address : out STD_LOGIC_VECTOR (15 downto 0); --accès au stockage + Ram_wr : out STD_LOGIC; --activation de l'écriture en RAM + Ram_Data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);--données des ports + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + AppAck : in STD_LOGIC; + AppReq : in STD_LOGIC; + PortId : out STD_LOGIC_VECTOR(3 downto 0); + port_in_cmd_en : out STD_LOGIC; + port_in_wr_en : out STD_LOGIC; + port_in_empty : in STD_LOGIC; + port_in_full : in STD_LOGIC; + port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_rd_en : out STD_LOGIC; + port_out_data_available : in STD_LOGIC); + END COMPONENT; + + COMPONENT EX0_FSM + PORT( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + + Initialized : in STD_LOGIC; + Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + instruction_en: in STD_LOGIC; + + ClkRate : in STD_LOGIC_VECTOR ; + uTimeResult : out STD_LOGIC_VECTOR; + TickResult : out STD_LOGIC_VECTOR + ); + END COMPONENT; + + +COMPONENT MPI_CORE_SCHEDULER + PORT( + clk : IN std_logic; + reset : IN std_logic; + priority_rotation : IN std_logic; + instruction_fifo_empty : IN std_logic; + instruction_fifo_rd_en : OUT std_logic; + instruction_fifo_data : IN std_logic_vector(Word-1 downto 0); + instruction_available : OUT std_logic; + + get_request_fifo_empty : IN std_logic; + get_request_fifo_rd_en : OUT std_logic; + get_request_fifo_data : IN std_logic_vector(Word-1 downto 0); + + fifo_rd_en : IN std_logic; + fifo_empty : OUT std_logic; + fifo_selected : OUT std_logic; + + data_out : OUT std_logic_vector(Word-1 downto 0) + + + ); + END COMPONENT; + +-- declaration des signaux d'interconnexion entre les modules du coresignal fifo_sel: std_logic; -- indique l'un des deux fifos d'instructions qui sont prêts +signal fifo_instr : std_logic; -- une instruction est prête dans les fifos d'instruction + + +signal scheduler_fifo_empty : std_logic; +signal scheduler_data_out : std_logic_vector(Word-1 downto 0); +signal dma_arbiter_data_rd_out : std_logic_vector(Word-1 downto 0); + +signal scheduler_priority_rotation : std_logic; +signal scheduler_rd_en : std_logic; + +signal dma_data_rd,dma_data_wr : std_logic_vector(Word-1 downto 0); -- bus à 3 états +signal dma_rd_address,dma_rd_address1,dma_rd_address2 : std_logic_vector(15 downto 0); -- ces bus doivent être gérés en logique 3 états! +signal dma_rd_address3 : std_logic_vector(15 downto 0); +signal dma_wr_address1,dma_wr_address3 : std_logic_vector(15 downto 0); +signal dma_wr_address2,dma_wr_address4 : std_logic_vector(15 downto 0); +signal dma_wr_address : std_logic_vector(15 downto 0); +signal switch_port_in_data_signal : std_logic_vector(Word-1 downto 0); +signal ram_data_out_signal : std_logic_vector(Word-1 downto 0); +signal weram,rdram,ram_wev,ram_env :std_logic:='0'; + +signal i_fifo2_signal : std_logic_vector(Word-1 downto 0); +signal Ex_EN : std_logic_vector(4 downto 1):=(others=>'0'); --active les sous MAE permettant de décoder les instructions MPI +signal Res4_en:std_logic;--acquittement du réusltat du module n°4 +signal Ex4_en,Ex1_RDY,Ex2_RDY,EX3_RDY,EX4_RDY : std_logic:='0'; -- indique la fin de l'exécution de la MAE +signal ex1_ram_rd,ex2_ram_rd,ex4_ram_rd ,Exi_ram_rd: std_logic:='0' ; -- validation lecture des données en RAM +signal ex1_ram_wr,ex2_ram_wr,ex4_ram_wr,Exi_ram_wr : std_logic :='0'; -- validation écriture des données en RAM +signal Exi_busy : std_logic:='0'; +signal Ex1_Result,Ex2_Result,Ex4_result : std_logic_vector(Word-1 downto 0); +signal Instr_in : STD_LOGIC_VECTOR (Word-1 downto 0); +--================interface DMA avec les modules ====================================== +signal dma_data_in,Dma_data_in1,dma_data_in2,dma_data_in4 : std_logic_vector(Word-1 downto 0); +signal dma_data_out : std_logic_vector(Word-1 downto 0); +signal dma_rd_request :std_logic_vector(4 downto 1):=(others=>'0'); +signal dma_wr_request :std_logic_vector(4 downto 1):=(others=>'0'); +signal dma_wr_grant,dma_rd_grant:std_logic_vector(4 downto 1); +-- +--====================================================================================== +--connexion au switch + +signal Noc1,NOC2,NOC3 : Type_Noc; -- regroupement des signaux qui vont au Noc + +--================================================================ +--déclaration des signaux d'état du Core +signal IsMain,SizeSet,RankSet,Initialized,AppReq,AppAck:std_logic; +signal InitReq,InitReq1,InitReq2 :std_logic:='0'; -- demande d'initialisation +signal InitAck,IAck,Ilatch : std_logic:='0'; +signal MPISize,MyRank : std_logic_vector(3 downto 0); +signal LibState: std_logic_vector(Word-1 downto 0):=(others=>'0'); --ready,receiving,sending,spawning,rwaiting,swaiting,... +signal NocSize :std_logic_vector(3 downto 0):=(others=>'0'); +Signal PortId : std_logic_vector(3 downto 0); +Signal uClkRate : std_logic_vector(Word-1 downto 0):="00011010"; --50 Mhz +signal uTimeCount :std_logic_vector(31 downto 0):=(others=>'0'); +signal TickCount : std_logic_vector(31 downto 0):=(others=>'0'); +signal RankSize: std_logic_vector(Word-1 downto 0):=(others=>'0'); +--======================================================== +--déclaration des signaux permettant d'activer le module +signal AdrSelect : std_logic_vector(ADRLEN-1 downto 0); +--======================================================== +--signal PushOut_d,RankSize,TickUsOut:std_logic_vector; --résultat de l'execution des commandes mpi +--======================================================== +--connexion avec les FIFO instructions +signal fifo1_wr : std_logic; +signal fifo1_din : std_logic_vector (Word-1 downto 0); +signal fifo_sel : std_logic; --permet d'arbitrer la priorité de lecture entre les deux fifos +signal i_fifo1_rd_en : std_logic; +signal fifo1_full : std_logic; +signal i_fifo1_empty : std_logic; +signal i_fifo1_data_out : std_logic_vector(Word-1 downto 0); +signal i_fifo2_rd_en : std_logic; +signal i_fifo2_data_out : std_logic_vector(Word-1 downto 0); +signal i_fifo2_data_in : std_logic_vector(Word-1 downto 0); +signal i_fifo2_wr_en : std_logic; +signal i_fifo2_empty : std_logic; +signal i_fifo2_full : std_logic; +signal Ex2_i_fifo2_data_in : std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal Ex2_i_fifo2_wr_en : std_logic:='0'; +--signaux pour les données entre modules +signal Snd_Ack :std_logic; +signal Rec_Rdy : std_logic; +signal Rec_Data : Typ_PortIO(0 to 3); +signal Snd_data : Typ_PortIO(0 to 3); +signal Snd_Start : std_logic; +signal Rec_Ack : std_logic; +--signal i_fifo2_empty : std_logic; +--signal i_fifo2_full : std_logic; +signal Ex4_i_fifo2_data_in : std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal Ex4_i_fifo2_wr_en : std_logic:='0'; +--signal i_fifo2_empty : std_logic; +--signal i_fifo2_full : std_logic; +-- signaux pour la gestion des MAE +signal n,n_i :natural range 0 to 7:=0; +signal St_Ex1,St_Ex2,St_Ex4:natural range 0 to 7:=0; +signal Next_St_Ex1,Next_St_Ex2,Next_St_Ex4:natural range 0 to 7:=0; +--=========================================================== + +begin +--switch_port_in_data_signal <= ; +--switch_port_out_data_signal <= ; +-- istanciation des composants du core MPI +Instruction_Fifo1: FIFO_64_FWFT PORT MAP( + clk =>clk, + din =>fifo1_din, + rd_en => i_fifo1_rd_en, + srst => reset, + wr_en => fifo1_wr, + dout =>i_fifo1_data_out, + empty => i_fifo1_empty, + full => fifo1_full + ); + +Instruction_Fifo2: FIFO_64_FWFT PORT MAP( + clk =>clk, + din => i_fifo2_data_in , + rd_en =>i_fifo2_rd_en, + srst =>reset, + wr_en =>i_fifo2_wr_en, + dout =>i_fifo2_data_out, + empty =>i_fifo2_empty, + full => i_fifo2_full + ); +LD_instr:load_instr PORT MAP ( + + Instruction =>Instruction, + Instruction_en =>Instruction_en, + clk =>clk, + reset =>reset, + dma_rd_grant =>dma_rd_grant(3), + dma_rd_request =>dma_rd_request(3), + copying=> Exi_busy, + instruction_ack =>iack, --indique la fin de la copie d'une instruction dans le FIFO + fifo_din => fifo1_din, + fifo_wr => fifo1_wr, + fifo_full =>fifo1_full, + Ram_rd_en=> Exi_ram_rd, + ram_address_rd => dma_rd_address3, + ram_data =>dma_data_out --sortie DMA +); + +pushout(0)<=ILatch; +pushout(1)<=IsMain; +pushout(2)<=SizeSet; +pushout(3)<=Ex4_result(6); --Spawn in progress on main +pushout(4)<=Initialized; +pushout(5)<=Ex1_result(1); -- +pushout(6)<=LibState(3); --Spawned child +pushout(7)<=Ex4_result(7); --Spawn complete +MPI_CORE_EX0_FSM: EX0_FSM PORT MAP( + instruction => i_fifo1_data_out, + instruction_en=> '1', + uTimeResult => uTimeCount, + TickResult => TickCount, + Initialized => Initialized, -- indique si la l'appel à init a été concluant + ClkRate => uClkRate, + clk =>clk , + reset => reset + ); +MPI_CORE_EX1_FSM: EX1_FSM PORT MAP( + clk =>clk , + reset =>reset, + pid => MyRank, --port Id + nprocs=>MPISize, -- à revoir dans certains cas ou tous les PEs ne sont pas connectés + fifo_empty => scheduler_fifo_empty , + fifo_data_out =>scheduler_data_out, + fifo_rd_en =>scheduler_rd_en, + fifo_src =>fifo_sel, + priority_rotation => scheduler_priority_rotation, + + instruction_en=>Ex_en(1), --active le module + Instruction => Instruction, + switch_port_in_full =>Noc1.port_in_full, --ces signaux doivent être contrôlés en 3 state logic + switch_port_in_data =>Noc1.port_in_data, + switch_port_in_wr_en =>Noc1.Port_in_wr_en , + + Snd_Data =>Snd_Data, + Snd_Start =>Snd_start, + Snd_Ack =>Snd_ack, + Ram_rd => ex1_ram_rd, + Ram_wr =>ex1_ram_wr, + ram_data_in =>dma_data_out, + Ram_data_out =>dma_data_in1, + ram_address=>dma_wr_address1, + --ram_address =>dma_rd_address2, --la même adresse sert pour la lecture ou l'écriture + dma_rd_request =>dma_rd_request(1), + dma_wr_request =>dma_wr_request(1), + dma_rd_grant =>dma_rd_grant(1) , + dma_wr_grant =>dma_wr_grant(1) , + + AppInitReq => InitReq1, -- requête d'initialisation de l'application + AppInitAck =>Res4_En , -- Acquitement d'initialisation + Initialized=>Initialized, -- état de la Lib + Result => Ex1_Result, -- le résultat de l'exécution + Ready=> Ex1_Rdy + ); +instruction_fifo_full<=fifo1_full; +dma_rd_address1<=dma_wr_address1; --la même adresse sert pour la lecture ou l'écriture en RAM +Exi_sync :process(reset,clk) + +begin + if rising_edge(clk) then + if reset='1' then + St_Ex2<=0; + St_Ex1<=0; + St_Ex4<=0; + Ilatch<='0'; + n<=0; + else + St_Ex2<=Next_St_Ex2; + St_Ex1<=Next_St_Ex1; + St_Ex4<=Next_St_Ex4; + ILatch<=Iack; + n<=n_i; + end if; +end if; +End process Exi_sync; +-- détermination de l'activation des module +--scheduler_priority_rotation<=not(Ex1_rdy); +Ex1_Act:process(ST_Ex1,Initialized,reset,fifo_instr,n,InitReq,Ex4_rdy,Ex1_rdy,Ex2_rdy)--A qoui sert encore ce processus (26/10/12) ???? +variable c_cyl:natural range 0 to 15:=0; +begin + if reset='1' then + Next_St_ex1<=0; + c_cyl:=0; +else -- cette machie à état permet de distinguer les activations de Ex4 et Ex1 + Next_St_ex1<=ST_EX1; + case St_ex1 is + when 0 => if InitReq='1' and Initialized='0' then + Next_St_ex1<=1; + elsif Initialized='1' then + Next_St_ex1 <=2; + elsif fifo_instr='1' then --cas d'une instruction directe qui est présente + --if fifo_sel='0' then + Next_St_ex1 <=2; + --end if; + end if; + + when 1 => if Ex4_Rdy='1' then + Next_St_ex1<=4; + end if; + when 2 => if Ex1_rdy='0' then --ex1 est libre et actif + Next_St_ex1<=3; + end if; + + when 3 => if Ex1_rdy='1' and Initialized='0'then --ex1 est occupé et actif + Next_St_ex1<=0; + elsif Ex1_rdy='1' and Initialized='1' then + Next_St_ex1<=2; + end if; + + when 4 => if Ex2_rdy='0' then --s'il y a un message du réseau + --compter quelques cycles d'horloges pour attendre initreq2 + if n=4 then + Next_St_ex1<=0; + n_i<=0; + else + n_i<=n+1; + end if; + else + Next_St_ex1<=0; + end if; + + when others => + Next_St_ex1<=0; + end case; +end if; +end process ex1_Act; + +ex1_v:process(St_Ex1) + begin + case St_Ex1 is + when 0 => + Ex_en(1)<='0'; + when 1 => + Ex_en(1)<='0'; + when 2|3 => + Ex_en(1)<='1'; + when others => + Ex_en(1)<='0'; + end case; + +end process ex1_v; + +Ex2_nextState:Process(reset,st_Ex2, Ex4_rdy,Initialized,Ex2_Result,Ex2_rdy) --active la réception lorsqu' Put ou un Get ou un Init a été effectué +begin +Next_St_Ex2<=st_Ex2; +Case st_Ex2 is + +when 0 => + if Initialized='1' and Ex4_rdy='1' then --- Ex1_result(0)='1' or Ex1_result(1)='1' or Ex1_result(2)='1' then + Next_St_Ex2<=1; --active la réception des mesages sur le noeud. + + else + Next_St_Ex2<=0; + end if; +When 1 => + if Ex2_rdy='0' then + Next_St_Ex2<=2; + end if; +When 2 => + if Ex2_rdy='1' then + Next_St_Ex2<=0; + end if; +when others => + Next_St_Ex2<=0; + end case; +end process; +Ex2_val:Process(st_Ex2,Ex4_result,reset) -- + +begin +Case st_Ex2 is + +when 0 => +Ex_en(2)<='0'; +--LibState(3)<='0'; +when 1|2 => + Ex_en(2) <='1'; +when 3|4|5|6|7 => + Ex_en(2)<='0'; +when others=> + Ex_en(2)<='0'; +end case; + if rising_edge(Ex4_result(1)) then + LibState(3)<='1'; --spawn a été détecté. + elsif reset='1' then + LibState(3)<='0'; + end if; +end process; + +Ex_en_proc:process (clk,reset) +begin + if rising_edge(clk) then + if reset='1' then + Ex4_en<='0'; + else + + if Ex_en(4)='1' then + Ex4_en<='1'; --synchro + else + Ex4_en<='0'; --synchro + end if; + end if; + end if; +end process; +Ex4_Active:process (St_Ex4,initreq1,initreq2,Ex1_rdy,Initialized,Res4_en) +begin + +case St_Ex4 is + when 0 => + if (InitReq1='1') then + Next_St_Ex4<=1; + elsif InitReq2='1' then --le module 1 n'est pas actif + Next_St_Ex4<=2; + else + Next_St_Ex4<=0; + end if; + when 1 => + If Res4_en='1' then --fin de l'exécution du module + Next_St_Ex4<=3; + end if; + when 2 => + if Res4_en='1' then --Ex2_result(0)='1' + Next_St_Ex4<=4; + end if; + when 3 => + if initreq1='0' then + Next_St_Ex4<=5; + end if; + when 4 => + if initreq2='0' then + Next_St_Ex4<=5; + end if; + when 5 => + Next_St_Ex4<=0; + when others => + Next_St_Ex4<=0; + end case; + +end process Ex4_active; + +Ex4_active_val:process (st_Ex4) +begin + case St_Ex4 is + when 0 => + AppReq<='0'; + InitReq<='0';Ex_en(4)<='0'; + AppAck<='0'; + when 1 => + AppReq<='1'; + InitReq<='1'; + Ex_en(4)<='1'; + AppAck<='0'; + when 2 => + AppReq<='1'; + InitReq<='1'; + Ex_en(4)<='1'; + AppAck<='0'; + when 3 => + AppReq<='0'; + InitReq<='0'; + Ex_en(4)<='0'; + AppAck<='1'; + when 4 => + AppReq<='0'; + InitReq<='0'; + Ex_en(4)<='0'; + AppAck<='1'; + when 5 => + AppReq<='0'; + InitReq<='0';Ex_en(4)<='0'; + AppAck<='1'; + when others => + AppReq<='0'; + InitReq<='0'; + AppAck<='0'; + Ex_en(4)<='0'; + end case ; +-- Appreq<=Ex_en(4); --signal d'activation de la MAE Init +--InitReq<=(not(Initialized) and InitReq1) or InitReq2; -- deux cas permettent d'activer l'initialisation +--AppAck<=Ex1_result(0) or Ex2_result(0); -- signal init completed +end process Ex4_active_val; +--Ex_en(2)<=Initialized; --- Me pose des soucis en ce moment ??? +Ex_en(3)<='0'; +--Ex_en(4)<= '1' when InitReq='1' else '0'; + +-- soit une requête du PE soit une requête du Core + + +MPI_CORE_EX2_FSM: EX2_FSM PORT MAP( + + clk =>clk, + reset =>reset, + instruction_en=>Ex_en(2), + Ready =>Ex2_rdy, --signale que le module est disponible + fifo_full =>i_fifo2_full, + + fifo_wr_en => Ex2_i_fifo2_wr_en, + fifo_data => Ex2_i_fifo2_data_in, + + switch_port_out_rd_en => Noc2.port_out_rd_en, + switch_data_available =>Noc2.port_out_data_available, + switch_port_out_data =>Noc2.port_out_data , + + Rec_Rdy => Rec_Rdy, + Rec_Data =>Rec_Data, + Rec_Ack =>Rec_Ack, + -- il manque un signal pour valider l'accès à la RAM + dma_wr_request =>dma_wr_request(2), + dma_wr_grant =>dma_wr_grant(2), + dma_rd_request =>dma_rd_request(2), + dma_rd_grant =>dma_rd_grant(2), + ram_address =>dma_wr_address2, + Ram_rd => ex2_ram_rd, + Ram_wr =>ex2_ram_wr, + Ram_data_out=> Dma_data_out, + Ram_data_in => Dma_data_in2, + packet_received =>packet_received, + packet_ack => packet_ack, + barrier_completed =>barrier_completed, + AppRank =>MyRank, + AppSize =>MPISize, + AppInitReq => InitReq2, -- requête d'initialisation de l'application + AppInitAck =>Res4_En , -- Acquitement d'initialisation + Initialized=>Initialized, + Result => Ex2_Result -- le résultat de l'exécution + ); +Dma_rd_address2<=Dma_wr_address2; +ICI_MPI_CORE_EX3_FSM: EX3_FSM PORT MAP( + instruction => x"00", --pas utiliser + ResOut => RankSize, + clk =>clk , + IsMain=>IsMain, + reset => reset + ); +MPI_CORE_EX4_FSM :EX4_FSM PORT MAP ( + Instruction => Instr_in, --STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_En =>Ex4_en, -- ='1' lorsque ce module est sollicité + clk =>clk, + reset =>reset, + ResultOut =>Ex4_Result, --STD_LOGIC_VECTOR (Word-1 downto 0); + Result_En =>Res4_En, -- ='1' lorsque fin de l'exécution du module + Ready => Ex4_Rdy, + NocSize =>NocSize, + AppRank =>MyRank, + AppSize =>MPISize, + IsMain =>IsMain, + Rec_Rdy => Rec_Rdy, + Rec_Data =>Rec_Data, + Rec_Ack =>Rec_Ack, + Snd_Ack =>Snd_ack, + Snd_data =>Snd_data, + Snd_Start =>Snd_Start, + + I_fifo_full =>i_fifo2_full, + + I_fifo_wr_en => Ex4_i_fifo2_wr_en, + I_fifo_data_in => Ex4_i_fifo2_data_in, + Initialized =>Initialized, + Ram_data_out => Dma_data_out, + Ram_address =>dma_wr_Address4, --accès au stockage + Ram_wr =>Ex4_Ram_wr, --activation de l'écriture en RAM + Ram_data_in =>Dma_data_in4, --données à écrire en RAM + DMA_rd_Request => dma_rd_request(4), + DMA_rd_grant => dma_rd_grant(4), + DMA_wr_Request => dma_wr_request(4), + DMA_wr_grant => dma_wr_grant(4), + AppAck =>AppAck, + AppReq =>InitReq, + PortId=>PortId, + port_in_cmd_en => Noc3.port_in_cmd_en, + port_in_wr_en =>Noc3.port_in_wr_en, + port_in_empty =>Noc3.port_in_empty, + port_in_full =>Noc3.port_in_full, + port_in_data =>Noc3.port_in_data, + port_out_data =>Noc3.port_out_data, + port_out_rd_en =>Noc3.port_out_rd_en, + port_out_data_available =>Noc3.port_out_data_available + + +); +--=============Mux des signaux d'accès à la RAM========= +ram_we<='1' when (weram='1' and ram_wev ='1') else '0'; -- le contrôleur DMA contrôle directement +Ram_en<= '1' when (rdram ='1' or weram='1') else '0'; -- les signaux qui vont vers la RAM + + --dma_data_in <=dma_data_in1 or dma_data_in2; + --dma_data_out <=dma_data_out1 or dma_data_out2; + mux_ad_ram_rd:process (dma_rd_grant,dma_rd_address1,dma_rd_address2,dma_rd_address3, + ex1_ram_rd, Ex2_ram_rd, Exi_ram_rd ) +begin + case dma_rd_grant is + when "0001" => dma_rd_address <= dma_rd_address1; + rdram<= ex1_ram_rd; + when "0010" => dma_rd_address <= dma_rd_address2; + rdram<= ex2_ram_rd; + when "0100" => dma_rd_address <= dma_rd_address3; + rdram<= exi_ram_rd; +-- when "1000" => dma_rd_address <= ; + when others => dma_rd_address <= (others =>'0'); + rdram<='0'; + end case; +end process; + mux_ad_ram_wr:process (dma_wr_grant,dma_wr_address1,dma_wr_address2,dma_wr_address4,Dma_data_in1,Dma_data_in2,Dma_data_in4, + ex1_ram_wr,ex2_ram_wr,ex4_ram_wr) +begin + case dma_wr_grant is + + when "0001" => dma_wr_address <= dma_wr_address1; + weram<=ex1_ram_wr ; + Dma_data_in<=Dma_data_in1; + when "0010" => dma_wr_address <= dma_wr_address2; + weram<=ex2_ram_wr ; + Dma_data_in<=Dma_data_in2; + when "1000" => dma_wr_address <= dma_wr_address4; + weram<=ex4_ram_wr; + Dma_data_in<=Dma_data_in4; + when others => dma_wr_address <= (others =>'0'); + weram<='0'; + end case; +end process; +--====================================================== + +--=================Mux des signaux qui vont au switch============ + clkout<=clk; -- permettra le lien avec le module du switch + + NOC1.port_out_data<=switch_port_out_data; + NOC1.port_out_data_available<=switch_port_out_data_vailaible; + NOC1.port_in_empty<=switch_port_in_empty; + NOC1.port_in_full<=switch_port_in_full; + + NOC2.port_out_data<=switch_port_out_data; + NOC2.port_out_data_available<=switch_port_out_data_vailaible; + NOC2.port_in_empty<=switch_port_in_empty; + NOC2.port_in_full<=switch_port_in_full; + + NOC3.port_out_data<=switch_port_out_data; + NOC3.port_out_data_available<=switch_port_out_data_vailaible; + NOC3.port_in_empty<=switch_port_in_empty; + NOC3.port_in_full<=switch_port_in_full; + mux_Noc:process (Ex_en,Noc1,Noc2,Noc3,switch_port_out_data_vailaible,Initialized,Initreq2, + ex2_i_fifo2_wr_en,ex2_i_fifo2_data_in,ex4_i_fifo2_data_in,ex4_i_fifo2_wr_en, + instruction,ex2_result) + +begin + case Ex_en is + + when"0001" => + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC2.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + when "0010"|"0011" => + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC2.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + i_fifo2_wr_en<=ex2_i_fifo2_wr_en; + i_fifo2_data_in<=ex2_i_fifo2_data_in; + when"1011" => --ce cas pose problème car on ne sait ce qui se passe !!! + if initreq2='1' then + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + else + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC2.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + end if; + i_fifo2_wr_en<=ex2_i_fifo2_wr_en; + i_fifo2_data_in<=ex2_i_fifo2_data_in; + when "1001" => --ca où un appel à init est effectué + if initialized='0' then + switch_port_in_data <=Noc3.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC3.port_in_wr_en; + switch_port_in_cmd_en <=NOC3.port_in_cmd_en; + else + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + end if; + i_fifo2_wr_en<=ex4_i_fifo2_wr_en; + i_fifo2_data_in<=ex4_i_fifo2_data_in; + when "1010" => --ca où un appel à init est effectué + --switch_port_in_data <=Noc3.port_in_data; +-- switch_port_out_rd_en<=NOC3.port_out_rd_en; +-- switch_port_in_wr_en <=NOC3.port_in_wr_en; +-- switch_port_in_cmd_en <=NOC3.port_in_cmd_en; + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + i_fifo2_wr_en<=ex4_i_fifo2_wr_en; + i_fifo2_data_in<=ex4_i_fifo2_data_in; + when others => --permet de gérer le cas où un spawn arrive par le réseau + switch_port_in_data <=Noc3.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC3.port_in_wr_en; + switch_port_in_cmd_en <=NOC3.port_in_cmd_en; + + i_fifo2_wr_en<=ex4_i_fifo2_wr_en; + i_fifo2_data_in<=ex4_i_fifo2_data_in; + end case; + Instr_in <=Instruction ; + if initreq2='1' and Ex_en(4)='1' then + Instr_in <=Ex2_Result ; + else + Instr_in <=Instruction ; + end if; + i_fifo2_wr_en<=ex2_i_fifo2_wr_en; + i_fifo2_data_in<=ex2_i_fifo2_data_in; + end process; + + +--=============================================================== +MPI_CORE_DMA_ARBITER: DMA_ARBITER PORT MAP( + clk =>clk, + reset =>reset, + + data_wr_mem => ram_data_in, --vers RAM + + data_rd_mem => Ram_data_out, --- Vers RAM + address_rd =>dma_rd_address, + address_wr =>dma_wr_address, + address_out_rd =>ram_address_rd, + address_out_wr =>ram_address_wr, + ram_en => ram_env, --validation lecture + ram_we =>ram_wev, --validation écriture + hold_req=>hold_req,--demande de bus à l'application + hold_ack=>hold_ack, -- libération du bus RAM par l'application + + data_rd_out => Dma_data_out, --vers périphérique + data_wr_in =>Dma_data_in, --vers périphérique + dma_wr_grant =>dma_wr_grant, + dma_rd_request => dma_rd_request, + dma_rd_grant => dma_rd_grant, + dma_wr_request => dma_wr_request + ); + + +CORE_SCHEDULER: MPI_CORE_SCHEDULER PORT MAP( -- permet de sélectionner la source de l'instruction + -- qui sera exécutée par la MAE EX1 + clk => clk, + reset => reset, + priority_rotation =>scheduler_priority_rotation, + instruction_fifo_empty =>i_fifo1_empty, + get_request_fifo_empty => i_fifo2_empty, + instruction_fifo_rd_en =>i_fifo1_rd_en, + get_request_fifo_rd_en =>i_fifo2_rd_en , + instruction_fifo_data =>i_fifo1_data_out, + get_request_fifo_data =>i_fifo2_data_out, + fifo_selected =>fifo_sel, + instruction_available => fifo_instr, + fifo_empty => scheduler_fifo_empty, + fifo_rd_en =>scheduler_rd_en, + data_out => scheduler_data_out + ); + +end structural; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/DEMUX1.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/DEMUX1.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/DEMUX1.vhd (revision 142) @@ -0,0 +1,54 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:35:09 06/13/2011 +-- Design Name: +-- Module Name: DEMUX1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity CDEMUX1 is + Port ( di : in STD_LOGIC; + sel : in STD_LOGIC; + do1 : out STD_LOGIC; + do2 : out STD_LOGIC); +end CDEMUX1; + +architecture Behavioral of CDEMUX1 is + +begin + +demux_process : process(di, sel) +begin + if sel = '0' then + do1 <= di; + do2 <= '0'; + else + do2 <= di; + do1 <='0'; + end if; +end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/DMA_ARBITER.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/DMA_ARBITER.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/DMA_ARBITER.vhd (revision 142) @@ -0,0 +1,479 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL +-- GAMOM ROLAND CHRISTIAN +-- +-- Create Date: 04:39:43 05/21/2011 +-- Design Name: +-- Module Name: DMA_ARBITER - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- gestionnaire DMA pour le port secodaire de la RAM true dual port des mémoire +-- privée de chaque noeud +-- Dependencies: +-- +-- Revision: 09/07/2012 +-- Revision 1.01 - File Created +-- Revision 1.2 - 19/03/2013 +-- Correction de bugs et optimisation du nombre de cycles +-- Création d'un testbench +-- Additional Comments: Ce module pourra être optimisé pour générer les adresses automatiquement +-- par le controleur DMA lorsqu'il est sollicité par la périphérie +-- +---------------------------------------------------------------------------------- +library IEEE; +library NocLib; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.numeric_std.all; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity DMA_ARBITER is + Port ( dma_rd_request : in STD_LOGIC_VEctor (3 downto 0):=(others=>'0'); + data_wr_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + data_rd_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + address_rd : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); --adresse pour lecture + address_wr : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); -- adresse pour écriture + address_out_wr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); -- adresse de sortie du DMA Arbiter + address_out_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_en : out STD_LOGIC; -- + ram_we : out STD_LOGIC; + data_wr_mem : out STD_LOGIC_VECTOR (Word-1 downto 0); -- donnée en sortie écriture + data_rd_mem : in STD_LOGIC_VECTOR (Word-1 downto 0); -- données en sortie lecture + dma_wr_grant : out STD_LOGIC_vector(3 downto 0):=(others=>'0'); -- autorisation d'écriture + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + clk : in std_logic; + reset : in std_logic; + dma_rd_grant : out STD_LOGIC_vector(3 downto 0):=(others=>'0'); -- autorisation de lecture + dma_wr_request : in STD_LOGIC_vector(3 downto 0):=(others=>'0')); -- demande de lecture +end DMA_ARBITER; + +architecture Behavioral of DMA_ARBITER is +type fsm_states is (idle,wait_ack,arbiter_ack, writing,ReadWrite,reading);-- definition du type etat pour le codage des etats des fsm +signal dmac_state : fsm_states; + +signal prio_rd,prio_wr:std_logic_vector(3 downto 0);--vecteur de bits de priorité +signal pri_rd,pri_wr : natural range 0 to 3; -- stocke le numéro du module qui a la priorité +signal dma_rd_logic : std_logic_vector(3 downto 0):=(others=>'0'); +signal dma_wr_logic : std_logic_vector(3 downto 0):=(others=>'0'); +signal dma_rd_latch,dma_wr_latch: std_logic_vector(3 downto 0):=(others=>'0'); +signal dma_req_wr, dma_req_rd : std_logic; +signal last_grant_rd,last_grant_wr : STD_LOGIC_vector(3 downto 0):=(others=>'0'); +signal tmp :std_logic_vector(3 downto 0):="0000"; + +begin +--========================================================================== +---le MUX qui contrôle les adresses est géré à l'extérieur du contrôleur DMA +dma_sync: process (clk,data_rd_mem,data_wr_in,address_rd,address_wr) +begin +data_rd_out<=data_rd_mem ; +data_wr_mem <= data_wr_in; +address_out_rd <= address_rd; +address_out_wr <= address_wr; + +end process; +--dma_rd_grant<= dma_rd_logic; +--dma_wr_grant<= dma_wr_logic; +dma_rd_grant<= dma_rd_latch; +dma_wr_grant<= dma_wr_latch; +--========================================================================== + +--Déterminer si une requête HOLD doit être émise vers l'application pour la libération du +--bus mémoire +tmp<=(others =>'0'); + +--for i in 0 to 3 loop +--dma_req_wr<=dma_req_wr or dma_wr_request(i); +--loop; + +--for i in 0 to 3 loop +-- dma_req_rd<=dma_req_rd or dma_rd_request(i); -- construire le signal request vers l'extérieur +--loop; +req_process:process(reset,dma_req_rd,dma_req_wr) +begin + if reset='1' then + hold_req<='0'; +else + if dma_req_rd='1' or dma_req_wr='1' then + hold_req<='1'; +else + hold_req<='0'; +end if; +end if; + +end process; +--hold_req<='1' when dma_req_rd='1' or dma_req_wr='1' else '0'; --envoyer un Hold vers l'application + + +-- machine à etat du DMAC +dmac_process : process(clk,reset) +--variable tmp : natural range 0 to 15; +variable tmp_rd,tmp_wr: std_logic_vector(3 downto 0); +variable req_rd,req_wr : std_logic:='0' ; + +begin + if rising_edge(clk) then + if reset = '1' then + dmac_state<= idle; + dma_wr_logic <="0000"; + dma_rd_logic <="0000"; + prio_rd <="0001"; -- au debut priorité lecture au premier module + prio_wr <="0010"; -- au debut priorité ecriture au deuxième module + pri_rd<=0;--index de la priorité + pri_wr<=1; + req_rd:='0'; + req_wr:='0'; + dma_req_wr<= '0'; + dma_req_rd<= '0'; + else + if req_wr='0' then --tant que le Ctrl DMA est libre alors faire bouger la priorité en écriture + case dma_wr_request is + when "0001" => pri_wr<=0; + prio_wr<="0001"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="0001"; + when "0010" => pri_wr<=1; + prio_wr<="0010"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="0010"; + when "0100" => pri_wr<=2; + prio_wr<="0100"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="0100"; + when "1000" => pri_wr<=3; + prio_wr<="1000"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="1000"; + + when others => + if req_rd='1' then --demande simultané de lecture et d'écriture + + if dma_rd_request(pri_rd)='1' then + pri_wr<=pri_rd; + req_wr:='1'; + for i in 0 to 3 loop + if i=pri_rd then + prio_wr(i)<='1'; + dma_wr_logic(i)<='1'; + else + prio_wr(i)<='0'; + dma_wr_logic(i)<='0'; + end if; + end loop; + + + end if; + + else --on affecte l'accè à la mémoire suivant le round robbin + tmp_wr:= (dma_wr_request and prio_wr) ; + dma_wr_logic <=tmp_wr; + + req_wr:= not(All_zeros(tmp_wr)); + dma_req_wr<= not(All_zeros(tmp_wr)); + end if; + -- la priorité est circulaire et décale à chaque coup d'horloge + if req_wr='0' then + prio_wr<=rol_vec(prio_wr); + if pri_wr=3 then + pri_wr<=0; + Prio_wr<="0001"; + else + pri_wr<=pri_wr+1; + end if; + end if; + end case; + else --req_wr='1' + + --demande simultané de lecture et d'écriture + + if dma_rd_request(pri_wr)='1' then + pri_rd<=pri_wr; + req_rd:='1'; + prio_rd<=prio_wr; +-- for i in 0 to 3 loop +-- if i=pri_rd then +-- prio_wr(i)<='1'; +-- dma_wr_logic(i)<='1'; +-- else +-- prio_wr(i)<='0'; +-- dma_wr_logic(i)<='0'; +-- end if; +-- end loop; + + end if; + + end if; + + if req_rd='0' then --tant que le Ctrl DMA est libre alors faire bouger la priorité + case dma_rd_request is + when "0001" => pri_rd<=0; + prio_rd<="0001"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="0001"; + when "0010" => pri_rd<=1; + prio_rd<="0010"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="0010"; + + when "0100" => pri_rd<=2; + prio_rd<="0100"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="0100"; + + when "1000" => pri_rd<=3; + prio_rd<="1000"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="1000"; + + when others => + --si une demande survient de la part d'un composant déjà acquitté alors celui-ci est prioritaire + if req_wr='1' then + + if dma_rd_request(pri_wr)='1' then + pri_rd<=pri_wr; + req_rd:='1'; + for i in 0 to 3 loop + if i=pri_wr then + prio_rd(i)<='1'; + dma_rd_logic(i)<='1'; + else + prio_rd(i)<='0'; + dma_rd_logic(i)<='0'; + end if; + end loop; + + + end if; + + else + tmp_rd:= (dma_rd_request and prio_rd) ; + dma_rd_logic<=tmp_rd; + dma_req_rd<= not (All_Zeros(tmp_rd)); + req_rd:= not (All_Zeros(tmp_rd)); + end if; + -- la priorité est circulaire et décale à chaque coup d'horloge + if req_rd='0' then + prio_rd<=rol_vec(prio_rd); + if pri_rd =3 then + pri_rd<=0; + prio_rd<="0001"; + else + + pri_rd<=pri_rd+1; + end if; + end if; + end case; + + end if; + + case dmac_state is + when idle => if req_rd='1' or req_wr='1' then + dmac_state<=wait_ack; + else -- initialiser la priorité + + + req_rd:='0'; + dma_req_rd<= '0'; + + + + req_wr:='0'; + dma_req_wr<= '0'; + + dma_wr_logic <="0000"; --aucun accès mémoire n'est accrédité + dma_rd_logic <="0000"; + + end if; + + when wait_ack => -- l'application doit autoriser l'utilisation de la RAM par le Core + if dma_wr_request(pri_wr) ='1' or dma_rd_request(pri_rd) ='1' then + if hold_ack='1' then + --dmac_state<=arbiter_ack; + if dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='1' then -- + dmac_state <= Readwrite; + elsif dma_wr_request(pri_wr) ='0' and dma_rd_request(pri_rd) ='1' then + dmac_state <= Reading; + elsif dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='0' then + dmac_state <= Writing; + else + dmac_state<=Idle; + end if; + end if; + else + + if dma_wr_request(pri_wr) ='0' then + req_wr:='0';-- forcer une nouvelle recherche de priorité + end if; + + if dma_rd_request(pri_rd) ='0' then + req_rd:='0'; + end if; + dmac_state<=Idle; + end if; + + + when arbiter_ack => +-- if dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='1' then -- +-- dmac_state <= Readwrite; +-- elsif dma_wr_request(pri_wr) ='0' and dma_rd_request(pri_rd) ='1' then +-- dmac_state <= Reading; +-- elsif dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='0' then +-- dmac_state <= Writing; +-- else + dmac_state<=Idle; +-- end if; + -- cet état a été combiné au précédent pour gagner un cycle + when Writing => if dma_wr_request(pri_wr) ='1' then + if hold_ack='1' then + -- on reste dans cet état + if dma_rd_request(pri_rd)='1' then + dmac_state<=ReadWrite; + else + req_rd:='0'; + end if; + else + dmac_state<=wait_ack; + end if; + elsif dma_rd_request(pri_rd) ='1' then + dmac_state <= Reading; + req_wr:='0'; + else + dmac_state <= idle; + req_wr:='0'; + end if; + + + when ReadWrite => if hold_ack='1' then + if dma_wr_request(pri_wr)='1' and dma_rd_request(pri_rd)='1' then + dmac_state <= ReadWrite; + elsif dma_wr_request(pri_wr)='1' and dma_rd_request(pri_rd)='0' then + dmac_state <= Writing; + req_rd:='0'; + elsif dma_wr_request(pri_wr)='0' and dma_rd_request(pri_rd)='1' then + dmac_state <= Reading; + req_wr:='0'; + else + dmac_state <= Idle; + req_rd:='0';req_wr:='0'; + end if; + else + if (dma_wr_request(pri_wr)='1') or (dma_rd_request(pri_rd)='1') then + dmac_state <= Wait_ack; + else + dmac_state <= Idle; + end if; + end if; + when Reading => + if dma_rd_request(pri_rd) ='1' then + if hold_ack='1' then + -- on reste dans cet état + if dma_wr_request(pri_wr)='1' then + dmac_state<=ReadWrite; + else + req_wr:='0'; + end if; + else + dmac_state<=wait_ack; + end if; + elsif dma_wr_request(pri_wr) ='1' then + dmac_state<=writing; + req_rd:='0'; + else + dmac_state <= idle; + req_rd:='0'; + end if; + when others => dmac_state <= idle; + end case; + end if; + end if; +end process; +-- action_asociées +ol: process(dmac_state, address_rd, address_wr,pri_wr,pri_rd,prio_wr,prio_rd,dma_wr_request,dma_rd_request) + +begin +--tester les requêtes DMA en lecture ou en écriture + +case dmac_state is + when idle => + ram_en <='0'; + ram_we <='0'; + dma_wr_latch <=(others=>'0'); + dma_rd_latch <=(others=>'0'); + --address_out_rd <= address_rd; + --hold_req<='0'; + when wait_ack => + ram_en <='0'; + ram_we <='0'; + dma_wr_latch<=(others=>'0'); + dma_rd_latch<=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= (others=>'Z'); + --hold_req<='1'; + when arbiter_ack => --à optimiser pour gagner un cycle + ram_en <='0'; + ram_we <='0'; + dma_wr_latch<=(others=>'0'); + dma_rd_latch<=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= (others=>'Z'); + when writing => -- ecriture dans la ram + ram_en <='1'; + ram_we <='1'; + dma_wr_latch<=(others=>'0'); + dma_wr_latch(pri_wr) <='1'; + dma_rd_latch <=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= address_wr; + --hold_req<='1'; + + when ReadWrite => -- Lecture et écriture simultannée dans la Dual Port RAM + ram_en <='1'; + ram_we <='1'; + dma_wr_latch<=(others=>'0'); + dma_wr_latch(pri_wr) <='1'; + dma_rd_latch<=(others=>'0'); + dma_rd_latch(pri_rd)<='1'; + + --address_out_rd <= address_rd; + --address_out_wr <= address_wr; + --hold_req<='1'; + when Reading => -- lecture dans la ram + ram_en <='1'; + ram_we <='0'; + dma_wr_latch<=(others=>'0'); + dma_rd_latch<=(others=>'0'); + dma_rd_latch(pri_rd)<='1'; + + --address_out_rd <= address_rd; + --address_out_wr <= (others=>'Z'); + --hold_req<='1'; + when others => + ram_en <='0'; + ram_we <='0'; + dma_wr_latch <=(others=>'0'); + dma_rd_latch <=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= (others=>'Z'); + --hold_req<='0'; + end case; +end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/DMA_ARBITER.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/DMA_ARBITER.vhd.bak (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/DMA_ARBITER.vhd.bak (revision 142) @@ -0,0 +1,466 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL +-- GAMOM ROLAND CHRISTIAN +-- +-- Create Date: 04:39:43 05/21/2011 +-- Design Name: +-- Module Name: DMA_ARBITER - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- gestionnaire DMA pour le port secodaire de la RAM true dual port des mémoire +-- privée de chaque noeud +-- Dependencies: +-- +-- Revision: 09/07/2012 +-- Revision 1.01 - File Created +-- Revision 1.2 - 19/03/2013 +-- Correction de bugs et optimisation du nombre de cycles +-- Création d'un testbench +-- Additional Comments: Ce module pourra être optimisé pour générer les adresses automatiquement +-- par le controleur DMA lorsqu'il est sollicité par la périphérie +-- +---------------------------------------------------------------------------------- +library IEEE; +library NocLib; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.numeric_std.all; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity DMA_ARBITER is + Port ( dma_rd_request : in STD_LOGIC_VEctor (3 downto 0):=(others=>'0'); + data_wr_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + data_rd_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + address_rd : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); --adresse pour lecture + address_wr : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); -- adresse pour écriture + address_out_wr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); -- adresse de sortie du DMA Arbiter + address_out_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_en : out STD_LOGIC; -- + ram_we : out STD_LOGIC; + data_wr_mem : out STD_LOGIC_VECTOR (Word-1 downto 0); -- donnée en sortie écriture + data_rd_mem : in STD_LOGIC_VECTOR (Word-1 downto 0); -- données en sortie lecture + dma_wr_grant : out STD_LOGIC_vector(3 downto 0):=(others=>'0'); -- autorisation d'écriture + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + clk : in std_logic; + reset : in std_logic; + dma_rd_grant : out STD_LOGIC_vector(3 downto 0):=(others=>'0'); -- autorisation de lecture + dma_wr_request : in STD_LOGIC_vector(3 downto 0):=(others=>'0')); -- demande de lecture +end DMA_ARBITER; + +architecture Behavioral of DMA_ARBITER is +type fsm_states is (idle,wait_ack,arbiter_ack, writing,ReadWrite,reading);-- definition du type etat pour le codage des etats des fsm +signal dmac_state : fsm_states; + +signal prio_rd,prio_wr:std_logic_vector(3 downto 0);--vecteur de bits de priorité +signal pri_rd,pri_wr : natural range 0 to 3; -- stocke le numéro du module qui a la priorité +signal dma_rd_logic : std_logic_vector(3 downto 0):=(others=>'0'); +signal dma_wr_logic : std_logic_vector(3 downto 0):=(others=>'0'); +signal dma_rd_latch,dma_wr_latch: std_logic_vector(3 downto 0):=(others=>'0'); +signal dma_req_wr, dma_req_rd : std_logic; +signal last_grant_rd,last_grant_wr : STD_LOGIC_vector(3 downto 0):=(others=>'0'); +signal tmp :std_logic_vector(3 downto 0):="0000"; + +begin +--========================================================================== +---le MUX qui contrôle les adresses est géré à l'extérieur du contrôleur DMA +dma_sync: process (clk,data_rd_mem,data_wr_in,address_rd,address_wr) +begin +data_rd_out<=data_rd_mem ; +data_wr_mem <= data_wr_in; +address_out_rd <= address_rd; +address_out_wr <= address_wr; + +end process; +--dma_rd_grant<= dma_rd_logic; +--dma_wr_grant<= dma_wr_logic; +dma_rd_grant<= dma_rd_latch; +dma_wr_grant<= dma_wr_latch; +--========================================================================== + +--Déterminer si une requête HOLD doit être émise vers l'application pour la libération du +--bus mémoire +tmp<=(others =>'0'); + +--for i in 0 to 3 loop +--dma_req_wr<=dma_req_wr or dma_wr_request(i); +--loop; + +--for i in 0 to 3 loop +-- dma_req_rd<=dma_req_rd or dma_rd_request(i); -- construire le signal request vers l'extérieur +--loop; +hold_req<='1' when dma_req_rd='1' or dma_req_wr='1' else '0'; --envoyer un Hold vers l'application + + +-- machine à etat du DMAC +dmac_process : process(clk,reset) +--variable tmp : natural range 0 to 15; +variable tmp_rd,tmp_wr: std_logic_vector(3 downto 0); +variable req_rd,req_wr : std_logic:='0' ; + +begin + if rising_edge(clk) then + if reset = '1' then + dmac_state<= idle; + dma_wr_logic <="0000"; + dma_rd_logic <="0000"; + prio_rd <="0001"; -- au debut priorité lecture au premier module + prio_wr <="0010"; -- au debut priorité ecriture au deuxième module + pri_rd<=0;--index de la priorité + pri_wr<=1; + req_rd:='0'; + req_wr:='0'; + dma_req_wr<= '0'; + dma_req_rd<= '0'; + else + if req_wr='0' then --tant que le Ctrl DMA est libre alors faire bouger la priorité en écriture + case dma_wr_request is + when "0001" => pri_wr<=0; + prio_wr<="0001"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="0001"; + when "0010" => pri_wr<=1; + prio_wr<="0010"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="0010"; + when "0100" => pri_wr<=2; + prio_wr<="0100"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="0100"; + when "1000" => pri_wr<=3; + prio_wr<="1000"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="1000"; + + when others => + if req_rd='1' then --demande simultané de lecture et d'écriture + + if dma_rd_request(pri_rd)='1' then + pri_wr<=pri_rd; + req_wr:='1'; + for i in 0 to 3 loop + if i=pri_rd then + prio_wr(i)<='1'; + dma_wr_logic(i)<='1'; + else + prio_wr(i)<='0'; + dma_wr_logic(i)<='0'; + end if; + end loop; + + + end if; + + else --on affecte l'accè à la mémoire suivant le round robbin + tmp_wr:= (dma_wr_request and prio_wr) ; + dma_wr_logic <=tmp_wr; + + req_wr:= not(All_zeros(tmp_wr)); + dma_req_wr<= not(All_zeros(tmp_wr)); + end if; + -- la priorité est circulaire et décale à chaque coup d'horloge + if req_wr='0' then + prio_wr<=rol_vec(prio_wr); + if pri_wr=3 then + pri_wr<=0; + Prio_wr<="0001"; + else + pri_wr<=pri_wr+1; + end if; + end if; + end case; + else --req_wr='1' + + --demande simultané de lecture et d'écriture + + if dma_rd_request(pri_wr)='1' then + pri_rd<=pri_wr; + req_rd:='1'; + prio_rd<=prio_wr; +-- for i in 0 to 3 loop +-- if i=pri_rd then +-- prio_wr(i)<='1'; +-- dma_wr_logic(i)<='1'; +-- else +-- prio_wr(i)<='0'; +-- dma_wr_logic(i)<='0'; +-- end if; +-- end loop; + + end if; + + end if; + + if req_rd='0' then --tant que le Ctrl DMA est libre alors faire bouger la priorité + case dma_rd_request is + when "0001" => pri_rd<=0; + prio_rd<="0001"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="0001"; + when "0010" => pri_rd<=1; + prio_rd<="0010"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="0010"; + + when "0100" => pri_rd<=2; + prio_rd<="0100"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="0100"; + + when "1000" => pri_rd<=3; + prio_rd<="1000"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="1000"; + + when others => + --si une demande survient de la part d'un composant déjà acquitté alors celui-ci est prioritaire + if req_wr='1' then + + if dma_rd_request(pri_wr)='1' then + pri_rd<=pri_wr; + req_rd:='1'; + for i in 0 to 3 loop + if i=pri_wr then + prio_rd(i)<='1'; + dma_rd_logic(i)<='1'; + else + prio_rd(i)<='0'; + dma_rd_logic(i)<='0'; + end if; + end loop; + + + end if; + + else + tmp_rd:= (dma_rd_request and prio_rd) ; + dma_rd_logic<=tmp_rd; + dma_req_rd<= not (All_Zeros(tmp_rd)); + req_rd:= not (All_Zeros(tmp_rd)); + end if; + -- la priorité est circulaire et décale à chaque coup d'horloge + if req_rd='0' then + prio_rd<=rol_vec(prio_rd); + if pri_rd =3 then + pri_rd<=0; + prio_rd<="0001"; + else + + pri_rd<=pri_rd+1; + end if; + end if; + end case; + + end if; + + case dmac_state is + when idle => if req_rd='1' or req_wr='1' then + dmac_state<=wait_ack; + else -- initialiser la priorité + + + req_rd:='0'; + dma_req_rd<= '0'; + + + + req_wr:='0'; + dma_req_wr<= '0'; + + dma_wr_logic <="0000"; --aucun accès mémoire n'est accrédité + dma_rd_logic <="0000"; + + end if; + + when wait_ack => -- l'application doit autoriser l'utilisation de la RAM par le Core + if dma_wr_request(pri_wr) ='1' or dma_rd_request(pri_rd) ='1' then + if hold_ack='1' then + --dmac_state<=arbiter_ack; + if dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='1' then -- + dmac_state <= Readwrite; + elsif dma_wr_request(pri_wr) ='0' and dma_rd_request(pri_rd) ='1' then + dmac_state <= Reading; + elsif dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='0' then + dmac_state <= Writing; + else + dmac_state<=Idle; + end if; + end if; + else + + if dma_wr_request(pri_wr) ='0' then + req_wr:='0';-- forcer une nouvelle recherche de priorité + end if; + + if dma_rd_request(pri_rd) ='0' then + req_rd:='0'; + end if; + dmac_state<=Idle; + end if; + + + when arbiter_ack => +-- if dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='1' then -- +-- dmac_state <= Readwrite; +-- elsif dma_wr_request(pri_wr) ='0' and dma_rd_request(pri_rd) ='1' then +-- dmac_state <= Reading; +-- elsif dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='0' then +-- dmac_state <= Writing; +-- else + dmac_state<=Idle; +-- end if; + -- cet état a été combiné au précédent pour gagner un cycle + when Writing => if dma_wr_request(pri_wr) ='1' then + if hold_ack='1' then + -- on reste dans cet état + if dma_rd_request(pri_rd)='1' then + dmac_state<=ReadWrite; + else + req_rd:='0'; + end if; + else + dmac_state<=wait_ack; + end if; + elsif dma_rd_request(pri_rd) ='1' then + dmac_state <= Reading; + req_wr:='0'; + else + dmac_state <= idle; + req_wr:='0'; + end if; + + + when ReadWrite => if hold_ack='1' then + if dma_wr_request(pri_wr)='1' and dma_rd_request(pri_rd)='1' then + dmac_state <= ReadWrite; + elsif dma_wr_request(pri_wr)='1' and dma_rd_request(pri_rd)='0' then + dmac_state <= Writing; + req_rd:='0'; + elsif dma_wr_request(pri_wr)='0' and dma_rd_request(pri_rd)='1' then + dmac_state <= Reading; + req_wr:='0'; + else + dmac_state <= Idle; + req_rd:='0';req_wr:='0'; + end if; + else + if (dma_wr_request(pri_wr)='1') or (dma_rd_request(pri_rd)='1') then + dmac_state <= Wait_ack; + else + dmac_state <= Idle; + end if; + end if; + when Reading => + if dma_rd_request(pri_rd) ='1' then + if hold_ack='1' then + -- on reste dans cet état + if dma_wr_request(pri_wr)='1' then + dmac_state<=ReadWrite; + else + req_wr:='0'; + end if; + else + dmac_state<=wait_ack; + end if; + elsif dma_wr_request(pri_wr) ='1' then + dmac_state<=writing; + req_rd:='0'; + else + dmac_state <= idle; + req_rd:='0'; + end if; + when others => dmac_state <= idle; + end case; + end if; + end if; +end process; +-- action_asociées +ol: process(dmac_state, address_rd, address_wr,pri_wr,pri_rd,prio_wr,prio_rd,dma_wr_request,dma_rd_request) + +begin +--tester les requêtes DMA en lecture ou en écriture + +case dmac_state is + when idle => + ram_en <='0'; + ram_we <='0'; + dma_wr_latch <=(others=>'0'); + dma_rd_latch <=(others=>'0'); + --address_out_rd <= address_rd; + --hold_req<='0'; + when wait_ack => + ram_en <='0'; + ram_we <='0'; + dma_wr_latch<=(others=>'0'); + dma_rd_latch<=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= (others=>'Z'); + --hold_req<='1'; + when arbiter_ack => --à optimiser pour gagner un cycle + ram_en <='0'; + ram_we <='0'; + dma_wr_latch<=(others=>'0'); + dma_rd_latch<=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= (others=>'Z'); + when writing => -- ecriture dans la ram + ram_en <='1'; + ram_we <='1'; + dma_wr_latch<=(others=>'0'); + dma_wr_latch(pri_wr) <='1'; + dma_rd_latch <=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= address_wr; + --hold_req<='1'; + + when ReadWrite => -- Lecture et écriture simultannée dans la Dual Port RAM + ram_en <='1'; + ram_we <='1'; + dma_wr_latch<=(others=>'0'); + dma_wr_latch(pri_wr) <='1'; + dma_rd_latch<=(others=>'0'); + dma_rd_latch(pri_rd)<='1'; + + --address_out_rd <= address_rd; + --address_out_wr <= address_wr; + --hold_req<='1'; + when Reading => -- lecture dans la ram + ram_en <='1'; + ram_we <='0'; + dma_wr_latch<=(others=>'0'); + dma_rd_latch<=(others=>'0'); + dma_rd_latch(pri_rd)<='1'; + + --address_out_rd <= address_rd; + --address_out_wr <= (others=>'Z'); + --hold_req<='1'; + when others => + ram_en <='0'; + ram_we <='0'; + dma_wr_latch <=(others=>'0'); + dma_rd_latch <=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= (others=>'Z'); + --hold_req<='0'; + end case; +end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX1_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX1_FSM.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX1_FSM.vhd (revision 142) @@ -0,0 +1,1321 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer:GAMOM /KIEGAING +-- +-- Create Date: 08:12:29 06/16/2011 +-- Design Name: +-- Module Name: EX1_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Ce module est chargé de recevoir les instructions du programme MPI et +-- de les exécuter (PUT) il coopère avec EX2 qui reçoit les instructions venant du NoC +-- (GET) +-- +-- Dependencies: +-- +-- Revision: 09/07/2012 +-- Revision 0.03 - File updated +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library NocLib ; +use Work.Packet_type.ALL; +USE ieee.numeric_std.ALL; + + +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX1_FSM is + -- parametres generiques du module : + + + Port ( + --instruction_available : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + instruction : in std_logic_vector(Word-1 downto 0); + instruction_en : in std_logic:='0'; -- active le module instruction + pid : in std_logic_vector(3 downto 0) ; -- id du processeur + nprocs : in std_logic_vector(3 downto 0);-- nombre de processeur du MPSOC - 1 + Result : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module + Ready : out std_logic; --indique la fin de l'éxécution d'une instruction + AppInitReq :out STD_LOGIC:='0'; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic ; -- état de la Lib + -- Accès au Fifo d'instructions + priority_rotation : out STD_LOGIC:='0'; + fifo_rd_en : out STD_LOGIC:='0'; + fifo_empty : in STD_LOGIC; + fifo_data_out : in STD_LOGIC_VECTOR (7 downto 0); + fifo_src : in STD_LOGIC; --permet de désigner le fifo qui est en service + + + Snd_Data : IN Typ_PortIO(0 to 3); + Snd_Start : IN std_logic; + Snd_Ack : OUT std_logic; + + -- Accès au réseau sur puce + switch_port_in_full : in std_logic; + switch_port_in_data : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); + switch_port_in_wr_en : out STD_LOGIC:='0'; + -- Accès à la mémoire RAM du PE + ram_data_in : in std_logic_vector(7 downto 0); + ram_data_out : out std_logic_vector(7 downto 0):=(others=>'0'); + ram_rd,ram_wr : out std_logic:='0'; + ram_address : out std_logic_vector(15 downto 0):=(others=>'0'); + + dma_wr_request : OUT std_logic:='0'; + dma_rd_request : OUT std_logic:='0'; + dma_wr_grant : in STD_LOGIC; + dma_rd_grant : in STD_LOGIC); +end EX1_FSM; + +architecture Behavioral of EX1_FSM is + +component proto_send is +generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée + fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie + fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie + fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée + fifo_in_data_out : in std_logic_vector(Word-1 downto 0); + fifo_out_data_in : out std_logic_vector(Word-1 downto 0); + packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet + copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo + snd_start : in std_logic; --début de la réception + snd_ack :in std_logic; -- acquittement de la réception + snd_comp : out std_logic; -- fin de la réception + mem :in memory(0 to sizemem-1)); --données à copier vers le fifo + + +end component proto_send; +-- definition du type etat pour le codage des etats des fsm +type fsm_states is (fifo_select, fetch_packet_type, decode_packet_type, fetch_addresses, + decode_packet_type2, read_status1,read_status2,ex1_barrier1, ex1_barrier2, ex1_barrier3, ex1_barrier4, + ex1_get1, ex1_get2,ex1_get3,ex1_get4, ex1_put1, ex1_put2, ex1_put3, ex1_put4,ex1_put5, + ex1_init1,ex1_init_run,ex1_init2,ex1_init3,ex1_spawn,ex1_ready,ex1_send_ack,ex1_Wsync); +-- machine a etat du module +signal ex1_state,Next_Ex1_state : fsm_states; + +-- les variables utilisées dans la fsm +signal snd_start1,snd_start_sync,snd_comp,snd_ack1,push:std_logic:='0'; +signal mem,mem_i : memory(0 to 3); +signal data_to_send,data_to_send_i,result_i,result1,noc_fifo_in : std_logic_vector(Word-1 downto 0); +signal packet_type,packet_type_i : std_logic_vector(3 downto 0); +--signal dpid : std_logic_vector(3 downto 0); +signal pid_counter,pid_counter_i : std_logic_vector(3 downto 0); +signal p_len,p_len_i: std_logic_vector(Word-1 downto 0); +signal src_address,src_address_i : std_logic_vector(ADRLEN-1 downto 0); +signal dma_rd,dma_wr,Wr_ok,rd_ok:std_logic:='0'; +--signal res_address : std_logic_vector(15 downto 0); +signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0); +signal n,n_i : natural range 0 to 15; +signal len,len_i : natural range 0 to 255; +signal fifo_rd,fifo_wr,fifo_copy:std_logic:='0'; +signal fifo_sel:std_logic:='0'; +signal run_init,run_init_i:std_logic:='0'; +begin +-- connection des signaux avec les ports +ram_address <= src_address; +result<=Result1; +sw_send: proto_send generic map (sizemem=>4) + port map ( + clk=>clk, + reset=>reset, + fifo_in_empty=>fifo_empty, + fifo_in_full=>'0',--pas utilisé + fifo_out_empty=>'0', + packet_len=>p_len, + copy_mode=>fifo_copy, + fifo_out_full => switch_port_in_full, + fifo_in_rd_en=>fifo_rd, + fifo_in_data_out=>fifo_data_out, +fifo_out_wr_en =>fifo_wr, + + fifo_out_data_in =>noc_fifo_in, + snd_start =>snd_start_sync, + snd_ack =>snd_ack1, + snd_comp=>snd_comp, + mem =>mem + ); +ex1_fsm_sync:process(clk) + + begin + if rising_edge(clk) then + if reset = '1' then + ex1_state <= fifo_select; + n<=0; + len<=0; + p_len<=(others=>'0'); + snd_ack<='0'; + src_address<=(others=>'0'); + dest_address<=(others=>'0'); + run_init<='0'; + else + ex1_state<=next_ex1_state; + n<=n_i; + len<=len_i; + p_len<=p_len_i; + dest_address<=dest_address_i; + Packet_type<=Packet_type_i; + Pid_counter<=Pid_counter_i; + Data_to_send<=Data_to_send_i; + Result1<=Result_i; + run_init<=Run_init_i; + for i in 0 to 3 loop + mem(i)<=mem_i(i); + end loop; + src_address <= src_address_i; + snd_ack<=snd_ack1; --acquittement de l'envoie des données pour EX4 + snd_start_sync<=snd_start1; + end if; + end if; + end process ex1_fsm_sync; +-- processus de transistion entre les etats +fsm_nst_logic : process(ex1_state,n,instruction_en,fifo_empty,fifo_data_out, switch_port_in_full,pid, + pid_counter,len,p_len,snd_start,snd_comp, ram_data_in,dma_rd_grant,dma_wr_grant,AppInitAck,src_address, + fifo_src,dest_address,packet_type,mem,snd_data,run_init,data_to_send) +variable tempval : std_logic_vector(Word-1 downto 0); +variable onepop,fifo_vide : std_logic:='0'; --indique que le fifo a été dépilé +begin + snd_ack1<='0'; + fifo_copy<='0'; + snd_start1<='0'; + n_i<=n; --valeur par défaut + Next_ex1_state <=Ex1_state; + Src_address_i<=src_address; + dest_address_i<=dest_address; + P_len_i<=P_len; + Packet_type_i<=Packet_type; + Pid_counter_i<=Pid_counter; + run_init_i<=Run_init; + Len_i<=Len; + Wr_ok<='0'; + Rd_ok<='0'; + Data_to_send_i<=Data_to_send; + dma_rd<='0'; --attention ceci peut changer le code + dma_wr<='0'; --il faut donc le vérifier + for i in 0 to 3 loop + mem_i(i)<=mem(i); + end loop; + case ex1_state is + when fifo_select => if instruction_en='1' and fifo_empty ='0' then + Next_ex1_state <= fetch_packet_type; + else + Next_ex1_state <= fifo_select; + end if; + rd_ok<='0'; + wr_ok<='0'; + if instruction_en='1' and snd_start='1' then + run_init_i<='1'; + Next_ex1_state<=ex1_init_run; + else + run_init_i<='0'; + end if; + --lecture du registre status de la mib MPI + when read_status1 => if dma_rd_grant = '1' then -- fin du mpi_put + Next_ex1_state <= read_status2; + else + Next_ex1_state <= read_status1; + end if; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16)); + when read_status2 => + Next_ex1_state <= fifo_select; + when fetch_packet_type => rd_ok<='0'; + if fifo_empty ='1' then + Next_ex1_state <= fifo_select; + else + packet_type_i <= fifo_data_out(7 downto 4); + data_to_send_i <= fifo_data_out; + Next_ex1_state <= decode_packet_type; + rd_ok<='1'; + end if; + when decode_packet_type => rd_ok<='0'; + if fifo_empty='0' then + if packet_type = MPI_PUT then + p_len_i <= fifo_data_out + 4; + n_i <= 0;rd_ok<='1'; + Next_ex1_state <= fetch_addresses; + elsif packet_type = MPI_GET then + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i <= fifo_data_out; + n_i <= 0; rd_ok<='1'; + Next_ex1_state <= fetch_addresses; + elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then + p_len_i <= "00000011"; -- = 3 + pid_counter_i <= "0000"; + rd_ok<='1'; + Next_ex1_state <= ex1_barrier1; + elsif packet_type = MPI_INIT then + Next_ex1_state<=ex1_init1; + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + n_i<=0;rd_ok<='1'; + elsif packet_type = MPI_ACK then + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + n_i <= 0; rd_ok<='0'; + Next_ex1_state <= ex1_send_Ack; + elsif packet_type = MPI_WIN_SYNC then + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + n_i <= 0; rd_ok<='0'; + Next_ex1_state <= ex1_WSynC; + elsif packet_type = MPI_SPAWN then + Next_ex1_state<=ex1_SPAWN; + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + onepop:='1';--il y a une donnée lue + src_address_i<=std_logic_vector(to_unsigned(Core_spawn_adr+1,16)); + rd_ok<='0'; + else -- packet non reconnu + --synthesis translate_off + report "Ex1 : ATTENTION paquet non reconnu !!!!!!!!!" ; + --synthesis translate_on + if fifo_empty = '1' then + Next_ex1_state <= fifo_select; + + else + rd_ok<='1'; + packet_type_i <= fifo_data_out(7 downto 4); --lire le prochain paquet + data_to_send_i <= fifo_data_out; + Next_ex1_state <= decode_packet_type;-- pas necessaire mais plus sure + end if; + end if; + end if; + when fetch_addresses => n_i<=n;rd_ok<='1'; + if fifo_empty = '0' and n = 0 then + src_address_i(15 downto 8) <= fifo_data_out; + n_i <= n + 1; + Next_ex1_state <= fetch_addresses; + elsif fifo_empty = '0' and n = 1 then + src_address_i(7 downto 0) <= fifo_data_out; + n_i <= n + 1; + Next_ex1_state <= fetch_addresses; + elsif fifo_empty = '0' and n = 2 then + dest_address_i(15 downto 8) <= fifo_data_out; + n_i <= n + 1; + Next_ex1_state <= fetch_addresses; + elsif fifo_empty = '0' and n = 3 then + dest_address_i(7 downto 0) <= fifo_data_out; + n_i <= n+1; + elsif n=4 then + rd_ok<='0'; + n_i<=0; + Next_ex1_state <= decode_packet_type2; + elsif fifo_empty='1' then + rd_ok<='0'; + Next_ex1_state <= fetch_addresses; --attendre les données manquantes + else + Next_ex1_state <= fifo_select; + end if; + when decode_packet_type2 => if packet_type = MPI_PUT then + Next_ex1_state <= ex1_put1; + elsif packet_type = MPI_GET then + Next_ex1_state <= ex1_get1; + end if; + -- execution du mpi put + when ex1_put1 => if dma_rd_grant = '1' then + Next_ex1_state <= ex1_put2; + else + Next_ex1_state <= ex1_put1; + end if; + Wr_ok<='0'; + when ex1_put2 =>Wr_ok<='0'; + if switch_port_in_full = '0' and n = 0 then + --envoie du code MPI_PUT + n_i<= n + 1; + wr_ok<='0'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 1 then + data_to_send_i <= p_len; + n_i<= n + 1; + wr_ok<='1'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 2 then + data_to_send_i <= dest_address(15 downto 8); + n_i<= n + 1; + wr_ok<='1'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 3 then + data_to_send_i <= dest_address(7 downto 0); + n_i<= n +1; + wr_ok<='1'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 4 then + p_len_i <= p_len - 4; + -- Next_ex1_state <= ex1_put3; + Wr_ok<='0'; + n_i<=n+1; + elsif n=5 and dma_rd_grant='1' then + Next_ex1_state <= ex1_put3; + n_i<=0; + Wr_ok<='1'; + else + Next_ex1_state <= ex1_put2; + end if; + when ex1_put3 => wr_ok<='0'; + if unsigned(p_len)>0 then + --if n=0 then +-- n_i<=1; --cycle d'attente pour la RAM +-- Wr_ok<='0'; +-- elsif n=1 then + if switch_port_in_full = '0' then + if n=1 then --creer un délai sur ces signaux par rapport à src_adress + p_len_i <= p_len - 1; + Wr_Ok<='1'; + end if; + n_i<=1; + src_address_i <= src_address+1; + Next_ex1_state <= ex1_put3; + + + else + Wr_Ok<='0'; + src_address_i <= src_address; + n_i<=0; + end if; + --elsif n=2 then +-- n_i<=0; --cycle d'attente pour la RAM +-- Wr_ok<='0'; +-- src_address_i <= src_address ; --prochaine lecture +-- +-- end if; + else + Wr_Ok<='0'; + Next_ex1_state <= ex1_put4; + end if; + when ex1_put4 =>rd_ok<='1'; + wr_ok<='0'; + if dma_rd_grant = '1' then -- fin du mpi_put + Next_ex1_state <= ex1_put5; + rd_ok<='0'; + n_i<=0; + data_to_send_i<="00000001"; + else + Next_ex1_state <= ex1_put4; + end if; + + if fifo_src='0' then --détection Put ou Get + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + else + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + end if; + when ex1_put5 => if n >0 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + rd_ok<='0';wr_ok<='0'; + if n=0 then + + n_i<=n+1; + elsif n=1 then + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + dma_wr<='1'; + dma_rd<='1'; + elsif n=2 then + if dma_rd_grant='1' then + n_i<=n+1; + dma_wr<='1'; + tempval:=Ram_data_in; + data_to_send_i<=ram_data_in; + end if; + rd_ok<='1'; + wr_ok<='0'; + + dma_rd<='1'; + elsif n=3 then + dma_rd<='1'; + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_in; + data_to_send_i<=ram_data_in; + --src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + tempval(5):='1'; -- SET du bit DSENT + data_to_send_i(5)<='1'; + if fifo_src='0' then -- c'est un put qui est exécuté + tempval(5):='1'; -- SET du bit DSENT + --data_to_send_i<=ram_data_in or "00100000"; + else -- c'est un Get qui est exécuté + --tempval(2):='1'; -- ne pas annuler le sending après un GET + --data_to_send_i<=ram_data_in or "00000100"; + end if; + --data_to_send_i<=tempval; --A tester + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + dma_rd<='0'; --libérer le bus et revenir en arrière + dma_wr<='0'; + n_i<=0; + end if; + elsif n=4 then + if dma_wr_grant = '1' and dma_rd_grant='1' then + n_i<=n+1; + + --src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + end if; + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='1'; + elsif n=5 then --accusé de réception + if dma_wr_grant = '1' and dma_rd_grant='1' then + n_i<=n+1; + + src_address_i<=std_logic_vector(to_unsigned(core_put_adr+6,16)); + data_to_send_i<="00000001"; + end if; + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='1'; + elsif n=6 then + if dma_wr_grant = '1' then + n_i<=n+1; + + -- SET du bit DSENT + data_to_send_i<="00000001"; + end if; + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='0'; + elsif n=7 then + n_i<=0; + Next_ex1_state <= fifo_select; + rd_ok<='0'; + wr_ok<='0'; + dma_wr<='0'; + dma_rd<='0'; + end if; + + + when ex1_get1 => wr_ok<='0'; + if switch_port_in_full = '0' and n = 0 then -- execution du mpi get + --écrire l'entête de la fonction + n_i<= n + 1; + Wr_ok<='0'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 1 then -- execution du mpi get + data_to_send_i <= "00001000"; -- longueur du paquet sur le réseau ? + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 2 then + data_to_send_i <= "0000"&pid; -- Rang source + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 3 then + data_to_send_i <= p_len; + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 4 then + data_to_send_i <= src_address(15 downto 8); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 5 then + data_to_send_i <= src_address(7 downto 0); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 6 then + data_to_send_i <= dest_address(15 downto 8); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 7 then + data_to_send_i <= dest_address(7 downto 0); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 8 then + Next_ex1_state <= ex1_get2; + n_i<=0; + Wr_ok<='1'; + else + Next_ex1_state <= ex1_get1; + end if; + when ex1_get2 => if dma_wr_grant = '1' then + Next_ex1_state <= ex1_get3; + src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16)); + data_to_send_i<="00000001"; + else + Next_ex1_state <= ex1_get2; + end if; + dma_wr<='1'; + when ex1_send_ack |ex1_Wsync=> rd_ok<='0'; + if n = 0 then -- execution du mpi ack /ou Mpi_Win_sync + if switch_port_in_full = '0' then + + wr_Ok<='0'; --envoie de la première donnée(code ack) + n_i<= n + 1; + onepop:='0'; + + end if; + elsif n = 1 then + if fifo_empty='0' and onepop='0' then + data_to_send_i <=p_len ; + + rd_Ok<='1'; --passe la longueur + onepop:=not onepop; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok<='0'; + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:=not onepop; + n_i<= n + 1; + wr_ok<='1'; + elsif (switch_port_in_full = '1') then + wr_Ok<='0'; + + end if; + + elsif (n= 2) then + if fifo_empty='0' and onepop='0' then + + data_to_send_i <=fifo_data_out; + rd_Ok<='1'; + onepop:=not onepop; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok<='0'; + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:=not onepop; + n_i<= n + 1; + wr_ok<='1'; + else + wr_Ok<='0'; + + end if; + elsif (n= 3) then + if fifo_empty='0' and onepop='0' then + + data_to_send_i <=fifo_data_out; + rd_Ok<='1'; + onepop:=not onepop; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok<='0'; + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:=not onepop; + n_i<= n + 1; + wr_ok<='1'; + + else + wr_Ok<='0'; + + end if; + elsif n = 4 then + n_i<=0; + Wr_Ok<='1'; + rd_ok<='0';--vider le tampon + Next_ex1_state <= fifo_select; + + end if; + + when ex1_get3 =>if n<2 then --ecriture de la fin d'envoie + if dma_wr_grant = '1' then -- fin du post de mpi_get + + n_i<=n+1; + data_to_send_i<="00000001"; + wr_ok<='1'; + rd_ok<='0'; + end if; + + elsif n=2 then + n_i<=0; + Next_ex1_state <= ex1_get4; + end if; + src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16)); + when ex1_get4 => wr_ok<='0'; + rd_ok<='0'; + dma_wr<='1'; + dma_rd<='1'; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + + if n=0 then + + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=1 then + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=2 then + if dma_rd_grant='1' then + n_i<=n+1; + rd_ok<='1'; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + else + n_i<=1; + end if; + + elsif n=3 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_in; + data_to_send_i<=Ram_data_in; + rd_ok<='1'; + wr_ok<='0'; + dma_wr<='1'; + dma_rd<='1'; + else + dma_wr<='0'; + dma_rd<='0'; + n_i<=n-1; + end if; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + elsif n=4 then + if dma_wr_grant = '1' and dma_rd_grant='1' then + n_i<=n+1; + rd_ok<='0'; + wr_ok<='1'; + tempval(6):='1'; --SET du bit Windows Busy --car réception Get + tempval(1):='1'; -- SET du bit DReceiving + data_to_send_i(6)<='1'; + data_to_send_i(1)<='1'; + --data_to_send_i<=tempval; -- à tester absolument !!! + else + rd_ok<='0'; + wr_ok<='1'; + n_i<=1; + end if; + dma_wr<='1'; + dma_rd<='1'; + elsif n=5 then + wr_ok<='1'; + if dma_wr_grant = '1' then + n_i<=n+1; + end if; + elsif n=6 then + n_i<=0; + Next_ex1_state <= fifo_select; + dma_wr<='0'; + dma_rd<='0'; + end if; + + when ex1_spawn => rd_ok<='0'; + if n = 0 then -- execution du mpi spawn + if switch_port_in_full = '0' then + + wr_Ok<='0'; + n_i<= n + 1; + onepop:='0'; + --data_to_send_i<=len; + end if; + elsif n = 1 then + if fifo_empty='0' and onepop='0' then + data_to_send_i <=p_len ; + + rd_Ok<='1'; + onepop:='1'; --une donnée lue il faut arrêter de dépiler + + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:='0'; + n_i<= n + 1; + wr_ok<='1'; + else + wr_Ok<='0'; + + end if; + + elsif (n= 2) or (n=3) then + if fifo_empty='0' and onepop='0' then + + data_to_send_i <=fifo_data_out; + rd_Ok<='1'; + onepop:='1'; --une donnée lue il faut arrêter de dépiler + + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:='0'; + n_i<= n + 1; + wr_ok<='1'; + else + wr_Ok<='0'; + + end if; + elsif n=4 then + n_i<=0; + Wr_Ok<='1'; + rd_ok<='0'; + Next_ex1_state <= fifo_select; + end if; + -- execution du barrier + when ex1_barrier1 => if switch_port_in_full = '0' then + Next_ex1_state <= ex1_barrier2; + else + Next_ex1_state <= ex1_barrier1; + end if; + when ex1_barrier2 => if switch_port_in_full = '0' then + Next_ex1_state <= ex1_barrier3; + else + Next_ex1_state <= ex1_barrier2; + end if; + when ex1_barrier3 => if switch_port_in_full = '0' then + Next_ex1_state <= ex1_barrier4; + else + Next_ex1_state <= ex1_barrier3; + end if; + when ex1_barrier4 => if packet_type = MPI_BARRIER_COMPLETED and pid_counter < nprocs then + pid_counter_i <= pid_counter + 1; + Next_ex1_state <= ex1_barrier1; + else + Next_ex1_state <= fifo_select; + end if; + when ex1_init1 => rd_ok<='0'; + if n=0 then + n_i<=n+1; + Len_i<=len-2; --deux données a été dépilée + elsif n=1 then --vider le fifo instruction + if len>0 then + if fifo_empty='0' then + rd_ok<='1'; + Len_i<=len-1; + + else + rd_ok<='0'; + Len_i<=Len; + end if; + else + n_i<=n+1; + end if; + elsif n=2 then -- + n_i<=0; + rd_ok<='0'; + Next_ex1_state<=ex1_init_run; + + end if; + + when ex1_init_run=> if n=0 then + if snd_start='1' then --le module ex4 veut envoyer des données + + n_i<=n+1; + + for i in 0 to 3 loop + mem_i(i)<=snd_data(i); + end loop; + if snd_data(0)(7 downto 4)=MPI_INIT or + snd_data(0)(7 downto 4)=MPI_SPAWN or + snd_data(0)(7 downto 4)=MPI_ACK then + + else + report "Ex1 : Une instruction inconnue a été envoyé par Ex4 sur le réseau !"; + end if; + P_len_i<=x"04"; + fifo_copy<='0'; + snd_ack1<='0'; + + end if; + if AppInitAck='1' then + Next_ex1_state<=ex1_init2; + end if; + elsif n=1 then + fifo_sel<='0';--pas de rotation du fifo instruction + snd_start1<='1'; + P_len_i<=x"04"; + fifo_copy<='0'; + snd_ack1<='0'; + + n_i<=n+1; + elsif n=2 then + snd_start1<='1'; + if snd_comp='1' then + snd_ack1<='1'; + + snd_start1<='0'; + n_i<=n+1; + end if; + elsif n=3 then + snd_start1<='0'; + snd_ack1<='1'; + fifo_sel<='0'; + if snd_start='0' then --attente l'annulation de l'envoie + n_i<=0; + snd_ack1<='0'; + if run_init='1' then + Next_EX1_state<=fifo_select; + --run_init<='0'; + end if; + end if; + end if; + + + when ex1_init2 => -- écriture dans le registre status reg. + src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16)); + if n=0 then --envoie du message Spawn Ack sur le réseau + if instruction(6)='1' then --Spawned=1 ? + n_i<=1; --envoie du message Spawn à main lib + data_to_send_i<="01010000"; --init+spawn + else + n_i<=4; --écrire le résultat de la fn + data_to_send_i<="00010000"; --init seul + end if; + + elsif n=1 then + n_i<=n+1; + mem_i(0)<=MPI_INIT & x"0"; --répondre au premier + mem_i(1)<=x"04"; + mem_i(2)<=x"00"; + mem_i(3)<=INIT_SPAWN & pid;-- indiquer qui répond au + elsif n=2 then + snd_start1<='1'; + n_i<=n+1; + fifo_copy<='0'; + elsif n=3 then + fifo_copy<='0'; + snd_start1<='1'; + if snd_comp='1' then + snd_ack1<='1'; + snd_start1<='0'; + n_i<=n+1; + end if; + elsif n=4 then --écriture du registre status + dma_wr<='1'; + wr_ok<='1'; + if dma_wr_grant = '1' then -- fin du mpi_init + n_i<=n+1; + end if; + elsif n=5 then + wr_ok<='1'; + dma_wr<='1'; + if dma_wr_grant = '1' then -- fin du mpi_init + n_i<=n+1; + end if; + elsif n=6 then + Next_ex1_state <= ex1_init3; + n_i<=0; + wr_ok<='0'; + end if; + + + when ex1_init3 =>--if AppInitAck='1' then + Next_ex1_state <= fifo_select; + --end if; + when ex1_ready => Next_ex1_state <= fifo_select; + when others => Next_ex1_state <= fifo_select; + end case; + + end process; + + -- sortie de la machine à etat + ex1_fsm_action : process(ex1_state, fifo_empty, switch_port_in_full, p_len,pid, + pid_counter, dma_rd,dma_wr,ram_data_in,AppInitAck,fifo_wr,noc_fifo_in,data_to_send, packet_type, wr_ok,rd_ok, + fifo_rd) + variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0'); + begin +-- code fonctionnel + Result_i<=Result1; + case ex1_state is + when fifo_select => priority_rotation <='1'; -- on peut changer la priorité + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result_i <=(others=>'0'); + Ready<='1'; + when read_status1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result_i <=(others=>'0'); + Ready<='0'; + when read_status2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + status_reg:=Ram_data_in; + Result_i <=(others=>'0'); + Ready<='0'; + when fetch_packet_type => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= (others =>'0'); + AppInitReq<='0'; + switch_port_in_wr_en <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + + when decode_packet_type => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= Data_To_Send; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when fetch_addresses => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when decode_packet_type2 =>priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= packet_type & pid_counter; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= p_len; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= "0000" & pid; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= "0000" & pid; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_get1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= Wr_ok; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + when ex1_get2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <='0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= dma_Wr; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_get3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others=>'0');---??? + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; -- le résultat de l'exécution + Ready<='0'; -- fin du module + Result_i <=(2=>'1',others=>'0');--Get completed + when ex1_get4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; --"00000001"; + Result_i <=(2=>'1',others=>'0'); --get completed + Ready<='0'; -- fin du module + when ex1_put1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_put2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + Ram_rd<='1'; + Ram_wr<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_put3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_data_in; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_put4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_data_in;---??? + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= rd_ok; + dma_wr_request <= wr_ok; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution + --result(1)<='1'; + Result_i <=(1=>'1',others=>'0');--put completed + Ready<='0'; -- fin du module + when ex1_put5 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; --"00000001"; + Result_i <=(1=>'1',others=>'0'); --put completed + Ready<='0'; -- fin du module + when ex1_init1 => priority_rotation <='0'; + if fifo_empty='0' then + fifo_rd_en <= rd_ok; + else + fifo_rd_en<='0'; + end if; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= wr_ok; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='1'; + Result_i <=(others=>'0'); + Ready<='0'; + when ex1_init_run => priority_rotation <='0'; + + fifo_rd_en <= fifo_rd; + + switch_port_in_data <= noc_fifo_in; + switch_port_in_wr_en <= fifo_wr; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='1'; + Result_i <=(others=>'0'); + Ready<='0'; + + when ex1_init2=> priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= noc_fifo_in; + switch_port_in_wr_en <= fifo_wr; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<=wr_ok; + Ram_data_out<=Data_to_send; -- le résultat de l'exécution + Ready<='0'; -- dans le registre status + Result_i <=(others=>'0');-- + when ex1_init3=> priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<='1'; + Ram_data_out<="00010000"; + Ready<='0'; -- fin du module + Result_i<=(0=>'1',others=>'0'); --le résultat de l'initialisation est écrit + + when ex1_spawn => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= Data_to_send; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when ex1_send_ack|ex1_Wsync => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= Data_to_send; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when ex1_ready => + Ready<='1'; -- fin du module + priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Ready<='0'; + + when others => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result_i <=(others=>'0'); + Ready<='0'; + end case; + + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX1_FSM.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX1_FSM.vhd.bak (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX1_FSM.vhd.bak (revision 142) @@ -0,0 +1,1319 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer:GAMOM /KIEGAING +-- +-- Create Date: 08:12:29 06/16/2011 +-- Design Name: +-- Module Name: EX1_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Ce module est chargé de recevoir les instructions du programme MPI et +-- de les exécuter (PUT) il coopère avec EX2 qui reçoit les instructions venant du NoC +-- (GET) +-- +-- Dependencies: +-- +-- Revision: 09/07/2012 +-- Revision 0.03 - File updated +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library NocLib ; +use Work.Packet_type.ALL; +USE ieee.numeric_std.ALL; + + +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX1_FSM is + -- parametres generiques du module : + + + Port ( + --instruction_available : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + instruction : in std_logic_vector(Word-1 downto 0); + instruction_en : in std_logic:='0'; -- active le module instruction + pid : in std_logic_vector(3 downto 0) ; -- id du processeur + nprocs : in std_logic_vector(3 downto 0);-- nombre de processeur du MPSOC - 1 + Result : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module + Ready : out std_logic; --indique la fin de l'éxécution d'une instruction + AppInitReq :out STD_LOGIC:='0'; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic ; -- état de la Lib + -- Accès au Fifo d'instructions + priority_rotation : out STD_LOGIC:='0'; + fifo_rd_en : out STD_LOGIC:='0'; + fifo_empty : in STD_LOGIC; + fifo_data_out : in STD_LOGIC_VECTOR (7 downto 0); + fifo_src : in STD_LOGIC; --permet de désigner le fifo qui est en service + + + Snd_Data : IN Typ_PortIO(0 to 3); + Snd_Start : IN std_logic; + Snd_Ack : OUT std_logic; + + -- Accès au réseau sur puce + switch_port_in_full : in std_logic; + switch_port_in_data : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); + switch_port_in_wr_en : out STD_LOGIC:='0'; + -- Accès à la mémoire RAM du PE + ram_data_in : in std_logic_vector(7 downto 0); + ram_data_out : out std_logic_vector(7 downto 0):=(others=>'0'); + ram_rd,ram_wr : out std_logic:='0'; + ram_address : out std_logic_vector(15 downto 0):=(others=>'0'); + + dma_wr_request : OUT std_logic:='0'; + dma_rd_request : OUT std_logic:='0'; + dma_wr_grant : in STD_LOGIC; + dma_rd_grant : in STD_LOGIC); +end EX1_FSM; + +architecture Behavioral of EX1_FSM is + +component proto_send is +generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée + fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie + fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie + fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée + fifo_in_data_out : in std_logic_vector(Word-1 downto 0); + fifo_out_data_in : out std_logic_vector(Word-1 downto 0); + packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet + copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo + snd_start : in std_logic; --début de la réception + snd_ack :in std_logic; -- acquittement de la réception + snd_comp : out std_logic; -- fin de la réception + mem :in memory(0 to sizemem-1)); --données à copier vers le fifo + + +end component proto_send; +-- definition du type etat pour le codage des etats des fsm +type fsm_states is (fifo_select, fetch_packet_type, decode_packet_type, fetch_addresses, + decode_packet_type2, read_status1,read_status2,ex1_barrier1, ex1_barrier2, ex1_barrier3, ex1_barrier4, + ex1_get1, ex1_get2,ex1_get3,ex1_get4, ex1_put1, ex1_put2, ex1_put3, ex1_put4,ex1_put5, + ex1_init1,ex1_init_run,ex1_init2,ex1_init3,ex1_spawn,ex1_ready,ex1_send_ack,ex1_Wsync); +-- machine a etat du module +signal ex1_state,Next_Ex1_state : fsm_states; + +-- les variables utilisées dans la fsm +signal snd_start1,snd_start_sync,snd_comp,snd_ack1,push:std_logic:='0'; +signal mem,mem_i : memory(0 to 3); +signal data_to_send,data_to_send_i,result_i,result1,noc_fifo_in : std_logic_vector(Word-1 downto 0); +signal packet_type,packet_type_i : std_logic_vector(3 downto 0); +--signal dpid : std_logic_vector(3 downto 0); +signal pid_counter,pid_counter_i : std_logic_vector(3 downto 0); +signal p_len,p_len_i: std_logic_vector(Word-1 downto 0); +signal src_address,src_address_i : std_logic_vector(ADRLEN-1 downto 0); +signal dma_rd,dma_wr,Wr_ok,rd_ok:std_logic:='0'; +--signal res_address : std_logic_vector(15 downto 0); +signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0); +signal n,n_i : natural range 0 to 15; +signal len,len_i : natural range 0 to 255; +signal fifo_rd,fifo_wr,fifo_copy:std_logic:='0'; +signal fifo_sel:std_logic:='0'; +signal run_init,run_init_i:std_logic:='0'; +begin +-- connection des signaux avec les ports +ram_address <= src_address; +result<=Result1; +sw_send: proto_send generic map (sizemem=>4) + port map ( + clk=>clk, + reset=>reset, + fifo_in_empty=>fifo_empty, + fifo_in_full=>'0',--pas utilisé + fifo_out_empty=>'0', + packet_len=>p_len, + copy_mode=>fifo_copy, + fifo_out_full => switch_port_in_full, + fifo_in_rd_en=>fifo_rd, + fifo_in_data_out=>fifo_data_out, +fifo_out_wr_en =>fifo_wr, + + fifo_out_data_in =>noc_fifo_in, + snd_start =>snd_start_sync, + snd_ack =>snd_ack1, + snd_comp=>snd_comp, + mem =>mem + ); +ex1_fsm_sync:process(clk) + + begin + if rising_edge(clk) then + if reset = '1' then + ex1_state <= fifo_select; + n<=0; + len<=0; + p_len<=(others=>'0'); + snd_ack<='0'; + src_address<=(others=>'0'); + dest_address<=(others=>'0'); + run_init<='0'; + else + ex1_state<=next_ex1_state; + n<=n_i; + len<=len_i; + p_len<=p_len_i; + dest_address<=dest_address_i; + Packet_type<=Packet_type_i; + Pid_counter<=Pid_counter_i; + Data_to_send<=Data_to_send_i; + Result1<=Result_i; + run_init<=Run_init_i; + for i in 0 to 3 loop + mem(i)<=mem_i(i); + end loop; + src_address <= src_address_i; + snd_ack<=snd_ack1; --acquittement de l'envoie des données pour EX4 + snd_start_sync<=snd_start1; + end if; + end if; + end process ex1_fsm_sync; +-- processus de transistion entre les etats +fsm_nst_logic : process(ex1_state,n,instruction_en,fifo_empty,fifo_data_out, switch_port_in_full,pid, + pid_counter,len,p_len,snd_start,snd_comp, ram_data_in,dma_rd_grant,dma_wr_grant,AppInitAck,src_address, + fifo_src,dest_address,packet_type,mem,snd_data,run_init,data_to_send) +variable tempval : std_logic_vector(Word-1 downto 0); +variable onepop,fifo_vide : std_logic:='0'; --indique que le fifo a été dépilé +begin + snd_ack1<='0'; + fifo_copy<='0'; + snd_start1<='0'; + n_i<=n; --valeur par défaut + Next_ex1_state <=Ex1_state; + Src_address_i<=src_address; + dest_address_i<=dest_address; + P_len_i<=P_len; + Packet_type_i<=Packet_type; + Pid_counter_i<=Pid_counter; + run_init_i<=Run_init; + Len_i<=Len; + Data_to_send_i<=Data_to_send; + dma_rd<='0'; --attention ceci peut changer le code + dma_wr<='0'; --il faut donc le vérifier + for i in 0 to 3 loop + mem_i(i)<=mem(i); + end loop; + case ex1_state is + when fifo_select => if instruction_en='1' and fifo_empty ='0' then + Next_ex1_state <= fetch_packet_type; + else + Next_ex1_state <= fifo_select; + end if; + rd_ok<='0'; + wr_ok<='0'; + if instruction_en='1' and snd_start='1' then + run_init_i<='1'; + Next_ex1_state<=ex1_init_run; + else + run_init_i<='0'; + end if; + --lecture du registre status de la mib MPI + when read_status1 => if dma_rd_grant = '1' then -- fin du mpi_put + Next_ex1_state <= read_status2; + else + Next_ex1_state <= read_status1; + end if; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16)); + when read_status2 => + Next_ex1_state <= fifo_select; + when fetch_packet_type => rd_ok<='0'; + if fifo_empty ='1' then + Next_ex1_state <= fifo_select; + else + packet_type_i <= fifo_data_out(7 downto 4); + data_to_send_i <= fifo_data_out; + Next_ex1_state <= decode_packet_type; + rd_ok<='1'; + end if; + when decode_packet_type => rd_ok<='0'; + if fifo_empty='0' then + if packet_type = MPI_PUT then + p_len_i <= fifo_data_out + 4; + n_i <= 0;rd_ok<='1'; + Next_ex1_state <= fetch_addresses; + elsif packet_type = MPI_GET then + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i <= fifo_data_out; + n_i <= 0; rd_ok<='1'; + Next_ex1_state <= fetch_addresses; + elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then + p_len_i <= "00000011"; -- = 3 + pid_counter_i <= "0000"; + rd_ok<='1'; + Next_ex1_state <= ex1_barrier1; + elsif packet_type = MPI_INIT then + Next_ex1_state<=ex1_init1; + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + n_i<=0;rd_ok<='1'; + elsif packet_type = MPI_ACK then + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + n_i <= 0; rd_ok<='0'; + Next_ex1_state <= ex1_send_Ack; + elsif packet_type = MPI_WIN_SYNC then + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + n_i <= 0; rd_ok<='0'; + Next_ex1_state <= ex1_WSynC; + elsif packet_type = MPI_SPAWN then + Next_ex1_state<=ex1_SPAWN; + len_i <= to_integer(unsigned(fifo_data_out)); + p_len_i<=fifo_data_out; + onepop:='1';--il y a une donnée lue + src_address_i<=std_logic_vector(to_unsigned(Core_spawn_adr+1,16)); + rd_ok<='0'; + else -- packet non reconnu + --synthesis translate_off + report "Ex1 : ATTENTION paquet non reconnu !!!!!!!!!" ; + --synthesis translate_on + if fifo_empty = '1' then + Next_ex1_state <= fifo_select; + + else + rd_ok<='1'; + packet_type_i <= fifo_data_out(7 downto 4); --lire le prochain paquet + data_to_send_i <= fifo_data_out; + Next_ex1_state <= decode_packet_type;-- pas necessaire mais plus sure + end if; + end if; + end if; + when fetch_addresses => n_i<=n;rd_ok<='1'; + if fifo_empty = '0' and n = 0 then + src_address_i(15 downto 8) <= fifo_data_out; + n_i <= n + 1; + Next_ex1_state <= fetch_addresses; + elsif fifo_empty = '0' and n = 1 then + src_address_i(7 downto 0) <= fifo_data_out; + n_i <= n + 1; + Next_ex1_state <= fetch_addresses; + elsif fifo_empty = '0' and n = 2 then + dest_address_i(15 downto 8) <= fifo_data_out; + n_i <= n + 1; + Next_ex1_state <= fetch_addresses; + elsif fifo_empty = '0' and n = 3 then + dest_address_i(7 downto 0) <= fifo_data_out; + n_i <= n+1; + elsif n=4 then + rd_ok<='0'; + n_i<=0; + Next_ex1_state <= decode_packet_type2; + elsif fifo_empty='1' then + rd_ok<='0'; + Next_ex1_state <= fetch_addresses; --attendre les données manquantes + else + Next_ex1_state <= fifo_select; + end if; + when decode_packet_type2 => if packet_type = MPI_PUT then + Next_ex1_state <= ex1_put1; + elsif packet_type = MPI_GET then + Next_ex1_state <= ex1_get1; + end if; + -- execution du mpi put + when ex1_put1 => if dma_rd_grant = '1' then + Next_ex1_state <= ex1_put2; + else + Next_ex1_state <= ex1_put1; + end if; + Wr_ok<='0'; + when ex1_put2 =>Wr_ok<='0'; + if switch_port_in_full = '0' and n = 0 then + --envoie du code MPI_PUT + n_i<= n + 1; + wr_ok<='0'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 1 then + data_to_send_i <= p_len; + n_i<= n + 1; + wr_ok<='1'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 2 then + data_to_send_i <= dest_address(15 downto 8); + n_i<= n + 1; + wr_ok<='1'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 3 then + data_to_send_i <= dest_address(7 downto 0); + n_i<= n +1; + wr_ok<='1'; + Next_ex1_state <= ex1_put2; + elsif switch_port_in_full = '0' and n = 4 then + p_len_i <= p_len - 4; + -- Next_ex1_state <= ex1_put3; + Wr_ok<='0'; + n_i<=n+1; + elsif n=5 and dma_rd_grant='1' then + Next_ex1_state <= ex1_put3; + n_i<=0; + Wr_ok<='1'; + else + Next_ex1_state <= ex1_put2; + end if; + when ex1_put3 => wr_ok<='0'; + if unsigned(p_len)>0 then + --if n=0 then +-- n_i<=1; --cycle d'attente pour la RAM +-- Wr_ok<='0'; +-- elsif n=1 then + if switch_port_in_full = '0' then + if n=1 then --creer un délai sur ces signaux par rapport à src_adress + p_len_i <= p_len - 1; + Wr_Ok<='1'; + end if; + n_i<=1; + src_address_i <= src_address+1; + Next_ex1_state <= ex1_put3; + + + else + Wr_Ok<='0'; + src_address_i <= src_address; + n_i<=0; + end if; + --elsif n=2 then +-- n_i<=0; --cycle d'attente pour la RAM +-- Wr_ok<='0'; +-- src_address_i <= src_address ; --prochaine lecture +-- +-- end if; + else + Wr_Ok<='0'; + Next_ex1_state <= ex1_put4; + end if; + when ex1_put4 =>rd_ok<='1'; + wr_ok<='0'; + if dma_rd_grant = '1' then -- fin du mpi_put + Next_ex1_state <= ex1_put5; + rd_ok<='0'; + n_i<=0; + data_to_send_i<="00000001"; + else + Next_ex1_state <= ex1_put4; + end if; + + if fifo_src='0' then --détection Put ou Get + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + else + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + end if; + when ex1_put5 => if n >0 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + rd_ok<='0';wr_ok<='0'; + if n=0 then + + n_i<=n+1; + elsif n=1 then + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + dma_wr<='1'; + dma_rd<='1'; + elsif n=2 then + if dma_rd_grant='1' then + n_i<=n+1; + dma_wr<='1'; + tempval:=Ram_data_in; + data_to_send_i<=ram_data_in; + end if; + rd_ok<='1'; + wr_ok<='0'; + + dma_rd<='1'; + elsif n=3 then + dma_rd<='1'; + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_in; + data_to_send_i<=ram_data_in; + --src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + tempval(5):='1'; -- SET du bit DSENT + data_to_send_i(5)<='1'; + if fifo_src='0' then -- c'est un put qui est exécuté + tempval(5):='1'; -- SET du bit DSENT + --data_to_send_i<=ram_data_in or "00100000"; + else -- c'est un Get qui est exécuté + --tempval(2):='1'; -- ne pas annuler le sending après un GET + --data_to_send_i<=ram_data_in or "00000100"; + end if; + --data_to_send_i<=tempval; --A tester + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + dma_rd<='0'; --libérer le bus et revenir en arrière + dma_wr<='0'; + n_i<=0; + end if; + elsif n=3 then + if dma_wr_grant = '1' and dma_rd_grant='1' then + n_i<=n+1; + + --src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + end if; + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='1'; + elsif n=4 then + if dma_wr_grant = '1' and dma_rd_grant='1' then + n_i<=n+1; + + src_address_i<=std_logic_vector(to_unsigned(core_put_adr+6,16)); + data_to_send_i<="00000001"; + end if; + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='1'; + elsif n=5 then + if dma_wr_grant = '1' then + n_i<=n+1; + + -- SET du bit DSENT + data_to_send_i<="00000001"; + end if; + rd_ok<='0'; + wr_ok<='1'; + dma_wr<='1'; + dma_rd<='0'; + elsif n=6 then + n_i<=0; + Next_ex1_state <= fifo_select; + rd_ok<='0'; + wr_ok<='0'; + dma_wr<='0'; + dma_rd<='0'; + end if; + + + when ex1_get1 => wr_ok<='0'; + if switch_port_in_full = '0' and n = 0 then -- execution du mpi get + --écrire l'entête de la fonction + n_i<= n + 1; + Wr_ok<='0'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 1 then -- execution du mpi get + data_to_send_i <= "00001000"; -- longueur du paquet sur le réseau ? + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 2 then + data_to_send_i <= "0000"&pid; -- Rang source + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 3 then + data_to_send_i <= p_len; + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 4 then + data_to_send_i <= src_address(15 downto 8); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 5 then + data_to_send_i <= src_address(7 downto 0); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 6 then + data_to_send_i <= dest_address(15 downto 8); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 7 then + data_to_send_i <= dest_address(7 downto 0); + n_i<= n + 1; + Wr_ok<='1'; + Next_ex1_state <= ex1_get1; + elsif switch_port_in_full = '0' and n = 8 then + Next_ex1_state <= ex1_get2; + n_i<=0; + Wr_ok<='1'; + else + Next_ex1_state <= ex1_get1; + end if; + when ex1_get2 => if dma_wr_grant = '1' then + Next_ex1_state <= ex1_get3; + src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16)); + data_to_send_i<="00000001"; + else + Next_ex1_state <= ex1_get2; + end if; + dma_wr<='1'; + when ex1_send_ack |ex1_Wsync=> rd_ok<='0'; + if n = 0 then -- execution du mpi ack /ou Mpi_Win_sync + if switch_port_in_full = '0' then + + wr_Ok<='0'; --envoie de la première donnée(code ack) + n_i<= n + 1; + onepop:='0'; + + end if; + elsif n = 1 then + if fifo_empty='0' and onepop='0' then + data_to_send_i <=p_len ; + + rd_Ok<='1'; --passe la longueur + onepop:=not onepop; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok<='0'; + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:=not onepop; + n_i<= n + 1; + wr_ok<='1'; + elsif (switch_port_in_full = '1') then + wr_Ok<='0'; + + end if; + + elsif (n= 2) then + if fifo_empty='0' and onepop='0' then + + data_to_send_i <=fifo_data_out; + rd_Ok<='1'; + onepop:=not onepop; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok<='0'; + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:=not onepop; + n_i<= n + 1; + wr_ok<='1'; + else + wr_Ok<='0'; + + end if; + elsif (n= 3) then + if fifo_empty='0' and onepop='0' then + + data_to_send_i <=fifo_data_out; + rd_Ok<='1'; + onepop:=not onepop; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok<='0'; + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:=not onepop; + n_i<= n + 1; + wr_ok<='1'; + + else + wr_Ok<='0'; + + end if; + elsif n = 4 then + n_i<=0; + Wr_Ok<='1'; + rd_ok<='0';--vider le tampon + Next_ex1_state <= fifo_select; + + end if; + + when ex1_get3 =>if n<2 then --ecriture de la fin d'envoie + if dma_wr_grant = '1' then -- fin du post de mpi_get + + n_i<=n+1; + data_to_send_i<="00000001"; + wr_ok<='1'; + rd_ok<='0'; + end if; + + elsif n=2 then + n_i<=0; + Next_ex1_state <= ex1_get4; + end if; + src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16)); + when ex1_get4 => wr_ok<='0'; + rd_ok<='0'; + dma_wr<='1'; + dma_rd<='1'; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + + if n=0 then + + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=1 then + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=2 then + if dma_rd_grant='1' then + n_i<=n+1; + rd_ok<='1'; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + else + n_i<=1; + end if; + + elsif n=3 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_in; + data_to_send_i<=Ram_data_in; + rd_ok<='1'; + wr_ok<='0'; + dma_wr<='1'; + dma_rd<='1'; + else + dma_wr<='0'; + dma_rd<='0'; + n_i<=n-1; + end if; + src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + elsif n=4 then + if dma_wr_grant = '1' and dma_rd_grant='1' then + n_i<=n+1; + rd_ok<='0'; + wr_ok<='1'; + tempval(6):='1'; --SET du bit Windows Busy --car réception Get + tempval(1):='1'; -- SET du bit DReceiving + data_to_send_i(6)<='1'; + data_to_send_i(1)<='1'; + --data_to_send_i<=tempval; -- à tester absolument !!! + else + rd_ok<='0'; + wr_ok<='1'; + n_i<=1; + end if; + dma_wr<='1'; + dma_rd<='1'; + elsif n=5 then + wr_ok<='1'; + if dma_wr_grant = '1' then + n_i<=n+1; + end if; + elsif n=6 then + n_i<=0; + Next_ex1_state <= fifo_select; + dma_wr<='0'; + dma_rd<='0'; + end if; + + when ex1_spawn => rd_ok<='0'; + if n = 0 then -- execution du mpi spawn + if switch_port_in_full = '0' then + + wr_Ok<='0'; + n_i<= n + 1; + onepop:='0'; + --data_to_send_i<=len; + end if; + elsif n = 1 then + if fifo_empty='0' and onepop='0' then + data_to_send_i <=p_len ; + + rd_Ok<='1'; + onepop:='1'; --une donnée lue il faut arrêter de dépiler + + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:='0'; + n_i<= n + 1; + wr_ok<='1'; + else + wr_Ok<='0'; + + end if; + + elsif (n= 2) or (n=3) then + if fifo_empty='0' and onepop='0' then + + data_to_send_i <=fifo_data_out; + rd_Ok<='1'; + onepop:='1'; --une donnée lue il faut arrêter de dépiler + + end if; + + if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1'; + onepop:='0'; + n_i<= n + 1; + wr_ok<='1'; + else + wr_Ok<='0'; + + end if; + elsif n=4 then + n_i<=0; + Wr_Ok<='1'; + rd_ok<='0'; + Next_ex1_state <= fifo_select; + end if; + -- execution du barrier + when ex1_barrier1 => if switch_port_in_full = '0' then + Next_ex1_state <= ex1_barrier2; + else + Next_ex1_state <= ex1_barrier1; + end if; + when ex1_barrier2 => if switch_port_in_full = '0' then + Next_ex1_state <= ex1_barrier3; + else + Next_ex1_state <= ex1_barrier2; + end if; + when ex1_barrier3 => if switch_port_in_full = '0' then + Next_ex1_state <= ex1_barrier4; + else + Next_ex1_state <= ex1_barrier3; + end if; + when ex1_barrier4 => if packet_type = MPI_BARRIER_COMPLETED and pid_counter < nprocs then + pid_counter_i <= pid_counter + 1; + Next_ex1_state <= ex1_barrier1; + else + Next_ex1_state <= fifo_select; + end if; + when ex1_init1 => rd_ok<='0'; + if n=0 then + n_i<=n+1; + Len_i<=len-2; --deux données a été dépilée + elsif n=1 then --vider le fifo instruction + if len>0 then + if fifo_empty='0' then + rd_ok<='1'; + Len_i<=len-1; + + else + rd_ok<='0'; + Len_i<=Len; + end if; + else + n_i<=n+1; + end if; + elsif n=2 then -- + n_i<=0; + rd_ok<='0'; + Next_ex1_state<=ex1_init_run; + + end if; + + when ex1_init_run=> if n=0 then + if snd_start='1' then --le module ex4 veut envoyer des données + + n_i<=n+1; + + for i in 0 to 3 loop + mem_i(i)<=snd_data(i); + end loop; + if snd_data(0)(7 downto 4)=MPI_INIT or + snd_data(0)(7 downto 4)=MPI_SPAWN or + snd_data(0)(7 downto 4)=MPI_ACK then + + else + report "Ex1 : Une instruction inconnue a été envoyé par Ex4 sur le réseau !"; + end if; + P_len_i<=x"04"; + fifo_copy<='0'; + snd_ack1<='0'; + + end if; + if AppInitAck='1' then + Next_ex1_state<=ex1_init2; + end if; + elsif n=1 then + fifo_sel<='0';--pas de rotation du fifo instruction + snd_start1<='1'; + P_len_i<=x"04"; + fifo_copy<='0'; + snd_ack1<='0'; + + n_i<=n+1; + elsif n=2 then + snd_start1<='1'; + if snd_comp='1' then + snd_ack1<='1'; + + snd_start1<='0'; + n_i<=n+1; + end if; + elsif n=3 then + snd_start1<='0'; + snd_ack1<='1'; + fifo_sel<='0'; + if snd_start='0' then --attente l'annulation de l'envoie + n_i<=0; + snd_ack1<='0'; + if run_init='1' then + Next_EX1_state<=fifo_select; + --run_init<='0'; + end if; + end if; + end if; + + + when ex1_init2 => -- écriture dans le registre status reg. + src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16)); + if n=0 then --envoie du message Spawn Ack sur le réseau + if instruction(6)='1' then --Spawned=1 ? + n_i<=1; --envoie du message Spawn à main lib + data_to_send_i<="01010000"; --init+spawn + else + n_i<=4; --écrire le résultat de la fn + data_to_send_i<="00010000"; --init seul + end if; + + elsif n=1 then + n_i<=n+1; + mem_i(0)<=MPI_INIT & x"0"; --répondre au premier + mem_i(1)<=x"04"; + mem_i(2)<=x"00"; + mem_i(3)<=INIT_SPAWN & pid;-- indiquer qui répond au + elsif n=2 then + snd_start1<='1'; + n_i<=n+1; + fifo_copy<='0'; + elsif n=3 then + fifo_copy<='0'; + snd_start1<='1'; + if snd_comp='1' then + snd_ack1<='1'; + snd_start1<='0'; + n_i<=n+1; + end if; + elsif n=4 then --écriture du registre status + dma_wr<='1'; + wr_ok<='1'; + if dma_wr_grant = '1' then -- fin du mpi_init + n_i<=n+1; + end if; + elsif n=5 then + wr_ok<='1'; + dma_wr<='1'; + if dma_wr_grant = '1' then -- fin du mpi_init + n_i<=n+1; + end if; + elsif n=6 then + Next_ex1_state <= ex1_init3; + n_i<=0; + wr_ok<='0'; + end if; + + + when ex1_init3 =>--if AppInitAck='1' then + Next_ex1_state <= fifo_select; + --end if; + when ex1_ready => Next_ex1_state <= fifo_select; + when others => Next_ex1_state <= fifo_select; + end case; + + end process; + + -- sortie de la machine à etat + ex1_fsm_action : process(ex1_state, fifo_empty, switch_port_in_full, p_len,pid, + pid_counter, dma_rd,dma_wr,ram_data_in,AppInitAck,fifo_wr,noc_fifo_in,data_to_send, packet_type, wr_ok,rd_ok, + fifo_rd) + variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0'); + begin +-- code fonctionnel + Result_i<=Result1; + case ex1_state is + when fifo_select => priority_rotation <='1'; -- on peut changer la priorité + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result_i <=(others=>'0'); + Ready<='1'; + when read_status1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result_i <=(others=>'0'); + Ready<='0'; + when read_status2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + status_reg:=Ram_data_in; + Result_i <=(others=>'0'); + Ready<='0'; + when fetch_packet_type => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= (others =>'0'); + AppInitReq<='0'; + switch_port_in_wr_en <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + + when decode_packet_type => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= Data_To_Send; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when fetch_addresses => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when decode_packet_type2 =>priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= packet_type & pid_counter; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= p_len; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= "0000" & pid; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_barrier4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= "0000" & pid; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_get1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= Wr_ok; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + when ex1_get2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <='0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= dma_Wr; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_get3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others=>'0');---??? + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; -- le résultat de l'exécution + Ready<='0'; -- fin du module + Result_i <=(2=>'1',others=>'0');--Get completed + when ex1_get4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; --"00000001"; + Result_i <=(2=>'1',others=>'0'); --get completed + Ready<='0'; -- fin du module + when ex1_put1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_put2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + Ram_rd<='1'; + Ram_wr<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_put3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_data_in; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; -- fin du module + + when ex1_put4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_data_in;---??? + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= rd_ok; + dma_wr_request <= wr_ok; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution + --result(1)<='1'; + Result_i <=(1=>'1',others=>'0');--put completed + Ready<='0'; -- fin du module + when ex1_put5 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; --"00000001"; + Result_i <=(1=>'1',others=>'0'); --put completed + Ready<='0'; -- fin du module + when ex1_init1 => priority_rotation <='0'; + if fifo_empty='0' then + fifo_rd_en <= rd_ok; + else + fifo_rd_en<='0'; + end if; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= wr_ok; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='1'; + Result_i <=(others=>'0'); + Ready<='0'; + when ex1_init_run => priority_rotation <='0'; + + fifo_rd_en <= fifo_rd; + + switch_port_in_data <= noc_fifo_in; + switch_port_in_wr_en <= fifo_wr; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='1'; + Result_i <=(others=>'0'); + Ready<='0'; + + when ex1_init2=> priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= noc_fifo_in; + switch_port_in_wr_en <= fifo_wr; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<=wr_ok; + Ram_data_out<=Data_to_send; -- le résultat de l'exécution + Ready<='0'; -- dans le registre status + Result_i <=(others=>'0');-- + when ex1_init3=> priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<='1'; + Ram_data_out<="00010000"; + Ready<='0'; -- fin du module + Result_i<=(0=>'1',others=>'0'); --le résultat de l'initialisation est écrit + + when ex1_spawn => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= Data_to_send; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when ex1_send_ack|ex1_Wsync => priority_rotation <='0'; + fifo_rd_en <= rd_ok; + switch_port_in_data <= Data_to_send; + switch_port_in_wr_en <= wr_ok; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result_i <=(others=>'0'); + Ready<='0'; + when ex1_ready => + Ready<='1'; -- fin du module + priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Ready<='0'; + + when others => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'0'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result_i <=(others=>'0'); + Ready<='0'; + end case; + + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX2_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX2_FSM.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX2_FSM.vhd (revision 142) @@ -0,0 +1,1747 @@ +---------------------------------------------------------------------------------- +-- Company: GRIIA - ETIS - LIP6 +-- Engineer: GAMOM, KIEGAING +-- +-- Create Date: 01:02:10 06/17/2011 +-- Design Name: +-- Module Name: EX2_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- machine a etat qui execute la reception des packet dans le core mpi +-- Dependencies: +--ss +-- Revision: 26/01/2012 +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +library NocLib ; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.Numeric_std.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use Work.Packet_type.ALL; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX2_FSM is + + generic ( + pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur + nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1 + ); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + + Instruction_en : in std_logic; + + dma_wr_grant : in STD_LOGIC; + dma_wr_request : out STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + ram_rd : out std_logic; + ram_wr : out std_logic; + ram_address : out std_logic_vector(ADRLEN-1 downto 0); + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + + fifo_data : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_wr_en : out STD_LOGIC; + fifo_full : in STD_LOGIC; + Rec_Rdy : OUT std_logic; + Rec_Data : out Typ_PortIO(0 to 3); + Rec_Ack : IN std_logic; + AppRank : in STD_LOGIC_VECTOR(3 downto 0); + AppSize : in STD_LOGIC_VECTOR(3 downto 0); + packet_received : out STD_LOGIC; + packet_ack : in STD_LOGIC; + barrier_completed : out STD_LOGIC; + Ready : Out std_logic; + AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic ; -- état de la Lib + Result : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module + switch_data_available : in STD_LOGIC; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_out_rd_en : out STD_LOGIC + + + + ); +end EX2_FSM; + +architecture Behavioral of EX2_FSM is +--module pour la lecture des données sur le réseau +CONSTANT MSIZE : natural :=4; --taille de la mémoire tampon pour les messages reçu +component Proto_receiv is + generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_empty,fifo_full : in std_logic; + rcv_start : in std_logic; --début de la réception + rcv_ack :in std_logic; -- acquittement de la réception + rcv_comp : out std_logic; -- fin de la réception + pop : out std_logic:='0'; + fifo_out : in std_logic_vector(Word-1 downto 0); + mem :out memory(0 to sizemem-1)); +end component Proto_receiv; + +COMPONENT SetBit + PORT( + clk : IN std_logic; + reset : IN std_logic; + BitMask : IN std_logic_vector(7 downto 0); + BitVal : IN std_logic; + start : in std_logic; + whole : in std_logic; + done : out std_logic; + dma_wr_grant : IN std_logic; + dma_rd_grant : IN std_logic; + Ram_data_in : out std_logic_vector(7 downto 0); + dma_wr_request : OUT std_logic; + dma_rd_request : OUT std_logic; + ram_rd : OUT std_logic; + ram_wr : OUT std_logic; + ram_address : IN std_logic_vector(15 downto 0); + Ram_data_out : in std_logic_vector(7 downto 0) + ); + End component SetBit; +--constante +constant Max_stack : integer:=7;--Le nombre de GET qui peuvent être empilés +-- définition du type etat de la machine à etat +type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2, +fetch_addresses,ex2_spawn1,ex2_spawn2,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4, +ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack1,ex2_ack2,ex2_ack3, + Ex2_WSync,Ex2_WComp,ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4, + ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2,Ex2_Set_Busy); +type fsm_ack is(ack0,ack_readwait,ack_checkwait,ack1,ack2,ack3,ack4,ack5,ack6); +type mem32 is array (natural range <>) of std_logic_vector (31 downto 0); +signal Next_Ex2_state,ex2_state :fsm_states; +signal ack_state,next_ack_state : fsm_ack; +-- +signal mode_get,match_get:std_logic:='0'; +signal mode_get_i,match_get_i:std_logic:='0'; +-- machine a etat du module +signal packet_type, packet_type_i : std_logic_vector(3 downto 0); +signal P_len_i,P_len : std_logic_vector(Word-1 downto 0); +signal barrier_counter,barrier_counter_i : std_logic_vector(3 downto 0); +signal pading_data,data_to_ram,Data_to_ram_i : std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal n,n_i : natural range 0 to 15; +signal dest_address,dest_address_i,ack_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0'); +signal data_to_write_fifo,data_to_write_fifo_i : std_logic_vector(Word-1 downto 0); +--******************************************* +--signaux pour la fonction SetBit +signal sb_BitMask : std_logic_vector(7 downto 0):=(others=>'0'); +signal sb_BitVal,sb_start,sb_done : std_logic:='0'; +signal sb_whole : std_logic:='0'; --écrire le mot entier +signal sb_Ram_data_in : std_logic_vector(7 downto 0); +signal sb_dma_wr_request : std_logic; +signal sb_dma_rd_request : std_logic; +signal sb_ram_rd : std_logic; +signal sb_ram_wr : std_logic; +signal sb_ram_address : std_logic_vector(15 downto 0):=(others=>'0'); +signal sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0'); +-- deuxième module pour set busy bit +signal Set_Wbusy : std_logic:='0'; --choix du Mux +signal GPost_Set,Gpost_Set_i : std_logic:='0'; --indique l'arrivée de Win_Compl + +--********************************************* +signal Ex2_on : std_logic:='0'; +signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; +signal sent_ack, sent_ack_i,wr_ack,instr_ack,Instr_ack_i:std_logic:='0'; --signaux pour la gesion de l'acquittement +signal dest_ack,dest_ack_i:std_logic_vector(3 downto 0) :=(others=>'0'); +signal to_fifo_ack :std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal Result_i,result1 : STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); +--signaux pour l'untilisation du composant de réception +signal rfifo_empty,rfifo_full:std_logic; +signal rcv_start,rcv_comp,rcv_ack:std_logic; +signal rpop:std_logic; +signal initreq,initreq_i:std_logic:='0'; --Requete d'initialisation +--signal mem:memory(0 to Msize-1)); +--jusqu'à 16 Get peuvent être attendus! +signal Wcomp : std_logic:='0'; --indique que tous les transferts sont terminés +signal WStart,WPost,WBUSY, WBUSY_i,RGET,RGET_i: std_logic:='0'; -- +signal Rec_WPost,Rec_WPost_i,GComp,GComp_i, GPost_i,GPost: std_logic_vector(Max_Stack downto 0):=(others=>'0'); +signal Waited_Get,Waited_Get_i : mem32(0 to Max_stack); +Signal Rec_Data_i,Rec_data_q : Typ_PortIO(0 to 3); +signal Get_Instr,Get_instr_i,Put_instr,Put_instr_i :memory(0 to 8); +signal Put_Id : std_logic_vector(31 downto 0):=(others=>'0'); +signal P_G,P_G_i: natural range 0 to 3:=0; --Msg Ack : 1 -> Put, 2-->Get +signal Ptr_Get,Ptr_Get_i : natural range 0 to Max_stack:=0; +signal Received_get,Received_get_i : std_logic_vector(Max_stack downto 0):=(others=>'0');--sera remis à 0 lorsque Wstart/WPost est reçu +begin + +ram_address <= ack_address when instr_ack='1' else dest_address; +--fifo_data <= data_to_write_fifo; +Result<=Result1; +p_instr_fifo:process(ack_state,data_to_write_fifo_i,wr_ack,to_fifo_ack,instr_ack) +begin + if instr_ack='1' then + fifo_data<=to_fifo_ack; +else + fifo_data<=data_to_write_fifo_i; +end if; +end process p_instr_fifo; + + + +R0:proto_receiv generic map (sizemem =>4) + port map ( + clk=>clk, + reset=>reset, + rcv_start=>rcv_start, + rcv_comp=>rcv_comp, + rcv_ack=>rcv_ack, + fifo_empty=>rfifo_empty, + fifo_full=>rfifo_full, + fifo_out=>switch_port_out_data, + pop=>rpop, + mem=>open + + ); +--envoie de l'acquittement +setbit1:SetBit + PORT MAP ( + clk =>clk, + reset =>reset, + BitMask =>sb_bitMask, + BitVal =>sb_bitval, + dma_wr_grant =>dma_wr_grant, + dma_rd_grant =>dma_rd_grant, + Ram_data_in => sb_Ram_data_in, + dma_wr_request =>sb_dma_wr_request, + dma_rd_request =>sb_dma_rd_request, + ram_rd =>sb_ram_rd, + ram_wr =>sb_ram_wr, + ram_address =>dest_address, + Ram_data_out =>sb_ram_data_out, + Start =>sb_start, + whole=>sb_whole, + done =>sb_done + ); + +-- processus de transistion entre les etats +ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized, + switch_data_available,switch_port_out_data,sb_ram_data_in,Data_to_Ram,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len, + sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy,Ptr_Get,Get_Instr,P_G,Waited_get,Received_get,rget,GPost,GPost_Set,packet_type,barrier_counter, + dest_ack,initreq,rec_wpost,Gcomp,rec_data_q,mode_get,match_get,Instr_ack,result1,data_to_write_fifo) +variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée +variable tempval : std_logic_vector(Word-1 downto 0); +variable n_e,i:natural range 0 to 15 :=0; + +--=================================================================- +procedure read_nocdat_fsm(sdata_avail: std_logic; +signal rd,wr:out std_logic; +signal Plen_i : in std_logic_vector(Word-1 downto 0); +signal Plen_o : out std_logic_vector(Word-1 downto 0); +variable n:out natural range 0 to 15;signal n_e:in natural range 0 to 15) is +--lit la suite des données qui sont dans le NoC et identifie le paramètre important +begin +if n_e<3 then + wr<='0'; + if sdata_avail='1' then + n:=n_e+1; + rd<='1'; + plen_o <=plen_i-1; + else + rd<='0'; + end if; + --result_i<=(others=>'0'); + elsif n_e=3 then + if sdata_avail='1' then + n:=n_e+1; + rd<='0'; + --P_len <=P_len_i -1; + --data_to_ram<=sportdout; + --Result_i<=sport_out_data; + else + rd<='0'; + end if; + end if; +end procedure; + +begin + + Next_Ex2_state <= Ex2_state; + Ex2_on<='0'; + sb_whole<='0'; + sb_start<='0'; --valeur par défaut + sb_bitmask<=x"FF"; + sb_bitval<='1'; + dma_rd<='0'; + dma_wr<='0'; + rd_ok<='0'; + wr_ok<='0'; + barrier_counter_i <= barrier_counter; + GPost_Set_i<=GPost_Set; + Rec_WPost_i<=Rec_WPost; + GPost_i<=GPost; + P_G_i<=P_G; + RGET_i<=RGET; + WBUSY_i<=WBUSY; + Result_i<=Result1; + Ptr_get_i<=Ptr_get; + mode_get_i<=mode_get; + data_to_write_fifo_i<=data_to_write_fifo; + match_get_i<=match_get; + GComp_i<=GComp; + Instr_ack_i<=Instr_ack; + received_get_i<=received_get; + mode_get_i<=mode_get; + InitReq_i<=InitReq; + match_get_i<=match_get; + Data_to_ram_i<=Data_to_ram; + dest_address_i<=dest_address; + for i in 0 to Max_stack loop + Waited_get_i(i)<=Waited_get(i); + end loop; + For i in 0 to 7 loop + Get_Instr_i(i)<=Get_instr(i); + end loop; + Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non + n_i<=n; --valeur par défaut de n_i + P_len_i<=P_len; + for i in 0 to 3 loop + Rec_Data_i(i)<=Rec_Data_q(i); + Packet_type_i<=Packet_type; + dest_ack_i<=dest_ack; + end loop; + case ex2_state is + when Ex2_ready => if Instruction_en='1' and switch_data_available='1' then + Next_Ex2_state <= fetch_packet_type; + end if; + rd_ok<='0';wr_ok<='0'; + when fetch_packet_type => if switch_data_available ='1' and Instruction_en='1' then --and initialized ='1' + Next_Ex2_state <= decode_packet_type; + packet_type_i<=switch_port_out_data(7 downto 4); + Dest_ack_i<=switch_port_out_data(3 downto 0); + Rec_Data_i(0)<=switch_port_out_data; --récupérer la première donnée reçue ! + rd_ok<='1'; + else + --Next_Ex2_state <= Ex2_Ready; + rd_ok<='0'; + end if; + n_i<=0; + when decode_packet_type => rd_ok<='0'; + if switch_data_available ='0' then + Next_Ex2_state <= decode_packet_type; + else + rd_ok<='1'; + Rec_Data_i(1)<=switch_port_out_data-2; + if packet_type = MPI_PUT then + P_len_i <= switch_port_out_data - 2; + n_i<=0; + + Next_Ex2_state <= decode_packet_type2; + elsif packet_type = MPI_GET then + P_len_i <=switch_port_out_data-2; + Next_Ex2_state <= decode_packet_type2; + elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then + P_len_i <= switch_port_out_data; + n_i<=0; + Next_Ex2_state <= ex2_barrier1; + elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then + n_i<=0; + wr_ok<='0'; + --rd_ok<='1'; + P_len_i <= switch_port_out_data-2; + Rec_Data_i(1)<=switch_port_out_data; + Next_Ex2_state <= ex2_init1; + elsif packet_type = MPI_ACK then + n_i<=0; + wr_ok<='0'; + rd_ok<='0'; + P_len_i <= switch_port_out_data-2; + Next_Ex2_state <= ex2_ack1; + elsif packet_type = MPI_WIN_SYNC then + n_i<=0; + wr_ok<='0'; + rd_ok<='0'; + P_len_i <= switch_port_out_data-2; + Next_Ex2_state <= ex2_Wsync; + elsif packet_type = MPI_SPAWN then + Next_Ex2_state <= ex2_spawn1; + wr_ok<='0'; + rd_ok<='0'; + else + Next_Ex2_state <= decode_packet_type; + rd_ok<='0'; + end if; + end if; + when decode_packet_type2 => if packet_type = MPI_PUT then + Next_Ex2_state <= fetch_addresses; + else + Next_Ex2_state <= ex2_get1; + end if; + when fetch_addresses => if n=0 then + if switch_data_available = '1' then + dest_address_i(15 downto 8) <= switch_port_out_data; + Rec_data_i(2)<=switch_port_out_data; + n_i <= n + 1; + rd_ok<='1'; + else + rd_ok<='0'; + end if; + elsif n=1 then + if switch_data_available = '1' then + dest_address_i(Word-1 downto 0) <= switch_port_out_data; + Rec_data_i(3)<=switch_port_out_data; + P_len_i <= P_len - 2; + Next_Ex2_state <= ex2_put1; + n_i<=0; + rd_ok<='1'; + else + rd_ok<='0'; + Next_Ex2_state <= fetch_addresses; + end if; + end if; + when ex2_ack1 => rd_ok<='0'; + if n<2 then --réception de l'acquittement. + n_e:=n; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); + n_i<=n_e; + elsif n=2 then + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + + data_to_ram_i<=switch_port_out_data; + Result_i<=switch_port_out_data; + end if; + + elsif n=3 then + n_i<=n+1;P_G_i<=0; + if data_to_ram(7 downto 4)=MPI_PUT then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr,16)); + wr_ok<='1'; + P_G_i<=1; --put ou get + P_len_i<=x"06"; --longueur de l'entête à parcourir + elsif data_to_ram(7 downto 4)=MPI_GET then + Result_i<=data_to_ram; + wr_ok<='1'; -- + P_G_i<=2; --put get + P_len_i<=x"06";--taille de l'instruction en mémoire + dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr,16)); + elsif data_to_ram(7 downto 4)=MPI_SPAWN then + Result_i<=data_to_ram; + wr_ok<='1'; -- + dest_address_i<=std_logic_vector(to_unsigned(Core_Spawn_adr+7,16)); + elsif data_to_ram(7 downto 4)=MPI_INIT then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Core_Init_adr+7,16)); + wr_ok<='1'; -- + -- + else + Result_i<="00000000"; + wr_ok<='0'; -- + n_i<=n; --code inconnu ! + end if; + elsif n=4 then + if P_G=1 or P_G=2 then + Next_ex2_state<=ex2_ack2; + else + Next_ex2_state<=ex2_ack3; + end if; + n_i<=0; + end if; + + when Ex2_ack2 =>if unsigned(p_len)>0 then + If Dma_rd_grant='1' then + if n=0 then + n_i<=n+1; --cycle d'attente pour la RAM + elsif n=1 then + dest_address_i <= dest_address+1; + n_i<=2; + elsif n>=2 then + + --creer un délai sur ces signaux par rapport à src_adress + + n_i<=n+1; + rd_ok<='1'; +-- if n>1 then + dest_address_i <= dest_address+1; + p_len_i <= p_len - 1; + --end if; + Get_Instr_i(n-2)<=Ram_data_out; --deux cycles de retard + Next_ex2_state <= ex2_ack2; + end if; + end if; + dma_rd<='1'; + rd_ok<='1'; + else + if P_G=1 then + dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16)); + else + dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16)); + Waited_get_i(ptr_get)(7 downto 0)<=Get_instr(0); --id + Waited_get_i(ptr_get)(15 downto 8)<=Get_instr(1); --longueur + Waited_get_i(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas + Waited_get_i(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut + RGET_i<='1'; + + Ptr_Get_i<=Ptr_Get+1; --prochain Get à traiter + end if; + Next_ex2_state <= ex2_ack3; + n_i<=0; --suite du process ack + rd_ok<='0'; + dma_rd<='0'; + end if; + +when ex2_ack3 => if n=0 then --set acknowlege bit of the instruction + sb_start<='1'; + sb_bitMask<=x"20";--cinquième bit à un + sb_bitval<='1'; + sb_whole<='0';--Modifier un seul bit ! + if sb_done='1' then + n_i<=1; + sb_start<='0'; + sb_bitval<='0'; + dest_address_i<=dest_address+1; + end if; + + elsif n=1 then + sb_start<='1'; + sb_bitMask<=Rec_Data_q(2); + sb_bitval<='1'; + sb_whole<='1'; + if sb_done='1' then + n_i<=n+1; + sb_start<='0'; + sb_bitval<='0'; + sb_whole<='0'; + end if; + + elsif n=2 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + end if; + + when ex2_Wsync => rd_ok<='0'; + if n<2 then --réception de la synchronisation. + n_e:=n; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); + n_i<=n_e; + elsif n=2 then + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + + data_to_ram_i<=switch_port_out_data; + Result_i<=switch_port_out_data; + end if; + + elsif n=3 then + n_i<=n+1;P_G_i<=0; + if data_to_ram(7 downto 4)=SYNC_WSTART then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); + wr_ok<='1'; + P_G_i<=1; --put ou get + P_len_i<=x"06"; --longueur de l'entête à parcourir + elsif data_to_ram(7 downto 4)=SYNC_WPOST then + Result_i<=data_to_ram; + wr_ok<='1'; -- + P_G_i<=2; --put get + P_len_i<=x"06";--taille de l'instruction en mémoire + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); + elsif data_to_ram(7 downto 4)=SYNC_WWAIT then + Result_i<=data_to_ram; + wr_ok<='1'; -- + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+7,16)); + elsif data_to_ram(7 downto 4)=SYNC_WCOMP then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); + wr_ok<='1'; -- + Next_Ex2_State<=Ex2_WCOMP; + n_i<=0; + else + Result_i<="00000000"; + wr_ok<='0'; -- + n_i<=n; --code inconnu ! + end if; + + end if; + when Ex2_Wcomp => dma_rd<='1'; + rd_ok<='1'; + + if n=0 then + n_i<=n+1; --cycle d'attente pour la RAM + i:=to_integer(unsigned(Rec_Data_q(0)(3 downto 0))); + GComp_i(i)<='1'; + elsif n=1 then + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); + If Dma_rd_grant='1' then + n_i<=2; + end if; + elsif n=2 then + If Dma_rd_grant='1' then + --creer un délai sur ces signaux par rapport à dest_adress + n_i<=n+1; + rd_ok<='1'; + dest_address_i <= dest_address+1; + GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard + + else + n_i<=1; + end if; + elsif n=3 then + If Dma_rd_grant='1' then + --GPost_i(15 downto 8)<=Ram_data_out; --Uncomment if needed + n_i<=n+1; + rd_ok<='1'; + dma_rd<='1'; + end if; + elsif n=4 then + --GPost_i(15 downto 8)<=Ram_data_out; --Uncomment if needed + + rd_ok<='1'; + dma_rd<='1'; + n_i<=n+1; + elsif n=5 then + rd_ok<='0'; + dma_rd<='0'; + n_i<=0; + If GPost=GComp then --le même nombre de post que de COmpleted ? + GPost_Set_i<='1'; + end if; + + Next_ex2_state <= ex2_set_busy; + end if; + + + when ex2_init1 => if n<2 then -- execution du mpi Init + wr_ok<='0'; + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + P_len_i <=P_len-1; + Rec_Data_i(n+2)<=switch_port_out_data; + data_to_ram_i<=switch_port_out_data; + Result_i<=switch_port_out_data; + else + rd_ok<='0'; + n_i<=n; + end if; + result_i<=(others=>'0'); + elsif n=2 then + n_i<=n+1; + rd_ok<='0'; + + elsif n=3 then + rd_ok<='0'; -- normalement plus rien à lire + n_i<=n+1; + if Initialized='1' then + if data_to_ram(7 downto 4)=INIT_SEEKMAIN then + Result_i<=data_to_ram; + InitReq_i<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=INIT_STAT then + Result_i<=data_to_ram; + InitReq_i<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=INIT_REGISTER then + Result_i<=data_to_ram; + InitReq_i<='0'; --permet d'activer Init de Ex_4 + report "Mise à jour des données d'initialisation"; + Next_Ex2_state<=ex2_ready; + n_i<=0; + elsif data_to_ram(7 downto 4)=INIT_SPAWN then + Result_i<=data_to_ram; + InitReq_i<='1'; --permet d'activer Init de Ex_4 + -- il faut mettre à jour l'état de Spawn + else + Result_i<="00000000"; + InitReq_i<='0'; --permet d'activer Init de Ex_4 + end if; + end if; + elsif n=4 then + n_i<=n+1; + elsif n=5 then + if p_len=0 then + Next_Ex2_state<=ex2_init2; + rd_ok<='0'; + else + p_len_i <=p_len -1; + rd_ok<='1'; --vider le tampon de lecture pour ce paquet ! + end if; + + end if; + when ex2_init2=> if n=5 then + if AppInitAck='1' then + n_i<=n+1; + InitReq_i<='0'; + Result_i<="00000001"; -- cette valeur permet d'acquitter la fonction Init + end if; + elsif n=6 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + InitReq_i<='0'; + end if; + + when ex2_put1 => rd_ok<='0'; --ne pas autoriser la lecture du switch + wr_ok<='0'; + dma_rd<='1'; + if n=0 then + if RGET='1' then + Lp: for i in 1 to Max_stack loop -- to Ptr_get normalement + if i<=Ptr_Get then + if waited_get(i-1)(3 downto 0)=rec_data_q(0)(3 downto 0) and + waited_get(i-1)(15 downto 8)=(rec_data_q(1)-2) and + waited_get(i-1)(23 downto 16)=rec_data_q(2) and + waited_get(i-1)(31 downto 24)=rec_data_q(3) then + if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data_q(0)(7 downto 4)=MPI_PUT) then + + match_get_i<='1'; + end if; + else + + end if; + end if; + exit Lp when i= Ptr_get; + end loop Lp; + end if; + + n_i<=1; + elsif n=1 then + if match_get='1' then + n_i<=3; --ne pas envoyer ack dans ce cas + report "GET Détecté ACK pas envoyé dans Ex2 du HCL n°" & image(pid); + else + n_i<=2; + end if; + elsif n=2 then + instr_ack_i<='1'; --activer l'envoie de l'accusé de réception + data_to_write_fifo_i<=to_fifo_ack; + wr_ok<=wr_ack; + if sent_ack='1' then + n_i<=3; + instr_ack_i<='0'; + dma_wr<='1'; + end if; + + elsif n=3 then + dma_wr<='1'; + if dma_wr_grant = '1' then + Next_Ex2_state <= ex2_put2; + data_to_ram_i<=switch_port_out_data; + rd_ok<='0'; + n_i<=0; + delai:=0; + else + Next_Ex2_state <= ex2_put1; + end if; + end if; + when ex2_put2 => rd_ok<='0'; + n_i<=1; + i:=to_integer(unsigned(Rec_Data_q(0)(3 downto 0))); + --Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + if unsigned( P_len) > 0 then + + if switch_data_available = '1' and delai=0 then + delai:=1; --une donné lue + P_len_i <= P_len - 1; + Next_Ex2_state <= ex2_put2; + rd_ok<='1'; + data_to_ram_i<=switch_port_out_data; + end if; + if dma_wr_grant='1' and delai=1 then + -- if n=1 then + wr_ok<='1'; + dest_address_i <= dest_address + 1; + delai:=0;--une donnée écrite + -- else + -- dest_address_i <= dest_address ; + -- end if; + --if delai=1 then + --data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch + --end if; + + else + dest_address_i<=dest_address; + wr_ok<='0'; + n_i<=0; + end if; + + Next_Ex2_state <= ex2_put2; + + else + rd_ok<='0'; + + + if dma_wr_grant='1' and n=1 then + + Next_Ex2_state <= ex2_put3; + Wr_ok<='0'; + n_i<=0; + end if; + end if; + + when ex2_put3 => if dma_rd_grant='1' then + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + Next_Ex2_state <= ex2_put4; + n_i<=0; + rd_ok<='1'; + wr_ok<='0'; + end if; + + when ex2_put4 => if n>0 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + if n=0 then + if RGET='1' then + L1: for i in 1 to Max_stack loop -- to Ptr_get normalement + if i<=Ptr_Get then + if waited_get(i-1)(3 downto 0)=rec_data_q(0)(3 downto 0) and + waited_get(i-1)(15 downto 8)=(rec_data_q(1)-2) and + waited_get(i-1)(23 downto 16)=rec_data_q(2) and + waited_get(i-1)(31 downto 24)=rec_data_q(3) then + if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data_q(0)(7 downto 4)=MPI_PUT) then + received_get_i(i-1)<='1'; + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + mode_get_i<='1'; + match_get_i<='1'; + end if; + else + + end if; + end if; + exit L1 when i= Ptr_get; + end loop L1; + end if; + + n_i<=n+1; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=1 then + if match_get='0' then + i:=to_integer(unsigned(Rec_Data_q(0)(3 downto 0))); + Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + end if; + if dma_rd_grant='1' then + if RGET='1' then --si on est en mode attente d'un Get + RGET_i<='0'; --Supposons tous les Gets reçus ! + test_wcomp:for i in 1 to Max_stack loop --Tous les Get reçus ? + if Ptr_get>=i then + if received_get(i-1)='0' then + RGET_i<='1'; --Non ! + end if; + end if; + exit test_wcomp when i=Ptr_get; + end loop test_wcomp; + + end if; + n_i<=n+1; + rd_ok<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + end if; + elsif n=2 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + tempval(4):='1'; --SET du bit DReceived + if Mode_Get='1' then --si get ack est détecté + tempval(6):=RGET; -- Bit 6 Busy=0 si dernier get reçu !! + mode_get_i<='1'; + end if; + data_to_ram_i<=tempval; + rd_ok<='0'; + wr_ok<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + n_i<=0; + end if; + elsif n=3 then + if dma_wr_grant='1' then + rd_ok<='0'; + wr_ok<='1'; + n_i<=n+1; + end if; + elsif n=4 then + if dma_wr_grant='1' then + rd_ok<='0'; + wr_ok<='1'; + + n_i<=5; + end if; + elsif n=5 then + Next_Ex2_state <= ex2_set_busy; + n_i<=0; + rd_ok<='0'; + wr_ok<='0'; + mode_get_i<='0'; + match_get_i<='0'; + end if; + + + + -- dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction + when ex2_put5 => + Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put + + when ex2_spawn1 => + + if n<2 then + n_e:=n; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); + n_i<=n_e; + Rec_Data_i(2)<=Switch_port_out_data; + elsif n=2 then + Rec_Data_i(3)<=Switch_port_out_data; + Result_i<=Switch_port_out_data; + Data_to_ram_i<=Switch_port_out_data; + n_i<=n+1; + rd_ok<='1'; + elsif n=3 then + if data_to_ram(7 downto 4)=SPAWN_LOAD then + Result_i<=data_to_ram; + wr_ok<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=SPAWN_COMP then + Result_i<=data_to_ram; + wr_ok<='0'; --permet d'activer Init de Ex_4 + + elsif data_to_ram(7 downto 4)=SPAWN_ERR then + Result_i<=data_to_ram; + wr_ok<='0'; --permet d'activer Init de Ex_4 + else + Result_i<=(others=>'0'); + + end if; + n_i<=n+1; + rd_ok<='0'; + elsif n=4 then + wr_ok<='1'; + if AppInitAck='1' then + wr_ok<='0'; + rd_ok<='0'; + n_i<=n+1; + end if; + elsif n=5 then + wr_ok<='0'; + rd_ok<='0'; + n_i<=0; + Next_Ex2_state <=Ex2_Ready; + end if; + when Ex2_Spawn2=> + Next_Ex2_state <=Ex2_Ready; + when ex2_get1 => rd_ok<='0'; --ne pas autoriser la lecture du switch + --ack_state<=next_ack_state; --MAE d'envoie de AR + dma_rd<='1'; + if n=0 then + instr_ack_i<='1'; --activer l'envoie de l'accusé de réception + data_to_write_fifo_i<=to_fifo_ack; + wr_ok<=wr_ack; + if sent_ack='1' then + n_i<=1; + instr_ack_i<='0'; + wr_ok<='0'; + --if switch_data_available='1' then + rd_ok<='0';-- + --P_len<=P_len-1; + --end if; + end if; + + elsif n=1 then + if switch_data_available='1' then + if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo + data_to_write_fifo_i <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put + wr_ok<='1'; + rd_ok<='1'; --autoriser la lecture du crossbar + P_len_i<=P_len-1; + n_i<=n+1; + else + Wr_ok<='0'; + Rd_ok<='0'; + end if; + else + Wr_ok<='0'; + rd_ok<='0'; + end if; + elsif n=2 then + if switch_data_available='1' then + if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo + --data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put + --P_len_i <= P_len-1;--le nombre d'octet qui restent à copier + Next_Ex2_state <= ex2_get2; + wr_ok<='0'; + rd_ok<='0'; --autoriser la lecture du crossbar + n_i<=0; + else + rd_ok<='0'; + wr_ok<='0'; + end if; + else + rd_ok<='0'; + wr_ok<='0'; + end if; + end if; + when ex2_get2 => if P_len>0 then + if fifo_full = '0' and switch_data_available ='1' then + data_to_write_fifo_i <= switch_port_out_data;--la longueur initiale du GET + p_len_i <= P_len - 1; + Next_Ex2_state <= ex2_get2; + wr_ok<='1'; + Rd_ok<='1'; + elsE + + wr_ok<='0'; + Rd_ok<='0'; + END IF; + else + if n=0 then + if fifo_full='0' then + wr_ok<='0';--une impulsion en plus + n_i<=n+1; + Next_Ex2_state <= ex2_get2; + else + wr_ok<='0'; + end if; + + else + Next_Ex2_state <= ex2_get3; + n_i<=0; + wr_ok<='0'; + end if; + rd_ok<='0'; + end if; + i:=to_integer(unsigned(Rec_Data_q(0)(3 downto 0))); + Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + + --préparer en avance l'adresse de lecture/écriture + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_get3 => wr_ok<='0'; + if dma_rd_grant='1' then -- fin du mpi_get + Next_Ex2_state <= ex2_get4; + n_i<=0; + --activer le bit sending du registre de transfert + else + Next_Ex2_state <= ex2_get3; + end if; + + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_get4 => if n <4 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + if n=0 then + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + elsif n=1 then + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + data_to_ram_i<=Ram_data_out; + elsif n=2 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + --tempval(2):='1'; --mise à 1 du Bit DSending + --tempval(5):='0'; --Mise à 0 du Bit Sent + data_to_ram_i(2)<='1'; --mise à 1 du Bit DSending + data_to_ram_i(5)<='0'; --Mise à 0 du Bit Sent + + data_to_ram_i<=tempval; + rd_ok<='1'; + wr_ok<='0'; + else + rd_ok<='1'; + wr_ok<='0'; + n_i<=0; + end if; + + + elsif n=3 then + if dma_wr_grant = '1' then + n_i<=n+1; + rd_ok<='0'; + wr_ok<='1'; + end if; + elsif n=4 then + if dma_wr_grant = '1' then + n_i<=0; + Next_Ex2_state <= Ex2_Ready; -- fin du mpi_get + else + rd_ok<='0'; + wr_ok<='1'; + --n<=n-1; + end if; + end if; + + + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_Set_Busy => if n=0 then --set busy bit of the instruction + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + n_i<=1; + if Gpost_Set='1' then + if (rec_wpost=gpost) and RGET='0' then + Wbusy_i<='0'; + Gpost_Set_i<='0'; + GComp_i<=(others=>'0'); + rec_wpost_i<=(others=>'0');--reset des messages reçu + else + Wbusy_i<='1'; + end if; + else + + n_i<=2; + end if; + if RGET='1' then + WBusy_i<='1'; + end if; + elsif n=1 then + sb_start<='1'; + sb_bitMask<=x"40";--6e bit à 1 + sb_bitval<=WBusy; + if sb_done='1' then + n_i<=2; + sb_start<='0'; + sb_bitval<='0'; + end if; + elsif n=2 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + end if; + -- execution du barrier + when ex2_barrier1 => if switch_data_available = '1' then + pading_data <= switch_port_out_data; + Next_Ex2_state <= ex2_barrier2; + else + Next_Ex2_state <= ex2_barrier1; + end if; + when ex2_barrier2 => if packet_type = MPI_BARRIER_REACHED then + barrier_counter_i <= barrier_counter + 1; + Next_Ex2_state <= ex2_barrier4; + else + Next_Ex2_state <= ex2_barrier3; + end if; + when ex2_barrier3 => if n < 10 then + n_i<= n + 1; + Next_Ex2_state <= ex2_barrier3; + else + Next_Ex2_state <= Ex2_Ready; + end if; + when ex2_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED + data_to_write_fifo_i <= MPI_BARRIER_COMPLETED & "0000"; + Next_Ex2_state <= ex2_barrier5; + else + Next_Ex2_state <= Ex2_Ready; + end if; + when ex2_barrier5 => if fifo_full = '0' then -- taille du packet MPI_BARRIER_COMPLETED + data_to_write_fifo_i <= "00000011"; + Next_Ex2_state <= ex2_barrier6; + else + Next_Ex2_state <= ex2_barrier5; + end if; + when ex2_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED + data_to_write_fifo_i <= "00000000"; + Next_Ex2_state <= ex2_barrier7; + else + Next_Ex2_state <= ex2_barrier6; + end if; + when ex2_barrier7 => if fifo_full = '0' then + barrier_counter_i <= "0000"; + Next_Ex2_state <= Ex2_Ready; + else + Next_Ex2_state <= ex2_barrier7; + end if; + + when others => Next_Ex2_state <= Ex2_Ready; + end case; + + end process; + + -- sortie de la machine à etat +-- + ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram,Dma_rd,Dma_wr, + switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request, + appInitAck,n,InitReq) + variable transact : std_logic_vector(Word-1 downto 0); + begin +-- code fonctionnel + sb_ram_data_out<=Ram_data_out; --presque toujours cette valeur + case Ex2_state is + when Ex2_Ready => fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='1'; + AppInitReq<='0'; + when fetch_packet_type => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='0'; + AppInitReq<='0'; + + + when decode_packet_type => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when decode_packet_type2 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + when fetch_addresses => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + when ex2_ack1 |ex2_Wsync => + Ready<='0'; + switch_port_out_rd_en<=rd_ok; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when ex2_ack2|Ex2_WCOMP => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= dma_rd; + dma_wr_request <= '0'; + Ram_rd<=rd_ok; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + when ex2_ack3 => + Ready<='0'; + switch_port_out_rd_en<=rd_ok; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when ex2_put1 => fifo_wr_en <= wr_ok; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= dma_wr; + dma_rd_request <= dma_rd; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_put2 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <=rd_ok; + + if rd_ok = '1' then + + Ram_data_in<=switch_port_out_data; + else + Ram_data_in<=data_to_ram; + end if; + Ram_wr<=wr_ok; + Ram_rd<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + when ex2_put3 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + --ne pas corrompre le contenu de la RAM + --Ram_data_in<=data_to_ram; + Ram_wr<='0'; + Ram_rd<='1'; + packet_received <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + + when ex2_put4 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <= '0'; + packet_received <= '1'; + dma_rd_request <= dma_rd; + dma_wr_request <=dma_wr; + Ram_wr<=wr_ok; + Ram_rd<=rd_ok; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_in<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution + + when ex2_put5 => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_in<=data_to_ram; + --Result <=(1=>'1',others=>'0'); --put completed + + when ex2_get1=> fifo_wr_en <= wr_ok; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= dma_rd; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_get2 => + switch_port_out_rd_en <=rd_ok; + fifo_wr_en <= Wr_ok; + Ready<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + + when ex2_get3 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <= '0'; + packet_received <= '1'; + dma_rd_request <= '1'; + dma_wr_request <='0'; + Ram_wr<='0'; + Ram_rd<='1'; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + --Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending + + when ex2_get4 => + Ready<='0'; + barrier_completed <= '0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '1'; + AppInitReq<='0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_in<=data_to_ram; --activer le bit DSending + + + when ex2_barrier1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + Ready<='0'; + AppInitReq<='0'; + + when ex2_barrier2 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + + when ex2_barrier3 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + Ready<='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '1'; + AppInitReq<='0'; + + when ex2_barrier4 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + + when ex2_barrier5 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_barrier6 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_barrier7 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_spawn1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok;--switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ready<='0'; + Ram_data_in<=(others =>'0'); + AppInitReq<=wr_ok; + when ex2_Spawn2 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + + Ram_data_in<=data_to_ram; + + Ram_wr<=wr_ok; + Ram_rd<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + when ex2_init1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok;--switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ready<='0'; + Ram_data_in<=(others =>'0'); + AppInitReq<=InitReq; + + + when ex2_init2 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ram_data_in<=(others =>'0'); + AppInitReq<= not(AppInitAck); + Ready<='0'; + + + when ex2_Set_Busy => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when others => Ready<='1'; -- le module est à nouveau libre + fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='1'; + AppInitReq<='0'; + end case; + + end process; + + ex2_fsm_sync:process(clk,reset) + + begin + + if reset = '1' then + ex2_state <= Ex2_Ready; + ack_state<=ack0; --MAE d'envoie de AR + n<=0; + P_len<=(others=>'0'); + GPost<=(others =>'0'); + Packet_type<=(others =>'0'); + P_G<=0; + Result1<=(others =>'0'); --juste une copie + dest_address <= (others =>'0'); + + WBUSY<='0'; + RGET<='0'; + InitReq<='0'; + mode_get<='0'; + match_get<='0'; + Sent_ack<='0'; + Instr_ack<='0'; + Ptr_Get<=0; + Rec_Wpost<=(others =>'0'); + dest_ack<=(others =>'0'); + For i in 0 to Max_stack loop + Waited_get(i)<=(others =>'0'); + end loop; + For i in 0 to 7 loop + Get_Instr(i)<=(others =>'0'); + end loop; + for i in 0 to 3 loop + Rec_Data_q(i)<=(others =>'0'); + end loop; + else + if rising_edge(clk) then + ex2_state<=next_ex2_state; + ack_state<=next_ack_state; --MAE d'envoie de AR + n<=n_i; + P_len<=P_len_i; + Packet_type<=packet_type_i; + P_G<=P_G_i; + Result1<=Result_i; --juste une copie + dest_address <= dest_address_i; + data_to_write_fifo<=data_to_write_fifo_i; + WBUSY<=WBUSY_i; + RGET<=RGET_i; + InitReq<=InitReq_i; + mode_get<=mode_get_i; + match_get<=match_get_i; + Sent_ack<=sent_ack_i; + Instr_ack<=Instr_ack_i; + Ptr_Get<=Ptr_Get_i; + Rec_Wpost<=Rec_WPost_i; + dest_ack<=dest_ack_i; + barrier_counter<=barrier_counter_i; + GPost<=GPost_i; + GComp<=GComp_i; + Received_get<=Received_get_i; + GPost_set<=GPost_Set_i; + data_to_ram<=data_to_ram_i; + For i in 0 to Max_stack loop + Waited_get(i)<=Waited_get_i(i); + end loop; + For i in 0 to 7 loop + Get_Instr(i)<=Get_instr_i(i); + end loop; + for i in 0 to 3 loop + Rec_Data_q(i)<=Rec_Data_i(i); + Rec_Data(i)<=Rec_data_i(i); + end loop; + end if; + end if; + end process ex2_fsm_sync; +snd_ack:process (ack_state,reset,fifo_full,instr_ack,Dest_Ack,apprank,Packet_type,ram_data_out,dma_rd_grant) +--ce processus est chargé d'emettre l'accusé de réception pour chaque instruction reçu +begin +-- if rising_edge(clk) then + Sent_ack_i<='0'; --pas besoin de le mémoriser + wr_ack<='0'; --valeur par défaut + ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); + if reset='1' then + next_ack_state<=ack0; + to_fifo_ack<=(others=>'1'); + else + next_ack_state<=ack_state; + + case ack_state is + when ack0 =>to_fifo_ack<=(others=>'0'); + Wr_ack<='0'; + if instr_ack='1' then + next_ack_state<=ack_readwait; + to_fifo_ack <= MPI_ACK & Dest_ack; + wr_ack<='0'; + end if; + + sent_ack_i<='0'; + when ack_readwait => to_fifo_ack <= MPI_ACK & Dest_ack; + ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); + --vérifier WinPost attend bien une action de cette source + if dma_rd_grant='1' then + next_ack_state<=ack_checkwait; + end if; + when ack_checkwait => to_fifo_ack <= MPI_ACK & Dest_ack; + ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); + if dma_rd_grant='1' and ram_data_out(conv_integer(dest_ack))='1' then + next_ack_state<=ack1; + elsif dma_rd_grant='0' then + next_ack_state<=ack_readwait; + else + next_ack_state<=ack6; --pas d'acknowledge à envoyer + assert true report "Packet non attendu de cette source !" + severity failure; + end if; + when ack1 => if fifo_full = '0' then -- conversion envoie lack à l'emetteur + -- en empilement dans le fifo + to_fifo_ack <= MPI_ACK & Dest_ack; + next_ack_state <= ack2; + wr_ack<='1'; + else + wr_ack<='0'; + end if; + sent_ack_i<='0'; + to_fifo_ack <= MPI_ACK & Dest_ack; + when ack2 => if fifo_full = '0' then + to_fifo_ack <= "00000100";--la longueur + + next_ack_state <= ack3; + wr_ack<='1'; + else -- + next_ack_state <= ack2; + wr_ack<='0'; + + end if; + to_fifo_ack <= "00000100"; + sent_ack_i<='0'; + when ack3 => if fifo_full = '0' then + to_fifo_ack <= "00000000";-- + next_ack_state <= ack4; + wr_ack<='1'; + else -- + next_ack_state <= ack3; + wr_ack<='0'; + + end if; + to_fifo_ack <= "00000000"; + sent_ack_i<='0'; + when ack4 => if fifo_full = '0' then + to_fifo_ack <=packet_type & apprank ;--l'instruction et le rang de lacquitteur + next_ack_state <= ack5; + wr_ack<='1'; + sent_ack_i<='0'; + else -- + next_ack_state <= ack4; + wr_ack<='0'; + sent_ack_i<='0'; + end if; + to_fifo_ack <=packet_type & apprank ; + when ack5 => if Instr_ack='0' then --dernier pulse + next_ack_state <= ack0; + else + next_ack_state <= ack6; + end if; + wr_ack<='0'; + sent_ack_i<='1'; + to_fifo_ack<=(others=>'1'); + when ack6 => if Instr_ack='0' then + next_ack_state <= ack0; + + end if; + wr_ack<='0'; + sent_ack_i<='1'; + to_fifo_ack<=(others=>'1'); +end case; +end if; +--end if; +end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX2_FSM.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX2_FSM.vhd.bak (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX2_FSM.vhd.bak (revision 142) @@ -0,0 +1,1746 @@ +---------------------------------------------------------------------------------- +-- Company: GRIIA - ETIS - LIP6 +-- Engineer: GAMOM, KIEGAING +-- +-- Create Date: 01:02:10 06/17/2011 +-- Design Name: +-- Module Name: EX2_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- machine a etat qui execute la reception des packet dans le core mpi +-- Dependencies: +--ss +-- Revision: 26/01/2012 +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +library NocLib ; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.Numeric_std.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use Work.Packet_type.ALL; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX2_FSM is + + generic ( + pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur + nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1 + ); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + + Instruction_en : in std_logic; + + dma_wr_grant : in STD_LOGIC; + dma_wr_request : out STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + ram_rd : out std_logic; + ram_wr : out std_logic; + ram_address : out std_logic_vector(ADRLEN-1 downto 0); + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + + fifo_data : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_wr_en : out STD_LOGIC; + fifo_full : in STD_LOGIC; + Rec_Rdy : OUT std_logic; + Rec_Data : buffer Typ_PortIO(0 to 3); + Rec_Ack : IN std_logic; + AppRank : in STD_LOGIC_VECTOR(3 downto 0); + AppSize : in STD_LOGIC_VECTOR(3 downto 0); + packet_received : out STD_LOGIC; + packet_ack : in STD_LOGIC; + barrier_completed : out STD_LOGIC; + Ready : Out std_logic; + AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic ; -- état de la Lib + Result : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module + switch_data_available : in STD_LOGIC; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_out_rd_en : out STD_LOGIC + + + + ); +end EX2_FSM; + +architecture Behavioral of EX2_FSM is +--module pour la lecture des données sur le réseau +CONSTANT MSIZE : natural :=4; --taille de la mémoire tampon pour les messages reçu +component Proto_receiv is + generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_empty,fifo_full : in std_logic; + rcv_start : in std_logic; --début de la réception + rcv_ack :in std_logic; -- acquittement de la réception + rcv_comp : out std_logic; -- fin de la réception + pop : out std_logic:='0'; + fifo_out : in std_logic_vector(Word-1 downto 0); + mem :out memory(0 to sizemem-1)); +end component Proto_receiv; + +COMPONENT SetBit + PORT( + clk : IN std_logic; + reset : IN std_logic; + BitMask : IN std_logic_vector(7 downto 0); + BitVal : IN std_logic; + start : in std_logic; + whole : in std_logic; + done : out std_logic; + dma_wr_grant : IN std_logic; + dma_rd_grant : IN std_logic; + Ram_data_in : out std_logic_vector(7 downto 0); + dma_wr_request : OUT std_logic; + dma_rd_request : OUT std_logic; + ram_rd : OUT std_logic; + ram_wr : OUT std_logic; + ram_address : IN std_logic_vector(15 downto 0); + Ram_data_out : in std_logic_vector(7 downto 0) + ); + End component SetBit; +--constante +constant Max_stack : integer:=7;--Le nombre de GET qui peuvent être empilés +-- définition du type etat de la machine à etat +type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2, +fetch_addresses,ex2_spawn1,ex2_spawn2,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4, +ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack1,ex2_ack2,ex2_ack3, + Ex2_WSync,Ex2_WComp,ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4, + ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2,Ex2_Set_Busy); +type fsm_ack is(ack0,ack_readwait,ack_checkwait,ack1,ack2,ack3,ack4,ack5,ack6); +type mem32 is array (natural range <>) of std_logic_vector (31 downto 0); +signal Next_Ex2_state,ex2_state :fsm_states; +signal ack_state,next_ack_state : fsm_ack; +-- +signal mode_get,match_get:std_logic:='0'; +signal mode_get_i,match_get_i:std_logic:='0'; +-- machine a etat du module +signal packet_type, packet_type_i : std_logic_vector(3 downto 0); +signal P_len_i,P_len : std_logic_vector(Word-1 downto 0); +signal barrier_counter,barrier_counter_i : std_logic_vector(3 downto 0); +signal pading_data,data_to_ram,Data_to_ram_i : std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal n,n_i : natural range 0 to 15; +signal dest_address,dest_address_i,ack_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0'); +signal data_to_write_fifo,data_to_write_fifo_i : std_logic_vector(Word-1 downto 0); +--******************************************* +--signaux pour la fonction SetBit +signal sb_BitMask : std_logic_vector(7 downto 0):=(others=>'0'); +signal sb_BitVal,sb_start,sb_done : std_logic:='0'; +signal sb_whole : std_logic:='0'; --écrire le mot entier +signal sb_Ram_data_in : std_logic_vector(7 downto 0); +signal sb_dma_wr_request : std_logic; +signal sb_dma_rd_request : std_logic; +signal sb_ram_rd : std_logic; +signal sb_ram_wr : std_logic; +signal sb_ram_address : std_logic_vector(15 downto 0):=(others=>'0'); +signal sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0'); +-- deuxième module pour set busy bit +signal Set_Wbusy : std_logic:='0'; --choix du Mux +signal GPost_Set,Gpost_Set_i : std_logic:='0'; --indique l'arrivée de Win_Compl + +--********************************************* +signal Ex2_on : std_logic:='0'; +signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; +signal sent_ack, sent_ack_i,wr_ack,instr_ack,Instr_ack_i:std_logic:='0'; --signaux pour la gesion de l'acquittement +signal dest_ack,dest_ack_i:std_logic_vector(3 downto 0) :=(others=>'0'); +signal to_fifo_ack :std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal Result_i,result1 : STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); +--signaux pour l'untilisation du composant de réception +signal rfifo_empty,rfifo_full:std_logic; +signal rcv_start,rcv_comp,rcv_ack:std_logic; +signal rpop:std_logic; +signal initreq,initreq_i:std_logic:='0'; --Requete d'initialisation +--signal mem:memory(0 to Msize-1)); +--jusqu'à 16 Get peuvent être attendus! +signal Wcomp : std_logic:='0'; --indique que tous les transferts sont terminés +signal WStart,WPost,WBUSY, WBUSY_i,RGET,RGET_i: std_logic:='0'; -- +signal Rec_WPost,Rec_WPost_i,GComp,GComp_i, GPost_i,GPost: std_logic_vector(Max_Stack downto 0):=(others=>'0'); +signal Waited_Get,Waited_Get_i : mem32(0 to Max_stack); +Signal Rec_Data_i : Typ_PortIO(0 to 3); +signal Get_Instr,Get_instr_i,Put_instr,Put_instr_i :memory(0 to 8); +signal Put_Id : std_logic_vector(31 downto 0):=(others=>'0'); +signal P_G,P_G_i: natural range 0 to 3:=0; --Msg Ack : 1 -> Put, 2-->Get +signal Ptr_Get,Ptr_Get_i : natural range 0 to Max_stack:=0; +signal Received_get,Received_get_i : std_logic_vector(Max_stack downto 0):=(others=>'0');--sera remis à 0 lorsque Wstart/WPost est reçu +begin + +ram_address <= ack_address when instr_ack='1' else dest_address; +--fifo_data <= data_to_write_fifo; +Result<=Result1; +p_instr_fifo:process(ack_state,data_to_write_fifo_i,wr_ack,to_fifo_ack,instr_ack) +begin + if instr_ack='1' then + fifo_data<=to_fifo_ack; +else + fifo_data<=data_to_write_fifo_i; +end if; +end process p_instr_fifo; + + + +R0:proto_receiv generic map (sizemem =>4) + port map ( + clk=>clk, + reset=>reset, + rcv_start=>rcv_start, + rcv_comp=>rcv_comp, + rcv_ack=>rcv_ack, + fifo_empty=>rfifo_empty, + fifo_full=>rfifo_full, + fifo_out=>switch_port_out_data, + pop=>rpop, + mem=>open + + ); +--envoie de l'acquittement +setbit1:SetBit + PORT MAP ( + clk =>clk, + reset =>reset, + BitMask =>sb_bitMask, + BitVal =>sb_bitval, + dma_wr_grant =>dma_wr_grant, + dma_rd_grant =>dma_rd_grant, + Ram_data_in => sb_Ram_data_in, + dma_wr_request =>sb_dma_wr_request, + dma_rd_request =>sb_dma_rd_request, + ram_rd =>sb_ram_rd, + ram_wr =>sb_ram_wr, + ram_address =>dest_address, + Ram_data_out =>sb_ram_data_out, + Start =>sb_start, + whole=>sb_whole, + done =>sb_done + ); + +-- processus de transistion entre les etats +ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized, + switch_data_available,switch_port_out_data,sb_ram_data_in,Data_to_Ram,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len, + sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy,Ptr_Get,Get_Instr,P_G,Waited_get,Received_get,rget,GPost,GPost_Set,packet_type,barrier_counter, + dest_ack,initreq,rec_wpost,Gcomp,rec_data,mode_get,match_get,Instr_ack,result1,data_to_write_fifo) +variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée +variable tempval : std_logic_vector(Word-1 downto 0); +variable n_e,i:natural range 0 to 15 :=0; + +--=================================================================- +procedure read_nocdat_fsm(sdata_avail: std_logic; +signal rd,wr:out std_logic; +signal Plen_i : in std_logic_vector(Word-1 downto 0); +signal Plen_o : out std_logic_vector(Word-1 downto 0); +variable n:out natural range 0 to 15;signal n_e:in natural range 0 to 15) is +--lit la suite des données qui sont dans le NoC et identifie le paramètre important +begin +if n_e<3 then + wr<='0'; + if sdata_avail='1' then + n:=n_e+1; + rd<='1'; + plen_o <=plen_i-1; + else + rd<='0'; + end if; + --result_i<=(others=>'0'); + elsif n_e=3 then + if sdata_avail='1' then + n:=n_e+1; + rd<='0'; + --P_len <=P_len_i -1; + --data_to_ram<=sportdout; + --Result_i<=sport_out_data; + else + rd<='0'; + end if; + end if; +end procedure; + +begin + + Next_Ex2_state <= Ex2_state; + Ex2_on<='0'; + sb_whole<='0'; + sb_start<='0'; --valeur par défaut + sb_bitmask<=x"FF"; + sb_bitval<='1'; + dma_rd<='0'; + dma_wr<='0'; + rd_ok<='0'; + wr_ok<='0'; + barrier_counter_i <= barrier_counter; + GPost_Set_i<=GPost_Set; + Rec_WPost_i<=Rec_WPost; + GPost_i<=GPost; + P_G_i<=P_G; + RGET_i<=RGET; + WBUSY_i<=WBUSY; + Result_i<=Result1; + Ptr_get_i<=Ptr_get; + mode_get_i<=mode_get; + data_to_write_fifo_i<=data_to_write_fifo; + match_get_i<=match_get; + GComp_i<=GComp; + Instr_ack_i<=Instr_ack; + received_get_i<=received_get; + mode_get_i<=mode_get; + InitReq_i<=InitReq; + match_get_i<=match_get; + Data_to_ram_i<=Data_to_ram; + dest_address_i<=dest_address; + for i in 0 to Max_stack loop + Waited_get_i(i)<=Waited_get(i); + end loop; + For i in 0 to 7 loop + Get_Instr_i(i)<=Get_instr(i); + end loop; + Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non + n_i<=n; --valeur par défaut de n_i + P_len_i<=P_len; + for i in 0 to 3 loop + Rec_Data_i(i)<=Rec_Data(i); + Packet_type_i<=Packet_type; + dest_ack_i<=dest_ack; + end loop; + case ex2_state is + when Ex2_ready => if Instruction_en='1' and switch_data_available='1' then + Next_Ex2_state <= fetch_packet_type; + end if; + rd_ok<='0';wr_ok<='0'; + when fetch_packet_type => if switch_data_available ='1' and Instruction_en='1' then --and initialized ='1' + Next_Ex2_state <= decode_packet_type; + packet_type_i<=switch_port_out_data(7 downto 4); + Dest_ack_i<=switch_port_out_data(3 downto 0); + Rec_Data_i(0)<=switch_port_out_data; --récupérer la première donnée reçue ! + rd_ok<='1'; + else + --Next_Ex2_state <= Ex2_Ready; + rd_ok<='0'; + end if; + n_i<=0; + when decode_packet_type => rd_ok<='0'; + if switch_data_available ='0' then + Next_Ex2_state <= decode_packet_type; + else + rd_ok<='1'; + Rec_Data_i(1)<=switch_port_out_data-2; + if packet_type = MPI_PUT then + P_len_i <= switch_port_out_data - 2; + n_i<=0; + + Next_Ex2_state <= decode_packet_type2; + elsif packet_type = MPI_GET then + P_len_i <=switch_port_out_data-2; + Next_Ex2_state <= decode_packet_type2; + elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then + P_len_i <= switch_port_out_data; + n_i<=0; + Next_Ex2_state <= ex2_barrier1; + elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then + n_i<=0; + wr_ok<='0'; + --rd_ok<='1'; + P_len_i <= switch_port_out_data-2; + Rec_Data_i(1)<=switch_port_out_data; + Next_Ex2_state <= ex2_init1; + elsif packet_type = MPI_ACK then + n_i<=0; + wr_ok<='0'; + rd_ok<='0'; + P_len_i <= switch_port_out_data-2; + Next_Ex2_state <= ex2_ack1; + elsif packet_type = MPI_WIN_SYNC then + n_i<=0; + wr_ok<='0'; + rd_ok<='0'; + P_len_i <= switch_port_out_data-2; + Next_Ex2_state <= ex2_Wsync; + elsif packet_type = MPI_SPAWN then + Next_Ex2_state <= ex2_spawn1; + wr_ok<='0'; + rd_ok<='0'; + else + Next_Ex2_state <= decode_packet_type; + rd_ok<='0'; + end if; + end if; + when decode_packet_type2 => if packet_type = MPI_PUT then + Next_Ex2_state <= fetch_addresses; + else + Next_Ex2_state <= ex2_get1; + end if; + when fetch_addresses => if n=0 then + if switch_data_available = '1' then + dest_address_i(15 downto 8) <= switch_port_out_data; + Rec_data_i(2)<=switch_port_out_data; + n_i <= n + 1; + rd_ok<='1'; + else + rd_ok<='0'; + end if; + elsif n=1 then + if switch_data_available = '1' then + dest_address_i(Word-1 downto 0) <= switch_port_out_data; + Rec_data_i(3)<=switch_port_out_data; + P_len_i <= P_len - 2; + Next_Ex2_state <= ex2_put1; + n_i<=0; + rd_ok<='1'; + else + rd_ok<='0'; + Next_Ex2_state <= fetch_addresses; + end if; + end if; + when ex2_ack1 => rd_ok<='0'; + if n<2 then --réception de l'acquittement. + n_e:=n; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); + n_i<=n_e; + elsif n=2 then + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + + data_to_ram_i<=switch_port_out_data; + Result_i<=switch_port_out_data; + end if; + + elsif n=3 then + n_i<=n+1;P_G_i<=0; + if data_to_ram(7 downto 4)=MPI_PUT then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr,16)); + wr_ok<='1'; + P_G_i<=1; --put ou get + P_len_i<=x"06"; --longueur de l'entête à parcourir + elsif data_to_ram(7 downto 4)=MPI_GET then + Result_i<=data_to_ram; + wr_ok<='1'; -- + P_G_i<=2; --put get + P_len_i<=x"06";--taille de l'instruction en mémoire + dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr,16)); + elsif data_to_ram(7 downto 4)=MPI_SPAWN then + Result_i<=data_to_ram; + wr_ok<='1'; -- + dest_address_i<=std_logic_vector(to_unsigned(Core_Spawn_adr+7,16)); + elsif data_to_ram(7 downto 4)=MPI_INIT then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Core_Init_adr+7,16)); + wr_ok<='1'; -- + -- + else + Result_i<="00000000"; + wr_ok<='0'; -- + n_i<=n; --code inconnu ! + end if; + elsif n=4 then + if P_G=1 or P_G=2 then + Next_ex2_state<=ex2_ack2; + else + Next_ex2_state<=ex2_ack3; + end if; + n_i<=0; + end if; + + when Ex2_ack2 =>if unsigned(p_len)>0 then + If Dma_rd_grant='1' then + if n=0 then + n_i<=n+1; --cycle d'attente pour la RAM + elsif n=1 then + dest_address_i <= dest_address+1; + n_i<=2; + elsif n>=2 then + + --creer un délai sur ces signaux par rapport à src_adress + + n_i<=n+1; + rd_ok<='1'; +-- if n>1 then + dest_address_i <= dest_address+1; + p_len_i <= p_len - 1; + --end if; + Get_Instr_i(n-2)<=Ram_data_out; --deux cycles de retard + Next_ex2_state <= ex2_ack2; + end if; + end if; + dma_rd<='1'; + rd_ok<='1'; + else + if P_G=1 then + dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16)); + else + dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16)); + Waited_get_i(ptr_get)(7 downto 0)<=Get_instr(0); --id + Waited_get_i(ptr_get)(15 downto 8)<=Get_instr(1); --longueur + Waited_get_i(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas + Waited_get_i(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut + RGET_i<='1'; + + Ptr_Get_i<=Ptr_Get+1; --prochain Get à traiter + end if; + Next_ex2_state <= ex2_ack3; + n_i<=0; --suite du process ack + rd_ok<='0'; + dma_rd<='0'; + end if; + +when ex2_ack3 => if n=0 then --set acknowlege bit of the instruction + sb_start<='1'; + sb_bitMask<=x"20";--cinquième bit à un + sb_bitval<='1'; + sb_whole<='0';--Modifier un seul bit ! + if sb_done='1' then + n_i<=1; + sb_start<='0'; + sb_bitval<='0'; + dest_address_i<=dest_address+1; + end if; + + elsif n=1 then + sb_start<='1'; + sb_bitMask<=Rec_Data(2); + sb_bitval<='1'; + sb_whole<='1'; + if sb_done='1' then + n_i<=n+1; + sb_start<='0'; + sb_bitval<='0'; + sb_whole<='0'; + end if; + + elsif n=2 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + end if; + + when ex2_Wsync => rd_ok<='0'; + if n<2 then --réception de la synchronisation. + n_e:=n; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); + n_i<=n_e; + elsif n=2 then + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + + data_to_ram_i<=switch_port_out_data; + Result_i<=switch_port_out_data; + end if; + + elsif n=3 then + n_i<=n+1;P_G_i<=0; + if data_to_ram(7 downto 4)=SYNC_WSTART then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); + wr_ok<='1'; + P_G_i<=1; --put ou get + P_len_i<=x"06"; --longueur de l'entête à parcourir + elsif data_to_ram(7 downto 4)=SYNC_WPOST then + Result_i<=data_to_ram; + wr_ok<='1'; -- + P_G_i<=2; --put get + P_len_i<=x"06";--taille de l'instruction en mémoire + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); + elsif data_to_ram(7 downto 4)=SYNC_WWAIT then + Result_i<=data_to_ram; + wr_ok<='1'; -- + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+7,16)); + elsif data_to_ram(7 downto 4)=SYNC_WCOMP then + Result_i<=data_to_ram; + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); + wr_ok<='1'; -- + Next_Ex2_State<=Ex2_WCOMP; + n_i<=0; + else + Result_i<="00000000"; + wr_ok<='0'; -- + n_i<=n; --code inconnu ! + end if; + + end if; + when Ex2_Wcomp => dma_rd<='1'; + rd_ok<='1'; + + if n=0 then + n_i<=n+1; --cycle d'attente pour la RAM + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + GComp_i(i)<='1'; + elsif n=1 then + dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); + If Dma_rd_grant='1' then + n_i<=2; + end if; + elsif n=2 then + If Dma_rd_grant='1' then + --creer un délai sur ces signaux par rapport à dest_adress + n_i<=n+1; + rd_ok<='1'; + dest_address_i <= dest_address+1; + GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard + + else + n_i<=1; + end if; + elsif n=3 then + If Dma_rd_grant='1' then + --GPost_i(15 downto 8)<=Ram_data_out; --Uncomment if needed + n_i<=n+1; + rd_ok<='1'; + dma_rd<='1'; + end if; + elsif n=4 then + --GPost_i(15 downto 8)<=Ram_data_out; --Uncomment if needed + + rd_ok<='1'; + dma_rd<='1'; + n_i<=n+1; + elsif n=5 then + rd_ok<='0'; + dma_rd<='0'; + n_i<=0; + If GPost=GComp then --le même nombre de post que de COmpleted ? + GPost_Set_i<='1'; + end if; + + Next_ex2_state <= ex2_set_busy; + end if; + + + when ex2_init1 => if n<2 then -- execution du mpi Init + wr_ok<='0'; + if switch_data_available='1' then + n_i<=n+1; + rd_ok<='1'; + P_len_i <=P_len-1; + Rec_Data_i(n+2)<=switch_port_out_data; + data_to_ram_i<=switch_port_out_data; + Result_i<=switch_port_out_data; + else + rd_ok<='0'; + n_i<=n; + end if; + result_i<=(others=>'0'); + elsif n=2 then + n_i<=n+1; + rd_ok<='0'; + + elsif n=3 then + rd_ok<='0'; -- normalement plus rien à lire + n_i<=n+1; + if Initialized='1' then + if data_to_ram(7 downto 4)=INIT_SEEKMAIN then + Result_i<=data_to_ram; + InitReq_i<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=INIT_STAT then + Result_i<=data_to_ram; + InitReq_i<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=INIT_REGISTER then + Result_i<=data_to_ram; + InitReq_i<='0'; --permet d'activer Init de Ex_4 + report "Mise à jour des données d'initialisation"; + Next_Ex2_state<=ex2_ready; + n_i<=0; + elsif data_to_ram(7 downto 4)=INIT_SPAWN then + Result_i<=data_to_ram; + InitReq_i<='1'; --permet d'activer Init de Ex_4 + -- il faut mettre à jour l'état de Spawn + else + Result_i<="00000000"; + InitReq_i<='0'; --permet d'activer Init de Ex_4 + end if; + end if; + elsif n=4 then + n_i<=n+1; + elsif n=5 then + if p_len=0 then + Next_Ex2_state<=ex2_init2; + rd_ok<='0'; + else + p_len_i <=p_len -1; + rd_ok<='1'; --vider le tampon de lecture pour ce paquet ! + end if; + + end if; + when ex2_init2=> if n=5 then + if AppInitAck='1' then + n_i<=n+1; + InitReq_i<='0'; + Result_i<="00000001"; -- cette valeur permet d'acquitter la fonction Init + end if; + elsif n=6 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + InitReq_i<='0'; + end if; + + when ex2_put1 => rd_ok<='0'; --ne pas autoriser la lecture du switch + wr_ok<='0'; + dma_rd<='1'; + if n=0 then + if RGET='1' then + Lp: for i in 1 to Max_stack loop -- to Ptr_get normalement + if i<=Ptr_Get then + if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and + waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and + waited_get(i-1)(23 downto 16)=rec_data(2) and + waited_get(i-1)(31 downto 24)=rec_data(3) then + if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then + + match_get_i<='1'; + end if; + else + + end if; + end if; + exit Lp when i= Ptr_get; + end loop Lp; + end if; + + n_i<=1; + elsif n=1 then + if match_get='1' then + n_i<=3; --ne pas envoyer ack dans ce cas + report "GET Détecté ACK pas envoyé dans Ex2 du HCL n°" & image(pid); + else + n_i<=2; + end if; + elsif n=2 then + instr_ack_i<='1'; --activer l'envoie de l'accusé de réception + data_to_write_fifo_i<=to_fifo_ack; + wr_ok<=wr_ack; + if sent_ack='1' then + n_i<=3; + instr_ack_i<='0'; + dma_wr<='1'; + end if; + + elsif n=3 then + dma_wr<='1'; + if dma_wr_grant = '1' then + Next_Ex2_state <= ex2_put2; + data_to_ram_i<=switch_port_out_data; + rd_ok<='0'; + n_i<=0; + delai:=0; + else + Next_Ex2_state <= ex2_put1; + end if; + end if; + when ex2_put2 => rd_ok<='0'; + n_i<=1; + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + --Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + if unsigned( P_len) > 0 then + + if switch_data_available = '1' and delai=0 then + delai:=1; --une donné lue + P_len_i <= P_len - 1; + Next_Ex2_state <= ex2_put2; + rd_ok<='1'; + data_to_ram_i<=switch_port_out_data; + end if; + if dma_wr_grant='1' and delai=1 then + -- if n=1 then + wr_ok<='1'; + dest_address_i <= dest_address + 1; + delai:=0;--une donnée écrite + -- else + -- dest_address_i <= dest_address ; + -- end if; + --if delai=1 then + --data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch + --end if; + + else + dest_address_i<=dest_address; + wr_ok<='0'; + n_i<=0; + end if; + + Next_Ex2_state <= ex2_put2; + + else + rd_ok<='0'; + + + if dma_wr_grant='1' and n=1 then + + Next_Ex2_state <= ex2_put3; + Wr_ok<='0'; + n_i<=0; + end if; + end if; + + when ex2_put3 => if dma_rd_grant='1' then + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + Next_Ex2_state <= ex2_put4; + n_i<=0; + rd_ok<='1'; + wr_ok<='0'; + end if; + + when ex2_put4 => if n>0 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + if n=0 then + if RGET='1' then + L1: for i in 1 to Max_stack loop -- to Ptr_get normalement + if i<=Ptr_Get then + if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and + waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and + waited_get(i-1)(23 downto 16)=rec_data(2) and + waited_get(i-1)(31 downto 24)=rec_data(3) then + if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then + received_get_i(i-1)<='1'; + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); + mode_get_i<='1'; + match_get_i<='1'; + end if; + else + + end if; + end if; + exit L1 when i= Ptr_get; + end loop L1; + end if; + + n_i<=n+1; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=1 then + if match_get='0' then + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + end if; + if dma_rd_grant='1' then + if RGET='1' then --si on est en mode attente d'un Get + RGET_i<='0'; --Supposons tous les Gets reçus ! + test_wcomp:for i in 1 to Max_stack loop --Tous les Get reçus ? + if Ptr_get>=i then + if received_get(i-1)='0' then + RGET_i<='1'; --Non ! + end if; + end if; + exit test_wcomp when i=Ptr_get; + end loop test_wcomp; + + end if; + n_i<=n+1; + rd_ok<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + end if; + elsif n=2 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + tempval(4):='1'; --SET du bit DReceived + if Mode_Get='1' then --si get ack est détecté + tempval(6):=RGET; -- Bit 6 Busy=0 si dernier get reçu !! + mode_get_i<='1'; + end if; + data_to_ram_i<=tempval; + rd_ok<='0'; + wr_ok<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + n_i<=0; + end if; + elsif n=3 then + if dma_wr_grant='1' then + rd_ok<='0'; + wr_ok<='1'; + n_i<=n+1; + end if; + elsif n=4 then + if dma_wr_grant='1' then + rd_ok<='0'; + wr_ok<='1'; + + n_i<=5; + end if; + elsif n=5 then + Next_Ex2_state <= ex2_set_busy; + n_i<=0; + rd_ok<='0'; + wr_ok<='0'; + mode_get_i<='0'; + match_get_i<='0'; + end if; + + + + -- dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction + when ex2_put5 => + Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put + + when ex2_spawn1 => + + if n<2 then + n_e:=n; + read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len,P_len_i,n_e,n); + n_i<=n_e; + Rec_Data_i(2)<=Switch_port_out_data; + elsif n=2 then + Rec_Data_i(3)<=Switch_port_out_data; + Result_i<=Switch_port_out_data; + Data_to_ram_i<=Switch_port_out_data; + n_i<=n+1; + rd_ok<='1'; + elsif n=3 then + if data_to_ram(7 downto 4)=SPAWN_LOAD then + Result_i<=data_to_ram; + wr_ok<='1'; --permet d'activer Init de Ex_4 + elsif data_to_ram(7 downto 4)=SPAWN_COMP then + Result_i<=data_to_ram; + wr_ok<='0'; --permet d'activer Init de Ex_4 + + elsif data_to_ram(7 downto 4)=SPAWN_ERR then + Result_i<=data_to_ram; + wr_ok<='0'; --permet d'activer Init de Ex_4 + else + Result_i<=(others=>'0'); + + end if; + n_i<=n+1; + rd_ok<='0'; + elsif n=4 then + wr_ok<='1'; + if AppInitAck='1' then + wr_ok<='0'; + rd_ok<='0'; + n_i<=n+1; + end if; + elsif n=5 then + wr_ok<='0'; + rd_ok<='0'; + n_i<=0; + Next_Ex2_state <=Ex2_Ready; + end if; + when Ex2_Spawn2=> + Next_Ex2_state <=Ex2_Ready; + when ex2_get1 => rd_ok<='0'; --ne pas autoriser la lecture du switch + --ack_state<=next_ack_state; --MAE d'envoie de AR + dma_rd<='1'; + if n=0 then + instr_ack_i<='1'; --activer l'envoie de l'accusé de réception + data_to_write_fifo_i<=to_fifo_ack; + wr_ok<=wr_ack; + if sent_ack='1' then + n_i<=1; + instr_ack_i<='0'; + wr_ok<='0'; + --if switch_data_available='1' then + rd_ok<='0';-- + --P_len<=P_len-1; + --end if; + end if; + + elsif n=1 then + if switch_data_available='1' then + if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo + data_to_write_fifo_i <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put + wr_ok<='1'; + rd_ok<='1'; --autoriser la lecture du crossbar + P_len_i<=P_len-1; + n_i<=n+1; + else + Wr_ok<='0'; + Rd_ok<='0'; + end if; + else + Wr_ok<='0'; + rd_ok<='0'; + end if; + elsif n=2 then + if switch_data_available='1' then + if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo + --data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put + --P_len_i <= P_len-1;--le nombre d'octet qui restent à copier + Next_Ex2_state <= ex2_get2; + wr_ok<='0'; + rd_ok<='0'; --autoriser la lecture du crossbar + n_i<=0; + else + rd_ok<='0'; + wr_ok<='0'; + end if; + else + rd_ok<='0'; + wr_ok<='0'; + end if; + end if; + when ex2_get2 => if P_len>0 then + if fifo_full = '0' and switch_data_available ='1' then + data_to_write_fifo_i <= switch_port_out_data;--la longueur initiale du GET + p_len_i <= P_len - 1; + Next_Ex2_state <= ex2_get2; + wr_ok<='1'; + Rd_ok<='1'; + elsE + + wr_ok<='0'; + Rd_ok<='0'; + END IF; + else + if n=0 then + if fifo_full='0' then + wr_ok<='0';--une impulsion en plus + n_i<=n+1; + Next_Ex2_state <= ex2_get2; + else + wr_ok<='0'; + end if; + + else + Next_Ex2_state <= ex2_get3; + n_i<=0; + wr_ok<='0'; + end if; + rd_ok<='0'; + end if; + i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); + Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! + + --préparer en avance l'adresse de lecture/écriture + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_get3 => wr_ok<='0'; + if dma_rd_grant='1' then -- fin du mpi_get + Next_Ex2_state <= ex2_get4; + n_i<=0; + --activer le bit sending du registre de transfert + else + Next_Ex2_state <= ex2_get3; + end if; + + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_get4 => if n <4 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + if n=0 then + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + elsif n=1 then + if dma_rd_grant='1' then + n_i<=n+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + data_to_ram_i<=Ram_data_out; + elsif n=2 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + --tempval(2):='1'; --mise à 1 du Bit DSending + --tempval(5):='0'; --Mise à 0 du Bit Sent + data_to_ram_i(2)<='1'; --mise à 1 du Bit DSending + data_to_ram_i(5)<='0'; --Mise à 0 du Bit Sent + + data_to_ram_i<=tempval; + rd_ok<='1'; + wr_ok<='0'; + else + rd_ok<='1'; + wr_ok<='0'; + n_i<=0; + end if; + + + elsif n=3 then + if dma_wr_grant = '1' then + n_i<=n+1; + rd_ok<='0'; + wr_ok<='1'; + end if; + elsif n=4 then + if dma_wr_grant = '1' then + n_i<=0; + Next_Ex2_state <= Ex2_Ready; -- fin du mpi_get + else + rd_ok<='0'; + wr_ok<='1'; + --n<=n-1; + end if; + end if; + + + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when ex2_Set_Busy => if n=0 then --set busy bit of the instruction + dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + n_i<=1; + if Gpost_Set='1' then + if (rec_wpost=gpost) and RGET='0' then + Wbusy_i<='0'; + Gpost_Set_i<='0'; + GComp_i<=(others=>'0'); + rec_wpost_i<=(others=>'0');--reset des messages reçu + else + Wbusy_i<='1'; + end if; + else + + n_i<=2; + end if; + if RGET='1' then + WBusy_i<='1'; + end if; + elsif n=1 then + sb_start<='1'; + sb_bitMask<=x"40";--6e bit à 1 + sb_bitval<=WBusy; + if sb_done='1' then + n_i<=2; + sb_start<='0'; + sb_bitval<='0'; + end if; + elsif n=2 then + Next_Ex2_state<=Ex2_Ready; + n_i<=0; + end if; + -- execution du barrier + when ex2_barrier1 => if switch_data_available = '1' then + pading_data <= switch_port_out_data; + Next_Ex2_state <= ex2_barrier2; + else + Next_Ex2_state <= ex2_barrier1; + end if; + when ex2_barrier2 => if packet_type = MPI_BARRIER_REACHED then + barrier_counter_i <= barrier_counter + 1; + Next_Ex2_state <= ex2_barrier4; + else + Next_Ex2_state <= ex2_barrier3; + end if; + when ex2_barrier3 => if n < 10 then + n_i<= n + 1; + Next_Ex2_state <= ex2_barrier3; + else + Next_Ex2_state <= Ex2_Ready; + end if; + when ex2_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED + data_to_write_fifo_i <= MPI_BARRIER_COMPLETED & "0000"; + Next_Ex2_state <= ex2_barrier5; + else + Next_Ex2_state <= Ex2_Ready; + end if; + when ex2_barrier5 => if fifo_full = '0' then -- taille du packet MPI_BARRIER_COMPLETED + data_to_write_fifo_i <= "00000011"; + Next_Ex2_state <= ex2_barrier6; + else + Next_Ex2_state <= ex2_barrier5; + end if; + when ex2_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED + data_to_write_fifo_i <= "00000000"; + Next_Ex2_state <= ex2_barrier7; + else + Next_Ex2_state <= ex2_barrier6; + end if; + when ex2_barrier7 => if fifo_full = '0' then + barrier_counter_i <= "0000"; + Next_Ex2_state <= Ex2_Ready; + else + Next_Ex2_state <= ex2_barrier7; + end if; + + when others => Next_Ex2_state <= Ex2_Ready; + end case; + + end process; + + -- sortie de la machine à etat +-- + ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram,Dma_rd,Dma_wr, + switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request, + appInitAck,n,InitReq) + variable transact : std_logic_vector(Word-1 downto 0); + begin +-- code fonctionnel + sb_ram_data_out<=Ram_data_out; --presque toujours cette valeur + case Ex2_state is + when Ex2_Ready => fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='1'; + AppInitReq<='0'; + when fetch_packet_type => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='0'; + AppInitReq<='0'; + + + when decode_packet_type => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when decode_packet_type2 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + when fetch_addresses => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + when ex2_ack1 |ex2_Wsync => + Ready<='0'; + switch_port_out_rd_en<=rd_ok; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when ex2_ack2|Ex2_WCOMP => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= dma_rd; + dma_wr_request <= '0'; + Ram_rd<=rd_ok; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + when ex2_ack3 => + Ready<='0'; + switch_port_out_rd_en<=rd_ok; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when ex2_put1 => fifo_wr_en <= wr_ok; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= dma_wr; + dma_rd_request <= dma_rd; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_put2 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <=rd_ok; + + if rd_ok = '1' then + + Ram_data_in<=switch_port_out_data; + else + Ram_data_in<=data_to_ram; + end if; + Ram_wr<=wr_ok; + Ram_rd<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + when ex2_put3 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + --ne pas corrompre le contenu de la RAM + --Ram_data_in<=data_to_ram; + Ram_wr<='0'; + Ram_rd<='1'; + packet_received <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + + when ex2_put4 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <= '0'; + packet_received <= '1'; + dma_rd_request <= dma_rd; + dma_wr_request <=dma_wr; + Ram_wr<=wr_ok; + Ram_rd<=rd_ok; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_in<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution + + when ex2_put5 => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_in<=data_to_ram; + --Result <=(1=>'1',others=>'0'); --put completed + + when ex2_get1=> fifo_wr_en <= wr_ok; + switch_port_out_rd_en <= rd_ok; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= dma_rd; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_get2 => + switch_port_out_rd_en <=rd_ok; + fifo_wr_en <= Wr_ok; + Ready<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + + when ex2_get3 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <= '0'; + packet_received <= '1'; + dma_rd_request <= '1'; + dma_wr_request <='0'; + Ram_wr<='0'; + Ram_rd<='1'; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + --Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending + + when ex2_get4 => + Ready<='0'; + barrier_completed <= '0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '1'; + AppInitReq<='0'; + dma_rd_request <= dma_rd; + dma_wr_request <= dma_wr; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_in<=data_to_ram; --activer le bit DSending + + + when ex2_barrier1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + Ready<='0'; + AppInitReq<='0'; + + when ex2_barrier2 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + + when ex2_barrier3 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + Ready<='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '1'; + AppInitReq<='0'; + + when ex2_barrier4 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + + when ex2_barrier5 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_barrier6 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_barrier7 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_in<=(others=>'0'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when ex2_spawn1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok;--switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ready<='0'; + Ram_data_in<=(others =>'0'); + AppInitReq<=wr_ok; + when ex2_Spawn2 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + + Ram_data_in<=data_to_ram; + + Ram_wr<=wr_ok; + Ram_rd<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + when ex2_init1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= rd_ok;--switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ready<='0'; + Ram_data_in<=(others =>'0'); + AppInitReq<=InitReq; + + + when ex2_init2 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ram_data_in<=(others =>'0'); + AppInitReq<= not(AppInitAck); + Ready<='0'; + + + when ex2_Set_Busy => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= sb_dma_rd_request; + dma_wr_request <= sb_dma_wr_request; + Ram_rd<=sb_ram_rd; + Ram_wr<=sb_ram_wr; + sb_ram_data_out<=Ram_data_out; + Ram_data_in<=sb_ram_data_in; + when others => Ready<='1'; -- le module est à nouveau libre + fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_in<=(others=>'0'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='1'; + AppInitReq<='0'; + end case; + + end process; + + ex2_fsm_sync:process(clk,reset) + + begin + + if reset = '1' then + ex2_state <= Ex2_Ready; + ack_state<=ack0; --MAE d'envoie de AR + n<=0; + P_len<=(others=>'0'); + GPost<=(others =>'0'); + Packet_type<=(others =>'0'); + P_G<=0; + Result1<=(others =>'0'); --juste une copie + dest_address <= (others =>'0'); + + WBUSY<='0'; + RGET<=0; + InitReq<='0'; + mode_get<='0'; + match_get<='0'; + Sent_ack<='0'; + Instr_ack<='0'; + Ptr_Get<=0; + Rec_Wpost<=(others =>'0'); + dest_ack<=(others =>'0'); + For i in 0 to Max_stack loop + Waited_get(i)<=(others =>'0'); + end loop; + For i in 0 to 7 loop + Get_Instr(i)<=(others =>'0'); + end loop; + for i in 0 to 3 loop + Rec_Data(i)<=(others =>'0'); + end loop; + else + if rising_edge(clk) then + ex2_state<=next_ex2_state; + ack_state<=next_ack_state; --MAE d'envoie de AR + n<=n_i; + P_len<=P_len_i; + Packet_type<=packet_type_i; + P_G<=P_G_i; + Result1<=Result_i; --juste une copie + dest_address <= dest_address_i; + data_to_write_fifo<=data_to_write_fifo_i; + WBUSY<=WBUSY_i; + RGET<=RGET_i; + InitReq<=InitReq_i; + mode_get<=mode_get_i; + match_get<=match_get_i; + Sent_ack<=sent_ack_i; + Instr_ack<=Instr_ack_i; + Ptr_Get<=Ptr_Get_i; + Rec_Wpost<=Rec_WPost_i; + dest_ack<=dest_ack_i; + barrier_counter<=barrier_counter_i; + GPost<=GPost_i; + GComp<=GComp_i; + Received_get<=Received_get_i; + GPost_set<=GPost_Set_i; + data_to_ram<=data_to_ram_i; + For i in 0 to Max_stack loop + Waited_get(i)<=Waited_get_i(i); + end loop; + For i in 0 to 7 loop + Get_Instr(i)<=Get_instr_i(i); + end loop; + for i in 0 to 3 loop + Rec_Data(i)<=Rec_Data_i(i); + end loop; + end if; + end if; + end process ex2_fsm_sync; +snd_ack:process (ack_state,reset,fifo_full,instr_ack,Dest_Ack,apprank,Packet_type,ram_data_out,dma_rd_grant) +--ce processus est chargé d'emettre l'accusé de réception pour chaque instruction reçu +begin +-- if rising_edge(clk) then + Sent_ack_i<='0'; --pas besoin de le mémoriser + wr_ack<='0'; --valeur par défaut + ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); + if reset='1' then + next_ack_state<=ack0; + to_fifo_ack<=(others=>'1'); + else + next_ack_state<=ack_state; + + case ack_state is + when ack0 =>to_fifo_ack<=(others=>'0'); + Wr_ack<='0'; + if instr_ack='1' then + next_ack_state<=ack_readwait; + to_fifo_ack <= MPI_ACK & Dest_ack; + wr_ack<='0'; + end if; + + sent_ack_i<='0'; + when ack_readwait => to_fifo_ack <= MPI_ACK & Dest_ack; + ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); + --vérifier WinPost attend bien une action de cette source + if dma_rd_grant='1' then + next_ack_state<=ack_checkwait; + end if; + when ack_checkwait => to_fifo_ack <= MPI_ACK & Dest_ack; + ack_address<=Std_logic_vector(to_unsigned(Core_Base_Adr+4+W_Gpost,Adrlen)); + if dma_rd_grant='1' and ram_data_out(conv_integer(dest_ack))='1' then + next_ack_state<=ack1; + elsif dma_rd_grant='0' then + next_ack_state<=ack_readwait; + else + next_ack_state<=ack6; --pas d'acknowledge à envoyer + assert true report "Packet non attendu de cette source !" + severity failure; + end if; + when ack1 => if fifo_full = '0' then -- conversion envoie lack à l'emetteur + -- en empilement dans le fifo + to_fifo_ack <= MPI_ACK & Dest_ack; + next_ack_state <= ack2; + wr_ack<='1'; + else + wr_ack<='0'; + end if; + sent_ack_i<='0'; + to_fifo_ack <= MPI_ACK & Dest_ack; + when ack2 => if fifo_full = '0' then + to_fifo_ack <= "00000100";--la longueur + + next_ack_state <= ack3; + wr_ack<='1'; + else -- + next_ack_state <= ack2; + wr_ack<='0'; + + end if; + to_fifo_ack <= "00000100"; + sent_ack_i<='0'; + when ack3 => if fifo_full = '0' then + to_fifo_ack <= "00000000";-- + next_ack_state <= ack4; + wr_ack<='1'; + else -- + next_ack_state <= ack3; + wr_ack<='0'; + + end if; + to_fifo_ack <= "00000000"; + sent_ack_i<='0'; + when ack4 => if fifo_full = '0' then + to_fifo_ack <=packet_type & apprank ;--l'instruction et le rang de lacquitteur + next_ack_state <= ack5; + wr_ack<='1'; + sent_ack_i<='0'; + else -- + next_ack_state <= ack4; + wr_ack<='0'; + sent_ack_i<='0'; + end if; + to_fifo_ack <=packet_type & apprank ; + when ack5 => if Instr_ack='0' then --dernier pulse + next_ack_state <= ack0; + else + next_ack_state <= ack6; + end if; + wr_ack<='0'; + sent_ack_i<='1'; + to_fifo_ack<=(others=>'1'); + when ack6 => if Instr_ack='0' then + next_ack_state <= ack0; + + end if; + wr_ack<='0'; + sent_ack_i<='1'; + to_fifo_ack<=(others=>'1'); +end case; +end if; +--end if; +end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX3_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX3_FSM.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX3_FSM.vhd (revision 142) @@ -0,0 +1,75 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM / KIEGAING +-- +-- Create Date: 09:22:58 05/20/2011 +-- Design Name: +-- Module Name: EX3_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- module du core mpi chargé d'exécuter les fonctions mpi_get_size et mpi_get_rank +-- Dependencies: +-- +-- Revision: 23/02/2012 +-- Revision 0.02 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +--package Packet_type +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use Work.Packet_type.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX3_FSM is + generic ( + pid : unsigned(Word-1 downto 0) := "00000001"; -- id du processeur + nprocs : unsigned(Word-1 downto 0):="00000011"-- nombre de processeur du MPSOC + ); + Port ( instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + ResOut : out STD_LOGIC_VECTOR (Word-1 downto 0); + pid_nprocs: out STD_LOGIC_VECTOR (Word-1 downto 0); + clk : in STD_LOGIC; + IsMain: in STD_LOGIC; + reset : in STD_LOGIC); +end EX3_FSM; + + +architecture Behavioral of EX3_FSM is + +signal instruction_signal : std_logic_vector(3 downto 0); +signal rank : unsigned(Word-1 downto 0) := pid; +signal size : unsigned(Word-1 downto 0) := nprocs; +begin +instruction_signal <= instruction(7 downto 4); +ex3_fsm_process : process(clk) +begin + + +if rising_edge(clk) then + if reset ='1' then + ResOut <= (others=>'0'); + else + if instruction_signal = MPI_GET_RANK then + ResOut <= std_logic_vector(rank); + elsif instruction_signal = MPI_GET_SIZE then + ResOut <= std_logic_vector(size); + elsif instruction_signal=MPI_INIT then + if IsMain='1' then --master est associé à la bibliothèque de rang 0 + rank<=rank+1; -- elle est responsable d'affecter de nouveaux rangs + end if; + end if; + end if; +end if; +end process; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX4_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX4_FSM.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX4_FSM.vhd (revision 142) @@ -0,0 +1,2011 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM +-- +-- Create Date: 14:44:36 03/07/2012 +-- Design Name: +-- Module Name: EX4_FSM - Behavioral +-- Project Name: MPI_CORE_COMPONENTS +-- Target Devices: SPARTAN 3E xc3s1200e +-- Tool versions: +-- Description: Ce module renferme les fonctions permettant d'initialiser la +-- bibliothèque matériel MPI +-- Dependencies: +-- +-- Revision: 25/juin/2012 au 24/Octobre/2012 +-- Revision 0.03 - File updated +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; + +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; +Library NocLib; +use NoCLib.CoreTypes.all; +use work.packet_type.all; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX4_FSM is + Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_En : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + ResultOut : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); + Result_En : out STD_LOGIC:='0'; + Ready : out STD_LOGIC; --indique que le module est disponible + NocSize : out STD_LOGIC_VECTOR(3 downto 0); + PortId : out STD_LOGIC_VECTOR(3 downto 0):=(others=>'0'); + AppRank : out STD_LOGIC_VECTOR(3 downto 0):=(others=>'0'); + AppSize : out STD_LOGIC_VECTOR(3 downto 0):=(others=>'0'); + IsMain : out STD_LOGIC; + I_fifo_full :in STD_LOGIC; --instruction fifo + I_fifo_wr_en: out STD_LOGIC;--instruction fifo Write enable + I_fifo_data_in :out STD_LOGIC_vector(Word-1 downto 0); --instruction fifo data + Initialized : out STD_LOGIC; + Snd_Ack : IN std_logic; + Rec_Rdy : IN std_logic; + Rec_Data : IN Typ_PortIO(0 to 3); + Snd_data : OUT Typ_PortIO(0 to 3); + Snd_Start : out std_logic; + Rec_Ack : OUT std_logic; + dma_wr_grant : in STD_LOGIC; + dma_wr_request : out STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + ram_rd : out std_logic; + ram_wr : out std_logic; + ram_address : out std_logic_vector(ADRLEN-1 downto 0);--accès au stockage + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + + AppAck : in STD_LOGIC; + AppReq : in STD_LOGIC; + port_in_cmd_en : out STD_LOGIC:='0'; + port_in_wr_en : out STD_LOGIC:='0'; + port_in_empty : in STD_LOGIC; + port_in_full : in STD_LOGIC; + port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'-'); + port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_rd_en : out STD_LOGIC:='0'; + port_out_data_available : in STD_LOGIC); +end EX4_FSM; + +architecture Behavioral of EX4_FSM is + +COMPONENT SetBit + PORT( + clk : IN std_logic; + reset : IN std_logic; + BitNum : IN std_logic_vector(0 to 2); + BitVal : IN std_logic; + dma_wr_grant : IN std_logic; + dma_rd_grant : IN std_logic; + Ram_data_in : IN std_logic_vector(7 downto 0); + + dma_wr_request : OUT std_logic; + dma_rd_request : OUT std_logic; + ram_rd : OUT std_logic; + ram_wr : OUT std_logic; + ram_address : OUT std_logic_vector(15 downto 0); + Ram_data_out : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; +Type Ar_MPIPort_In is array (positive range <>) of Typ_MPIPort_in; +Type Ar_MPIPort_out is array (positive range <>) of Typ_MPIPort_out; + + --MAE pour emission de init + --type init1_type is (init,NocSize,InitToNoc,NextPort,EndBCast); + -- MAE pour affectation des rangs aux différentes librairies MPI + type init2_type is (init,GetPortNum,DecodeData,IsPortZero,SeekMain1,SeekMain2,StoreMain,SetMainFlag,ReadNoc,GetMainReq,StoreRank,NewRank,SendRank,RegRank,SendPeerStat,AskPeerStat,GetPeerStat,SendApp,SpawnApp,SpawnLoad,ErrSpawn,EndInit); + -- MAE pour réception de init depuis le réseau; + type init3_type is (init,GetNocSize,ReadInitHead,StorePort,EndInit); + type typ_send is (s_init,s_head,s_len,s_len2,s_data,s_end); + type typ_receiv is (r_wait,r_dlen,r_drop,r_glen,r_data,r_pulse,r_end); + type typ_cmd is (cmdstart,cmdpost,cmdpostidle,cmdread,cmdlen,cmdglen,cmddata,cmdend,cmdtimeout); + type typ_mem16 is array(natural range <>) of std_logic_vector(15 downto 0);-- + type typ_sendproc is (Hcl_init_off,Hcl_init_on); + + signal etsnd : typ_send; + signal etrec:typ_receiv; --pour la machine à état de réception + signal etcmd :typ_cmd; --pour la machine à état de commande + signal et_sendproc :typ_sendproc; +signal IS_state,next_Is_state : natural range 0 to 3:=0; + +-- signal stInit1, next_stInit1 : init1_type; + signal stInit2, next_stInit2 : init2_type; + --signal stInit3, next_stInit3 : init3_type; + --signaux pour l'interface avec les ports + signal cport_in_wr_en,sport_in_wr_en:std_logic; + signal cport_out_rd_en,rport_out_rd_en:std_logic; + signal rdy:std_logic:='0'; --signal busy/ready + signal tosend,tosend4 :std_logic_vector(Word-1 downto 0); + signal PeerStat,PeerStat_i : std_logic_vector(15 downto 0):=(others=>'0'); --état des autres Lib initialisées + signal SpawnReq,SpawnReq_Q : std_logic_vector(15 downto 0):=(others=>'0'); --état des autres HT qui ont appelés le Spawn + signal Spawn_grp,Spawn_grp_Q :typ_mem16(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); --un max de quatre groupes de fils est prévu + signal Grp_id,grp_id_i :natural range 0 to 3:=0; --id du groupe des HT fils + signal selector : std_logic_vector (2 downto 0); -- pour le MUX des signaux vers le port + --signaux pour les états des MAE + signal NocSizeOk,PortCountFlag : std_logic; + signal PortNumFlag,PortNumFlag_i,EquFlag,EquFlag_i,MainResp: std_logic:='0'; + signal StatAsked,RankAsked,RankSent:std_logic; + signal nextr,nextr_i : natural :=0; + signal RTS_cmd,RTS_dat,RTS_I,CTR,BCast,Send_Ack,DS_Ack,CM_Ack:std_logic:='0'; + signal I_Send_Ack,I_Send_Rdy:std_logic:='0'; + signal Rcv_On,Snd_On,Cmd_On : std_logic:='0'; --status des MAE d'envoie et de réception + signal SpawnOn,SpawnInit ,SpawnInit_i:std_logic:='0'; --indique que le Spawn est activé + signal SpawnNbReq,SpawnNbAck,SpawnNBAck_i : natural range 0 to 15 :=0; --compte le nombre de requêtes et le nombre d'acquitement + signal SpawnNbReq_Q : natural range 0 to 15 :=0; --compte le nombre de requêtes et le nombre d'acquitement + signal SpawnCmd0,SpawnCmd1, SpawnCmd2 :std_logic_vector(Word-1 downto 0):=(others=>'0'); + signal SpawnCmd0_Q,SpawnCmd1_Q, SpawnCmd2_Q :std_logic_vector(Word-1 downto 0):=(others=>'0'); + signal SpawnDest :std_logic_vector(3 downto 0); + Signal Ht_Start,Ht_Start_i : natural range 0 to 15:=0; + Signal vPeerStat,vPeerStat_i : std_logic_vector(15 downto 0):=(others=>'0'); + signal IsMain_i,IsMain1,Initialized_i,HCL_init,HCL_Init_i: std_logic:='0'; + signal DS_RDY ,BCast_Rdy,Send_RDY,CM_RDY:std_logic:='0'; + signal ExecTime_out:std_logic; + --signaux de gestion de la RAM + signal Ram_Next_Address : std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_BASE_ADR+CORE_Rank2port_BASE,16)); + signal Ram_NExt_Address_i :std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_BASE_ADR+CORE_Rank2port_BASE,16)); + signal n,n_i:natural range 0 to 15 :=0; + signal n0,n0_i:natural range 0 to 7:=0; + signal DataToRam : std_logic_vector(Word-1 downto 0) ; + signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; + --Signaux des résultats et de l'état + signal PortNum_i,PortNum,MyPort : std_logic_vector(3 downto 0); -- + signal NocMax ,NocMax_i: std_logic_vector(3 downto 0):=(others=>'0'); -- Nombre de ports du réseau -1 ? + signal MyRank : std_logic_vector(3 downto 0) ; --rang du PE + signal AppSize_i,AppSize1:std_logic_vector(3 downto 0) ;--taille de l'application + signal Spawn_done,Spawn_done_i:std_logic:='0'; --indique que le Spawn a été effectué + signal MainPort,MainPort_i : std_logic_vector(3 downto 0) ; --Port de la lib main + signal NextRank,NextRank_i : std_logic_vector(3 downto 0):=(others=>'0'); --utiliser pour gérer les affectations de rangs MPI + signal Data_To_Send,Data_to_send_i : Typ_PortIo(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); -- permet d'empiler les données à envoyer + signal RankToPort :Typ_PortIo(0 to 15);--permet d'associer un port réseau à chaque rang + signal CmdReceived : Typ_PortIO(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); + signal DataReceived : Typ_PortIO(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); + signal Datalen,DataLen_i : natural range 0 to 7:=0; --indique la longueur des données + --other outputs + signal StatAsked_i,RankAsked_i,MainResp_i,RankSent_i,Result_i:std_logic:='0'; + signal snd_start_q,snd_start_i:std_logic:='0';--version interne des signaux de sortie + --signal BCast_Rdy_i : std_logic; + signal cdlen,dcount : natural range 0 to 255:=0; --longueur du paquet reçu par le process pcmd + signal timeout,timeout_i : natural range 0 to 4095:=0; + signal PortStat,PortStat_i : std_logic_vector(3 downto 0):=(others=>'0'); + signal PeerPort,PeerPort_i : natural range 0 to 15:=0; -- désigne le port qui emet une requête + signal PeerRTS,PeerRTS_i,PeerCTR:std_logic:='0'; + signal cpt,cpt_peer : natural range 0 to 31:=0; --compteur pour le nombre de HT initialisés + signal clk_cyl,clk_cyl_i : natural range 0 to 15:=0; +begin +--======================================================================================= +--fonctions du module +--======================================================================================= +--======================================================================================= + +-- Inst_SetBit: SetBit PORT MAP( +-- clk => clk, +-- reset => reset , +-- ce => cmd, +-- BitNum => , +-- BitVal => '1', +-- dma_wr_grant => dma_wr_grant , +-- dma_wr_request => dma_wr_request, +-- dma_rd_grant => dma_rd_grant, +-- dma_rd_request => dma_rd_request, +-- ram_rd => ram_rd, +-- ram_wr => ram_wr, +-- ram_address => , +-- Ram_data_in => Ram_data_in, +-- Ram_data_out => Ram_data_out +-- ); + + + -- Gestion de l'initialisation du Core MPI + sync_Init2 : process (clk,reset) + begin + if reset='1' then + stinit2<=init; + StatAsked<='0'; + MyPort<=(others=>'0'); + NextRank<=(others =>'0'); + PortNumFlag<='0'; + RankSent<='0'; + AppRank<="0000"; + AppSize1<="0000"; + SpawnNbAck<=0; + ISMain1<='0'; + MyPort<="0000"; + MyRank<="0000"; + Ready<='0'; + SpawnNbReq_q<=0; + SpawnReq_Q<=(others=>'0'); + SpawnCmd0_Q<=(others=>'0'); + SpawnCmd1_Q<=(others=>'0'); + SpawnCmd2_Q<=(others=>'0'); + --Spawn_grp_q<=Spawn_grp; --à traiter + for i in 0 to 3 loop + Spawn_grp_q(i)<=(others=>'0'); + end loop; + PeerRTS<='0'; + PortNum<="0000"; + Spawn_done<='0'; + HCL_init<='0'; + MainResp<='0'; + SpawnInit<='0'; + PeerStat<=(others=>'0'); + PortStat<=(others=>'0'); + HCL_init<='0'; + PeerStat<=(others=>'0'); + DataLen<=0; + MainPort<=(others=>'0'); + Nextr<=0; + NocMax<=(others=>'0'); + PeerPort<=0; + grp_id<=0; + HT_Start<=0; + vPeerStat<=(others=>'0'); + elsif rising_edge(clk) then + stinit2<=next_stinit2; + IS_State<=Next_IS_State; + n0<=n0_i; + --ajout des autres affectations ici + Ram_Next_Address<=Ram_Next_Address_i; + PortNumFlag<=PortNumFlag_i; + RankAsked<=RankAsked_i; + RankSent<=RankSent_i; + AppRank<=MyRank; + timeout<=timeout_i; + SpawnInit<=SpawnInit_i; + cpt<=cpt_peer; + clk_cyl<=clk_cyl_i; + NextRank<=NextRank_i; + StatAsked<=StatAsked_i; + MainResp<=MainResp_i; + AppSize1<=AppSize_i; + n<=n_i; + Ht_Start<=Ht_Start_i; + Grp_Id<=Grp_Id_i; + vPeerStat<=vPeerStat_i; + SpawnNbAck<=SpawnNbAck_i; + PortStat<=PortStat_i; + EquFlag<=EquFlag_i; + --IsMain1<=IsMain_i; + if ismain_i='1' then + IsMain1<='1'; + + else + IsMain1<=IsMain1; + end if; + if stInit2=DecodeData then + MyPort<=Cmdreceived(2)(3 downto 0); + end if; + + if stInit2=StoreRank and ExecTime_Out='1' then + MyRank<=MyPort; + elsif stInit2=StoreRank then + MyRank<=DataReceived(2)(3 downto 0); + elsif stInit2=SetMainFlag then + MyRank<=MyPort; + end if; + Ready<=Rdy; + snd_start_q<=snd_start_i; + SpawnNbReq_q<=SpawnNbReq; + SpawnReq_Q<=SpawnReq; + SpawnCmd0_Q<=SpawnCmd0; + SpawnCmd1_Q<=SpawnCmd1; + SpawnCmd2_Q<=SpawnCmd2; + Spawn_grp_q<=Spawn_grp; + PeerRTS<=PeerRTS_i; + PortNum<=PortNum_i; + Spawn_done<=Spawn_done_i; + HCL_init<=Hcl_init_i; + PeerStat<=PeerStat_i; + DataLen<=DataLen_i; + MainPort<=MainPort_i; + Nextr<=NextR_i; + NocMax<=NoCMax_i; + PeerPort<=PeerPort_i; + grp_id<=grp_id_i; + for i in 0 to 3 loop + data_to_send(i)<=data_to_send_i(i); + end loop; + end if; +end process; + +AppSize<=AppSize1; + + Init2_DECODE: process (stinit2,n, CmdReceived, EquFlag, MyPort, DS_RDY, MainResp, DataReceived, + SpawnOn,Ram_Next_Address,PeerRTS,PortSTAT,dma_rd,dma_wr,Send_rdy,I_Send_rdy,rd_ok,wr_ok,Instruction, + MainPort,PeerStat,SpawnCmd0,SpawnCmd1,SpawnCmd2,SpawnInit,BCast_rdy,Data_to_send,portnum, + PortNumFlag,peerport,NocMax,Nextrank,rankasked,NextR,IsMain1,ExecTime_out,DataToRam) + variable nextadr : natural :=0;--to_integer(unsigned(Ram_Next_Address)); + variable nport : natural range 0 to 15:=0; + begin + for i in 0 to 3 loop + data_to_send_i(i)<=data_to_send(i); + end loop; + PortNum_i<=PortNum; + PortNumFlag_i<=PortNumFlag; + PortID<=MyPort; + PeerPort_i<=PeerPort; + NocMax_i<=NoCMax; + NextRank_i<=NextRank; + MainPort_i<=MainPort; + PeerStat_i<=PeerStat; + EquFlag_i<=EquFlag; + RankAsked_i<=RankAsked; + NextR_i<=NextR; + Ram_Next_Address_i<=Ram_Next_Address; + Ram_address<=(others=>'1'); + Ram_data_in<=(others=>'1'); + dma_rd_request<='0'; + dma_wr_request<='0'; + Initialized_i<='0'; + rdy<='0'; + ram_rd<='0'; + ram_wr<='0'; + I_Send_ack<='0'; + IsMain_i<='0'; + send_ack<='0'; + DataLen_i<=0; + Case stInit2 is + When Init => + RTS_cmd<='0'; + --RTS_dat<='0'; + RTS_I<='0'; + BCast<='0'; + Result_En<='0'; + Initialized_i<='0'; + CM_Ack <='0'; + CTR<='0' ; + DS_ACK<='0'; + Send_Ack<='0'; + ram_wr<='0'; + rdy<='1';--le module est disponible + ResultOut<=(others=>'0'); + if PortNumFlag='1' and IsMain1='1' then + PortNum_i<=Instruction(3 downto 0); + else + PortNum_i<=(others=>'-'); + end if; + EquFlag_i<='0'; + RankAsked_i<='0'; + dma_wr_request<='0'; + dma_rd_request<='0'; + When GetPortNum => + RTS_cmd<='1'; + RTS_I<='0'; + + Result_En<='0'; + Initialized_i<='0'; + BCast<='0'; --réalise un envoie non collectif + CM_Ack<='0'; -- les données sont maintenant attendues + CTR<='0' ; + data_to_send_i(0)<=X"0" & GETPORTID; + DS_ACK<='0'; + Send_Ack<='0'; + ram_wr<='0'; + rdy<='0'; + IsMain_i<='0'; + ResultOut<=(others=>'0'); + PortNum_i<=(others=>'-'); + RankAsked_i<='0'; + dma_wr_request<='0'; + When DecodeData => + EquFlag_i<=(All_zeros(Cmdreceived(2)(3 downto 0))); + RTS_cmd<='0'; + RTS_I<='0'; + BCast<='0'; + + Result_En<='0'; + + CM_Ack <='1'; --les données ont été reçues + --MyPort<=Cmdreceived(2)(3 downto 0); + PortNum_i<=Cmdreceived(2)(3 downto 0); --récupère les valeurs de port + PeerPort_i<=To_integer(unsigned(Cmdreceived(2)(3 downto 0))); + NocMax_i<=Cmdreceived(2)(7 downto 4); -- et la taille du réseau + PortNumFlag_i<='1'; -- le numéro du port est maintenant connu + CTR<='0' ; + DS_ACK<='0'; + Send_Ack<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + When IsPortZero => --Ce port est-il le n° 0 du NoC ? + BCast<='0'; + Result_En<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + NextRank_i<="0001"; -- le prochain rang à affecter sera le n° 1 + nextr_i<=1; + IsMain_i<=EquFlag; + --MyRank<="0000"; + MainPort_i<="0000"; + --MainAdr<="0000"; -- le port 0 est le main Lib par défaut; + CTR<='0' ; + DS_ACK<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + When SeekMain1 => -- recherche de la lib main + RTS_cmd<='0'; + --RTS_DAT<='1'; + RTS_I<='1'; + CTR<='1' ; -- prêt à recevoir les données Clear To Receive + DS_ACK<='0'; --les données sont attendus + Send_Ack<=BCast_rdy; + I_Send_Ack<=BCAst_rdy; + data_to_send_i(0)<=MPI_INIT & MyPort ; + data_to_send_i(1)<="00000100"; -- la longueur du packet =4 + data_to_send_i(2)<="0000" & MyPort; --propose sa propre adresse + data_to_send_i(3)<=INIT_SEEKMAIN & MyPort ; + DataLen_i<=4; + BCast<='1'; + + Result_En<='0'; + Initialized_i<='0'; + ram_wr<='0'; + rdy<='0'; + ResultOut<=(others=>'0'); + RankAsked_i<='0'; + dma_wr_request<='0'; + When SeekMain2 => -- recherche de la lib main + RTS_cmd<='0'; + RTS_I<='0'; + CTR<='1' ; -- prêt à recevoir les données Clear To Receive + DS_ACK<= DS_RDY; --les données sont acquittées aussitôt reçues + Send_Ack<=BCast_rdy; +-- data_to_send_i(0)<=INIT_SEEKMAIN & MyPort ; +-- data_to_send_i(1)<="00000011"; -- la longueur du packet =3 +-- data_to_send_i(2)<="0000" & MyPort; --propose sa propre adresse +-- DataLen<=3; + BCast<='0'; + Result_En<='0'; + Initialized_i<='0'; + ram_wr<='0'; + rdy<='0'; + ResultOut<=(others=>'0'); + EquFlag_i<='0'; + RankAsked_i<='0'; + dma_wr_request<='0'; + When StoreMain => -- la Main Lib est une autre + BCAST<='0'; + Result_En<='0'; + IsMain_i<='0'; + Initialized_i<='0'; + DS_ACK<=DS_RDY; + Send_Ack<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<=not(MainResp); -- essayer de recevoir tant que le main n'a pas répondu + ram_wr<='1'; + rdy<='0'; + ResultOut<=(others=>'0'); + RankAsked_i<='0'; + EquFlag_i<='0'; + MainPort_i<=DataReceived(0)(3 downto 0); + ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16)); + ram_data_in<=DataReceived(0)(3 downto 0)& DataReceived(2)(3 downto 0); --MainPort & MyRank + dma_wr_request<= '0'; ---pas très sûr + + When AskPeerStat => -- Interroge les données d'initialisation + RTS_cmd<='0'; + if n=0 then + --RTS_DAT<='0'; --on peut envoyer les données + RTS_I<='1'; + else + --RTS_DAT<='0'; --on désactive l'envoie des données + RTS_I<='0'; + end if; + CTR<='0' ; -- prêt à recevoir les données Clear To Receive + DS_ACK<='0'; --les données sont attendus + I_Send_Ack<=I_Send_rdy; + Send_Ack<=Send_rdy; + data_to_send_i(0)<=MPI_INIT & MainPort ; + data_to_send_i(1)<="00000100"; -- la longueur du packet =4 + data_to_send_i(2)<="0000" & MyPort; --indique sa propre adresse + data_to_send_i(3)<=INIT_STAT & MyPort ; + DataLen_i<=4; + BCast<='0'; + Result_En<='0'; + ram_wr<='0'; + rdy<='0'; + ResultOut<=(others=>'0'); + EquFlag_i<='0'; + RankAsked_i<='0'; + dma_wr_request<='0'; + When SetMainFlag => -- Cette Lib est la Main Lib + if (Datareceived(3)(7 downto 4) = INIT_SEEKMAIN) then + RankAsked_i<='1'; + else + RankAsked_i<='0'; + end if; + RTS_cmd<='0'; + Initialized_i<='0'; + RTS_I<='0'; + BCast<='0'; + IsMain_i<='1'; + Result_En<='0'; + --MyRank<="0000"; + MainPort_i<="0000"; + PeerStat_i(0)<='1'; --la main lib est initialisée + CTR<='1'; + DS_ACK<='0'; + ram_wr<='1'; + rdy<='0'; + ResultOut<=(others=>'0'); + EquFlag_i<='0'; + ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16)); + ram_data_in<=(others =>'0'); -- le port vaut 0 et la mainlib est aussi à 0 + dma_wr_request<='1'; + When ReadNoc => + if (Datareceived(3)(7 downto 4) = INIT_SEEKMAIN) then + RankAsked_i<='1' ; + else + RankAsked_i<='0'; + end if; + ram_wr<='0'; -- pas d'écriture en RAM + rdy<='0'; + BCast<='0'; + DS_ACK<='0'; + --IsMain<='0'; + Result_En<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<='1'; + ResultOut<=(others=>'0'); + PortNum_i<=DataReceived(2)(3 downto 0); -- le port qui demande un rang; + PeerPort_i<= To_integer(unsigned(DataReceived(2)(3 downto 0))); + --EquFlag<='1'; + dma_wr_request<='0'; + When GetMainReq => + --RankAsked_i<='1'; + ram_wr<='0'; -- pas + BCast<='0'; + DS_ACK<='1'; + Result_En<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<='1'; + ResultOut<=(others=>'0'); + PortNum_i<=DataReceived(0)(3 downto 0); -- le port qui demande un rang; + EquFlag_i<='1'; + dma_wr_request<='0'; + When GetPeerStat => + --RankAsked_i<='1'; + ram_wr<='0'; -- pas + BCast<='0'; + DS_ACK<=DS_RDY; + Result_En<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<=rd_ok; + ResultOut<=(others=>'0'); + PortNum_i<=DataReceived(0)(3 downto 0); --adresse du Main Port + PeerStat_i(7 downto 0)<=DataReceived(2); -- état des initialisations + EquFlag_i<='0'; + dma_wr_request<=dma_wr; + ram_wr<=wr_ok; + rdy<='0'; + ram_rd<=rd_ok; + Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_Init_Adr+2,ADRLEN)); --incr_vec(Ram_Next_Address,'1'); + ram_address<=Ram_Next_Address; -- + ram_data_in<=DataReceived(2); --enregistrer les ports actifs + + When NewRank => + nport:=to_integer(Unsigned(PortNum)); --port ayant sollicité le rang + nextr_i<=to_integer(unsigned(nextrank)); + if PeerStat(nport)='0' then -- si le rang n'a pas encore été affecté à ce port + nextrank_i<=incr_vec(nextrank,'1'); + RankToPort(to_integer(unsigned(nextrank)))<="0000" & PortNum; + NextAdr:=NextAdr+1; + end if; + data_to_send_i(0)<=MPI_INIT & PortNum ; + data_to_send_i(1)<="00000100"; + data_to_send_i(2)<="0000" & NextRank; --ici c'est la valeur avant incrémentation ! + data_to_send_i(3)<=INIT_SETRANK & PortNum ; + PeerStat_i(nport)<='1'; -- mise à jour du status + DataLen_i<=4; + BCast<='0'; + DS_ACK<='0'; + Result_En<='0'; + EquFlag_i<='1'; + RTS_cmd<='0'; + RTS_I<='1'; + CTR<='0' ; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='1'; + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + + When SendRank => + BCast<='0'; + Result_En<='0'; + EquFlag_i<='1'; + + RTS_I<='1'; + DataLen_i<=4; + RTS_cmd<='0'; + DS_ACK<='0'; + Send_Ack<='0'; + CTR<='0' ; + ram_wr<='0'; + Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_RANK_ADR+Nextr-1,16)); + ResultOut<=(others=>'0'); + RankAsked_i<='1'; + dma_wr_request<='0'; + When RegRank => + RankAsked_i<='0'; + + CTR<='1' ; -- continuer à recevoir les données du NoC + Result_En<='0'; + RTS_cmd<='0'; + DS_ACK<='0'; + Send_Ack<=Send_RDY; + I_Send_ack<=i_send_rdy; + Rts_I<='0'; + BCast<='0'; + EquFlag_i<='1'; + ram_wr<='1'; + + Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_RANK_ADR+Nextr-1,16)); --incr_vec(Ram_Next_Address,'1'); + ram_address<=Ram_Next_Address; -- le rang qui a été envoyé; + -- "le motif 0001 indique juste que le port est bien activé + ram_data_in<="0001" & PortNum; --enregistrer le port qui a fait la demande en RAM + ResultOut<=(others=>'0'); + dma_wr_request<='1'; + When SendPeerStat => + BCast<='0'; + Result_En<='0'; + EquFlag_i<='0'; + RTS_I<=PeerRTS; + RTS_cmd<='0'; + DS_ACK<='0'; + data_to_send_i(0)<=MPI_INIT & PortStat ; + data_to_send_i(1)<="00000100"; + data_to_send_i(2)<=PeerStat(7 downto 0); + data_to_send_i(3)<=INIT_REGISTER & MyPort ; + Send_Ack<=Send_Rdy; + I_Send_Ack<=I_Send_Rdy; + CTR<='0' ; + ram_wr<='0'; + rdy<='0'; + ResultOut<=(others=>'0'); + RankAsked_i<='1'; + dma_wr_request<='0'; + Initialized_i<='1'; + When StoreRank => --le processus qui écoute le Port et qui + --stoke les adresses des autres bib va gérer le stockage du rang + BCAST<='0'; + DS_ACK<='1'; + Send_Ack<='0'; + RTS_cmd<='0'; + EquFlag_i<='0'; + RTS_I<='0'; + CTR<='0'; + Result_En<='0'; + + if ExecTime_out='1' then + MainPort_i<="0000"; + --MyRank<=MyPort; + initialized_i<='0'; + else + MainPort_i<=DataReceived(0)(3 downto 0); + --MyRank<=DataReceived(2)(3 downto 0); + Initialized_i<='1'; + end if; + ram_wr<='1'; + --ram_address<=DataReceived(2); -- le rang qui a été envoyé; + ram_address<= STD_logic_vector(to_unsigned(Core_init_adr+1,16)); + ram_data_in<=DataReceived(0)(3 downto 0)& DataReceived(2)(3 downto 0); --MainPort & MyRank + ResultOut<=(others=>'0'); + RankAsked_i<='0'; + dma_wr_request<='1'; + When SendApp => --ajouter du code pour recevoir l'adr du reg status + Initialized_i<='1'; + ResultOut<="00000001"; -- Init Ok + Result_En<='1'; + PortId<=MyPort; + BCAST<='0'; + DS_ACK<='1'; + Send_Ack<='0'; + RTS_cmd<='0'; + RTS_I<='0'; + CTR<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + dma_wr_request<='0'; + When SpawnApp => + RTS_cmd<='0'; + RTS_I<='0'; + Result_En<='0'; + DS_ACK<=DS_RDY; + BCAST<='0'; + CTR<='0'; --cette mise à 1 permet de ctrler la fin de réception + rdy<='0'; + ram_wr<=wr_ok; + ram_rd<=rd_ok; + Ram_Next_Address_i<= STD_logic_vector(to_unsigned(CORE_BASE_ADR,ADRLEN)); --incr_vec(Ram_Next_Address,'1'); + ram_address<=Ram_Next_Address; -- le rang qui a été envoyé; + -- "le motif 0001 indique juste que le port est bien activé + ram_data_in<=DataToRam; --enregistrer le port qui a fait la demande en RAM + dma_rd_request <= dma_rd; + dma_wr_request <=dma_wr; + RankAsked_i<='0'; + if n>=3 then + ResultOut<=("00000010");--spawn completed + else + ResultOut<=("00000000");--spawn message received + end if; + + When SpawnLoad => + RTS_cmd<='0'; + --RTS_DAT<='1'; --à tester + RTS_I<=PeerRTS; -- pour le timing + Result_En<='0'; + DS_ACK<='0'; + BCAST<='0'; + CTR<='0'; + rdy<='0'; + ram_wr<=wr_ok; + ram_rd<=rd_ok; + data_to_send_i(0)<=SpawnCmd0; + data_to_send_i(1)<="00000100"; + data_to_send_i(2)<=SpawnCmd1; + data_to_send_i(3)<=SpawnCmd2; -- SPAWN_LOAD & MyPort ; + Send_Ack<=Send_Rdy; + I_Send_Ack<=I_Send_rdy; + RankAsked_i<='0'; + if SpawnInit='1' then + ResultOut<=("10000000"); --spawn completed + else + ResultOut<=("01000000");--spawn in progress + end if; + When ErrSpawn => + RTS_cmd<='0'; + RTS_I<='0'; + Result_En<='1'; + DS_ACK<='0'; + Send_Ack<='0'; + BCAST<='0'; + CTR<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + dma_rd_request<='0'; + When EndInit => + RTS_cmd<='0'; + RTS_I<='0'; + Result_En<='0'; + DS_ACK<='0'; + Send_Ack<='0'; + BCAST<='0'; + CTR<='0'; + ram_wr<='0'; + rdy<='0'; + RankAsked_i<='0'; + ResultOut<=(others=>'0'); + dma_wr_request<='0'; + dma_rd_request<='0'; + end case; + end process; + +result_proc:process (ISMain_i,Initialized_i,stInit2,reset,HCL_init) +begin +if reset='1' then + --IsMain1<='0'; + Initialized<='0'; + HCL_Init_i<='0'; + +Else + HCL_init_i<=HCl_init; + Initialized<=Hcl_init; +-- if ismain_i='1' then +-- IsMain1<='1'; +-- end if; + + if Initialized_i='1' and stInit2=EndInit then + Initialized<='1'; + HCL_Init_i<='1'; + elsif stInit2=SendApp then + HCL_Init_i<='1'; + end if; +end if; +end process result_proc; + --================ + --Traitement du Spawn + --=================== + + --================== + NEXT_STInit2_DECODE: process (stInit2,AppReq,Instruction_en, AppAck,PortNumFlag,EquFlag,MainResp,StatAsked,RankAsked,RankSent,CM_RDY, CmdReceived, + BCast_Rdy, DS_RDY, DataReceived,Ht_Start,vPeerStat, Send_RDY, I_Send_RDY,TimeOut,Dma_rd_grant,Dma_wr_grant,cpt,n,clk_cyl,IsMain1,SpawnOn, + Instruction,Hcl_Init,Spawn_done,mainport,PeerStat,PeerRTS,Rec_Data,SpawnInit,grp_id,Ram_data_out,Spawn_grp,MyPort,spawnNbreq_q, + Appsize1,portstat,spawncmd0_q,spawncmd1_q,spawncmd2_q,spawn_grp_q,SpawnReq_q,MyRank,ExecTime_out,peerport,portnum) + variable InitTimeOut :natural:=0; + variable LastPort,Ht_hole : std_logic:='0'; + variable i,nbSpawn,htloc,Ht_Id : natural range 0 to 15:=0; + --variable vPeerStat : std_logic_vector(15 downto 0); + variable vPortStat,nulvect : std_logic_vector(3 downto 0):="0000"; + variable tempval : std_logic_vector(Word-1 downto 0); + begin + --declare default state for next_state to avoid latches + next_stInit2 <= stInit2; --default is to stay in current state + --insert statements to decode next_state + --below is a simple example + vPeerStat_i<=vPeerStat; + SpawnNbReq<=SpawnNbReq_q; + StatAsked_i<=StatAsked; + MainResp_i<=MainResp; + AppSize_i<=AppSize1; + PortStat_i<=PortStat; + SpawnInit_i<=SpawnInit; + grp_id_i<=grp_id; + PeerRTS_i<=PeerRTS; + RankSent_i<=RankSent; + --PortNumFlag_i<=PortNumFlag; + SpawnReq<=SpawnReq_q; + Spawn_done_i<=Spawn_done; + Ht_Start_i<=Ht_Start; + SpawnCmd0<=SpawnCmd0_Q; + SpawnCmd1<=SpawnCmd1_Q; + SpawnCmd2<=SpawnCmd2_Q; + Timeout_i<=Timeout; + clk_cyl_i<=clk_cyl; + n_i<=n; + Cpt_peer<=cpt; + DataToRam<=(others=>'0');--A revoir + dma_rd<='0'; + dma_wr<='0'; + rd_ok<='0'; + wr_ok<='0'; + for i in 0 to 3 loop + Spawn_grp(i)<=Spawn_grp_q(i); + end loop; + case (stInit2) is + + + When Init =>If Instruction_en='1' and AppReq='1' then + If PortNumFlag='1' and IsMain1='1' then + if instruction(7 downto 4)=INIT_SEEKMAIN and (instruction(3 downto 0)/=MyRank) then + Next_stInit2 <=NewRank;--affecter un rang au demandeur. + elsif instruction(7 downto 4)=INIT_STAT then + StatASked_i<='1'; + Next_stInit2 <=SendPeerStat; --envoyer des stat au demandeur + elsif instruction(7 downto 4)=SPAWN_LOAD then + SpawnInit_i<='0'; -- indique le debut du Spawn + Next_stInit2 <=SpawnLoad; + elsif instruction(7 downto 4)=INIT_SPAWN then + SpawnInit_i<='1'; -- indique la fin du + Next_stInit2 <=SpawnLoad; --dans ce cas il s'agit de terminer le spawn + else --ignorer ce message + Next_stInit2 <=SendApp; + end if; + elsif HCL_Init='1' and IsMain1='0' then + Next_stInit2 <=SendApp; --ignorer ce message simplement + else + Next_stInit2 <=GetPortNum; -- initialiser la bibliothèque normalement + end if; + TimeOut_i<=0;PeerRTS_i<='0'; + + elsif SpawnOn='1' and Spawn_done='0' then + Next_stInit2 <=SpawnApp; + TimeOut_i<=0; + end if; + cpt_peer<=0;LastPort:='0';n_i<=0; + When GetPortNum => -- récupérer le numéro du port + + if CM_RDY='1' then + Next_stInit2 <=DecodeData; + end if; + + When DecodeData => -- cet état permet de lire les données reçues du port + --if CM_RDY='1' then + if ((Cmdreceived(2)(3 downto 0) or nulvect)=nulvect) then -- teste si le n° du port est zero + --EquFlag<='1'; + else + --EquFlag<='0'; + end if; + + Next_stInit2 <=IsPortZero; + --end if; + When IsPortZero => + if PortNumFlag='1' then + + End if; + if EquFlag='0' then --tester le numéro de port obtenu + Next_stInit2 <=SeekMain1; -- chercher le numéro de port sur le réseau + else + Next_stInit2<=SetMainFlag; -- enregistrer le numéro de port + End If; + TimeOut_i<=0; + + When SeekMain1 =>If BCast_RDY='1' then -- si tous les envois ont été postés + Next_stInit2<=SeekMain2; + End if; + When SeekMain2 => + If DS_RDY='1' then -- Si un jeu de données a été reçu + if (Datareceived(3)(7 downto 4) = INIT_SETRANK) then + MainResp_i<='1'; + Next_stInit2 <=StoreMain; -- de la librairie pricipale + else + MainResp_i<='0'; + Timeout_i<=0; + end if; + + elsif (ExecTime_Out='1') then + + -- le Noc ne répond pas + -- affecter un numéro en raport avec le port + Next_stInit2 <=SeekMain2; + elsif TimeOut=800 then + --essayer de redemander l'initialisation + assert true report "Ex4:seekmain ->redemander l'initialisation" + severity failure; + Timeout_i<=0; + Next_stInit2 <=SeekMain1; + else + Timeout_i<=TimeOut+1; + End if; + + + + When StoreMain => + if DataReceived(3)(7 downto 4)= INIT_SETRANK then + -- enregistrer le Main Adresse et les adresses des autres processus + -- dans la variable prévue à cet effet + Next_stInit2 <=StoreRank; + + elsif Datareceived(3)(7 downto 4) = INIT_SEEKMAIN then + -- ignorer ce message + Next_stInit2 <=StoreMain; --essayer de recevoir le rang + + + end if; + + When StoreRank => + --il faut prévoir du code pour s'assurer que la RAM a bien enregistrer + -- la donnée ... + if dma_wr_grant = '1' then + if clk_cyl=2 then --prévoir deux cycle d'horloge pour lire en RAM + Next_stInit2 <=AskPeerStat; + TimeOut_i<=0; + clk_cyl_i<=0; + else + clk_cyl_i<=clk_cyl+1; + end if; + else + Next_stInit2 <=StoreRank; + TimeOut_i<=0; + clk_cyl_i<=0; + end if; + When AskPeerStat =>if n=0 then + If I_SEND_RDY='1' then -- si tous les envois ont été postés + n_i<=1; + StatAsked_i<='0'; + End if; + elsif n=1 then + If I_SEND_RDY='0' then -- si tous les envois ont été postés + Next_stInit2<=GetPeerStat; + StatAsked_i<='1'; + MainResp_i<='0'; + n_i<=0; + End if; + end if; + When GetPeerStat => rd_ok<='0'; + if n=0 then + rd_ok<='1'; + If DS_RDY='1' then -- Si un jeu de données a été reçu + if (Datareceived(3) = INIT_REGISTER & MainPort ) then + MainResp_i<='1'; + n_i<=n+1; + + else + MainResp_i<='0'; + Timeout_i<=0; + n_i<=n; + end if; + + elsif TimeOut=1800 then + --essayer de redemander les statistiques + assert true report "Ex4:GetPeerStat timeout ->Les statistiques n'ont pas été reçu" + severity failure; + Timeout_i<=0; + If StatAsked='1' then + Next_stInit2 <=AskPeerStat; -- ceci n'est pas sûr + else + Next_stInit2 <=GetPeerStat; + end if; + else + Timeout_i<=TimeOut+1; + End if; + elsif n=1 then --écrire le résultat de l'initialisation + dma_wr<='1'; + if dma_wr_grant='1' then + n_i<=n+1; + wr_ok<='1'; + end if; + elsif n=2 then + n_i<=n+1; --écriture dans la RAM + elsif n=3 then + n_i<=0; + dma_wr<='0'; + Next_stInit2 <=SendApp; -- de la librairie pricipale + end if; + When SetMainFlag => + if dma_wr_grant='1' then + TimeOut_i<=0; + Next_stInit2 <=ReadNoc; + elsif Timeout=800 then + assert true report "Ex4:SetMainFlag timeout ->La mémoire n'est pas dispo dma_wr_grant=0" + severity failure; + Next_stInit2 <=SendApp; + else + TimeOut_i<=TimeOut+1; +-- end if; -- il est envisagée de terminer le programme à ce point + end if; + when ReadNoc => if DS_RDY='1' then + if (Datareceived(3)(7 downto 4) = INIT_STAT) then + StatAsked_i<='1' ; + Next_stInit2 <=SendPeerStat; + LastPort:='0'; + else + StatAsked_i<='0'; + Next_stInit2 <=GetMainReq; + end if; + + Timeout_i<=0; + elsif Timeout=400 then + assert true report "Ex4:ReadNoc timeout pas de données lues sur le NoC après 200 cycles" + severity failure; + Timeout_i<=0; + --if StatAsked = '1' then + --Next_stInit2 <=ErrSpawn; --il y a eu une erreur + Next_stInit2 <=SendApp; + -- else + -- Next_stInit2 <=SendPeerStat; + -- end if; + else + TimeOut_i<=TimeOut+1; + end if; + + When GetMainReq => if RankAsked='1' and PeerStat(PeerPort)='0' then + Next_stInit2 <=NewRank; -- un nouveau rang est demandé + else + Next_stInit2 <=ReadNoC; -- sinon essayer encore de lire un jeu de données. + end if; + When NewRank => + Next_stInit2 <=SendRank; + When SendRank => + if I_Send_RDY='1' then --RankSent + Next_stInit2 <=RegRank; + RankSent_i<='1'; -- le rang a été envoyé + TimeOut_i<=0; -- prépare le traitement de la prochaine requête + -- d'attente des ports + elsif Timeout=800 then + assert true report "Impossible d'envoyer le rang" + severity failure; + timeout_i<=0; + else + TimeOut_i<=TimeOut+1; + end if; + When RegRank => + --il faut prévoir du code pour s'assurer que la RAM a bien enregistrer + -- la donnée ... + if dma_wr_grant = '1' then +-- if DS_RDY='1' then + RankSent_i<='0'; + if DS_RDY='0' then + + Next_stInit2 <=ReadNoc; + end if; + elsif Timeout=800 then + Next_stInit2 <=SendApp; + assert true report "Ex4:RegRank Timeout dma_wr_grant=0 " + severity failure; + else + TimeOut_i<=TimeOut+1; +-- end if; -- il est envisagée + end if; + --calcul de la taille de l'appli + HtLoc:=0; + for i in 0 to 7 loop + if peerStat(i)='1' then --trouve le prochai rang libre + HtLoc:=HtLoc+1; + end if; + end loop; + AppSize_i<=std_logic_vector(to_unsigned(HtLoc,4)); + + When SendPeerStat => + + if cpt<=unsigned(NoCMax)and LastPort='0' then + if peerRts='0' then -- pas encore envoyer les données alors les préparer + if StatAsked='1' then + + PortStat_i<=PortNum; + vPortStat:=std_logic_vector(to_unsigned(PeerPort,4)); + else + PortStat_i<=std_logic_vector(to_unsigned(cpt,4));--Port à contacter + vPortStat:=std_logic_vector(to_unsigned(cpt,4)); + end if; + + if StatAsked='1' then + LastPort:='1'; -- on traite u seul port celui qui en a fait la demande + if PeerStat(PeerPort)='1' then + PeerRts_i<='1'; + end if; + else + if (PeerStat(cpt)='1') and not(vPortStat=MyPort) then + PeerRts_i<='1'; + end if; + if cpt Impossible d'envoyer sur le NoC" + severity failure; + else + TimeOut_i<=TimeOut+1; + end if; + end if; + elsif PeerRTS='1' then -- le dernier port est il activé ? + if I_Send_RDY='1' then + RankSent_i<='1'; -- les stat ont été envoyé + TimeOut_i<=0; -- prépare le traitement de la prochaine requête + PeerRts_i<='0'; + if statAsked='1' then + -- Next_stInit2<=ReadNoc; + + Next_stInit2<=SendApp; --terminer l'application + end if; + + elsif TimeOut=100 then + Next_stInit2 <=EndInit; + assert true report "Ex4:SendPeerStat Timeout -> Impossible d'envoyer sur le NoC" + severity failure; + else + TimeOut_i<=TimeOut+1; + end if; + else + Next_stInit2<=SendApp; + end if; + When SendApp => -- envoyer au programme un signal + -- et attendre un acquittement et l'adresse de base + If AppAck='1' then + Next_stInit2 <=EndInit; + end if; + + When SpawnLoad => + + if n=0 then + ht_id:=to_integer(unsigned(rec_data(0)(3 downto 0))); + vPeerStat_i<=PeerStat; --récupérer la situation actuelle des tâches créées + if IsMain1='1' and SpawnInit='0' then + SpawnNbReq<=to_integer(unsigned(Instruction(3 downto 0))); -- sauver le nombre de HT à créer + + n_i<=1; + SpawnReq(ht_id)<='1'; --Note l'id de HT qui a appelé le Spawn + elsif IsMain1='1' and SpawnInit='1' then -- il faut envoyer les acquittements + ht_id:=to_integer(unsigned(rec_data(0)(3 downto 0))); + Spawn_grp(grp_id)(ht_id)<='1'; --noter le port du Fils Spawné dans ce groupe + Ht_start_i<=0; --compte le nombre de tâches chargées + n_i<=6; + + else + if SpawnOn='1' then --if IsMain_i='0' then -- il faut juste charger puis activer la tâche + n_i<=7; + end if; + assert true + Report "SpawnLoad : Cas non prévu !" + severity failure; + end if; + elsif n=1 then + if PeerStat=SpawnReq_q then --tous les Hts ont appelés Spawn ? + ht_hole:='0'; + L1: for i in 0 to 15 loop + if vPeerStat(i)='0' then + SpawnDest<=std_logic_vector(to_unsigned(i,4)); -- le port à activer + SpawnCmd0<=MPI_SPAWN & std_logic_vector(to_unsigned(i,4)); + vPeerStat_i(i)<='1'; + Ht_Start_i<=Ht_Start+1; + Ht_Hole:='1'; -- une place a été trouvé + else + Ht_hole:='0'; -- pas de place trouvé + end if; + exit L1 when ht_hole='1'; + end loop L1; + if Ht_hole='0' then -- toutes les tâches n'ont pas été créés + -- aller à la fin ! en signalant une erreur! + SpawnCMd2<=Spawn_Err & "0001"; --erreur pas assez de ports sur le NoC + n_i<=9; + else + n_i<=n+1; + SpawnCmd1<=PeerStat(7 downto 0); + SpawnCmd2<=SPAWN_START & MyPort; + end if; + else --Tous les Hts n'ont pas appelé Spawn encore + Next_stInit2<=SendApp; --on termine normalement + n_i<=0; + end if; + elsif n=2 then + PeerRTS_i<='1'; -- envoyer les données du Spawn + n_i<=n+1; + elsif n=3 then + if I_Send_RDy='1' then + n_i<=n+1; + PeerRts_i<='0'; + end if; + elsif n=4 then + if SpawnInit='0' then + if Ht_Start>=SpawnNbReq_q then + n_i<=n+1; + else + n_i<=1; -- passer à la création du HT suivant + end if; + else + n_i<=7; -- passer au contact du HT suivant + end if; + elsif n=5 then + -- Aller à la fin le résultat du Spawn + + n_i<=10; + elsif n=6 then + nbSpawn:=0; + for i in 0 to 15 loop + if Spawn_grp(grp_id)(i)='1' then + nbSpawn:=nbSpawn+1; + end if; + end loop; + if nbSpawn=SpawnNbReq_q then + n_i<=n+1; --aller renvoyer les réponses + else + n_i<=10; --fin du Spawn + + end if; + elsif n=7 then + Ht_hole:='0'; +L2: for i in 0 to 7 loop --for i in Ht_start to 7 loop + if i>=Ht_start then + if vPeerStat(i)='1' and Spawn_grp(grp_id)(i)='0' then --on avertit les membres du groupe parent + --mais pas ceux du groupe Fils ! + SpawnDest<=std_logic_vector(to_unsigned(i,4)); -- le port à avertir + SpawnCmd0<=MPI_ACK & std_logic_vector(to_unsigned(i,4)); + vPeerStat_i(i)<='0'; + Ht_Start_i<=i+1; -- le prochain Ht à prévenir + Ht_Hole:='1'; -- Une tâche doit être avertie + else + Ht_hole:='0'; -- + end if; + end if; + exit L2 when ht_hole='1'; + end loop L2; + n_i<=n+1; + elsif n=8 then + if Ht_hole='1' then -- + -- un HT existant à prévenir ! + SpawnCmd1<=Spawn_grp(grp_id)(7 downto 0); + SpawnCMd2<=MPI_SPAWN & MyRank; -- fin du Spawn + n_i<=2; --envoyer la donnée sur le réseau + elsif vpeerstat /=spawn_grp(grp_id) then --il ne reste plus de membres à prévenir ? + n_i<=7; --on est sorti mais ce n'est pas la fin + + else -- fin du Spawn car tous ont été averti + n_i<=10; + SpawnNbReq<=0; + SpawnReq<=(others=>'0'); + vPeerStat_i<=(others=>'0'); + grp_id_i<=grp_id+1; --incrementer le compteur de groupes************ + end if; + elsif n=9 then + assert true report "error in Spawn command" + severity failure; + elsif n=10 then + n_i<=0; + Next_stInit2<=SendApp; + end if; + + When SpawnApp=> + --Mise à jour du bit 6 du registre status du COre. + if n>=0 and n <4 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; + + if n=0 then + if DS_RDY='1' then --- + if Datareceived(3)(7 downto 4)=SPAWN_START then + n_i<=n+1; + else + Next_stInit2<=ErrSpawn; + n_i<=0; --erreur instruction incorrecte + end if; + + rd_ok<='1'; + wr_ok<='0'; + end if; + elsif n=1 or n=2 then + if dma_rd_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + end if; + rd_ok<='1'; + wr_ok<='0'; + + elsif n=3 then + if dma_rd_grant='1' and dma_wr_grant='1' then + n_i<=n+1; + tempval:=Ram_data_out; + tempval(6):='1'; + + dataToram<=tempval; + rd_ok<='0'; + wr_ok<='1'; + else + rd_ok<='1'; + wr_ok<='0'; + end if; + elsif n=4 then + if spawninit='0' then + Spawn_done_i<='1'; + end if; + rd_ok<='0'; + wr_ok<='0'; + n_i<=0; + Next_stInit2<=EndInit; + end if; + + When ErrSpawn => + assert true + report "Ex4/stInit2/SpawnApp:Erreur lors de Spawn" + severity failure; + Next_stInit2<=Init; + When EndInit=> + + StatAsked_i<='0'; --reset de ces variables + Next_stInit2<=Init; + end case; + end process; + +--================================================ +--sauvegarde du rang et du main port à l'adresse de retour de la fonction Init +--================================================== + +--==================================================== +--envoie des données sur le port +--=================================================== +selector<=(Rcv_on,Cmd_on,Snd_on); + +process (selector,Rport_out_rd_en,cport_out_rd_en,sPort_in_wr_en ,cPort_in_wr_en, + tosend ,tosend4) +begin + case selector is + + when "000" => port_in_data<=(others=>'-'); + Port_in_wr_en<='0'; + Port_out_rd_en<='0'; + + when "001" => port_in_data<=tosend; --envoie de données + Port_in_wr_en<=sPort_in_wr_en ; + Port_out_rd_en<='0'; + when "101" => port_in_data<=tosend; --envoie de données + Port_in_wr_en<=sPort_in_wr_en ; + Port_out_rd_en<=Rport_out_rd_en ; + when "010" | "110" | "011" | "111" => + port_in_data<=tosend4; --envoie de commande GetPort + Port_in_wr_en<=cPort_in_wr_en; + Port_out_rd_en<=cport_out_rd_en; + + when "100" => port_in_data<=(others=>'-'); -- réception de données + Port_in_wr_en<='0'; + Port_out_rd_en<=Rport_out_rd_en ; + + when others => port_in_data<=(others=>'-'); + Port_in_wr_en<='0'; + Port_out_rd_en<='0'; + end case; +end process; + +--================================================== + + --=============================================================== + --processus d'accès au réseau + --=============================================================== + + + + + + preceiv:process(clk,reset) + + variable origport,destport : natural range 0 to 15; + variable dcount,dlen ,rtimeout:natural range 0 to 1023; + variable ptype : std_logic_vector(3 downto 0); + variable bad_paquet :std_logic:='0'; + begin +-- + + if reset='1' then + etrec<=r_wait; + destport:=1; + rtimeout:=0; + bad_paquet:='0'; + spawnon<='0'; + else + if rising_edge(clk) then + case etrec is + when r_wait => + + rtimeout:=0; + bad_paquet:='0'; + --modifier le 01-08-pour gérer le Spawn + if Port_out_data_available='1' and Cmd_on='0' then + ptype:=port_out_data(7 downto 4); + origport:=to_integer(unsigned(port_out_data(3 downto 0))); + + if ptype=MPI_SPAWN and not(portnumflag='1') then + etrec<=r_dlen; --identification de la signature d'en tête valide + Datareceived(0)<=Port_out_data; --stocker l'entête + bad_paquet:='0'; + SpawnOn<='1'; --le spawn est actif + elsif Instruction_en='0' and CTR='0' and Hcl_init= '0' then + --il faut éliminer ce paquet qui est inoportun ! + Bad_paquet:='1'; + etrec<=r_glen; --il faut ignorer cette donnée et quitter + dcount:=1; + elsif CTR='1' then + if ptype=MPI_INIT or ptype=INIT_SETRANK or ptype=INIT_SEEKMAIN or ptype=INIT_REGISTER then + etrec<=r_dlen; --identification de la signature d'en tête valide + Datareceived(0)<=Port_out_data; --stocker l'entête + bad_paquet:='0'; + else + --une donnée non attendue est présente sur le port + etrec<=r_dlen; --il faut ignorer cette donnée et quitter + dcount:=1; + bad_paquet:='1'; + Datareceived(0)<=(others=>'0'); + end if; + end if; + --elsif Port_out_data_available='1' and CTR='0' then + -- etrec<=r_drop; + else + + etrec<=r_wait; + end if; + DS_RDY<='0'; + When r_drop => -- ignorer les messages qui arrivent à ce noeud tant que + --l'application n'a pas été initialisée + if port_out_data_available='0' then + etrec<=r_end; + dcount:=0; + + end if; + + + + --Rport_out_rd_en<='1'; --lire les données qui sont dans le tampon de sortie + DS_RDY<='0'; + when r_Dlen => --positionnement du mot de longueur des données + if Port_out_data_available ='1' then + + --Rport_out_rd_en<='1'; + etrec<=r_glen; + rtimeout:=0; + else + rtimeout:=rtimeout+1; + if rtimeout>=30 then + assert true report "Ex4:etrec r_glen Timeout -> Impossible de recevoir du NoC" + severity failure; + Exectime_out<='0'; --read Noc time out + etrec<=r_end; -- données pas prêtes + end if; + + + end if; + DS_RDY<='0'; + -- + when r_glen => --lecture effective de la longueur des données + if port_out_data_available='1' then + dlen:=to_integer(unsigned(port_out_data(Word-1 downto 0))); + Datareceived(1)<=Port_out_data; + --RPort_out_rd_en<='0'; + etrec<=r_data; + dcount:=2; -- initialisation du compteur de reception (il y a + -- déjà deux mots reçues + else + rtimeout:=rtimeout+1; + if rtimeout>=30 then + assert true report "Ex4:etrec Timeout -> Impossible de recevoir sur le NoC" + severity failure; + ExecTime_out<='0'; + etrec<=r_end; -- données pas prêtes + end if; + + end if; + DS_RDY<='0'; + when r_data => -- lecture des données + if port_out_data_available='1' then + + --Rport_out_rd_en<='1'; --autoriser la lecture + if bad_paquet='0' then + DataReceived(dcount)<=Port_out_data; --récupération des données + else + DataReceived(2)<=(others=>'0'); + --ignorer ces données + end if; + --assert true report "Donnée lue :"; --& string(unsigned(port4_out(Word-1 downto 0))) + DS_RDY<='0'; + dcount:=dcount+1; + --severity note; + if dlen <=dcount then -- ce doit être égale ici et non <= ??? + etrec<=r_end; + DS_RDY<= not bad_paquet; -- jeu de données disponibles + elsif dcount=255 then --dépassement de la capacité + DS_RDY<='0'; + etrec<=r_end; + end if; + else + rtimeout:=rtimeout+1; + if rtimeout>=30 then + ExecTime_out<='0'; + etrec<=r_end; -- données pas prêtes + end if; + DS_RDY<='0'; + + end if; + when r_pulse => + etrec<=r_end; + DS_RDY<=not bad_paquet; + when r_end => + + --rPort_out_rd_en <='0'; + + if DS_ACK='1' or rtimeout> 30 or (CTR='0' and SpawnOn='0') or bad_paquet='1' then + DS_RDY<='0'; + SpawnOn<='0'; + etrec<=r_wait; + else + DS_RDY<=DS_RDY; + end if; + end case; + end if;--reset='1' + end if; + end process preceiv; + + val_preceiv: process (etrec) + begin + case etrec is + when r_wait => +-- DS_RDY<='0'; + rcv_on<='0'; + Rport_out_rd_en <='0'; + when r_dlen => +-- DS_RDY<='0'; + Rport_out_rd_en <='1'; + rcv_On<='1'; + when r_drop => +-- DS_RDY<='0'; + Rport_out_rd_en <='1'; + rcv_On<='1'; + when r_glen => + Rport_out_rd_en <='1'; +-- DS_RDY<='0'; + rcv_On<='1'; + when r_data => + Rport_out_rd_en <='1'; +-- DS_RDY<='0'; + rcv_On<='1'; + when r_pulse => + Rport_out_rd_en <='0'; + rcv_On<='1'; +-- DS_RDY<='1'; + when r_end => + Rport_out_rd_en <='0'; +-- DS_RDY<='0'; + rcv_On<='0'; + when others => + Rport_out_rd_en <='0'; +-- DS_RDY<='0'; + rcv_On<='0'; + end case; + end process; + + psend:process(clk,reset) + --génération des paquets à partir du port courant + variable pactype :natural range 0 to 15; + variable destport : natural range 0 to 15:=0; + variable realdlen, i,i_pair : natural range 0 to 255; + variable MaxPort : natural :=4; -- en fait ne doit pas être 0 + + + begin + if rising_edge(clk) then + if reset='1' then + etsnd<=s_init; + + + + else -- le process s'exécute sur chaque front + -- montant de l'horloge + case etsnd is + when s_init => tosend<=(others=>'-'); + MaxPort :=to_integer(unsigned(NOCMAX)); + sPort_in_wr_en<='0'; + BCast_RDY<='0'; -- pas la fin de du Broadcasting + Send_RDY<='0'; + if port_in_full='0' and Rts_dat='1' then --on peut aussi tester si le port est vide + + Snd_on<='1'; + if Bcast='1' then -- envoyer à tous les ports le même message ? + DestPort :=0; + else + DestPort:=to_integer(unsigned(data_to_send(0)(3 downto 0))); + end if; + etsnd<=s_head; + end if; + when s_head => -- construction et envoie de l'en-tête + Send_RDY<='0'; --l'envoi commence + BCast_RDY<='0'; + Snd_on<='1'; + --pactype:=to_integer(MPI_INIT);-- + pactype:=to_integer(unsigned(data_to_send(0)(7 downto 4))); + --realdlen:=to_integer(unsigned(Datalen)); + --? destport:=MAXPORT; -- le port de destination + + tosend <=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4)); + sPort_in_wr_en<='1'; -- + + i:=1; + etsnd<=s_len2; -- passer à l'état suivant + + when s_len => + BCast_RDY<='0'; + Send_RDY<='0'; + Snd_on<='1'; + --tosend<=(STD_LOGIC_VECTOR(to_unsigned(Realdlen,8))); + tosend<=data_to_send(1); + sPort_in_wr_en <='1'; + + + --port1_in<=tosend1; --copie directe sur le port + etsnd<=s_len2; + when s_len2 => + --tosend<=(STD_LOGIC_VECTOR(to_unsigned(realdlen,8))); + sPort_in_wr_en<='1'; + tosend<=data_to_send(1); + + --port1_in<=tosend1; --copie directe sur le port + etsnd<=s_data; + BCast_RDY<='0'; + Send_RDY<='0'; + Snd_on<='1'; + i:=i+1; + when s_data => + Snd_on<='1'; + if Port_in_full='0' and RTS_dat='1' then + sPort_in_wr_en<='1'; + + --envoie des données sur le port + tosend<=data_to_send(i); + + + if i+1>=datalen then + etsnd<=s_end; + Send_RDY<='1'; --l'envoi est terminé + if BCast='1' and destport=MAXPort then + BCAST_RDY<='1'; --l'envoi collectif aussi + else + BCast_RDY<='0'; + + end if; + else + BCast_RDY<='0'; + Send_RDY<='0'; + i:=i+1; + end if; + elsif port_in_full='1' then + sPort_in_wr_en<='0'; + else + sPort_in_wr_en<='0'; + BCast_RDY<='0'; + Send_RDY<='0'; + end if; + when s_end => + tosend<=(others=>'-'); + + sPort_in_wr_en<='0'; + if Bcast='1' then + if destPort + if Port_in_empty='1' and RTS_Cmd='1' then + etcmd<=cmdpost; + + end if; + destport:=0; + ctimeout:=0; + origport:=1; + dcount<=0; + when cmdpost => + if Port_in_empty='1' then + etcmd<=cmdread; + end if; + + when cmdpostidle => --permet juste la prise en compte de la commande + etcmd<=cmdread; + dcount<=0;-- initialisation du compteur de reception + when cmdread => + + + ctimeout:=0; + + if Port_out_data_available='1' then + mport:=to_integer(unsigned(port_out_data(7 downto 4))); + pid:=to_integer(unsigned(port_out_data(3 downto 0)))+1; + CmdReceived(dcount)<=port_out_data; + --cdata_out_en(origport)<='1'; +-- if pid=origport then --le port a été bien identifié + etcmd<=cmdglen; -- + dcount<=dcount+1; +-- else +-- etcmd<=cmdtimeout; +-- end if; + else + + etcmd<=cmdread; + end if; + + + when cmdlen => --positionnement du mot de longueur des données + if Port_out_data_available='1' then + + etcmd<=cmdglen; + ctimeout:=0; + else + ctimeout:=ctimeout+1; + if ctimeout>=30 then + assert true report "Ex4:etcmd Timeout -> impossible de recevoir du le NoC" + severity failure; + etcmd<=cmdtimeout; -- données pas prêtes + end if; + + + end if; + when cmdglen => --lecture effective de la longueur des données + if Port_out_data_available='1' then + cdlen<=to_integer(unsigned(port_out_data(Word-1 downto 0))); + CmdReceived(dcount)<=port_out_data; + etcmd<=cmddata; + dcount<=dcount+1; + else + ctimeout:=ctimeout+1; + if ctimeout>=30 then + --time_out(destport)<='1'; + assert true report "Ex4:etcmd Timeout -> impossible de recevoir du le NoC" + severity failure; + etcmd<=cmdtimeout; -- données pas prêtes + end if; + + end if; + + when cmddata => + if (port_out_data_available='1' and ctimeout<30) then + + --cdata_out_en(origport)<='1'; + mport:=to_integer(unsigned(port_out_data(7 downto 4))); + --attention les ports sont numérotés à partir de 0 + pid:=to_integer(unsigned(port_out_data(3 downto 0)))+1; + CmdReceived(dcount)<=port_out_data; + if (dcount>=cdlen-1 ) then--attention le compteur de données commence à 0 + etcmd<=cmdend; + --CM_RDY<='1'; + else + dcount<=dcount+1; + end if; + Else + + if ctimeout>=30 then + --time_out(destport)<='1'; + etcmd<=cmdtimeout; -- données pas prêtes + assert true report "Ex4:etcmd. cmddata Timeout -> impossible de recevoir du le NoC" + severity failure; + else + ctimeout:=ctimeout+1; + etcmd<=cmdend; + end if; + end if; + when cmdend => + + etcmd<=cmdstart; + + when cmdtimeout => + + etcmd<=cmdstart; + end case; + --sorigport<=origport; + end if; --reset='1' + end if; + end process pcmd; + +majetcmd: process (etcmd,data_to_send, port_out_data_available, dcount,port_out_data) +variable origport : natural; +variable i:natural:=0; + begin + case etcmd is + when cmdstart => + i:=0; + Port_in_cmd_en<='0'; + tosend4<=(others=>'-'); + cport_out_rd_en<='0'; + cport_in_wr_en<='0'; + CM_RDY<='0'; + Cmd_on<='0'; + when cmdpost | cmdpostidle => + cport_in_wr_en<='1'; + tosend4<=data_to_send(0); ---code pour getportid + Port_in_cmd_en<='1'; + cport_out_rd_en<='0'; + CM_RDY<='0'; + Cmd_on<='1'; + when cmdread => + tosend4<=(others=>'-'); + cPort_in_wr_en<='0'; + cport_out_rd_en<=port_out_data_available; + --CmdReceived(dcount)<=port_out_data; --mettre les données dans le tampon + Port_in_cmd_en<='1'; + CM_RDY<='0'; + Cmd_on<='1'; + when cmdlen |cmdglen => --positionnement du mot de longueur des données + tosend4<=(others=>'-'); + cport_in_wr_en<='0'; + cport_out_rd_en<=port_out_data_available; + Port_in_cmd_en<='1'; + --CmdReceived(dcount)<= port_out_data; + CM_RDY<='0'; + Cmd_on<='1'; + when cmddata => + tosend4<=(others=>'-'); + cport_in_wr_en<='0'; + cport_out_rd_en<=Port_out_data_available; + Port_in_cmd_en<='1'; + --CmdReceived(dcount)<=port_out_data; --mettre les données dans le tampon + i:=i+1; + CM_RDY<='0'; + Cmd_on<='1'; + when cmdend => + tosend4<=(others=>'-'); + cport_in_wr_en<='0'; + cport_out_rd_en<='0'; + --CmdReceived(dcount)<=port_out_data; + Port_in_cmd_en<='0'; + CM_RDY<='1'; + Cmd_on<='0'; + when cmdtimeout => + tosend4<=(others=>'-'); + cport_in_wr_en<='0'; + cport_out_rd_en<='0'; + Port_in_cmd_en<='0'; + Cmd_on<='1'; + cm_rdy<='0'; + end case; + +end process majetcmd ; +snd_start<=snd_start_q; +i_send_val:process(et_sendproc,snd_start_q,HCL_Init,Send_RDY,RTS_I,Snd_Ack,I_send_ack,data_to_send,Bcast_rdy,Bcast) +begin +snd_start_i<=snd_start_q; +RTS_DAT<='0'; +case et_sendproc is +when Hcl_Init_off => + if RTS_I='1' and i_send_ack='0' then + RTS_DAT<='1'; + elsif i_send_ack='1' then + + RTS_DAT<='0'; + end if; + i_send_rdy<=send_rdy; + for i in 0 to 3 loop + Snd_data(i)<=(others=>'0'); + end loop; +When Hcl_Init_on => +if RTS_I='1' and snd_ack='0' then + snd_start_i<='1'; + elsif i_send_ack='1' then + + snd_start_i<='0'; + else + snd_start_i<='0'; + end if; + i_send_rdy<=snd_ack; + Snd_data<=data_to_send; +end case; +end process; +mae_send:process(clk,reset) +begin + if reset='1' then + et_sendproc<=Hcl_init_off; + elsif rising_edge(clk) then + +if HCL_Init='1' then + et_sendproc<=Hcl_init_on; +else + et_sendproc<=Hcl_init_off; +end if; +end if; +end process; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/Ex0_Fsm.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/Ex0_Fsm.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/Ex0_Fsm.vhd (revision 142) @@ -0,0 +1,210 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM +-- +-- Create Date: 05:37:34 03/06/2012 +-- Design Name: +-- Module Name: Ex0_Fsm - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Fournit le temps en µs depuis l'initialisation de la bibliothèque +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library NocLib ; + +--use NocLib.CoreTypes.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Ex0_Fsm is + Port ( Initialized : in STD_LOGIC; + + Instruction : in STD_LOGIC_VECTOR (7 downto 0); + instruction_en: in STD_LOGIC; --ceci n'est pas nécessaire dans ce module + -- car le module fonctionne en permanence. + clk : in STD_LOGIC; + reset : in STD_LOGIC; + ClkRate : in STD_LOGIC_VECTOR; --la fréquence de l'horloge en Mhz + uTimeResult : out STD_LOGIC_VECTOR; + TickResult : out STD_LOGIC_VECTOR; + OvFus : out STD_Logic:='0' + ); +end Ex0_Fsm; + +architecture Behavioral of Ex0_Fsm is + + --Use descriptive names for the states, like st1_reset, st2_search + type state_type is (Init,COunt,UsOut,OverFlow); + signal state, next_state : state_type; + --Declare internal signals for all outputs of the state-machine + signal Tick_Count,Tick_Count_i: std_logic_vector(31 downto 0):=(others=>'0'); + signal Time_Ucount,Time_Ucount_i :std_logic_vector(31 downto 0):=(others=>'0'); + signal OvF,Ovf_us,ovF_i,zero :std_logic; -- overflow flag + signal ClkR_Count,Clkr_Count_i : std_logic_vector(ClkRate'high downto ClkRate'low):=(others=>'0'); + signal en : std_logic:='1'; + --other outputs +begin +utime_PROC: process (clk) + begin + if (rising_edge(clk)) then + if (reset = '1') or Initialized='0' then + state <= init; + -- Time_UCount<= (others=>'0'); + Tick_Count <=(others=>'0'); + else + state <= next_state; + TickResult<= Tick_Count; + uTimeResult <=Time_ucount; + OvF<=OvF_i; + OvfUs<=Ovf_us; + Tick_count<=Tick_count_i; + Time_UCount<= Time_UCount_i; + end if; + end if; + end process; + + --MOORE State-Machine - Outputs based on state only + OUTPUT_DECODE: process (state,clkr_count,time_ucount,Ovf,clkrate) + FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is + --this function increments a std_logic_vector type by '1' + VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE tb : std_logic_vector(s1'high downto s1'low); + BEGIN + tb(s1'low) := en; + V := s1; + for i in (V'low + 1) to V'high loop + tb(i) := V(i - 1) and tb(i -1); + end loop; + for i in V'low to V'high loop + if(tb(i) = '1') then + V(i) := not(V(i)); + end if; + end loop; + return V; + end incr_vec; -- end function + + +FUNCTION dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is + --this function decrements a std_logic_vector type by '1' + VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE tb : std_logic_vector(s1'high downto s1'low); + BEGIN + tb(s1'low) := not(en); + V := s1; + for i in (V'low + 1) to V'high loop + tb(i) := V(i - 1) or tb(i -1); + end loop; + for i in V'low to V'high loop + if(tb(i) = '0') then + V(i) := not(V(i)); + end if; + end loop; + return V; + end dcr_vec; -- end function +FUNCTION all_ones(s1:std_logic_vector) return std_logic is + --this function tells if all bits of a vector are '1' + --return value Z is '1', then vector has all 1 bits + --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE Z : std_logic; + BEGIN + Z := s1(s1'low); + FOR i IN (s1'low+1) to s1'high LOOP + Z := Z AND s1(i); + END LOOP; + RETURN Z; + END all_ones; -- end function +FUNCTION all_zeros(s1:std_logic_vector) return std_logic is + --this function tells if all bits of a vector are '0' + --return value Z if '1', then vector has all 0 bits + --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE Z : std_logic; + BEGIN + Z := '0'; + FOR i IN (s1'low) to s1'high LOOP + Z := Z OR s1(i); + END LOOP; + RETURN not(Z); + END all_zeros; -- end function + + begin + Tick_count_i<=Tick_COunt; + Ovf_i<=Ovf; + en<='1'; + Clkr_count_i<=Clkr_Count; + --insert statements to decode internal output signals + --below is simple example + case state is + When Init => + Clkr_Count<=ClkRate; --initialiser le décompte + Time_uCount_i<=( others =>'0'); -- mettre à 0 le compteur des µS + Tick_Count_i<=(others =>'0'); --mettre à 0 les ticks + When Count => + Tick_count_i<=incr_vec(Tick_Count,en); + ClkR_Count_i<=dcr_vec(Clkr_Count,en); --compteur de µs + zero<=all_zeros(ClkR_Count); -- + OvF_i<=All_ones(Tick_count); -- + when UsOut => + Time_Ucount_i<=incr_vec(time_ucount,en); + Clkr_Count<=ClkRate; + Tick_count_i<=incr_vec(Tick_Count,en); + OvF_i<=All_ones(Tick_count); + zero<='0'; + OvF_us<=All_ones(Time_Ucount); + when OverFlow => + Tick_count_i<=incr_vec(Tick_Count,en); --compteur de tick + ClkR_Count<=dcr_vec(Clkr_Count,en); + OvF_us<=All_ones(Time_Ucount); + OvF_i<=All_ones(Tick_count); + end case; + end process; + + NEXT_STATE_DECODE: process (state, Initialized, zero, OvF) + begin + --declare default state for next_state to avoid latches + next_state <= state; --default is to stay in current state + --insert statements to decode next_state + --below is a simple example + case (state) is + when Init => + if Initialized = '1' then + + next_state <= count; + end if; + when Count => + if Zero = '0' then + next_state <= Count; + elsif Zero = '1' then + next_state <=Usout; + + end if; + when UsOut => + If OvF='0' then + next_state <= count; + elsif OvF='1' then + next_state <= OverFlow; + end if; + When OverFlow => + next_state<=Count; +-- when others => +-- next_state <= Init; + end case; + end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/FIFO_64_FWFT.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/FIFO_64_FWFT.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/FIFO_64_FWFT.vhd (revision 142) @@ -0,0 +1,223 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL/GAMOM +-- +-- Create Date: 19:51:54 04/19/2011 +-- Design Name: +-- Module Name: FIFO_64 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +--FIFO 64 Octets utisé pour les modules d'entrée +-- ce fifo est de type fwft first word falls throught ce qui +-- signifie que l'on a toujours la donnée au sommet de la pile en +-- sortie du fifo. +-- Dependencies: RAM_64.vhd +-- +-- Revision: 08-11-2012 +-- Revision 0.01 - File Created +-- Additional Comments: suppression du signal counter_en dans les expressions +-- 08/11/12 : prise en compte du retard de propagation des infos dans la FIFO. +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FIFO_64_FWFT is + Port ( clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR (Word-1 downto 0); + rd_en : in STD_LOGIC; + srst : in STD_LOGIC; + wr_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR (Word-1 downto 0); + empty : out STD_LOGIC; + full : out STD_LOGIC); +end FIFO_64_FWFT; + +architecture Behavioral of FIFO_64_FWFT is +-- declaration de la ram 64 octets +COMPONENT RAM_64 + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector(5 downto 0); + addrb : IN std_logic_vector(5 downto 0); + dia : IN std_logic_vector(Word-1 downto 0); + --doa : OUT std_logic_vector(Word-1 downto 0); + dob : OUT std_logic_vector(Word-1 downto 0) + ); + END COMPONENT; +type fsm_states is (state0, state1, state2);-- definition du type etat pour le codage des etats des fsm +signal fwft_fsm_state : fsm_states; +type ram_type is array (63 downto 0) of std_logic_vector (Word-1 downto 0); + signal RAM: ram_type; +-- declaration des signeaux des compteurs +signal push_address_counter : std_logic_vector(5 downto 0); +signal pop_address_counter : std_logic_vector(5 downto 0); +signal fifo_counter : std_logic_vector(5 downto 0):=(others=>'0'); +--autre signaux +signal rd_ready : std_logic:='0'; +signal empty_signal : std_logic; +signal full_signal : std_logic; +signal wr_en_signal : std_logic; +signal rd_en_signal : std_logic; +signal clk_signal : std_logic; +signal dob_signal : std_logic_vector(Word-1 downto 0); +signal dout_signal : std_logic_vector(Word-1 downto 0); +signal doa_signal : std_logic_vector(Word-1 downto 0); +signal counter_en : std_logic; + +begin + +-- ram instantiation de la ram 64 octets du FIFO +--fifo_RAM_64: RAM_64 PORT MAP( +-- clka => clk_signal, +-- clkb => clk_signal, +-- wea => wr_en_signal, +-- ena => wr_en_signal, +-- enb => rd_en_signal, +-- addra => push_address_counter, +-- addrb => pop_address_counter, +-- dia => din, +-- --doa => doa_signal, +-- dob => dob_signal +-- ); +-- circuiterie des signaux de validation et d'etat du fifo +wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein +rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide +full_signal <= '1' when fifo_counter = "111111" else + '0'; +empty_signal <= '1' when rd_ready='0' or unsigned(fifo_counter) = 0 else + '0'; +clk_signal <= clk; +full <= full_signal; +empty <= empty_signal; + +-- sortie du fifo fwft +dout <= dout_signal; + +-- le processus des transistion +fwft_fsm_nsl : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + fwft_fsm_state <= state0; + else + case fwft_fsm_state is + when state0 => if wr_en_signal = '1' then --tampon vide seule l'écriture est possible + fwft_fsm_state <= state1; + end if; + + + when state1 => --if rd_en_signal = '1' and wr_en_signal='1' then --écriture seule dans le tampon + + fwft_fsm_state <= state2; + --end if; + + when state2 => if rd_en_signal = '1' and wr_en_signal='1' then + fwft_fsm_state <= state2; + elsif rd_en_signal='1' and wr_en_signal='0' and unsigned(fifo_counter) = 1 then --lecture avec écriture + fwft_fsm_state <= state0; + elsif unsigned(fifo_counter) = 0 then + fwft_fsm_state <= state0; + end if; + + when others => fwft_fsm_state <= state0; + end case; + end if; + end if; + end process; + -- actions associées à la fsm + -- mux qui oriente les sortie doa et dob vers out + val_fwft:process (fwft_fsm_state,dob_signal) + + begin + case fwft_fsm_state is + when state0 => + + dout_signal <= dob_signal; + counter_en <= '0'; + rd_ready <='0'; + when state1 => + + dout_signal <= dob_signal; + counter_en <= '1'; + rd_ready <='0'; + when state2 => + + dout_signal <= dob_signal; + counter_en <= '1'; + rd_ready <='1'; + when others => + dout_signal <= dob_signal; + counter_en <= '0'; + rd_ready <='0'; + end case; +end process; +doa_latch_process : process(clk) +begin + if rising_edge(clk) then + if wr_en_signal ='1' then + doa_signal <= din; + end if; + end if; +end process; + +-- processus de comptage des adresses d'empilement +push_process : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + push_address_counter <= (others =>'0'); + elsif wr_en_signal ='1' then + RAM(conv_integer(push_address_counter)) <=din; + push_address_counter <= push_address_counter +1; + end if; + end if; +end process; + + -- processus de comptage des adresses depilement du fifo +pop_process : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + pop_address_counter <= (others =>'0'); + elsif rd_en_signal ='1' then + pop_address_counter <= pop_address_counter +1; + end if; + end if; + end process; + dob_signal<=RAM(conv_integer(pop_address_counter)); + -- processus de comptage des octets dans le fifo + fifo_counter_process : process(clk) + variable count : std_logic_vector(5 downto 0):= (others=>'0'); +begin + if rising_edge(clk) then + if srst = '1' then + fifo_counter <= (others =>'0'); + count:=(others =>'0'); + else + if wr_en_signal ='1' and rd_en_signal ='0' then + count:=count+1; + end if; + if rd_en_signal ='1' and wr_en_signal ='0' and counter_en='1' then + count:=count-1; + end if; + fifo_counter<=count; + end if; + end if; +end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/FIfo_mem.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/FIfo_mem.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/FIfo_mem.vhd (revision 142) @@ -0,0 +1,91 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04:35:05 10/15/2012 +-- Design Name: +-- Module Name: FIfo_mem - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +entity FIFO is + generic (N: integer := 6; -- number of address bits for 2**N address locations +M: integer := 8); -- number of data bits to/from FIFO + port (CLK, PUSH, POP, INIT: in std_logic; + DIN: in std_logic_vector(N-1 downto 0); +DOUT: out std_logic_vector(N-1 downto 0); + FULL, EMPTY, NOPUSH, NOPOP: out std_logic; + clk: IN std_logic; + + rd_en: IN std_logic; + srst: IN std_logic; + wr_en: IN std_logic; + + empty: OUT std_logic; + full: OUT std_logic); +end entity FIFO; +architecture TOP_HIER of FIFO is +signal WE: std_logic; +signal A: std_logic_vector(N-1 downto 0); +signal PUSH, POP, INIT: std_logic; + +signal NOPUSH, NOPOP: std_logic; + +component FIFO_LOGIC is + generic (N: integer); -- number of address bits + port (CLK, PUSH, POP, INIT: in std_logic; + ADD: out std_logic_vector(N-1 downto 0); + FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic); +end component FIFO_LOGIC; + +COMPONENT RAM_256 + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector(Word-1 downto 0); + addrb : IN std_logic_vector(Word-1 downto 0); + dia : IN std_logic_vector(Word-1 downto 0); + dob : OUT std_logic_vector(Word-1 downto 0) + ); +END COMPONENT; +begin +-- example of component instantiation using positional notation +FL: FIFO_LOGIC generic map (N) + port map (CLK, PUSH, POP, INIT, A, FULL, EMPTY, WE, NOPUSH, NOPOP); +Push<=wr_en; +pop<=rd_en; +nopush<=nopush; +nopop<=nopop; +init<=srst; +-- example of component instantiation using keyword notation +--R: RAM generic map (W => N, K => M) +-- port map (DIN => DIN, ADDR => A, WR => WE, DOUT => DOUT); +R: RAM_256 PORT MAP( + clka => clk, + clkb => clk, + wea => we, + ena => '1', + enb => '1', + addra => A, + addrb => A, + dia => din, + dob => dout + ); +end architecture TOP_HIER; Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/FIfo_proc.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/FIfo_proc.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/FIfo_proc.vhd (revision 142) @@ -0,0 +1,102 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04:35:05 10/15/2012 +-- Design Name: +-- Module Name: FIfo_mem - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +entity FIFO_LOGIC is + generic (N: integer := 3); + port (CLK, PUSH, POP, INIT: in std_logic; + ADD: out std_logic_vector(N-1 downto 0); + FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic); +end entity FIFO_LOGIC; +architecture RTL of FIFO_LOGIC is +signal WPTR, RPTR: std_logic_vector(N-1 downto 0); +signal LASTOP: std_logic; +begin +SYNC: process (CLK) begin + if (CLK'event and CLK = '1') then + if (INIT = '1') then -- initialization -- + WPTR <= (others => '0'); + RPTR <= (others => '0'); + LASTOP <= '0'; + elsif (POP = '1' and EMPTY = '0') then -- pop -- + RPTR <= RPTR + 1; + LASTOP <= '0'; + elsif (PUSH = '1' and FULL = '0') then -- push -- + WPTR <= WPTR + 1; + LASTOP <= '1'; + end if; -- otherwise all Fs hold their value -- + end if; +end process SYNC; +COMB: process (PUSH, POP, WPTR, RPTR, LASTOP, FULL, EMPTY) begin +-- full and empty flags -- + if (RPTR = WPTR) then + if (LASTOP = '1') then + FULL <= '1'; + EMPTY <= '0'; + else + FULL <= '0'; + EMPTY <= '1'; + end if; + else + FULL <= '0'; + EMPTY <= '0'; + end if; +-- address, write enable and nopush/nopop logic -- + if (POP = '0' and PUSH = '0') then -- no operation -- + ADD <= RPTR; + WE <= '0'; + NOPUSH <= '0'; + NOPOP <= '0'; + elsif (POP = '0' and PUSH = '1') then -- push only -- + ADD <= WPTR; + NOPOP <= '0'; + if (FULL = '0') then -- valid write condition -- + WE <= '1'; + NOPUSH <= '0'; + else -- no write condition -- + WE <= '0'; + NOPUSH <= '1'; + end if; + elsif (POP = '1' and PUSH = '0') then -- pop only -- + ADD <= RPTR; + NOPUSH <= '0'; + WE <= '0'; + if (EMPTY = '0') then -- valid read condition -- + NOPOP <= '0'; + else + NOPOP <= '1'; -- no red condition -- + end if; + else -- push and pop at same time - + if (EMPTY = '0') then -- valid pop -- + ADD <= RPTR; + WE <= '0'; + NOPUSH <= '1'; + NOPOP <= '0'; + else + ADD <= wptr; + WE <= '1'; + NOPUSH <= '0'; + NOPOP <= '1'; + end if; + end if; +end process COMB; +end architecture RTL; Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/Fifo2Mem.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/Fifo2Mem.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/Fifo2Mem.vhd (revision 142) @@ -0,0 +1,168 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM Roland Christian +-- +-- Create Date: 19:16:34 05/23/2014 +-- Design Name: +-- Module Name: Fifo2Mem - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: ce module permet de lire une fifo et d'écrire le résultat dans la mémoire Ram +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +Library NocLib; +use NoCLib.CoreTypes.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Fifo2Mem is + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + wr_start : in STD_LOGIC; + fifo_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_data_available : in STD_LOGIC; + datalen : in STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_data_out_en : out STD_LOGIC; + fifo_empty : in STD_LOGIC; + ram_busy : in STD_LOGIC; + ram_addr_start : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_addr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + ram_wr : out STD_LOGIC; + ram_en : out STD_LOGIC; + wr_comp :out STD_LOGIC + + ); +end Fifo2Mem; + +architecture Behavioral of Fifo2Mem is +type typ_wr_mem is(start,write_mem,stop); +signal et_wr_mem , next_et_wr_mem: typ_wr_mem; +signal data_to_ram,Data_to_ram_i : std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal P_len_i,P_len : std_logic_vector(Word-1 downto 0); +signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; +signal n,n_i : natural range 0 to 15:=0; +signal dest_address,dest_address_i,ack_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0'); +begin +wr_mem_sync:process(clk) +begin +if rising_edge(clk) then +if reset='1' then + n<=0; + P_len<=(others=>'0'); + dest_address<=(others=>'0'); + data_to_ram<=(others=>'0'); +else +dest_address<=dest_address_i; +P_len<=P_len_i; +Data_to_ram<=data_to_ram_i; +et_wr_mem<=next_et_wr_mem; +n<=n_i; +end if; +end if; +end process; +wr_mem_next:process(et_wr_mem,Fifo_data_available,P_len,wr_start,datalen,fifo_data_out, +ram_addr_start,ram_busy,dest_address) +variable delai :natural range 0 to 1; +begin + + next_et_wr_mem<=et_wr_mem; + P_len_i<=P_len; + dest_address_i<=dest_address; + case et_wr_mem is + +when start =>if wr_start='1' then + next_et_wr_mem<=write_mem; + P_len_i<=datalen; + dest_address_i<=ram_addr_start; + end if; + +when write_mem=> rd_ok<='0'; + + + if unsigned( P_len)>0 and wr_start='1' then + + if fifo_data_available = '1' and delai=0 then + delai:=1; --une donné lue + P_len_i <= P_len - 1; + next_et_wr_mem<=write_mem; + rd_ok<='1'; + data_to_ram_i<=fifo_data_out; + end if; + if ram_busy='0' and delai=1 then + wr_ok<='1'; + dest_address_i <= dest_address + 1; + delai:=0;--une donnée écrite + + else + dest_address_i<=dest_address; + wr_ok<='0'; + + end if; + + next_et_wr_mem<=stop; + + else + rd_ok<='0'; + Wr_ok<='0'; + + if ram_busy='0' and wr_start='1' then + + next_et_wr_mem<=stop; + end if; + + end if; + when stop =>if wr_Start='0' then --attendre que le signal start soit ramener à 0 + next_et_wr_mem<=start; + end if; + end case; + end process; + +process(et_wr_mem,rd_ok,wr_ok,data_to_ram,ram_addr_start,fifo_data_out) +begin +case et_wr_mem is +when start =>Ram_wr<='0'; + Ram_en<='0'; + Ram_data_in<=data_to_ram; + fifo_data_out_en<='0'; + wr_comp<='0'; + Ram_addr<=Ram_addr_start; +when write_mem=> + fifo_data_out_en <=rd_ok; + if rd_ok = '1' then + + Ram_data_in<=fifo_data_out; + else + Ram_data_in<=data_to_ram; + end if; + ram_addr<=dest_address; + Ram_wr<=wr_ok; + Ram_en<=wr_ok; + wr_comp<='0'; +when stop => + Ram_wr<='0'; + Ram_en<='0'; + ram_addr<=dest_address; + Ram_data_in<=data_to_ram; + fifo_data_out_en<='0'; + wr_comp<='1'; + + end case; +end process; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPICORETEST.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPICORETEST.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPICORETEST.vhd (revision 142) @@ -0,0 +1,702 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 01:27:32 04/20/2012 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/MPICORETEST.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: MPI_NOC +-- +-- Dependencies: +-- +-- Revision: 11 Juillet 2012 +-- Revision 0.01 - File Created +-- Additional Comments:Permet de tester le composant MPI +-- en simulant deux PE qui s'échangent des données. +-- Notes: +-- +-- +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +library NocLib ; +--use IEEE.STD_LOGIC_ARITH.ALL; +--use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +use work.MPI_RMA.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +USE ieee.numeric_std.ALL; + +ENTITY MPICORETEST IS +--port (clkm : in std_logic; +--reset : in std_logic; +--result : out std_logic_vector(Word-1 downto 0)); +END MPICORETEST; + +ARCHITECTURE behavior OF MPICORETEST IS +--constant WORD :positive:=8; +constant MEMSIZE:positive:=65535; + -- Components declaration + COMPONENT RAM_v + generic (width : positive;size :positive); + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector; + addrb : IN std_logic_vector; + dia : IN std_logic_vector; + dob : OUT std_logic_vector + ); + END COMPONENT; + + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT MPI_NOC + generic (NPROC : positive:=2); + PORT( + MPI_Node_in : IN Ar_MPIPort_in(1 to 2); + MPI_Node_Out : OUT Ar_MPIPort_out(1 to 2) + ); + END COMPONENT; + + constant clk_period : time := 10 ns; + +--===================signaux pour l'horloge ============================== +signal reset,clkm : std_logic := '0'; +--======================================================================== + --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0'; + signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic; + signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal PE_Instr_en : std_logic:='0'; + signal sram : typ_dpram; + signal pe_hold_ack,pe_hold_req : std_logic; + --signal pe_putadr:std_logic_vector(MEMSIZE-1 downto 0);-- adresse du bloc pour Put + --signal pe_getadr:std_logic_vector(MEMSIZE-1 downto 0);-- adresse du bloc pour get + signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée + signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO + signal Lib_Init : std_logic; -- l'initialisation est terminée + + --données du programme PE + signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0); + signal dpid,dpid_i : natural range 0 to 15:=1; + --Inputs + signal MPI_Node_in : Ar_MPIPort_in(1 to 2) ; +-- Port details +-- instruction : STD_LOGIC_VECTOR (Word -1 downto 0); +-- instruction_en : STD_LOGIC; +-- packet_ack : std_logic; +-- ram_data_in : STD_LOGIC_VECTOR (Word-1 downto 0); +-- clk : STD_LOGIC; +-- reset : STD_LOGIC; + --Outputs + signal MPI_Node_Out : Ar_MPIPort_out(1 to 2); +-- détails des champs de Typ_MPIPORT_Out +-- +-- +-- ram_we : STD_LOGIC; +-- ram_en : STD_LOGIC; +-- packet_received : STD_LOGIC; +-- barrier_completed : STD_LOGIC; +-- instruction_fifo_full : STD_LOGIC; +-- PushOut : STD_LOGIC_VECTOR (WORD-1 downto 0); +-- ram_data_out : STD_LOGIC_VECTOR (WORD-1 downto 0); +-- ram_address : STD_LOGIC_VECTOR (ADRLEN-1 downto 0); +-- +--end record; + -- + -- a + + + --signaux pour la gestion de la MAE + type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, + putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); +signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées +signal count,count_i : natural range 0 to 15:=0; + +--signal adresse,adresse_rd :natural range 0 to 65536; + + signal etPutGet : typ_mae; + signal Ram_busy :std_logic:='0'; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: MPI_NOC GENERIC MAP (NPROC=>2) + PORT MAP ( + MPI_Node_in => MPI_Node_in, + MPI_Node_Out => MPI_Node_Out + ); +Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN) + PORT MAP( + clka =>clkm, + clkb => clkm, + wea => ram_we, + ena => ram_ena, + enb => ram_enb, + addra => ram_addra, + addrb =>ram_addrb, + dia => ram_din, + dob => ram_do + ); + + --MUX de la RAM + + ram_addrb <= MPI_Node_out(1).ram_address_rd WHEN ramsel ='1' ELSE + pe_ram_addrb; + ram_addra <= MPI_Node_out(1).ram_address_wr WHEN ramsel ='1' ELSE + pe_ram_addra; + + +ram_ena <= MPI_Node_out(1).ram_en WHEN ramsel ='1' ELSE + pe_ram_ena; +ram_enb <= MPI_Node_out(1).ram_en WHEN ramsel ='1' ELSE + pe_ram_enb; +ram_ena <= MPI_Node_out(1).ram_en WHEN ramsel ='1' ELSE + pe_ram_ena; + +ram_we<= MPI_Node_out(1).ram_we WHEN ramsel ='1' ELSE + pe_ram_we; + +ram_din <= MPI_Node_out(1).ram_data_in WHEN ramsel ='1' ELSE + pe_ram_din; + + +MPI_Node_in(1).ram_data_out<=ram_do when ramsel='1' else (others=>'Z'); +pe_ram_do<=ram_do when ramsel='0' else (others=>'Z'); + + +pe_hold_req<=MPI_Node_out(1).hold_req; +MPI_Node_in(1).hold_ack<=pe_hold_ack; +MPI_Node_in(1).reset<=reset; +MPI_Node_in(1).clk<=clkm; +MPI_Node_in(1).instruction_en<=PE_instr_en; +MPI_Node_in(1).instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8)); + +Lib_Instr_ack<=MPI_Node_out(1).Pushout(0); --l'instruction a été copié +Lib_init<=MPI_Node_out(1).Pushout(4); -- Initialized +--============================================================= + -- Clock process definitions +--============================================================= + clk_process :process + begin + clkm <= '0' ; + wait for 10 ns;--clk_period/2; + clkm <= '1' ; + wait for 10 ns;--clk_period/2; + end process; + stim_proc: process + begin + -- hold reset state for 100 ns. + reset<='0'; + wait for 1 ns; + reset<='1'; + wait for clk_period*10; + reset<='0'; + wait; + + + end process; +--================================================================ +dpid<=dpid_i; + pPutGet:process(clkm) + + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout,dlen,ct : natural range 0 to 255; + variable adrToset : std_logic_vector(ADRLEN-1 downto 0); + variable iack : std_logic:='0'; + variable adresse,adresse_rd :natural range 0 to 65536; + + begin + + if (clkm'event and clkm='1') then + if reset='1' then + etputget<=start; + + + dcount<=0; + + else + + case etputget is + when start => + if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide + etputget<=Fillmem; + end if; + Ram_busy<='0'; + PE_Instr_En<='0'; + iack:='0'; + adresse:=256; + adresse_rd:=0; + timeout:=0; + dcount<=0; + when Fillmem => + if mpi_node_out(1).hold_req='0' then + + + + PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f"; + PE_Instr_En<='0'; + dcount<=dcount+1; + + if dcount=50 then + bfill:=bfill+1; + + if bfill=4 then + etputget<=InitApp; + else + etputget<=nextfill; + end if; + else + adresse:=adresse+1; + etputget<=Fillmem; + end if; + else -- attente de la libéraion de la mémoire + timeout:=timeout+1; + if timeout=100 then + etputget<=st_timeout; + end if; + + end if; + when nextfill => --prépare le prochain bloc mémoire qui sera rempli + adresse:=100*bfill; + dcount<=0; + etputget<=Fillmem; + PE_Instr_En<='0'; + when InitApp => + --code pour Init ici + --mettre mpi_init à l'adresse mpi + + PE_Ram_din<=MPI_INIT & x"0" ; + adresse:=core_init_adr; + + PE_Instr_En<='0'; + fsrc:=1; + adrToSet:=std_logic_vector(to_unsigned(core_init_adr,ADRLEN)); + if ret/=fsrc then + dcount<=0; + etputget<=writeptr; + adresse:=core_base_adr+2; + PE_Instr_En<='0'; + else + if Lib_instr_ack='1' then -- attente de la prise en compte de l'instruction + etputget<=InitCompleted; + PE_instr_en<='0'; + + else + PE_Instr_en<='1'; + end if; + + end if; + + when writeptr => + PE_Instr_En<='0'; + if PE_Hold_req = '0' then --s'assurer que le bus est disponible + + if dcount=0 then + PE_RAM_Din<=AdrToSet(Word-1 downto 0); + dcount <=dcount+1; + --adresse:=adresse+1; --prépare la prochaine écriture + elsif dcount=1 then + dcount <=dcount+1; + adresse:=adresse+1; --prépare la prochaine écriture + PE_RAM_Din<=AdrToSet(15 downto 8); + elsif dcount=2 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + ret:=fsrc; + dcount<=0; + timeout:=0; + + if fsrc=1 then + etputget <= InitApp; + elsif fsrc=2 then + etputget <= putdata; + elsif fsrc=3 then + etputget <= getdata; + else + etputget <= start; + end if; + + end if; + + end if; + When InstrCopy => + if Lib_instr_ack='1' then + etputget<=Writeptr; + PE_instr_en<='0'; + iack:='1'; + + else + PE_Instr_en<='1'; + end if; + + when InitCompleted => + + if Lib_Init='1' then + etputget<=putdata; + PE_Instr_En<='0'; + else + PE_Instr_En<='0'; + end if; + when putdata => --construire le packet pour le Put + DestRank:=1; + adresse_rd:=core_base_adr+Core_Rank2port_base+DestRank; + + PE_Instr_En<='0'; + timeout:=0; + dcount<=0; + fsrc:=2; + adrToSet:=std_logic_vector(to_unsigned(core_put_adr,ADRLEN)); + if ret/=fsrc then + adresse:=core_base_adr+2; + etputget<=writeptr; + ret:=0; + else + if Lib_instr_ack/='1' then + etputget<= putdata2; + end if; + end if; + + when putdata2 => + + if ramsel = '0' then --si le PE a accès à la RAM + dlen:=to_integer(unsigned(datalen)); + pMPI_put(clkm,destrank,SrcAdr1 & Srcadr0,DestAdr1 & DestAdr0,Dlen,sram,ct); + adresse:=to_integer(unsigned(sram.addr_wr)); + PE_ram_din<=sram.data_in; + dcount<=ct; + if dcount<=6 then +-- +-- PE_Instr_En<='0'; +-- if dcount=0 then +-- adresse:=core_put_adr; +-- PE_Ram_din<=MPI_PUT & std_logic_vector(to_unsigned(Dpid,4)); +-- elsif dcount=1 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=Datalen ; +-- elsif dcount=2 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=SrcAdr1 ; +-- elsif dcount=3 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=SrcAdr0 ; +-- elsif dcount=4 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=DestAdr1 ; +-- elsif dcount=5 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=DestAdr0 ; + elsif dcount=7 then --juste après la valeur 6 en fait +-- adresse:=core_base_adr+1; +-- adresse_rd:=core_base_adr; +-- PE_Ram_din<=x"01"; --instruction pulse enable; + PE_Instr_En<='1'; +-- + end if; +-- dcount<=dcount+1; +-- end if; + elsif PE_instr_En='0' then + timeout:=timeout+1; + if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire + ram_busy<='1'; + timeout:=0; + PE_Instr_En<='0'; + end if; + end if; + if dcount >=6 then + Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI + if Lib_instr_ack='1' then -- Instruction ack + PE_Instr_En<='0'; + if Ramsel='0' then + adresse:=core_base_adr+1; + PE_Ram_din<=x"00"; --ramener le IPulse à 0; + Ram_busy<='0'; + etPutGet<=putcompleted; + else + + Ram_busy<='1'; --force la prise du bus + end if; + else + + timeout:=timeout+1; + if timeout=150 then + etputget<=st_timeout; + end if; + end if; + end if; + + + when putcompleted => + adresse_rd:=core_put_adr+6; + if PE_Ram_do(0)='1' then --Put completed + etPutGet<=GetData; + end if; + PE_Instr_En<='0'; + when getdata => --positionnement du mot de longueur des données + + DestRank:=1; + timeout:=0; + dcount<=0; + fsrc:=3; + adrToSet:=std_logic_vector(to_unsigned(core_get_adr,ADRLEN)); + if ret/=fsrc then + adresse:=core_base_adr+2; + etputget<=writeptr; + ret:=0; + else + adresse:=core_get_adr; + etputget<= getdata2; + end if; + PE_Instr_En<='0'; + when getdata2 => + + if ramsel='0' then + + pMPI_get(clkm,destrank,SrcAdr1 & Srcadr0,DestAdr1 & DestAdr0,Dlen,sram,ct); + adresse:=to_integer(unsigned(sram.addr_wr)); + PE_ram_din<=sram.data_in; + dcount<=ct; + if dcount<=6 then + +-- if dcount<=0 then +-- adresse:=core_get_adr; +-- PE_Ram_din<=MPI_GET & std_logic_vector(to_unsigned(Dpid,4)); +-- elsif dcount=1 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=Datalen ; +-- elsif dcount=2 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=SrcAdr1 ; +-- elsif dcount=3 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=SrcAdr0 ; +-- elsif dcount=4 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=DestAdr1 ; +-- elsif dcount=5 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=DestAdr0 ; + + elsif dcount=7 then +-- adresse:=core_base_adr+1; + adresse_rd:=core_base_adr; + PE_Instr_En<='1'; +-- PE_Ram_din<=x"01"; --instruction pulse enable; + timeout:=0; + end if; +-- dcount<=dcount+1; +-- end if; + elsif PE_Instr_En='0'then + timeout:=timeout+1; + if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire + ram_busy<='1'; + timeout:=0; + PE_Instr_En<='0'; + end if; + end if; + + if dcount >=6 then + Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI + if Lib_instr_ack='1' then -- Instruction ack + PE_Instr_En<='0'; + if Ramsel='0' then + adresse:=core_base_adr+1; + PE_Ram_din<=x"00"; --ramener le IPulse à 0; + Ram_busy<='0'; + etPutGet<=getcompleted; + else + + Ram_busy<='1'; --force la prise du bus + end if; + else + + timeout:=timeout+1; + if timeout=150 then + etputget<=st_timeout; + end if; + end if; + + + end if; + + + + when getcompleted => + adresse_rd:=core_get_adr+6; + PE_Instr_En<='0'; + if PE_Ram_do(0)='1' then --Put completed + if Ramsel='0' then + adresse:=core_base_adr+1; + PE_Ram_din<=x"00"; --ramener le IPulse à 0; + etPutGet<=Terminate; + else + timeout:=timeout+1; + end if; + end if; + + + when terminate => + + + etputget<=start; + + when st_timeout => + + --if ram_busy='1' then + etputget<=start; + --end if + + etputget<=start; + end case; + pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,ADRLEN)); + pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,ADRLEN)); + end if; --reset='1' + end if; + end process pPutGet; + +majPutGet:process (etputget) + + begin + case etputget is + when start => + + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + when fillmem => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + when nextfill => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + when InitApp => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + when Initcompleted => + --PE_Instr_En<='1'; + when writeptr => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + -- dcount<=dcount+1; + + --PE_Instr_En<='0'; + when InstrCopy => --instruction copy + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + + + when putdata => --positionnement du mot de longueur des données + --dcount<=0; + srcadr0<=X"00"; + srcadr1<=X"01"; + destadr0<=X"00"; + destadr1<=X"02"; + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + --lecture du n° de port de destination + PE_Ram_enb<='1'; + datalen<=std_logic_vector(to_unsigned(50,8)); + dpid_i<=to_integer(unsigned(PE_ram_do(3 downto 0))); --le port est situé ur les 4 bits de poids faible + --PE_Instr_En<='0'; + when putdata2 => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + -- dcount<=dcount+1; + if dcount>=5 then + --PE_Instr_En<='1'; + else + --PE_Instr_En<='0'; + end if; + when putcompleted => + PE_Ram_we <='1'; + PE_Ram_ena <='1'; + -- lecture du résultat + PE_Ram_enb <='1'; + --PE_Instr_En<='1'; + when getdata => + --dcount<=0; + srcadr0<=X"00"; + srcadr1<=X"02"; + destadr0<=X"00"; + destadr1<=X"03"; + datalen<=std_logic_vector(to_unsigned(50,8)); + --PE_Instr_En<='0'; + when getdata2 => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + --dcount<=dcount+1; + if dcount=5 then + --PE_Instr_En<='1'; + else + --PE_Instr_En<='0'; + end if; + when getcompleted => + PE_Ram_we <='1'; + PE_Ram_ena <='1'; + -- lecture du résultat + PE_Ram_enb <='1'; + --PE_Instr_En<='1'; + when terminate => + + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + when st_timeout => + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + end case; + +end process majPutGet ; + + hold:process (pe_hold_req,clkm,reset) + begin + if rising_edge(clkm) then + if reset='1' then + pe_hold_ack<='0'; + else + if pe_hold_req='1' then + ramsel<=not(ram_busy); + pe_hold_ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération + else + pe_hold_ack<='0'; + ramsel<='0'; + end if; + end if; + end if; + end process hold; +END; Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_CORE_SCHEDULER.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_CORE_SCHEDULER.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_CORE_SCHEDULER.vhd (revision 142) @@ -0,0 +1,135 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:16:03 06/13/2011 +-- Design Name: +-- Module Name: MPI_CORE_SCHEDULER - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity MPI_CORE_SCHEDULER is + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC; + instruction_fifo_empty : in STD_LOGIC; + instruction_fifo_data : in STD_LOGIC_VECTOR (7 downto 0); + instruction_available : out STD_LOGIC; + + get_request_fifo_data : in STD_LOGIC_VECTOR (7 downto 0); + get_request_fifo_empty : in STD_LOGIC; + instruction_fifo_rd_en : out STD_LOGIC; + get_request_fifo_rd_en : out STD_LOGIC; + + fifo_selected : out STD_LOGIC; + fifo_empty : out STD_LOGIC; + fifo_rd_en : in STD_LOGIC; + data_out : out STD_LOGIC_VECTOR (7 downto 0) + ); +end MPI_CORE_SCHEDULER; + +architecture Behavioral of MPI_CORE_SCHEDULER is + +signal sel_signal : std_logic; +-- declaration des composants du scheduler +COMPONENT CDEMUX1 + PORT( + di : IN std_logic; + sel : IN std_logic; + do1 : OUT std_logic; + do2 : OUT std_logic + ); + END COMPONENT; + +COMPONENT CMUXP1 + PORT( + di1 : IN std_logic; + di2 : IN std_logic; + sel : IN std_logic; + do : OUT std_logic + ); + END COMPONENT; + +COMPONENT CMUX8 + PORT( + di1 : IN std_logic_vector(7 downto 0); + di2 : IN std_logic_vector(7 downto 0); + sel : IN std_logic; + do : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + +COMPONENT round_robbin_machine + PORT( + get_request_fifo_empty : IN std_logic; + instruction_fifo_empty : IN std_logic; + priority_rotation : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + fifo_selected : OUT std_logic; + instruction_available : OUT std_logic; + mux_sel : OUT std_logic + ); +END COMPONENT; +begin +-- instances des composants + + +mpi_core_rr_machine: round_robbin_machine PORT MAP( + get_request_fifo_empty => get_request_fifo_empty, + instruction_fifo_empty => instruction_fifo_empty, + priority_rotation => priority_rotation , + clk => clk, + fifo_selected => fifo_selected, + instruction_available => instruction_available , + reset => reset, + mux_sel => sel_signal + ); + + +Fifo_empty_MUX: CMUXP1 PORT MAP( + di1 => instruction_fifo_empty , + di2 => get_request_fifo_empty, + do => fifo_empty, + sel => sel_signal + ); + + + +rd_en_demux: CDEMUX1 PORT MAP( + di => fifo_rd_en , + sel => sel_signal, + do1 => instruction_fifo_rd_en, + do2 => get_request_fifo_rd_en + ); + +data_MUX8: CMUX8 PORT MAP( + di1 => instruction_fifo_data , + di2 => get_request_fifo_data, + sel => sel_signal, + do => data_out + ); + + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_NOC.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_NOC.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_NOC.vhd (revision 142) @@ -0,0 +1,172 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:05:07 11/19/2011 +-- Design Name: +-- Module Name: MPI_NOC - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library NocLib ; + +use NocLib.CoreTypes.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity MPI_NOC is +generic (NPROC : positive:=4); + port( + + MPI_Node_in : in Ar_MPIPort_in(1 to NPROC); + MPI_Node_Out : out Ar_MPIPort_out(1 to NPROC) + ); +end MPI_NOC; + +architecture structural of MPI_NOC is +-- Declare signals for interconnections + +--constant NPROC : positive :=8 ; + --Inputs + signal noc_portOut :typ_portio(1 to NPROC); + signal noc_portIn :typ_portio(1 to NPROC); + + signal noc_fifo_in_full : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_data_available : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_fifo_in_empty : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_data_in_en : std_logic_vector(NPROC downto 1) := (others => '0'); + signal noc_cmd_in_en : std_logic_vector(NPROC downto 1) := (others => '0'); + signal noc_data_out_en : std_logic_vector(NPROC downto 1) := (others => '0'); + -- signal noc_clk : std_logic := '0'; + --signal noc_reset : std_logic := '0'; + +-- Declare components +COMPONENT SWITCH_GEN + GENERIC (number_of_ports : positive := NPROC); + PORT( + Port_in : IN typ_PortIO(1 to number_of_ports); + Port_out : OUT typ_PortIO(1 to number_of_ports); + data_in_en : IN std_logic_vector(NPROC downto 1); + cmd_in_en : IN std_logic_vector(NPROC downto 1); + data_out_en : IN std_logic_vector(NPROC downto 1); + fifo_in_full : OUT std_logic_vector(NPROC downto 1); + fifo_in_empty : OUT std_logic_vector(NPROC downto 1); + data_available : OUT std_logic_vector(NPROC downto 1); + clk : IN std_logic; + reset : IN std_logic + ); + END COMPONENT; + COMPONENT CORE_MPI is + Port ( instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + instruction_en : in STD_LOGIC; + + barrier_completed : out STD_LOGIC; + packet_received : out STD_LOGIC; + packet_ack : in std_logic; + PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); + ram_we : out STD_LOGIC; + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_address_wr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_in_wr_en : out STD_LOGIC; -- OK (au switch) pour lire les données + switch_port_in_empty : in STD_LOGIC; + switch_port_in_cmd_en : out STD_LOGIC; + switch_port_in_full : in STD_LOGIC; -- port d'entréendu switch saturé + switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); -- port de donées d'entrée + switch_port_out_rd_en : out STD_LOGIC; -- OK (au switch) pour écrire les données + switch_port_out_data_vailaible : in STD_LOGIC; -- Donnée disponible à la sortie (du switch) + clk : in STD_LOGIC; + clkout : out std_logic; + reset : in STD_LOGIC; + ram_en : out STD_LOGIC; + instruction_fifo_full : out STD_LOGIC; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0)); + end COMPONENT; +-- cette fonction met en place l'architecture d'exécution de l'environnement +-- elle permet de construire le Noc et de connecter les différents core MPI +-- chaque core reçoit un ID qui sera son Rank lors de l'appel à MPI_GET_Rank +-- faut il créer une petite mémoire chargée de stocker les IDs ? +-- Oui car cette mémoire sera consultée par la fonction MPI_Init pour associer +-- un communicateur au MPI Core + + + + begin +Socsyst: if nproc > 1 generate --nproc + -- instancier le switch et connecter les différents ports + +sw_gen1: SWITCH_GEN generic map (NPROC) + PORT MAP ( + Port_in => Noc_PortIn, + + Port_out => noc_Portout, + + --signaux de contrôle de la lecture des ports + data_in_en => noc_data_in_en, + cmd_in_en => noc_cmd_in_en, + data_out_en => noc_data_out_en, + fifo_in_full => noc_fifo_in_full, + fifo_in_empty => noc_fifo_in_empty, + data_available => noc_data_available, + clk => MPI_Node_in(1).clk, + reset => MPI_Node_in(1).reset + ); + end generate; +HCL_c: for i in 1 to nproc generate -- nproc + hardmpi:core_mpi port map ( + + + PushOut=>MPI_Node_out(i).PushOut, + ram_we=> MPI_Node_out(i).ram_we, + ram_en=>MPI_Node_out(i).ram_en , + hold_req=>MPI_NODE_out(i).hold_req, + packet_received=>MPI_Node_out(i).packet_received , + packet_ack=>MPI_Node_in(i).packet_ack, + hold_ack=>MPI_NODE_in(i).hold_ack, + ram_address_rd => MPI_Node_out(i).ram_address_rd , + ram_address_wr => MPI_Node_out(i).ram_address_wr , + ram_data_in=>MPI_Node_out(i).ram_data_in , + ram_data_out=>MPI_Node_in(i).ram_data_out, + barrier_completed =>MPI_Node_out(i).barrier_completed, + instruction => MPI_Node_in(i).instruction, + instruction_en => MPI_Node_in(i).instruction_en, + instruction_fifo_full =>MPI_Node_Out(i).instruction_fifo_full, + switch_port_in_wr_en => noc_data_in_en(i), + switch_port_in_cmd_en=>noc_cmd_in_en(i), + switch_port_in_full => noc_fifo_in_full(i), + switch_port_in_empty => noc_fifo_in_empty(i), + switch_port_in_data => noc_PortIn(i), + switch_port_out_rd_en => noc_data_out_en(i), + switch_port_out_data_vailaible => noc_data_available(i), + switch_port_out_data => noc_PortOut(i), + clk =>MPI_Node_in(1).clk, + reset =>MPI_Node_in(1).reset + + ); + end generate; + + + + +end Structural; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_PKG.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_PKG.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_PKG.vhd (revision 142) @@ -0,0 +1,127 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +Library NocLib; +use NocLib.CoreTypes.all; +package mpi_pkg is +-- Declare constants + +-- constant : time := ns; + constant NPROC : positive:= 8; + +-- type declaration +type portio is array(1 to NPROC) of std_logic_vector (Word-1 downto 0); +-- type is +-- record +-- : std_logic_vector( Word-1 downto 0); +-- : std_logic; +-- end record; + + +-- Declare signals for interconnections + + + --Inputs + signal noc_portOut :portio; + signal noc_portIn :portio; + + signal noc_fifo_in_full : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_data_available : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_fifo_in_empty : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_data_in_en : std_logic_vector(NPROC downto 1) := (others => '0'); + signal noc_data_out_en : std_logic_vector(NPROC downto 1) := (others => '0'); + signal noc_clk : std_logic := '0'; + signal noc_reset : std_logic := '0'; + +-- Declare components +COMPONENT SWITCH_GENERIQUE + GENERIC (number_of_ports : positive := 8); + PORT( + Port1_in : IN std_logic_vector(Word-1 downto 0); + Port2_in : IN std_logic_vector(Word-1 downto 0); + Port3_in : IN std_logic_vector(Word-1 downto 0); + Port4_in : IN std_logic_vector(Word-1 downto 0); + Port5_in : IN std_logic_vector(Word-1 downto 0); + Port6_in : IN std_logic_vector(Word-1 downto 0); + Port7_in : IN std_logic_vector(Word-1 downto 0); + Port8_in : IN std_logic_vector(Word-1 downto 0); + Port9_in : IN std_logic_vector(Word-1 downto 0); + Port10_in : IN std_logic_vector(Word-1 downto 0); + Port11_in : IN std_logic_vector(Word-1 downto 0); + Port12_in : IN std_logic_vector(Word-1 downto 0); + Port13_in : IN std_logic_vector(Word-1 downto 0); + Port14_in : IN std_logic_vector(Word-1 downto 0); + Port15_in : IN std_logic_vector(Word-1 downto 0); + Port16_in : IN std_logic_vector(Word-1 downto 0); + Port1_out : OUT std_logic_vector(Word-1 downto 0); + Port2_out : OUT std_logic_vector(Word-1 downto 0); + Port3_out : OUT std_logic_vector(Word-1 downto 0); + Port4_out : OUT std_logic_vector(Word-1 downto 0); + Port5_out : OUT std_logic_vector(Word-1 downto 0); + Port6_out : OUT std_logic_vector(Word-1 downto 0); + Port7_out : OUT std_logic_vector(Word-1 downto 0); + Port8_out : OUT std_logic_vector(Word-1 downto 0); + Port9_out : OUT std_logic_vector(Word-1 downto 0); + Port10_out : OUT std_logic_vector(Word-1 downto 0); + Port11_out : OUT std_logic_vector(Word-1 downto 0); + Port12_out : OUT std_logic_vector(Word-1 downto 0); + Port13_out : OUT std_logic_vector(Word-1 downto 0); + Port14_out : OUT std_logic_vector(Word-1 downto 0); + Port15_out : OUT std_logic_vector(Word-1 downto 0); + Port16_out : OUT std_logic_vector(Word-1 downto 0); + data_in_en : IN std_logic_vector(8 downto 1); + data_out_en : IN std_logic_vector(8 downto 1); + fifo_in_full : OUT std_logic_vector(8 downto 1); + fifo_in_empty : OUT std_logic_vector(8 downto 1); + data_available : OUT std_logic_vector(8 downto 1); + clk : IN std_logic; + reset : IN std_logic + ); + END COMPONENT; + COMPONENT CORE_MPI is + Port ( instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + instruction_en : in STD_LOGIC; + ram_data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + barrier_completed : out STD_LOGIC; + packet_received : out STD_LOGIC; + packet_ack : in std_logic; + PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); + ram_we : out STD_LOGIC; + ram_address : out STD_LOGIC_VECTOR (15 downto 0); + ram_data_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_in_wr_en : out STD_LOGIC; -- OK (au switch) pour lire les données + switch_port_in_full : in STD_LOGIC; -- port d'entréendu switch saturé + switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); -- port de donées d'entrée + switch_port_out_rd_en : out STD_LOGIC; -- OK (au switch) pour écrire les données + switch_port_out_data_vailaible : in STD_LOGIC; -- Donnée disponible à la sortie (du switch) + clk : in STD_LOGIC; + reset : in STD_LOGIC; + ram_en : out STD_LOGIC; + instruction_fifo_full : out STD_LOGIC; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0)); + end COMPONENT; +-- declare functions and procedure + +end MPI_PKG; + + +package body MPI_PKG is + +-- Example 1 + + + +-- cette fonction met en place l'architecture d'exécution de l'environnement +-- elle permet de construire le Noc et de connecter les différents core MPI +-- chaque core reçoit un ID qui sera son Rank lors de l'appel à MPI_GET_Rank +-- faut il créer une petite mémoire chargée de stocker les IDs ? +-- Oui car cette mémoire sera consultée par la fonction MPI_Init pour associer +-- un communicateur au MPI Core + + +end MPI_PKG; Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_RMA.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_RMA.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_RMA.vhd (revision 142) @@ -0,0 +1,1835 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +use work.PACKET_TYPE.all; + +package Mpi_Rma is +procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural;signal SysRam :out typ_dpram); +procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram); +procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural); + +procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural); +procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector ); + +procedure pMPI_Win_create(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; + info:natural; comm:Mpi_Comm; Win: inout MPI_Win ); +procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win); +procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win); +procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win); +procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win); +procedure pMPI_Comm_Spawn(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; +command : natural; argv :natural; maxprocs : natural; info : natural; root : natural; comm : natural; +signal intercomm :out natural; signal array_of_errcodes : out natural); +-- declare functions and procedure +procedure MPI_Alloc_mem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; +SIZE : natural; MPI_INFO: natural; baseptr: out std_logic_vector(ADRLEN-1 downto 0)); + procedure ReadMem( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; data: out std_logic_vector); +procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; Data:in std_logic_vector); + +procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + variable AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic); + +end MPI_Rma; + + +package body MPI_Rma is +----int MPI_Put( +-- void *origin_addr, +-- int origin_count, +-- MPI_Datatype origin_datatype, +-- int target_rank, +-- MPI_Aint target_disp, +-- int target_count, +-- MPI_Datatype target_datatype, +-- MPI_Win win +--); +-- Example 1 +procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural) is +variable i,dcount,wr_state : natural:=0; +variable adresse :natural; +variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr; +variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp; +variable put_adr : std_logic_vector (ADRLEN-1 downto 0); +variable config_reg: std_logic_vector (Word-1 downto 0); +constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0'); + begin + put_adr:=conv_Std_logic_vector(Core_put_adr,ADRLEN); + + addr1:=Orig_Addr; + addr2:=Target_Disp; + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + end if; +-- + +-- if rising_edge(clkin) then + if dcount= 0 then + dcount:=dcount+1; + Interf.S.Intstate1<=0; + Interf.O.Instruction<=x"00"; + elsif dcount>=1 and dcount <=3 then + if interf.I.ramsel='0' then + Interf.O.membusy<='0'; + --SysRam.O.we<='1'; + --SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + wr_state:=interf.S.Intstate1; + WritePtr (put_adr,wr_state,SysRam); + interf.S.Intstate1<=wr_state; + if wr_state =0 then + -- fin de l'écriture du pointeur en mémoire + dcount:=4; + end if; + end if; + + elsif dcount=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + if target_rank <=15 then --limitation de cete version à 16 rang + Interf.S.Gstart(Target_rank)<='1'; + end if; + adresse:=core_put_adr; + SysRam.O.Data_in<=MPI_PUT & conv_std_logic_vector(Target_Rank,4); --code fonction + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=5 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+1; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + Interf.O.Instruction<=x"06"; -- nombre de mots de l'instruction + end if; + elsif dcount=6 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+2; + SysRam.O.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=7 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+3; + SysRam.O.Data_in<=Addr1(Word-1 downto 0); --source Bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=8 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+4; + SysRam.O.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=9 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+5; + SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=10 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+6; + SysRam.O.Data_in<=(others=>'0'); -- valeur d'acquittement + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=11 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + if interf.I.ramsel='0' then + adresse:=core_base_adr+1; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire; + Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction + Interf.O.membusy<='0'; + dcount:=dcount+1; + end if; + elsif dcount=12 then + if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ? + Interf.O.Instr_En<='0'; --désactiver la prise en compte de l'instruction + dcount:=dcount+1; + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + else + Interf.O.Instr_En<='1'; + end if; + adresse:=core_base_adr+1; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + --SysRam.O.Ram_busy<='0'; --?? + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer la lecture du résultat du Put + SysRam.O.enb<='1'; + elsif dcount=13 then + adresse:=core_base_adr+1; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du Put + SysRam.O.enb<='1'; + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=14 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du Put + SysRam.O.enb<='0'; + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + adresse:=core_base_adr+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=15 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_put_adr+6,Adrlen)); + if SysRam.I.Data_out(0)='1' then --fin du MPI PUT ici pour l'envoie ! + dcount:=dcount+1; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + Interf.S.Intstate2<=255; --timer pour la réception + interf.s.tmem(0)<=x"02"; + report "MPV pMPI_PUT():Ex1 de HCL a répondu concernant l'envoi"; + end if; + end if; + elsif dcount=16 or dcount=17 or dcount=18 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + -- ce cycle permet d'attendre la donnée en sortie après le changement d'adresse + + if interf.I.ramsel='0' then + dcount:=dcount+1; -- ce cycle permet d'attendre la donnée en sortie après le changement d'adresse + + elsif Interf.S.Intstate2>0 then + dcount:=16; + Interf.S.Intstate2<=Interf.S.Intstate2-1; + elsif interf.s.tmem(0)>0 then + interf.s.tmem(0)<=interf.s.tmem(0)-1; + Interf.S.Intstate2<=255; + dcount:=16; + else + dcount:=1;--recommencer l'envoi + end if; + elsif dcount=19 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + if SysRam.I.Data_out(5)='1' then --Message du MPI PUT bien reçu ! + dcount:=dcount+1; + report "MPV pMPI_PUT():Ex2 de HCL a reçu un acquittement concernant l'envoi"; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + elsif Interf.S.Intstate2>0 then + Interf.S.Intstate2<=Interf.S.Intstate2-1; + elsif interf.s.tmem(0)>0 then + interf.s.tmem(0)<=interf.s.tmem(0)-1; + Interf.S.Intstate2<=255; + else + dcount:=1;--recommencer l'envoi + report "MPV pMPI_PUT():Timeout EX2 n'a pas reçu d'acquitement concernant l'envoi. reémission en cours..."; + end if; + else + dcount:=16; + end if; + elsif dcount=20 then + dcount:=0; --fin normale de la fonction + Interf.O.membusy<='0'; + report "MPV pMPI_PUT():fin normale de la fonction"; + end if; + + + NExtCtx:=dcount; + -- end if; + end procedure; + +procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural) is +variable i,wcount,dcount : natural range 0 to 255:=0; +variable adresse :natural; +variable wdata: std_logic_vector(Word-1 downto 0):=(others=>'0'); +variable bitval : std_logic:='0'; +variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr; +variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp; +variable get_adr : std_logic_vector (ADRLEN-1 downto 0); +variable config_reg,win_reg: std_logic_vector (Word-1 downto 0); +constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0'); + begin + get_adr:=Std_logic_vector(to_unsigned(Core_get_adr,ADRLEN)); + + addr1:=Orig_Addr; + addr2:=Target_Disp; + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + end if; +-- + + -- if rising_edge(clkin) then + + if dcount =0 then + dcount:=dcount+1; + Interf.S.IntState1<=0; + elsif dcount>=1 and dcount <=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + wcount:=Interf.S.IntState1; + WritePtr (get_adr,wcount,SysRam); + Interf.S.IntState1<=wcount; + Interf.O.membusy<='1'; + Interf.O.Instruction<=x"00"; + if wcount =0 then + dcount:=4; + Interf.S.Intstate1<=1; + end if; + else + Interf.S.IntState1<=0; + + end if; + + elsif dcount=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if target_rank <=15 then --limitation de cete version à 16 rang + Interf.S.Gstart(Target_rank)<='1'; + end if; + adresse:=core_get_adr; + SysRam.O.Data_in<=MPI_GET & conv_Std_logic_vector(Target_Rank,4); --code fonction + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + dcount:=dcount+1; + end if; + elsif dcount=5 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+1; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + interf.O.Instruction<=x"06"; --le nbre de mots de l'intstruction + dcount:=dcount+1; + end if; + elsif dcount=6 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+2; + SysRam.O.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + dcount:=dcount+1; + + end if; + elsif dcount=7 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+3; + SysRam.O.Data_in<=Addr1(Word-1 downto 0); --source Bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + dcount:=dcount+1; + end if; + elsif dcount=8 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+4; + SysRam.O.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + dcount:=dcount+1; + end if; + elsif dcount=9 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+5; + SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + dcount:=dcount+1; + end if; + elsif dcount=10 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+7; + SysRam.O.Data_in<=x"00"; -- résultat du GET + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + Interf.S.IntState2<=0; + dcount:=dcount+1; + end if; + elsif dcount=11 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + addr1:=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + wcount:=Interf.S.IntState2; + wdata:=x"01";bitval:='1'; + setBit(wcount,Interf,SysRam,addr1(ADrLen-1 downto 0),wdata,bitval); + Interf.S.IntState2<=wcount; + if wcount=0 then + dcount:=dcount+1; + Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction + end if; + + elsif dcount=12 then + if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ? + Interf.O.Instr_En<='0'; --désactiver la prise en compte de l'instruction + dcount:=dcount+1; + config_reg:=SysRam.I.Data_out and x"f6"; + --SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + end if; + adresse:=core_base_adr+1; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + --SysRam.O.Ram_busy<='0'; --?? + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer la lecture du résultat du get + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + elsif dcount=13 then + + adresse:=core_base_adr+1; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du get + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + Interf.s.IntState2<=255; + Interf.s.tmem(0)<=x"08"; --tempo pour l'attente du résultat de Get + elsif dcount=14 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du GET + SysRam.O.enb<='0'; + adresse:=core_base_adr+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=18;--dcount+1; + Interf.O.membusy<='1'; + + end if; + elsif dcount=15 then + + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer l'écriture du WBusy + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy + SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + elsif dcount=16 then + + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer l'écriture du WBusy + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy + SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy + dcount:=dcount+1; + Interf.O.membusy<='1'; + + end if; + elsif dcount=17 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du GET + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; + SysRam.O.Data_in<=config_reg ; --; + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + elsif dcount>=18 and dcount <=21 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_get_adr+6,Adrlen)); + if SysRam.I.Data_out(0)='1' then --fin du MPI get ici pour l'envoie ! + dcount:=dcount+1; + end if; + end if; + elsif dcount>=22 and dcount <=24 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + if SysRam.I.Data_out(5)='1' then --Message du MPI Get bien reçu ! + dcount:=dcount+1; --ce test est fait avant l'arrivée effective des données ce qui pose problème ! + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + elsif Interf.S.Intstate2>0 then + Interf.S.Intstate2<=Interf.S.Intstate2-1; + elsif interf.s.tmem(0)>0 then + interf.s.tmem(0)<=interf.s.tmem(0)-1; + Interf.S.Intstate2<=255; + else + dcount:=1;--recommencer l'envoi + end if; + end if; + + elsif dcount=25 then + dcount:=0; --fin normale de la fonction + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + end if; + + NExtCtx:=dcount; +-- end if; + end procedure; +Procedure pMPI_Comm_group(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; COMM :in MPI_Comm; signal grp : out Mpi_group ) is +Begin +--cette procédure permet de récupérer le groupe qui est associé à un communicateur +--dans notre cas c'est la récupération du groupe associé à COMM_WORLD +end procedure; +--int MPI_Group_incl(MPI_Group group, int n, int *ranks, +-- MPI_Group *newgroup) +Procedure pMPI_group_incl(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; + GRP: Mpi_group; n:natural;ranks :natural; newgroup: out Mpi_group) is +Begin +-- cette procedure a pour algo de parcourir les rangs qui sont dans la mémoire pointée par ranks +-- et d'activer l'un des bits de position de newgroup. +-- +-- +end procedure; + +procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector ) is +variable adresse_rd : natural range 0 to 2**ADRLEN-1; + +begin + + if NextCtx =0 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + + NextCtx:=1; + + elsif NextCtx=1 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + NextCtx:=2; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=2 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); + NextCtx:=3; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=3 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); + NextCtx:=4; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=4 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); + NextCtx:=0; + Interf.O.membusy<='0'; + end if; + end if; +end procedure; + +--int MPI_Win_create( +-- void *base, +-- MPI_Aint size, +-- int disp_unit, +-- MPI_Info info, +-- MPI_Comm comm, +-- MPI_Win *win +--); +procedure pMPI_Win_create(NextCtx : inout natural ;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; + info:natural; comm:Mpi_Comm; Win: inout MPI_Win ) is + -- parcours de la liste des fenêtres existantes à la recherche d'un emplacement libre + -- si fenêtre libre trouvée, et + -- mise à 1 du Bit WCreate du registre status + type wtype is array (1 to 4 ) of natural range 0 to 255; + variable AdrWin: std_logic_vector(ADRLEN-1 downto 0); + variable adresse : std_logic_vector(ADRLEN-1 downto 0); + variable clkin : std_logic:='1'; + variable wcreate_adr : std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_wcreate_adr,ADRLEN)); + variable w0 : std_logic_vector(Word-1 downto 0); + variable adrnat : natural; + variable sizewin : std_logic_vector(Word-1 downto 0); + variable count : natural range 0 to 255; + variable wdisp :wtype:=(4,14,24,34); --stocke l'adresse de la prochaine Win libre +begin +-- création d'une fenêtre il s'agit d'affecter l'objet Win et de retourner +-- le pointeur qui permet de le décrire + + +If NextCtx=0 then + NExtCtx:=NextCtx+1; + count:=0; + Interf.O.membusy<='0'; + Interf.S.IntState1<=count; +elsif NextCtx>=1 and NextCtx <= 4 then + count:=Interf.S.IntState1; + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(NextCtx),16)); + readmem(count,interf,sysRam,AdrWin,w0); + if count=0 then + if w0(0)/='1' then -- cette fenêtre est libre + NextCtx:=6; --étape de la création de la fenêtre + Win.addr:=base; --l'adresse de la fenêtre + Win.id:=NextCtx; -- la référence provisoire de la fenêtre + Win.size:=Size; -- la taille de la fenêtre + + else + NextCtx:=NextCtx+1; + end if; + end if; + Interf.S.IntState1<=count;--sauvegarde du statut de la sous-procédure + +elsif NextCtx=5 then + -- Plus de fenêtre disponible erreur + NextCtx:=1; -- boucle sans fin :) + Win.id:=0; + Win.addr:=x"0000"; +elsif NextCtx=6 then + --Affectation de l'objet Windows car une place est disponible + count:=Interf.S.IntState1; + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + Writemem(count,interf,SysRam,AdrWin,x"01"); --signal status pour created + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + +elsif NextCtx=8 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + interf.S.winid<=interf.S.winid+1; + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,AdrWin+1,stdlv(interf.S.winid,8)); --win id de la fenêtre + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=9 then + + adrnat:=Core_base_adr+Wdisp(Win.id); + + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + count:=Interf.S.IntState1; + + + Writemem(count,interf,SysRam,AdrWin+2,base(7 downto 0)); --adresse basse + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=10 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,AdrWin+3,base(15 downto 8)); --adresse haute + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=11 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + sizewin:=std_logic_vector(to_unsigned(size,8)); + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,AdrWin+4,sizewin); -- taille de la fenêtre + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=12 then + --cette étape consiste à envoyer le message WINCREATE Sur le réseau et à récupérer + -- les informations donnant le numéro de la fenêtre + W0:=MPI_WIN_CREATE & std_logic_vector(to_unsigned(0,4)); --code fonction + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,wcreate_adr,w0); + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + + elsif NextCtx=13 then + w0:=std_logic_vector(to_unsigned(Win.Id,8)); -- id proposé pour la fenêtre en création + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,wcreate_adr+1,w0); + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=14 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + count:=Interf.S.IntState1; + if interf.I.ramsel='0' then + WritePtr (wcreate_adr,count,SysRam); --écriture du pointeur d'instruction + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + end if; + elsif NextCtx=15 then + -- il faut mettre instruction_en à 1 + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + adresse:=stdlv(core_base_adr+1); + SysRam.O.addr_rd<=adresse; + SysRam.O.Addr_wr<=adresse; + SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire; + Writemem(count,interf,SysRam,adresse,x"01"); + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + Interf.O.Instr_En<='1'; + adresse:=stdlv(core_base_adr); + SysRam.O.Addr_rd<=adresse; + NextCtx:=NextCtx+1; + elsif NextCtx=16 then --acquittement de la copie des données dans le tampon de la lib + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=NextCtx+1; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + elsif NextCtx=17 then + -- lecture du résultat de l'instruction + + +else + +end if; +end procedure; +--int MPI_Win_start( +-- MPI_Group group, +-- int assert, +-- MPI_Win win +--); +procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is +--cette fonction active les bits WStart pour chaque processus avec lequel +-- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à +--chacune de ces cibles + variable dcount : natural range 0 to 255:=0; + variable cstatus : std_logic_vector(Word-1 downto 0); + begin + + -- retour de l'adresse de de la fenêtre dans la structure Win + -- initialisation des bits concernant + + if NextCtx =0 then + NextCtx:=NextCtx+1; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + SysRam.O.Data_in<=x"01"; --mise à 1 du bit WSTART et remise à zero de tous les autres Bits + + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + Interf.S.GStart<=(others=>'0'); + end if; + elsif NextCtx=2 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + SysRam.O.Data_in<=x"01"; + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + SysRam.O.Data_in<=x"01"; + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=4 then + NextCtx:=0; + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + end if; + + + end procedure; +procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is +variable adresse :natural; +variable wcount: natural range 0 to 255:=0; +variable LRam : typ_dpRam; +variable SyncDest,i : natural range 0 to 15; --destination du message de synchronisation +variable W0 :std_logic_vector(Word-1 downto 0); +variable wcompl_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN)); + +begin + -- + wcompl_adr:=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN)); + LRam:=SysRam; -- nécessaire pour le débogage + if NextCtx =0 then + + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + Interf.O.MemBusy<='1'; --occuper la mémoire + Interf.S.IntState1<=0; + NextCtx:=1; + adresse:=core_wcompl_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + Interf.O.Instruction<=x"00"; + elsif NextCtx=1 then --écriture du ptr d'intruction + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if interf.I.ramsel='0' then + + adresse:=core_wcompl_adr; + + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + wcount:=Interf.S.IntState1; + WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir + Interf.S.IntState1<=wcount; + + if wcount =0 then + NextCtx:=2; + Interf.S.IntState1<=0; + Interf.S.IntState2<=0; + Interf.S.tmem(0)<=Interf.S.GStart(7 downto 0); --cibles impactées + Interf.S.tmem(1)<=Interf.S.GStart(15 downto 8); --cibles impactées + adresse:=core_wcompl_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + end if; + else + Interf.S.IntState1<=0; --recommencer l'écriture du pointeur + end if; + elsif NextCtx=2 then + if Interf.I.Ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr; + NextCtx:=10; --aller à la fin de la fonction + i:=0; + l1:for i in 0 to 7 loop + -- i:=i+1; + if i>=interf.s.intState2 then + if interf.s.gstart(i)='1' then + SysRam.O.Data_in<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4)); + Interf.S.tmem(2)<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4)); + + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.S.tmem(0)(i)<='0'; --ce dest a été traité ! + NextCtx:=4; + Interf.S.IntState2<=i+1; + exit l1; + end if; + end if; + exit l1 when i=7; + end loop l1; + end if; + elsif NextCtx=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr; + wcount:=Interf.S.IntState1; + WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir + Interf.S.IntState1<=wcount; + SysRam.O.Data_in<= Interf.S.tmem(2); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if wcount=0 then + NextCtx:=NextCtx+1; + end if; + end if; + elsif NextCtx=4 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr+1; + SysRam.O.Data_in<= x"04" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + elsif NextCtx=5 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr+2; + Interf.O.Instruction<=x"04";--longueur de l'instruction + SysRam.O.Data_in<=x"00" ;-- + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=6; + elsif NextCtx=6 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr+3; + SysRam.O.Data_in<= SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=7; + elsif NextCtx=7 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + adresse:=core_wcompl_adr+3; + SysRam.O.Data_in<=SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + + elsif NextCtx=8 then --fin de la fonction + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + --dcount:=0; + Interf.O.membusy<='0'; + Interf.O.Instr_En<='1'; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr+5,AdrLen)); + NextCtx:=NextCtx+1; + elsif NextCtx=9 then --acquittement de la copie des données dans le tampon + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=10; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + + elsif NextCtx=10 then --lecture de la fin de WComplete + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.S.IntState2=0 then --aucune instruction MPI exécutée ? + NextCtx:=12; + elsif Interf.S.tmem(0)/=0 then --plus de message compl à envoyer + NextCtx:=2; + elsif Interf.S.tmem(0)=0 then + if interf.I.ramsel='0' then + NextCtx:=NextCtx+1; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + end if; + end if; + elsif NextCtx=11 then --test de la fin des transferts + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + if SysRam.I.Data_out(0)='1' and SysRam.I.Data_out(6)='0' then --si WStart=1 et Wbusy=0 + --il faut un DSent=1 pour Put ou un DSending pour Get + if SysRam.I.Data_out(5)='1' or (SysRam.I.Data_out(4)='1' and SysRam.I.Data_out(1)='1') then + NextCtx:=NextCtx+1; + end if; + end if; + + end if; + elsif NextCtx=12 then + Interf.S.IntState1<=0; -- initialisation du compteur d'état + Interf.S.IntState2<=0; + SysRam.O.enb<='0'; + NextCtx:=0; --fin de la fonction + end if; + +end procedure; +procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is +--cette fonction active les bits WStart pour chaque processus avec lequel +-- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à +--chacune de ces cibles + variable W_Ptr : natural range 0 to 65535:=0;--adresse de la fenêtre en mémoire + variable dcount : natural range 0 to 255:=0; + variable cstatus : std_logic_vector(Word-1 downto 0); + begin + + -- retour de l'adresse de de la fenêtre dans la structure Win + -- initialisation des bits concernant + if Win.id =0 then + W_ptr:=Core_Base_Adr+4; + end if; + if NextCtx =0 then + + if pgroup.grp=0 then --rien à faire + nextCtx:=5; + Interf.S.GPost<=(others=>'0'); + else + NextCtx:=NextCtx+1; + end if; + Interf.O.Instruction<=x"00"; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + SysRam.O.Data_in<=x"48"; --mise à 1 du bit WPOST et WBusy et remise à zero de tous les autres Bits + + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + + end if; + --limitation de cete version à 16 rang + Interf.S.GPost<=pgroup.grp; + elsif NextCtx=2 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + SysRam.O.Data_in<=x"48"; --mise à 1 du bit WPOST et WBusy et remise à zero de tous les autres Bits + + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + + end if; + elsif NextCtx=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_Ptr+W_Gpost,Adrlen)); + SysRam.O.Data_in<=pgroup.grp(7 downto 0); + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; +elsif NextCtx=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_Gpost+1,Adrlen)); + SysRam.O.Data_in<=pgroup.grp(15 downto 8); + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; +elsif NextCtx=6 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_Gpost+1,Adrlen)); + SysRam.O.Data_in<=pgroup.grp(15 downto 8); + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=5 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + NextCtx:=0; + Interf.O.membusy<='0'; + end if; + + + end procedure; + + procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is +--permet de synchroniser la fin des opérations sur une fenêtre +variable dcount : natural range 0 to 255:=0; +variable cstatus : std_logic_vector(Word-1 downto 0); +variable W_Ptr : natural range 0 to 65535:=0;--adresse de la fenêtre en mémoire +begin + W_Ptr:=Core_base_adr+4;--adresse du reg status de la première fenêtre + if NextCtx =0 then + NextCtx:=NextCtx+1; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + NextCtx:=NextCtx+1; + end if; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+4,Adrlen)); + If Interf.S.Gpost=0 then + NextCtx:=5; --rien à synchroniser + end if; + elsif (NextCtx>=2) and (NextCtx <=3) then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + NextCtx:=NextCtx+1; + else + NextCtx:=1; + end if; + elsif NextCtx=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + + if SysRam.I.Data_out(3)='1' and SysRam.I.Data_out(6)='0' then --si WPost=1 et WBusy=0 + --il faut un DSent=1 pour Put ou un DSending pour Get + if SysRam.I.Data_out(4)='1' or (SysRam.I.Data_out(5)='1' and SysRam.I.Data_out(2)='1') then + NextCtx:=NextCtx+1; + Interf.S.GPost<=(others=>'0'); + end if; + elsif SysRam.I.Data_out(3)='0' then + NextCtx:=NextCtx; --pas d'opérations en attente + else + NextCtx:=NextCtx; --on attend + end if; + else + NextCtx:=2; --retour à l'atente du Bit ! + end if; + + elsif NextCtx=5 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + Interf.O.membusy<='0'; + NextCtx:=0; + end if; + + +end procedure; + + + Procedure pMPI_Finalize(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram) is + begin + + end procedure; + + procedure pMPI_Comm_Spawn(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; +command : natural; argv :natural; maxprocs : natural; info : natural; root : natural; comm : natural; +signal intercomm :out natural; signal array_of_errcodes : out natural) is + +variable i,dcount : natural:=0; +variable adresse :natural; +variable spawn_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_spawn_adr,ADRLEN)); +begin + spawn_adr:=Std_logic_vector(to_unsigned(Core_spawn_adr,ADRLEN)); + if NextCtx =0 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.Instruction<=x"00"; + NextCtx:=1; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + NextCtx:=2; + adresse:=core_spawn_adr; + SysRam.O.Data_in<=MPI_SPAWN & x"0" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + Interf.O.Instr_En<='0'; + Interf.S.IntState2<=1; -- préparation de la destination du spawn + end if; + elsif NextCtx=2 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if interf.I.ramsel='0' then + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + adresse:=core_spawn_adr; + if interf.I.ismain='1' then ---déclanche l'éxécution de la commande + SysRam.O.Data_in<=MPI_spawn & x"0";--Std_logic_vector(to_unsigned(Interf.S.IntState2+2,4)) ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + else -- envoie d'une commande spawn à la main lib + SysRam.O.Data_in<=MPI_spawn & x"0" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + + end if; + end if; + + elsif NextCtx=3 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + adresse:=core_spawn_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + elsif NextCtx=4 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+1; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(4,8)) ;--la longueur + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instruction<=x"04"; + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=5 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+2; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(maxprocs,8)) ;--le nombre de processus + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=6 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+3; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Data_in<=SPAWN_LOAD & std_logic_vector(to_unsigned(maxprocs,4)) ;--l'instruction + NextCtx:=NextCtx+1; + + end if; + elsif NextCtx=7 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+3; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Data_in<=SPAWN_LOAD & std_logic_vector(to_unsigned(maxprocs,4)) ;--l'instruction + NextCtx:=NextCtx+1; + report "MPV SPAWN activé " & integer'image(interf.I.Rank); + end if; + elsif NextCtx=8 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+7; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Data_in<=std_logic_vector(to_unsigned(0,Word)) ;--l'acquittement en retour + NextCtx:=NextCtx+1; + -- report "MPV SPAWN activé " & integer'image(interf.I.Rank); + end if; + elsif NextCtx=9 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + dcount:=Interf.S.IntState1; + if interf.I.ramsel='0' then + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,ADRLEN)); + WritePtr (spawn_adr,dcount,SysRam); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + Interf.S.IntState1<=dcount; + if dcount =0 then + NextCtx:=NextCtx+1; + end if; + end if; + elsif NextCtx=10 then + + --fin de la fonction + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + dcount:=0; + Interf.O.membusy<='0'; + Interf.O.Instr_En<='1'; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen)); + NextCtx:=NextCtx+1; + elsif NextCtx=11 then --acquittement de la copie des données dans le tampon + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=NextCtx+1; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + elsif NextCtx=12 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+7; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + if interf.I.ramsel='0' then + NextCtx:=NextCtx+1; + end if; + + elsif NextCtx=13 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+7; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + if SysRam.I.Data_out(5)='1' then --spawned + NextCtx:=NextCtx+1; + intercomm<=1; + end if; + Interf.O.membusy<='0'; + else + NextCtx:=12; + end if; + elsif NextCtx=14 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+8; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils + NextCtx:=NextCtx+1; + + end if; + Interf.O.membusy<='0'; + + elsif NextCtx=15 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+8; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils + NextCtx:=NextCtx+1; + + end if; + Interf.O.membusy<='0'; + + elsif NextCtx =16 then + Interf.O.Instr_En<='0'; + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + NextCtx:=0; + --array_of_errcodes<=0; + end if; + array_of_errcodes<=NextCtx; + end procedure; + +procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram) is +variable i,dcount,wcount : natural range 0 to 255:=0; +variable adresse :natural; +variable LRam : typ_dpRam; +variable W0 :std_logic_vector(Word-1 downto 0); +variable init_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN)); +begin + init_adr:=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN)); + LRam:=SysRam; -- nécessaire pour le débogage + if NextCtx =0 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.S.IntState1<=0; + Interf.O.Instruction<=x"00"; + NextCtx:=1; + adresse:=core_init_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + + elsif NextCtx=1 then --écriture du ptr d'intruction + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if interf.I.ramsel='0' then + + adresse:=core_init_adr; + + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + + wcount:=Interf.S.IntState1; + WritePtr (Init_adr,wcount,SysRam); + Interf.S.IntState1<=wcount; + + if wcount =0 then + NextCtx:=2; + Interf.S.IntState1<=0; + adresse:=core_init_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + end if; + end if; + elsif NextCtx=2 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + adresse:=core_init_adr; + SysRam.O.Data_in<=MPI_INIT & x"0" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=3; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=3 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_init_adr+1; + SysRam.O.Data_in<= x"04" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=4 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + Interf.O.membusy<='1'; + SysRam.O.enb<='0'; + adresse:=core_init_adr+1; + Interf.O.Instruction<=x"04"; + SysRam.O.Data_in<=x"04" ;--longueur de l'instruction + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=5; + end if; + elsif NextCtx=5 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + Interf.O.membusy<='1'; + SysRam.O.enb<='0'; + adresse:=core_init_adr+2; + SysRam.O.Data_in<= x"00" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=6; + end if; + + elsif NextCtx=6 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_init_adr+3; + SysRam.O.Data_in<=x"00" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=7; + end if; + elsif NextCtx=7 then --fin de la fonction + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + dcount:=0; + Interf.O.membusy<='0'; + Interf.O.Instruction(6)<=Interf.I.Spawned; --- préciser que la HT est dynamique + Interf.O.Instr_En<='1'; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen)); + NextCtx:=8; + elsif NextCtx=8 then --acquittement de la copie des données dans le tampon + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=9; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + + elsif NextCtx=9 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,Adrlen)); + if SysRam.I.Data_out(4)='1' then + NextCtx:=10; + Interf.S.IntState1<=0; -- initialisation du compteur d'état + end if; + Interf.O.membusy<='0'; + end if; + elsif NextCtx =10 then + dcount:=Interf.S.IntState1; --permet de sauvegarder l'état interne du compteur + readmem(dcount,interf,sysRam,init_Adr,w0); + Interf.S.IntState1<=dcount; + w0:=SysRam.I.Data_out; + if dcount=0 then + Interf.I.ismain<=all_zeros(SysRam.I.Data_out(3 downto 0));--Rank=0 -> MainLib + NextCtx:=NextCtx+1; + end if; + elsif NextCtx =11 then + Interf.O.Instruction<=x"00"; + Interf.O.Instr_En<='0'; + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + NextCtx:=0; + end if; + + +end procedure; + + +procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; Data:in std_logic_vector) is +--cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + + if dcount=0 then + --if interf.I.ramsel='0' then + dcount :=dcount+1; + --Interf.O.membusy<='1'; + --end if; + SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); + SysRam.O.Addr_wr<=adrToSet; + elsif dcount=1 then + if interf.I.ramsel='0' then + Interf.O.membusy<='1'; + dcount :=dcount+1; + end if; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + SysRam.O.Data_in<=data; + SysRam.O.Addr_wr<=adrToSet; + elsif dcount=2 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + SysRam.O.Data_in<=data; + dcount :=dcount+1; + SysRam.O.Addr_wr<=AdrToSet; + elsif dcount=3 then + Interf.O.membusy<='1'; + dcount :=dcount+1; + SysRam.O.Addr_wr<=adrToSet; + SysRam.O.Data_in<=data; + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + Interf.O.membusy<='0'; + SysRam.O.Addr_wr<=AdrToSet; + end if; + + NextCtx:=dcount; +end procedure; + +-- écriture dans la mémoire +procedure ReadMem( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; data: out std_logic_vector) is +--cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + if dcount=0 then + --if interf.I.ramsel='0' then + dcount :=dcount+1; + -- Interf.O.membusy<='1'; + --end if; + + SysRam.O.Addr_rd<=adrToSet; + elsif dcount=1 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + Interf.O.membusy<='0'; + end if; + data:=SysRam.I.Data_out; + SysRam.O.Addr_rd<=adrToSet; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + elsif dcount=2 then + if interf.I.ramsel='0' then + data:=SysRam.I.Data_out; + dcount :=dcount+1; + else + dcount:=2; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.Addr_rd<=adrToSet; + elsif dcount=3 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrToSet; + data:=SysRam.I.Data_out; + Interf.O.membusy<='0'; + else + dcount:=2; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + Interf.O.membusy<='0'; + data:=SysRam.I.Data_out; + end if; + data:=SysRam.I.Data_out; + NextCtx:=dcount; +end procedure; + +procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + variable AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic) is +--cette procédure permet de mettre à jour un Bit un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable tempdata:std_logic_vector(Word-1 downto 0); + + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + if dcount=0 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + Interf.O.membusy<='1'; + end if; + + SysRam.O.Addr_rd<=adrVect; + SysRam.O.Addr_Wr<=adrVect; + elsif dcount=1 then + if interf.I.ramsel='0' then + tempdata:=SysRam.I.Data_out; + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + end if; + SysRam.O.enb<='1'; + SySRam.O.ena<='0'; + SysRam.O.we<='0'; + elsif dcount=2 then + tempdata:=SysRam.I.Data_out; + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + SysRam.O.enb<='1'; + SySRam.O.ena<='0'; + SysRam.O.we<='0'; + elsif dcount=3 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_Wr<=adrVect; + SysRam.O.We<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + tempdata:=SysRam.I.Data_out; + Interf.O.membusy<='1'; + end if; + elsif dcount=4 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_Wr<=adrVect; + SysRam.O.We<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + tempdata:=SysRam.I.Data_out; + if BitVal='1' then + TempData:=Tempdata or BitMask; + else + TempData:=TempData and not (BitMAsk); + end if; + SysRam.O.Data_in<=TempData; + Interf.O.membusy<='1'; + end if; + elsif dcount=5 then --attente d'écriture + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + SysRam.O.We<='1'; + SysRam.O.ena<='1'; + --SysRam.O.Data_in<=TempData; + Interf.O.membusy<='1'; + end if; + elsif dcount=6 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + Interf.O.membusy<='0'; + SysRam.O.We<='0'; + SysRam.O.ena<='0'; + + end if; + + NextCtx:=dcount; +end procedure; + + + + + + + + + + + + + + + + +procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural;signal SysRam :out typ_dpram) is +--cette procédure permet d'écrire dans la mémoire du PE(tâche matérielle) +--les données de l'appel de la procédure +variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; +begin + if count /=0 then --préserver la valeur de count entre les appels + dcount:=count; + else + + + end if; + adresse:=Core_base_adr+2; + AdrToSet:=AdrVect; + if dcount=0 then + SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); + dcount :=dcount+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=1 then + + SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); + SysRam.O.We<='1';SysRam.O.Ena<='1'; + dcount :=dcount+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + elsif dcount=2 then + SysRam.O.We<='1';SysRam.O.Ena<='1'; + SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); + dcount :=dcount+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); + elsif dcount=3 then + dcount :=dcount+1; + SysRam.O.We<='1';SysRam.O.Ena<='1'; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + SysRam.O.We<='0';SysRam.O.Ena<='0'; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + end if; + + count:=dcount; +end procedure; +--int MPI_Alloc_mem(MPI_Aint size, MPI_Info info, void *baseptr) +procedure MPI_Alloc_mem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; +SIZE : natural; MPI_INFO: natural; baseptr: out std_logic_vector(ADRLEN-1 downto 0)) is +begin + --baseptr:=std_logic_vector(unsigned(Interf.S.HeapPtr,ADRLEN)); -- + -- Interf.S.HeapPtr<=Interf.S.HeapPtr+SIZE; + baseptr:=(others=>'1'); +end procedure; +end MPI_Rma; Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_RMA.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_RMA.vhd.bak (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MPI_RMA.vhd.bak (revision 142) @@ -0,0 +1,1834 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +use work.PACKET_TYPE.all; + +package Mpi_Rma is +procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural;signal SysRam :out typ_dpram); +procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram); +procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural); + +procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural); +procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector ); + +procedure pMPI_Win_create(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; + info:natural; comm:Mpi_Comm; Win: inout MPI_Win ); +procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win); +procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win); +procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win); +procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win); +procedure pMPI_Comm_Spawn(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; +command : natural; argv :natural; maxprocs : natural; info : natural; root : natural; comm : natural; +signal intercomm :out natural; signal array_of_errcodes : out natural); +-- declare functions and procedure +procedure MPI_Alloc_mem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; +SIZE : natural; MPI_INFO: natural; baseptr: out std_logic_vector(ADRLEN-1 downto 0)); + procedure ReadMem( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; data: out std_logic_vector); +procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; Data:in std_logic_vector); + +procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + variable AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic); + +end MPI_Rma; + + +package body MPI_Rma is +----int MPI_Put( +-- void *origin_addr, +-- int origin_count, +-- MPI_Datatype origin_datatype, +-- int target_rank, +-- MPI_Aint target_disp, +-- int target_count, +-- MPI_Datatype target_datatype, +-- MPI_Win win +--); +-- Example 1 +procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural) is +variable i,dcount,wr_state : natural:=0; +variable adresse :natural; +variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr; +variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp; +variable put_adr : std_logic_vector (ADRLEN-1 downto 0); +variable config_reg: std_logic_vector (Word-1 downto 0); +constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0'); + begin + put_adr:=conv_Std_logic_vector(Core_put_adr,ADRLEN); + + addr1:=Orig_Addr; + addr2:=Target_Disp; + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + end if; +-- + +-- if rising_edge(clkin) then + if dcount= 0 then + dcount:=dcount+1; + Interf.S.Intstate1<=0; + Interf.O.Instruction<=x"00"; + elsif dcount>=1 and dcount <=3 then + if interf.I.ramsel='0' then + Interf.O.membusy<='0'; + --SysRam.O.we<='1'; + --SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + wr_state:=interf.S.Intstate1; + WritePtr (put_adr,wr_state,SysRam); + interf.S.Intstate1<=wr_state; + if wr_state =0 then + -- fin de l'écriture du pointeur en mémoire + dcount:=4; + end if; + end if; + + elsif dcount=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + if target_rank <=15 then --limitation de cete version à 16 rang + Interf.S.Gstart(Target_rank)<='1'; + end if; + adresse:=core_put_adr; + SysRam.O.Data_in<=MPI_PUT & conv_std_logic_vector(Target_Rank,4); --code fonction + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=5 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+1; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + Interf.O.Instruction<=x"06"; -- nombre de mots de l'instruction + end if; + elsif dcount=6 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+2; + SysRam.O.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=7 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+3; + SysRam.O.Data_in<=Addr1(Word-1 downto 0); --source Bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=8 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+4; + SysRam.O.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=9 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+5; + SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=10 then + if interf.I.ramsel='0' then + adresse:=core_put_adr+6; + SysRam.O.Data_in<=(others=>'0'); -- valeur d'acquittement + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + end if; + elsif dcount=11 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + if interf.I.ramsel='0' then + adresse:=core_base_adr+1; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire; + Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction + Interf.O.membusy<='0'; + dcount:=dcount+1; + end if; + elsif dcount=12 then + if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ? + Interf.O.Instr_En<='0'; --désactiver la prise en compte de l'instruction + dcount:=dcount+1; + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + else + Interf.O.Instr_En<='1'; + end if; + adresse:=core_base_adr+1; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + --SysRam.O.Ram_busy<='0'; --?? + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer la lecture du résultat du Put + SysRam.O.enb<='1'; + elsif dcount=13 then + adresse:=core_base_adr+1; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du Put + SysRam.O.enb<='1'; + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=14 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du Put + SysRam.O.enb<='0'; + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + adresse:=core_base_adr+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=15 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_put_adr+6,Adrlen)); + if SysRam.I.Data_out(0)='1' then --fin du MPI PUT ici pour l'envoie ! + dcount:=dcount+1; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + Interf.S.Intstate2<=255; --timer pour la réception + interf.s.tmem(0)<=x"02"; + report "MPV pMPI_PUT():Ex1 de HCL a répondu concernant l'envoi"; + end if; + end if; + elsif dcount=16 or dcount=17 or dcount=18 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + -- ce cycle permet d'attendre la donnée en sortie après le changement d'adresse + + if interf.I.ramsel='0' then + dcount:=dcount+1; -- ce cycle permet d'attendre la donnée en sortie après le changement d'adresse + + elsif Interf.S.Intstate2>0 then + dcount:=16; + Interf.S.Intstate2<=Interf.S.Intstate2-1; + elsif interf.s.tmem(0)>0 then + interf.s.tmem(0)<=interf.s.tmem(0)-1; + Interf.S.Intstate2<=255; + dcount:=16; + else + dcount:=1;--recommencer l'envoi + end if; + elsif dcount=19 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + if SysRam.I.Data_out(5)='1' then --Message du MPI PUT bien reçu ! + dcount:=dcount+1; + report "MPV pMPI_PUT():Ex2 de HCL a reçu un acquittement concernant l'envoi"; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_put_adr+7,Adrlen); + elsif Interf.S.Intstate2>0 then + Interf.S.Intstate2<=Interf.S.Intstate2-1; + elsif interf.s.tmem(0)>0 then + interf.s.tmem(0)<=interf.s.tmem(0)-1; + Interf.S.Intstate2<=255; + else + dcount:=1;--recommencer l'envoi + report "MPV pMPI_PUT():Timeout EX2 n'a pas reçu d'acquitement concernant l'envoi. reémission en cours..."; + end if; + else + dcount:=16; + end if; + elsif dcount=20 then + dcount:=0; --fin normale de la fonction + Interf.O.membusy<='0'; + report "MPV pMPI_PUT():fin normale de la fonction"; + end if; + + + NExtCtx:=dcount; + -- end if; + end procedure; + +procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural) is +variable i,wcount,dcount : natural range 0 to 255:=0; +variable adresse :natural; +variable wdata: std_logic_vector(Word-1 downto 0):=(others=>'0'); +variable bitval : std_logic:='0'; +variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr; +variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp; +variable get_adr : std_logic_vector (ADRLEN-1 downto 0); +variable config_reg,win_reg: std_logic_vector (Word-1 downto 0); +constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0'); + begin + get_adr:=Std_logic_vector(to_unsigned(Core_get_adr,ADRLEN)); + + addr1:=Orig_Addr; + addr2:=Target_Disp; + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + end if; +-- + + -- if rising_edge(clkin) then + + if dcount =0 then + dcount:=dcount+1; + Interf.S.IntState1<=0; + elsif dcount>=1 and dcount <=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + wcount:=Interf.S.IntState1; + WritePtr (get_adr,wcount,SysRam); + Interf.S.IntState1<=wcount; + Interf.O.membusy<='1'; + Interf.O.Instruction<=x"00"; + if wcount =0 then + dcount:=4; + Interf.S.Intstate1<=1; + end if; + else + Interf.S.IntState1<=0; + + end if; + + elsif dcount=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if target_rank <=15 then --limitation de cete version à 16 rang + Interf.S.Gstart(Target_rank)<='1'; + end if; + adresse:=core_get_adr; + SysRam.O.Data_in<=MPI_GET & conv_Std_logic_vector(Target_Rank,4); --code fonction + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + dcount:=dcount+1; + end if; + elsif dcount=5 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+1; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + interf.O.Instruction<=x"06"; --le nbre de mots de l'intstruction + dcount:=dcount+1; + end if; + elsif dcount=6 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+2; + SysRam.O.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + dcount:=dcount+1; + + end if; + elsif dcount=7 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+3; + SysRam.O.Data_in<=Addr1(Word-1 downto 0); --source Bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + dcount:=dcount+1; + end if; + elsif dcount=8 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+4; + SysRam.O.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + dcount:=dcount+1; + end if; + elsif dcount=9 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+5; + SysRam.O.Data_in<=Addr2(Word-1 downto 0); -- destination bas + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + dcount:=dcount+1; + end if; + elsif dcount=10 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + adresse:=core_get_adr+7; + SysRam.O.Data_in<=x"00"; -- résultat du GET + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + Interf.S.IntState2<=0; + dcount:=dcount+1; + end if; + elsif dcount=11 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + addr1:=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + wcount:=Interf.S.IntState2; + wdata:=x"01";bitval:='1'; + setBit(wcount,Interf,SysRam,addr1(ADrLen-1 downto 0),wdata,bitval); + Interf.S.IntState2<=wcount; + if wcount=0 then + dcount:=dcount+1; + Interf.O.Instr_En<='1'; --active la prise en compte de l'instruction + end if; + + elsif dcount=12 then + if Interf.I.Instr_ack='1' then -- le Core a reçu l'instruction ? + Interf.O.Instr_En<='0'; --désactiver la prise en compte de l'instruction + dcount:=dcount+1; + config_reg:=SysRam.I.Data_out and x"f6"; + --SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + end if; + adresse:=core_base_adr+1; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + --SysRam.O.Ram_busy<='0'; --?? + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer la lecture du résultat du get + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + elsif dcount=13 then + + adresse:=core_base_adr+1; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du get + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + Interf.s.IntState2<=255; + Interf.s.tmem(0)<=x"08"; --tempo pour l'attente du résultat de Get + elsif dcount=14 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du GET + SysRam.O.enb<='0'; + adresse:=core_base_adr+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out and x"f6"; + SysRam.O.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=18;--dcount+1; + Interf.O.membusy<='1'; + + end if; + elsif dcount=15 then + + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer l'écriture du WBusy + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy + SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + elsif dcount=16 then + + SysRam.O.we<='0'; + SysRam.O.ena<='0'; -- préparer l'écriture du WBusy + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; --mettre à 1 Wbusy + SysRam.O.Data_in<=config_reg ; --mettre à 1 Wbusy + dcount:=dcount+1; + Interf.O.membusy<='1'; + + end if; + elsif dcount=17 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; -- préparer l'écriture du résultat du GET + SysRam.O.enb<='1'; + adresse:=core_base_adr+5; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if interf.I.ramsel='0' then + config_reg:=SysRam.I.Data_out or x"40"; + SysRam.O.Data_in<=config_reg ; --; + dcount:=dcount+1; + Interf.O.membusy<='1'; + end if; + elsif dcount>=18 and dcount <=21 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_get_adr+6,Adrlen)); + if SysRam.I.Data_out(0)='1' then --fin du MPI get ici pour l'envoie ! + dcount:=dcount+1; + end if; + end if; + elsif dcount>=22 and dcount <=24 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + if SysRam.I.Data_out(5)='1' then --Message du MPI Get bien reçu ! + dcount:=dcount+1; --ce test est fait avant l'arrivée effective des données ce qui pose problème ! + SysRam.O.addr_rd<=conv_Std_logic_vector(Core_Get_adr+7,Adrlen); + elsif Interf.S.Intstate2>0 then + Interf.S.Intstate2<=Interf.S.Intstate2-1; + elsif interf.s.tmem(0)>0 then + interf.s.tmem(0)<=interf.s.tmem(0)-1; + Interf.S.Intstate2<=255; + else + dcount:=1;--recommencer l'envoi + end if; + end if; + + elsif dcount=25 then + dcount:=0; --fin normale de la fonction + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + end if; + + NExtCtx:=dcount; +-- end if; + end procedure; +Procedure pMPI_Comm_group(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; COMM :in MPI_Comm; signal grp : out Mpi_group ) is +Begin +--cette procédure permet de récupérer le groupe qui est associé à un communicateur +--dans notre cas c'est la récupération du groupe associé à COMM_WORLD +end procedure; +--int MPI_Group_incl(MPI_Group group, int n, int *ranks, +-- MPI_Group *newgroup) +Procedure pMPI_group_incl(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; + GRP: Mpi_group; n:natural;ranks :natural; newgroup: out Mpi_group) is +Begin +-- cette procedure a pour algo de parcourir les rangs qui sont dans la mémoire pointée par ranks +-- et d'activer l'un des bits de position de newgroup. +-- +-- +end procedure; + +procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector ) is +variable adresse_rd : natural range 0 to 2**ADRLEN-1; + +begin + + if NextCtx =0 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + + NextCtx:=1; + + elsif NextCtx=1 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + NextCtx:=2; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=2 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); + NextCtx:=3; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=3 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); + NextCtx:=4; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=4 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.I.ramsel='0' then + Rank<=SysRam.I.Data_out(3 downto 0); + Interf.S.Rank<=conv_integer(SysRam.I.Data_out(3 downto 0)); + NextCtx:=0; + Interf.O.membusy<='0'; + end if; + end if; +end procedure; + +--int MPI_Win_create( +-- void *base, +-- MPI_Aint size, +-- int disp_unit, +-- MPI_Info info, +-- MPI_Comm comm, +-- MPI_Win *win +--); +procedure pMPI_Win_create(NextCtx : inout natural ;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; + info:natural; comm:Mpi_Comm; Win: inout MPI_Win ) is + -- parcours de la liste des fenêtres existantes à la recherche d'un emplacement libre + -- si fenêtre libre trouvée, et + -- mise à 1 du Bit WCreate du registre status + type wtype is array (1 to 4 ) of natural range 0 to 255; + variable AdrWin: std_logic_vector(ADRLEN-1 downto 0); + variable adresse : std_logic_vector(ADRLEN-1 downto 0); + variable clkin : std_logic:='1'; + variable wcreate_adr : std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_wcreate_adr,ADRLEN)); + variable w0 : std_logic_vector(Word-1 downto 0); + variable adrnat : natural; + variable sizewin : std_logic_vector(Word-1 downto 0); + variable count : natural range 0 to 255; + variable wdisp :wtype:=(4,14,24,34); --stocke l'adresse de la prochaine Win libre +begin +-- création d'une fenêtre il s'agit d'affecter l'objet Win et de retourner +-- le pointeur qui permet de le décrire + + +If NextCtx=0 then + NExtCtx:=NextCtx+1; + count:=0; + Interf.O.membusy<='0'; + Interf.S.IntState1<=count; +elsif NextCtx>=1 and NextCtx <= 4 then + count:=Interf.S.IntState1; + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(NextCtx),16)); + readmem(count,interf,sysRam,AdrWin,w0); + if count=0 then + if w0(0)/='1' then -- cette fenêtre est libre + NextCtx:=6; --étape de la création de la fenêtre + Win.addr:=base; --l'adresse de la fenêtre + Win.id:=NextCtx; -- la référence provisoire de la fenêtre + Win.size:=Size; -- la taille de la fenêtre + + else + NextCtx:=NextCtx+1; + end if; + end if; + Interf.S.IntState1<=count;--sauvegarde du statut de la sous-procédure + +elsif NextCtx=5 then + -- Plus de fenêtre disponible erreur + NextCtx:=1; -- boucle sans fin :) + Win.id:=0; + Win.addr:=x"0000"; +elsif NextCtx=6 then + --Affectation de l'objet Windows car une place est disponible + count:=Interf.S.IntState1; + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + Writemem(count,interf,SysRam,AdrWin,x"01"); --signal status pour created + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + +elsif NextCtx=8 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + interf.S.winid<=interf.S.winid+1; + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,AdrWin+1,stdlv(interf.S.winid,8)); --win id de la fenêtre + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=9 then + + adrnat:=Core_base_adr+Wdisp(Win.id); + + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + count:=Interf.S.IntState1; + + + Writemem(count,interf,SysRam,AdrWin+2,base(7 downto 0)); --adresse basse + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=10 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,AdrWin+3,base(15 downto 8)); --adresse haute + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=11 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + sizewin:=std_logic_vector(to_unsigned(size,8)); + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,AdrWin+4,sizewin); -- taille de la fenêtre + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=12 then + --cette étape consiste à envoyer le message WINCREATE Sur le réseau et à récupérer + -- les informations donnant le numéro de la fenêtre + W0:=MPI_WIN_CREATE & std_logic_vector(to_unsigned(0,4)); --code fonction + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,wcreate_adr,w0); + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + + elsif NextCtx=13 then + w0:=std_logic_vector(to_unsigned(Win.Id,8)); -- id proposé pour la fenêtre en création + count:=Interf.S.IntState1; + Writemem(count,interf,SysRam,wcreate_adr+1,w0); + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=14 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + count:=Interf.S.IntState1; + if interf.I.ramsel='0' then + WritePtr (wcreate_adr,count,SysRam); --écriture du pointeur d'instruction + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + end if; + elsif NextCtx=15 then + -- il faut mettre instruction_en à 1 + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + adresse:=stdlv(core_base_adr+1); + SysRam.O.addr_rd<=adresse; + SysRam.O.Addr_wr<=adresse; + SysRam.O.Data_in<=x"01"; --instruction pulse enable via la mémoire; + Writemem(count,interf,SysRam,adresse,x"01"); + Interf.S.IntState1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + Interf.O.Instr_En<='1'; + adresse:=stdlv(core_base_adr); + SysRam.O.Addr_rd<=adresse; + NextCtx:=NextCtx+1; + elsif NextCtx=16 then --acquittement de la copie des données dans le tampon de la lib + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=NextCtx+1; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + elsif NextCtx=17 then + -- lecture du résultat de l'instruction + + +else + +end if; +end procedure; +--int MPI_Win_start( +-- MPI_Group group, +-- int assert, +-- MPI_Win win +--); +procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is +--cette fonction active les bits WStart pour chaque processus avec lequel +-- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à +--chacune de ces cibles + variable dcount : natural range 0 to 255:=0; + variable cstatus : std_logic_vector(Word-1 downto 0); + begin + + -- retour de l'adresse de de la fenêtre dans la structure Win + -- initialisation des bits concernant + + if NextCtx =0 then + NextCtx:=NextCtx+1; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + SysRam.O.Data_in<=x"01"; --mise à 1 du bit WSTART et remise à zero de tous les autres Bits + + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + Interf.S.GStart<=(others=>'0'); + end if; + elsif NextCtx=2 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + SysRam.O.Data_in<=x"01"; + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + SysRam.O.Data_in<=x"01"; + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=4 then + NextCtx:=0; + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + end if; + + + end procedure; +procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is +variable adresse :natural; +variable wcount: natural range 0 to 255:=0; +variable LRam : typ_dpRam; +variable SyncDest,i : natural range 0 to 15; --destination du message de synchronisation +variable W0 :std_logic_vector(Word-1 downto 0); +variable wcompl_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN)); + +begin + -- + wcompl_adr:=Std_logic_vector(to_unsigned(Core_wcompl_adr,ADRLEN)); + LRam:=SysRam; -- nécessaire pour le débogage + if NextCtx =0 then + + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + Interf.O.MemBusy<='1'; --occuper la mémoire + Interf.S.IntState1<=0; + NextCtx:=1; + adresse:=core_wcompl_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + Interf.O.Instruction<=x"00"; + elsif NextCtx=1 then --écriture du ptr d'intruction + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if interf.I.ramsel='0' then + + adresse:=core_wcompl_adr; + + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + wcount:=Interf.S.IntState1; + WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir + Interf.S.IntState1<=wcount; + + if wcount =0 then + NextCtx:=2; + Interf.S.IntState1<=0; + Interf.S.IntState2<=0; + Interf.S.tmem(0)<=Interf.S.GStart(7 downto 0); --cibles impactées + Interf.S.tmem(1)<=Interf.S.GStart(15 downto 8); --cibles impactées + adresse:=core_wcompl_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + end if; + else + Interf.S.IntState1<=0; --recommencer l'écriture du pointeur + end if; + elsif NextCtx=2 then + if Interf.I.Ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr; + NextCtx:=10; --aller à la fin de la fonction + i:=0; + l1:for i in 0 to 7 loop + -- i:=i+1; + if i>=interf.s.intState2 then + if interf.s.gstart(i)='1' then + SysRam.O.Data_in<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4)); + Interf.S.tmem(2)<=MPI_WIN_SYNC & std_logic_vector(to_unsigned(i,4)); + + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.S.tmem(0)(i)<='0'; --ce dest a été traité ! + NextCtx:=4; + Interf.S.IntState2<=i+1; + exit l1; + end if; + end if; + exit l1 when i=7; + end loop l1; + end if; + elsif NextCtx=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr; + wcount:=Interf.S.IntState1; + WritePtr (wcompl_adr,wcount,SysRam); --attn cette fonction ne met pas à jour (we et ena) ! a voir + Interf.S.IntState1<=wcount; + SysRam.O.Data_in<= Interf.S.tmem(2); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + if wcount=0 then + NextCtx:=NextCtx+1; + end if; + end if; + elsif NextCtx=4 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr+1; + SysRam.O.Data_in<= x"04" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + elsif NextCtx=5 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr+2; + Interf.O.Instruction<=x"04";--longueur de l'instruction + SysRam.O.Data_in<=x"00" ;-- + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=6; + elsif NextCtx=6 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_wcompl_adr+3; + SysRam.O.Data_in<= SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=7; + elsif NextCtx=7 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + adresse:=core_wcompl_adr+3; + SysRam.O.Data_in<=SYNC_WCOMP & std_logic_vector(to_unsigned(Interf.S.Rank,4)); + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + + elsif NextCtx=8 then --fin de la fonction + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + --dcount:=0; + Interf.O.membusy<='0'; + Interf.O.Instr_En<='1'; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr+5,AdrLen)); + NextCtx:=NextCtx+1; + elsif NextCtx=9 then --acquittement de la copie des données dans le tampon + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=10; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + + elsif NextCtx=10 then --lecture de la fin de WComplete + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + if interf.S.IntState2=0 then --aucune instruction MPI exécutée ? + NextCtx:=12; + elsif Interf.S.tmem(0)/=0 then --plus de message compl à envoyer + NextCtx:=2; + elsif Interf.S.tmem(0)=0 then + if interf.I.ramsel='0' then + NextCtx:=NextCtx+1; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + end if; + end if; + elsif NextCtx=11 then --test de la fin des transferts + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+5,Adrlen)); + if SysRam.I.Data_out(0)='1' and SysRam.I.Data_out(6)='0' then --si WStart=1 et Wbusy=0 + --il faut un DSent=1 pour Put ou un DSending pour Get + if SysRam.I.Data_out(5)='1' or (SysRam.I.Data_out(4)='1' and SysRam.I.Data_out(1)='1') then + NextCtx:=NextCtx+1; + end if; + end if; + + end if; + elsif NextCtx=12 then + Interf.S.IntState1<=0; -- initialisation du compteur d'état + Interf.S.IntState2<=0; + SysRam.O.enb<='0'; + NextCtx:=0; --fin de la fonction + end if; + +end procedure; +procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is +--cette fonction active les bits WStart pour chaque processus avec lequel +-- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à +--chacune de ces cibles + variable W_Ptr : natural range 0 to 65535:=0;--adresse de la fenêtre en mémoire + variable dcount : natural range 0 to 255:=0; + variable cstatus : std_logic_vector(Word-1 downto 0); + begin + + -- retour de l'adresse de de la fenêtre dans la structure Win + -- initialisation des bits concernant + if Win.id =0 then + W_ptr:=Core_Base_Adr+4; + end if; + if NextCtx =0 then + + if pgroup.grp=0 then --rien à faire + nextCtx:=5; + Interf.S.GPost<=(others=>'0'); + else + NextCtx:=NextCtx+1; + end if; + Interf.O.Instruction<=x"00"; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + SysRam.O.Data_in<=x"48"; --mise à 1 du bit WPOST et WBusy et remise à zero de tous les autres Bits + + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + + end if; + --limitation de cete version à 16 rang + Interf.S.GPost<=pgroup.grp; + elsif NextCtx=2 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + SysRam.O.Data_in<=x"48"; --mise à 1 du bit WPOST et WBusy et remise à zero de tous les autres Bits + + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + + end if; + elsif NextCtx=3 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_Ptr+W_Gpost,Adrlen)); + SysRam.O.Data_in<=pgroup.grp(7 downto 0); + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; +elsif NextCtx=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_Gpost+1,Adrlen)); + SysRam.O.Data_in<=pgroup.grp(15 downto 8); + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; +elsif NextCtx=6 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + SysRam.O.addr_wr<=Std_logic_vector(to_unsigned(W_ptr+W_Gpost+1,Adrlen)); + SysRam.O.Data_in<=pgroup.grp(15 downto 8); + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=5 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + NextCtx:=0; + Interf.O.membusy<='0'; + end if; + + + end procedure; + + procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is +--permet de synchroniser la fin des opérations sur une fenêtre +variable dcount : natural range 0 to 255:=0; +variable cstatus : std_logic_vector(Word-1 downto 0); +variable W_Ptr : natural range 0 to 65535:=0;--adresse de la fenêtre en mémoire +begin + W_Ptr:=Core_base_adr+4;--adresse du reg status de la première fenêtre + if NextCtx =0 then + NextCtx:=NextCtx+1; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + NextCtx:=NextCtx+1; + end if; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+4,Adrlen)); + If Interf.S.Gpost=0 then + NextCtx:=5; --rien à synchroniser + end if; + elsif (NextCtx>=2) and (NextCtx <=3) then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + NextCtx:=NextCtx+1; + else + NextCtx:=1; + end if; + elsif NextCtx=4 then + if interf.I.ramsel='0' then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(W_ptr+W_status,Adrlen)); + + if SysRam.I.Data_out(3)='1' and SysRam.I.Data_out(6)='0' then --si WPost=1 et WBusy=0 + --il faut un DSent=1 pour Put ou un DSending pour Get + if SysRam.I.Data_out(4)='1' or (SysRam.I.Data_out(5)='1' and SysRam.I.Data_out(2)='1') then + NextCtx:=NextCtx+1; + Interf.S.GPost<=(others=>'0'); + end if; + elsif SysRam.I.Data_out(3)='0' then + NextCtx:=NextCtx; --pas d'opérations en attente + else + NextCtx:=NextCtx; --on attend + end if; + else + NextCtx:=2; --retour à l'atente du Bit ! + end if; + + elsif NextCtx=5 then + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + Interf.O.membusy<='0'; + NextCtx:=0; + end if; + + +end procedure; + + + Procedure pMPI_Finalize(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram) is + begin + + end procedure; + + procedure pMPI_Comm_Spawn(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; +command : natural; argv :natural; maxprocs : natural; info : natural; root : natural; comm : natural; +signal intercomm :out natural; signal array_of_errcodes : out natural) is + +variable i,dcount : natural:=0; +variable adresse :natural; +variable spawn_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_spawn_adr,ADRLEN)); +begin + spawn_adr:=Std_logic_vector(to_unsigned(Core_spawn_adr,ADRLEN)); + if NextCtx =0 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.Instruction<=x"00"; + NextCtx:=1; + elsif NextCtx=1 then + if interf.I.ramsel='0' then + NextCtx:=2; + adresse:=core_spawn_adr; + SysRam.O.Data_in<=MPI_SPAWN & x"0" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.membusy<='1'; + Interf.O.Instr_En<='0'; + Interf.S.IntState2<=1; -- préparation de la destination du spawn + end if; + elsif NextCtx=2 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if interf.I.ramsel='0' then + NextCtx:=NextCtx+1; + Interf.O.membusy<='1'; + adresse:=core_spawn_adr; + if interf.I.ismain='1' then ---déclanche l'éxécution de la commande + SysRam.O.Data_in<=MPI_spawn & x"0";--Std_logic_vector(to_unsigned(Interf.S.IntState2+2,4)) ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + else -- envoie d'une commande spawn à la main lib + SysRam.O.Data_in<=MPI_spawn & x"0" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + + end if; + end if; + + elsif NextCtx=3 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + adresse:=core_spawn_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + elsif NextCtx=4 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+1; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(4,8)) ;--la longueur + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instruction<=x"04"; + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=5 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+2; + SysRam.O.Data_in<=std_logic_vector(to_unsigned(maxprocs,8)) ;--le nombre de processus + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=6 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+3; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Data_in<=SPAWN_LOAD & std_logic_vector(to_unsigned(maxprocs,4)) ;--l'instruction + NextCtx:=NextCtx+1; + + end if; + elsif NextCtx=7 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+3; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Data_in<=SPAWN_LOAD & std_logic_vector(to_unsigned(maxprocs,4)) ;--l'instruction + NextCtx:=NextCtx+1; + report "MPV SPAWN activé " & integer'image(interf.I.Rank); + end if; + elsif NextCtx=8 then + if interf.I.ramsel='0' then + adresse:=core_spawn_adr+7; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + SysRam.O.Data_in<=std_logic_vector(to_unsigned(0,Word)) ;--l'acquittement en retour + NextCtx:=NextCtx+1; + -- report "MPV SPAWN activé " & integer'image(interf.I.Rank); + end if; + elsif NextCtx=9 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + dcount:=Interf.S.IntState1; + if interf.I.ramsel='0' then + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,ADRLEN)); + WritePtr (spawn_adr,dcount,SysRam); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + Interf.S.IntState1<=dcount; + if dcount =0 then + NextCtx:=NextCtx+1; + end if; + end if; + elsif NextCtx=10 then + + --fin de la fonction + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + dcount:=0; + Interf.O.membusy<='0'; + Interf.O.Instr_En<='1'; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen)); + NextCtx:=NextCtx+1; + elsif NextCtx=11 then --acquittement de la copie des données dans le tampon + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=NextCtx+1; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + elsif NextCtx=12 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+7; + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + if interf.I.ramsel='0' then + NextCtx:=NextCtx+1; + end if; + + elsif NextCtx=13 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+7; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + if SysRam.I.Data_out(5)='1' then --spawned + NextCtx:=NextCtx+1; + intercomm<=1; + end if; + Interf.O.membusy<='0'; + else + NextCtx:=12; + end if; + elsif NextCtx=14 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+8; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils + NextCtx:=NextCtx+1; + + end if; + Interf.O.membusy<='0'; + + elsif NextCtx=15 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + adresse:=core_spawn_adr+8; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(adresse,Adrlen)); + Intercomm<=conv_integer(SysRam.I.Data_out);-- le groupe des Ht Fils + NextCtx:=NextCtx+1; + + end if; + Interf.O.membusy<='0'; + + elsif NextCtx =16 then + Interf.O.Instr_En<='0'; + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + NextCtx:=0; + --array_of_errcodes<=0; + end if; + array_of_errcodes<=NextCtx; + end procedure; + +procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram) is +variable i,dcount,wcount : natural range 0 to 255:=0; +variable adresse :natural; +variable LRam : typ_dpRam; +variable W0 :std_logic_vector(Word-1 downto 0); +variable init_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN)); +begin + init_adr:=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN)); + LRam:=SysRam; -- nécessaire pour le débogage + if NextCtx =0 then + + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.S.IntState1<=0; + Interf.O.Instruction<=x"00"; + NextCtx:=1; + adresse:=core_init_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + + elsif NextCtx=1 then --écriture du ptr d'intruction + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + if interf.I.ramsel='0' then + + adresse:=core_init_adr; + + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.O.Instr_En<='0'; + Interf.O.membusy<='1'; + + wcount:=Interf.S.IntState1; + WritePtr (Init_adr,wcount,SysRam); + Interf.S.IntState1<=wcount; + + if wcount =0 then + NextCtx:=2; + Interf.S.IntState1<=0; + adresse:=core_init_adr; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + end if; + end if; + elsif NextCtx=2 then + if interf.I.ramsel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + adresse:=core_init_adr; + SysRam.O.Data_in<=MPI_INIT & x"0" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=3; + Interf.O.membusy<='1'; + end if; + elsif NextCtx=3 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_init_adr+1; + SysRam.O.Data_in<= x"04" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=4 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + Interf.O.membusy<='1'; + SysRam.O.enb<='0'; + adresse:=core_init_adr+1; + Interf.O.Instruction<=x"04"; + SysRam.O.Data_in<=x"04" ;--longueur de l'instruction + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=5; + end if; + elsif NextCtx=5 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + Interf.O.membusy<='1'; + SysRam.O.enb<='0'; + adresse:=core_init_adr+2; + SysRam.O.Data_in<= x"00" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=6; + end if; + + elsif NextCtx=6 then + if Interf.I.ramSel='0' then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='0'; + Interf.O.membusy<='1'; + adresse:=core_init_adr+3; + SysRam.O.Data_in<=x"00" ; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=7; + end if; + elsif NextCtx=7 then --fin de la fonction + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.membusy<='0'; + dcount:=0; + Interf.O.membusy<='0'; + Interf.O.Instruction(6)<=Interf.I.Spawned; --- préciser que la HT est dynamique + Interf.O.Instr_En<='1'; + SysRam.O.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen)); + NextCtx:=8; + elsif NextCtx=8 then --acquittement de la copie des données dans le tampon + if Interf.I.Instr_ack='1' then + Interf.O.Instr_En<='0'; + NextCtx:=9; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + + elsif NextCtx=9 then --lecture de la fin de l'initialisation + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + Interf.O.Instruction<=x"00"; + if interf.I.ramsel='0' then + SysRam.O.addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,Adrlen)); + if SysRam.I.Data_out(4)='1' then + NextCtx:=10; + Interf.S.IntState1<=0; -- initialisation du compteur d'état + end if; + Interf.O.membusy<='0'; + end if; + elsif NextCtx =10 then + dcount:=Interf.S.IntState1; --permet de sauvegarder l'état interne du compteur + readmem(dcount,interf,sysRam,init_Adr,w0); + Interf.S.IntState1<=dcount; + w0:=SysRam.I.Data_out; + if dcount=0 then + Interf.I.ismain<=all_zeros(SysRam.I.Data_out(3 downto 0));--Rank=0 -> MainLib + NextCtx:=NextCtx+1; + end if; + elsif NextCtx =11 then + Interf.O.Instr_En<='0'; + Interf.O.membusy<='0'; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='0'; + NextCtx:=0; + end if; + + +end procedure; + + +procedure WriteMem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; Data:in std_logic_vector) is +--cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + + if dcount=0 then + --if interf.I.ramsel='0' then + dcount :=dcount+1; + --Interf.O.membusy<='1'; + --end if; + SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); + SysRam.O.Addr_wr<=adrToSet; + elsif dcount=1 then + if interf.I.ramsel='0' then + Interf.O.membusy<='1'; + dcount :=dcount+1; + end if; + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + SysRam.O.Data_in<=data; + SysRam.O.Addr_wr<=adrToSet; + elsif dcount=2 then + SysRam.O.we<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + SysRam.O.Data_in<=data; + dcount :=dcount+1; + SysRam.O.Addr_wr<=AdrToSet; + elsif dcount=3 then + Interf.O.membusy<='1'; + dcount :=dcount+1; + SysRam.O.Addr_wr<=adrToSet; + SysRam.O.Data_in<=data; + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + Interf.O.membusy<='0'; + SysRam.O.Addr_wr<=AdrToSet; + end if; + + NextCtx:=dcount; +end procedure; + +-- écriture dans la mémoire +procedure ReadMem( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; data: out std_logic_vector) is +--cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + if dcount=0 then + --if interf.I.ramsel='0' then + dcount :=dcount+1; + -- Interf.O.membusy<='1'; + --end if; + + SysRam.O.Addr_rd<=adrToSet; + elsif dcount=1 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + Interf.O.membusy<='0'; + end if; + data:=SysRam.I.Data_out; + SysRam.O.Addr_rd<=adrToSet; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + elsif dcount=2 then + if interf.I.ramsel='0' then + data:=SysRam.I.Data_out; + dcount :=dcount+1; + else + dcount:=2; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + SysRam.O.Addr_rd<=adrToSet; + elsif dcount=3 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrToSet; + data:=SysRam.I.Data_out; + Interf.O.membusy<='0'; + else + dcount:=2; + end if; + SysRam.O.we<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + Interf.O.membusy<='0'; + data:=SysRam.I.Data_out; + end if; + data:=SysRam.I.Data_out; + NextCtx:=dcount; +end procedure; + +procedure SetBit( NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + variable AdrVect:in std_logic_vector(ADrLen-1 downto 0); variable BitMask: in std_logic_vector(Word-1 downto 0);bitval:in std_logic) is +--cette procédure permet de mettre à jour un Bit un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable tempdata:std_logic_vector(Word-1 downto 0); + + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + if dcount=0 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + Interf.O.membusy<='1'; + end if; + + SysRam.O.Addr_rd<=adrVect; + SysRam.O.Addr_Wr<=adrVect; + elsif dcount=1 then + if interf.I.ramsel='0' then + tempdata:=SysRam.I.Data_out; + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + end if; + SysRam.O.enb<='1'; + SySRam.O.ena<='0'; + SysRam.O.we<='0'; + elsif dcount=2 then + tempdata:=SysRam.I.Data_out; + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + SysRam.O.enb<='1'; + SySRam.O.ena<='0'; + SysRam.O.we<='0'; + elsif dcount=3 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_Wr<=adrVect; + SysRam.O.We<='0'; + SysRam.O.ena<='0'; + SysRam.O.enb<='1'; + tempdata:=SysRam.I.Data_out; + Interf.O.membusy<='1'; + end if; + elsif dcount=4 then + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_Wr<=adrVect; + SysRam.O.We<='1'; + SysRam.O.ena<='1'; + SysRam.O.enb<='1'; + tempdata:=SysRam.I.Data_out; + if BitVal='1' then + TempData:=Tempdata or BitMask; + else + TempData:=TempData and not (BitMAsk); + end if; + SysRam.O.Data_in<=TempData; + Interf.O.membusy<='1'; + end if; + elsif dcount=5 then --attente d'écriture + if interf.I.ramsel='0' then + dcount :=dcount+1; + SysRam.O.Addr_rd<=adrVect; + SysRam.O.We<='1'; + SysRam.O.ena<='1'; + --SysRam.O.Data_in<=TempData; + Interf.O.membusy<='1'; + end if; + elsif dcount=6 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + Interf.O.membusy<='0'; + SysRam.O.We<='0'; + SysRam.O.ena<='0'; + + end if; + + NextCtx:=dcount; +end procedure; + + + + + + + + + + + + + + + + +procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural;signal SysRam :out typ_dpram) is +--cette procédure permet d'écrire dans la mémoire du PE(tâche matérielle) +--les données de l'appel de la procédure +variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; +begin + if count /=0 then --préserver la valeur de count entre les appels + dcount:=count; + else + + + end if; + adresse:=Core_base_adr+2; + AdrToSet:=AdrVect; + if dcount=0 then + SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); + dcount :=dcount+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=1 then + + SysRam.O.Data_in<=AdrToSet(Word-1 downto 0); + SysRam.O.We<='1';SysRam.O.Ena<='1'; + dcount :=dcount+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + elsif dcount=2 then + SysRam.O.We<='1';SysRam.O.Ena<='1'; + SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); + dcount :=dcount+1; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); + elsif dcount=3 then + dcount :=dcount+1; + SysRam.O.We<='1';SysRam.O.Ena<='1'; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + SysRam.O.Data_in<=AdrToSet(ADRLEN-1 downto Word); + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + SysRam.O.We<='0';SysRam.O.Ena<='0'; + SysRam.O.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + end if; + + count:=dcount; +end procedure; +--int MPI_Alloc_mem(MPI_Aint size, MPI_Info info, void *baseptr) +procedure MPI_Alloc_mem(NextCtx : inout natural range 0 to 255;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; +SIZE : natural; MPI_INFO: natural; baseptr: out std_logic_vector(ADRLEN-1 downto 0)) is +begin + --baseptr:=std_logic_vector(unsigned(Interf.S.HeapPtr,ADRLEN)); -- + -- Interf.S.HeapPtr<=Interf.S.HeapPtr+SIZE; + baseptr:=(others=>'1'); +end procedure; +end MPI_Rma; Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MUX1.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MUX1.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MUX1.vhd (revision 142) @@ -0,0 +1,46 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:18:52 06/13/2011 +-- Design Name: +-- Module Name: MUX1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity CMUXP1 is + Port ( di1 : in STD_LOGIC; + di2 : in STD_LOGIC; + do : out STD_LOGIC; + sel : in STD_LOGIC); +end CMUXP1; + +architecture Behavioral of CMUXP1 is + +begin + --modelisation d'un multiplexeur 1 bit + with sel select + do <= di1 when '0', + di2 when '1', + di1 when others; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MUX8.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MUX8.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MUX8.vhd (revision 142) @@ -0,0 +1,45 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:30:26 06/13/2011 +-- Design Name: +-- Module Name: MUX8 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity CMUX8 is + Port ( di1 : in STD_LOGIC_VECTOR (7 downto 0); + di2 : in STD_LOGIC_VECTOR (7 downto 0); + sel : in STD_LOGIC; + do : out STD_LOGIC_VECTOR (7 downto 0)); +end CMUX8; + +architecture Behavioral of CMUX8 is + +begin + with sel select + do <= di1 when '0', + di2 when '1', + di1 when others; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MultiMPITest.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MultiMPITest.vhd.bak (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MultiMPITest.vhd.bak (revision 142) @@ -0,0 +1,228 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM Roland Christian +-- +-- Create Date: 16:44:13 08/01/2012 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/MultiMPITest.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: MPI_NOC +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- +-- +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +library NocLib ; + +use NocLib.CoreTypes.all; +LIbrary MPI_HCL; +use MPI_HCL.Packet_type.all; +use work.Hcl_Arch_conf.all; +USE ieee.numeric_std.ALL; + +ENTITY MultiMPITest IS +--simulation translate_off +port (clkm : in std_logic; +reset : in std_logic; +result : out std_logic_vector(Word-1 downto 0)); +--simulation translate_on +END MultiMPITest; + +ARCHITECTURE behavior OF MultiMPITest IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT MPI_NOC + generic (NPROC: natural:=2); + PORT( + MPI_Node_in : IN Ar_MPIPort_in(1 to NPROC); + MPI_Node_Out : OUT Ar_MPIPort_out(1 to NPROC) + ); + END COMPONENT; + Component PE + generic(destid : natural); + Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : out STD_LOGIC; + Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + CE : in STD_LOGIC; + Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_WE : in STD_LOGIC; + Core_RAM_EN : in STD_LOGIC; + --Core_RAM_ENB : in STD_LOGIC; + Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_Hold_req : in STD_LOGIC; + Core_Hold_Ack : out STD_LOGIC); +end Component; + + constant clk_period : time := 15 ns; + constant PROC : positive :=4; +-- synthesis translate_off +--===================signaux pour l'horloge ============================== +--signal reset,clkm : std_logic := '0'; +--======================================================================== +-- synthesis translate_on + --signaux pour la gestion de la MAE + type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, + putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); +signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées +signal count,count_i : natural range 0 to 15:=0; + +signal MPI_Node_in : Ar_MPIPort_in(1 to PROC) ; +signal MPI_Node_Out : Ar_MPIPort_out(1 to PROC); + + + + +BEGIN + Xbar: MPI_NOC GENERIC MAP (NPROC=>NOC_SIZE) + PORT MAP ( + MPI_Node_in => MPI_Node_in, + MPI_Node_Out => MPI_Node_Out + ); + +--PE1: PE generic map (DestId=>0) +--Port Map ( +--Instruction => MPi_Node_in(1).Instruction, +-- Instruction_en => MPi_Node_in(1).Instruction_en, +-- Core_PushOut => MPi_Node_out(1).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(1).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(1).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(1).ram_we, +-- Core_RAM_EN => MPI_Node_out(1).ram_en, +-- -- Core_RAM_ENB => MPI_Node_out(1).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(1).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(1).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(1).hold_req, +-- Core_Hold_Ack => MPI_Node_in(1).hold_ack +--); +-- +--PE2: PE Generic map (DestId=>1) +-- Port Map ( +-- Instruction => MPi_Node_in(2).Instruction, +-- Instruction_en => MPi_Node_in(2).Instruction_en, +-- Core_PushOut => MPi_Node_out(2).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(2).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(2).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(2).ram_we, +-- Core_RAM_EN => MPI_Node_out(2).ram_en, +-- --Core_RAM_ENB => MPI_Node_out(2).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(2).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(2).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(2).hold_req, +-- Core_Hold_Ack => MPI_Node_in(2).hold_ack +--); +--PE3: PE generic map (DestId=>2) +--Port Map ( +--Instruction => MPi_Node_in(3).Instruction, +-- Instruction_en => MPi_Node_in(3).Instruction_en, +-- Core_PushOut => MPi_Node_out(3).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(3).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(3).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(3).ram_we, +-- Core_RAM_EN => MPI_Node_out(3).ram_en, +-- -- Core_RAM_ENB => MPI_Node_out(1).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(3).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(3).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(3).hold_req, +-- Core_Hold_Ack => MPI_Node_in(3).hold_ack +--); +-- +--PE4: PE Generic map (DestId=>3) +-- Port Map ( +-- Instruction => MPi_Node_in(4).Instruction, +-- Instruction_en => MPi_Node_in(4).Instruction_en, +-- Core_PushOut => MPi_Node_out(4).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- CE => '1', +-- Core_RAM_Data_Out =>MPi_Node_in(4).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(4).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(4).ram_we, +-- Core_RAM_EN => MPI_Node_out(4).ram_en, +-- --Core_RAM_ENB => MPI_Node_out(2).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(4).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(4).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(4).hold_req, +-- Core_Hold_Ack => MPI_Node_in(4).hold_ack +--); +--MPI_Node_in(1).reset<=reset; +--MPI_Node_in(1).clk<=clkm; +--MPI_Node_in(2).reset<=reset; +--MPI_Node_in(2).clk<=clkm; +--MPI_Node_in(3).reset<=reset; +--MPI_Node_in(3).clk<=clkm; +--MPI_Node_in(4).reset<=reset; +--MPI_Node_in(4).clk<=clkm; +Result<=MPi_Node_out(1).PushOut; +PE_s:for i in 1 to STATIC_HT generate +S: PE Generic map (DestId=>i-1) + Port Map ( + Instruction => MPi_Node_in(i).Instruction, + Instruction_en => MPi_Node_in(i).Instruction_en, + Core_PushOut => MPi_Node_out(i).PushOut, + clk =>clkm, + reset =>reset, + CE => '1', + Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out, + Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in, + Core_RAM_WE => MPI_Node_out(i).ram_we, + Core_RAM_EN => MPI_Node_out(i).ram_en, + --Core_RAM_ENB => MPI_Node_out(2).ram_en, + Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr, + Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd, + Core_Hold_req => MPI_Node_out(i).hold_req, + Core_Hold_Ack => MPI_Node_in(i).hold_ack +); +MPI_Node_in(i).reset<=reset; +MPI_Node_in(i).clk<=clkm; +end generate PE_s; +dyn_HT: if dyn_allowed='1' generate +PE_D:for i in STATIC_HT+1 to NOC_SIZE generate +D: PE Generic map (DestId=>i-1) + Port Map ( + Instruction => MPi_Node_in(i).Instruction, + Instruction_en => MPi_Node_in(i).Instruction_en, + Core_PushOut => MPi_Node_out(i).PushOut, + clk =>clkm, + reset =>reset, + CE => '0', + Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out, + Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in, + Core_RAM_WE => MPI_Node_out(i).ram_we, + Core_RAM_EN => MPI_Node_out(i).ram_en, + --Core_RAM_ENB => MPI_Node_out(2).ram_en, + Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr, + Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd, + Core_Hold_req => MPI_Node_out(i).hold_req, + Core_Hold_Ack => MPI_Node_in(i).hold_ack +); +MPI_Node_in(i).reset<=reset; +MPI_Node_in(i).clk<=clkm; +end generate PE_D; +end generate dyn_HT; +END; Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MultiMPITest_new.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MultiMPITest_new.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/MultiMPITest_new.vhd (revision 142) @@ -0,0 +1,359 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM Roland Christian +-- +-- Create Date: 16:44:13 08/01/2012 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/MultiMPITest.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: MPI_NOC +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- +-- +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +library NocLib ; + +use NocLib.CoreTypes.all; +LIbrary MPI_HCL; +use MPI_HCL.Packet_type.all; +use work.Hcl_Arch_conf.all; +USE ieee.numeric_std.ALL; + +ENTITY Mpi_template IS +--simulation translate_off +port (clkm : in std_logic; +reset : in std_logic; +sw : in std_logic_vector(3 downto 0); --bouton bascule +Led : out std_logic_vector(Word-1 downto 0)); +--simulation translate_on +END MPi_template; + +ARCHITECTURE behavior OF MPI_Template IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT MPI_NOC + generic (NPROC: natural:=2); + PORT( + MPI_Node_in : IN Ar_MPIPort_in(1 to NPROC); + MPI_Node_Out : OUT Ar_MPIPort_out(1 to NPROC) + ); + END COMPONENT; + component proto_send is +generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée + fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie + fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie + fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée + fifo_in_data_out : in std_logic_vector(Word-1 downto 0); + fifo_out_data_in : out std_logic_vector(Word-1 downto 0); + packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet + copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo + snd_start : in std_logic; --début de la réception + snd_ack :in std_logic; -- acquittement de la réception + snd_comp : out std_logic; -- fin de la réception + mem :in memory(0 to sizemem-1)); --données à copier vers le fifo + end component proto_send; +Component Fifo2mem is +Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + wr_start : in STD_LOGIC; + fifo_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_data_available : in STD_LOGIC; + datalen : STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_data_out_en : out STD_LOGIC; + fifo_empty : in STD_LOGIC; + ram_busy : in STD_LOGIC; + ram_addr_start : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_addr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + ram_wr : out STD_LOGIC; + ram_en : out STD_LOGIC; + wr_comp :out STD_LOGIC); +end component fifo2mem; + Component PE + generic(destid : natural; + use_dyn:natural); + Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : out STD_LOGIC; + Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + CE : in STD_LOGIC; + Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_WE : in STD_LOGIC; + Core_RAM_EN : in STD_LOGIC; + --Core_RAM_ENB : in STD_LOGIC; + Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_Hold_req : in STD_LOGIC; + Core_Hold_Ack : out STD_LOGIC); +end Component; + + constant clk_period : time := 15 ns; + constant PROC : positive :=NOC_SIZE; --4 +-- synthesis translate_off +--===================signaux pour l'horloge ============================== +--signal reset,clkm : std_logic := '0'; +--======================================================================== +-- synthesis translate_on + --signaux pour la gestion de la MAE + type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, + putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); + +--groupe de signaux utilisé pour communiquer avec l'extérieur de la plateforme +type arDpRam is array (natural range <>) of typ_dpRam; +type typ_Pconsole is(idle,get_bus,get_ht_mem,rd_ht_mem,wr_ht_mem,et_end); +signal et_Pconsole,Next_et_Pconsole : typ_pconsole; +signal Pcons_ram :typ_dpram; --signaux pour accès à la ram par la console +signal pcons_hold_req,pcons_hold_ack: std_logic;--pour accès à la Ram du HT +signal pcons_wr_comp,pcons_wr_start : std_logic;--pour contrôler l'écriture dans la Ram du HT +signal pcons_rd_comp,pcons_rd_start :std_logic; +signal pcons_ram_busy : std_logic:='0'; +signal pcons_ht : natural range 0 to 15;--le numéro du HT qui est sollicité +signal mux_hold_req,dmux_hold_ack: std_logic_vector(1 to PROC); --multiplexer les signaux d'accès RAM HT entre Core_MPI et console +signal mux_ram : Ar_DpRam(1 to PROC); +signal pcons_sel:std_logic_vector(1 to PROC);--état de la sélection du MUX entre Console et Core MPI +-- +--signaux pour le module de communication RS232C +signal rs_cmd,rs_rw,rs_comp:std_logic; +signal rs_addr_start:std_logic_vector(adrlen-1 downto 0); +signal rs_plen :std_logic_vector(word-1 downto 0); +signal rs_fifo_data_out_en:std_logic; +signal rs_fifo_data_available : std_logic; +signal rs_fifo_data_out :std_logic_vector(word-1 downto 0); +-- +signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées +signal count,count_i : natural range 0 to 15:=0; + +signal MPI_Node_in : Ar_MPIPort_in(1 to PROC) ; +signal MPI_Node_Out : Ar_MPIPort_out(1 to PROC); + + + + +BEGIN +SysMPI: MPI_NOC GENERIC MAP (NPROC=>NOC_SIZE) + PORT MAP ( + MPI_Node_in => MPI_Node_in, + MPI_Node_Out => MPI_Node_Out + ); + +res_Led_sw:process (MPi_Node_out(1).PushOut,MPi_Node_out(1).PushOut) +variable p:natural range 0 to 15:=0; +begin +p:=to_integer(unsigned(sw)); --récupérer les switchs pour définir les entrées +Led<=MPi_Node_out(p).PushOut; +end process; + +S_Grp:for i in 1 to STATIC_HT generate +S: PE Generic map (DestId=>i-1, + use_dyn=>0) + Port Map ( + Instruction => MPi_Node_in(i).Instruction, + Instruction_en => MPi_Node_in(i).Instruction_en, + Core_PushOut => MPi_Node_out(i).PushOut, + clk =>clkm, + reset =>reset, + CE => '1', + Core_RAM_Data_Out =>mux_ram(i).i.Data_out, + Core_RAM_Data_IN => mux_ram(i).o.data_in, + Core_RAM_WE => mux_ram(i).o.we, + Core_RAM_EN => mux_ram(i).o.enb, + Core_RAM_Address_Wr => mux_ram(i).o.addr_wr, + Core_RAM_Address_Rd => mux_ram(i).o.addr_rd, + Core_Hold_req => mux_hold_req(i), + Core_Hold_Ack => dmux_hold_ack(i) +-- Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(i).ram_we, +-- Core_RAM_EN => MPI_Node_out(i).ram_en, +-- --Core_RAM_ENB => MPI_Node_out(2).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(i).hold_req, +-- Core_Hold_Ack => MPI_Node_in(i).hold_ack +); +MPI_Node_in(i).reset<=reset; +MPI_Node_in(i).clk<=clkm; +end generate S_Grp; +dyn_mod: if dyn_allowed='1' generate +D_Grp:for i in STATIC_HT+1 to NOC_SIZE generate +D: PE Generic map (DestId=>i-1, + use_dyn=>1) + Port Map ( + Instruction => MPi_Node_in(i).Instruction, + Instruction_en => MPi_Node_in(i).Instruction_en, + Core_PushOut => MPi_Node_out(i).PushOut, + clk =>clkm, + reset =>reset, + CE => '0', + Core_RAM_Data_Out =>mux_ram(i).i.Data_out, + Core_RAM_Data_IN => mux_ram(i).o.data_in, + Core_RAM_WE => mux_ram(i).o.we, + Core_RAM_EN => mux_ram(i).o.enb, + Core_RAM_Address_Wr => mux_ram(i).o.addr_wr, + Core_RAM_Address_Rd => mux_ram(i).o.addr_rd, + Core_Hold_req => mux_hold_req(i), + Core_Hold_Ack => dmux_hold_ack(i) +); +MPI_Node_in(i).reset<=reset; +MPI_Node_in(i).clk<=clkm; +end generate D_Grp; +end generate dyn_mod; + +--lecture de la mémoire de communication de chaque tâche et envoie des données +-- sur le port série +Pcons_sync:process(clkm) +begin +if rising_edge(clkm) then +if reset='1' then +Et_Pconsole<=idle; +else +et_Pconsole<=next_et_Pconsole; + +end if; +end if; +end process; +Pcons_next : process(et_Pconsole,rs_cmd) +variable bus_free:std_logic:='0'; +begin +case et_pconsole is +when idle => if rs_cmd='1' then + next_et_pconsole<=get_bus; + end if; +when get_bus => +bus_free:='0'; +for i in 1 to PROC loop + if MPI_Node_out(i).Hold_req='0' then + Pcons_sel(i)<='1'; + bus_free:='1'; + else + Pcons_sel(i)<='0'; + end if; +end loop; +if bus_free='1' then + next_et_pconsole<=get_ht_mem; +end if; +when get_ht_mem => if rs_rw='1' then + next_et_pconsole<=rd_ht_mem; + else --if rs_rw='1' then + next_et_pconsole<=wr_ht_mem; + end if; +when rd_ht_mem => if pcons_rd_comp='0' then + next_et_pconsole<=et_end; + end if; +when wr_ht_mem=> if pcons_wr_comp='1' then + next_et_pconsole<=et_end; + + end if; +when et_end => + for i in 1 to PROC loop + Pcons_sel(i)<='0'; + end loop; + if rs_cmd='0' then --atendre la fin de la cmd + next_et_pconsole<=idle; + end if; +end case; +end process; +Pcons_val : process(et_Pconsole) +begin +pcons_rd_start<='0'; +pcons_wr_start<='0'; +rs_comp<='0'; +case et_pconsole is +when idle => +when get_bus => +when get_ht_mem => +when rd_ht_mem => pcons_rd_start<='1'; +when wr_ht_mem=> pcons_wr_start<='1'; +when et_end=>rs_comp<='1'; + pcons_wr_start<='0'; +end case; +end process; +--Multiplexeur de la console pour l'accès à la RAM de chaque HT. +Ram_mux: process (clkm,MPI_Node_out,pcons_sel ) + begin +for i in 1 to PROC loop + case Pcons_sel(i) is + + + when '1' => + mux_ram(i).o.addr_wr<=pcons_ram.o.addr_wr; + mux_ram(i).o.addr_rd<=pcons_ram.o.addr_rd ; + mux_ram(i).o.we<=pcons_ram.o.we; + mux_ram(i).o.enb<=pcons_ram.o.enb; + mux_ram(i).o.data_in<=pcons_ram.o.data_in; + mux_hold_req(i)<=Pcons_Hold_req; + when others => + mux_ram(i).o.addr_wr<=MPI_Node_out(i).Ram_address_wr; + mux_ram(i).o.addr_rd<=MPI_Node_out(i).Ram_address_rd ; + mux_ram(i).o.we<=MPI_Node_out(i).Ram_we; + mux_ram(i).o.enb<=MPI_Node_out(i).Ram_en; + mux_ram(i).o.data_in<=MPI_Node_out(i).Ram_data_in; + mux_hold_req(i)<=MPI_Node_out(i).Hold_req; +end case ; +end loop; +end process ; +--écriture dans la mémoire d'une tâche matérielle +Inst_Fifo2Mem: Fifo2Mem PORT MAP( + clk =>clkm , + reset =>reset , + wr_start =>pcons_wr_start , + fifo_data_out => rs_fifo_data_out, + fifo_data_available =>rs_fifo_data_available , + datalen =>rs_plen , + fifo_data_out_en =>rs_fifo_data_out_en , + fifo_empty =>'0' , + ram_busy => pcons_ram_busy, --not pcons_sel(pcons_ht) , + ram_addr_start =>rs_addr_start , + ram_addr =>pcons_ram.o.addr_wr, + ram_data_in =>pcons_ram.o.data_in , + ram_wr =>pcons_ram.o.we , + ram_en =>pcons_ram.o.enb , + wr_comp =>pcons_wr_comp + ); +--démultiplexeurs de la console pour accès à la RAM de chaque Tâche matérielle. +Ram_dmux : process(MPI_node_in,mux_ram,PCons_sel,pcons_ht) +variable Tram_out:std_logic_vector(Word-1 downto 0):=(others=>'0'); +begin +for i in 1 to PROC loop +case PCons_sel(i) is + +when '1' => if pcons_ht=i then + Pcons_hold_ack<=dmux_hold_ack(i); + end if; + --Pcons_ram.I.data_out<=mux_ram(i).i.data_out; + if i=pcons_ht then + Pcons_ram.I.data_out<=mux_ram(i).i.data_out; + else + TRam_out:=Tram_out or mux_ram(i).i.data_out; + end if; + MPI_Node_in(i).hold_ack<='0'; + MPI_Node_in(i).Ram_data_out<=(others=>'-'); +when others => Pcons_hold_ack<='0'; + --Pcons_ram.I.data_out<=(others=>'-'); + TRam_out:=(others=>'-'); + MPI_Node_in(i).hold_ack<=dmux_hold_ack(i); + MPI_Node_in(i).Ram_data_out<=mux_ram(i).i.data_out; +end case; +end loop; + +end process; +END; Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/Packet_type.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/Packet_type.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/Packet_type.vhd (revision 142) @@ -0,0 +1,106 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions +-- package definissant le codage des fonctions MPI +-- dans le champs packet type des instructions MPI + +-- Ce fichier définit les trames des instruction MPI qui sont utilisables +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package Packet_type is + + constant ADRLEN1 :natural:=16; + constant MPI_COMM_WORLD :natural:=1; + constant MPI_DEFAULT :natural:=0; + constant MPI_INT :natural:=1; + constant MPI_INFO_NULL :natural:=0; + constant Default_Win :natural:=1; + constant MPI_GET_RANK : std_logic_vector(3 downto 0) := "0000"; + constant MPI_GET_SIZE : std_logic_vector(3 downto 0) := "0001"; + constant MPI_BARRIER : std_logic_vector(3 downto 0) := "0010"; + constant MPI_BARRIER_REACHED : std_logic_vector(3 downto 0) := "0011"; + constant MPI_BARRIER_COMPLETED : std_logic_vector(3 downto 0) := "1110"; + constant MPI_ACK : std_logic_vector(3 downto 0) := "0100"; + constant MPI_PUT : std_logic_vector(3 downto 0) := "0101"; + constant MPI_GET : std_logic_vector(3 downto 0) := "0110"; + constant MPI_BROADCAST : std_logic_vector(3 downto 0) := "0111"; + constant MPI_INIT : std_logic_vector(3 downto 0) := "1000"; + constant MPI_SPAWN : std_logic_vector(3 downto 0) := "1001"; + + constant MPI_WIN_CREATE : std_logic_vector(3 downto 0) := "1010"; + constant MPI_WIN_SYNC :std_logic_vector(3 downto 0):="1011"; + constant MPI_WIN_COMPLETE : std_logic_vector(3 downto 0) := "1100"; + constant MPI_WIN_POST : std_logic_vector(3 downto 0) := "1101"; + constant MPI_WIN_WAIT : std_logic_vector(3 downto 0) := "1110"; + + + + constant MPI_WTIME : std_logic_vector(3 downto 0) := "1110"; + constant MPI_WTICK : std_logic_vector(3 downto 0) := "1111"; + constant MPI_CONFIG : std_logic_vector(3 downto 0) := "1101"; + --paramètres des commandes + Constant INIT_SEEKMAIN : std_logic_vector(3 downto 0) := "0001"; + Constant INIT_SETRANK : std_logic_vector(3 downto 0) := "0011"; + Constant INIT_REGISTER : std_logic_vector(3 downto 0) := "0010"; + Constant INIT_STAT : std_logic_vector(3 downto 0) := "0100"; + Constant INIT_SPAWN : std_logic_vector(3 downto 0) := "0101"; + + Constant SPAWN_LOAD : std_logic_vector(3 downto 0) := "1001"; + Constant SPAWN_START : std_logic_vector(3 downto 0) := "1010"; + Constant SPAWN_COMP : std_logic_vector(3 downto 0) := "1011"; + Constant SPAWN_ERR : std_logic_vector(3 downto 0) := "1110"; + +Constant SYNC_WSTART : std_logic_vector(3 downto 0) := "0001"; + Constant SYNC_WPOST : std_logic_vector(3 downto 0) := "0010"; + Constant SYNC_WCOMP : std_logic_vector(3 downto 0) := "0011"; + Constant SYNC_WWAIT : std_logic_vector(3 downto 0) := "0100"; +-- constantes pour le NoC + Constant NOC_GETPORTID : std_logic_vector(7 downto 0) := "00000001"; +--constante pour les Ptr +constant W_Status :natural:=0; --position relative des champs dans la mémoire +constant W_Id :natural:=2; -- pour le type MPI_Win +constant W_GStart :natural:=3; +constant W_GPost :natural:=5; +constant W_Addr :natural:=7; +constant W_Size :natural:=9; +constant W_comm :natural:=10; + +Type MPI_Datatype is (MPI_BYTE,MPI_INTEGER,MPI_REAL,MPI_PACKET, MPI_pointer); +SUBType MPI_COMM is natural range 0 to 2**ADRLEN1-1 ; --pointeur sur la structure du communicateur +subType Mpi_AInt is natural range 0 to 2**ADRLEN1-1 ; +--subType Mpi_win is natural range 0 to 2**ADRLEN1-1 ; +Type MPI_COMM_struc is record + id : natural range 0 to 3; -- id du communicateur + grp : std_logic_vector(15 downto 0); --groupe associé au communicateur + nproc : natural range 0 to 15; -- nombre de membres du groupe de ce communicateur + AddrLib : std_logic_vector(15 downto 0); -- adresse dans la mémoire de la Lib + -- des registres GStart et GPost + ParentId:natural range 0 to 3; --Id du communicateur parent si Intercomm=1 + C_open,C_close,InterComm : std_logic; -- état du communciateur (Inistialisé ou finalisé) +end record; + +Type Mpi_Win is record + status : std_logic_vector(7 downto 0); --état de la fenêtre (create,Start,Complete,Post,WaitSync, etc.) + id : natural range 0 to 15 ; -- numéro de la fenêtre + + Addr : std_logic_vector(15 downto 0); -- adresse dans la mémoire locale du PE + Size : natural range 0 to 65535; -- taille de la fenêtre en octets + GPost : std_logic_vector(15 downto 0);--registres de synchronisation en cible + GStart : std_logic_vector(15 downto 0);-- registre de synchronisation source + comm : MPI_COMM; -- Ptr sur communicateur associé à la fenêtre +end record; +Type Mpi_group is record --normalement sous-goupe d'un communicateur + grp : std_logic_vector(15 downto 0); --( vecteur de la liste des processus du groupe) + nb : natural range 0 to 15; -- nombre de membres(processus du groupe) + comm_id : natural range 0 to 3; -- reférence du communicateur +end record; + +type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinPost,WinStart, + putdata,getdata,WinWait,WinCompleted,GetCmd,MpiSpawn,finalize,st_timeout); +end Packet_type; +package body Packet_type is + + +end Packet_type; Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/RAM_32_32.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/RAM_32_32.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/RAM_32_32.vhd (revision 142) @@ -0,0 +1,119 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM NGOUNOU +-- +-- Create Date: 18:33:31 03/05/2012 +-- Design Name: +-- Module Name: RAM_32_32 - Behavioral +-- Project Name: MPI_Core +-- Target Devices: +-- Tool versions: +-- Description: permet de stocker les données locales de la librairie MPI +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RAM_v is +generic(width : positive:=32; Size:positive:=16); +Port ( clka, clkb : in std_logic; + wea : in std_logic; + ena, enb : in std_logic; + addra, addrb : in std_logic_vector(size-1 downto 0); --cinq lignes d'adresse + dia : in std_logic_vector(width-1 downto 0); + dob : out std_logic_vector(width-1 downto 0)); +end RAM_v; + +architecture Behavioral of RAM_v is + attribute RAM_STYLE : string; + signal Lra,Lrb :std_logic:='0'; + signal sel : std_logic_vector(1 downto 0); + signal read_addr:std_logic_vector(12 downto 0); + signal doa,dout : std_logic_vector(width-1 downto 0); + type ram_type is array (2**(size-3)-1 downto 0) of std_logic_vector (width-1 downto 0); + signal RAM1,RAM2: ram_type; + attribute RAM_STYLE of RAM1: signal is "BLOCK"; + attribute RAM_STYLE of RAM2: signal is "BLOCK"; +begin + process (clka) + begin + if clka'event and clka = '1' then + if ena = '1' then + if wea = '1' then + + RAM1(conv_integer(addra(12 downto 0))) <= dia; + -- RAM2(conv_integer(addra(12 downto 0))) <= dia; + end if; + end if; + --if conv_integer(addrb)>8191 then +-- report "Erreur d'adresse"; +-- else +-- doa<=RAM1(conv_integer(addrb)); +-- end if; + -- Lra<='1'; +-- else +-- if lrb='1' then +-- Lra<='0'; +-- end if; +-- end if; + if conv_integer(addra)>8191 then + report "Erreur adresse Ecriture > 8191" + severity warning; + end if; + end if; + end process; + + + process (clkb) + begin + if clkb'event and clkb = '1' then + + if enb = '1' and ena='1' and addra=addrb then + --dout <= dia; --la sortie est égale à l'entrée + report "Collision R/W à l'adresse " & integer'image(conv_integer(addra)) + severity note; + read_addr<=addrb(12 downto 0); + Lra<='1'; + elsif enb='1' then + read_addr<=addrb(12 downto 0); + Lrb<='1'; + -- dout <= RAM2(conv_integer(addrb(12 downto 0))); + else + if Lra='1' then + Lrb<='0'; + end if; + end if; + if conv_integer(addrb)>8191 then + report "Erreur adresse de lecture > 8191" + severity warning; + end if; + end if; + end process; + --dob<=dout; + dob <= RAM1(conv_integer(read_addr)); + --sel<=(Lra,Lrb); +-- With sel select +-- dob <=dout when "11", +-- doa when "10", +-- dout when "01", +-- dout when "00", +-- dout when others; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/RAM_32_32.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/RAM_32_32.vhd.bak (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/RAM_32_32.vhd.bak (revision 142) @@ -0,0 +1,119 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM NGOUNOU +-- +-- Create Date: 18:33:31 03/05/2012 +-- Design Name: +-- Module Name: RAM_32_32 - Behavioral +-- Project Name: MPI_Core +-- Target Devices: +-- Tool versions: +-- Description: permet de stocker les données locales de la librairie MPI +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RAM_v is +generic(width : positive:=32; Size:positive:=16); +Port ( clka, clkb : in std_logic; + wea : in std_logic; + ena, enb : in std_logic; + addra, addrb : in std_logic_vector(size-1 downto 0); --cinq lignes d'adresse + dia : in std_logic_vector(width-1 downto 0); + dob : out std_logic_vector(width-1 downto 0)); +end RAM_v; + +architecture Behavioral of RAM_v is + attribute RAM_STYLE : string; + signal Lra,Lrb :std_logic:='0'; + signal sel : std_logic_vector(1 downto 0); + signal read_addr:std_logic_vector(12 downto 0); + signal doa,dout : std_logic_vector(width-1 downto 0); + type ram_type is array (2**(size-3)-1 downto 0) of std_logic_vector (width-1 downto 0); + signal RAM1,RAM2: ram_type; + attribute RAM_STYLE of RAM1: signal is "BLOCK"; + attribute RAM_STYLE of RAM2: signal is "BLOCK"; +begin + process (clka) + begin + if clka'event and clka = '1' then + if ena = '1' then + if wea = '1' then + + RAM1(conv_integer(addra(12 downto 0))) <= dia; + -- RAM2(conv_integer(addra(12 downto 0))) <= dia; + end if; + end if; + --if conv_integer(addrb)>8191 then +-- report "Erreur d'adresse"; +-- else +-- doa<=RAM1(conv_integer(addrb)); +-- end if; + -- Lra<='1'; +-- else +-- if lrb='1' then +-- Lra<='0'; +-- end if; +-- end if; + if conv_integer(addra)>8191 then + report "Erreur adresse Ecriture > 8191" + severity warning; + end if; + end if; + end process; + + + process (clkb) + begin + if clkb'event and clkb = '1' then + + if enb = '1' and ena='1' and addra=addrb then + --dout <= dia; --la sortie est égale à l'entrée + report "Collision R/W à l'adresse " & integer'image(conv_integer(addra)) + severity note; + read_addr<=addrb(12 downto 0); + Lra<='1'; + elsif enb='1' then + read_addr<=addrb(12 downto 0); + Lrb<='1'; + -- dout <= RAM2(conv_integer(addrb(12 downto 0))); + else + if Lra='1' then + Lrb<='0'; + end if; + end if; + if conv_integer(addrb)>8191 then + report "Erreur adresse de lecture > 8191" + severity warning; + end if; + end if; + end process; + --dob<=dout; + dout <= RAM1(conv_integer(read_addr)); + sel<=(Lra,Lrb); + With sel select + dob <=dout when "11", + doa when "10", + dout when "01", + dout when "00", + dout when others; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/RAM_64.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/RAM_64.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/RAM_64.vhd (revision 142) @@ -0,0 +1,67 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 18:54:08 04/19/2011 +-- Design Name: +-- Module Name: RAM_64 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: SYNTHESE d'une RAM 64 octet par inferation +-- la ram possède un port d'écriture et un port de lecture +-- le port primaire est à lecture et ecrite et le port secondaire à lecture seule +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RAM_64 is + Port ( clka, clkb : in std_logic; + wea : in std_logic; + ena, enb : in std_logic; + addra, addrb : in std_logic_vector(5 downto 0); + dia : in std_logic_vector(Word-1 downto 0); + dob : out std_logic_vector(Word-1 downto 0)); +end RAM_64; + +architecture Behavioral of RAM_64 is + type ram_type is array (63 downto 0) of std_logic_vector (Word-1 downto 0); + signal RAM: ram_type; +begin + process (clka) + begin + if clka'event and clka = '1' then + if ena = '1' then + if wea = '1' then + RAM(conv_integer(addra)) <= dia; + end if; + end if; + end if; + end process; + + process (clkb) + begin + if clkb'event and clkb = '1' then + if enb = '1' then + --dob <= RAM(conv_integer(addrb)) ; + end if; + end if; + end process; + dob <= RAM(conv_integer(addrb)) ; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/RAM_MUX.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/RAM_MUX.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/RAM_MUX.vhd (revision 142) @@ -0,0 +1,96 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:45:28 07/26/2012 +-- Design Name: +-- Module Name: RAM_MUX - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- Multiplexeur de la memoire du noeud +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +library NocLib ; +--use IEEE.STD_LOGIC_ARITH.ALL; +--use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +USE ieee.numeric_std.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RAM_MUX is + Port ( ram_ena_in : in STD_LOGIC_VECTOR (1 downto 0); + ram_enb_in : in STD_LOGIC_VECTOR (1 downto 0); + ram_we_in : in STD_LOGIC_VECTOR (1 downto 0); + ram_dina_in_0 : in STD_LOGIC_VECTOR (word - 1 downto 0); + ram_dina_in_1 : in STD_LOGIC_VECTOR (word - 1 downto 0); + ram_addra_in_0 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_addra_in_1 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_addrb_in_0 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_addrb_in_1 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_dob_in : in STD_LOGIC_VECTOR (word - 1 downto 0); + + + ram_ena_out : out STD_LOGIC; + ram_enb_out : out STD_LOGIC; + ram_we_out : out STD_LOGIC; + ram_dina_out : out STD_LOGIC_VECTOR (word - 1 downto 0); + ram_addra_out : out STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_addrb_out : out STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_dob_out_0 : out STD_LOGIC_VECTOR (word - 1 downto 0); + ram_dob_out_1 : out STD_LOGIC_VECTOR (word - 1 downto 0); + sel : in std_logic + ); +end RAM_MUX; + +architecture Behavioral of RAM_MUX is + +begin + +mux : process(sel,ram_ena_in,ram_enb_in ,ram_we_in,ram_dina_in_0, ram_dina_in_1,ram_addra_in_0,ram_addra_in_1, ram_addrb_in_0, ram_addrb_in_1, ram_dob_in) + begin + + if sel = '1' then + -- si sel est à 1 les entrées 1 sont sur les sorties correspondantes + ram_ena_out <= ram_ena_in(1); + ram_enb_out <= ram_enb_in(1); + ram_we_out <= ram_we_in(1); + ram_dina_out <= ram_dina_in_1; + ram_addra_out <= ram_addra_in_1; + ram_addrb_out <= ram_addrb_in_1 ; + ram_dob_out_1 <= ram_dob_in; + ram_dob_out_0 <= (others => '0'); + else + -- si est à 0 les entrées 0 sont sur les sorties correspondantes + ram_ena_out <= ram_ena_in(0); + ram_enb_out <= ram_enb_in(0); + ram_we_out <= ram_we_in(0); + ram_dina_out <= ram_dina_in_0; + ram_addra_out <= ram_addra_in_0; + ram_addrb_out <= ram_addrb_in_0 ; + ram_dob_out_0 <= ram_dob_in; + ram_dob_out_1 <= (others => '0'); + + end if; + + + end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/SetBit.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/SetBit.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/SetBit.vhd (revision 142) @@ -0,0 +1,187 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:30:11 08/01/2013 +-- Design Name: +-- Module Name: SetBit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +Library NocLib; +use NoCLib.CoreTypes.all; +--use work.packet_type.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity SetBit is + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + BitMask : in std_logic_vector(Word-1 downto 0); + BitVal : in std_logic; + whole : in std_logic; + dma_wr_grant : in STD_LOGIC; + dma_wr_request : out STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + ram_rd : out std_logic; + ram_wr : out std_logic; + start : in std_logic; + done : out std_logic; + ram_address : in std_logic_vector(ADRLEN-1 downto 0);--accès au stockage + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0)); +end SetBit; + +architecture Behavioral of SetBit is +signal State,Next_State:natural range 0 to 15 :=0; +signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; +signal tempval,tempval_i : std_logic_vector(Word-1 downto 0):=(others=>'1'); +begin +PSetBit_sync:process(clk,reset) + +begin +if rising_edge(clk) then +if reset='1' then + State<=0; + Tempval<=(others=>'0'); +else + State<=Next_State; + Tempval<=tempval_i; +end if; +end if; +end process; + +PSetBit:process (State,tempval,Start,whole,BitMask,BitVal,Dma_rd_grant,Dma_wr_grant,ram_data_out) + begin + Next_State<=State; + + tempval_i<=tempval; + wr_ok<='0'; + rd_ok<='0'; +if State >0 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; +case State is +when 0 =>Ram_data_in<=tempval; + rd_ok<='0'; + Wr_ok<='0'; + done<='0'; + if start='1' and whole='1' then + Next_State<=5; + wr_ok<='0'; + ram_data_in<=bitmask; + elsif start='1' then + Next_State<=State+1; + end if; + +when 1=> Ram_data_in<=tempval; + if dma_rd_grant='1' then + Next_State<=State+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + done<='0'; + When 2|3=>Ram_data_in<=Ram_data_out; + if dma_rd_grant='1' then --cycle d'attente + Next_State<=State+1; + else + Next_State<=1; --recommencer l'attente si perte de priorité + end if; + rd_ok<='1'; + wr_ok<='0'; + done<='0'; + When 4 => + Ram_data_in<=ram_data_out; + done<='0'; + rd_ok<='1'; + if dma_rd_grant='1' and dma_wr_grant='1' then + Next_State<=5; + --tempval<=Ram_data_out; +-- if bitval='1' then +-- tempval<= Ram_data_out or BitMask; +-- else +-- tempval<= Ram_data_out and not (BitMask); +-- end if; + if whole='1' then + --ram_data_in<=bitmask; + tempval_i<= BitMask; + else + if bitval='1' then + --ram_data_in<=Ram_data_out or BitMask; + tempval_i<= Ram_data_out or BitMask; + else + --Ram_data_in<=Ram_data_out and not (BitMask); + tempval_i<= Ram_data_out and not (BitMask); + end if; + end if; + rd_ok<='1'; + wr_ok<='1'; + else + Next_State<=State; + report "SetBit:Impossible d'avoir accès en R/W à la RAM"; + end if; + When 5 |6 => + Ram_data_in<=tempval; + if dma_wr_grant='1' then + if whole='1' then + ram_data_in<=bitmask; + else + ram_data_in<=tempval; + end if; + Next_State<=State+1; + else + Next_state<=5; + end if; + wr_ok<='1'; + rd_ok<='1'; + done<='0'; + When 7=> + done<='1'; + if start='0' then + Next_State<=0; + wr_ok<='0'; + end if; + rd_ok<='0'; + wr_ok<='0'; + Ram_data_in<=tempval; + When others => + Next_State<=0; + rd_ok<='0'; + wr_ok<='0'; + done<='0'; + Ram_data_in<=tempval; +end case; + +end process PSetBit; +dma_rd_request <= dma_rd; +dma_wr_request <=dma_wr; +Ram_wr<=wr_ok; +Ram_rd<=rd_ok; +--Ram_data_out<=data_to_ram; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/SetBit.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/SetBit.vhd.bak (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/SetBit.vhd.bak (revision 142) @@ -0,0 +1,187 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:30:11 08/01/2013 +-- Design Name: +-- Module Name: SetBit - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +Library NocLib; +use NoCLib.CoreTypes.all; +--use work.packet_type.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity SetBit is + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + BitMask : in std_logic_vector(Word-1 downto 0); + BitVal : in std_logic; + whole : in std_logic; + dma_wr_grant : in STD_LOGIC; + dma_wr_request : out STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + ram_rd : out std_logic; + ram_wr : out std_logic; + start : in std_logic; + done : out std_logic; + ram_address : in std_logic_vector(ADRLEN-1 downto 0);--accès au stockage + Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0)); +end SetBit; + +architecture Behavioral of SetBit is +signal State,Next_State:natural range 0 to 15 :=0; +signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; +signal tempval,tempval_i : std_logic_vector(Word-1 downto 0):=(others=>'1'); +begin +PSetBit_sync:process(clk,reset) + +begin +if rising_edge(clk) then +if reset='1' then + State<=0; + Tempval<=(others=>'0'); +else + State<=Next_State; + Tempval<=tempval_i; +end if; +end if; +end process; + +PSetBit:process (State,tempval,Start,whole,BitMask,BitVal,Dma_rd_grant,Dma_wr_grant,ram_data_out) + begin + Next_State<=State; + + tempval_i<=tempval; + wr_ok<='0'; + rd_ok<='0'; +if State >0 then + + dma_wr<='1'; --demander un accès exclusif au bus + dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données + else + dma_wr<='0'; + dma_rd<='0'; + end if; +case State is +when 0 =>Ram_data_in<=tempval; + rd_ok<='0'; + Wr_ok<='0'; + done<='0'; + if start='1' and whole='1' then + Next_State<=5; + wr_ok<='1'; + ram_data_in<=bitmask; + elsif start='1' then + Next_State<=State+1; + end if; + +when 1=> Ram_data_in<=tempval; + if dma_rd_grant='1' then + Next_State<=State+1; + + end if; + rd_ok<='1'; + wr_ok<='0'; + done<='0'; + When 2|3=>Ram_data_in<=Ram_data_out; + if dma_rd_grant='1' then --cycle d'attente + Next_State<=State+1; + else + Next_State<=1; --recommencer l'attente si perte de priorité + end if; + rd_ok<='1'; + wr_ok<='0'; + done<='0'; + When 4 => + Ram_data_in<=ram_data_out; + done<='0'; + rd_ok<='1'; + if dma_rd_grant='1' and dma_wr_grant='1' then + Next_State<=5; + --tempval<=Ram_data_out; +-- if bitval='1' then +-- tempval<= Ram_data_out or BitMask; +-- else +-- tempval<= Ram_data_out and not (BitMask); +-- end if; + if whole='1' then + --ram_data_in<=bitmask; + tempval_i<= BitMask; + else + if bitval='1' then + --ram_data_in<=Ram_data_out or BitMask; + tempval_i<= Ram_data_out or BitMask; + else + --Ram_data_in<=Ram_data_out and not (BitMask); + tempval_i<= Ram_data_out and not (BitMask); + end if; + end if; + rd_ok<='1'; + wr_ok<='1'; + else + Next_State<=State; + report "SetBit:Impossible d'avoir accès en R/W à la RAM"; + end if; + When 5 |6 => + Ram_data_in<=tempval; + if dma_wr_grant='1' then + if whole='1' then + ram_data_in<=bitmask; + else + ram_data_in<=tempval; + end if; + Next_State<=State+1; + else + Next_state<=5; + end if; + wr_ok<='1'; + rd_ok<='1'; + done<='0'; + When 7=> + done<='1'; + if start='0' then + Next_State<=0; + wr_ok<='0'; + end if; + rd_ok<='0'; + wr_ok<='0'; + Ram_data_in<=tempval; + When others => + Next_State<=0; + rd_ok<='0'; + wr_ok<='0'; + done<='0'; + Ram_data_in<=tempval; +end case; + +end process PSetBit; +dma_rd_request <= dma_rd; +dma_wr_request <=dma_wr; +Ram_wr<=wr_ok; +Ram_rd<=rd_ok; +--Ram_data_out<=data_to_ram; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/UART_TX_CTRL.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/UART_TX_CTRL.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/UART_TX_CTRL.vhd (revision 142) @@ -0,0 +1,159 @@ +---------------------------------------------------------------------------- +-- UART_TX_CTRL.vhd -- UART Data Transfer Component +---------------------------------------------------------------------------- +-- Author: Sam Bobrowicz +-- Copyright 2011 Digilent, Inc. +---------------------------------------------------------------------------- +-- +---------------------------------------------------------------------------- +-- This component may be used to transfer data over a UART device. It will +-- serialize a byte of data and transmit it over a TXD line. The serialized +-- data has the following characteristics: +-- *9600 Baud Rate +-- *8 data bits, LSB first +-- *1 stop bit +-- *no parity +-- +-- Port Descriptions: +-- +-- SEND - Used to trigger a send operation. The upper layer logic should +-- set this signal high for a single clock cycle to trigger a +-- send. When this signal is set high DATA must be valid . Should +-- not be asserted unless READY is high. +-- DATA - The parallel data to be sent. Must be valid the clock cycle +-- that SEND has gone high. +-- CLK - A 100 MHz clock is expected +-- READY - This signal goes low once a send operation has begun and +-- remains low until it has completed and the module is ready to +-- send another byte. +-- UART_TX - This signal should be routed to the appropriate TX pin of the +-- external UART device. +-- +---------------------------------------------------------------------------- +-- +---------------------------------------------------------------------------- +-- Revision History: +-- 08/08/2011(SamB): Created using Xilinx Tools 13.2 +---------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_STD.All; +entity UART_TX_CTRL is + generic (ComRate : natural:=217); --vitesse de port serie pour 230400 Bauds @50 MHz + Port ( SEND : in STD_LOGIC; + DATA : in STD_LOGIC_VECTOR (7 downto 0); + CLK : in STD_LOGIC; + READY : out STD_LOGIC; + UART_TX : out STD_LOGIC); +end UART_TX_CTRL; + +architecture Behavioral of UART_TX_CTRL is + +type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT); + +--constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "00000011011001";--217 = (round(50MHz / 230 400)) - 1 +constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := std_logic_vector(to_unsigned(comrate,14)); +constant BIT_INDEX_MAX : natural := 10; + +--Counter that keeps track of the number of clock cycles the current bit has been held stable over the +--UART TX line. It is used to signal when the ne +signal bitTmr : std_logic_vector(13 downto 0) := (others => '0'); + +--combinatorial logic that goes high when bitTmr has counted to the proper value to ensure +--a 9600 baud rate +signal bitDone : std_logic; + +--Contains the index of the next bit in txData that needs to be transferred +signal bitIndex : natural; + +--a register that holds the current data being sent over the UART TX line +signal txBit : std_logic := '1'; + +--A register that contains the whole data packet to be sent, including start and stop bits. +signal txData : std_logic_vector(9 downto 0); + +signal txState : TX_STATE_TYPE := RDY; + +begin + +--Next state logic +next_txState_process : process (CLK) +begin + if (rising_edge(CLK)) then + case txState is + when RDY => + if (SEND = '1') then + txState <= LOAD_BIT; + end if; + when LOAD_BIT => + txState <= SEND_BIT; + when SEND_BIT => + if (bitDone = '1') then + if (bitIndex = BIT_INDEX_MAX) then + txState <= RDY; + else + txState <= LOAD_BIT; + end if; + end if; + when others=> --should never be reached + txState <= RDY; + end case; + end if; +end process; + +bit_timing_process : process (CLK) +begin + if (rising_edge(CLK)) then + if (txState = RDY) then + bitTmr <= (others => '0'); + else + if (bitDone = '1') then + bitTmr <= (others => '0'); + else + bitTmr <= bitTmr + 1; + end if; + end if; + end if; +end process; + +bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else + '0'; + +bit_counting_process : process (CLK) +begin + if (rising_edge(CLK)) then + if (txState = RDY) then + bitIndex <= 0; + elsif (txState = LOAD_BIT) then + bitIndex <= bitIndex + 1; + end if; + end if; +end process; + +tx_data_latch_process : process (CLK) +begin + if (rising_edge(CLK)) then + if (SEND = '1') then + txData <= '1' & DATA & '0'; + end if; + end if; +end process; + +tx_bit_process : process (CLK) +begin + if (rising_edge(CLK)) then + if (txState = RDY) then + txBit <= '1'; + elsif (txState = LOAD_BIT) then + txBit <= txData(bitIndex); + end if; + end if; +end process; + +UART_TX <= txBit; +READY <= '1' when (txState = RDY) else + '0'; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/com_icap.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/com_icap.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/com_icap.vhd (revision 142) @@ -0,0 +1,758 @@ +library ieee; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity com_icap is + generic ( hexmode : boolean := true; -- false is for faster binary mode, but will not work on all machines/boards + ComRate : integer := 217); -- ComRate = f_CLK / Boud_rate (e.g., 25 MHz/115200 Boud = 217) + port ( + CLK: in std_logic; + Rx: in std_logic; --entrée série des données + Tx: out std_logic; + RxErr: out std_logic; --erreur de réception + debug0: out std_logic_vector(19 downto 0); + debug1: out std_logic_vector(19 downto 0); + debug2: out std_logic_vector(19 downto 0); + bs_load_start : in std_logic; --début de réception bitstream + bs_load_comp : out std_logic; --fin de réception + bs_load_ack : in std_logic; --acquitement bistream + bs_load_data : out std_logic_vector(31 downto 0); + rxWord : out std_logic_vector(7 downto 0); -- mot reçu + RxRdy : out std_logic; --données reçues + WriteData: out std_logic_vector(31 downto 0); + ComActive: out std_logic; + WriteStrobe: out std_logic; --valide l'écriture sur l'ICAP + ReceiveLED: out std_logic); +end com_icap; + +architecture a_com_icap of com_icap is + +constant TimeToSendValue : integer := 16777216-1; --200000000; +constant CRC_InitValue : std_logic_vector(15 downto 0) := "1111111111111111"; +constant TestFileChecksum : std_logic_vector(19 downto 0) := x"40351"; --à changer en fonction du bitstream + +function ASCII2HEX(ASCII: std_logic_vector(7 downto 0)) return std_logic_vector is +begin + case ASCII is + when x"30" => return "00000"; -- 0 + when x"31" => return "00001"; + when x"32" => return "00010"; + when x"33" => return "00011"; + when x"34" => return "00100"; + when x"35" => return "00101"; + when x"36" => return "00110"; + when x"37" => return "00111"; + when x"38" => return "01000"; + when x"39" => return "01001"; + when x"41" => return "01010"; -- A + when x"61" => return "01010"; -- a + when x"42" => return "01011"; -- B + when x"62" => return "01011"; -- b + when x"43" => return "01100"; -- C + when x"63" => return "01100"; -- c + when x"44" => return "01101"; -- D + when x"64" => return "01101"; -- d + when x"45" => return "01110"; -- E + when x"65" => return "01110"; -- e + when x"46" => return "01111"; -- F + when x"66" => return "01111"; -- f + when others =>return "1----"; -- The MSB encodes if there was an unknown code -> error + end case; +end; + +type ReceiveStateType is (HighNibble, LowNibble); +signal ReceiveState : ReceiveStateType; +signal HighReg : std_logic_vector(3 downto 0); +signal HexValue : std_logic_vector(4 downto 0); -- a '0' MSB indicates a valid value on [3..0] +signal HexData : std_logic_vector(7 downto 0); -- the received byte in hexmode mode +signal HexWriteStrobe : std_logic; -- we received two hex nibles and have a result byte +signal Stop_Err,rec_ok :std_logic:='0'; +signal ComCount : integer range 0 to 4095; +signal ComTick : std_logic; +type ComStateType is (WaitForStartBit, DelayAfterStartBit, GetBit0, GetBit1, GetBit2, + GetBit3, GetBit4, GetBit5, GetBit6, GetBit7, GetStopBit); +type loadbs_Type is(idle,read_word0,read_word1,read_word2,read_word3,check_sync,reset_reg,write_icap,end_loadbs); +signal ComState,Next_ComState : ComStateType; +signal et_loadbs,Next_et_loadbs:loadbs_Type; +signal ReceivedWord,receivedSwap : std_logic_vector(7 downto 0); +signal RxLocal : std_logic; + +--signal W0, W1, W2, W3, W4, W5, W6, W7 : std_logic_vector(7 downto 0); + +signal ID_Reg : std_logic_vector(23 downto 0); +signal fifo_reg,fifo_reg_i : std_logic_vector(31 downto 0); --registre de détection de début du bitstream +signal sync_ok,desync_ok,cmd_detected:std_logic; +signal sync_ok_i,desync_ok_i,cmd_detected_i:std_logic; +signal reading : std_logic:='0'; +constant sync_reg : std_logic_vector(31 downto 0):=x"AA995566"; +constant desync_cmd : std_logic_vector(31 downto 0) :=x"30008001"; +constant desync_word : std_logic_vector(31 downto 0):=x"0000000D"; +signal Start_Reg : std_logic_vector(31 downto 0); +signal Size_Reg : std_logic_vector(31 downto 0); +signal CRC_Reg : std_logic_vector(15 downto 0); +signal Command_Reg : std_logic_vector(7 downto 0); +signal Data_Reg : std_logic_vector(7 downto 0); + +signal TimeToSend : std_logic; +signal TimeToSendCounter : integer range 0 to TimeToSendValue; + +type PresentType is (Idle, GetID_00, GetID_AA, GetID_FF, + GetSize3, GetSize2, GetSize1, GetSize0, + GetCommand, EvalCommand, + GetData, GetFinish); +signal PresentState : PresentType; + +signal scan_count : integer range 0 to 63; +constant tast_entprell : integer := 2000000; -- 100 ms; +signal tast_count : integer range 0 to tast_entprell; +signal tast_trigger, tast_trigger_delay : std_logic; + +signal feedback_mode : std_logic := '0'; +signal swap_mode : std_logic := '0'; + +signal LocalWriteStrobe : std_logic; + +signal local_scan_control, local_scan_control_delay : std_logic := '0'; +signal scan_shift_strobe_from_receiver : std_logic; +signal tx_write_strobe_from_receiver : std_logic; +signal tx_write_strobe : std_logic; + +signal state_counter : integer range 0 to 127 := 0; +signal com_en: std_logic; +signal com_en_counter : natural range 0 to 511; +signal com_active_counter : natural range 0 to 40000; +signal TxOut: std_logic; + +signal Word_Count : std_logic_vector(31 downto 0); +--signal ADR_Reg : std_logic_vector(31 downto 0); + +signal CRCReg,b_counter : std_logic_vector(19 downto 0) := TestFileChecksum; +signal ReceivedWordDebug : std_logic_vector(7 downto 0); +signal blink : std_logic_vector(22 downto 0) := (others => '0'); + +begin + +P_sync:process(clk) +begin + if clk'event AND clk='1' then + RxLocal <= Rx; + Tx <= TxOUT; + end if; -- clk; +end process; + +P_com_en:process(clk) +begin + if clk'event AND clk='1' then + if ComState=WaitForStartBit then + ComCount <= ComRate/2; -- @ 25 MHz --vérifier le demi-bit + ComTick <= '0'; + elsif ComCount=0 then + ComCount <= ComRate; + ComTick <= '1'; + else + ComCount <= ComCount - 1; + ComTick <= '0'; + end if; + end if; -- clk +end process; + +P_COM:process(clk) +begin + if clk'event AND clk='1' then + Rec_Ok<='0'; + case ComState is + when WaitForStartBit => + if RxLocal='0' then + ComState <= DelayAfterStartBit; + ReceivedWord <= (others => '0'); + ReceivedSwap<= (others => '0'); + Stop_Err<='0'; + end if; + when DelayAfterStartBit => + if ComTick='1' then + if rxLocal='0' then + ComState <= GetBit0; + Stop_Err<='0'; + else + Stop_Err<='1'; + ComState <=WaitForStartBit; --Erreur de stop trame incorrecte ! + end if; + end if; + when GetBit0 => + if ComTick='1' then + ComState <= GetBit1; + ReceivedWord(0) <= RxLocal; + ReceivedSwap(7) <= RxLocal; + end if; + when GetBit1 => + if ComTick='1' then + ComState <= GetBit2; + ReceivedWord(1) <= RxLocal; + ReceivedSwap(6) <= RxLocal; + end if; + when GetBit2 => + if ComTick='1' then + ComState <= GetBit3; + ReceivedWord(2) <= RxLocal; + ReceivedSwap(5) <= RxLocal; + end if; + when GetBit3 => + if ComTick='1' then + ComState <= GetBit4; + ReceivedWord(3) <= RxLocal; + ReceivedSwap(4) <= RxLocal; + end if; + when GetBit4 => + if ComTick='1' then + ComState <= GetBit5; + ReceivedWord(4) <= RxLocal; + ReceivedSwap(3) <= RxLocal; + end if; + when GetBit5 => + if ComTick='1' then + ComState <= GetBit6; + ReceivedWord(5) <= RxLocal; + ReceivedSwap(2) <= RxLocal; + end if; + when GetBit6 => + if ComTick='1' then + ComState <= GetBit7; + ReceivedWord(6) <= RxLocal; + ReceivedSwap(1) <= RxLocal; + end if; + when GetBit7 => + if ComTick='1' then + ComState <= GetStopBit; + ReceivedWord(7) <= RxLocal; + ReceivedSwap(0) <= RxLocal; + end if; + when GetStopBit => + if ComTick='1' then + ComState <= WaitForStartBit; + end if; + Rec_Ok<='1'; + end case; + end if; --clk +end process P_COM; + +--Get_header:process(comState,presentState,ReceivedWord,ComTick) +--begin +-- +-- if ComState=GetStopBit AND ComTick='1' then +-- case PresentState is +-- when GetID_00 => ID_Reg(23 downto 16) <= ReceivedWord; +-- when GetID_AA => ID_Reg(15 downto 8) <= ReceivedWord; +-- when GetID_FF => ID_Reg(7 downto 0) <= ReceivedWord; +-- when GetSize0 => Size_Reg(31 downto 24) <= ReceivedWord; +-- when GetSize1 => Size_Reg(23 downto 16) <= ReceivedWord; +-- when GetSize2 => Size_Reg(15 downto 8) <= ReceivedWord; +-- when GetSize3 => Size_Reg(7 downto 0) <= ReceivedWord; +---- when GetStart3 => Start_Reg(31 downto 24) <= ReceivedWord; +---- when GetStart2 => Start_Reg(23 downto 16) <= ReceivedWord; +---- when GetStart1 => Start_Reg(15 downto 8) <= ReceivedWord; +---- when GetStart0 => Start_Reg(7 downto 0) <= ReceivedWord; +---- when GetSize3 => Size_Reg(31 downto 24) <= ReceivedWord; +---- when GetSize2 => Size_Reg(23 downto 16) <= ReceivedWord; +---- when GetSize1 => Size_Reg(15 downto 8) <= ReceivedWord; +---- when GetSize0 => Size_Reg(7 downto 0) <= ReceivedWord; +---- when GetCRC_H => CRC_Reg(15 downto 8) <= ReceivedWord; +---- when GetCRC_L => CRC_Reg(7 downto 0) <= ReceivedWord; +-- when GetCommand => Command_Reg <= ReceivedWord; +-- when GetData => Data_Reg <= ReceivedWord; +-- when others => +-- end case; +-- end if; +--end process get_header ; + +--P_FSM:process(clk) +--begin +-- if clk'event AND clk='1' then +-- case PresentState is +-- when Idle => +-- if ComState=WaitForStartBit AND RxLocal='0' then PresentState <= GetID_00; end if; +-- when GetID_00 => +-- if TimeToSend='1' then PresentState<=Idle; +-- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetID_AA; end if; +-- when GetID_AA => +-- if TimeToSend='1' then PresentState<=Idle; +-- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetID_FF; end if; +-- when GetID_FF => +-- if TimeToSend='1' then PresentState<=Idle; +-- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetSize3; end if; +-- when GetSize3 => +-- if TimeToSend='1' then PresentState<=Idle; +-- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetSize2; end if; +-- when GetSize2 => +-- if TimeToSend='1' then PresentState<=Idle; +-- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetSize1; end if; +-- when GetSize1 => +-- if TimeToSend='1' then PresentState<=Idle; +-- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetSize0; end if; +-- when GetSize0 => +-- if TimeToSend='1' then PresentState<=Idle; +-- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetCommand; end if; +-- when GetCommand => +-- if TimeToSend='1' then PresentState<=Idle; +-- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= EvalCommand; end if; +-- when EvalCommand => +-- if ID_Reg=x"00AAFF" AND (Command_Reg=x"01" OR Command_Reg=x"02")then +-- PresentState <= GetData; +-- else +-- PresentState <= Idle; +-- end if; +-- when GetData => +-- if TimeToSend='1' then PresentState<=Idle; +-- elsif Word_Count=0 AND LocalWriteStrobe='1' then +-- PresentState <= GetFinish; +---- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetData2; +-- end if; +---- when GetData0 => +---- if TimeToSend='1' then PresentState<=Idle; +---- elsif ComState=GetStopBit AND ComTick='1' then +---- if Word_Count /= 0 then +---- PresentState <= GetData3; +---- else +---- PresentState <= GetFinish; +---- end if; +---- end if; +-- when GetFinish => +-- PresentState <= Idle; +-- end case; +-- end if;--clk +--end process; +--Command <= Command_Reg; + +--L_hexmode : if (hexmode=true) generate +-- +-- HexValue <= ASCII2HEX(ReceivedWord); +-- +-- process(clk) +-- begin +-- if CLK'event AND CLK='1' then +-- if PresentState/=GetData then +-- ReceiveState <= HighNibble; +-- elsif ComState=GetStopBit AND ComTick='1' AND HexValue(HexValue'high)='0' then +-- if(ReceiveState=HighNibble) then +-- ReceiveState <= LowNibble; +-- else +-- ReceiveState <= HighNibble; +-- end if; +-- end if; +-- end if; -- CLK +-- end process; +-- +-- process(clk) +-- begin +-- if CLK'event AND CLK='1' then +-- if ComState=GetStopBit AND ComTick='1' AND HexValue(HexValue'high)='0' then +-- if(ReceiveState=HighNibble) then +-- HighReg <= HexValue(3 downto 0); +-- HexWriteStrobe <= '0'; +-- else -- LowNibble +-- HexData <= HighReg & HexValue(3 downto 0); +-- HexWriteStrobe <= '1'; +-- end if; +-- else +-- HexWriteStrobe <= '0'; +-- end if; +-- end if; -- CLK +-- end process; +-- +--end generate; +debug0 <= CRCReg; +--debug1(7 downto 0) <= ID_Reg(15 downto 8); +--debug2(7 downto 0) <= ID_Reg(7 downto 0); +--debug0 <= CRCReg; +debug1(8 downto 0) <= Rec_ok & ReceivedWord ; +debug2 <= HexValue(3 downto 0) & ReceivedWordDebug & ReceivedWord ; + +--P_checksum:process(clk) +--begin +-- if clk'event AND clk='1' then +-- if PresentState=GetCommand then -- init before data arrives +-- CRCReg <= (others => '0'); +-- b_counter <= (others => '0'); +-- elsif hexmode=true then +-- if ComState=GetStopBit AND ComTick='1' AND HexValue(HexValue'high)='0' AND PresentState=GetData AND ReceiveState=LowNibble then +-- CRCReg <= CRCReg + (HighReg & HexValue(3 downto 0)); +-- b_counter <= b_counter +1; +-- end if; +-- else -- binary mode +-- if ComState=GetStopBit AND ComTick='1' AND (PresentState=GetData) then +-- CRCReg <= CRCReg + ReceivedWord; +-- b_counter <= b_counter +1; +-- end if; +-- end if; -- checksum computation +-- +-- if (PresentState=GetData) then +-- ReceiveLED <= '1'; -- receive process in progress +-- elsif (PresentState=Idle) and (CRCReg/=TestFileChecksum) then +-- ReceiveLED <= blink(blink'high); +-- else +-- ReceiveLED <= '0'; -- receive process was OK +-- end if; +-- +-- blink <= blink -1; +-- +-- end if; --clk +--end process; + +--P_bus:process(clk) +--begin +-- if clk'event AND clk='1' then +---- if PresentState=EvalCommand then +---- ADR_Reg <= Start_Reg; +---- elsif PresentState=GetData AND ComState=GetStopBit AND ComTick='1' then +---- ADR_Reg <= ADR_Reg + 1; +---- end if; +-- +---- if PresentState=EvalCommand then +---- Word_Count <= Size_Reg; +---- LocalWriteStrobe <= '0'; +---- elsif PresentState=GetData AND ComState=GetStopBit AND ComTick='1' AND Word_Count /= 0 then +---- Word_Count <= Word_Count - 1; +---- LocalWriteStrobe <= '1'; +---- else +---- Word_Count <= Word_Count; +---- LocalWriteStrobe <= '0'; +---- end if; +-- +-- if hexmode=false then +-- WriteStrobe <= LocalWriteStrobe ; -- delay Strobe to ensure that data is valid when applying clk +-- -- should further prevent glitches in ICAP clk +-- else +-- WriteStrobe <= HexWriteStrobe ; +-- end if; +-- +-- end if; -- clk +--end process; + +-- ComLoaderActive <= '0'; +--WriteData <= Data_Reg when (hexmode=false) else HexData; +ReceivedWordDebug <= Data_Reg when (hexmode=false) else HexData; +--ComActive <= '1' when (PresentState=GetData OR PresentState=GetFinish) else '0'; +ComActive <= '1' when (et_loadbs=read_word0 OR + et_loadbs=read_word1 or + et_loadbs=read_word2 or + et_loadbs=read_word3 or + et_loadbs=end_loadbs ) else '0'; +WriteStrobe <= LocalWriteStrobe; +--P_OutReg:process(clk) +--begin +-- if clk'event AND clk='1' then +-- if PresentState=GetFinish AND D_Reg=b"0000_0000_1010_1010_1111_1111" then +-- scan_shift_strobe_from_receiver <= '1'; +-- if W7(4)='1' then +-- tx_write_strobe_from_receiver <= '1'; +-- else +-- tx_write_strobe_from_receiver <= '0'; +-- end if; +-- else +-- scan_shift_strobe_from_receiver <= '0'; +-- tx_write_strobe_from_receiver <= '0'; +-- end if; -- new Package +-- end if; --clk +--end process; +-- +P_TimeOut:process(clk) +-- im Moment einmal dafür benutzt rauszufinden, ob ComState 'verhungert' und +-- damit die ganze Maschine stehen bleibt +begin + if clk'event AND clk='1' then +-- if (PresentState=Idle AND ComState=WaitForStartBit AND RxLocal='0') OR + if (et_loadbs=Idle) OR + ComState=GetStopBit then + -- Init TimeOut wenn neue Eingangs-Sequenz startet + -- oder wenn wieder ein Byte empfangen wurde + -- um missglückten Empfangsvorgang abzubrechen + TimeToSendCounter <= TimeToSendValue; + TimeToSend <= '0'; + elsif TimeToSendCounter>0 then + TimeToSendCounter <= TimeToSendCounter - 1; + TimeToSend <= '0'; + else + TimeToSendCounter <= TimeToSendCounter; + TimeToSend <= '1'; -- force FSM to go back to idle when inactive + end if; + end if; --clk +end process; +loadbs_sync:process(clk) +begin +if rising_edge(clk) then +et_loadbs<=next_et_loadbs; +fifo_reg<=fifo_reg_i; +sync_ok<=sync_ok_i; +desync_ok<=desync_ok_i; +cmd_detected<=cmd_detected_i; + blink <= blink -1; +end if; +end process; +--================================================================== +--**afectation des sorties de la MAE LAOD BITSTREAM +--================================================================== +next_loadbs:process(et_loadbs,fifo_reg,comstate,comtick,RxLocal, +cmd_detected,sync_ok,desync_ok,Timetosend,bs_load_start,bs_load_ack) +begin +next_et_loadbs<=et_loadbs; + +sync_ok_i<=sync_ok; +desync_ok_i<=desync_ok; +cmd_detected_i<=cmd_detected; +bs_load_comp<='0'; +case et_loadbs is +when idle => + + if ComState=WaitForStartBit AND RxLocal='0' and bs_load_start='1' then + next_et_loadbs <= check_sync; +sync_ok_i<='1'; + end if; +when check_sync=> + +if fifo_reg=sync_reg then +next_et_loadbs<=write_icap; +end if; +if TimeToSend='1' then -- false alerte ? + next_et_loadbs<=idle; + end if; + +when write_icap => + + +if fifo_reg=desync_word and cmd_detected='1' then +desync_ok_i<='1'; +cmd_detected_i<='1'; +elsif desync_ok='1' then + desync_ok_i<='1'; +cmd_detected_i<='1'; +elsif fifo_reg=desync_cmd then +cmd_detected_i<='1'; +desync_ok_i<='0'; +else +cmd_detected_i<='0'; +desync_ok_i<='0'; +end if; +next_et_loadbs<=reset_reg; +when reset_reg=> +next_et_loadbs<=read_word0; +when read_word0=> if ComState=GetStopBit AND ComTick='1' then + + next_et_loadbs<=read_word1; + end if; + if TimeToSend='1' then + next_et_loadbs<=end_loadbs; + end if; + when read_word1=> if ComState=GetStopBit AND ComTick='1' then + next_et_loadbs<=read_word2; + else + if TimeToSend='1' then + next_et_loadbs<=end_loadbs; + end if; + end if; + when read_word2=> if ComState=GetStopBit AND ComTick='1' then + next_et_loadbs<=read_word3; + else + if TimeToSend='1' then + next_et_loadbs<=end_loadbs; + end if; + end if; + when read_word3=> if ComState=GetStopBit AND ComTick='1' then + next_et_loadbs<=write_icap; + if TimeToSend='1' then + next_et_loadbs<=end_loadbs; + end if; + end if; + when end_loadbs=> + if bs_load_ack='1' then + next_et_loadbs<=Idle; + end if; + bs_load_comp<='1'; + end case; + +end process; +--========================================================== +--** +--========================================================== +val_loadbs:process(et_loadbs,receivedWord,Comstate,ComTick,fifo_reg,blink, +desync_ok) +begin +fifo_reg_i<=fifo_reg; +localwritestrobe<='0'; +case et_loadbs is +when idle => +ReceiveLED <= '0'; +when check_sync=> +ReceiveLED <= '0'; +if ComState=GetStopBit AND ComTick='1' then +fifo_reg_i(31 downto 8)<=fifo_reg(23 downto 0); +fifo_reg_i(7 downto 0)<=Receivedword; +end if; +when write_icap=> +localWritestrobe<='1'; +bs_load_data<=fifo_reg; +when reset_reg=> +fifo_reg_i<=(others=>'0'); --remise à zero du registre d'écriture +when read_word0=>fifo_reg_i(31 downto 24)<=ReceivedWord; +ReceiveLED <= '1'; +when read_word1=>fifo_reg_i(23 downto 16)<=ReceivedWord; +ReceiveLED <= '1'; +when read_word2=>fifo_reg_i(15 downto 8)<=ReceivedWord; +ReceiveLED <= '1'; +when read_word3=>fifo_reg_i(7 downto 0)<=ReceivedWord; +ReceiveLED <= '1'; +when end_loadbs=>fifo_reg_i<=(others=>'1'); +if desync_ok='0' then + ReceiveLED <= blink(blink'high); + else + ReceiveLED <= '0'; -- receive process was OK + end if; +end case; + + + +end process; +---------------------------------------------------------------------------------- +-- the Tx Send-Process + +--tx_write_strobe <= tx_write_strobe_from_receiver OR (tast_trigger AND (NOT tast_trigger_delay)); + +--P_com_en2:process(clk, com_en_counter) +--begin +-- +-- if clk'event AND clk='1' then +-- +-- +-- if (tx_write_strobe='1') OR (tx_write_strobe='0' AND com_en_counter = 0) then +-- com_en_counter <= 433; --433 @ 50 MHz ###### +-- else +-- com_en_counter <= com_en_counter - 1; +-- end if; +-- +-- end if; +-- +-- if com_en_counter = 0 then +-- com_en <= '1'; +-- else +-- com_en <= '0'; +-- end if; +--end process; +-- +--P_SendCounter:process(clk, com_en) +--begin +-- if clk'event AND clk='1' then +-- if tx_write_strobe='1' then -- send_to_com_strobe 10 Hz so we send new values 10 times a second +-- state_counter <= 80; +-- elsif state_counter>0 then +-- if com_en_counter=0 then +-- state_counter <= state_counter - 1 ; +-- end if; +-- else +-- state_counter <= state_counter ; +-- end if; +-- end if; -- clk +--end process; + +-- P_SendMux:process(state_counter, TxOut, clk) +-- begin +-- if clk'event AND clk='1' then +-- case state_counter is +-- when 80 => TxOut <= '0'; -- send start bit +-- when 79 => TxOut <= W0(0); +-- when 78 => TxOut <= W0(1); +-- when 77 => TxOut <= W0(2); +-- when 76 => TxOut <= W0(3); +-- when 75 => TxOut <= W0(4); +-- when 74 => TxOut <= W0(5); +-- when 73 => TxOut <= W0(6); +-- when 72 => TxOut <= W0(7); +-- when 71 => TxOut <= '1'; -- send stop bit +-- +-- when 70 => TxOut <= '0'; -- send start bit +-- when 69 => TxOut <= W1(0); +-- when 68 => TxOut <= W1(1); +-- when 67 => TxOut <= W1(2); +-- when 66 => TxOut <= W1(3); +-- when 65 => TxOut <= W1(4); +-- when 64 => TxOut <= W1(5); +-- when 63 => TxOut <= W1(6); +-- when 62 => TxOut <= W1(7); +-- when 61 => TxOut <= '1'; -- send stop bit +-- +-- when 60 => TxOut <= '0'; -- send start bit +-- when 59 => TxOut <= W2(0); +-- when 58 => TxOut <= W2(1); +-- when 57 => TxOut <= W2(2); +-- when 56 => TxOut <= W2(3); +-- when 55 => TxOut <= W2(4); +-- when 54 => TxOut <= W2(5); +-- when 53 => TxOut <= W2(6); +-- when 52 => TxOut <= W2(7); +-- when 51 => TxOut <= '1'; -- send stop bit +-- +-- when 50 => TxOut <= '0'; -- send start bit +-- when 49 => TxOut <= W3(0); +-- when 48 => TxOut <= W3(1); +-- when 47 => TxOut <= W3(2); +-- when 46 => TxOut <= W3(3); +-- when 45 => TxOut <= W3(4); +-- when 44 => TxOut <= W3(5); +-- when 43 => TxOut <= W3(6); +-- when 42 => TxOut <= W3(7); +-- when 41 => TxOut <= '1'; -- send stop bit +-- +-- when 40 => TxOut <= '0'; -- send start bit +-- when 39 => TxOut <= W4(0); +-- when 38 => TxOut <= W4(1); +-- when 37 => TxOut <= W4(2); +-- when 36 => TxOut <= W4(3); +-- when 35 => TxOut <= W4(4); +-- when 34 => TxOut <= W4(5); +-- when 33 => TxOut <= W4(6); +-- when 32 => TxOut <= W4(7); +-- when 31 => TxOut <= '1'; -- send stop bit +-- +-- when 30 => TxOut <= '0'; -- send start bit +-- when 29 => TxOut <= W5(0); +-- when 28 => TxOut <= W5(1); +-- when 27 => TxOut <= W5(2); +-- when 26 => TxOut <= W5(3); +-- when 25 => TxOut <= W5(4); +-- when 24 => TxOut <= W5(5); +-- when 23 => TxOut <= W5(6); +-- when 22 => TxOut <= W5(7); +-- when 21 => TxOut <= '1'; -- send stop bit +-- +-- when 20 => TxOut <= '0'; -- send start bit +-- when 19 => TxOut <= W6(0); +-- when 18 => TxOut <= W6(1); +-- when 17 => TxOut <= W6(2); +-- when 16 => TxOut <= W6(3); +-- when 15 => TxOut <= W6(4); +-- when 14 => TxOut <= W6(5); +-- when 13 => TxOut <= W6(6); +-- when 12 => TxOut <= W6(7); +-- when 11 => TxOut <= '1'; -- send stop bit +-- +-- when 10 => TxOut <= '0'; -- send start bit +-- when 9 => TxOut <= W7(0); +-- when 8 => TxOut <= '1'; -- finally the command ID sequence +-- when 7 => TxOut <= '1'; +-- when 6 => TxOut <= '0'; +-- when 5 => TxOut <= swap_mode; +-- when 4 => TxOut <= '0'; +-- when 3 => TxOut <= '1'; +-- when 2 => TxOut <= '1'; +-- +-- when others => TxOut <= '1'; -- send stop bit +-- end case; +-- end if; -- clk; +-- end process; +-- +TxOut<=Rx; +RxErr<=Stop_err; +end architecture; + + + + + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/fifo_256_fwft_tb.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/fifo_256_fwft_tb.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/fifo_256_fwft_tb.vhd (revision 142) @@ -0,0 +1,85 @@ +LIBRARY ieee ; +LIBRARY unisim ; +LIBRARY work ; +USE ieee.std_logic_1164.all ; +USE ieee.std_logic_arith.all ; +USE ieee.STD_LOGIC_UNSIGNED.all ; +USE unisim.VCOMPONENTS.all ; +USE work.CoreTypes.all ; +ENTITY fifo_256_fwft_tb IS +END ; + +ARCHITECTURE fifo_256_fwft_tb_arch OF fifo_256_fwft_tb IS + SIGNAL dout : std_logic_vector (7 downto 0) ; + SIGNAL srst : STD_LOGIC ; + SIGNAL rd_en : STD_LOGIC ; + SIGNAL clk : STD_LOGIC:='0' ; + SIGNAL full : STD_LOGIC ; + SIGNAL empty : STD_LOGIC ; + SIGNAL wr_en : STD_LOGIC ; + SIGNAL din : std_logic_vector (7 downto 0) ; + COMPONENT FIFO_256_FWFT + PORT ( + dout : out std_logic_vector (7 downto 0) ; + srst : in STD_LOGIC ; + rd_en : in STD_LOGIC ; + clk : in STD_LOGIC ; + full : out STD_LOGIC ; + empty : out STD_LOGIC ; + wr_en : in STD_LOGIC ; + din : in std_logic_vector (7 downto 0) ); + END COMPONENT ; +BEGIN + DUT : FIFO_256_FWFT + PORT MAP ( + dout => dout , + srst => srst , + rd_en => rd_en , + clk => clk , + full => full , + empty => empty , + wr_en => wr_en , + din => din ) ; + + + +clk <= not clk after 5 ns; +srst<='0','1' after 10 ns,'0' after 100 ns; + +input_data:process +begin + + wr_en<='0'; + wait for 10 ns; + srst<='0'; + wr_en<='1'; + for i in 0 to 10 loop + din<=conv_std_logic_vector(i,8); + wait for 10 ns; +end loop; + wr_en<='0'; + wait for 10 ns; + + for i in 11 to 20 loop + wr_en<='1'; + din<=conv_std_logic_vector(i,8); + wait for 10 ns; + wr_en<='0'; + wait for 10 ns; +end loop; + --wait; +end process; + +output_data:process(clk,empty) +begin + -- if rising_edge(clk) then + if empty='0' then + rd_en<='1'; +else + rd_en<='0'; +end if; + +--end if; +end process; + +end fifo_256_fwft_tb_arch; Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/image_pkg.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/image_pkg.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/image_pkg.vhd (revision 142) @@ -0,0 +1,134 @@ +---------------------------------------------------------------------------- +-- Copyright (c) 1996, Ben Cohen. All rights reserved. +-- This model can be used in conjunction with the Kluwer Academic books +-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0 +-- "VHDL Amswers to Frequently Asked Questions", ISBN 0-7923-9791-6 +-- Web page: http://members.aol.com/vhdlcohen/vhdl +-- email: vhdlcohen@aol.com +-- +-- This source file for the image package +-- may be used and distributed without restriction provided +-- that this copyright statement is not removed from the file +-- and that any derivative work contains this copyright notice. +------------------------------------------------------------------------------- +library IEEE; + use IEEE.Std_Logic_1164.all; + use IEEE.Std_Logic_TextIO.all; + use IEEE.Std_Logic_Arith.all; + +library Std; + use STD.TextIO.all; + +package Image_Pkg is + function Image(In_Image : Time) return String; + function Image(In_Image : Bit) return String; + function Image(In_Image : Bit_Vector) return String; + function Image(In_Image : Integer) return String; + function Image(In_Image : Real) return String; + function Image(In_Image : Std_uLogic) return String; + function Image(In_Image : Std_uLogic_Vector) return String; + function Image(In_Image : Std_Logic_Vector) return String; + function Image(In_Image : Signed) return String; + function Image(In_Image : UnSigned) return String; + +end Image_Pkg; + +package body Image_Pkg is + function Image(In_Image : Time) return String is + variable L : Line; -- access type + variable W : String(1 to 25) := (others => ' '); + -- Long enough to hold a time string + begin + -- the WRITE procedure creates an object with "NEW". + -- L is passed as an output of the procedure. + Std.TextIO.WRITE(L, in_image); + -- Copy L.all onto W + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Bit) return String is + variable L : Line; -- access type + variable W : String(1 to 3) := (others => ' '); + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Bit_Vector) return String is + variable L : Line; -- access type + variable W : String(1 to In_Image'length) := (others => ' '); + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Integer) return String is + variable L : Line; -- access type + variable W : String(1 to 32) := (others => ' '); + -- Long enough to hold a time string + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Real) return String is + variable L : Line; -- access type + variable W : String(1 to 32) := (others => ' '); + -- Long enough to hold a time string + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Std_uLogic) return String is + variable L : Line; -- access type + variable W : String(1 to 3) := (others => ' '); + begin + IEEE.Std_Logic_Textio.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Std_uLogic_Vector) return String is + variable L : Line; -- access type + variable W : String(1 to In_Image'length) := (others => ' '); + begin + IEEE.Std_Logic_Textio.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Std_Logic_Vector) return String is + variable L : Line; -- access type + variable W : String(1 to In_Image'length) := (others => ' '); + begin + IEEE.Std_Logic_TextIO.WRITE(L, In_Image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Signed) return String is + begin + return Image(Std_Logic_Vector(In_Image)); + end Image; + + function Image(In_Image : UnSigned) return String is + begin + return Image(Std_Logic_Vector(In_Image)); + end Image; + +end Image_Pkg; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/load_instr.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/load_instr.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/load_instr.vhd (revision 142) @@ -0,0 +1,372 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM NGOUNOU +-- +-- Create Date: 04:57:14 07/15/2012 +-- Design Name: +-- Module Name: load_instr - Behavioral +-- Project Name: MPI CORE +-- Target Devices: +-- Tool versions: +-- Description: Ce module permet de charger une instruction dans le FIFO 1 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +library NocLib; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; +use NocLib.CoreTypes.all; +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity load_instr is + Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : in STD_LOGIC; + + clk : in STD_LOGIC; + reset : in STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC:='0'; + instruction_ack : out STD_LOGIC:='0'; + fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_wr :out std_logic:='0'; + copying :out std_logic:='0'; + fifo_full : in STD_LOGIC; + ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0); + Ram_rd_en : out std_logic); +end load_instr; + +architecture Behavioral of load_instr is +--déclaration des types manipulés +type typ_loadinst is (init,setadr,readptr,getbus,readmem,freebus,st_timeout); +--déclaration des signaux +signal Ram_address_i,Ram_address_q:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); +--signal ptr, ptr_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); --pointeur vers l'instruction en RAM +signal Base_Adr , Base_Adr_i : STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); +signal adr_ptr : natural range 0 to 65536:=0; +signal Base_AdrSet : std_logic:='0' ; --indique l'adresse de base des instructions positionée +signal fifo_din_i,fifo_din_q:std_logic_vector(WORD-1 downto 0):=(others=>'-'); +signal iLen,iLen_i : natural range 0 to 15:=0; --longueur de l'instruction à copier dans le Fifo +signal fifo_wr_i,fifo_wr_q :std_logic:='0'; +signal rd_ok:std_logic:='0'; +signal base_adrset_i : std_logic:='0'; +signal ptr,ptr_i : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0'); +signal instruction_ack_i,instruction_ack_q :std_logic:='0'; +signal Dma_rd_request_i,Dma_rd_request_q :std_logic:='0'; +signal count,count_i : natural range 0 to 31:=0; --permet de faie évoluer la sous-MAE +signal etloadinst,next_loadinst : typ_loadinst; +signal timeout, timeout_i: natural range 0 to 255; +begin +SYNC_PROC: process (clk) + begin + if rising_edge(clk) then + if reset = '1' then + etloadinst <= init; + Base_adrSet<= '0'; + dma_rd_request_q<='0'; + instruction_ack_q<='0'; + count<=0; + Ilen<=0; + Base_adr<=x"0000"; + fifo_din_q<=(others=>'0'); + else + etloadinst <= next_loadinst; + fifo_din_q <= fifo_din_i; + Base_Adr<=Base_Adr_i; + Base_AdrSet<=Base_adrSet_i; + ptr<=ptr_i; + fifo_wr_q<=fifo_wr_i; + ram_address_q<=ram_address_i; + adr_ptr<=to_integer(to_01(unsigned(ram_address_i))); + dma_rd_request_q<=dma_rd_request_i; + instruction_ack_q<=instruction_ack_i; + count<=count_i; + Ilen<=Ilen_i; + Timeout<=timeout_i; + + + end if; + end if; + end process; + --***************************************** + -- assign other outputs to internal signals + fifo_wr<=fifo_wr_q; + instruction_ack<=instruction_ack_q; + dma_rd_request<=dma_rd_request_q; + Ram_address_rd<=Ram_address_q; + --************************************************************************* + OUTPUT_DECODE: process (etloadinst,fifo_din_q,Count_i,Ram_data,Dma_rd_grant, + Base_AdrSet,Dma_rd_request_q,instruction_ack_q,rd_ok) + variable Adr_inst1,adr_inst2 : natural; + begin + fifo_din_i <= fifo_din_q; + fifo_din<=fifo_din_q; + dma_rd_request_i<=dma_rd_request_q; + instruction_ack_i<=instruction_ack_q; + + --Base_AdrSet_i<=Base_adrSet; + case etloadinst is + when init => + Dma_rd_request_i<='0'; + --fifo_wr<='0'; + copying<='0'; + Ram_rd_en<='0'; + Instruction_ack_i<='0'; + fifo_din_i<=(others=>'-'); + --Base_AdrSet_i<='0'; + + when SetAdr => + Dma_rd_request_i<='0'; + Instruction_ack_i<='0'; + --fifo_wr<='0'; + copying<='0'; + Ram_rd_en<='0'; + + fifo_din_i<=(others=>'-'); + --Base_AdrSet_i<='1'; + + when getbus => + --fifo_wr<='0'; + copying<='1'; + Ram_rd_en<='0'; + Dma_rd_request_i<='1'; + Instruction_ack_i<='0'; + fifo_din_i<=(others=>'-'); + -- Base_AdrSet_i<='1'; + when readptr => + --fifo_wr<='0'; + + copying<='1'; + Ram_rd_en<=rd_ok; + Dma_rd_request_i<='1'; + Instruction_ack_i<='0'; + fifo_din_i<=(others=>'-'); + --Base_AdrSet_i<='1'; + when readmem => + Dma_rd_request_i<='1'; + copying<='1'; + Ram_rd_en<=rd_ok; + --fifo_wr<=fifo_wr_i; + fifo_din_i<=Ram_data; + fifo_din<=Ram_data; + --Base_AdrSet_i<='1'; + Instruction_ack_i<='0'; + + when freebus => + Dma_rd_request_i<='0'; + --fifo_wr<='0'; + copying<='0'; + Ram_rd_en<='0'; + Instruction_ack_i<='1'; + fifo_din_i<=(others=>'-'); + --Base_AdrSet_i<='1'; + when st_timeout => + Dma_rd_request_i<='0'; + -- fifo_wr<='0'; + copying<='0'; + Ram_rd_en<='0'; + Instruction_ack_i<='0'; + fifo_din_i<=(others=>'-'); + --Base_AdrSet_i<='1'; + end case; + end process; + + NEXT_STATE_DECODE: process (etloadinst, Ram_address_q,Base_AdrSet,Adr_Ptr,Ram_data,Instruction,instruction_en, + fifo_full,dma_rd_grant,count,Ilen,Base_adr,ptr,timeout,fifo_wr_q) + + --variable ptr : std_logic_vector(ADRLEN-1 downto 0); + + variable Base_AD,ADRtmp,iptr : natural range 0 to 65535; + begin + --declare default state for next_state to avoid latches + next_loadinst <= etloadinst; --default is to stay in current state + Ram_address_i<=Ram_address_q; + --Base_Adr_i<=Base_adr; + ptr_i<=ptr; + BASE_AD:=to_integer(to_01(unsigned(base_adr))); --pour éviter le latch + count_i<=count; + Ilen_i<=Ilen; + AdrTmp:=Adr_ptr; + timeout_i<=timeout; + rd_ok<='0'; + fifo_wr_i<=fifo_wr_q; + --below is a simple example + case (etloadinst) is + when init => if base_adrset='1' and Instruction_en='1' then + Ilen_i<=to_integer(unsigned(Instruction(3 downto 0)));--initialisation de longueur + next_loadinst<=getbus; + --elsif Instruction_en='1' then + -- next_loadinst<=Setadr; + --Base_Adr_i<=X"0000"; + else + next_loadinst<=init; + --Base_Adr_i<=X"0000"; + Ilen_i<=0; + end if; + fifo_wr_i<='0'; + count_i<=0; + + -- + When Setadr => if Base_adrSet='0' then + -- Base_Adr_i<=std_logic_vector(to_unsigned(Core_upper_adr,8)) & X"00"; --récupération des bits de poids forts de l'instruction + -- + end if; + next_loadinst<=init; + Ram_address_i<=(others=>'0'); + count_i<=0; + when getbus => + BASE_AD:=to_integer(to_01(unsigned(base_adr))); + if dma_rd_grant = '1' then + next_loadinst <= readptr; + + -- prépare la prochaine lecture + + else + + end if; + Ram_address_i<=(others=>'0'); + count_i<=0; + When readptr => + --s'assurer que le bus est disponible + + if count=0 then + + Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+2,16)); + if dma_rd_grant='1' then + count_i <=count+1; + end if; + elsif count=1 then-- attend que la donnée soit positionnée + if dma_rd_grant = '1' then + count_i <=count+1; + rd_ok<='1'; + + end if; + + elsif count=2 then + if dma_rd_grant = '1' then + count_i <=count+1; + ptr_i(Word-1 downto 0)<=Ram_data; + rd_ok<='1'; + else + count_i<=0; + end if; + Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16)); + + elsif count=3 then + Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16)); + if dma_rd_grant = '1' then + count_i <=count+1; + rd_ok<='1'; + ptr_i(Word-1 downto 0)<=Ram_data; + end if; + + elsif count=4 then + if dma_rd_grant = '1' then + ptr_i(15 downto 8)<=Ram_data; + count_i<=0; + timeout_i<=0; + next_loadinst <= readmem; + else + count_i<=3; + end if; + report "Readptr " & image(ptr); + else + + end if; + + if dma_rd_grant = '0' then + assert true report "Mauvaise lecture" severity failure; + timeout_i<=timeout+1; + end if; + when readmem => + if fifo_full='0' then + if ilen >0 then + if count=0 then + iptr:=to_integer(to_01(unsigned(ptr))); + AdrTmp:=iptr; + if dma_rd_grant = '1' then + count_i <=count+1; + fifo_wr_i<='0'; + end if; + elsif count=1 then + if dma_rd_grant = '1' then + count_i <=count+1; + fifo_wr_i<='0'; + rd_ok<='0'; + end if; + elsif count=2 then + if dma_rd_grant = '1' then + count_i <=count+1; + fifo_wr_i<='0'; + rd_ok<='1'; + else + count_i<=1; + end if; + elsif count=3 then + count_i <=count+1; + AdrTmp:=Adr_Ptr+1; + elsif count=4 then + fifo_wr_i<='1'; --écriture de la donnée dans le fifo + Ilen_i<=Ilen-1; + count_i<=1; + end if; + else --Ilen=0 ? + fifo_wr_i<='0'; + next_loadinst<=freebus; + end if; + end if; + + Ram_address_i<=STD_LOGIC_VECTOR(to_unsigned(AdrTmp,16)); + if dma_rd_grant = '0' or Fifo_full='1' then + timeout_i<=timeout+1; + fifo_wr_i<='0'; + Count_i<=1; --recommencer les cycles d'attente de la donnée + if timeout=200 then + next_loadinst<=st_timeout; + end if; + end if; + + when freebus => + fifo_wr_i<='0'; + count_i<=0; + Ram_address_i<=(others=>'0'); + if instruction_en='0' then + next_loadinst <= init; + end if; + when st_timeout => + fifo_wr_i<='0'; + Ram_address_i<=(others=>'0'); + next_loadinst<=init; + report "Copie D'instruction *** RAM/Fifo a été indisponible pour trop longtemps !!!"; + count_i<=0; + end case; + end process; +base_ad_proc:process(reset) +begin + + if reset = '1' then + Base_adrSet_i<='0'; + Base_Adr_i<=x"0000"; +else + Base_adrSet_i<='1'; + Base_Adr_i<=std_logic_vector(to_unsigned(Core_upper_adr,8)) & X"00"; --récupération des bits de poids forts de l'instruction + -- + +end if; + + +end process; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/load_instr.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/load_instr.vhd.bak (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/load_instr.vhd.bak (revision 142) @@ -0,0 +1,370 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM NGOUNOU +-- +-- Create Date: 04:57:14 07/15/2012 +-- Design Name: +-- Module Name: load_instr - Behavioral +-- Project Name: MPI CORE +-- Target Devices: +-- Tool versions: +-- Description: Ce module permet de charger une instruction dans le FIFO 1 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +library NocLib; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; +use NocLib.CoreTypes.all; +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity load_instr is + Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : in STD_LOGIC; + + clk : in STD_LOGIC; + reset : in STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC:='0'; + instruction_ack : out STD_LOGIC:='0'; + fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_wr :out std_logic:='0'; + copying :out std_logic:='0'; + fifo_full : in STD_LOGIC; + ram_address_rd : buffer STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0); + Ram_rd_en : out std_logic); +end load_instr; + +architecture Behavioral of load_instr is +--déclaration des types manipulés +type typ_loadinst is (init,setadr,readptr,getbus,readmem,freebus,st_timeout); +--déclaration des signaux +signal Ram_address_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); +--signal ptr, ptr_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); --pointeur vers l'instruction en RAM +signal Base_Adr , Base_Adr_i : STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); +signal adr_ptr : natural range 0 to 65536:=0; +signal Base_AdrSet : std_logic:='0' ; --indique l'adresse de base des instructions positionée +signal fifo_din_i,fifo_din_q:std_logic_vector(WORD-1 downto 0):=(others=>'-'); +signal iLen,iLen_i : natural range 0 to 15:=0; --longueur de l'instruction à copier dans le Fifo +signal fifo_wr_i,fifo_wr_q :std_logic:='0'; +signal rd_ok:std_logic:='0'; +signal base_adrset_i : std_logic:='0'; +signal ptr,ptr_i : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0'); +signal instruction_ack_i,instruction_ack_q :std_logic:='0'; +signal Dma_rd_request_i,Dma_rd_request_q :std_logic:='0'; +signal count,count_i : natural range 0 to 31:=0; --permet de faie évoluer la sous-MAE +signal etloadinst,next_loadinst : typ_loadinst; +signal timeout, timeout_i: natural range 0 to 255; +begin +SYNC_PROC: process (clk) + begin + if rising_edge(clk) then + if (reset = '1') or instruction_en='0' then + etloadinst <= init; + Base_adrSet<= '0'; + dma_rd_request_q<='0'; + instruction_ack_q<='0'; + count<=0; + Ilen<=0; + fifo_din_q<=(others=>'0'); + else + etloadinst <= next_loadinst; + fifo_din_q <= fifo_din_i; + Base_Adr<=Base_Adr_i; + Base_AdrSet<=Base_adrSet_i; + ptr<=ptr_i; + fifo_wr_q<=fifo_wr_i; + ram_address_rd<=ram_address_i; + adr_ptr<=to_integer(to_01(unsigned(ram_address_i))); + dma_rd_request_q<=dma_rd_request_i; + instruction_ack_q<=instruction_ack_i; + count<=count_i; + Ilen<=Ilen_i; + Timeout<=timeout_i; + + + end if; + end if; + end process; + --***************************************** + -- assign other outputs to internal signals + fifo_wr<=fifo_wr_q; + instruction_ack<=instruction_ack_q; + dma_rd_request<=dma_rd_request_q; + --************************************************************************* + OUTPUT_DECODE: process (etloadinst,fifo_din_q,Count_i,Ram_data,Dma_rd_grant, + Base_AdrSet,Dma_rd_request_q,instruction_ack_q,rd_ok) + variable Adr_inst1,adr_inst2 : natural; + begin + fifo_din_i <= fifo_din_q; + fifo_din<=fifo_din_q; + dma_rd_request_i<=dma_rd_request_q; + instruction_ack_i<=instruction_ack_q; + + --Base_AdrSet_i<=Base_adrSet; + case etloadinst is + when init => + Dma_rd_request_i<='0'; + --fifo_wr<='0'; + copying<='0'; + Ram_rd_en<='0'; + Instruction_ack_i<='0'; + fifo_din_i<=(others=>'-'); + --Base_AdrSet_i<='0'; + + when SetAdr => + Dma_rd_request_i<='0'; + Instruction_ack_i<='0'; + --fifo_wr<='0'; + copying<='0'; + Ram_rd_en<='0'; + + fifo_din_i<=(others=>'-'); + --Base_AdrSet_i<='1'; + + when getbus => + --fifo_wr<='0'; + copying<='1'; + Ram_rd_en<='0'; + Dma_rd_request_i<='1'; + Instruction_ack_i<='0'; + fifo_din_i<=(others=>'-'); + -- Base_AdrSet_i<='1'; + when readptr => + --fifo_wr<='0'; + + copying<='1'; + Ram_rd_en<=rd_ok; + Dma_rd_request_i<='1'; + Instruction_ack_i<='0'; + fifo_din_i<=(others=>'-'); + --Base_AdrSet_i<='1'; + when readmem => + Dma_rd_request_i<='1'; + copying<='1'; + Ram_rd_en<=rd_ok; + --fifo_wr<=fifo_wr_i; + fifo_din_i<=Ram_data; + fifo_din<=Ram_data; + --Base_AdrSet_i<='1'; + Instruction_ack_i<='0'; + + when freebus => + Dma_rd_request_i<='0'; + --fifo_wr<='0'; + copying<='0'; + Ram_rd_en<='0'; + Instruction_ack_i<='1'; + fifo_din_i<=(others=>'-'); + --Base_AdrSet_i<='1'; + when st_timeout => + Dma_rd_request_i<='0'; + -- fifo_wr<='0'; + copying<='0'; + Ram_rd_en<='0'; + Instruction_ack_i<='0'; + fifo_din_i<=(others=>'-'); + --Base_AdrSet_i<='1'; + end case; + end process; + + NEXT_STATE_DECODE: process (etloadinst, Ram_address_rd,Base_AdrSet,Adr_Ptr,Ram_data,Instruction,instruction_en, + fifo_full,dma_rd_grant,count,Ilen,Base_adr,timeout,fifo_wr_q) + + --variable ptr : std_logic_vector(ADRLEN-1 downto 0); + + variable Base_AD,ADRtmp,iptr : natural range 0 to 65535; + begin + --declare default state for next_state to avoid latches + next_loadinst <= etloadinst; --default is to stay in current state + Ram_address_i<=Ram_address_rd; + --Base_Adr_i<=Base_adr; + ptr_i<=ptr; + count_i<=count; + Ilen_i<=Ilen; + AdrTmp:=Adr_ptr; + timeout_i<=timeout; + rd_ok<='0'; + fifo_wr_i<=fifo_wr_q; + --below is a simple example + case (etloadinst) is + when init => if base_adrset='1' and Instruction_en='1' then + Ilen_i<=to_integer(unsigned(Instruction(3 downto 0)));--initialisation de longueur + next_loadinst<=getbus; + --elsif Instruction_en='1' then + -- next_loadinst<=Setadr; + --Base_Adr_i<=X"0000"; + else + next_loadinst<=init; + --Base_Adr_i<=X"0000"; + Ilen_i<=0; + end if; + fifo_wr_i<='0'; + count_i<=0; + + -- + When Setadr => if Base_adrSet='0' then + -- Base_Adr_i<=std_logic_vector(to_unsigned(Core_upper_adr,8)) & X"00"; --récupération des bits de poids forts de l'instruction + -- + end if; + next_loadinst<=init; + Ram_address_i<=(others=>'0'); + count_i<=0; + when getbus => + BASE_AD:=to_integer(to_01(unsigned(base_adr))); + if dma_rd_grant = '1' then + next_loadinst <= readptr; + + -- prépare la prochaine lecture + + else + + end if; + Ram_address_i<=(others=>'0'); + count_i<=0; + When readptr => + --s'assurer que le bus est disponible + + if count=0 then + + Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+2,16)); + if dma_rd_grant='1' then + count_i <=count+1; + end if; + elsif count=1 then-- attend que la donnée soit positionnée + if dma_rd_grant = '1' then + count_i <=count+1; + rd_ok<='1'; + + end if; + + elsif count=2 then + if dma_rd_grant = '1' then + count_i <=count+1; + ptr_i(Word-1 downto 0)<=Ram_data; + rd_ok<='1'; + else + count_i<=0; + end if; + Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16)); + + elsif count=3 then + Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16)); + if dma_rd_grant = '1' then + count_i <=count+1; + rd_ok<='1'; + ptr_i(Word-1 downto 0)<=Ram_data; + end if; + + elsif count=4 then + if dma_rd_grant = '1' then + ptr_i(15 downto 8)<=Ram_data; + count_i<=0; + timeout_i<=0; + next_loadinst <= readmem; + else + count_i<=3; + end if; + report "Readptr " & image(ptr); + else + + end if; + + if dma_rd_grant = '0' then + assert true report "Mauvaise lecture" severity failure; + timeout_i<=timeout+1; + end if; + when readmem => + if fifo_full='0' then + if ilen >0 then + if count=0 then + iptr:=to_integer(to_01(unsigned(ptr))); + AdrTmp:=iptr; + if dma_rd_grant = '1' then + count_i <=count+1; + fifo_wr_i<='0'; + end if; + elsif count=1 then + if dma_rd_grant = '1' then + count_i <=count+1; + fifo_wr_i<='0'; + rd_ok<='0'; + end if; + elsif count=2 then + if dma_rd_grant = '1' then + count_i <=count+1; + fifo_wr_i<='0'; + rd_ok<='1'; + else + count_i<=1; + end if; + elsif count=3 then + count_i <=count+1; + AdrTmp:=Adr_Ptr+1; + elsif count=4 then + fifo_wr_i<='1'; --écriture de la donnée dans le fifo + Ilen_i<=Ilen-1; + fifo_wr_i<='0'; + count_i<=1; + end if; + else --Ilen=0 ? + fifo_wr_i<='0'; + next_loadinst<=freebus; + end if; + end if; + + Ram_address_i<=STD_LOGIC_VECTOR(to_unsigned(AdrTmp,16)); + if dma_rd_grant = '0' or Fifo_full='1' then + timeout_i<=timeout+1; + fifo_wr_i<='0'; + Count_i<=1; --recommencer les cycles d'attente de la donnée + if timeout=200 then + next_loadinst<=st_timeout; + end if; + end if; + + when freebus => + fifo_wr_i<='0'; + count_i<=0; + Ram_address_i<=(others=>'0'); + if instruction_en='0' then + next_loadinst <= init; + end if; + when st_timeout => + fifo_wr_i<='0'; + Ram_address_i<=(others=>'0'); + next_loadinst<=init; + report "Copie D'instruction *** RAM/Fifo a été indisponible pour trop longtemps !!!"; + count_i<=0; + end case; + end process; +base_ad_proc:process(reset) +begin + + if reset = '1' then + Base_adrSet_i<='0'; + Base_Adr_i<=x"0000"; +else + Base_adrSet_i<='1'; + Base_Adr_i<=std_logic_vector(to_unsigned(Core_upper_adr,8)) & X"00"; --récupération des bits de poids forts de l'instruction + -- + +end if; + + +end process; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/mem2fifo.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/mem2fifo.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/mem2fifo.vhd (revision 142) @@ -0,0 +1,191 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 18:01:21 28/06/2014 +-- Design Name: +-- Module Name: Mem2fifo - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +Library NoCLib; +use NoCLib.CoreTypes.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity mem2fifo_a is --copy from memory to fifo + port ( + clk,reset : in std_logic; + copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo + snd_start : in std_logic; --début de la réception + snd_ack :in std_logic; -- acquittement de la réception + ram_busy :in std_logic; -- mémoire occupée + datalen : in std_logic_vector(Word-1 downto 0); --la longueur du paquet + ram_addr_start :in std_logic_vector(ADRLEN-1 downto 0); --addresse de début du bloc de donnée à copier + fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie + fifo_out_wr_en : out std_logic; --écriture autorisée dans la fifo de sortie + ram_in_rd_en : out std_logic; --lecture autorisée dans la fifo d'entrée + ram_in_data_out : in std_logic_vector(Word-1 downto 0); + ram_in_addr_rd :out std_logic_vector(ADRLEN-1 downto 0); --addresse de la donnée à copier + fifo_out_data_in : out std_logic_vector(Word-1 downto 0); + snd_comp : out std_logic); -- fin de la réception + +end mem2fifo_a; + +architecture Behavioral of mem2fifo_a is +type typ_send is (s_head,s_len,s_len2,s_data,s_pulse,s_end); + signal etsnd : typ_send; + signal snd_state,next_snd_state:natural range 0 to 7:=0; + signal p_len,p_len_i : natural range 0 to 255; + signal n,n_i:natural range 0 to 255; + signal wr_ok,rd_ok:std_logic:='0'; + signal wr_ok_i,rd_ok_i:std_logic:='0'; + signal sfifo_in,Data_to_send,Data_to_send_i : std_logic_vector(Word-1 downto 0); + signal spush : std_logic:='0'; + signal err : std_logic_vector(Word-1 downto 0):=(others =>'0'); +begin + +mem_copy_sync:process(clk,reset) + +begin + + + if reset='1' then + n<=0; + Snd_state<=0; + P_len<=0; + Data_to_send<=(others=>'0'); + wr_ok<='0'; + rd_ok<='0'; +else + if rising_edge(clk) then + Snd_state<=Next_Snd_state; + n<=n_i; + p_len<=P_len_i; + Data_to_send<=Data_to_send_i; + wr_ok<=wr_ok_i; + rd_ok<=rd_ok_i; +end if; +end if; +end process mem_copy_sync; + -- affectation concurentes +mem_copy_val:process (Snd_state,Etsnd,n,copy_mode,data_to_send,rd_ok,wr_ok,spush, +ram_addr_start) +begin + fifo_out_wr_en<='0'; + ram_in_rd_en<='0'; + fifo_out_data_in<=data_to_send; + ram_in_addr_rd<=std_logic_vector(to_unsigned(to_integer(unsigned(ram_addr_start)+n),ADRLEN)); + + if (Snd_state=1) or (snd_state=2) then + fifo_out_wr_en<=wr_ok; + ram_in_rd_en<=rd_ok; + fifo_out_data_in<=data_to_send; + ram_in_addr_rd<=std_logic_vector(to_unsigned(to_integer(unsigned(ram_addr_start)+n),ADRLEN)); + end if; + +end process mem_copy_val; + -- process qui envoie des données en provenance d'un Fifo vers un Fifo + mem_to_fifo:process(snd_state,copy_mode,snd_start,snd_ack, + fifo_out_full,ram_in_data_out,p_len,n,wr_ok,rd_ok,datalen,Data_to_send) + variable onepop:std_logic:='0'; + begin + Next_snd_state<=snd_state; --valeur par defaut + Data_To_Send_i<=Data_to_send; + wr_ok_i<=wr_ok; + rd_ok_i<=rd_ok; + n_i<=n; + p_len_i<=p_len; + snd_comp<='0'; + case snd_state is + + when 0 => wr_ok_i<='0';rd_ok_i<='0';onepop:='0'; + if snd_start='1' then + P_len_i<=to_integer(unsigned(datalen)); + next_snd_state<=1; + n_i<=0; + rd_ok_i<='1'; + end if; + + snd_comp<='0'; + when 1=> --placer la première donnée sur le bus + if copy_mode='1' then + + data_to_send_i <=ram_in_data_out ; + + else + data_to_send_i<=ram_in_data_out; + end if; + rd_ok_i<='1'; + next_snd_state<=2; + when 2=> if P_len > 0 then + if copy_mode='1' then + if onepop='0' then + data_to_send_i <=ram_in_data_out ; + rd_Ok_i<='1'; + onepop:='1'; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok_i<='0'; + end if; + else + onepop:='1';rd_ok_i<='1'; + data_to_send_i<=ram_in_data_out; + end if; + + if (fifo_out_full = '0') and onepop='1' then + -- if onepop='1' then + wr_ok_i<='1'; + onepop:='0'; + p_len_i<=p_len-1; + n_i<=n+1; --passer à l'octet suivant + else + wr_Ok_i<='0'; + end if; + else + rd_ok_i<='0'; + wr_ok_i<='0'; + next_snd_state<=3; + snd_comp<='0'; + end if; + when 3 => --fin de la copie + if snd_ack='1' then + + next_snd_state<=4; + end if; + wr_ok_i<='0';rd_ok_i<='0'; + snd_comp<='1'; + + when 4 =>if snd_start='0' then --ces deux étapes peuvent être combinées en une seule + next_snd_state<=0; + end if; + snd_comp<='0'; + +when others => next_snd_state<=0; + snd_comp<='0'; + rd_ok_i<='0'; + wr_ok_i<='0'; + data_to_send_i <=(others=>'U'); + end case; + end process mem_to_fifo; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/mem2fifo.vhd.bak =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/mem2fifo.vhd.bak (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/mem2fifo.vhd.bak (revision 142) @@ -0,0 +1,191 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 18:01:21 28/06/2014 +-- Design Name: +-- Module Name: Mem2fifo - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; +Library NoCLib; +use NoCLib.CoreTypes.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity mem2fifo_a is --copy from memory to fifo + port ( + clk,reset : in std_logic; + copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo + snd_start : in std_logic; --début de la réception + snd_ack :in std_logic; -- acquittement de la réception + ram_busy :in std_logic; -- mémoire occupée + datalen : in std_logic_vector(Word-1 downto 0); --la longueur du paquet + ram_addr_start :in std_logic_vector(ADRLEN-1 downto 0); --addresse de début du bloc de donnée à copier + fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie + fifo_out_wr_en : out std_logic; --écriture autorisée dans la fifo de sortie + ram_in_rd_en : out std_logic; --lecture autorisée dans la fifo d'entrée + ram_in_data_out : in std_logic_vector(Word-1 downto 0); + ram_in_addr_rd :out std_logic_vector(ADRLEN-1 downto 0); --addresse de la donnée à copier + fifo_out_data_in : out std_logic_vector(Word-1 downto 0); + snd_comp : out std_logic); -- fin de la réception + +end mem2fifo_a; + +architecture Behavioral of mem2fifo_a is +type typ_send is (s_head,s_len,s_len2,s_data,s_pulse,s_end); + signal etsnd : typ_send; + signal snd_state,next_snd_state:natural range 0 to 7:=0; + signal p_len,p_len_i : natural range 0 to 255; + signal n,n_i:natural range 0 to 255; + signal wr_ok,rd_ok:std_logic:='0'; + signal wr_ok_i,rd_ok_i:std_logic:='0'; + signal sfifo_in,Data_to_send,Data_to_send_i : std_logic_vector(Word-1 downto 0); + signal spush : std_logic:='0'; + signal err : std_logic_vector(Word-1 downto 0):=(others =>'0'); +begin + +mem_copy_sync:process(clk,reset) + +begin + + + if reset='1' then + n<=0; + Snd_state<=0; + P_len<=0; + Data_to_send<=(others=>'0'); + wr_ok<='0'; + rd_ok<='0'; +else + if rising_edge(clk) then + Snd_state<=Next_Snd_state; + n<=n_i; + p_len<=P_len_i; + Data_to_send<=Data_to_send_i; + wr_ok<=wr_ok_i; + rd_ok<=rd_ok_i; +end if; +end if; +end process mem_copy_sync; + -- affectation concurentes +mem_copy_val:process (Snd_state,Etsnd,n,copy_mode,data_to_send,rd_ok,wr_ok,spush, +ram_addr_start,data_to_send) +begin + fifo_out_wr_en<='0'; + ram_in_rd_en<='0'; + fifo_out_data_in<=data_to_send; + ram_in_addr_rd<=std_logic_vector(to_unsigned(to_integer(unsigned(ram_addr_start)+n),ADRLEN)); + + if (Snd_state=1) or (snd_state=2) then + fifo_out_wr_en<=wr_ok; + ram_in_rd_en<=rd_ok; + fifo_out_data_in<=data_to_send; + ram_in_addr_rd<=std_logic_vector(to_unsigned(to_integer(unsigned(ram_addr_start)+n),ADRLEN)); + end if; + +end process mem_copy_val; + -- process qui envoie des données en provenance d'un Fifo vers un Fifo + mem_to_fifo:process(snd_state,copy_mode,snd_start,snd_ack, + fifo_out_full,ram_in_data_out,p_len,n,wr_ok,rd_ok,datalen) + variable onepop:std_logic:='0'; + begin + Next_snd_state<=snd_state; --valeur par defaut + Data_To_Send_i<=Data_to_send; + wr_ok_i<=wr_ok; + rd_ok_i<=rd_ok; + n_i<=n; + p_len_i<=p_len; + snd_comp<='0'; + case snd_state is + + when 0 => wr_ok_i<='0';rd_ok_i<='0';onepop:='0'; + if snd_start='1' then + P_len_i<=to_integer(unsigned(datalen)); + next_snd_state<=1; + n_i<=0; + rd_ok_i<='1'; + end if; + + snd_comp<='0'; + when 1=> --placer la première donnée sur le bus + if copy_mode='1' then + + data_to_send_i <=ram_in_data_out ; + + else + data_to_send_i<=ram_in_data_out; + end if; + rd_ok_i<='1'; + next_snd_state<=2; + when 2=> if P_len > 0 then + if copy_mode='1' then + if onepop='0' then + data_to_send_i <=ram_in_data_out ; + rd_Ok_i<='1'; + onepop:='1'; --une donnée lue il faut arrêter de dépiler + + else + rd_Ok_i<='0'; + end if; + else + onepop:='1';rd_ok_i<='1'; + data_to_send_i<=ram_in_data_out; + end if; + + if (fifo_out_full = '0') and onepop='1' then + -- if onepop='1' then + wr_ok_i<='1'; + onepop:='0'; + p_len_i<=p_len-1; + n_i<=n+1; --passer à l'octet suivant + else + wr_Ok_i<='0'; + end if; + else + rd_ok_i<='0'; + wr_ok_i<='0'; + next_snd_state<=3; + snd_comp<='0'; + end if; + when 3 => --fin de la copie + if snd_ack='1' then + + next_snd_state<=4; + end if; + wr_ok_i<='0';rd_ok_i<='0'; + snd_comp<='1'; + + when 4 =>if snd_start='0' then --ces deux étapes peuvent être combinées en une seule + next_snd_state<=0; + end if; + snd_comp<='0'; + +when others => next_snd_state<=0; + snd_comp<='0'; + rd_ok_i<='0'; + wr_ok_i<='0'; + data_to_send_i <=(others=>'U'); + end case; + end process mem_to_fifo; + +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/round_robbin_machine.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/round_robbin_machine.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/round_robbin_machine.vhd (revision 142) @@ -0,0 +1,79 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:53:00 06/13/2011 +-- Design Name: +-- Module Name: round_robbin_machine - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity round_robbin_machine is + Port ( get_request_fifo_empty : in STD_LOGIC; + instruction_fifo_empty : in STD_LOGIC; + priority_rotation : in STD_LOGIC; + clk : in STD_LOGIC; + fifo_selected : out STD_LOGIC; + instruction_available : out STD_LOGIC; + reset : in STD_LOGIC; + mux_sel : out STD_LOGIC); +end round_robbin_machine; + +architecture Behavioral of round_robbin_machine is +signal priority : std_logic; +signal fifo_selected_signal : std_logic; + +begin +-- instruction disponible si au moins un fifo n'est pas vide +instruction_available <= '1' when instruction_fifo_empty = '0' or get_request_fifo_empty = '0' else + '0'; +--signal indiquant a EX1_FSM le fifo selectionne +fifo_selected <= fifo_selected_signal; +mux_sel <= fifo_selected_signal; + +rr_machine_process : process(clk) +begin + if rising_edge(clk) then + if reset = '1' then + priority <= '0'; + fifo_selected_signal <= '0'; + elsif priority_rotation = '1' then + if priority = '0' then + if instruction_fifo_empty = '0' then + fifo_selected_signal <= '0'; + elsif get_request_fifo_empty = '0' then + fifo_selected_signal <= '1'; + end if; + priority <= '1'; + else + if get_request_fifo_empty = '0' then + fifo_selected_signal <= '1'; + elsif instruction_fifo_empty = '0' then + fifo_selected_signal <= '0'; + end if; + priority <= '0'; + end if; + end if; + end if; + end process; +end Behavioral; + Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/sim_fifo.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/sim_fifo.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/sim_fifo.vhd (revision 142) @@ -0,0 +1,185 @@ +-- TestBench Template +-- ce module permet de tester le FIFO et de valider son fonctionnement. + LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE ieee.numeric_std.ALL; + Library NocLib ; + use NocLib.CoreTypes.all; + ENTITY testbench IS + END testbench; + + ARCHITECTURE behavior OF testbench IS +constant clk_period : time := 10 ns; +constant MSIZE :natural :=256; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + -- Component Declaration + +component FIFO_256_FWFT --Le FIFO à tester + port ( + clk: IN std_logic; + din: IN std_logic_VECTOR(7 downto 0); + rd_en: IN std_logic; + srst: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(7 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +end component; +component proto_receiv -- permet de tester la lecture dans le FIFO +generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_empty,fifo_full : in std_logic; + pop : out std_logic:='0'; + fifo_out : in std_logic_vector(Word-1 downto 0); + rcv_start : in std_logic; --début de la réception + rcv_ack :in std_logic; -- acquittement de la réception + rcv_comp : out std_logic; -- fin de la réception + mem :out memory(0 to sizemem-1)); +end component; + +component proto_send +generic (sizemem : natural := 64); + port ( + clk,reset : in std_logic; + fifo_empty,fifo_full : in std_logic; + push : out std_logic:='0'; + fifo_in : out std_logic_vector(Word-1 downto 0); + snd_start : in std_logic; --début de l'emission + snd_ack :in std_logic; -- acquittement de l'émission + snd_comp : out std_logic; -- fin de l'émission + mem :in memory(0 to sizemem-1)); + + end component; + +type typ_snd_rec is ( fillmem,send1, send2, recv1,recv2); +type typ_receiv is (r_wait,r_head,r_dlen,r_glen,r_start,r_end); + signal storage1,storage2 : memory (0 to MSIZE-1); + SIGNAL fifo_empty,fifo_full : std_logic:='0'; + signal push,pop ,spush,spop: std_logic:='0'; + SIGNAL data_in,data_out: std_logic_vector(7 downto 0); + signal ROn,Rdone,RAck:std_logic:='0'; + signal SOn,Sdone,SAck:std_logic:='0'; + signal etreceiv :typ_receiv; + + signal pipo : typ_snd_rec; + + BEGIN + + + +uut : FIFO_256_FWFT + port map ( + clk => clk, + din => data_in, + rd_en => pop, + srst => reset, + wr_en => push, + dout => data_out, + empty => fifo_empty, + full => fifo_full); + +rec_pro: proto_receiv generic map(sizemem =>MSIZE) + port map (clk=>clk, + reset=>reset, + fifo_empty=>fifo_empty, + fifo_full=>fifo_full, + rcv_start =>Ron, + rcv_ack => Rack, + rcv_comp=> Rdone, + pop=>pop, + fifo_out =>data_out, + mem=>storage2 + ); +snd_pro: proto_send generic map (sizemem =>MSIZE) +port map (clk=>clk, + reset=>reset, + fifo_empty=>fifo_empty, + fifo_full=>fifo_full, + snd_start =>Son, + snd_ack => Sack, + snd_comp=> Sdone, + push=>push, + fifo_in =>data_in, + mem=>storage1 + ); + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + + end process; +reset_proc: process + begin + -- hold reset state for 100 ns. + reset<='0'; + wait for 1 ns; + reset<='1'; + wait for clk_period*10; + reset<='0'; + wait; + -- insert stimulus here +end process; +pr_pingpong : process(clk,reset) +variable i: natural range 0 to MSIZE-1; +begin +if reset='1' then + pipo<=fillmem; + i:=0; + else + if rising_edge(clk) then + case pipo is + when fillmem => -- remplissage de la mémoire d'envoie + if i=0 then + storage1(0)<=x"51"; -- le code de la fonction + elsif i=1 then + storage1(1)<=x"05"; -- le nombre d'octets à envoyer dans le tampon. + elsif (i>=2) and (i<= MSIZE-2) then + storage1(i)<=std_logic_vector(to_unsigned(i-2,Word)); + + else + pipo<=send1; + i:=0; + end if; + i:=i+1; + when send1 => + + Son<='1'; --activer l'emission des données + Sack<='0'; + if i=2 then --activer la réception des données + Ron<='1'; + else + Ron<='0'; + i:=i+1; + end if; + if sdone='1' then + pipo<=send2; + + end if; + when send2 => + i:=0; + Son<='0'; + Sack<='1'; + pipo<=recv1; + when recv1 => + ron<='1'; + rack<='0'; + if Rdone='1' then + pipo<=recv2; + end if; + when recv2 => + Ron<='0'; + Rack<='1'; + pipo<=send1; + i:=0; + end case; + + + end if; +end if; +end process; + +END; Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/spi_ctrl.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/spi_ctrl.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/spi_ctrl.vhd (revision 142) @@ -0,0 +1,630 @@ +-- +-- Copyright (C) 2006 Johannes Hausensteiner (johannes.hausensteiner@pcl.at) +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License +-- as published by the Free Software Foundation; either version 2 +-- of the License, or (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +-- +-- +-- Filename: spi_ctrl.vhd +-- +-- Function: SPI Flash controller for DIY Calculator +-- +-- +-- Changelog +-- +-- 0.1 25.Sep.2006 JH new +-- 0.2 15.Nov.2006 JH remove old code +-- 1.0 5.Feb.2007 JH new clocking scheme +-- 1.1 4.Apr.2007 JH implement high address byte +-- 1.2 16.Apr.2007 JH clock enable +-- 1.3 23.Apr.2007 JH remove all asynchronous elements +-- 1.4 4.May 2007 JH resolve read timing +-- 1.5 10.May 2007 JH remove read signal +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity spi_ctrl is + port ( + clk_in : in std_logic; + rst : in std_logic; + spi_clk : out std_logic; + spi_cs : out std_logic; + spi_din : in std_logic; + spi_dout : out std_logic; + sel : in std_logic; + wr : in std_logic; + addr : in std_logic_vector (2 downto 0); + d_in : in std_logic_vector (7 downto 0); + d_out : out std_logic_vector (7 downto 0) + ); +end spi_ctrl; + +architecture rtl of spi_ctrl is + -- clock generator + constant SYS_FREQ : integer := 25000000; -- 25MHz + constant SPI_FREQ : integer := 6250000; -- 6.25MHz + signal clk_en : std_logic; + signal clk_cnt : integer range 0 to (SYS_FREQ/SPI_FREQ)-1; + + type state_t is ( + IDLE, TxCMD, TxADD_H, TxADD_M, TxADD_L, TxDUMMY, TxDATA, RxDATA, + WAIT1, WAIT2, WAIT3, WAIT4, WAIT6, WAIT5, WAIT7, WAIT8, CLR_CMD); + signal state, next_state : state_t; + + -- transmitter + signal tx_reg, tx_sreg : std_logic_vector (7 downto 0); + signal tx_empty, tx_empty_set : std_logic; + signal tx_bit_cnt : std_logic_vector (3 downto 0); + + -- receiver + signal rx_sreg : std_logic_vector (7 downto 0); + signal rx_ready, rx_ready_set, rx_bit_cnt_clr : std_logic; + signal rx_bit_cnt : std_logic_vector (3 downto 0); + + signal wr_cmd, wr_data, wr_add_h, wr_add_m, wr_add_l : std_logic; + signal rd_stat, rd_add_h, rd_add_m, rd_add_l : std_logic; + signal rd_data, rd_data1, rd_data2 : std_logic; + signal spi_cs_int, spi_clk_int : std_logic; + + -- auxiliary signals + signal rx_enable, rx_empty, rx_empty_clr : std_logic; + signal tx_enable, tx_enable_d : std_logic; + signal tx_new_data, tx_new_data_clr, is_tx_data, is_wait6 : std_logic; + signal cmd_clr, busy : std_logic; + + -- registers + signal cmd, tx_data, rx_data : std_logic_vector (7 downto 0); + signal add_h, add_m, add_l : std_logic_vector (7 downto 0); + + -- FLASH commands + constant NOP : std_logic_vector (7 downto 0) := x"FF"; -- no cmd to execute + constant WREN : std_logic_vector (7 downto 0) := x"06"; -- write enable + constant WRDI : std_logic_vector (7 downto 0) := x"04"; -- write disable + constant RDSR : std_logic_vector (7 downto 0) := x"05"; -- read status reg + constant WRSR : std_logic_vector (7 downto 0) := x"01"; -- write stat. reg + constant RDCMD: std_logic_vector (7 downto 0) := x"03"; -- read data + constant F_RD : std_logic_vector (7 downto 0) := x"0B"; -- fast read data + constant PP : std_logic_vector (7 downto 0) := x"02"; -- page program + constant SE : std_logic_vector (7 downto 0) := x"D8"; -- sector erase + constant BE : std_logic_vector (7 downto 0) := x"C7"; -- bulk erase + constant DP : std_logic_vector (7 downto 0) := x"B9"; -- deep power down + constant RES : std_logic_vector (7 downto 0) := x"AB"; -- read signature +begin + -- assign signals + spi_cs <= spi_cs_int; + spi_clk <= spi_clk_int; + spi_dout <= tx_sreg(7); + + -- clock generator + spi_divider : process (rst, clk_in) + begin + if rst = '1' then + clk_cnt <= 0; + clk_en <= '0'; + spi_clk_int <= '1'; + elsif falling_edge (clk_in) then + if clk_cnt = ((SYS_FREQ / SPI_FREQ) - 2) or + clk_cnt = ((SYS_FREQ / SPI_FREQ) - 3) then + clk_cnt <= clk_cnt + 1; + clk_en <= '0'; + if tx_enable = '1' or rx_enable = '1' then + spi_clk_int <= '0'; + else + spi_clk_int <= '1'; + end if; + elsif clk_cnt = ((SYS_FREQ / SPI_FREQ) - 1) then + clk_cnt <= 0; + clk_en <= '1'; + spi_clk_int <= '1'; + else + clk_cnt <= clk_cnt + 1; + clk_en <= '0'; + spi_clk_int <= '1'; + end if; + end if; + end process; + + -- address decoder + process (sel, addr, wr) + variable input : std_logic_vector (4 downto 0); + begin + input := sel & addr & wr; + -- defaults + wr_data <= '0'; + wr_cmd <= '0'; + wr_add_h <= '0'; + wr_add_m <= '0'; + wr_add_l <= '0'; + rd_data <= '0'; + rd_stat <= '0'; + rd_add_h <= '0'; + rd_add_m <= '0'; + rd_add_l <= '0'; + case input is + when "10000" => rd_data <= '1'; + when "10001" => wr_data <= '1'; + when "10010" => rd_stat <= '1'; + when "10011" => wr_cmd <= '1'; + when "10100" => rd_add_l <= '1'; + when "10101" => wr_add_l <= '1'; + when "10110" => rd_add_m <= '1'; + when "10111" => wr_add_m <= '1'; + when "11000" => rd_add_h <= '1'; + when "11001" => wr_add_h <= '1'; + when others => null; + end case; + end process; + + -- read back registers + d_out(0) <= (rx_data(0) and rd_data) + or (busy and rd_stat) + or (add_h(0) and rd_add_h) + or (add_m(0) and rd_add_m) + or (add_l(0) and rd_add_l); + + d_out(1) <= (rx_data(1) and rd_data) + or (tx_empty and rd_stat) + or (add_h(1) and rd_add_h) + or (add_m(1) and rd_add_m) + or (add_l(1) and rd_add_l); + + d_out(2) <= (rx_data(2) and rd_data) + or (rx_ready and rd_stat) + or (add_h(2) and rd_add_h) + or (add_m(2) and rd_add_m) + or (add_l(2) and rd_add_l); + + d_out(3) <= (rx_data(3) and rd_data) + or (is_wait6 and rd_stat) + or (add_h(3) and rd_add_h) + or (add_m(3) and rd_add_m) + or (add_l(3) and rd_add_l); + + d_out(4) <= (rx_data(4) and rd_data) + or ('0' and rd_stat) + or (add_h(4) and rd_add_h) + or (add_m(4) and rd_add_m) + or (add_l(4) and rd_add_l); + + d_out(5) <= (rx_data(5) and rd_data) + or ('0' and rd_stat) + or (add_h(5) and rd_add_h) + or (add_m(5) and rd_add_m) + or (add_l(5) and rd_add_l); + + d_out(6) <= (rx_data(6) and rd_data) + or ('0' and rd_stat) + or (add_h(6) and rd_add_h) + or (add_m(6) and rd_add_m) + or (add_l(6) and rd_add_l); + + d_out(7) <= (rx_data(7) and rd_data) + or ('0' and rd_stat) + or (add_h(7) and rd_add_h) + or (add_m(7) and rd_add_m) + or (add_l(7) and rd_add_l); + + -- write command register + process (rst, cmd_clr, clk_in) + begin + if rst = '1' or cmd_clr = '1' then + cmd <= NOP; + elsif rising_edge (clk_in) then + if wr_cmd = '1' then + cmd <= d_in; + end if; + end if; + end process; + + -- write address high register + process (rst, clk_in) + begin + if rst = '1' then + add_h <= x"00"; + elsif rising_edge (clk_in) then + if wr_add_h = '1' then + add_h <= d_in; + end if; + end if; + end process; + + -- write address mid register + process (rst, clk_in) + begin + if rst = '1' then + add_m <= x"00"; + elsif rising_edge (clk_in) then + if wr_add_m ='1' then + add_m <= d_in; + end if; + end if; + end process; + + -- write address low register + process (rst, clk_in) + begin + if rst = '1' then + add_l <= x"00"; + elsif rising_edge (clk_in) then + if wr_add_l ='1' then + add_l <= d_in; + end if; + end if; + end process; + + -- write tx data register + process (rst, clk_in) + begin + if rst = '1' then + tx_data <= x"00"; + elsif rising_edge (clk_in) then + if wr_data = '1' then + tx_data <= d_in; + end if; + end if; + end process; + + -- new tx data flag + tx_new_data_clr <= tx_empty_set and is_tx_data; + process (rst, tx_new_data_clr, clk_in) + begin + if rst = '1' or tx_new_data_clr = '1' then + tx_new_data <= '0'; + elsif rising_edge (clk_in) then + if wr_data ='1' then + tx_new_data <= '1'; + end if; + end if; + end process; + + -- advance the state machine + process (rst, clk_in) + begin + if rst = '1' then + state <= IDLE; + elsif rising_edge (clk_in) then + if clk_en = '1' then + state <= next_state; + end if; + end if; + end process; + + -- state machine transition table + process (state, cmd, tx_bit_cnt, tx_new_data, rx_bit_cnt, rx_empty) + begin + case state is + when IDLE => + case cmd is + when NOP => next_state <= IDLE; + when others => next_state <= TxCMD; + end case; + + when TxCMD => + if tx_bit_cnt < x"7" then + next_state <= TxCMD; + else + case cmd is + when WREN | WRDI | BE | DP => next_state <= CLR_CMD; + when SE | PP | RES | RDCMD | F_RD|WRSR|RDSR => next_state <= WAIT1; + when others => next_state <= CLR_CMD; + end case; + end if; + + when WAIT1 => + case cmd is + when WREN | WRDI | BE | DP => next_state <= CLR_CMD; + when SE | PP | RES | RDCMD | F_RD => next_state <= TxADD_H; + when WRSR => next_state <= TxDATA; + when RDSR => next_state <= RxDATA; + when others => next_state <= CLR_CMD; + end case; + + when TxADD_H => + if tx_bit_cnt < x"7" then + next_state <= TxADD_H; + else + next_state <= WAIT2; + end if; + + when WAIT2 => next_state <= TxADD_M; + + when TxADD_M => + if tx_bit_cnt < x"7" then + next_state <= TxADD_M; + else + next_state <= WAIT3; + end if; + + when WAIT3 => next_state <= TxADD_L; + + when TxADD_L => + if tx_bit_cnt < x"7" then + next_state <= TxADD_L; + else + case cmd is + when PP => next_state <= WAIT6; + when SE | RES | RDCMD | F_RD => next_state <= WAIT4; + when others => next_state <= CLR_CMD; + end case; + end if; + + when WAIT4 => + case cmd is + when F_RD => next_state <= TxDUMMY; + when RES | RDCMD => next_state <= RxDATA; + when others => next_state <= CLR_CMD; + end case; + + when TxDUMMY => + if tx_bit_cnt < x"7" then + next_state <= TxDUMMY; + else + next_state <= WAIT8; + end if; + + when WAIT7 => next_state <= WAIT8; + + when WAIT8 => + case cmd is + when RDCMD | F_RD => + if rx_empty = '1' then + next_state <= RxDATA; + else + next_state <= WAIT8; + end if; + when others => next_state <= CLR_CMD; + end case; + + when RxDATA => + if rx_bit_cnt < x"7" then + next_state <= RxDATA; + else + case cmd is + when RDCMD | F_RD => next_state <= WAIT7; + when RDSR | RES => next_state <= WAIT5; + when others => next_state <= CLR_CMD; + end case; + end if; + + when TxDATA => + if tx_bit_cnt < x"7" then + next_state <= TxDATA; + else + case cmd is + when PP => next_state <= WAIT6; + when others => next_state <= CLR_CMD; + end case; + end if; + + when WAIT6 => + case cmd is + when PP => + if tx_new_data = '1' then + next_state <= TxDATA; + else + next_state <= WAIT6; + end if; + when others => next_state <= CLR_CMD; + end case; + + when WAIT5 => next_state <= CLR_CMD; + + when CLR_CMD => next_state <= IDLE; + end case; + end process; + + -- state machine output table + process (state, cmd, tx_data, add_m, add_l, add_h) + begin + -- default values + tx_enable <= '0'; + rx_enable <= '0'; + rx_bit_cnt_clr <= '1'; + tx_reg <= x"FF"; + spi_cs_int <= '0'; + busy <= '1'; + cmd_clr <= '0'; + is_tx_data <= '0'; + is_wait6 <= '0'; + + case state is + when IDLE => + busy <= '0'; + when TxCMD => + tx_reg <= cmd; + tx_enable <= '1'; + spi_cs_int <= '1'; + when TxDATA => + tx_reg <= tx_data; + tx_enable <= '1'; + spi_cs_int <= '1'; + is_tx_data <= '1'; + when TxADD_H => + tx_reg <= add_h; + tx_enable <= '1'; + spi_cs_int <= '1'; + when TxADD_M => + tx_reg <= add_m; + tx_enable <= '1'; + spi_cs_int <= '1'; + when TxADD_L => + tx_reg <= add_l; + tx_enable <= '1'; + spi_cs_int <= '1'; + when TxDUMMY => + tx_reg <= x"00"; + tx_enable <= '1'; + spi_cs_int <= '1'; + when RxDATA => + rx_bit_cnt_clr <= '0'; + rx_enable <= '1'; + spi_cs_int <= '1'; + when WAIT1 | WAIT2 | WAIT3 | WAIT4 | WAIT8 => + spi_cs_int <= '1'; + when WAIT6 => + is_wait6 <= '1'; + spi_cs_int <= '1'; + when WAIT5 | WAIT7 => + rx_bit_cnt_clr <= '0'; + spi_cs_int <= '1'; + when CLR_CMD => + cmd_clr <= '1'; + when others => null; + end case; + end process; + + -- the tx_empty flip flop + process (rst, wr_data, clk_in) + begin + if rst = '1' then + tx_empty <= '1'; + elsif wr_data = '1' then + tx_empty <= '0'; + elsif rising_edge (clk_in) then + if tx_empty_set = '1' then + tx_empty <= '1'; + end if; + end if; + end process; + + -- delay the tx_enable signal + process (rst, clk_in) + begin + if rst = '1' then + tx_enable_d <= '0'; + elsif rising_edge (clk_in) then + tx_enable_d <= tx_enable; + end if; + end process; + + -- transmitter shift register and bit counter + process (rst, tx_reg, tx_enable_d, clk_in) + begin + if rst = '1' then + tx_sreg <= x"FF"; + tx_bit_cnt <= x"0"; + tx_empty_set <= '0'; + elsif tx_enable_d = '0' then + tx_sreg <= tx_reg; + tx_bit_cnt <= x"0"; + tx_empty_set <= '0'; + elsif rising_edge (clk_in) then + if clk_en = '1' then + tx_bit_cnt <= tx_bit_cnt + 1; + tx_sreg <= tx_sreg (6 downto 0) & '1'; + if tx_bit_cnt = x"6" and is_tx_data = '1' then + tx_empty_set <= '1'; + else + tx_empty_set <= '0'; + end if; + end if; + end if; + end process; + + -- synchronize rd_data + process (rst, clk_in) + begin + if rst = '1' then + rd_data1 <= '0'; + elsif falling_edge (clk_in) then + rd_data1 <= rd_data; + end if; + end process; + + process (rst, clk_in) + begin + if rst = '1' then + rd_data2 <= '0'; + elsif falling_edge (clk_in) then + if rd_data = '0' then + rd_data2 <= rd_data1; + end if; + end if; + end process; + + -- the rx_empty flip flop + process (rst, clk_in) + begin + if rst = '1' then + rx_empty <= '1'; + elsif rising_edge (clk_in) then + if rx_empty_clr = '1' then + rx_empty <= '0'; + elsif rd_data2 = '1' then + rx_empty <= '1'; + end if; + end if; + end process; + + -- the rx_ready flip flop + process (rst, clk_in) + begin + if rst = '1' then + rx_ready <= '0'; + elsif rising_edge (clk_in) then + if rd_data = '1' then + rx_ready <= '0'; + elsif rx_ready_set = '1' then + rx_ready <= '1'; + end if; + end if; + end process; + + -- the rx_data register + process (rst, clk_in) + begin + if rst = '1' then + rx_data <= x"FF"; + elsif rising_edge (clk_in) then + if rx_ready_set = '1' then + rx_data <= rx_sreg; + end if; + end if; + end process; + + -- receiver shift register and bit counter + process (rst, rx_bit_cnt_clr, clk_in) + begin + if rst = '1' or rx_bit_cnt_clr = '1' then + rx_bit_cnt <= x"0"; + rx_ready_set <= '0'; + rx_empty_clr <= '0'; + rx_sreg <= x"FF"; + elsif rising_edge (clk_in) then + if clk_en = '1' then + rx_sreg <= rx_sreg (6 downto 0) & spi_din; + case rx_bit_cnt is + when x"0" => + rx_bit_cnt <= rx_bit_cnt + 1; + rx_ready_set <= '0'; + rx_empty_clr <= '1'; + when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" => + rx_bit_cnt <= rx_bit_cnt + 1; + rx_ready_set <= '0'; + rx_empty_clr <= '0'; + when x"7" => + rx_bit_cnt <= rx_bit_cnt + 1; + rx_ready_set <= '1'; + rx_empty_clr <= '0'; + when others => + null; + end case; + end if; + end if; + end process; +end rtl; Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/test_DMA.vhd =================================================================== --- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/test_DMA.vhd (revision 142) +++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/test_DMA.vhd (revision 142) @@ -0,0 +1,295 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 14:37:10 03/18/2013 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/test_DMA.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: DMA_ARBITER +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY test_DMA IS +END test_DMA; + +ARCHITECTURE behavior OF test_DMA IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT DMA_ARBITER + PORT( + dma_rd_request : IN std_logic_vector(3 downto 0); + data_wr_in : IN std_logic_vector(7 downto 0); + data_rd_out : OUT std_logic_vector(7 downto 0); + address_rd : IN std_logic_vector(15 downto 0); + address_wr : IN std_logic_vector(15 downto 0); + address_out_wr : OUT std_logic_vector(15 downto 0); + address_out_rd : OUT std_logic_vector(15 downto 0); + ram_en : OUT std_logic; + ram_we : OUT std_logic; + data_wr_mem : OUT std_logic_vector(7 downto 0); + data_rd_mem : IN std_logic_vector(7 downto 0); + dma_wr_grant : OUT std_logic_vector(3 downto 0); + hold_req : OUT std_logic; + hold_ack : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + dma_rd_grant : OUT std_logic_vector(3 downto 0); + dma_wr_request : IN std_logic_vector(3 downto 0) + ); + END COMPONENT; + +COMPONENT RAM_v + generic (width : positive;size :positive); + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector; + addrb : IN std_logic_vector; + dia : IN std_logic_vector; + dob : OUT std_logic_vector + ); + END COMPONENT; + --Inputs + signal dma_rd_request : std_logic_vector(3 downto 0) := (others => '0'); + signal data_wr_in : std_logic_vector(7 downto 0) := (others => '0'); + signal address_rd : std_logic_vector(15 downto 0) := (others => '0'); + signal address_wr : std_logic_vector(15 downto 0) := (others => '0'); + signal data_rd_mem : std_logic_vector(7 downto 0) := (others => '0'); + signal hold_ack : std_logic := '0'; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal dma_wr_request : std_logic_vector(3 downto 0) := (others => '0'); + + --Outputs + signal data_rd_out : std_logic_vector(7 downto 0); + signal address_out_wr : std_logic_vector(15 downto 0); + signal address_out_rd : std_logic_vector(15 downto 0); + signal ram_en : std_logic; + signal ram_we : std_logic; + signal data_wr_mem : std_logic_vector(7 downto 0); + signal dma_wr_grant : std_logic_vector(3 downto 0); + signal hold_req : std_logic; + signal dma_rd_grant : std_logic_vector(3 downto 0); + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: DMA_ARBITER PORT MAP ( + dma_rd_request => dma_rd_request, + data_wr_in => data_wr_in, + data_rd_out => data_rd_out, + address_rd => address_rd, + address_wr => address_wr, + address_out_wr => address_out_wr, + address_out_rd => address_out_rd, + ram_en => ram_en, + ram_we => ram_we, + data_wr_mem => data_wr_mem, + data_rd_mem => data_rd_mem, + dma_wr_grant => dma_wr_grant, + hold_req => hold_req, + hold_ack => hold_ack, + clk => clk, + reset => reset, + dma_rd_grant => dma_rd_grant, + dma_wr_request => dma_wr_request + ); + +Inst_RAM_v: RAM_v generic map(width=>8,size=>16) + PORT MAP( + clka =>clk, + clkb => clk, + wea => ram_we, + ena => ram_en, + enb => ram_en, + addra => address_out_wr, + addrb =>address_out_rd, + dia => data_wr_mem, + dob => data_rd_mem + ); + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + reset_proc: process + begin + -- hold reset state for 100 ns. + reset <='1'; + wait for 100 ns; + reset<='0'; + wait for clk_period*10; + + -- insert stimulus here + + wait; + end process; + + stim_proc: process (clk,reset) + variable i,j,k,l : std_logic_vector(15 downto 0); + variable x: integer ; --indique le temps à partir duquel chaque + --permet de faire des requêtes DMA et de les valider + begin + if rising_edge(clk) then + if reset ='1' then + x:=0; + else + x:=x+1; + if x>=1 and x<=20 then + dma_rd_request<="0001"; + elsif x>=21 and x<=40 then + dma_rd_request<="0011"; + elsif x>=41 and x<=60 then + dma_rd_request<="0010"; + elsif x>=61 and x<=80 then + dma_rd_request<="0110"; + elsif x>=81 and x<=100 then + dma_rd_request<="0100"; + elsif x>=61 and x<=80 then + dma_rd_request<="1100"; + elsif x>=101 and x<=120 then + dma_rd_request<="1101"; + elsif x>=121 and x<=140 then + dma_rd_request<="1001"; + elsif x>=141 and x<=160 then + dma_rd_request<="1000"; + elsif x>=161 and x<=180 then + dma_rd_request<="0000"; + elsif x>=181 and x<=200 then + dma_rd_request<="0111"; + elsif x>=181 and x<=200 then + dma_rd_request<="1111"; + elsif x>=181 and x<=200 then + dma_rd_request<="1110"; + else + x:=0; + + end if; + + end if; + end if; + end process; +stim2_proc: process (clk,reset) + variable i,j,k,l : std_logic_vector(15 downto 0); + variable x: integer ; --indique le temps à partir duquel chaque + --permet de faire des requêtes DMA et de les valider + begin + if rising_edge(clk) then + if reset ='1' then + x:=0; + else + x:=x+1; + if x>=1 and x<=10 then + dma_wr_request<="0001"; + elsif x>=11 and x<=20 then + dma_wr_request<="0011"; + elsif x>=21 and x<=30 then + dma_wr_request<="0010"; + elsif x>=31 and x<=40 then + dma_wr_request<="0110"; + elsif x>=41 and x<=50 then + dma_wr_request<="0100"; + elsif x>=51 and x<=60 then + dma_wr_request<="1100"; + elsif x>=61 and x<=80 then + dma_wr_request<="1101"; + elsif x>=81 and x<=90 then + dma_wr_request<="1001"; + elsif x>=91 and x<=100 then + dma_wr_request<="1000"; + elsif x>=101 and x<=110 then + dma_wr_request<="0000"; + elsif x>=111 and x<=120 then + dma_wr_request<="0111"; + elsif x>=121 and x<=130 then + dma_wr_request<="1111"; + elsif x>=131 and x<=200 then + dma_wr_request<="1110"; + else + x:=0; + + end if; + + end if; + end if; + end process; +liredat:process (dma_rd_grant) +begin + + +if dma_rd_grant="0001" then +address_rd<=x"0000"; +elsif dma_rd_grant="0010" then +address_rd<=x"0002"; +elsif dma_rd_grant="0100" then +address_rd<=x"0004"; +elsif dma_rd_grant="1000" then +address_rd<=x"0006"; +else + + address_rd<=x"0000"; +end if; + +end process; +ecriredat:process (dma_wr_grant) +begin + + +if dma_wr_grant="0001" then +address_wr<=x"0000"; +data_wr_in<=x"0a"; +elsif dma_rd_grant="0010" then +address_wr<=x"0002"; +data_wr_in<=x"20"; +elsif dma_rd_grant="0100" then +address_wr<=x"0004"; +data_wr_in<=x"a0"; +elsif dma_rd_grant="1000" then +address_wr<=x"0006"; +data_wr_in<=x"0F"; +else + + address_wr<=x"0000"; + +end if; + +end process; +Hold_ack<=Hold_req; -- toujours autoriser la gestion de la mémoire par le DMA + +END;