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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:35:09 06/13/2011 
-- Design Name: 
-- Module Name:    DEMUX1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DEMUX1 is
    Port ( di : in  STD_LOGIC;
           sel : in  STD_LOGIC;
           do1 : out  STD_LOGIC;
           do2 : out  STD_LOGIC);
end DEMUX1;

architecture Behavioral of DEMUX1 is

begin

demux_process : process(di, sel)
begin
  if sel = '0' then
     do1 <= di;
	  do2 <= '0';
  else
     do2 <= di;
	  do1 <='0';
  end if;
end process;


end Behavioral;

