Index: /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/Timer_Par/Hold_FSM.vhd
===================================================================
--- /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/Timer_Par/Hold_FSM.vhd	(revision 152)
+++ /PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/Timer_Par/Hold_FSM.vhd	(revision 152)
@@ -0,0 +1,124 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: GAMOM Roland Christian
+-- 
+-- Create Date:    17:38:35 04/20/2013 
+-- Design Name: 
+-- Module Name:    Hold_FSM - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Hold_FSM is
+    Port ( Hold_Req : in  STD_LOGIC;
+           ram_busy : in  STD_LOGIC;
+           Clk : in  STD_LOGIC;
+           Reset : in  STD_LOGIC;
+           Ramsel : out  STD_LOGIC;
+           Hold_Ack : out  STD_LOGIC);
+end Hold_FSM;
+
+architecture Behavioral of Hold_FSM is
+type typ_Hld is (Ht_free,Ht_Lock,Core_Lock);
+signal Holdstate,Hold_st :typ_hld;
+		signal Ram_sel :std_logic:='0';
+		signal front_Rbusy,front_hReq:std_logic:='0';
+begin
+
+hold_sync:process (clk,reset)
+ begin
+ if rising_edge(clk) then
+	
+		
+ end if;
+ end process hold_sync;
+ Ramsel_state:process(clk)--,HoldState,Hold_Req,ram_Busy,Front_HReq,Front_RBusy)
+ 
+ begin
+ 
+ if rising_edge(clk) then
+ if reset='1' then
+		HolDState<=Ht_free;
+	else
+--		HolDState<=Hold_St;
+--	 Hold_St<=HoldState;
+ case HoldState is
+ when Ht_free =>
+	if Hold_Req='1' and ram_busy='0'   then
+		HolDState <=Core_lock;
+	elsif Hold_Req='0' and ram_busy='1' then
+		HoldState <=HT_lock;
+	elsif Hold_Req='1' and ram_busy='1' then
+		HoldState <=HT_lock;
+	else
+		HoldState <=HT_free;
+	end if;
+ when Ht_lock =>
+	if Hold_Req='0' and ram_busy='0'  then
+		HoldState <=HT_free;
+	elsif Hold_Req='1' and Ram_busy='0' then
+		HoldState <=Core_lock;
+	else
+		HoldState <=HT_lock;
+	end if;
+ 
+ When Core_lock =>
+	If Hold_Req='0' and Ram_busy='0' then
+		HoldState <=HT_free;
+	elsif Hold_Req='0' and Ram_busy='1' then
+		HoldState <=HT_lock;
+	else
+		HoldState <=Core_lock;
+	end if;
+ end case ;
+ end if;
+ end if;
+
+ end process;
+ 
+  Ramsel_val:process(HoldState,Hold_Req,Ram_Busy)
+ 
+ begin
+ case HoldState is
+ when Ht_free =>
+ ram_sel<='0';
+ Hold_Ack<='0';
+ when Ht_Lock =>
+ ram_sel<='0';
+ Hold_Ack<='0';
+ when Core_lock =>
+ Ram_sel <='1';
+ Hold_Ack<='1';
+ end case;
+ if Hold_Req= not(front_HReq) then
+	front_HReq<= not front_HReq;
+end if;
+
+if Ram_busy= not (front_RBusy) then
+	front_RBusy<= not front_RBusy;
+end if;
+ end process ramsel_val;
+ Ramsel<=Ram_sel;
+--=======================================================================
+end Behavioral;
+