MPICORETEST Project Status (08/03/2012 - 19:01:09)
Project File:	MPI_CORE_COMPONENTS.xise	Parser Errors:	No Errors
Module Name:	CORE_MPI	Implementation State:	Synthesized (Stopped)
Target Device:	xc6slx100t-3fgg484	Errors:
Product Version:	ISE 12.3	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Total Number Slice Registers	598	17,344	3%
Number used as Flip Flops	340
Number used as Latches	258
Number of 4 input LUTs	1,291	17,344	7%
Number of occupied Slices	791	8,672	9%
Number of Slices containing only related logic	791	791	100%
Number of Slices containing unrelated logic	0	791	0%
Total Number of 4 input LUTs	1,362	17,344	7%
Number used as logic	1,211
Number used as a route-thru	71
Number used for Dual Port RAMs	80
Number of bonded IOBs	95	190	50%
Number of BUFGMUXs	3	24	12%
Average Fanout of Non-Clock Nets	3.64

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Fri 3. Aug 10:50:10 2012
Translation Report	Current	Fri 3. Aug 10:50:14 2012	0	5 Warnings (5 new)	0
Map Report	Current	Fri 3. Aug 10:50:21 2012	0	33 Warnings (33 new)	4 Infos (2 new)
Place and Route Report	Current	Fri 3. Aug 10:51:00 2012	0	18 Warnings (18 new)	4 Infos (0 new)
CPLD Fitter Report (Text)
Power Report
Post-PAR Static Timing Report	Current	Fri 3. Aug 10:51:04 2012	0	0	5 Infos (0 new)
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 08/03/2012 - 19:02:25