testbench Project Status
Project File: | GENERIC_16_16.xise | Parser Errors:
Module Name: | testbench | Implementation State: | New
Target Device: | xc3s1200e-4ft256 | Errors: |
Product Version: | ISE 12.3 | Warnings: |
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: |  | Final Timing Score: |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report |  |  |  |  |
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 11/29/2012 - 18:08:12