Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.bld =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.bld (revision 17) +++ (revision ) @@ -1,40 +1,0 @@ -Release 12.3 ngdbuild M.70d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -Command Line: d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe --intstyle ise -dd _ngo -nt timestamp -i -p xc3s1200e-ft256-5 CORE_MPI.ngc -CORE_MPI.ngd - -Reading NGO file "C:/Core MPI/CORE_MPI/CORE_MPI.ngc" ... -Gathering constraint information from source properties... -Done. - -Resolving constraint associations... -Checking Constraint Associations... -Done... - -Checking expanded design ... -WARNING:NgdBuild:452 - logical net 'MyRank<0>' has no driver -WARNING:NgdBuild:452 - logical net 'MyRank<1>' has no driver -WARNING:NgdBuild:452 - logical net 'MyRank<2>' has no driver -WARNING:NgdBuild:452 - logical net 'MyRank<3>' has no driver -WARNING:NgdBuild:452 - logical net 'instruction_fifo2_full' has no driver - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -NGDBUILD Design Results Summary: - Number of errors: 0 - Number of warnings: 5 - -Total memory usage is 146244 kilobytes - -Writing NGD file "CORE_MPI.ngd" ... -Total REAL time to NGDBUILD completion: 2 sec -Total CPU time to NGDBUILD completion: 2 sec - -Writing NGDBUILD log file "CORE_MPI.bld"... Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.cmd_log =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.cmd_log (revision 17) +++ (revision ) @@ -1,5 +1,0 @@ -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/CORE_MPI.xst" -ofn "C:/Core MPI/CORE_MPI/CORE_MPI.syr" -ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1200e-ft256-5 "CORE_MPI.ngc" CORE_MPI.ngd -map -intstyle ise -p xc3s1200e-ft256-5 -cm area -ir off -pr off -c 100 -o CORE_MPI_map.ncd CORE_MPI.ngd CORE_MPI.pcf -par -w -intstyle ise -ol high -t 1 CORE_MPI_map.ncd CORE_MPI.ncd CORE_MPI.pcf -trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml CORE_MPI.twx CORE_MPI.ncd -o CORE_MPI.twr CORE_MPI.pcf Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.lso =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.lso (revision 17) +++ (revision ) @@ -1,2 +1,0 @@ -NocLib -work Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.pcf =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.pcf (revision 17) +++ (revision ) @@ -1,4 +1,0 @@ -//! ************************************************************************** -// Written by: Map M.70d on Fri Aug 03 10:50:21 2012 -//! ************************************************************************** - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.prj (revision 17) +++ (revision ) @@ -1,17 +1,0 @@ -vhdl NocLib "../SWITCH_GENERIC_16_16/CoreTypes.vhd" -vhdl work "round_robbin_machine.vhd" -vhdl work "RAM_64.vhd" -vhdl work "Packet_type.vhd" -vhdl work "MUX8.vhd" -vhdl work "MUX1.vhd" -vhdl work "DEMUX1.vhd" -vhdl work "MPI_CORE_SCHEDULER.vhd" -vhdl work "load_instr.vhd" -vhdl work "FIFO_64_FWFT.vhd" -vhdl work "EX4_FSM.vhd" -vhdl work "EX3_FSM.vhd" -vhdl work "EX2_FSM.vhd" -vhdl work "EX1_FSM.vhd" -vhdl work "Ex0_Fsm.vhd" -vhdl work "DMA_ARBITER.vhd" -vhdl work "CORE_MPI.vhd" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.ptwx =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.ptwx (revision 17) +++ (revision ) @@ -1,332 +1,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -]> -Autotimespec constraint for clock net clkout_OBUFAutotimespec constraint for clock net dma_rd_grant<3>Autotimespec constraint for clock net MPI_CORE_EX4_FSM/NextRank_or0000Autotimespec constraint for clock net LD_instr/Mtridata_Ram_address_i_not0001Autotimespec constraint for clock net LD_instr/etloadinst_cmp_eq0020Autotimespec constraint for clock net MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000Autotimespec constraint for clock net LD_instr/timeout_not0001Autotimespec constraint for clock net MPI_CORE_EX4_FSM/stInit2_FSM_FFd20INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.syr =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.syr (revision 17) +++ (revision ) @@ -1,2771 +1,0 @@ -Release 12.3 - xst M.70d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. ---> Parameter TMPDIR set to xst/projnav.tmp - - -Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.09 secs - ---> Parameter xsthdpdir set to xst - - -Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.09 secs - ---> Reading design: CORE_MPI.prj - -TABLE OF CONTENTS - 1) Synthesis Options Summary - 2) HDL Compilation - 3) Design Hierarchy Analysis - 4) HDL Analysis - 5) HDL Synthesis - 5.1) HDL Synthesis Report - 6) Advanced HDL Synthesis - 6.1) Advanced HDL Synthesis Report - 7) Low Level Synthesis - 8) Partition Report - 9) Final Report - 9.1) Device utilization summary - 9.2) Partition Resource Summary - 9.3) TIMING REPORT - - -========================================================================= -* Synthesis Options Summary * -========================================================================= ----- Source Parameters -Input File Name : "CORE_MPI.prj" -Input Format : mixed -Ignore Synthesis Constraint File : NO - ----- Target Parameters -Output File Name : "CORE_MPI" -Output Format : NGC -Target Device : xc3s1200e-5-ft256 - ----- Source Options -Top Module Name : CORE_MPI -Automatic FSM Extraction : YES -FSM Encoding Algorithm : Auto -Safe Implementation : No -FSM Style : LUT -RAM Extraction : Yes -RAM Style : Auto -ROM Extraction : Yes -Mux Style : Auto -Decoder Extraction : YES -Priority Encoder Extraction : Yes -Shift Register Extraction : YES -Logical Shifter Extraction : YES -XOR Collapsing : YES -ROM Style : Auto -Mux Extraction : Yes -Resource Sharing : YES -Asynchronous To Synchronous : NO -Multiplier Style : LUT -Automatic Register Balancing : No - ----- Target Options -Add IO Buffers : YES -Global Maximum Fanout : 100000 -Add Generic Clock Buffer(BUFG) : 24 -Register Duplication : YES -Slice Packing : YES -Optimize Instantiated Primitives : NO -Use Clock Enable : Yes -Use Synchronous Set : Yes -Use Synchronous Reset : Yes -Pack IO Registers into IOBs : Auto -Equivalent register Removal : YES - ----- General Options -Optimization Goal : Speed -Optimization Effort : 1 -Keep Hierarchy : Soft -Netlist Hierarchy : As_Optimized -RTL Output : Yes -Global Optimization : AllClockNets -Read Cores : YES -Write Timing Constraints : NO -Cross Clock Analysis : NO -Hierarchy Separator : / -Bus Delimiter : <> -Case Specifier : Maintain -Slice Utilization Ratio : 100 -BRAM Utilization Ratio : 100 -Verilog 2001 : YES -Auto BRAM Packing : NO -Slice Utilization Ratio Delta : 5 - -========================================================================= - - -========================================================================= -* HDL Compilation * -========================================================================= -Compiling vhdl file "C:/Core MPI/CORE_MPI/round_robbin_machine.vhd" in Library work. -Architecture behavioral of Entity round_robbin_machine is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/MUX1.vhd" in Library work. -Architecture behavioral of Entity mux1 is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/DEMUX1.vhd" in Library work. -Architecture behavioral of Entity demux1 is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/MUX8.vhd" in Library work. -Architecture behavioral of Entity mux8 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/CoreTypes.vhd" in Library NocLib. -Architecture coretypes of Entity coretypes is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/Packet_type.vhd" in Library work. -Architecture packet_type of Entity packet_type is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/RAM_64.vhd" in Library work. -Architecture behavioral of Entity ram_64 is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/FIFO_64_FWFT.vhd" in Library work. -Architecture behavioral of Entity fifo_64_fwft is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/load_instr.vhd" in Library work. -Architecture behavioral of Entity load_instr is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/Ex0_Fsm.vhd" in Library work. -Architecture behavioral of Entity ex0_fsm is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/EX1_FSM.vhd" in Library work. -Architecture behavioral of Entity ex1_fsm is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/EX2_FSM.vhd" in Library work. -Architecture behavioral of Entity ex2_fsm is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/EX3_FSM.vhd" in Library work. -Architecture behavioral of Entity ex3_fsm is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/EX4_FSM.vhd" in Library work. -Architecture behavioral of Entity ex4_fsm is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/DMA_ARBITER.vhd" in Library work. -Architecture behavioral of Entity dma_arbiter is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/MPI_CORE_SCHEDULER.vhd" in Library work. -Architecture behavioral of Entity mpi_core_scheduler is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" in Library work. -Architecture structural of Entity core_mpi is up to date. - -========================================================================= -* Design Hierarchy Analysis * -========================================================================= -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ) with generics. - nprocs = "0100" - pid = "0001" - -Analyzing hierarchy for entity in library (architecture ) with generics. - nprocs = "00000011" - pid = "00000001" - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - - -========================================================================= -* HDL Analysis * -========================================================================= -Analyzing Entity in library (Architecture ). -WARNING:Xst:753 - "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" line 408: Unconnected output port 'OvFus' of component 'EX0_FSM'. -INFO:Xst:1561 - "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" line 468: Mux is complete : default of case is discarded -WARNING:Xst:753 - "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" line 522: Unconnected output port 'pid_nprocs' of component 'EX3_FSM'. -WARNING:Xst:819 - "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" line 581: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: - -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -WARNING:Xst:819 - "C:/Core MPI/CORE_MPI/Ex0_Fsm.vhd" line 82: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: - , -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -WARNING:Xst:819 - "C:/Core MPI/CORE_MPI/EX1_FSM.vhd" line 287: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: - -INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. -Entity analyzed. Unit generated. - -Analyzing generic Entity in library (Architecture ). - nprocs = "0100" - pid = "0001" -INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. -Entity analyzed. Unit generated. - -Analyzing generic Entity in library (Architecture ). - nprocs = "00000011" - pid = "00000001" -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch. -INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch. -INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch. -INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch. -INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register > in unit has a constant value of 00000011 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - - -========================================================================= -* HDL Synthesis * -========================================================================= - -Performing bidirectional port resolution... -INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/load_instr.vhd". - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 7 | - | Transitions | 39 | - | Inputs | 23 | - | Outputs | 9 | - | Clock | clk (rising_edge) | - | Reset | etloadinst$or0000 (positive) | - | Reset type | synchronous | - | Reset State | init | - | Power Up State | init | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- -WARNING:Xst:737 - Found 16-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 16-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 16-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 16-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:736 - Found 16-bit latch for signal created at line 183. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. - Using one-hot encoding for signal . -WARNING:Xst:736 - Found 1-bit latch for signal created at line 183. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 19-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 16-bit adder for signal . - Found 1-bit register for signal . - Found 19-bit register for signal . - Found 8-bit adder for signal created at line 308. - Found 8-bit tristate buffer for signal . - Found 16-bit adder for signal created at line 203. - Found 16-bit tristate buffer for signal . - Summary: - inferred 1 Finite State Machine(s). - inferred 46 D-type flip-flop(s). - inferred 3 Adder/Subtractor(s). - inferred 24 Tristate(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/Ex0_Fsm.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 1. - Using one-hot encoding for signal . -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 32-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Summary: - inferred 70 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/EX1_FSM.vhd". - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 18 | - | Transitions | 58 | - | Inputs | 21 | - | Outputs | 22 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | fifo_select | - | Power Up State | fifo_select | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 8-bit tristate buffer for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 9-bit comparator greater for signal created at line 195. - Found 4-bit comparator less for signal created at line 267. - Found 8-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 107. - Found 8-bit register for signal . - Found 8-bit addsub for signal created at line 107. - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 268. - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 198. - Summary: - inferred 1 Finite State Machine(s). - inferred 68 D-type flip-flop(s). - inferred 4 Adder/Subtractor(s). - inferred 2 Comparator(s). - inferred 8 Tristate(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/EX2_FSM.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0000. -INFO:Xst:1799 - State execute_spawn is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 18 | - | Transitions | 51 | - | Inputs | 20 | - | Outputs | 18 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | fetch_packet_type | - | Power Up State | fetch_packet_type | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- -WARNING:Xst:736 - Found 8-bit latch for signal created at line 244. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. - Using one-hot encoding for signal . -WARNING:Xst:736 - Found 1-bit latch for signal created at line 244. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 8-bit tristate buffer for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 154. - Found 9-bit comparator greater for signal created at line 151. - Found 5-bit comparator less for signal created at line 195. - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 97. - Found 8-bit register for signal . - Found 8-bit subtractor for signal created at line 97. - Summary: - inferred 1 Finite State Machine(s). - inferred 40 D-type flip-flop(s). - inferred 3 Adder/Subtractor(s). - inferred 2 Comparator(s). - inferred 8 Tristate(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/EX3_FSM.vhd". -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 00000011. - Found 8-bit register for signal . - Found 8-bit up counter for signal . - Summary: - inferred 1 Counter(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/EX4_FSM.vhd". -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0000. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0000. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0000. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value 00000000. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal <7:4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 21 | - | Inputs | 9 | - | Outputs | 7 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | r_wait | - | Power Up State | r_wait | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 9 | - | Transitions | 23 | - | Inputs | 8 | - | Outputs | 11 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | cmdstart | - | Power Up State | cmdstart | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 13 | - | Inputs | 5 | - | Outputs | 7 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | s_init | - | Power Up State | s_init | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 14 | - | Transitions | 31 | - | Inputs | 12 | - | Outputs | 15 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | asynchronous | - | Reset State | init | - | Power Up State | init | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- -WARNING:Xst:737 - Found 4-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 16-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 31-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 4-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 16-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 4-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 4-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 2-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 4-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 31-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 8-bit tristate buffer for signal . - Found 4-bit register for signal . - Found 8-bit 4-to-1 multiplexer for signal <$varindex0000> created at line 635. - Found 2-bit adder carry out for signal created at line 638. - Found 1-bit register for signal . - Found 4-bit comparator equal for signal created at line 641. - Found 8-bit register for signal . - Found 8-bit subtractor for signal created at line 737. - Found 8-bit register for signal . - Found 8-bit register for signal >. - Found 8-bit register for signal >. - Found 8-bit register for signal . - Found 8-bit adder for signal created at line 689. - Found 8-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 8-bit adder for signal created at line 728. - Found 4-bit adder for signal created at line 709. - Found 9-bit subtractor for signal created at line 758. - Found 4-bit comparator equal for signal created at line 711. - Found 9-bit comparator equal for signal created at line 758. - Found 8-bit comparator greatequal for signal created at line 729. - Found 8-bit comparator greatequal for signal created at line 764. - Found 8-bit comparator less for signal created at line 751. - Found 8-bit adder for signal created at line 502. - Found 8-bit adder for signal created at line 535. - Found 8-bit comparator greatequal for signal created at line 503. - Found 8-bit comparator lessequal for signal created at line 537. - Found 8-bit adder for signal created at line 637. - Found 4-bit adder for signal created at line 655. - Found 8-bit comparator greater for signal created at line 638. - Found 4-bit comparator less for signal created at line 656. - Found 8-bit register for signal . - Found 8-bit register for signal created at line 588. - Found 1-bit register for signal created at line 588. - Found 4-bit register for signal . - Found 31-bit adder for signal created at line 239. - Found 31-bit adder for signal created at line 218. - Found 4-bit adder for signal created at line 220. - Found 1-bit register for signal >. - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 240. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit adder for signal created at line 325. - Found 8-bit tristate buffer for signal . - Found 8-bit tristate buffer for signal . - Summary: - inferred 4 Finite State Machine(s). - inferred 116 D-type flip-flop(s). - inferred 15 Adder/Subtractor(s). - inferred 10 Comparator(s). - inferred 8 Multiplexer(s). - inferred 24 Tristate(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/DMA_ARBITER.vhd". -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 25 | - | Inputs | 7 | - | Outputs | 9 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- -WARNING:Xst:736 - Found 1-bit latch for signal created at line 294. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 310. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 294. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 310. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 294. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 310. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 294. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 310. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 295. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 319. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 295. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 319. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 295. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 319. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 295. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 319. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 4-bit register for signal . - Found 1-bit 4-to-1 multiplexer for signal created at line 218. - Found 1-bit 4-to-1 multiplexer for signal created at line 209. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit 4-to-1 multiplexer for signal created at line 218. - Found 1-bit 4-to-1 multiplexer for signal created at line 209. - Found 2-bit register for signal . - Found 2-bit adder for signal created at line 186. - Found 2-bit register for signal . - Found 2-bit adder for signal created at line 141. - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 1 Finite State Machine(s). - inferred 24 D-type flip-flop(s). - inferred 2 Adder/Subtractor(s). - inferred 4 Multiplexer(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/RAM_64.vhd". - Found 64x8-bit dual-port RAM for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/round_robbin_machine.vhd". - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/MUX1.vhd". -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/DEMUX1.vhd". -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/MUX8.vhd". -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/FIFO_64_FWFT.vhd". -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 3 | - | Transitions | 9 | - | Inputs | 4 | - | Outputs | 3 | - | Clock | clk (rising_edge) | - | Reset | srst (positive) | - | Reset type | synchronous | - | Reset State | state0 | - | Power Up State | state0 | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit register for signal . - Found 6-bit updown counter for signal . - Found 6-bit up counter for signal . - Found 6-bit up counter for signal . - Summary: - inferred 1 Finite State Machine(s). - inferred 3 Counter(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/MPI_CORE_SCHEDULER.vhd". -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/CORE_MPI.vhd". -WARNING:Xst:1306 - Output > is never assigned. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 00011010. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value 0. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value 0. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value 0. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 16-bit tristate buffer for signal . - Found 16-bit tristate buffer for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 32 Tristate(s). -Unit synthesized. - -INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. - -========================================================================= -HDL Synthesis Report - -Macro Statistics -# RAMs : 2 - 64x8-bit dual-port RAM : 2 -# Adders/Subtractors : 27 - 16-bit adder : 5 - 2-bit adder : 2 - 2-bit adder carry out : 1 - 31-bit adder : 2 - 4-bit adder : 6 - 8-bit adder : 7 - 8-bit addsub : 1 - 8-bit subtractor : 2 - 9-bit subtractor : 1 -# Counters : 7 - 6-bit up counter : 4 - 6-bit updown counter : 2 - 8-bit up counter : 1 -# Registers : 110 - 1-bit register : 69 - 16-bit register : 2 - 19-bit register : 1 - 2-bit register : 2 - 32-bit register : 2 - 4-bit register : 13 - 8-bit register : 21 -# Latches : 98 - 1-bit latch : 67 - 16-bit latch : 7 - 19-bit latch : 1 - 2-bit latch : 1 - 31-bit latch : 2 - 32-bit latch : 1 - 4-bit latch : 5 - 8-bit latch : 14 -# Comparators : 14 - 4-bit comparator equal : 2 - 4-bit comparator less : 2 - 5-bit comparator less : 1 - 8-bit comparator greatequal : 3 - 8-bit comparator greater : 1 - 8-bit comparator less : 1 - 8-bit comparator lessequal : 1 - 9-bit comparator equal : 1 - 9-bit comparator greater : 2 -# Multiplexers : 5 - 1-bit 4-to-1 multiplexer : 4 - 8-bit 4-to-1 multiplexer : 1 -# Tristates : 9 - 16-bit tristate buffer : 3 - 8-bit tristate buffer : 6 - -========================================================================= - -========================================================================= -* Advanced HDL Synthesis * -========================================================================= - -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. --------------------- - State | Encoding --------------------- - state0 | 00 - state1 | 01 - state2 | 10 --------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -------------------------- - State | Encoding -------------------------- - idle | 000 - wait_ack | 001 - arbiter_ack | 011 - writing | 111 - readwrite | 010 - reading | 110 -------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------- - State | Encoding -------------------------------- - init | 00000000000001 - getportnum | 00000000000100 - decodedata | 00000000001000 - isportzero | 00000000010000 - seekmain | 00000000100000 - storemain | 00000010000000 - setmainflag | 00000001000000 - getmainreq | 00000000000010 - storerank | 00000100000000 - newrank | 00010000000000 - sendrank | 00100000000000 - regrank | 01000000000000 - sendapp | 00001000000000 - endinit | 10000000000000 -------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. --------------------- - State | Encoding --------------------- - s_init | 000001 - s_head | 000010 - s_len | 000100 - s_len2 | 001000 - s_data | 010000 - s_end | 100000 --------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. --------------------------- - State | Encoding --------------------------- - cmdstart | 000000001 - cmdpost | 000000010 - cmdpostidle | 000000100 - cmdread | 000001000 - cmdlen | 000010000 - cmdglen | 001000000 - cmddata | 010000000 - cmdend | 100000000 - cmdtimeout | 000100000 --------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. ---------------------- - State | Encoding ---------------------- - r_wait | 000 - r_dlen | 001 - r_drop | 011 - r_glen | 110 - r_start | 111 - r_end | 010 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------------------- - State | Encoding -------------------------------------------- - fetch_packet_type | 000000000000000001 - decode_packet_type | 000000000000000010 - decode_packet_type2 | 000000000000000100 - fetch_addresses | 000000000000100000 - execute_spawn | unreached - execute_put1 | 000000000010000000 - execute_put2 | 000000001000000000 - execute_put3 | 000000010000000000 - execute_get1 | 000000000001000000 - execute_get2 | 000000100000000000 - execute_barrier1 | 000000000000001000 - execute_barrier2 | 000001000000000000 - execute_barrier3 | 000100000000000000 - execute_barrier4 | 000010000000000000 - execute_barrier5 | 001000000000000000 - execute_barrier6 | 010000000000000000 - execute_barrier7 | 100000000000000000 - execute_init1 | 000000000000010000 - execute_init2 | 000000000100000000 -------------------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------------------- - State | Encoding -------------------------------------------- - fifo_select | 000000000000000001 - fetch_packet_type | 000000000000000010 - decode_packet_type | 000000000000000100 - fetch_addresses | 000000000000001000 - decode_packet_type2 | 000000000001000000 - execute_barrier1 | 000000000000010000 - execute_barrier2 | 000100000000000000 - execute_barrier3 | 001000000000000000 - execute_barrier4 | 010000000000000000 - execute_get1 | 000000000100000000 - execute_get2 | 000010000000000000 - execute_put1 | 000000000010000000 - execute_put2 | 000000001000000000 - execute_put3 | 000000010000000000 - execute_put4 | 000000100000000000 - execute_put5 | 000001000000000000 - execute_init1 | 000000000000100000 - execute_init2 | 100000000000000000 -------------------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. ------------------------- - State | Encoding ------------------------- - init | 000 - setadr | 011 - readptr | 010 - getbus | 001 - readmem | 110 - freebus | 111 - st_timeout | 101 ------------------------- -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block base_adrset_i. - You should achieve better results by setting this init to 1. -WARNING:Xst:1426 - The value init of the FF/Latch origport0_0 hinder the constant cleaning in the block MPI_CORE_EX4_FSM. - You should achieve better results by setting this init to 1. -WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block Initialized. - You should achieve better results by setting this init to 1. -WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block 0. - You should achieve better results by setting this init to 1. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Synthesizing (advanced) Unit . -INFO:Xst:3048 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 64-word x 8-bit | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 64-word x 8-bit | | - | addrB | connected to signal | | - | doB | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . - -========================================================================= -Advanced HDL Synthesis Report - -Macro Statistics -# FSMs : 9 -# RAMs : 2 - 64x8-bit dual-port distributed RAM : 2 -# Adders/Subtractors : 27 - 16-bit adder : 5 - 2-bit adder : 2 - 2-bit adder carry out : 1 - 31-bit adder : 2 - 4-bit adder : 6 - 8-bit adder : 7 - 8-bit addsub : 1 - 8-bit subtractor : 2 - 9-bit subtractor : 1 -# Counters : 7 - 6-bit up counter : 4 - 6-bit updown counter : 2 - 8-bit up counter : 1 -# Registers : 403 - Flip-Flops : 403 -# Latches : 98 - 1-bit latch : 67 - 16-bit latch : 7 - 19-bit latch : 1 - 2-bit latch : 1 - 31-bit latch : 2 - 32-bit latch : 1 - 4-bit latch : 5 - 8-bit latch : 14 -# Comparators : 14 - 4-bit comparator equal : 2 - 4-bit comparator less : 2 - 5-bit comparator less : 1 - 8-bit comparator greatequal : 3 - 8-bit comparator greater : 1 - 8-bit comparator less : 1 - 8-bit comparator lessequal : 1 - 9-bit comparator equal : 1 - 9-bit comparator greater : 2 -# Multiplexers : 5 - 1-bit 4-to-1 multiplexer : 4 - 8-bit 4-to-1 multiplexer : 1 - -========================================================================= - -========================================================================= -* Low Level Synthesis * -========================================================================= -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1426 - The value init of the FF/Latch origport0_0 hinder the constant cleaning in the block EX4_FSM. - You should achieve better results by setting this init to 1. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1426 - The value init of the FF/Latch base_adrset_i hinder the constant cleaning in the block load_instr. - You should achieve better results by setting this init to 1. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1426 - The value init of the FF/Latch ram_data_out_0 hinder the constant cleaning in the block EX1_FSM. - You should achieve better results by setting this init to 1. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<1> Mtridata_Ram_data<1> signal will be lost. -WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<2> Mtridata_Ram_data<2> signal will be lost. -WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<3> Mtridata_Ram_data<3> signal will be lost. -WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<4> Mtridata_Ram_data<4> signal will be lost. -WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<5> Mtridata_Ram_data<5> signal will be lost. -WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<6> Mtridata_Ram_data<6> signal will be lost. -WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<7> Mtridata_Ram_data<7> signal will be lost. -WARNING:Xst:1294 - Latch is equivalent to a wire in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1426 - The value init of the FF/Latch Initialized hinder the constant cleaning in the block EX4_FSM. - You should achieve better results by setting this init to 1. -WARNING:Xst:1426 - The value init of the FF/Latch ResultOut_0 hinder the constant cleaning in the block EX4_FSM. - You should achieve better results by setting this init to 1. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:638 - in unit EX4_FSM Conflict on KEEP property on signal Mtridata_tosend<6> and Mtridata_tosend<7> Mtridata_tosend<7> signal will be lost. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_1_mux0000, Tick_Count<1>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<2>, V_2_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_3_mux0000, Tick_Count<3>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<4>, V_4_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_5_mux0000, Tick_Count<5>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<6>, V_6_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<7>, V_7_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<8>, V_8_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<9>, V_9_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<10>, V_10_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_11_mux0000, Tick_Count<11>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_12_mux0000, Tick_Count<12>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<13>, V_13_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<14>, V_14_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_15_mux0000, Tick_Count<15>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_16_mux0000, Tick_Count<16>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_17_mux0000, Tick_Count<17>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_18_mux0000, Tick_Count<18>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_19_mux0000, Tick_Count<19>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_20_mux0000, Tick_Count<20>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<21>, V_21_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<22>, V_22_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_23_mux0000, Tick_Count<23>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_24_mux0000, Tick_Count<24>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<25>, V_25_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<26>, V_26_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<27>, V_27_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<28>, V_28_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_29_mux0000, Tick_Count<29>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<30>, V_30_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<31>, V_31_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: ClkR_Count<1>, V0_1_mux0000, zero_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: ClkR_Count<0>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<0>. -WARNING:Xst:2042 - Unit CORE_MPI: 32 internal tristates are replaced by logic (pull-up yes): dma_rd_address<0>, dma_rd_address<10>, dma_rd_address<11>, dma_rd_address<12>, dma_rd_address<13>, dma_rd_address<14>, dma_rd_address<15>, dma_rd_address<1>, dma_rd_address<2>, dma_rd_address<3>, dma_rd_address<4>, dma_rd_address<5>, dma_rd_address<6>, dma_rd_address<7>, dma_rd_address<8>, dma_rd_address<9>, dma_wr_address<0>, dma_wr_address<10>, dma_wr_address<11>, dma_wr_address<12>, dma_wr_address<13>, dma_wr_address<14>, dma_wr_address<15>, dma_wr_address<1>, dma_wr_address<2>, dma_wr_address<3>, dma_wr_address<4>, dma_wr_address<5>, dma_wr_address<6>, dma_wr_address<7>, dma_wr_address<8>, dma_wr_address<9>. -WARNING:Xst:2042 - Unit EX4_FSM: 24 internal tristates are replaced by logic (pull-up yes): port_in_data<0>, port_in_data<1>, port_in_data<2>, port_in_data<3>, port_in_data<4>, port_in_data<5>, port_in_data<6>, port_in_data<7>, tosend4<0>, tosend4<1>, tosend4<2>, tosend4<3>, tosend4<4>, tosend4<5>, tosend4<6>, tosend4<7>, tosend<0>, tosend<1>, tosend<2>, tosend<3>, tosend<4>, tosend<5>, tosend<6>, tosend<7>. -WARNING:Xst:2042 - Unit EX2_FSM: 8 internal tristates are replaced by logic (pull-up yes): Ram_data<0>, Ram_data<1>, Ram_data<2>, Ram_data<3>, Ram_data<4>, Ram_data<5>, Ram_data<6>, Ram_data<7>. -WARNING:Xst:2042 - Unit EX1_FSM: 8 internal tristates are replaced by logic (pull-up yes): switch_port_in_data<0>, switch_port_in_data<1>, switch_port_in_data<2>, switch_port_in_data<3>, switch_port_in_data<4>, switch_port_in_data<5>, switch_port_in_data<6>, switch_port_in_data<7>. -WARNING:Xst:2042 - Unit load_instr: 24 internal tristates are replaced by logic (pull-up yes): Ram_address_i<0>, Ram_address_i<10>, Ram_address_i<11>, Ram_address_i<12>, Ram_address_i<13>, Ram_address_i<14>, Ram_address_i<15>, Ram_address_i<1>, Ram_address_i<2>, Ram_address_i<3>, Ram_address_i<4>, Ram_address_i<5>, Ram_address_i<6>, Ram_address_i<7>, Ram_address_i<8>, Ram_address_i<9>, fifo_din_i<0>, fifo_din_i<1>, fifo_din_i<2>, fifo_din_i<3>, fifo_din_i<4>, fifo_din_i<5>, fifo_din_i<6>, fifo_din_i<7>. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed - -Mapping all equations... -Building and optimizing final netlist ... -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -Found area constraint ratio of 100 (+ 5) on block CORE_MPI, actual ratio is 9. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . - -Final Macro Processing ... - -========================================================================= -Final Register Report - -Macro Statistics -# Registers : 340 - Flip-Flops : 340 - -========================================================================= - -========================================================================= -* Partition Report * -========================================================================= - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -========================================================================= -* Final Report * -========================================================================= -Final Results -RTL Top Level Output File Name : CORE_MPI.ngr -Top Level Output File Name : CORE_MPI -Output Format : NGC -Optimization Goal : Speed -Keep Hierarchy : Soft - -Design Statistics -# IOs : 98 - -Cell Usage : -# BELS : 1549 -# GND : 8 -# INV : 16 -# LUT1 : 61 -# LUT2 : 147 -# LUT2_D : 3 -# LUT2_L : 2 -# LUT3 : 257 -# LUT3_D : 6 -# LUT3_L : 8 -# LUT4 : 702 -# LUT4_D : 27 -# LUT4_L : 45 -# MUXCY : 80 -# MUXF5 : 100 -# VCC : 3 -# XORCY : 84 -# FlipFlops/Latches : 598 -# FD : 1 -# FDC : 12 -# FDCE : 1 -# FDE : 220 -# FDPE : 1 -# FDR : 36 -# FDRE : 39 -# FDRS : 23 -# FDRSE : 1 -# FDS : 4 -# FDSE : 2 -# LD : 147 -# LD_1 : 54 -# LDE : 57 -# RAMS : 40 -# RAM16X1D : 40 -# Clock Buffers : 3 -# BUFG : 3 -# IO Buffers : 95 -# IBUF : 31 -# OBUF : 64 -========================================================================= - -Device utilization summary: ---------------------------- - -Selected Device : 3s1200eft256-5 - - Number of Slices: 705 out of 8672 8% - Number of Slice Flip Flops: 598 out of 17344 3% - Number of 4 input LUTs: 1354 out of 17344 7% - Number used as logic: 1274 - Number used as RAMs: 80 - Number of IOs: 98 - Number of bonded IOBs: 95 out of 190 50% - Number of GCLKs: 3 out of 24 12% - ---------------------------- -Partition Resource Summary: ---------------------------- - - No Partitions were found in this design. - ---------------------------- - - -========================================================================= -TIMING REPORT - -NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. - FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT - GENERATED AFTER PLACE-and-ROUTE. - -Clock Information: ------------------- --------------------------------------------------------------------------------------------------+-----------------------------------------------------+-------+ -Clock Signal | Clock buffer(FF name) | Load | --------------------------------------------------------------------------------------------------+-----------------------------------------------------+-------+ -LD_instr/instruction_ack | NONE(Ex_EN_1) | 1 | -clk | IBUF+BUFG | 379 | -dma_data_in_not0001(dma_data_in_not00011:O) | NONE(*)(dma_data_in_0) | 8 | -MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001(MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not00011:O) | NONE(*)(MPI_CORE_DMA_ARBITER/dma_rd_grant_0_mux0001)| 1 | -MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001(MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not00011:O) | NONE(*)(MPI_CORE_DMA_ARBITER/dma_wr_grant_0_mux0001)| 1 | -MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000(MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq00001:O)| NONE(*)(MPI_CORE_DMA_ARBITER/dma_rd_grant_1_mux0001)| 1 | -MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000(MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq00001:O)| NONE(*)(MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux0001)| 1 | -MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000(MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq00001:O)| NONE(*)(MPI_CORE_DMA_ARBITER/dma_rd_grant_3_mux0001)| 1 | -MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000(MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq00001:O)| NONE(*)(MPI_CORE_DMA_ARBITER/dma_wr_grant_1_mux0001)| 1 | -MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000(MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq00001:O)| NONE(*)(MPI_CORE_DMA_ARBITER/dma_wr_grant_2_mux0001)| 1 | -MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000(MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq00001:O)| NONE(*)(MPI_CORE_DMA_ARBITER/dma_wr_grant_3_mux0001)| 1 | -LD_instr/fifo_wr_i_not0001(LD_instr/fifo_wr_i_not00011:O) | NONE(*)(LD_instr/fifo_wr_i) | 1 | -LD_instr/Mtrien_Ram_address_i_not0001(LD_instr/Mtrien_Ram_address_i_not0001:O) | NONE(*)(LD_instr/Mtrien_Ram_address_i) | 1 | -LD_instr/etloadinst_cmp_eq0022(LD_instr/etloadinst_FSM_Out31:O) | NONE(*)(LD_instr/base_adrset_i) | 9 | -MPI_CORE_DMA_ARBITER/dma_rd_grant<2>(MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux00041:O) | NONE(*)(LD_instr/ptr_15) | 16 | -LD_instr/count_i_not0001(LD_instr/count_i_not000154:O) | NONE(*)(LD_instr/count_i_0) | 18 | -LD_instr/timeout_not0001(LD_instr/timeout_not0001:O) | NONE(*)(LD_instr/timeout_0) | 8 | -LD_instr/Mtridata_Ram_address_i_not0001(LD_instr/Mtridata_Ram_address_i_not00011:O) | NONE(*)(LD_instr/Mtridata_Ram_address_i_0) | 16 | -LD_instr/etloadinst_cmp_eq00201(LD_instr/etloadinst_FSM_FFd2-In31:O) | BUFG(*)(LD_instr/ADRtmp_0) | 32 | -LD_instr/etloadinst_cmp_eq0019(LD_instr/etloadinst_FSM_FFd3-In210:O) | NONE(*)(LD_instr/Base_AD_8) | 8 | -MPI_CORE_EX1_FSM/ram_rd_or0000(MPI_CORE_EX1_FSM/ram_rd_or0000:O) | NONE(*)(MPI_CORE_EX1_FSM/ram_rd) | 1 | -MPI_CORE_EX1_FSM/ram_wr_or0000(MPI_CORE_EX1_FSM/ram_wr_or00001:O) | NONE(*)(MPI_CORE_EX1_FSM/ram_wr) | 1 | -MPI_CORE_EX1_FSM/AppInitReq_or0000(MPI_CORE_EX1_FSM/AppInitReq_or000032:O) | NONE(*)(MPI_CORE_EX1_FSM/AppInitReq) | 1 | -MPI_CORE_EX1_FSM/Result_1_or0000(MPI_CORE_EX1_FSM/Result_1_or00001:O) | NONE(*)(MPI_CORE_EX1_FSM/Result_1) | 1 | -MPI_CORE_EX1_FSM/ex1_state_mach_FSM_FFd7 | NONE(MPI_CORE_EX1_FSM/ram_data_out_0) | 1 | -MPI_CORE_EX2_FSM/fifo_wr_en_or0000(MPI_CORE_EX2_FSM/fifo_wr_en_or00001:O) | NONE(*)(MPI_CORE_EX2_FSM/switch_port_out_rd_en) | 1 | -MPI_CORE_EX2_FSM/ex2_state_mach_FSM_FFd18 | NONE(MPI_CORE_EX2_FSM/Mtrien_Ram_data) | 1 | -MPI_CORE_EX4_FSM/DS_Ack_or0000(MPI_CORE_EX4_FSM/DS_Ack_or000010:O) | NONE(*)(MPI_CORE_EX4_FSM/DS_Ack) | 1 | -MPI_CORE_EX4_FSM/WeRam_or0000(MPI_CORE_EX4_FSM/WeRam_or000016:O) | NONE(*)(MPI_CORE_EX4_FSM/WeRam) | 1 | -MPI_CORE_EX4_FSM/stInit2_FSM_FFd12 | NONE(MPI_CORE_EX4_FSM/Result_En) | 1 | -MPI_CORE_EX4_FSM/CTR_or0000(MPI_CORE_EX4_FSM/CTR_or0000:O) | NONE(*)(MPI_CORE_EX4_FSM/CTR) | 1 | -MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 | BUFG | 50 | -MPI_CORE_EX4_FSM/stInit2_FSM_FFd5 | NONE(MPI_CORE_EX4_FSM/Initialized) | 5 | -MPI_CORE_EX4_FSM/stInit2_FSM_FFd10 | NONE(MPI_CORE_EX4_FSM/IsMain) | 1 | -MPI_CORE_EX4_FSM/etcmd_FSM_FFd9 | NONE(MPI_CORE_EX4_FSM/cport_out_rd_en) | 3 | -MPI_CORE_EX4_FSM/RankAsked_i_or0000(MPI_CORE_EX4_FSM/RankAsked_i_or000019:O) | NONE(*)(MPI_CORE_EX4_FSM/RankAsked_i) | 1 | -MPI_CORE_EX4_FSM/DS_RDY | NONE(MPI_CORE_EX4_FSM/RankAsked_i_mux0001) | 9 | -MPI_CORE_EX4_FSM/stInit2_FSM_FFd9 | NONE(MPI_CORE_EX4_FSM/MainResp) | 1 | -MPI_CORE_EX4_FSM/CM_RDY | NONE(MPI_CORE_EX4_FSM/EquFlag) | 1 | -MPI_CORE_EX4_FSM/DataRam_or0000(MPI_CORE_EX4_FSM/DataRam_or000019:O) | NONE(*)(MPI_CORE_EX4_FSM/DataRam_0) | 8 | -MPI_CORE_EX4_FSM/NextRank_or0000(MPI_CORE_EX4_FSM/NextRank_or000019_f5:O) | NONE(*)(MPI_CORE_EX4_FSM/nextr_0) | 8 | -MPI_CORE_EX4_FSM/Datalen_or0000(MPI_CORE_EX4_FSM/Datalen_or000019:O) | NONE(*)(MPI_CORE_EX4_FSM/DataToSend_2_0) | 5 | -MPI_CORE_EX4_FSM/DataToSend_0_or0000(MPI_CORE_EX4_FSM/DataToSend_0_or000016:O) | NONE(*)(MPI_CORE_EX4_FSM/DataToSend_0_0) | 6 | -MPI_CORE_EX4_FSM/timeout_i_not0001(MPI_CORE_EX4_FSM/timeout_i_not000164:O) | NONE(*)(MPI_CORE_EX4_FSM/timeout_i_0) | 8 | -MPI_CORE_EX4_FSM/PortNum_i_or0000(MPI_CORE_EX4_FSM/PortNum_i_or000019_f5:O) | NONE(*)(MPI_CORE_EX4_FSM/PortNum_i_0) | 4 | -MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000(MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq00001:O) | NONE(*)(MPI_CORE_EX4_FSM/CmdReceived_2_0) | 8 | -MPI_CORE_EX4_FSM/stInit2_FSM_FFd11 | NONE(MPI_CORE_EX4_FSM/NocMax_0) | 4 | --------------------------------------------------------------------------------------------------+-----------------------------------------------------+-------+ -(*) These 34 clock signal(s) are generated by combinatorial logic, -and XST is not able to identify which are the primary clock signals. -Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. -INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. - -Asynchronous Control Signals Information: ----------------------------------------- -------------------------------------------------------------------------------------------------------------------+------------------------+-------+ -Control Signal | Buffer(FF name) | Load | -------------------------------------------------------------------------------------------------------------------+------------------------+-------+ -reset | IBUF | 13 | -CORE_SCHEDULER/mpi_core_rr_machine/fifo_selected_signal(CORE_SCHEDULER/mpi_core_rr_machine/fifo_selected_signal:Q)| NONE(Ex_EN_1) | 1 | -------------------------------------------------------------------------------------------------------------------+------------------------+-------+ - -Timing Summary: ---------------- -Speed Grade: -5 - - Minimum period: 10.039ns (Maximum Frequency: 99.612MHz) - Minimum input arrival time before clock: 8.389ns - Maximum output required time after clock: 11.634ns - Maximum combinational path delay: 7.591ns - -Timing Detail: --------------- -All values displayed in nanoseconds (ns) - -========================================================================= -Timing constraint: Default period analysis for Clock 'clk' - Clock period: 10.039ns (frequency: 99.612MHz) - Total number of paths / destination ports: 9939 / 747 -------------------------------------------------------------------------- -Delay: 10.039ns (Levels of Logic = 14) - Source: Instruction_Fifo2/fifo_counter_0 (FF) - Destination: Instruction_Fifo1/fifo_counter_5 (FF) - Source Clock: clk rising - Destination Clock: clk rising - - Data Path: Instruction_Fifo2/fifo_counter_0 to Instruction_Fifo1/fifo_counter_5 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - FDRE:C->Q 8 0.514 0.673 fifo_counter_0 (fifo_counter_0) - LUT3_L:I2->LO 1 0.612 0.103 fwft_fsm_state_cmp_eq0001_SW0 (N5) - LUT4:I3->O 12 0.612 0.886 fwft_fsm_state_cmp_eq0001 (empty) - end scope: 'Instruction_Fifo2' - begin scope: 'CORE_SCHEDULER' - begin scope: 'Fifo_empty_MUX' - LUT3:I1->O 17 0.612 0.896 do1 (do) - end scope: 'Fifo_empty_MUX' - end scope: 'CORE_SCHEDULER' - begin scope: 'MPI_CORE_EX1_FSM' - LUT4:I3->O 2 0.612 0.449 fifo_rd_en1 (fifo_rd_en) - end scope: 'MPI_CORE_EX1_FSM' - begin scope: 'CORE_SCHEDULER' - begin scope: 'rd_en_demux' - LUT2:I1->O 11 0.612 0.796 do11 (do1) - end scope: 'rd_en_demux' - end scope: 'CORE_SCHEDULER' - begin scope: 'Instruction_Fifo1' - LUT4_D:I3->O 3 0.612 0.454 Mcount_fifo_counter_cy<1>1 (Mcount_fifo_counter_cy<1>) - LUT4_L:I3->LO 1 0.612 0.103 Mcount_fifo_counter_cy<3>1 (Mcount_fifo_counter_cy<3>) - LUT4:I3->O 1 0.612 0.000 Mcount_fifo_counter_xor<5>11 (Result<5>) - FDRE:D 0.268 fifo_counter_5 - ---------------------------------------- - Total 10.039ns (5.678ns logic, 4.361ns route) - (56.6% logic, 43.4% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'MPI_CORE_DMA_ARBITER/dma_rd_grant<2>' - Clock period: 1.988ns (frequency: 502.930MHz) - Total number of paths / destination ports: 16 / 16 -------------------------------------------------------------------------- -Delay: 1.988ns (Levels of Logic = 1) - Source: LD_instr/ptr_15 (LATCH) - Destination: LD_instr/ptr_15 (LATCH) - Source Clock: MPI_CORE_DMA_ARBITER/dma_rd_grant<2> falling - Destination Clock: MPI_CORE_DMA_ARBITER/dma_rd_grant<2> falling - - Data Path: LD_instr/ptr_15 to LD_instr/ptr_15 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LDE:G->Q 3 0.588 0.520 ptr_15 (ptr_15) - LUT3:I1->O 1 0.612 0.000 ptr_15_mux00061 (ptr_15_mux0006) - LDE:D 0.268 ptr_15 - ---------------------------------------- - Total 1.988ns (1.468ns logic, 0.520ns route) - (73.8% logic, 26.2% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'LD_instr/timeout_not0001' - Clock period: 4.635ns (frequency: 215.766MHz) - Total number of paths / destination ports: 36 / 8 -------------------------------------------------------------------------- -Delay: 4.635ns (Levels of Logic = 3) - Source: LD_instr/timeout_2 (LATCH) - Destination: LD_instr/timeout_6 (LATCH) - Source Clock: LD_instr/timeout_not0001 falling - Destination Clock: LD_instr/timeout_not0001 falling - - Data Path: LD_instr/timeout_2 to LD_instr/timeout_6 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 5 0.588 0.690 timeout_2 (timeout_2) - LUT4:I0->O 6 0.612 0.721 Madd_etloadinst_add0000_cy<3>11 (Madd_etloadinst_add0000_cy<3>) - LUT3:I0->O 2 0.612 0.532 Madd_etloadinst_add0000_cy<5>11 (Madd_etloadinst_add0000_cy<5>) - LUT3:I0->O 1 0.612 0.000 timeout_mux0006<6>1 (timeout_mux0006<6>) - LD:D 0.268 timeout_6 - ---------------------------------------- - Total 4.635ns (2.692ns logic, 1.943ns route) - (58.1% logic, 41.9% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'LD_instr/Mtridata_Ram_address_i_not0001' - Clock period: 8.684ns (frequency: 115.150MHz) - Total number of paths / destination ports: 157 / 16 -------------------------------------------------------------------------- -Delay: 8.684ns (Levels of Logic = 8) - Source: LD_instr/Mtridata_Ram_address_i_3 (LATCH) - Destination: LD_instr/Mtridata_Ram_address_i_12 (LATCH) - Source Clock: LD_instr/Mtridata_Ram_address_i_not0001 falling - Destination Clock: LD_instr/Mtridata_Ram_address_i_not0001 falling - - Data Path: LD_instr/Mtridata_Ram_address_i_3 to LD_instr/Mtridata_Ram_address_i_12 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 3 0.588 0.603 Mtridata_Ram_address_i_3 (Mtridata_Ram_address_i<3>) - LUT4_L:I0->LO 1 0.612 0.103 tb_11_and000012_SW1 (N83) - LUT4:I3->O 4 0.612 0.502 tb_11_and000012 (V_6_and0000) - LUT4:I3->O 5 0.612 0.541 tb_11_and000031 (V_10_and0000) - LUT4:I3->O 1 0.612 0.360 Mtridata_Ram_address_i_mux0000<3>36 (Mtridata_Ram_address_i_mux0000<3>36) - LUT4_L:I3->LO 1 0.612 0.103 Mtridata_Ram_address_i_mux0000<3>85_SW0 (N105) - LUT4:I3->O 1 0.612 0.360 Mtridata_Ram_address_i_mux0000<3>85 (Mtridata_Ram_address_i_mux0000<3>85) - LUT4:I3->O 1 0.612 0.360 Mtridata_Ram_address_i_mux0000<3>129_SW0 (N107) - LUT4:I3->O 1 0.612 0.000 Mtridata_Ram_address_i_mux0000<3>129 (Mtridata_Ram_address_i_mux0000<3>) - LD:D 0.268 Mtridata_Ram_address_i_12 - ---------------------------------------- - Total 8.684ns (5.752ns logic, 2.932ns route) - (66.2% logic, 33.8% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'LD_instr/etloadinst_cmp_eq00201' - Clock period: 6.006ns (frequency: 166.503MHz) - Total number of paths / destination ports: 226 / 32 -------------------------------------------------------------------------- -Delay: 6.006ns (Levels of Logic = 19) - Source: LD_instr/iptr_0 (LATCH) - Destination: LD_instr/ADRtmp_15 (LATCH) - Source Clock: LD_instr/etloadinst_cmp_eq00201 falling - Destination Clock: LD_instr/etloadinst_cmp_eq00201 falling - - Data Path: LD_instr/iptr_0 to LD_instr/ADRtmp_15 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LDE:G->Q 2 0.588 0.532 iptr_0 (iptr_0) - LUT2:I0->O 1 0.612 0.000 Madd_ADRtmp_addsub0000_lut<0> (Madd_ADRtmp_addsub0000_lut<0>) - MUXCY:S->O 1 0.404 0.000 Madd_ADRtmp_addsub0000_cy<0> (Madd_ADRtmp_addsub0000_cy<0>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<1> (Madd_ADRtmp_addsub0000_cy<1>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<2> (Madd_ADRtmp_addsub0000_cy<2>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<3> (Madd_ADRtmp_addsub0000_cy<3>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<4> (Madd_ADRtmp_addsub0000_cy<4>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<5> (Madd_ADRtmp_addsub0000_cy<5>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<6> (Madd_ADRtmp_addsub0000_cy<6>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<7> (Madd_ADRtmp_addsub0000_cy<7>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<8> (Madd_ADRtmp_addsub0000_cy<8>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<9> (Madd_ADRtmp_addsub0000_cy<9>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<10> (Madd_ADRtmp_addsub0000_cy<10>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<11> (Madd_ADRtmp_addsub0000_cy<11>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<12> (Madd_ADRtmp_addsub0000_cy<12>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<13> (Madd_ADRtmp_addsub0000_cy<13>) - MUXCY:CI->O 0 0.052 0.000 Madd_ADRtmp_addsub0000_cy<14> (Madd_ADRtmp_addsub0000_cy<14>) - XORCY:CI->O 1 0.699 0.509 Madd_ADRtmp_addsub0000_xor<15> (ADRtmp_addsub0000<15>) - LUT3:I0->O 2 0.612 0.449 ADRtmp_mux0014<15> (ADRtmp_mux0014<15>) - LUT3:I1->O 1 0.612 0.000 ADRtmp_mux0016<15>1 (ADRtmp_mux0016<15>) - LDE:D 0.268 ADRtmp_15 - ---------------------------------------- - Total 6.006ns (4.516ns logic, 1.490ns route) - (75.2% logic, 24.8% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'MPI_CORE_EX4_FSM/NextRank_or0000' - Clock period: 4.311ns (frequency: 231.941MHz) - Total number of paths / destination ports: 20 / 8 -------------------------------------------------------------------------- -Delay: 4.311ns (Levels of Logic = 5) - Source: MPI_CORE_EX4_FSM/nextr_1 (LATCH) - Destination: MPI_CORE_EX4_FSM/nextr_3 (LATCH) - Source Clock: MPI_CORE_EX4_FSM/NextRank_or0000 rising - Destination Clock: MPI_CORE_EX4_FSM/NextRank_or0000 rising - - Data Path: MPI_CORE_EX4_FSM/nextr_1 to MPI_CORE_EX4_FSM/nextr_3 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 4 0.588 0.651 nextr_1 (nextr_1) - LUT1:I0->O 1 0.612 0.000 Madd_nextr_addsub0000_cy<1>_rt (Madd_nextr_addsub0000_cy<1>_rt) - MUXCY:S->O 1 0.404 0.000 Madd_nextr_addsub0000_cy<1> (Madd_nextr_addsub0000_cy<1>) - MUXCY:CI->O 0 0.052 0.000 Madd_nextr_addsub0000_cy<2> (Madd_nextr_addsub0000_cy<2>) - XORCY:CI->O 1 0.699 0.426 Madd_nextr_addsub0000_xor<3> (nextr_addsub0000<3>) - LUT2:I1->O 1 0.612 0.000 nextr_mux0000<3>1 (nextr_mux0000<3>) - LD_1:D 0.268 nextr_3 - ---------------------------------------- - Total 4.311ns (3.235ns logic, 1.077ns route) - (75.0% logic, 25.0% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000' - Clock period: 2.071ns (frequency: 482.777MHz) - Total number of paths / destination ports: 8 / 8 -------------------------------------------------------------------------- -Delay: 2.071ns (Levels of Logic = 1) - Source: MPI_CORE_EX4_FSM/CmdReceived_2_0 (LATCH) - Destination: MPI_CORE_EX4_FSM/CmdReceived_2_0 (LATCH) - Source Clock: MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 falling - Destination Clock: MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 falling - - Data Path: MPI_CORE_EX4_FSM/CmdReceived_2_0 to MPI_CORE_EX4_FSM/CmdReceived_2_0 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 3 0.588 0.603 CmdReceived_2_0 (CmdReceived_2_0) - LUT4:I0->O 1 0.612 0.000 CmdReceived_2_mux0000<0>2 (CmdReceived_2_mux0000<0>) - LD:D 0.268 CmdReceived_2_0 - ---------------------------------------- - Total 2.071ns (1.468ns logic, 0.603ns route) - (70.9% logic, 29.1% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'MPI_CORE_EX4_FSM/stInit2_FSM_FFd21' - Clock period: 3.772ns (frequency: 265.080MHz) - Total number of paths / destination ports: 272 / 32 -------------------------------------------------------------------------- -Delay: 3.772ns (Levels of Logic = 16) - Source: MPI_CORE_EX4_FSM/nextadr_1 (LATCH) - Destination: MPI_CORE_EX4_FSM/nextadr_15 (LATCH) - Source Clock: MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 falling - Destination Clock: MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 falling - - Data Path: MPI_CORE_EX4_FSM/nextadr_1 to MPI_CORE_EX4_FSM/nextadr_15 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 2 0.588 0.532 nextadr_1 (nextadr_1) - LUT1:I0->O 1 0.612 0.000 Madd_nextadr_add0000_cy<1>_rt (Madd_nextadr_add0000_cy<1>_rt) - MUXCY:S->O 1 0.404 0.000 Madd_nextadr_add0000_cy<1> (Madd_nextadr_add0000_cy<1>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<2> (Madd_nextadr_add0000_cy<2>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<3> (Madd_nextadr_add0000_cy<3>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<4> (Madd_nextadr_add0000_cy<4>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<5> (Madd_nextadr_add0000_cy<5>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<6> (Madd_nextadr_add0000_cy<6>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<7> (Madd_nextadr_add0000_cy<7>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<8> (Madd_nextadr_add0000_cy<8>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<9> (Madd_nextadr_add0000_cy<9>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<10> (Madd_nextadr_add0000_cy<10>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<11> (Madd_nextadr_add0000_cy<11>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<12> (Madd_nextadr_add0000_cy<12>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<13> (Madd_nextadr_add0000_cy<13>) - MUXCY:CI->O 0 0.051 0.000 Madd_nextadr_add0000_cy<14> (Madd_nextadr_add0000_cy<14>) - XORCY:CI->O 1 0.699 0.000 Madd_nextadr_add0000_xor<15> (nextadr_add0000<15>) - LD:D 0.268 nextadr_15 - ---------------------------------------- - Total 3.772ns (3.241ns logic, 0.532ns route) - (85.9% logic, 14.1% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' - Total number of paths / destination ports: 942 / 459 -------------------------------------------------------------------------- -Offset: 8.389ns (Levels of Logic = 8) - Source: switch_port_in_full (PAD) - Destination: MPI_CORE_EX1_FSM/n_2 (FF) - Destination Clock: clk rising - - Data Path: switch_port_in_full to MPI_CORE_EX1_FSM/n_2 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 35 1.106 1.226 switch_port_in_full_IBUF (switch_port_in_full_IBUF) - begin scope: 'MPI_CORE_EX1_FSM' - LUT4:I0->O 13 0.612 0.839 packet_length_and00021 (packet_length_and0002) - LUT4_L:I3->LO 1 0.612 0.103 data_to_send_or0001_SW0_SW0 (N50) - LUT4:I3->O 2 0.612 0.383 data_to_send_or0001 (data_to_send_or0001) - LUT4:I3->O 2 0.612 0.410 n_mux0000<0>123 (n_mux0000<0>123) - LUT3_D:I2->O 2 0.612 0.383 n_mux0000<0>128 (N2) - LUT4:I3->O 1 0.612 0.000 n_mux0000<1>1 (n_mux0000<1>) - FDE:D 0.268 n_2 - ---------------------------------------- - Total 8.389ns (5.046ns logic, 3.343ns route) - (60.1% logic, 39.9% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'MPI_CORE_DMA_ARBITER/dma_rd_grant<2>' - Total number of paths / destination ports: 16 / 16 -------------------------------------------------------------------------- -Offset: 2.515ns (Levels of Logic = 4) - Source: ram_data_out<7> (PAD) - Destination: LD_instr/ptr_15 (LATCH) - Destination Clock: MPI_CORE_DMA_ARBITER/dma_rd_grant<2> falling - - Data Path: ram_data_out<7> to LD_instr/ptr_15 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 4 1.106 0.529 ram_data_out_7_IBUF (ram_data_out_7_IBUF) - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - begin scope: 'LD_instr' - LUT3:I2->O 1 0.612 0.000 ptr_7_mux00041 (ptr_7_mux0004) - LDE:D 0.268 ptr_7 - ---------------------------------------- - Total 2.515ns (1.986ns logic, 0.529ns route) - (79.0% logic, 21.0% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'LD_instr/etloadinst_cmp_eq0022' - Total number of paths / destination ports: 8 / 8 -------------------------------------------------------------------------- -Offset: 1.731ns (Levels of Logic = 2) - Source: instruction<0> (PAD) - Destination: LD_instr/Base_Adr_8 (LATCH) - Destination Clock: LD_instr/etloadinst_cmp_eq0022 falling - - Data Path: instruction<0> to LD_instr/Base_Adr_8 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 1 1.106 0.357 instruction_0_IBUF (instruction_0_IBUF) - begin scope: 'LD_instr' - LDE:D 0.268 Base_Adr_8 - ---------------------------------------- - Total 1.731ns (1.374ns logic, 0.357ns route) - (79.4% logic, 20.6% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'MPI_CORE_EX2_FSM/fifo_wr_en_or0000' - Total number of paths / destination ports: 1 / 1 -------------------------------------------------------------------------- -Offset: 3.133ns (Levels of Logic = 3) - Source: switch_port_out_data_vailaible (PAD) - Destination: MPI_CORE_EX2_FSM/switch_port_out_rd_en (LATCH) - Destination Clock: MPI_CORE_EX2_FSM/fifo_wr_en_or0000 falling - - Data Path: switch_port_out_data_vailaible to MPI_CORE_EX2_FSM/switch_port_out_rd_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 50 1.106 1.147 switch_port_out_data_vailaible_IBUF (switch_port_out_data_vailaible_IBUF) - begin scope: 'MPI_CORE_EX2_FSM' - LUT3:I1->O 1 0.612 0.000 switch_port_out_rd_en_mux00001 (switch_port_out_rd_en_mux0000) - LD:D 0.268 switch_port_out_rd_en - ---------------------------------------- - Total 3.133ns (1.986ns logic, 1.147ns route) - (63.4% logic, 36.6% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'MPI_CORE_EX4_FSM/etcmd_FSM_FFd9' - Total number of paths / destination ports: 1 / 1 -------------------------------------------------------------------------- -Offset: 3.133ns (Levels of Logic = 3) - Source: switch_port_out_data_vailaible (PAD) - Destination: MPI_CORE_EX4_FSM/cport_out_rd_en (LATCH) - Destination Clock: MPI_CORE_EX4_FSM/etcmd_FSM_FFd9 rising - - Data Path: switch_port_out_data_vailaible to MPI_CORE_EX4_FSM/cport_out_rd_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 50 1.106 1.147 switch_port_out_data_vailaible_IBUF (switch_port_out_data_vailaible_IBUF) - begin scope: 'MPI_CORE_EX4_FSM' - LUT4:I1->O 1 0.612 0.000 cport_out_rd_en_mux00001 (cport_out_rd_en_mux0000) - LD_1:D 0.268 cport_out_rd_en - ---------------------------------------- - Total 3.133ns (1.986ns logic, 1.147ns route) - (63.4% logic, 36.6% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000' - Total number of paths / destination ports: 8 / 8 -------------------------------------------------------------------------- -Offset: 2.713ns (Levels of Logic = 3) - Source: switch_port_out_data<0> (PAD) - Destination: MPI_CORE_EX4_FSM/CmdReceived_2_0 (LATCH) - Destination Clock: MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 falling - - Data Path: switch_port_out_data<0> to MPI_CORE_EX4_FSM/CmdReceived_2_0 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 9 1.106 0.727 switch_port_out_data_0_IBUF (switch_port_out_data_0_IBUF) - begin scope: 'MPI_CORE_EX4_FSM' - LUT4:I2->O 1 0.612 0.000 CmdReceived_2_mux0000<0>2 (CmdReceived_2_mux0000<0>) - LD:D 0.268 CmdReceived_2_0 - ---------------------------------------- - Total 2.713ns (1.986ns logic, 0.727ns route) - (73.2% logic, 26.8% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' - Total number of paths / destination ports: 1619 / 48 -------------------------------------------------------------------------- -Offset: 11.634ns (Levels of Logic = 8) - Source: MPI_CORE_EX1_FSM/ex1_state_mach_FSM_FFd9 (FF) - Destination: switch_port_in_data<7> (PAD) - Source Clock: clk rising - - Data Path: MPI_CORE_EX1_FSM/ex1_state_mach_FSM_FFd9 to switch_port_in_data<7> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - FDRS:C->Q 17 0.514 1.045 ex1_state_mach_FSM_FFd9 (ex1_state_mach_FSM_FFd9) - LUT2:I0->O 4 0.612 0.502 n_mux0000<0>221 (N341) - LUT4:I3->O 9 0.612 0.766 switch_port_in_data_mux0000<0>31 (N21) - LUT4:I1->O 8 0.612 0.673 switch_port_in_data_and00001 (switch_port_in_data_not0001_inv) - LUT3:I2->O 1 0.612 0.426 switch_port_in_data<7>LogicTrst22_SW0 (N88) - LUT4:I1->O 1 0.612 0.509 switch_port_in_data<7>LogicTrst22 (switch_port_in_data<7>) - end scope: 'MPI_CORE_EX1_FSM' - LUT4:I0->O 1 0.612 0.357 switch_port_in_data<7>1 (switch_port_in_data_7_OBUF) - OBUF:I->O 3.169 switch_port_in_data_7_OBUF (switch_port_in_data<7>) - ---------------------------------------- - Total 11.634ns (7.355ns logic, 4.279ns route) - (63.2% logic, 36.8% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000' - Total number of paths / destination ports: 34 / 18 -------------------------------------------------------------------------- -Offset: 7.351ns (Levels of Logic = 6) - Source: MPI_CORE_DMA_ARBITER/dma_wr_grant_1_mux0001 (LATCH) - Destination: ram_address_wr<15> (PAD) - Source Clock: MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 falling - - Data Path: MPI_CORE_DMA_ARBITER/dma_wr_grant_1_mux0001 to ram_address_wr<15> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.509 dma_wr_grant_1_mux0001 (dma_wr_grant_1_mux0001) - LUT4:I0->O 38 0.612 1.226 dma_wr_grant_1_mux00041 (dma_wr_grant<1>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I0->O 1 0.612 0.000 dma_wr_address<9>LogicTrst_F (N122) - MUXF5:I0->O 1 0.278 0.357 dma_wr_address<9>LogicTrst (dma_wr_address<9>) - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - OBUF:I->O 3.169 ram_address_wr_9_OBUF (ram_address_wr<9>) - ---------------------------------------- - Total 7.351ns (5.259ns logic, 2.092ns route) - (71.5% logic, 28.5% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000' - Total number of paths / destination ports: 34 / 18 -------------------------------------------------------------------------- -Offset: 8.095ns (Levels of Logic = 5) - Source: MPI_CORE_DMA_ARBITER/dma_wr_grant_3_mux0001 (LATCH) - Destination: ram_we (PAD) - Source Clock: MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 falling - - Data Path: MPI_CORE_DMA_ARBITER/dma_wr_grant_3_mux0001 to ram_we - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.509 dma_wr_grant_3_mux0001 (dma_wr_grant_3_mux0001) - LUT4:I0->O 37 0.612 1.226 dma_wr_grant_3_mux00041 (dma_wr_grant<3>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I0->O 2 0.612 0.410 ram_en_or00001_SW0 (N86) - LUT4:I2->O 1 0.612 0.357 ram_we_and00001 (ram_we_OBUF) - OBUF:I->O 3.169 ram_we_OBUF (ram_we) - ---------------------------------------- - Total 8.095ns (5.593ns logic, 2.502ns route) - (69.1% logic, 30.9% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001' - Total number of paths / destination ports: 18 / 18 -------------------------------------------------------------------------- -Offset: 7.960ns (Levels of Logic = 5) - Source: MPI_CORE_DMA_ARBITER/dma_wr_grant_0_mux0001 (LATCH) - Destination: ram_we (PAD) - Source Clock: MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 rising - - Data Path: MPI_CORE_DMA_ARBITER/dma_wr_grant_0_mux0001 to ram_we - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.509 dma_wr_grant_0_mux0001 (dma_wr_grant_0_mux0001) - LUT4:I0->O 23 0.612 1.091 dma_wr_grant_0_mux00042 (dma_wr_grant<0>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I1->O 2 0.612 0.410 ram_en_or00001_SW0 (N86) - LUT4:I2->O 1 0.612 0.357 ram_we_and00001 (ram_we_OBUF) - OBUF:I->O 3.169 ram_we_OBUF (ram_we) - ---------------------------------------- - Total 7.960ns (5.593ns logic, 2.367ns route) - (70.3% logic, 29.7% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX1_FSM/ram_wr_or0000' - Total number of paths / destination ports: 2 / 2 -------------------------------------------------------------------------- -Offset: 6.135ns (Levels of Logic = 4) - Source: MPI_CORE_EX1_FSM/ram_wr (LATCH) - Destination: ram_we (PAD) - Source Clock: MPI_CORE_EX1_FSM/ram_wr_or0000 rising - - Data Path: MPI_CORE_EX1_FSM/ram_wr to ram_we - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.387 ram_wr (ram_wr) - end scope: 'MPI_CORE_EX1_FSM' - LUT4:I2->O 2 0.612 0.410 ram_en_or00001_SW0 (N86) - LUT4:I2->O 1 0.612 0.357 ram_we_and00001 (ram_we_OBUF) - OBUF:I->O 3.169 ram_we_OBUF (ram_we) - ---------------------------------------- - Total 6.135ns (4.981ns logic, 1.154ns route) - (81.2% logic, 18.8% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX4_FSM/WeRam_or0000' - Total number of paths / destination ports: 2 / 2 -------------------------------------------------------------------------- -Offset: 6.108ns (Levels of Logic = 4) - Source: MPI_CORE_EX4_FSM/WeRam (LATCH) - Destination: ram_we (PAD) - Source Clock: MPI_CORE_EX4_FSM/WeRam_or0000 rising - - Data Path: MPI_CORE_EX4_FSM/WeRam to ram_we - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.360 WeRam (WeRam) - end scope: 'MPI_CORE_EX4_FSM' - LUT4:I3->O 2 0.612 0.410 ram_en_or00001_SW0 (N86) - LUT4:I2->O 1 0.612 0.357 ram_we_and00001 (ram_we_OBUF) - OBUF:I->O 3.169 ram_we_OBUF (ram_we) - ---------------------------------------- - Total 6.108ns (4.981ns logic, 1.127ns route) - (81.5% logic, 18.5% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000' - Total number of paths / destination ports: 34 / 18 -------------------------------------------------------------------------- -Offset: 7.351ns (Levels of Logic = 6) - Source: MPI_CORE_DMA_ARBITER/dma_wr_grant_2_mux0001 (LATCH) - Destination: ram_address_wr<15> (PAD) - Source Clock: MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 falling - - Data Path: MPI_CORE_DMA_ARBITER/dma_wr_grant_2_mux0001 to ram_address_wr<15> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.509 dma_wr_grant_2_mux0001 (dma_wr_grant_2_mux0001) - LUT4:I0->O 38 0.612 1.226 dma_wr_grant_2_mux00041 (dma_wr_grant<2>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I0->O 1 0.612 0.000 dma_wr_address<9>LogicTrst_G (N123) - MUXF5:I1->O 1 0.278 0.357 dma_wr_address<9>LogicTrst (dma_wr_address<9>) - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - OBUF:I->O 3.169 ram_address_wr_9_OBUF (ram_address_wr<9>) - ---------------------------------------- - Total 7.351ns (5.259ns logic, 2.092ns route) - (71.5% logic, 28.5% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'LD_instr/instruction_ack' - Total number of paths / destination ports: 31 / 11 -------------------------------------------------------------------------- -Offset: 7.062ns (Levels of Logic = 4) - Source: Ex_EN_1 (FF) - Destination: switch_port_in_wr_en (PAD) - Source Clock: LD_instr/instruction_ack rising - - Data Path: Ex_EN_1 to switch_port_in_wr_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - FDC:C->Q 7 0.514 0.754 Ex_EN_1 (Ex_EN_1) - LUT3:I0->O 1 0.612 0.000 switch_port_in_data_cmp_eq00001 (switch_port_in_data_cmp_eq00001) - MUXF5:I1->O 9 0.278 0.766 switch_port_in_data_cmp_eq0000_f5 (switch_port_in_data_cmp_eq0000) - LUT4:I1->O 1 0.612 0.357 switch_port_in_wr_en1 (switch_port_in_wr_en_OBUF) - OBUF:I->O 3.169 switch_port_in_wr_en_OBUF (switch_port_in_wr_en) - ---------------------------------------- - Total 7.062ns (5.185ns logic, 1.877ns route) - (73.4% logic, 26.6% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX1_FSM/AppInitReq_or0000' - Total number of paths / destination ports: 21 / 11 -------------------------------------------------------------------------- -Offset: 8.188ns (Levels of Logic = 5) - Source: MPI_CORE_EX1_FSM/AppInitReq (LATCH) - Destination: switch_port_out_rd_en (PAD) - Source Clock: MPI_CORE_EX1_FSM/AppInitReq_or0000 rising - - Data Path: MPI_CORE_EX1_FSM/AppInitReq to switch_port_out_rd_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 3 0.588 0.603 AppInitReq (AppInitReq) - end scope: 'MPI_CORE_EX1_FSM' - LUT2:I0->O 5 0.612 0.690 InitReq1 (Ex_EN<4>) - LUT4:I0->O 11 0.612 0.945 switch_port_out_rd_en11 (N0) - LUT4:I0->O 1 0.612 0.357 switch_port_out_rd_en25 (switch_port_out_rd_en_OBUF) - OBUF:I->O 3.169 switch_port_out_rd_en_OBUF (switch_port_out_rd_en) - ---------------------------------------- - Total 8.188ns (5.593ns logic, 2.595ns route) - (68.3% logic, 31.7% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX4_FSM/stInit2_FSM_FFd5' - Total number of paths / destination ports: 26 / 12 -------------------------------------------------------------------------- -Offset: 8.298ns (Levels of Logic = 5) - Source: MPI_CORE_EX4_FSM/Initialized (LATCH) - Destination: switch_port_out_rd_en (PAD) - Source Clock: MPI_CORE_EX4_FSM/stInit2_FSM_FFd5 falling - - Data Path: MPI_CORE_EX4_FSM/Initialized to switch_port_out_rd_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 8 0.588 0.712 Initialized (Initialized) - end scope: 'MPI_CORE_EX4_FSM' - LUT2:I1->O 5 0.612 0.690 InitReq1 (Ex_EN<4>) - LUT4:I0->O 11 0.612 0.945 switch_port_out_rd_en11 (N0) - LUT4:I0->O 1 0.612 0.357 switch_port_out_rd_en25 (switch_port_out_rd_en_OBUF) - OBUF:I->O 3.169 switch_port_out_rd_en_OBUF (switch_port_out_rd_en) - ---------------------------------------- - Total 8.298ns (5.593ns logic, 2.705ns route) - (67.4% logic, 32.6% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX4_FSM/stInit2_FSM_FFd21' - Total number of paths / destination ports: 41 / 26 -------------------------------------------------------------------------- -Offset: 8.273ns (Levels of Logic = 6) - Source: MPI_CORE_EX4_FSM/RTS_cmd (LATCH) - Destination: switch_port_in_data<5> (PAD) - Source Clock: MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 rising - - Data Path: MPI_CORE_EX4_FSM/RTS_cmd to switch_port_in_data<5> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 7 0.588 0.671 RTS_cmd (RTS_cmd) - LUT3:I1->O 13 0.612 0.988 port_in_data_and00001 (port_in_data_not0001_inv) - LUT3:I0->O 1 0.612 0.000 port_in_data<5>LogicTrst_G (N159) - MUXF5:I1->O 1 0.278 0.387 port_in_data<5>LogicTrst (port_in_data<5>) - end scope: 'MPI_CORE_EX4_FSM' - LUT4:I2->O 1 0.612 0.357 switch_port_in_data<5>1 (switch_port_in_data_5_OBUF) - OBUF:I->O 3.169 switch_port_in_data_5_OBUF (switch_port_in_data<5>) - ---------------------------------------- - Total 8.273ns (5.871ns logic, 2.402ns route) - (71.0% logic, 29.0% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX4_FSM/CTR_or0000' - Total number of paths / destination ports: 25 / 10 -------------------------------------------------------------------------- -Offset: 8.330ns (Levels of Logic = 6) - Source: MPI_CORE_EX4_FSM/CTR (LATCH) - Destination: switch_port_in_data<5> (PAD) - Source Clock: MPI_CORE_EX4_FSM/CTR_or0000 rising - - Data Path: MPI_CORE_EX4_FSM/CTR to switch_port_in_data<5> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 9 0.588 0.727 CTR (CTR) - LUT3:I2->O 13 0.612 0.988 port_in_data_and00001 (port_in_data_not0001_inv) - LUT3:I0->O 1 0.612 0.000 port_in_data<5>LogicTrst_G (N159) - MUXF5:I1->O 1 0.278 0.387 port_in_data<5>LogicTrst (port_in_data<5>) - end scope: 'MPI_CORE_EX4_FSM' - LUT4:I2->O 1 0.612 0.357 switch_port_in_data<5>1 (switch_port_in_data_5_OBUF) - OBUF:I->O 3.169 switch_port_in_data_5_OBUF (switch_port_in_data<5>) - ---------------------------------------- - Total 8.330ns (5.871ns logic, 2.459ns route) - (70.5% logic, 29.5% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX4_FSM/etcmd_FSM_FFd9' - Total number of paths / destination ports: 3 / 2 -------------------------------------------------------------------------- -Offset: 7.096ns (Levels of Logic = 5) - Source: MPI_CORE_EX4_FSM/cport_out_rd_en (LATCH) - Destination: switch_port_out_rd_en (PAD) - Source Clock: MPI_CORE_EX4_FSM/etcmd_FSM_FFd9 rising - - Data Path: MPI_CORE_EX4_FSM/cport_out_rd_en to switch_port_out_rd_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.360 cport_out_rd_en (cport_out_rd_en) - LUT4:I3->O 1 0.612 0.360 port_out_rd_en_SW1 (N122) - LUT4:I3->O 1 0.612 0.426 port_out_rd_en (port_out_rd_en) - end scope: 'MPI_CORE_EX4_FSM' - LUT4:I1->O 1 0.612 0.357 switch_port_out_rd_en25 (switch_port_out_rd_en_OBUF) - OBUF:I->O 3.169 switch_port_out_rd_en_OBUF (switch_port_out_rd_en) - ---------------------------------------- - Total 7.096ns (5.593ns logic, 1.503ns route) - (78.8% logic, 21.2% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX1_FSM/ram_rd_or0000' - Total number of paths / destination ports: 1 / 1 -------------------------------------------------------------------------- -Offset: 6.485ns (Levels of Logic = 5) - Source: MPI_CORE_EX1_FSM/ram_rd (LATCH) - Destination: ram_en (PAD) - Source Clock: MPI_CORE_EX1_FSM/ram_rd_or0000 rising - - Data Path: MPI_CORE_EX1_FSM/ram_rd to ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.509 ram_rd (ram_rd) - end scope: 'MPI_CORE_EX1_FSM' - LUT4:I0->O 1 0.612 0.000 ram_en_or0000382 (ram_en_or0000382) - MUXF5:I0->O 1 0.278 0.360 ram_en_or000038_f5 (ram_en_or000038) - LUT4:I3->O 1 0.612 0.357 ram_en_or000050 (ram_en_OBUF) - OBUF:I->O 3.169 ram_en_OBUF (ram_en) - ---------------------------------------- - Total 6.485ns (5.259ns logic, 1.226ns route) - (81.1% logic, 18.9% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000' - Total number of paths / destination ports: 34 / 17 -------------------------------------------------------------------------- -Offset: 8.200ns (Levels of Logic = 6) - Source: MPI_CORE_DMA_ARBITER/dma_rd_grant_1_mux0001 (LATCH) - Destination: ram_en (PAD) - Source Clock: MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 falling - - Data Path: MPI_CORE_DMA_ARBITER/dma_rd_grant_1_mux0001 to ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.387 dma_rd_grant_1_mux0001 (dma_rd_grant_1_mux0001) - LUT4:I2->O 34 0.612 1.225 dma_rd_grant_1_mux00041 (dma_rd_grant<1>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I0->O 1 0.612 0.000 ram_en_or0000381 (ram_en_or0000381) - MUXF5:I1->O 1 0.278 0.360 ram_en_or000038_f5 (ram_en_or000038) - LUT4:I3->O 1 0.612 0.357 ram_en_or000050 (ram_en_OBUF) - OBUF:I->O 3.169 ram_en_OBUF (ram_en) - ---------------------------------------- - Total 8.200ns (5.871ns logic, 2.329ns route) - (71.6% logic, 28.4% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001' - Total number of paths / destination ports: 18 / 17 -------------------------------------------------------------------------- -Offset: 7.942ns (Levels of Logic = 6) - Source: MPI_CORE_DMA_ARBITER/dma_rd_grant_0_mux0001 (LATCH) - Destination: ram_en (PAD) - Source Clock: MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 rising - - Data Path: MPI_CORE_DMA_ARBITER/dma_rd_grant_0_mux0001 to ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.387 dma_rd_grant_0_mux0001 (dma_rd_grant_0_mux0001) - LUT4:I2->O 20 0.612 0.967 dma_rd_grant_0_mux00041 (dma_rd_grant<0>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I2->O 1 0.612 0.000 ram_en_or0000382 (ram_en_or0000382) - MUXF5:I0->O 1 0.278 0.360 ram_en_or000038_f5 (ram_en_or000038) - LUT4:I3->O 1 0.612 0.357 ram_en_or000050 (ram_en_OBUF) - OBUF:I->O 3.169 ram_en_OBUF (ram_en) - ---------------------------------------- - Total 7.942ns (5.871ns logic, 2.071ns route) - (73.9% logic, 26.1% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000' - Total number of paths / destination ports: 34 / 17 -------------------------------------------------------------------------- -Offset: 8.078ns (Levels of Logic = 6) - Source: MPI_CORE_DMA_ARBITER/dma_rd_grant_3_mux0001 (LATCH) - Destination: ram_en (PAD) - Source Clock: MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 falling - - Data Path: MPI_CORE_DMA_ARBITER/dma_rd_grant_3_mux0001 to ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.387 dma_rd_grant_3_mux0001 (dma_rd_grant_3_mux0001) - LUT4:I2->O 34 0.612 1.103 dma_rd_grant_3_mux00041 (dma_rd_grant<3>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I2->O 1 0.612 0.000 ram_en_or0000381 (ram_en_or0000381) - MUXF5:I1->O 1 0.278 0.360 ram_en_or000038_f5 (ram_en_or000038) - LUT4:I3->O 1 0.612 0.357 ram_en_or000050 (ram_en_OBUF) - OBUF:I->O 3.169 ram_en_OBUF (ram_en) - ---------------------------------------- - Total 8.078ns (5.871ns logic, 2.207ns route) - (72.7% logic, 27.3% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000' - Total number of paths / destination ports: 34 / 17 -------------------------------------------------------------------------- -Offset: 9.115ns (Levels of Logic = 8) - Source: MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux0001 (LATCH) - Destination: ram_en (PAD) - Source Clock: MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 falling - - Data Path: MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux0001 to ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.387 dma_rd_grant_2_mux0001 (dma_rd_grant_2_mux0001) - LUT4:I2->O 128 0.612 1.102 dma_rd_grant_2_mux00041 (dma_rd_grant<2>) - end scope: 'MPI_CORE_DMA_ARBITER' - begin scope: 'LD_instr' - LUT4:I3->O 1 0.612 0.426 Ram_rd_en1 (Ram_rd_en) - end scope: 'LD_instr' - LUT4:I1->O 1 0.612 0.000 ram_en_or0000381 (ram_en_or0000381) - MUXF5:I1->O 1 0.278 0.360 ram_en_or000038_f5 (ram_en_or000038) - LUT4:I3->O 1 0.612 0.357 ram_en_or000050 (ram_en_OBUF) - OBUF:I->O 3.169 ram_en_OBUF (ram_en) - ---------------------------------------- - Total 9.115ns (6.483ns logic, 2.632ns route) - (71.1% logic, 28.9% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX2_FSM/fifo_wr_en_or0000' - Total number of paths / destination ports: 2 / 1 -------------------------------------------------------------------------- -Offset: 6.508ns (Levels of Logic = 5) - Source: MPI_CORE_EX2_FSM/switch_port_out_rd_en (LATCH) - Destination: switch_port_out_rd_en (PAD) - Source Clock: MPI_CORE_EX2_FSM/fifo_wr_en_or0000 falling - - Data Path: MPI_CORE_EX2_FSM/switch_port_out_rd_en to switch_port_out_rd_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 2 0.588 0.532 switch_port_out_rd_en (switch_port_out_rd_en) - end scope: 'MPI_CORE_EX2_FSM' - LUT3:I0->O 1 0.612 0.000 switch_port_out_rd_en131 (switch_port_out_rd_en131) - MUXF5:I1->O 1 0.278 0.360 switch_port_out_rd_en13_f5 (switch_port_out_rd_en13) - LUT4:I3->O 1 0.612 0.357 switch_port_out_rd_en25 (switch_port_out_rd_en_OBUF) - OBUF:I->O 3.169 switch_port_out_rd_en_OBUF (switch_port_out_rd_en) - ---------------------------------------- - Total 6.508ns (5.259ns logic, 1.249ns route) - (80.8% logic, 19.2% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX1_FSM/Result_1_or0000' - Total number of paths / destination ports: 1 / 1 -------------------------------------------------------------------------- -Offset: 4.114ns (Levels of Logic = 2) - Source: MPI_CORE_EX1_FSM/Result_1 (LATCH) - Destination: PushOut<5> (PAD) - Source Clock: MPI_CORE_EX1_FSM/Result_1_or0000 falling - - Data Path: MPI_CORE_EX1_FSM/Result_1 to PushOut<5> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.357 Result_1 (Result_1) - end scope: 'MPI_CORE_EX1_FSM' - OBUF:I->O 3.169 PushOut_5_OBUF (PushOut<5>) - ---------------------------------------- - Total 4.114ns (3.757ns logic, 0.357ns route) - (91.3% logic, 8.7% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX4_FSM/stInit2_FSM_FFd10' - Total number of paths / destination ports: 1 / 1 -------------------------------------------------------------------------- -Offset: 4.114ns (Levels of Logic = 2) - Source: MPI_CORE_EX4_FSM/IsMain (LATCH) - Destination: PushOut<1> (PAD) - Source Clock: MPI_CORE_EX4_FSM/stInit2_FSM_FFd10 falling - - Data Path: MPI_CORE_EX4_FSM/IsMain to PushOut<1> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.357 IsMain (IsMain) - end scope: 'MPI_CORE_EX4_FSM' - OBUF:I->O 3.169 PushOut_1_OBUF (PushOut<1>) - ---------------------------------------- - Total 4.114ns (3.757ns logic, 0.357ns route) - (91.3% logic, 8.7% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_CORE_EX4_FSM/DataToSend_0_or0000' - Total number of paths / destination ports: 6 / 6 -------------------------------------------------------------------------- -Offset: 6.457ns (Levels of Logic = 5) - Source: MPI_CORE_EX4_FSM/DataToSend_0_3 (LATCH) - Destination: switch_port_in_data<3> (PAD) - Source Clock: MPI_CORE_EX4_FSM/DataToSend_0_or0000 rising - - Data Path: MPI_CORE_EX4_FSM/DataToSend_0_3 to switch_port_in_data<3> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 3 0.588 0.454 DataToSend_0_3 (DataToSend_0_3) - LUT4:I3->O 1 0.612 0.000 port_in_data<3>LogicTrst_F (N162) - MUXF5:I0->O 1 0.278 0.387 port_in_data<3>LogicTrst (port_in_data<3>) - end scope: 'MPI_CORE_EX4_FSM' - LUT4:I2->O 1 0.612 0.357 switch_port_in_data<3>1 (switch_port_in_data_3_OBUF) - OBUF:I->O 3.169 switch_port_in_data_3_OBUF (switch_port_in_data<3>) - ---------------------------------------- - Total 6.457ns (5.259ns logic, 1.198ns route) - (81.4% logic, 18.6% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'dma_data_in_not0001' - Total number of paths / destination ports: 8 / 8 -------------------------------------------------------------------------- -Offset: 4.114ns (Levels of Logic = 2) - Source: dma_data_in_7 (LATCH) - Destination: ram_data_in<7> (PAD) - Source Clock: dma_data_in_not0001 falling - - Data Path: dma_data_in_7 to ram_data_in<7> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.357 dma_data_in_7 (dma_data_in_7) - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - OBUF:I->O 3.169 ram_data_in_7_OBUF (ram_data_in<7>) - ---------------------------------------- - Total 4.114ns (3.757ns logic, 0.357ns route) - (91.3% logic, 8.7% route) - -========================================================================= -Timing constraint: Default path analysis - Total number of paths / destination ports: 10 / 10 -------------------------------------------------------------------------- -Delay: 7.591ns (Levels of Logic = 5) - Source: switch_port_in_full (PAD) - Destination: switch_port_in_wr_en (PAD) - - Data Path: switch_port_in_full to switch_port_in_wr_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 35 1.106 1.226 switch_port_in_full_IBUF (switch_port_in_full_IBUF) - begin scope: 'MPI_CORE_EX1_FSM' - LUT4:I0->O 1 0.612 0.509 switch_port_in_wr_en1 (switch_port_in_wr_en) - end scope: 'MPI_CORE_EX1_FSM' - LUT4:I0->O 1 0.612 0.357 switch_port_in_wr_en1 (switch_port_in_wr_en_OBUF) - OBUF:I->O 3.169 switch_port_in_wr_en_OBUF (switch_port_in_wr_en) - ---------------------------------------- - Total 7.591ns (5.499ns logic, 2.092ns route) - (72.4% logic, 27.6% route) - -========================================================================= - - -Total REAL time to Xst completion: 27.00 secs -Total CPU time to Xst completion: 26.61 secs - ---> - -Total memory usage is 346700 kilobytes - -Number of errors : 0 ( 0 filtered) -Number of warnings : 596 ( 0 filtered) -Number of infos : 111 ( 0 filtered) - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.twr =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.twr (revision 17) +++ (revision ) @@ -1,160 +1,0 @@ --------------------------------------------------------------------------------- -Release 12.3 Trace (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 5 --n 3 -fastpaths -xml CORE_MPI.twx CORE_MPI.ncd -o CORE_MPI.twr CORE_MPI.pcf - -Design file: CORE_MPI.ncd -Physical constraint file: CORE_MPI.pcf -Device,package,speed: xc3s1200e,ft256,-5 (PRODUCTION 1.27 2010-09-15) -Report level: verbose report - -Environment Variable Effect --------------------- ------ -NONE No environment variables were set --------------------------------------------------------------------------------- - -INFO:Timing:2698 - No timing constraints found, doing default enumeration. -INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths - option. All paths that are not constrained will be reported in the - unconstrained paths section(s) of the report. -INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on - a 50 Ohm transmission line loading model. For the details of this model, - and for more information on accounting for different loading conditions, - please see the device datasheet. -INFO:Timing:3390 - This architecture does not support a default System Jitter - value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock - Uncertainty calculation. -INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and - 'Phase Error' calculations, these terms will be zero in the Clock - Uncertainty calculation. Please make appropriate modification to - SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase - Error. - - - -Data Sheet report: ------------------ -All values displayed in nanoseconds (ns) - -Setup/Hold to clock clk -------------------------------+------------+------------+------------------+--------+ - |Max Setup to|Max Hold to | | Clock | -Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | -------------------------------+------------+------------+------------------+--------+ -hold_ack | 3.319(R)| -0.085(R)|clkout_OBUF | 0.000| -instruction_en | 5.277(R)| 0.181(R)|clkout_OBUF | 0.000| -ram_data_out<0> | 1.188(R)| 0.201(R)|clkout_OBUF | 0.000| -ram_data_out<1> | 0.504(R)| 0.749(R)|clkout_OBUF | 0.000| -ram_data_out<2> | 1.538(R)| -0.084(R)|clkout_OBUF | 0.000| -ram_data_out<3> | 0.356(R)| 0.861(R)|clkout_OBUF | 0.000| -ram_data_out<4> | 1.084(R)| 0.270(R)|clkout_OBUF | 0.000| -ram_data_out<5> | 1.282(R)| 0.112(R)|clkout_OBUF | 0.000| -ram_data_out<6> | 2.652(R)| -0.981(R)|clkout_OBUF | 0.000| -ram_data_out<7> | 2.074(R)| -0.520(R)|clkout_OBUF | 0.000| -reset | 6.675(R)| 1.317(R)|clkout_OBUF | 0.000| -switch_port_in_empty | 0.141(R)| 1.366(R)|clkout_OBUF | 0.000| -switch_port_in_full | 7.505(R)| 0.772(R)|clkout_OBUF | 0.000| -switch_port_out_data<0> | 3.671(R)| 1.216(R)|clkout_OBUF | 0.000| -switch_port_out_data<1> | 3.525(R)| 1.240(R)|clkout_OBUF | 0.000| -switch_port_out_data<2> | 4.059(R)| 1.054(R)|clkout_OBUF | 0.000| -switch_port_out_data<3> | 3.453(R)| 1.025(R)|clkout_OBUF | 0.000| -switch_port_out_data<4> | 5.184(R)| 0.556(R)|clkout_OBUF | 0.000| -switch_port_out_data<5> | 6.064(R)| 0.826(R)|clkout_OBUF | 0.000| -switch_port_out_data<6> | 5.364(R)| 1.212(R)|clkout_OBUF | 0.000| -switch_port_out_data<7> | 5.569(R)| 0.858(R)|clkout_OBUF | 0.000| -switch_port_out_data_vailaible| 5.067(R)| 1.541(R)|clkout_OBUF | 0.000| -------------------------------+------------+------------+------------------+--------+ - -Clock clk to Pad -----------------------+------------+------------------+--------+ - | clk (edge) | | Clock | -Destination | to PAD |Internal Clock(s) | Phase | -----------------------+------------+------------------+--------+ -PushOut<0> | 8.202(R)|clkout_OBUF | 0.000| -hold_req | 9.533(R)|clkout_OBUF | 0.000| -instruction_fifo_full | 12.737(R)|clkout_OBUF | 0.000| -ram_address_rd<0> | 11.241(R)|clkout_OBUF | 0.000| -ram_address_rd<1> | 11.976(R)|clkout_OBUF | 0.000| -ram_address_rd<2> | 11.592(R)|clkout_OBUF | 0.000| -ram_address_rd<3> | 13.165(R)|clkout_OBUF | 0.000| -ram_address_rd<4> | 11.648(R)|clkout_OBUF | 0.000| -ram_address_rd<5> | 12.980(R)|clkout_OBUF | 0.000| -ram_address_rd<6> | 12.098(R)|clkout_OBUF | 0.000| -ram_address_rd<7> | 13.258(R)|clkout_OBUF | 0.000| -ram_address_rd<8> | 11.949(R)|clkout_OBUF | 0.000| -ram_address_rd<9> | 11.022(R)|clkout_OBUF | 0.000| -ram_address_rd<10> | 14.510(R)|clkout_OBUF | 0.000| -ram_address_rd<11> | 13.370(R)|clkout_OBUF | 0.000| -ram_address_rd<12> | 15.000(R)|clkout_OBUF | 0.000| -ram_address_rd<13> | 12.023(R)|clkout_OBUF | 0.000| -ram_address_rd<14> | 13.047(R)|clkout_OBUF | 0.000| -ram_address_rd<15> | 12.062(R)|clkout_OBUF | 0.000| -ram_address_wr<0> | 13.745(R)|clkout_OBUF | 0.000| -ram_address_wr<1> | 14.168(R)|clkout_OBUF | 0.000| -ram_address_wr<2> | 13.487(R)|clkout_OBUF | 0.000| -ram_address_wr<3> | 13.049(R)|clkout_OBUF | 0.000| -ram_address_wr<4> | 13.597(R)|clkout_OBUF | 0.000| -ram_address_wr<5> | 13.254(R)|clkout_OBUF | 0.000| -ram_address_wr<6> | 13.518(R)|clkout_OBUF | 0.000| -ram_address_wr<7> | 13.610(R)|clkout_OBUF | 0.000| -ram_address_wr<8> | 13.927(R)|clkout_OBUF | 0.000| -ram_address_wr<9> | 13.986(R)|clkout_OBUF | 0.000| -ram_address_wr<10> | 14.360(R)|clkout_OBUF | 0.000| -ram_address_wr<11> | 14.093(R)|clkout_OBUF | 0.000| -ram_address_wr<12> | 14.325(R)|clkout_OBUF | 0.000| -ram_address_wr<13> | 14.020(R)|clkout_OBUF | 0.000| -ram_address_wr<14> | 14.698(R)|clkout_OBUF | 0.000| -ram_address_wr<15> | 14.177(R)|clkout_OBUF | 0.000| -ram_en | 15.786(R)|clkout_OBUF | 0.000| -ram_we | 14.367(R)|clkout_OBUF | 0.000| -switch_port_in_cmd_en | 13.675(R)|clkout_OBUF | 0.000| -switch_port_in_data<0>| 15.755(R)|clkout_OBUF | 0.000| -switch_port_in_data<1>| 15.413(R)|clkout_OBUF | 0.000| -switch_port_in_data<2>| 15.065(R)|clkout_OBUF | 0.000| -switch_port_in_data<3>| 15.706(R)|clkout_OBUF | 0.000| -switch_port_in_data<4>| 17.666(R)|clkout_OBUF | 0.000| -switch_port_in_data<5>| 16.851(R)|clkout_OBUF | 0.000| -switch_port_in_data<6>| 17.239(R)|clkout_OBUF | 0.000| -switch_port_in_data<7>| 17.320(R)|clkout_OBUF | 0.000| -switch_port_in_wr_en | 14.153(R)|clkout_OBUF | 0.000| -switch_port_out_rd_en | 15.970(R)|clkout_OBUF | 0.000| -----------------------+------------+------------------+--------+ - -Clock to Setup on destination clock clk ----------------+---------+---------+---------+---------+ - | Src:Rise| Src:Fall| Src:Rise| Src:Fall| -Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ----------------+---------+---------+---------+---------+ -clk | 7.585| | | | ----------------+---------+---------+---------+---------+ - -Pad to Pad --------------------+----------------------+---------+ -Source Pad |Destination Pad | Delay | --------------------+----------------------+---------+ -clk |clkout | 6.836| -ram_data_out<0> |switch_port_in_data<0>| 6.903| -ram_data_out<1> |switch_port_in_data<1>| 7.039| -ram_data_out<2> |switch_port_in_data<2>| 6.694| -ram_data_out<3> |switch_port_in_data<3>| 7.561| -ram_data_out<4> |switch_port_in_data<4>| 8.919| -ram_data_out<5> |switch_port_in_data<5>| 9.958| -ram_data_out<6> |switch_port_in_data<6>| 10.951| -ram_data_out<7> |switch_port_in_data<7>| 9.270| -switch_port_in_full|switch_port_in_wr_en | 9.334| --------------------+----------------------+---------+ - - -Analysis completed Fri Aug 03 10:51:04 2012 --------------------------------------------------------------------------------- - -Trace Settings: -------------------------- -Trace Settings - -Peak Memory Usage: 203 MB - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.twx =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.twx (revision 17) +++ (revision ) @@ -1,338 +1,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -]> -Release 12.3 Trace (nt64)Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 5 --n 3 -fastpaths -xml CORE_MPI.twx CORE_MPI.ncd -o CORE_MPI.twr CORE_MPI.pcf - -CORE_MPI.ncdCORE_MPI.ncdCORE_MPI.pcfCORE_MPI.pcfxc3s1200e-5PRODUCTION 1.27 2010-09-153INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.clkhold_ack3.319-0.085instruction_en5.2770.181ram_data_out<0>1.1880.201ram_data_out<1>0.5040.749ram_data_out<2>1.538-0.084ram_data_out<3>0.3560.861ram_data_out<4>1.0840.270ram_data_out<5>1.2820.112ram_data_out<6>2.652-0.981ram_data_out<7>2.074-0.520reset6.6751.317switch_port_in_empty0.1411.366switch_port_in_full7.5050.772switch_port_out_data<0>3.6711.216switch_port_out_data<1>3.5251.240switch_port_out_data<2>4.0591.054switch_port_out_data<3>3.4531.025switch_port_out_data<4>5.1840.556switch_port_out_data<5>6.0640.826switch_port_out_data<6>5.3641.212switch_port_out_data<7>5.5690.858switch_port_out_data_vailaible5.0671.541clkclkclk7.585clkclkout6.836ram_data_out<0>switch_port_in_data<0>6.903ram_data_out<1>switch_port_in_data<1>7.039ram_data_out<2>switch_port_in_data<2>6.694ram_data_out<3>switch_port_in_data<3>7.561ram_data_out<4>switch_port_in_data<4>8.919ram_data_out<5>switch_port_in_data<5>9.958ram_data_out<6>switch_port_in_data<6>10.951ram_data_out<7>switch_port_in_data<7>9.270switch_port_in_fullswitch_port_in_wr_en9.334Fri Aug 03 10:51:04 2012 TraceTrace Settings - -Peak Memory Usage: 203 MB - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.unroutes =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.unroutes (revision 17) +++ (revision ) @@ -1,9 +1,0 @@ -Release 12.3 - par M.70d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -Fri Aug 03 10:51:00 2012 - -All signals are completely routed. - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.xpi =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.xpi (revision 17) +++ (revision ) @@ -1,3 +1,0 @@ -PROGRAM=PAR -STATE=ROUTED -TIMESPECS_MET=OFF Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.xst =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI.xst (revision 17) +++ (revision ) @@ -1,56 +1,0 @@ -set -tmpdir "xst/projnav.tmp" -set -xsthdpdir "xst" -run --ifn CORE_MPI.prj --ifmt mixed --ofn CORE_MPI --ofmt NGC --p xc3s1200e-5-ft256 --top CORE_MPI --opt_mode Speed --opt_level 1 --iuc NO --keep_hierarchy Soft --netlist_hierarchy As_Optimized --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case Maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style LUT --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract Yes --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract Yes --resource_sharing YES --async_to_sync NO --mult_style LUT --iobuf YES --max_fanout 100000 --bufg 24 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob Auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_beh.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_beh.prj (revision 17) +++ (revision ) @@ -1,17 +1,0 @@ -vhdl NocLib "../SWITCH_GENERIC_16_16/CoreTypes.vhd" -vhdl work "round_robbin_machine.vhd" -vhdl work "RAM_64.vhd" -vhdl work "Packet_type.vhd" -vhdl work "MUX8.vhd" -vhdl work "MUX1.vhd" -vhdl work "DEMUX1.vhd" -vhdl work "MPI_CORE_SCHEDULER.vhd" -vhdl work "load_instr.vhd" -vhdl work "FIFO_64_FWFT.vhd" -vhdl work "EX4_FSM.vhd" -vhdl work "EX3_FSM.vhd" -vhdl work "EX2_FSM.vhd" -vhdl work "EX1_FSM.vhd" -vhdl work "Ex0_Fsm.vhd" -vhdl work "DMA_ARBITER.vhd" -vhdl work "CORE_MPI.vhd" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_envsettings.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_envsettings.html (revision 17) +++ (revision ) @@ -1,496 +1,0 @@ -Xilinx System Settings Report - -
System Settings

- - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Environment Settings
Environment Variablexstngdbuildmappar
PATHEXT.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
Pathd:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
D:\Xilinx\12.3\ISE_DS\common\bin\nt64;
D:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\CMake 2.8\bin;
C:\qtsdk\mingw\bin;
C:\qtsdk\qtcreator\bin;
C:\Program Files (x86)\Graphviz 2.28\bin;
C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox		d:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
D:\Xilinx\12.3\ISE_DS\common\bin\nt64;
D:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\CMake 2.8\bin;
C:\qtsdk\mingw\bin;
C:\qtsdk\qtcreator\bin;
C:\Program Files (x86)\Graphviz 2.28\bin;
C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox		d:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
D:\Xilinx\12.3\ISE_DS\common\bin\nt64;
D:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\CMake 2.8\bin;
C:\qtsdk\mingw\bin;
C:\qtsdk\qtcreator\bin;
C:\Program Files (x86)\Graphviz 2.28\bin;
C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox		d:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
D:\Xilinx\12.3\ISE_DS\common\bin\nt64;
D:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\CMake 2.8\bin;
C:\qtsdk\mingw\bin;
C:\qtsdk\qtcreator\bin;
C:\Program Files (x86)\Graphviz 2.28\bin;
C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox
XILINXd:\Xilinx\12.3\ISE_DS\ISE\d:\Xilinx\12.3\ISE_DS\ISE\d:\Xilinx\12.3\ISE_DS\ISE\d:\Xilinx\12.3\ISE_DS\ISE\
XILINX_DSPD:\Xilinx\12.3\ISE_DS\ISED:\Xilinx\12.3\ISE_DS\ISED:\Xilinx\12.3\ISE_DS\ISED:\Xilinx\12.3\ISE_DS\ISE
XILINX_EDKD:\Xilinx\12.3\ISE_DS\EDKD:\Xilinx\12.3\ISE_DS\EDKD:\Xilinx\12.3\ISE_DS\EDKD:\Xilinx\12.3\ISE_DS\EDK
XILINX_PLANAHEADD:\Xilinx\12.3\ISE_DS\PlanAheadD:\Xilinx\12.3\ISE_DS\PlanAheadD:\Xilinx\12.3\ISE_DS\PlanAheadD:\Xilinx\12.3\ISE_DS\PlanAhead
- - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn CORE_MPI.prj 
-ifmt mixedMIXED
-ofn CORE_MPI 
-ofmt NGCNGC
-p xc3s1200e-5-ft256 
-top CORE_MPI 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-iucUse synthesis Constraints FileNONO
-keep_hierarchyKeep HierarchySoftNO
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNO
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYES
-write_timing_constraintsWrite Timing ConstraintsNONO
-cross_clock_analysisCross Clock AnalysisNONO
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100%
-bram_utilization_ratioBRAM Utilization Ratio100100%
-verilog2001Verilog 2001YESYES
-fsm_extract YESYES
-fsm_encoding AutoAUTO
-safe_implementation NoNO
-fsm_style LUTLUT
-ram_extract YesYES
-ram_style AutoAUTO
-rom_extract YesYES
-shreg_extract YESYES
-rom_style AutoAUTO
-auto_bram_packing NONO
-resource_sharing YESYES
-async_to_sync NONO
-mult_style LUTAUTO
-iobuf YESYES
-max_fanout 100000500
-bufg 2424
-register_duplication YESYES
-register_balancing NoNO
-optimize_primitives NONO
-use_clock_enable YesYES
-use_sync_set YesYES
-use_sync_reset YesYES
-iob AutoAUTO
-equivalent_register_removal YESYES
-slice_utilization_ratio_maxmargin 50%
- - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
Translation Property Settings
Switch NameProperty NameValueDefault Value
-intstyle iseNone
-dd _ngoNone
-p xc3s1200e-ft256-5None
- - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Map Property Settings
Switch NameProperty NameValueDefault Value
-irUse RLOC ConstraintsOFFOFF
-cmOptimization Strategy (Cover Mode)areaarea
-intstyle iseNone
-o CORE_MPI_map.ncdNone
-prPack I/O Registers/Latches into IOBsoffoff
-p xc3s1200e-ft256-5None
- - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Place and Route Property Settings
Switch NameProperty NameValueDefault Value
-t 11
-intstyle ise 
-olPlace & Route Effort Level (Overall)highstd
-w truefalse
- - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHzIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHzIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHzIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHz
HostGAMOM-PCGAMOM-PCGAMOM-PCGAMOM-PC
OS NameMicrosoft Microsoft Microsoft Microsoft
OS ReleaseService Pack 1 (build 7601)Service Pack 1 (build 7601)Service Pack 1 (build 7601)Service Pack 1 (build 7601)
- Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_map.map =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_map.map (revision 17) +++ (revision ) @@ -1,205 +1,0 @@ -Release 12.3 Map M.70d (nt64) -Xilinx Map Application Log File for Design 'CORE_MPI' - -Design Information ------------------- -Command Line : map -intstyle ise -p xc3s1200e-ft256-5 -cm area -ir off -pr off --c 100 -o CORE_MPI_map.ncd CORE_MPI.ngd CORE_MPI.pcf -Target Device : xc3s1200e -Target Package : ft256 -Target Speed : -5 -Mapper Version : spartan3e -- $Revision: 1.52 $ -Mapped Date : Fri Aug 03 10:50:15 2012 - -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:54 - 'xc3s1200e' is a WebPack part. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. ----------------------------------------------------------------------- -Mapping design into LUTs... -Running directed packing... -Running delay-based LUT packing... -Running related packing... -Updating timing models... -WARNING:PhysDesignRules:372 - Gated clock. Clock net dma_rd_grant<3> is sourced - by a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a combinatorial pin. This - is not good design practice. Use the CE pin to control the loading of data - into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/count_i_not0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - LD_instr/Mtridata_Ram_address_i_not0001 is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - LD_instr/etloadinst_cmp_eq0022 is sourced by a combinatorial pin. This is not - good design practice. Use the CE pin to control the loading of data into the - flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - LD_instr/etloadinst_cmp_eq0019 is sourced by a combinatorial pin. This is not - good design practice. Use the CE pin to control the loading of data into the - flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net MPI_CORE_EX4_FSM/CTR_or0000 - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a combinatorial pin. This - is not good design practice. Use the CE pin to control the loading of data - into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a combinatorial pin. This - is not good design practice. Use the CE pin to control the loading of data - into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/timeout_not0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/fifo_wr_i_not0001 - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a combinatorial pin. This is not - good design practice. Use the CE pin to control the loading of data into the - flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net dma_data_in_not0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a combinatorial pin. This is not - good design practice. Use the CE pin to control the loading of data into the - flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a combinatorial pin. This is not - good design practice. Use the CE pin to control the loading of data into the - flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a combinatorial pin. This is not - good design practice. Use the CE pin to control the loading of data into the - flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. - -Design Summary --------------- - -Design Summary: -Number of errors: 0 -Number of warnings: 33 -Logic Utilization: - Total Number Slice Registers: 598 out of 17,344 3% - Number used as Flip Flops: 340 - Number used as Latches: 258 - Number of 4 input LUTs: 1,291 out of 17,344 7% -Logic Distribution: - Number of occupied Slices: 791 out of 8,672 9% - Number of Slices containing only related logic: 791 out of 791 100% - Number of Slices containing unrelated logic: 0 out of 791 0% - *See NOTES below for an explanation of the effects of unrelated logic. - Total Number of 4 input LUTs: 1,362 out of 17,344 7% - Number used as logic: 1,211 - Number used as a route-thru: 71 - Number used for Dual Port RAMs: 80 - (Two LUTs used per Dual Port RAM) - - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - - Number of bonded IOBs: 95 out of 190 50% - Number of BUFGMUXs: 3 out of 24 12% - -Average Fanout of Non-Clock Nets: 3.64 - -Peak Memory Usage: 274 MB -Total REAL time to MAP completion: 5 secs -Total CPU time to MAP completion: 3 secs - -NOTES: - - Related logic is defined as being logic that shares connectivity - e.g. two - LUTs are "related" if they share common inputs. When assembling slices, - Map gives priority to combine logic that is related. Doing so results in - the best timing performance. - - Unrelated logic shares no connectivity. Map will only begin packing - unrelated logic into a slice once 99% of the slices are occupied through - related logic packing. - - Note that once logic distribution reaches the 99% level through related - logic packing, this does not mean the device is completely utilized. - Unrelated logic packing will then begin, continuing until all usable LUTs - and FFs are occupied. Depending on your timing budget, increased levels of - unrelated logic packing may adversely affect the overall timing performance - of your design. - -Mapping completed. -See MAP report file "CORE_MPI_map.mrp" for details. Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_map.mrp =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_map.mrp (revision 17) +++ (revision ) @@ -1,398 +1,0 @@ -Release 12.3 Map M.70d (nt64) -Xilinx Mapping Report File for Design 'CORE_MPI' - -Design Information ------------------- -Command Line : map -intstyle ise -p xc3s1200e-ft256-5 -cm area -ir off -pr off --c 100 -o CORE_MPI_map.ncd CORE_MPI.ngd CORE_MPI.pcf -Target Device : xc3s1200e -Target Package : ft256 -Target Speed : -5 -Mapper Version : spartan3e -- $Revision: 1.52 $ -Mapped Date : Fri Aug 03 10:50:15 2012 - -Design Summary --------------- -Number of errors: 0 -Number of warnings: 33 -Logic Utilization: - Total Number Slice Registers: 598 out of 17,344 3% - Number used as Flip Flops: 340 - Number used as Latches: 258 - Number of 4 input LUTs: 1,291 out of 17,344 7% -Logic Distribution: - Number of occupied Slices: 791 out of 8,672 9% - Number of Slices containing only related logic: 791 out of 791 100% - Number of Slices containing unrelated logic: 0 out of 791 0% - *See NOTES below for an explanation of the effects of unrelated logic. - Total Number of 4 input LUTs: 1,362 out of 17,344 7% - Number used as logic: 1,211 - Number used as a route-thru: 71 - Number used for Dual Port RAMs: 80 - (Two LUTs used per Dual Port RAM) - - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - - Number of bonded IOBs: 95 out of 190 50% - Number of BUFGMUXs: 3 out of 24 12% - -Average Fanout of Non-Clock Nets: 3.64 - -Peak Memory Usage: 274 MB -Total REAL time to MAP completion: 5 secs -Total CPU time to MAP completion: 3 secs - -NOTES: - - Related logic is defined as being logic that shares connectivity - e.g. two - LUTs are "related" if they share common inputs. When assembling slices, - Map gives priority to combine logic that is related. Doing so results in - the best timing performance. - - Unrelated logic shares no connectivity. Map will only begin packing - unrelated logic into a slice once 99% of the slices are occupied through - related logic packing. - - Note that once logic distribution reaches the 99% level through related - logic packing, this does not mean the device is completely utilized. - Unrelated logic packing will then begin, continuing until all usable LUTs - and FFs are occupied. Depending on your timing budget, increased levels of - unrelated logic packing may adversely affect the overall timing performance - of your design. - -Table of Contents ------------------ -Section 1 - Errors -Section 2 - Warnings -Section 3 - Informational -Section 4 - Removed Logic Summary -Section 5 - Removed Logic -Section 6 - IOB Properties -Section 7 - RPMs -Section 8 - Guide Report -Section 9 - Area Group and Partition Summary -Section 10 - Timing Report -Section 11 - Configuration String Information -Section 12 - Control Set Information -Section 13 - Utilization by Hierarchy - -Section 1 - Errors ------------------- - -Section 2 - Warnings --------------------- -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. -WARNING:PhysDesignRules:372 - Gated clock. Clock net dma_rd_grant<3> is sourced - by a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a combinatorial pin. This - is not good design practice. Use the CE pin to control the loading of data - into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/count_i_not0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - LD_instr/Mtridata_Ram_address_i_not0001 is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - LD_instr/etloadinst_cmp_eq0022 is sourced by a combinatorial pin. This is not - good design practice. Use the CE pin to control the loading of data into the - flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - LD_instr/etloadinst_cmp_eq0019 is sourced by a combinatorial pin. This is not - good design practice. Use the CE pin to control the loading of data into the - flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net MPI_CORE_EX4_FSM/CTR_or0000 - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a combinatorial pin. This - is not good design practice. Use the CE pin to control the loading of data - into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a combinatorial pin. This - is not good design practice. Use the CE pin to control the loading of data - into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/timeout_not0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net LD_instr/fifo_wr_i_not0001 - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a combinatorial pin. This is not - good design practice. Use the CE pin to control the loading of data into the - flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net dma_data_in_not0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a combinatorial pin. This is not - good design practice. Use the CE pin to control the loading of data into the - flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a combinatorial pin. This is not - good design practice. Use the CE pin to control the loading of data into the - flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a combinatorial pin. This is not - good design practice. Use the CE pin to control the loading of data into the - flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a combinatorial pin. This is - not good design practice. Use the CE pin to control the loading of data into - the flip-flop. - -Section 3 - Informational -------------------------- -INFO:Security:54 - 'xc3s1200e' is a WebPack part. -INFO:LIT:243 - Logical network MyRank<0> has no load. -INFO:LIT:395 - The above info message is repeated 47 more times for the - following (max. 5 shown): - MyRank<1>, - MyRank<2>, - MyRank<3>, - instruction_fifo2_full, - packet_ack - To see the details of these info messages, please use the -detail switch. -INFO:MapLib:562 - No environment variables are currently set. -INFO:LIT:244 - All of the single ended outputs in this design are using slew - rate limited output drivers. The delay on speed critical single ended outputs - can be dramatically reduced by designating them as fast outputs. - -Section 4 - Removed Logic Summary ---------------------------------- - 11 block(s) optimized away - -Section 5 - Removed Logic -------------------------- - -Optimized Block(s): -TYPE BLOCK -GND Instruction_Fifo2/XST_GND -GND Instruction_Fifo2/fifo_RAM_64/XST_GND -GND LD_instr/XST_GND -VCC LD_instr/XST_VCC -GND MPI_CORE_DMA_ARBITER/XST_GND -GND MPI_CORE_EX1_FSM/XST_GND -VCC MPI_CORE_EX1_FSM/XST_VCC -GND MPI_CORE_EX2_FSM/XST_GND -GND MPI_CORE_EX4_FSM/XST_GND -VCC MPI_CORE_EX4_FSM/XST_VCC -GND XST_GND - -To enable printing of redundant blocks removed and signals merged, set the -detailed map report option and rerun map. - -Section 6 - IOB Properties --------------------------- - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | -| | | | | Term | Strength | Rate | | | Delay | -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -| PushOut<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| PushOut<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| PushOut<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| PushOut<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| PushOut<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| PushOut<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| barrier_completed | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| clk | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| clkout | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| hold_ack | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| hold_req | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| instruction<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| instruction<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| instruction<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| instruction<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| instruction<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| instruction<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| instruction<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| instruction<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| instruction_en | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| instruction_fifo_full | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| packet_received | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_rd<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_address_wr<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_data_in<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_data_in<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_data_in<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_data_in<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_data_in<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_data_in<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_data_in<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_data_in<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_data_out<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| ram_data_out<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| ram_data_out<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| ram_data_out<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| ram_data_out<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| ram_data_out<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| ram_data_out<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| ram_data_out<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| ram_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ram_we | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| reset | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| switch_port_in_cmd_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| switch_port_in_data<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| switch_port_in_data<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| switch_port_in_data<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| switch_port_in_data<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| switch_port_in_data<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| switch_port_in_data<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| switch_port_in_data<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| switch_port_in_data<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| switch_port_in_empty | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| switch_port_in_full | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| switch_port_in_wr_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| switch_port_out_data<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| switch_port_out_data<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| switch_port_out_data<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| switch_port_out_data<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| switch_port_out_data<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| switch_port_out_data<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| switch_port_out_data<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| switch_port_out_data<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| switch_port_out_data_vailaible | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| switch_port_out_rd_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ - -Section 7 - RPMs ----------------- - -Section 8 - Guide Report ------------------------- -Guide not run on this design. - -Section 9 - Area Group and Partition Summary --------------------------------------------- - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -Area Group Information ----------------------- - - No area groups were found in this design. - ----------------------- - -Section 10 - Timing Report --------------------------- -This design was not run using timing mode. - -Section 11 - Configuration String Details ------------------------------------------ -Use the "-detail" map option to print out Configuration Strings - -Section 12 - Control Set Information ------------------------------------- -No control set information for this architecture. - -Section 13 - Utilization by Hierarchy -------------------------------------- -Use the "-detail" map option to print out the Utilization by Hierarchy section. Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_pad.csv =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_pad.csv (revision 17) +++ (revision ) @@ -1,287 +1,0 @@ -#Release 12.3 - par M.70d (nt64) -#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -#Fri Aug 03 10:51:00 2012 - -# -## NOTE: This file is designed to be imported into a spreadsheet program -# such as Microsoft Excel for viewing, printing and sorting. The | -# character is used as the data field separator. This file is also designed -# to support parsing. -# -#INPUT FILE: CORE_MPI_map.ncd -#OUTPUT FILE: CORE_MPI_pad.csv -#PART TYPE: xc3s1200e -#SPEED GRADE: -5 -#PACKAGE: ft256 -# -# Pinout by Pin Number: -# -# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, -Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity, -A1,,,GND,,,,,,,,,,,, -A2,,,TDI,,,,,,,,,,,, -A3,,IBUF,IP,UNUSED,,0,,,,,,,,, -A4,,DIFFS,IO_L17N_0/VREF_0,UNUSED,,0,,,,,,,,, -A5,,DIFFM,IO_L17P_0,UNUSED,,0,,,,,,,,, -A6,,,VCCAUX,,,,,,,,2.5,,,, -A7,,IOB,IO,UNUSED,,0,,,,,,,,, -A8,,DIFFMI,IP_L10P_0/GCLK8,UNUSED,,0,,,,,,,,, -A9,,DIFFS,IO_L09N_0/GCLK7,UNUSED,,0,,,,,,,,, -A10,,DIFFM,IO_L09P_0/GCLK6,UNUSED,,0,,,,,,,,, -A11,,,VCCAUX,,,,,,,,2.5,,,, -A12,,IOB,IO,UNUSED,,0,,,,,,,,, -A13,,DIFFS,IO_L03N_0/VREF_0,UNUSED,,0,,,,,,,,, -A14,,DIFFS,IO_L01N_0,UNUSED,,0,,,,,,,,, -A15,,,TCK,,,,,,,,,,,, -A16,,,GND,,,,,,,,,,,, -B1,,DIFFM,IO_L01P_3,UNUSED,,3,,,,,,,,, -B2,,DIFFS,IO_L01N_3,UNUSED,,3,,,,,,,,, -B3,,DIFFS,IO_L19N_0/HSWAP,UNUSED,,0,,,,,,,,, -B4,,IOB,IO,UNUSED,,0,,,,,,,,, -B5,,,VCCO_0,,,0,,,,,2.50,,,, -B6,,IOB,IO,UNUSED,,0,,,,,,,,, -B7,,DIFFM,IO_L13P_0,UNUSED,,0,,,,,,,,, -B8,clk,IBUF,IP_L10N_0/GCLK9,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE, -B9,,,GND,,,,,,,,,,,, -B10,,IOB,IO,UNUSED,,0,,,,,,,,, -B11,,DIFFS,IO_L05N_0/VREF_0,UNUSED,,0,,,,,,,,, -B12,,,VCCO_0,,,0,,,,,2.50,,,, -B13,,DIFFM,IO_L03P_0,UNUSED,,0,,,,,,,,, -B14,,DIFFM,IO_L01P_0,UNUSED,,0,,,,,,,,, -B15,,,TMS,,,,,,,,,,,, -B16,,IBUF,IP,UNUSED,,1,,,,,,,,, -C1,,DIFFM,IO_L02P_3,UNUSED,,3,,,,,,,,, -C2,,DIFFS,IO_L02N_3/VREF_3,UNUSED,,3,,,,,,,,, -C3,,DIFFM,IO_L19P_0,UNUSED,,0,,,,,,,,, -C4,,DIFFS,IO_L18N_0,UNUSED,,0,,,,,,,,, -C5,,DIFFM,IO_L18P_0,UNUSED,,0,,,,,,,,, -C6,,DIFFM,IO_L15P_0,UNUSED,,0,,,,,,,,, -C7,,DIFFS,IO_L13N_0,UNUSED,,0,,,,,,,,, -C8,,DIFFM,IO_L11P_0/GCLK10,UNUSED,,0,,,,,,,,, -C9,,DIFFSI,IP_L07N_0,UNUSED,,0,,,,,,,,, -C10,,DIFFMI,IP_L07P_0,UNUSED,,0,,,,,,,,, -C11,,DIFFM,IO_L05P_0,UNUSED,,0,,,,,,,,, -C12,,DIFFSI,IP_L02N_0,UNUSED,,0,,,,,,,,, -C13,,IBUF,IP,UNUSED,,0,,,,,,,,, -C14,,,TDO,,,,,,,,,,,, -C15,,DIFFS,IO_L19N_1/LDC2,UNUSED,,1,,,,,,,,, -C16,ram_data_out<7>,IBUF,IO_L19P_1/LDC1,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -D1,,DIFFM,IO_L05P_3,UNUSED,,3,,,,,,,,, -D2,,IBUF,IP,UNUSED,,3,,,,,,,,, -D3,,,PROG_B,,,,,,,,,,,, -D4,,,VCCINT,,,,,,,,1.2,,,, -D5,,DIFFMI,IP_L16P_0,UNUSED,,0,,,,,,,,, -D6,,DIFFS,IO_L15N_0,UNUSED,,0,,,,,,,,, -D7,,DIFFS,IO_L14N_0/VREF_0,UNUSED,,0,,,,,,,,, -D8,,DIFFS,IO_L11N_0/GCLK11,UNUSED,,0,,,,,,,,, -D9,,IOB,IO/VREF_0,UNUSED,,0,,,,,,,,, -D10,,DIFFM,IO_L06P_0,UNUSED,,0,,,,,,,,, -D11,,DIFFM,IO_L04P_0,UNUSED,,0,,,,,,,,, -D12,,DIFFMI,IP_L02P_0,UNUSED,,0,,,,,,,,, -D13,,,VCCINT,,,,,,,,1.2,,,, -D14,ram_data_out<6>,IBUF,IO_L18N_1/LDC0,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -D15,ram_address_rd<12>,IOB,IO_L18P_1/HDC,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -D16,ram_data_out<5>,IBUF,IP/VREF_1,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -E1,,DIFFS,IO_L05N_3,UNUSED,,3,,,,,,,,, -E2,,,VCCO_3,,,3,,,,,2.50,,,, -E3,,DIFFM,IO_L03P_3,UNUSED,,3,,,,,,,,, -E4,,DIFFS,IO_L03N_3,UNUSED,,3,,,,,,,,, -E5,,,VCCINT,,,,,,,,1.2,,,, -E6,,DIFFSI,IP_L16N_0,UNUSED,,0,,,,,,,,, -E7,,DIFFM,IO_L14P_0,UNUSED,,0,,,,,,,,, -E8,,DIFFM,IO_L12P_0,UNUSED,,0,,,,,,,,, -E9,,DIFFM,IO_L08P_0/GCLK4,UNUSED,,0,,,,,,,,, -E10,,DIFFS,IO_L06N_0,UNUSED,,0,,,,,,,,, -E11,,DIFFS,IO_L04N_0,UNUSED,,0,,,,,,,,, -E12,,,VCCINT,,,,,,,,1.2,,,, -E13,ram_address_rd<14>,IOB,IO_L17P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -E14,ram_data_out<4>,IBUF,IP,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -E15,,,VCCO_1,,,1,,,,,2.50,,,, -E16,ram_address_rd<10>,IOB,IO_L17N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -F1,,,VCCAUX,,,,,,,,2.5,,,, -F2,,IBUF,IP,UNUSED,,3,,,,,,,,, -F3,,DIFFM,IO_L04P_3,UNUSED,,3,,,,,,,,, -F4,,DIFFS,IO_L04N_3/VREF_3,UNUSED,,3,,,,,,,,, -F5,,IBUF,IP,UNUSED,,3,,,,,,,,, -F6,,,GND,,,,,,,,,,,, -F7,,,VCCO_0,,,0,,,,,2.50,,,, -F8,,DIFFS,IO_L12N_0,UNUSED,,0,,,,,,,,, -F9,,DIFFS,IO_L08N_0/GCLK5,UNUSED,,0,,,,,,,,, -F10,,,VCCO_0,,,0,,,,,2.50,,,, -F11,,,GND,,,,,,,,,,,, -F12,ram_address_rd<7>,IOB,IO_L16N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -F13,switch_port_in_data<3>,IOB,IO_L16P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -F14,ram_address_rd<11>,IOB,IO_L15P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -F15,clkout,IOB,IO_L15N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -F16,,,VCCAUX,,,,,,,,2.5,,,, -G1,,IBUF,IP/VREF_3,UNUSED,,3,,,,,,,,, -G2,,DIFFS,IO_L07N_3,UNUSED,,3,,,,,,,,, -G3,,DIFFM,IO_L07P_3,UNUSED,,3,,,,,,,,, -G4,,DIFFS,IO_L06N_3,UNUSED,,3,,,,,,,,, -G5,,DIFFM,IO_L06P_3,UNUSED,,3,,,,,,,,, -G6,,,VCCO_3,,,3,,,,,2.50,,,, -G7,,,GND,,,,,,,,,,,, -G8,,,GND,,,,,,,,,,,, -G9,,,GND,,,,,,,,,,,, -G10,,,GND,,,,,,,,,,,, -G11,,,VCCO_1,,,1,,,,,2.50,,,, -G12,ram_data_out<3>,IBUF,IP,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -G13,ram_address_rd<5>,IOB,IO_L14P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -G14,ram_address_rd<3>,IOB,IO_L14N_1/A0,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -G15,switch_port_in_data<5>,IOB,IO_L13P_1/A2,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -G16,ram_address_rd<15>,IOB,IO_L13N_1/A1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -H1,,IBUF,IP,UNUSED,,3,,,,,,,,, -H2,,,GND,,,,,,,,,,,, -H3,,DIFFM,IO_L09P_3/LHCLK2,UNUSED,,3,,,,,,,,, -H4,,DIFFS,IO_L09N_3/LHCLK3/IRDY2,UNUSED,,3,,,,,,,,, -H5,,DIFFM,IO_L08P_3/LHCLK0,UNUSED,,3,,,,,,,,, -H6,,DIFFS,IO_L08N_3/LHCLK1,UNUSED,,3,,,,,,,,, -H7,,,GND,,,,,,,,,,,, -H8,,,GND,,,,,,,,,,,, -H9,,,GND,,,,,,,,,,,, -H10,,,GND,,,,,,,,,,,, -H11,ram_address_rd<13>,IOB,IO_L12N_1/A3/RHCLK7,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -H12,switch_port_in_data<4>,IOB,IO_L12P_1/A4/RHCLK6,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -H13,ram_data_out<2>,IBUF,IP/VREF_1,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -H14,switch_port_in_data<2>,IOB,IO_L11N_1/A5/RHCLK5,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -H15,ram_address_rd<6>,IOB,IO_L11P_1/A6/RHCLK4/IRDY1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -H16,ram_data_out<1>,IBUF,IP,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -J1,,DIFFM,IO_L12P_3,UNUSED,,3,,,,,,,,, -J2,,DIFFM,IO_L10P_3/LHCLK4/TRDY2,UNUSED,,3,,,,,,,,, -J3,,DIFFS,IO_L10N_3/LHCLK5,UNUSED,,3,,,,,,,,, -J4,,DIFFS,IO_L11N_3/LHCLK7,UNUSED,,3,,,,,,,,, -J5,,DIFFM,IO_L11P_3/LHCLK6,UNUSED,,3,,,,,,,,, -J6,,IBUF,IP,UNUSED,,3,,,,,,,,, -J7,,,GND,,,,,,,,,,,, -J8,,,GND,,,,,,,,,,,, -J9,,,GND,,,,,,,,,,,, -J10,,,GND,,,,,,,,,,,, -J11,instruction_en,IBUF,IP,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -J12,ram_data_out<0>,IBUF,IP,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -J13,ram_address_rd<9>,IOB,IO_L10N_1/A7/RHCLK3/TRDY1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -J14,switch_port_in_data<1>,IOB,IO_L10P_1/A8/RHCLK2,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -J15,,,GND,,,,,,,,,,,, -J16,switch_port_in_data<7>,IOB,IO_L09N_1/A9/RHCLK1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -K1,hold_req,IOB,IO_L12N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -K2,,DIFFM,IO_L13P_3,UNUSED,,3,,,,,,,,, -K3,,DIFFS,IO_L13N_3,UNUSED,,3,,,,,,,,, -K4,,IBUF,IP,UNUSED,,3,,,,,,,,, -K5,,DIFFM,IO_L15P_3,UNUSED,,3,,,,,,,,, -K6,,,VCCO_3,,,3,,,,,2.50,,,, -K7,,,GND,,,,,,,,,,,, -K8,,,GND,,,,,,,,,,,, -K9,,,GND,,,,,,,,,,,, -K10,,,GND,,,,,,,,,,,, -K11,,,VCCO_1,,,1,,,,,2.50,,,, -K12,switch_port_in_data<0>,IOB,IO_L07N_1/A11,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -K13,ram_address_rd<2>,IOB,IO_L07P_1/A12,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -K14,ram_address_rd<4>,IOB,IO_L08N_1/VREF_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -K15,switch_port_in_wr_en,IOB,IO_L08P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -K16,switch_port_in_data<6>,IOB,IO_L09P_1/A10/RHCLK0,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -L1,,,VCCAUX,,,,,,,,2.5,,,, -L2,,DIFFS,IO_L14N_3/VREF_3,UNUSED,,3,,,,,,,,, -L3,,DIFFM,IO_L14P_3,UNUSED,,3,,,,,,,,, -L4,,DIFFS,IO_L17N_3,UNUSED,,3,,,,,,,,, -L5,,DIFFS,IO_L15N_3,UNUSED,,3,,,,,,,,, -L6,,,GND,,,,,,,,,,,, -L7,,,VCCO_2,,,2,,,,,2.50,,,, -L8,ram_address_wr<6>,IOB,IO_L09N_2/D6/GCLK13,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -L9,ram_address_wr<13>,IOB,IO_L13P_2/M0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -L10,,,VCCO_2,,,2,,,,,2.50,,,, -L11,,,GND,,,,,,,,,,,, -L12,hold_ack,IBUF,IO_L05P_1,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -L13,switch_port_in_cmd_en,IOB,IO_L05N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -L14,ram_address_rd<0>,IOB,IO_L06P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -L15,ram_address_rd<1>,IOB,IO_L06N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -L16,,,VCCAUX,,,,,,,,2.5,,,, -M1,,DIFFM,IO_L16P_3,UNUSED,,3,,,,,,,,, -M2,,,VCCO_3,,,3,,,,,2.50,,,, -M3,instruction<0>,IBUF,IP,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE, -M4,ram_data_in<0>,IOB,IO_L17P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -M5,,,VCCINT,,,,,,,,1.2,,,, -M6,ram_data_in<6>,IOB,IO_L05P_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -M7,ram_address_wr<0>,IOB,IO,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -M8,ram_address_wr<5>,IOB,IO_L09P_2/D7/GCLK12,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -M9,ram_address_wr<14>,IOB,IO_L13N_2/DIN/D0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -M10,ram_we,IOB,IO_L15N_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -M11,switch_port_out_data<1>,IBUF,IP_L17N_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -M12,,,VCCINT,,,,,,,,1.2,,,, -M13,switch_port_out_data_vailaible,IBUF,IP,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -M14,switch_port_in_empty,IBUF,IP,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -M15,,,VCCO_1,,,1,,,,,2.50,,,, -M16,ram_address_rd<8>,IOB,IO_L04N_1/VREF_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -N1,,DIFFS,IO_L16N_3,UNUSED,,3,,,,,,,,, -N2,,IBUF,IP/VREF_3,UNUSED,,3,,,,,,,,, -N3,,IBUF,IP,UNUSED,,3,,,,,,,,, -N4,,,VCCINT,,,,,,,,1.2,,,, -N5,ram_data_in<2>,IOB,IO_L03N_2/MOSI/CSI_B,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -N6,ram_data_in<7>,IOB,IO_L05N_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -N7,ram_address_wr<3>,IOB,IO_L07P_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -N8,ram_address_wr<8>,IOB,IO_L10P_2/D4/GCLK14,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -N9,ram_address_wr<11>,IOB,IO_L12N_2/D1/GCLK3,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -N10,instruction<7>,IBUF,IO_L15P_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -N11,switch_port_out_data<0>,IBUF,IP_L17P_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -N12,switch_port_out_data<3>,IBUF,IO_L18N_2/A20,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -N13,,,VCCINT,,,,,,,,1.2,,,, -N14,PushOut<4>,IOB,IO_L03P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -N15,switch_port_in_full,IBUF,IO_L03N_1/VREF_1,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -N16,switch_port_out_rd_en,IOB,IO_L04P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P1,,DIFFS,IO_L18N_3,UNUSED,,3,,,,,,,,, -P2,,DIFFM,IO_L18P_3,UNUSED,,3,,,,,,,,, -P3,,DIFFM,IO_L01P_2/CSO_B,UNUSED,,2,,,,,,,,, -P4,,DIFFS,IO_L01N_2/INIT_B,UNUSED,,2,,,,,,,,, -P5,ram_data_in<1>,IOB,IO_L03P_2/DOUT/BUSY,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P6,ram_address_wr<2>,IOB,IO_L06N_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P7,ram_address_wr<4>,IOB,IO_L07N_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P8,ram_address_wr<9>,IOB,IO_L10N_2/D3/GCLK15,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P9,ram_address_wr<10>,IOB,IO_L12P_2/D2/GCLK2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P10,ram_address_wr<15>,IOB,IO_L14P_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P11,PushOut<5>,IOB,IO_L16N_2/A22,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P12,PushOut<0>,IOB,IO_L18P_2/A21,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P13,switch_port_out_data<6>,IBUF,IO/VREF_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -P14,PushOut<3>,IOB,IO_L20P_2/VS0/A17,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P15,instruction_fifo_full,IOB,IO_L02N_1/A13,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P16,barrier_completed,IOB,IO_L02P_1/A14,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -R1,,DIFFS,IO_L19N_3,UNUSED,,3,,,,,,,,, -R2,,DIFFM,IO_L19P_3,UNUSED,,3,,,,,,,,, -R3,instruction<2>,IBUF,IP_L02N_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -R4,ram_data_in<3>,IOB,IO/VREF_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -R5,,,VCCO_2,,,2,,,,,2.50,,,, -R6,ram_address_wr<1>,IOB,IO_L06P_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -R7,instruction<3>,IBUF,IP_L08P_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -R8,,,GND,,,,,,,,,,,, -R9,instruction<6>,IBUF,IP_L11N_2/M2/GCLK1,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -R10,ram_en,IOB,IO_L14N_2/VREF_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -R11,PushOut<1>,IOB,IO_L16P_2/A23,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -R12,,,VCCO_2,,,2,,,,,2.50,,,, -R13,switch_port_out_data<5>,IBUF,IO_L19N_2/VS1/A18,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -R14,switch_port_out_data<2>,IBUF,IO_L20N_2/CCLK,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -R15,PushOut<2>,IOB,IO_L01N_1/A15,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -R16,packet_received,IOB,IO_L01P_1/A16,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -T1,,,GND,,,,,,,,,,,, -T2,,IBUF,IP,UNUSED,,2,,,,,,,,, -T3,instruction<1>,IBUF,IP_L02P_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -T4,ram_data_in<4>,IOB,IO_L04P_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -T5,ram_data_in<5>,IOB,IO_L04N_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -T6,,,VCCAUX,,,,,,,,2.5,,,, -T7,instruction<4>,IBUF,IP_L08N_2/VREF_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -T8,ram_address_wr<7>,IOB,IO/D5,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -T9,instruction<5>,IBUF,IP_L11P_2/RDWR_B/GCLK0,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -T10,ram_address_wr<12>,IOB,IO/M1,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -T11,,,VCCAUX,,,,,,,,2.5,,,, -T12,reset,IBUF,IO,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -T13,switch_port_out_data<7>,IBUF,IO_L19P_2/VS2/A19,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -T14,switch_port_out_data<4>,IBUF,IP,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -T15,,,DONE,,,,,,,,,,,, -T16,,,GND,,,,,,,,,,,, - -# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, -# -#* Default value. -#** This default Pullup/Pulldown value can be overridden in Bitgen. -#****** Special VCCO requirements may apply. Please consult the device -# family datasheet for specific guideline on VCCO requirements. -# -# -# Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_pad.txt =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_pad.txt (revision 17) +++ (revision ) @@ -1,286 +1,0 @@ -Release 12.3 - par M.70d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -Fri Aug 03 10:51:00 2012 - - -INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: -1. The _pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. -2. The _pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. -3. The .pad file designed for parsing by customers. It uses the "|" as a data field separator. - -INPUT FILE: CORE_MPI_map.ncd -OUTPUT FILE: CORE_MPI_pad.txt -PART TYPE: xc3s1200e -SPEED GRADE: -5 -PACKAGE: ft256 - -Pinout by Pin Number: - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -|Pin Number|Signal Name |Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity| -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -|A1 | | |GND | | | | | | | | | | | | -|A2 | | |TDI | | | | | | | | | | | | -|A3 | |IBUF |IP |UNUSED | |0 | | | | | | | | | -|A4 | |DIFFS |IO_L17N_0/VREF_0 |UNUSED | |0 | | | | | | | | | -|A5 | |DIFFM |IO_L17P_0 |UNUSED | |0 | | | | | | | | | -|A6 | | |VCCAUX | | | | | | | |2.5 | | | | -|A7 | |IOB |IO |UNUSED | |0 | | | | | | | | | -|A8 | |DIFFMI |IP_L10P_0/GCLK8 |UNUSED | |0 | | | | | | | | | -|A9 | |DIFFS |IO_L09N_0/GCLK7 |UNUSED | |0 | | | | | | | | | -|A10 | |DIFFM |IO_L09P_0/GCLK6 |UNUSED | |0 | | | | | | | | | -|A11 | | |VCCAUX | | | | | | | |2.5 | | | | -|A12 | |IOB |IO |UNUSED | |0 | | | | | | | | | -|A13 | |DIFFS |IO_L03N_0/VREF_0 |UNUSED | |0 | | | | | | | | | -|A14 | |DIFFS |IO_L01N_0 |UNUSED | |0 | | | | | | | | | -|A15 | | |TCK | | | | | | | | | | | | -|A16 | | |GND | | | | | | | | | | | | -|B1 | |DIFFM |IO_L01P_3 |UNUSED | |3 | | | | | | | | | -|B2 | |DIFFS |IO_L01N_3 |UNUSED | |3 | | | | | | | | | -|B3 | |DIFFS |IO_L19N_0/HSWAP |UNUSED | |0 | | | | | | | | | -|B4 | |IOB |IO |UNUSED | |0 | | | | | | | | | -|B5 | | |VCCO_0 | | |0 | | | | |2.50 | | | | -|B6 | |IOB |IO |UNUSED | |0 | | | | | | | | | -|B7 | |DIFFM |IO_L13P_0 |UNUSED | |0 | | | | | | | | | -|B8 |clk |IBUF |IP_L10N_0/GCLK9 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE | -|B9 | | |GND | | | | | | | | | | | | -|B10 | |IOB |IO |UNUSED | |0 | | | | | | | | | -|B11 | |DIFFS |IO_L05N_0/VREF_0 |UNUSED | |0 | | | | | | | | | -|B12 | | |VCCO_0 | | |0 | | | | |2.50 | | | | -|B13 | |DIFFM |IO_L03P_0 |UNUSED | |0 | | | | | | | | | -|B14 | |DIFFM |IO_L01P_0 |UNUSED | |0 | | | | | | | | | -|B15 | | |TMS | | | | | | | | | | | | -|B16 | |IBUF |IP |UNUSED | |1 | | | | | | | | | -|C1 | |DIFFM |IO_L02P_3 |UNUSED | |3 | | | | | | | | | -|C2 | |DIFFS |IO_L02N_3/VREF_3 |UNUSED | |3 | | | | | | | | | -|C3 | |DIFFM |IO_L19P_0 |UNUSED | |0 | | | | | | | | | -|C4 | |DIFFS |IO_L18N_0 |UNUSED | |0 | | | | | | | | | -|C5 | |DIFFM |IO_L18P_0 |UNUSED | |0 | | | | | | | | | -|C6 | |DIFFM |IO_L15P_0 |UNUSED | |0 | | | | | | | | | -|C7 | |DIFFS |IO_L13N_0 |UNUSED | |0 | | | | | | | | | -|C8 | |DIFFM |IO_L11P_0/GCLK10 |UNUSED | |0 | | | | | | | | | -|C9 | |DIFFSI |IP_L07N_0 |UNUSED | |0 | | | | | | | | | -|C10 | |DIFFMI |IP_L07P_0 |UNUSED | |0 | | | | | | | | | -|C11 | |DIFFM |IO_L05P_0 |UNUSED | |0 | | | | | | | | | -|C12 | |DIFFSI |IP_L02N_0 |UNUSED | |0 | | | | | | | | | -|C13 | |IBUF |IP |UNUSED | |0 | | | | | | | | | -|C14 | | |TDO | | | | | | | | | | | | -|C15 | |DIFFS |IO_L19N_1/LDC2 |UNUSED | |1 | | | | | | | | | -|C16 |ram_data_out<7> |IBUF |IO_L19P_1/LDC1 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|D1 | |DIFFM |IO_L05P_3 |UNUSED | |3 | | | | | | | | | -|D2 | |IBUF |IP |UNUSED | |3 | | | | | | | | | -|D3 | | |PROG_B | | | | | | | | | | | | -|D4 | | |VCCINT | | | | | | | |1.2 | | | | -|D5 | |DIFFMI |IP_L16P_0 |UNUSED | |0 | | | | | | | | | -|D6 | |DIFFS |IO_L15N_0 |UNUSED | |0 | | | | | | | | | -|D7 | |DIFFS |IO_L14N_0/VREF_0 |UNUSED | |0 | | | | | | | | | -|D8 | |DIFFS |IO_L11N_0/GCLK11 |UNUSED | |0 | | | | | | | | | -|D9 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | | -|D10 | |DIFFM |IO_L06P_0 |UNUSED | |0 | | | | | | | | | -|D11 | |DIFFM |IO_L04P_0 |UNUSED | |0 | | | | | | | | | -|D12 | |DIFFMI |IP_L02P_0 |UNUSED | |0 | | | | | | | | | -|D13 | | |VCCINT | | | | | | | |1.2 | | | | -|D14 |ram_data_out<6> |IBUF |IO_L18N_1/LDC0 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|D15 |ram_address_rd<12> |IOB |IO_L18P_1/HDC |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|D16 |ram_data_out<5> |IBUF |IP/VREF_1 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|E1 | |DIFFS |IO_L05N_3 |UNUSED | |3 | | | | | | | | | -|E2 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|E3 | |DIFFM |IO_L03P_3 |UNUSED | |3 | | | | | | | | | -|E4 | |DIFFS |IO_L03N_3 |UNUSED | |3 | | | | | | | | | -|E5 | | |VCCINT | | | | | | | |1.2 | | | | -|E6 | |DIFFSI |IP_L16N_0 |UNUSED | |0 | | | | | | | | | -|E7 | |DIFFM |IO_L14P_0 |UNUSED | |0 | | | | | | | | | -|E8 | |DIFFM |IO_L12P_0 |UNUSED | |0 | | | | | | | | | -|E9 | |DIFFM |IO_L08P_0/GCLK4 |UNUSED | |0 | | | | | | | | | -|E10 | |DIFFS |IO_L06N_0 |UNUSED | |0 | | | | | | | | | -|E11 | |DIFFS |IO_L04N_0 |UNUSED | |0 | | | | | | | | | -|E12 | | |VCCINT | | | | | | | |1.2 | | | | -|E13 |ram_address_rd<14> |IOB |IO_L17P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|E14 |ram_data_out<4> |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|E15 | | |VCCO_1 | | |1 | | | | |2.50 | | | | -|E16 |ram_address_rd<10> |IOB |IO_L17N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|F1 | | |VCCAUX | | | | | | | |2.5 | | | | -|F2 | |IBUF |IP |UNUSED | |3 | | | | | | | | | -|F3 | |DIFFM |IO_L04P_3 |UNUSED | |3 | | | | | | | | | -|F4 | |DIFFS |IO_L04N_3/VREF_3 |UNUSED | |3 | | | | | | | | | -|F5 | |IBUF |IP |UNUSED | |3 | | | | | | | | | -|F6 | | |GND | | | | | | | | | | | | -|F7 | | |VCCO_0 | | |0 | | | | |2.50 | | | | -|F8 | |DIFFS |IO_L12N_0 |UNUSED | |0 | | | | | | | | | -|F9 | |DIFFS |IO_L08N_0/GCLK5 |UNUSED | |0 | | | | | | | | | -|F10 | | |VCCO_0 | | |0 | | | | |2.50 | | | | -|F11 | | |GND | | | | | | | | | | | | -|F12 |ram_address_rd<7> |IOB |IO_L16N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|F13 |switch_port_in_data<3> |IOB |IO_L16P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|F14 |ram_address_rd<11> |IOB |IO_L15P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|F15 |clkout |IOB |IO_L15N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|F16 | | |VCCAUX | | | | | | | |2.5 | | | | -|G1 | |IBUF |IP/VREF_3 |UNUSED | |3 | | | | | | | | | -|G2 | |DIFFS |IO_L07N_3 |UNUSED | |3 | | | | | | | | | -|G3 | |DIFFM |IO_L07P_3 |UNUSED | |3 | | | | | | | | | -|G4 | |DIFFS |IO_L06N_3 |UNUSED | |3 | | | | | | | | | -|G5 | |DIFFM |IO_L06P_3 |UNUSED | |3 | | | | | | | | | -|G6 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|G7 | | |GND | | | | | | | | | | | | -|G8 | | |GND | | | | | | | | | | | | -|G9 | | |GND | | | | | | | | | | | | -|G10 | | |GND | | | | | | | | | | | | -|G11 | | |VCCO_1 | | |1 | | | | |2.50 | | | | -|G12 |ram_data_out<3> |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|G13 |ram_address_rd<5> |IOB |IO_L14P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|G14 |ram_address_rd<3> |IOB |IO_L14N_1/A0 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|G15 |switch_port_in_data<5> |IOB |IO_L13P_1/A2 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|G16 |ram_address_rd<15> |IOB |IO_L13N_1/A1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|H1 | |IBUF |IP |UNUSED | |3 | | | | | | | | | -|H2 | | |GND | | | | | | | | | | | | -|H3 | |DIFFM |IO_L09P_3/LHCLK2 |UNUSED | |3 | | | | | | | | | -|H4 | |DIFFS |IO_L09N_3/LHCLK3/IRDY2 |UNUSED | |3 | | | | | | | | | -|H5 | |DIFFM |IO_L08P_3/LHCLK0 |UNUSED | |3 | | | | | | | | | -|H6 | |DIFFS |IO_L08N_3/LHCLK1 |UNUSED | |3 | | | | | | | | | -|H7 | | |GND | | | | | | | | | | | | -|H8 | | |GND | | | | | | | | | | | | -|H9 | | |GND | | | | | | | | | | | | -|H10 | | |GND | | | | | | | | | | | | -|H11 |ram_address_rd<13> |IOB |IO_L12N_1/A3/RHCLK7 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|H12 |switch_port_in_data<4> |IOB |IO_L12P_1/A4/RHCLK6 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|H13 |ram_data_out<2> |IBUF |IP/VREF_1 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|H14 |switch_port_in_data<2> |IOB |IO_L11N_1/A5/RHCLK5 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|H15 |ram_address_rd<6> |IOB |IO_L11P_1/A6/RHCLK4/IRDY1|OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|H16 |ram_data_out<1> |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|J1 | |DIFFM |IO_L12P_3 |UNUSED | |3 | | | | | | | | | -|J2 | |DIFFM |IO_L10P_3/LHCLK4/TRDY2 |UNUSED | |3 | | | | | | | | | -|J3 | |DIFFS |IO_L10N_3/LHCLK5 |UNUSED | |3 | | | | | | | | | -|J4 | |DIFFS |IO_L11N_3/LHCLK7 |UNUSED | |3 | | | | | | | | | -|J5 | |DIFFM |IO_L11P_3/LHCLK6 |UNUSED | |3 | | | | | | | | | -|J6 | |IBUF |IP |UNUSED | |3 | | | | | | | | | -|J7 | | |GND | | | | | | | | | | | | -|J8 | | |GND | | | | | | | | | | | | -|J9 | | |GND | | | | | | | | | | | | -|J10 | | |GND | | | | | | | | | | | | -|J11 |instruction_en |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|J12 |ram_data_out<0> |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|J13 |ram_address_rd<9> |IOB |IO_L10N_1/A7/RHCLK3/TRDY1|OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|J14 |switch_port_in_data<1> |IOB |IO_L10P_1/A8/RHCLK2 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|J15 | | |GND | | | | | | | | | | | | -|J16 |switch_port_in_data<7> |IOB |IO_L09N_1/A9/RHCLK1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|K1 |hold_req |IOB |IO_L12N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|K2 | |DIFFM |IO_L13P_3 |UNUSED | |3 | | | | | | | | | -|K3 | |DIFFS |IO_L13N_3 |UNUSED | |3 | | | | | | | | | -|K4 | |IBUF |IP |UNUSED | |3 | | | | | | | | | -|K5 | |DIFFM |IO_L15P_3 |UNUSED | |3 | | | | | | | | | -|K6 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|K7 | | |GND | | | | | | | | | | | | -|K8 | | |GND | | | | | | | | | | | | -|K9 | | |GND | | | | | | | | | | | | -|K10 | | |GND | | | | | | | | | | | | -|K11 | | |VCCO_1 | | |1 | | | | |2.50 | | | | -|K12 |switch_port_in_data<0> |IOB |IO_L07N_1/A11 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|K13 |ram_address_rd<2> |IOB |IO_L07P_1/A12 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|K14 |ram_address_rd<4> |IOB |IO_L08N_1/VREF_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|K15 |switch_port_in_wr_en |IOB |IO_L08P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|K16 |switch_port_in_data<6> |IOB |IO_L09P_1/A10/RHCLK0 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|L1 | | |VCCAUX | | | | | | | |2.5 | | | | -|L2 | |DIFFS |IO_L14N_3/VREF_3 |UNUSED | |3 | | | | | | | | | -|L3 | |DIFFM |IO_L14P_3 |UNUSED | |3 | | | | | | | | | -|L4 | |DIFFS |IO_L17N_3 |UNUSED | |3 | | | | | | | | | -|L5 | |DIFFS |IO_L15N_3 |UNUSED | |3 | | | | | | | | | -|L6 | | |GND | | | | | | | | | | | | -|L7 | | |VCCO_2 | | |2 | | | | |2.50 | | | | -|L8 |ram_address_wr<6> |IOB |IO_L09N_2/D6/GCLK13 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|L9 |ram_address_wr<13> |IOB |IO_L13P_2/M0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|L10 | | |VCCO_2 | | |2 | | | | |2.50 | | | | -|L11 | | |GND | | | | | | | | | | | | -|L12 |hold_ack |IBUF |IO_L05P_1 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|L13 |switch_port_in_cmd_en |IOB |IO_L05N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|L14 |ram_address_rd<0> |IOB |IO_L06P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|L15 |ram_address_rd<1> |IOB |IO_L06N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|L16 | | |VCCAUX | | | | | | | |2.5 | | | | -|M1 | |DIFFM |IO_L16P_3 |UNUSED | |3 | | | | | | | | | -|M2 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|M3 |instruction<0> |IBUF |IP |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE | -|M4 |ram_data_in<0> |IOB |IO_L17P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|M5 | | |VCCINT | | | | | | | |1.2 | | | | -|M6 |ram_data_in<6> |IOB |IO_L05P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|M7 |ram_address_wr<0> |IOB |IO |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|M8 |ram_address_wr<5> |IOB |IO_L09P_2/D7/GCLK12 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|M9 |ram_address_wr<14> |IOB |IO_L13N_2/DIN/D0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|M10 |ram_we |IOB |IO_L15N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|M11 |switch_port_out_data<1> |IBUF |IP_L17N_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|M12 | | |VCCINT | | | | | | | |1.2 | | | | -|M13 |switch_port_out_data_vailaible|IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|M14 |switch_port_in_empty |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|M15 | | |VCCO_1 | | |1 | | | | |2.50 | | | | -|M16 |ram_address_rd<8> |IOB |IO_L04N_1/VREF_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|N1 | |DIFFS |IO_L16N_3 |UNUSED | |3 | | | | | | | | | -|N2 | |IBUF |IP/VREF_3 |UNUSED | |3 | | | | | | | | | -|N3 | |IBUF |IP |UNUSED | |3 | | | | | | | | | -|N4 | | |VCCINT | | | | | | | |1.2 | | | | -|N5 |ram_data_in<2> |IOB |IO_L03N_2/MOSI/CSI_B |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|N6 |ram_data_in<7> |IOB |IO_L05N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|N7 |ram_address_wr<3> |IOB |IO_L07P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|N8 |ram_address_wr<8> |IOB |IO_L10P_2/D4/GCLK14 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|N9 |ram_address_wr<11> |IOB |IO_L12N_2/D1/GCLK3 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|N10 |instruction<7> |IBUF |IO_L15P_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|N11 |switch_port_out_data<0> |IBUF |IP_L17P_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|N12 |switch_port_out_data<3> |IBUF |IO_L18N_2/A20 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|N13 | | |VCCINT | | | | | | | |1.2 | | | | -|N14 |PushOut<4> |IOB |IO_L03P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|N15 |switch_port_in_full |IBUF |IO_L03N_1/VREF_1 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|N16 |switch_port_out_rd_en |IOB |IO_L04P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P1 | |DIFFS |IO_L18N_3 |UNUSED | |3 | | | | | | | | | -|P2 | |DIFFM |IO_L18P_3 |UNUSED | |3 | | | | | | | | | -|P3 | |DIFFM |IO_L01P_2/CSO_B |UNUSED | |2 | | | | | | | | | -|P4 | |DIFFS |IO_L01N_2/INIT_B |UNUSED | |2 | | | | | | | | | -|P5 |ram_data_in<1> |IOB |IO_L03P_2/DOUT/BUSY |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P6 |ram_address_wr<2> |IOB |IO_L06N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P7 |ram_address_wr<4> |IOB |IO_L07N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P8 |ram_address_wr<9> |IOB |IO_L10N_2/D3/GCLK15 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P9 |ram_address_wr<10> |IOB |IO_L12P_2/D2/GCLK2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P10 |ram_address_wr<15> |IOB |IO_L14P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P11 |PushOut<5> |IOB |IO_L16N_2/A22 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P12 |PushOut<0> |IOB |IO_L18P_2/A21 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P13 |switch_port_out_data<6> |IBUF |IO/VREF_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|P14 |PushOut<3> |IOB |IO_L20P_2/VS0/A17 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P15 |instruction_fifo_full |IOB |IO_L02N_1/A13 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P16 |barrier_completed |IOB |IO_L02P_1/A14 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|R1 | |DIFFS |IO_L19N_3 |UNUSED | |3 | | | | | | | | | -|R2 | |DIFFM |IO_L19P_3 |UNUSED | |3 | | | | | | | | | -|R3 |instruction<2> |IBUF |IP_L02N_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|R4 |ram_data_in<3> |IOB |IO/VREF_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|R5 | | |VCCO_2 | | |2 | | | | |2.50 | | | | -|R6 |ram_address_wr<1> |IOB |IO_L06P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|R7 |instruction<3> |IBUF |IP_L08P_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|R8 | | |GND | | | | | | | | | | | | -|R9 |instruction<6> |IBUF |IP_L11N_2/M2/GCLK1 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|R10 |ram_en |IOB |IO_L14N_2/VREF_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|R11 |PushOut<1> |IOB |IO_L16P_2/A23 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|R12 | | |VCCO_2 | | |2 | | | | |2.50 | | | | -|R13 |switch_port_out_data<5> |IBUF |IO_L19N_2/VS1/A18 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|R14 |switch_port_out_data<2> |IBUF |IO_L20N_2/CCLK |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|R15 |PushOut<2> |IOB |IO_L01N_1/A15 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|R16 |packet_received |IOB |IO_L01P_1/A16 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|T1 | | |GND | | | | | | | | | | | | -|T2 | |IBUF |IP |UNUSED | |2 | | | | | | | | | -|T3 |instruction<1> |IBUF |IP_L02P_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|T4 |ram_data_in<4> |IOB |IO_L04P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|T5 |ram_data_in<5> |IOB |IO_L04N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|T6 | | |VCCAUX | | | | | | | |2.5 | | | | -|T7 |instruction<4> |IBUF |IP_L08N_2/VREF_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|T8 |ram_address_wr<7> |IOB |IO/D5 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|T9 |instruction<5> |IBUF |IP_L11P_2/RDWR_B/GCLK0 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|T10 |ram_address_wr<12> |IOB |IO/M1 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|T11 | | |VCCAUX | | | | | | | |2.5 | | | | -|T12 |reset |IBUF |IO |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|T13 |switch_port_out_data<7> |IBUF |IO_L19P_2/VS2/A19 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|T14 |switch_port_out_data<4> |IBUF |IP |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|T15 | | |DONE | | | | | | | | | | | | -|T16 | | |GND | | | | | | | | | | | | -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -* Default value. -** This default Pullup/Pulldown value can be overridden in Bitgen. -****** Special VCCO requirements may apply. Please consult the device - family datasheet for specific guideline on VCCO requirements. - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_summary.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_summary.html (revision 17) +++ (revision ) @@ -1,192 +1,0 @@ -Xilinx Design Summary - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MPICORETEST Project Status (08/03/2012 - 19:01:09)
Project File:MPI_CORE_COMPONENTS.xiseParser Errors: No Errors
Module Name:CORE_MPIImplementation State:Synthesized (Stopped)
Target Device:xc6slx100t-3fgg484
  • Errors:
 
Product Version:ISE 12.3
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 - 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: - -System Settings -
  • Final Timing Score:
 
- - - - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers59817,3443% 
    Number used as Flip Flops340   
    Number used as Latches258   
Number of 4 input LUTs1,29117,3447% 
Number of occupied Slices7918,6729% 
    Number of Slices containing only related logic791791100% 
    Number of Slices containing unrelated logic07910% 
Total Number of 4 input LUTs1,36217,3447% 
    Number used as logic1,211   
    Number used as a route-thru71   
    Number used for Dual Port RAMs80   
Number of bonded IOBs9519050% 
Number of BUFGMUXs32412% 
Average Fanout of Non-Clock Nets3.64   
- - - - 
- - - - - - - - - - - - - - - - - -
Performance Summary [-]
Final Timing Score:0 (Setup: 0, Hold: 0)Pinout Data:Pinout Report
Routing Results: -All Signals Completely RoutedClock Data:Clock Report
Timing Constraints: -All Constraints Met  
- - - - 
- - - - - - - - - - - -
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentFri 3. Aug 10:50:10 2012   
Translation ReportCurrentFri 3. Aug 10:50:14 201205 Warnings (5 new)0
Map ReportCurrentFri 3. Aug 10:50:21 2012033 Warnings (33 new)4 Infos (2 new)
Place and Route ReportCurrentFri 3. Aug 10:51:00 2012018 Warnings (18 new)4 Infos (0 new)
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentFri 3. Aug 10:51:04 2012005 Infos (0 new)
Bitgen Report     
- 
- - -
Secondary Reports [-]
Report NameStatusGenerated
- - -
Date Generated: 08/03/2012 - 19:02:25
- Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_summary.xml =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_summary.xml (revision 17) +++ (revision ) @@ -1,10 +1,0 @@ - - - - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_usage.xml =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_usage.xml (revision 17) +++ (revision ) @@ -1,43 +1,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_vhdl.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/CORE_MPI_vhdl.prj (revision 17) +++ (revision ) @@ -1,17 +1,0 @@ -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\CoreTypes.vhd" -vhdl work "C:\Core MPI\CORE_MPI\round_robbin_machine.vhd" -vhdl work "C:\Core MPI\CORE_MPI\RAM_64.vhd" -vhdl work "C:\Core MPI\CORE_MPI\Packet_type.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MUX8.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MUX1.vhd" -vhdl work "C:\Core MPI\CORE_MPI\DEMUX1.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MPI_CORE_SCHEDULER.vhd" -vhdl work "C:\Core MPI\CORE_MPI\load_instr.vhd" -vhdl work "C:\Core MPI\CORE_MPI\FIFO_64_FWFT.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX4_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX3_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX2_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX1_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\Ex0_Fsm.vhd" -vhdl work "C:\Core MPI\CORE_MPI\DMA_ARBITER.vhd" -vhdl work "C:\Core MPI\CORE_MPI\CORE_MPI.vhd" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST.cmd_log =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST.cmd_log (revision 17) +++ (revision ) @@ -1,1 +1,0 @@ -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MPICORETEST.xst" -ofn "C:/Core MPI/CORE_MPI/MPICORETEST.syr" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST.fdo =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST.fdo (revision 17) +++ (revision ) @@ -1,107 +1,0 @@ -###################################################################### -## -## Filename: MPICORETEST.fdo -## Created on: Mon Oct 01 19:06:13 Paris, Madrid (heure d’été) 2012 -## -## Auto generated by Project Navigator for Behavioral Simulation -## -## ---------------------DONOT EDIT THIS FILE------------------------- -## You may want to add additional commands to control the simulation -## in the user specific do file (.udo) which is automatically -## generated in the project directory and will not be removed on -## subsequent simulation flows run from Project Navigator. -## ---------------------DONOT EDIT THIS FILE------------------------- -## -###################################################################### -# -# Create work library -# -vlib work -# -# Compile sources -# -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/CoreTypes.vhd" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/RAM_256.vhd" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/Arbiter.vhd" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/Crossbit.vhd" -vcom -explicit -93 "round_robbin_machine.vhd" -vcom -explicit -93 "RAM_64.vhd" -vcom -explicit -93 "Packet_type.vhd" -vcom -explicit -93 "MUX8.vhd" -vcom -explicit -93 "MUX1.vhd" -vcom -explicit -93 "DEMUX1.vhd" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/Scheduler.vhd" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/Crossbar.vhd" -vcom -explicit -93 "MPI_CORE_SCHEDULER.vhd" -vcom -explicit -93 "load_instr.vhd" -vcom -explicit -93 "FIFO_64_FWFT.vhd" -vcom -explicit -93 "EX4_FSM.vhd" -vcom -explicit -93 "EX3_FSM.vhd" -vcom -explicit -93 "EX2_FSM.vhd" -vcom -explicit -93 "EX1_FSM.vhd" -vcom -explicit -93 "Ex0_Fsm.vhd" -vcom -explicit -93 "DMA_ARBITER.vhd" -vlib NocLib -vcom -explicit -93 -work NocLib "../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" -vcom -explicit -93 "CORE_MPI.vhd" -vcom -explicit -93 "RAM_32_32.vhd" -vcom -explicit -93 "MPI_RMA.vhd" -vcom -explicit -93 "MPI_NOC.vhd" -vcom -explicit -93 "MPICORETEST.vhd" -# -# Call vsim to invoke simulator -# -vsim -voptargs="+acc" -t 1ps -lib work work.MPICORETEST -# -# Source the wave do file -# -do {MPICORETEST_wave.fdo} -# -# Set the window types -# -view wave -view structure -view signals -# -# Source the user do file -# -do {MPICORETEST.udo} -# -# Run simulation for this time -# -run 1000ns -# -# End -# Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST.lso =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST.lso (revision 17) +++ (revision ) @@ -1,2 +1,0 @@ -NocLib -work Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST.prj (revision 17) +++ (revision ) @@ -1,44 +1,0 @@ -vhdl NocLib "../SWITCH_GENERIC_16_16/CoreTypes.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/RAM_256.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Arbiter.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Crossbit.vhd" -vhdl work "round_robbin_machine.vhd" -vhdl work "RAM_64.vhd" -vhdl work "Packet_type.vhd" -vhdl work "MUX8.vhd" -vhdl work "MUX1.vhd" -vhdl work "DEMUX1.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Scheduler.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Crossbar.vhd" -vhdl work "MPI_CORE_SCHEDULER.vhd" -vhdl work "load_instr.vhd" -vhdl work "FIFO_64_FWFT.vhd" -vhdl work "EX4_FSM.vhd" -vhdl work "EX3_FSM.vhd" -vhdl work "EX2_FSM.vhd" -vhdl work "EX1_FSM.vhd" -vhdl work "Ex0_Fsm.vhd" -vhdl work "DMA_ARBITER.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" -vhdl work "CORE_MPI.vhd" -vhdl work "RAM_32_32.vhd" -vhdl work "MPI_NOC.vhd" -vhdl work "MPICORETEST.vhd" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST.syr =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST.syr (revision 17) +++ (revision ) @@ -1,249 +1,0 @@ -Release 12.3 - xst M.70d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. ---> Parameter TMPDIR set to xst/projnav.tmp - - -Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.09 secs - ---> Parameter xsthdpdir set to xst - - -Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.10 secs - ---> Reading design: MPICORETEST.prj - -TABLE OF CONTENTS - 1) Synthesis Options Summary - 2) HDL Compilation - 3) Design Hierarchy Analysis - 4) HDL Analysis - 5) HDL Synthesis - 5.1) HDL Synthesis Report - 6) Advanced HDL Synthesis - 6.1) Advanced HDL Synthesis Report - 7) Low Level Synthesis - 8) Partition Report - 9) Final Report - 9.1) Device utilization summary - 9.2) Partition Resource Summary - 9.3) TIMING REPORT - - -========================================================================= -* Synthesis Options Summary * -========================================================================= ----- Source Parameters -Input File Name : "MPICORETEST.prj" -Input Format : mixed -Ignore Synthesis Constraint File : NO - ----- Target Parameters -Output File Name : "MPICORETEST" -Output Format : NGC -Target Device : xc3s1200e-5-ft256 - ----- Source Options -Top Module Name : MPICORETEST -Automatic FSM Extraction : YES -FSM Encoding Algorithm : Auto -Safe Implementation : No -FSM Style : LUT -RAM Extraction : Yes -RAM Style : Auto -ROM Extraction : Yes -Mux Style : Auto -Decoder Extraction : YES -Priority Encoder Extraction : Yes -Shift Register Extraction : YES -Logical Shifter Extraction : YES -XOR Collapsing : YES -ROM Style : Auto -Mux Extraction : Yes -Resource Sharing : YES -Asynchronous To Synchronous : NO -Multiplier Style : LUT -Automatic Register Balancing : No - ----- Target Options -Add IO Buffers : YES -Global Maximum Fanout : 100000 -Add Generic Clock Buffer(BUFG) : 24 -Register Duplication : YES -Slice Packing : YES -Optimize Instantiated Primitives : NO -Use Clock Enable : Yes -Use Synchronous Set : Yes -Use Synchronous Reset : Yes -Pack IO Registers into IOBs : Auto -Equivalent register Removal : YES - ----- General Options -Optimization Goal : Speed -Optimization Effort : 1 -Keep Hierarchy : Soft -Netlist Hierarchy : As_Optimized -RTL Output : Yes -Global Optimization : AllClockNets -Read Cores : YES -Write Timing Constraints : NO -Cross Clock Analysis : NO -Hierarchy Separator : / -Bus Delimiter : <> -Case Specifier : Maintain -Slice Utilization Ratio : 100 -BRAM Utilization Ratio : 100 -Verilog 2001 : YES -Auto BRAM Packing : NO -Slice Utilization Ratio Delta : 5 - -========================================================================= - - -========================================================================= -* HDL Compilation * -========================================================================= -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/Arbiter.vhd" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/RAM_256.vhd" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/Crossbit.vhd" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/CoreTypes.vhd" in Library NocLib. -Package compiled. -Package body compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/Crossbar.vhd" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/Scheduler.vhd" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/round_robbin_machine.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/MUX1.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/DEMUX1.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/MUX8.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" in Library NocLib. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/Packet_type.vhd" in Library work. -Package compiled. -Package body compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/RAM_64.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/FIFO_64_FWFT.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/load_instr.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/Ex0_Fsm.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/EX1_FSM.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/EX2_FSM.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/EX3_FSM.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/EX4_FSM.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/DMA_ARBITER.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/MPI_CORE_SCHEDULER.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/MPI_NOC.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/RAM_32_32.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. -Compiling vhdl file "C:/Core MPI/CORE_MPI/MPICORETEST.vhd" in Library work. -Entity compiled. -ERROR:HDLParsers:1015 - "C:/Core MPI/CORE_MPI/MPICORETEST.vhd" Line 196. Wait for statement unsupported. -ERROR:HDLParsers:1015 - "C:/Core MPI/CORE_MPI/MPICORETEST.vhd" Line 198. Wait for statement unsupported. -ERROR:HDLParsers:1015 - "C:/Core MPI/CORE_MPI/MPICORETEST.vhd" Line 204. Wait for statement unsupported. -ERROR:HDLParsers:1015 - "C:/Core MPI/CORE_MPI/MPICORETEST.vhd" Line 206. Wait for statement unsupported. ---> - -Total memory usage is 286304 kilobytes - -Number of errors : 4 ( 0 filtered) -Number of warnings : 0 ( 0 filtered) -Number of infos : 0 ( 0 filtered) - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST.xst =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST.xst (revision 17) +++ (revision ) @@ -1,56 +1,0 @@ -set -tmpdir "xst/projnav.tmp" -set -xsthdpdir "xst" -run --ifn MPICORETEST.prj --ifmt mixed --ofn MPICORETEST --ofmt NGC --p xc3s1200e-5-ft256 --top MPICORETEST --opt_mode Speed --opt_level 1 --iuc NO --keep_hierarchy Soft --netlist_hierarchy As_Optimized --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case Maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style LUT --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract Yes --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract Yes --resource_sharing YES --async_to_sync NO --mult_style LUT --iobuf YES --max_fanout 100000 --bufg 24 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob Auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST_summary.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST_summary.html (revision 17) +++ (revision ) @@ -1,83 +1,0 @@ -Xilinx Design Summary - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MPICORETEST Project Status (08/03/2012 - 19:01:09)
Project File:MPI_CORE_COMPONENTS.xiseParser Errors: No Errors
Module Name:MPICORETESTImplementation State:Synthesized (Stopped)
Target Device:xc6slx100t-3fgg484
  • Errors:
 
Product Version:ISE 12.3
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 - 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: - -System Settings -
  • Final Timing Score:
 
- - - - - - - - - - - - 
- - - - - - - - - - - -
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentFri 3. Aug 10:13:12 2012   
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
- 
- - -
Secondary Reports [-]
Report NameStatusGenerated
- - -
Date Generated: 08/03/2012 - 19:02:25
- Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST_vhdl.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPICORETEST_vhdl.prj (revision 17) +++ (revision ) @@ -1,44 +1,0 @@ -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\CoreTypes.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\RAM_256.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\Arbiter.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER9_9.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER8_8.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER7_7.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER6_6.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER5_5.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER4_4.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER3_3.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER2_2.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER16_16.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER15_15.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER14_14.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER13_13.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER12_12.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER11_11.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER10_10.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\FIFO_256_FWFT.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\Crossbit.vhd" -vhdl work "C:\Core MPI\CORE_MPI\round_robbin_machine.vhd" -vhdl work "C:\Core MPI\CORE_MPI\RAM_64.vhd" -vhdl work "C:\Core MPI\CORE_MPI\Packet_type.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MUX8.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MUX1.vhd" -vhdl work "C:\Core MPI\CORE_MPI\DEMUX1.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\Scheduler.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\OUTPUT_PORT_MODULE.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\INPUT_PORT_MODULE.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\Crossbar.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MPI_CORE_SCHEDULER.vhd" -vhdl work "C:\Core MPI\CORE_MPI\load_instr.vhd" -vhdl work "C:\Core MPI\CORE_MPI\FIFO_64_FWFT.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX4_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX3_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX2_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX1_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\Ex0_Fsm.vhd" -vhdl work "C:\Core MPI\CORE_MPI\DMA_ARBITER.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SWITCH_GEN.vhd" -vhdl work "C:\Core MPI\CORE_MPI\CORE_MPI.vhd" -vhdl work "C:\Core MPI\CORE_MPI\RAM_32_32.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MPI_NOC.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MPICORETEST.vhd" Index: /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_CORE_COMPONENTS.gise =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_CORE_COMPONENTS.gise (revision 17) +++ /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_CORE_COMPONENTS.gise (revision 18) @@ -23,322 +23,15 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.bld =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.bld (revision 17) +++ (revision ) @@ -1,59 +1,0 @@ -Release 12.3 ngdbuild M.70d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -Command Line: d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe --intstyle ise -dd _ngo -nt timestamp -i -p xc3s1200e-ft256-5 MPI_NOC.ngc -MPI_NOC.ngd - -Reading NGO file "C:/Core MPI/CORE_MPI/MPI_NOC.ngc" ... -Gathering constraint information from source properties... -Done. - -Resolving constraint associations... -Checking Constraint Associations... -Done... - -Checking expanded design ... -WARNING:NgdBuild:452 - logical net 'connect_core[2].hardmpi/MyRank<0>' has no - driver -WARNING:NgdBuild:452 - logical net 'connect_core[2].hardmpi/MyRank<1>' has no - driver -WARNING:NgdBuild:452 - logical net 'connect_core[2].hardmpi/MyRank<2>' has no - driver -WARNING:NgdBuild:452 - logical net 'connect_core[2].hardmpi/MyRank<3>' has no - driver -WARNING:NgdBuild:452 - logical net - 'connect_core[2].hardmpi/instruction_fifo2_full' has no driver -WARNING:NgdBuild:452 - logical net 'connect_core[2].hardmpi/packet_ack' has no - driver -WARNING:NgdBuild:452 - logical net 'connect_core[1].hardmpi/MyRank<0>' has no - driver -WARNING:NgdBuild:452 - logical net 'connect_core[1].hardmpi/MyRank<1>' has no - driver -WARNING:NgdBuild:452 - logical net 'connect_core[1].hardmpi/MyRank<2>' has no - driver -WARNING:NgdBuild:452 - logical net 'connect_core[1].hardmpi/MyRank<3>' has no - driver -WARNING:NgdBuild:452 - logical net - 'connect_core[1].hardmpi/instruction_fifo2_full' has no driver -WARNING:NgdBuild:452 - logical net 'connect_core[1].hardmpi/packet_ack' has no - driver - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -NGDBUILD Design Results Summary: - Number of errors: 0 - Number of warnings: 12 - -Total memory usage is 153860 kilobytes - -Writing NGD file "MPI_NOC.ngd" ... -Total REAL time to NGDBUILD completion: 3 sec -Total CPU time to NGDBUILD completion: 3 sec - -Writing NGDBUILD log file "MPI_NOC.bld"... Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.cmd_log =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.cmd_log (revision 17) +++ (revision ) @@ -1,6 +1,0 @@ -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MPI_NOC.xst" -ofn "C:/Core MPI/CORE_MPI/MPI_NOC.syr" -ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1200e-ft256-5 "MPI_NOC.ngc" MPI_NOC.ngd -map -intstyle ise -p xc3s1200e-ft256-5 -cm area -ir off -pr off -c 100 -o MPI_NOC_map.ncd MPI_NOC.ngd MPI_NOC.pcf -par -w -intstyle ise -ol high -t 1 MPI_NOC_map.ncd MPI_NOC.ncd MPI_NOC.pcf -trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml MPI_NOC.twx MPI_NOC.ncd -o MPI_NOC.twr MPI_NOC.pcf -trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml MPI_NOC_preroute.twx MPI_NOC_map.ncd -o MPI_NOC_preroute.twr MPI_NOC.pcf -ucf MPI_NOC.ucf Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.lso =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.lso (revision 17) +++ (revision ) @@ -1,2 +1,0 @@ -NocLib -work Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.pcf =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.pcf (revision 17) +++ (revision ) @@ -1,9 +1,0 @@ -//! ************************************************************************** -// Written by: Map M.70d on Fri Aug 03 10:15:54 2012 -//! ************************************************************************** - -SCHEMATIC START; -NET "MPI_Node_in_1__clk_BUFGP/IBUFG" BEL - "MPI_Node_in_1__clk_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT; -SCHEMATIC END; - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.prj (revision 17) +++ (revision ) @@ -1,42 +1,0 @@ -vhdl NocLib "../SWITCH_GENERIC_16_16/CoreTypes.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/RAM_256.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Arbiter.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Crossbit.vhd" -vhdl work "round_robbin_machine.vhd" -vhdl work "RAM_64.vhd" -vhdl work "Packet_type.vhd" -vhdl work "MUX8.vhd" -vhdl work "MUX1.vhd" -vhdl work "DEMUX1.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Scheduler.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Crossbar.vhd" -vhdl work "MPI_CORE_SCHEDULER.vhd" -vhdl work "load_instr.vhd" -vhdl work "FIFO_64_FWFT.vhd" -vhdl work "EX4_FSM.vhd" -vhdl work "EX3_FSM.vhd" -vhdl work "EX2_FSM.vhd" -vhdl work "EX1_FSM.vhd" -vhdl work "Ex0_Fsm.vhd" -vhdl work "DMA_ARBITER.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" -vhdl work "CORE_MPI.vhd" -vhdl work "MPI_NOC.vhd" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.syr =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.syr (revision 17) +++ (revision ) @@ -1,4101 +1,0 @@ -Release 12.3 - xst M.70d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. ---> Parameter TMPDIR set to xst/projnav.tmp - - -Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.09 secs - ---> Parameter xsthdpdir set to xst - - -Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.09 secs - ---> Reading design: MPI_NOC.prj - -TABLE OF CONTENTS - 1) Synthesis Options Summary - 2) HDL Compilation - 3) Design Hierarchy Analysis - 4) HDL Analysis - 5) HDL Synthesis - 5.1) HDL Synthesis Report - 6) Advanced HDL Synthesis - 6.1) Advanced HDL Synthesis Report - 7) Low Level Synthesis - 8) Partition Report - 9) Final Report - 9.1) Device utilization summary - 9.2) Partition Resource Summary - 9.3) TIMING REPORT - - -========================================================================= -* Synthesis Options Summary * -========================================================================= ----- Source Parameters -Input File Name : "MPI_NOC.prj" -Input Format : mixed -Ignore Synthesis Constraint File : NO - ----- Target Parameters -Output File Name : "MPI_NOC" -Output Format : NGC -Target Device : xc3s1200e-5-ft256 - ----- Source Options -Top Module Name : MPI_NOC -Automatic FSM Extraction : YES -FSM Encoding Algorithm : Auto -Safe Implementation : No -FSM Style : LUT -RAM Extraction : Yes -RAM Style : Auto -ROM Extraction : Yes -Mux Style : Auto -Decoder Extraction : YES -Priority Encoder Extraction : Yes -Shift Register Extraction : YES -Logical Shifter Extraction : YES -XOR Collapsing : YES -ROM Style : Auto -Mux Extraction : Yes -Resource Sharing : YES -Asynchronous To Synchronous : NO -Multiplier Style : LUT -Automatic Register Balancing : No - ----- Target Options -Add IO Buffers : YES -Global Maximum Fanout : 100000 -Add Generic Clock Buffer(BUFG) : 24 -Register Duplication : YES -Slice Packing : YES -Optimize Instantiated Primitives : NO -Use Clock Enable : Yes -Use Synchronous Set : Yes -Use Synchronous Reset : Yes -Pack IO Registers into IOBs : Auto -Equivalent register Removal : YES - ----- General Options -Optimization Goal : Speed -Optimization Effort : 1 -Keep Hierarchy : Soft -Netlist Hierarchy : As_Optimized -RTL Output : Yes -Global Optimization : AllClockNets -Read Cores : YES -Write Timing Constraints : NO -Cross Clock Analysis : NO -Hierarchy Separator : / -Bus Delimiter : <> -Case Specifier : Maintain -Slice Utilization Ratio : 100 -BRAM Utilization Ratio : 100 -Verilog 2001 : YES -Auto BRAM Packing : NO -Slice Utilization Ratio Delta : 5 - -========================================================================= - - -========================================================================= -* HDL Compilation * -========================================================================= -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/Arbiter.vhd" in Library NocLib. -Architecture behavioral of Entity arbiter is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/RAM_256.vhd" in Library NocLib. -Architecture behavioral of Entity ram_256 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler2_2 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler3_3 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler4_4 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler5_5 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler6_6 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler7_7 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler8_8 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler9_9 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler10_10 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler11_11 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler12_12 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler13_13 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler14_14 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler15_15 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD" in Library NocLib. -Architecture behavioral of Entity scheduler16_16 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/Crossbit.vhd" in Library NocLib. -Architecture behavioral of Entity crossbit is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd" in Library NocLib. -Architecture behavioral of Entity fifo_256_fwft is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/CoreTypes.vhd" in Library NocLib. -Architecture coretypes of Entity coretypes is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" in Library NocLib. -Architecture behavioral of Entity input_port_module is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd" in Library NocLib. -Architecture behavioral_description of Entity output_port_module is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/Crossbar.vhd" in Library NocLib. -Architecture behavioral of Entity crossbar is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/Scheduler.vhd" in Library NocLib. -Architecture behavioral of Entity scheduler is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/round_robbin_machine.vhd" in Library work. -Architecture behavioral of Entity round_robbin_machine is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/MUX1.vhd" in Library work. -Architecture behavioral of Entity mux1 is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/DEMUX1.vhd" in Library work. -Architecture behavioral of Entity demux1 is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/MUX8.vhd" in Library work. -Architecture behavioral of Entity mux8 is up to date. -Compiling vhdl file "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" in Library NocLib. -Architecture behavioral of Entity switch_gen is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/Packet_type.vhd" in Library work. -Architecture packet_type of Entity packet_type is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/RAM_64.vhd" in Library work. -Architecture behavioral of Entity ram_64 is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/FIFO_64_FWFT.vhd" in Library work. -Architecture behavioral of Entity fifo_64_fwft is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/load_instr.vhd" in Library work. -Architecture behavioral of Entity load_instr is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/Ex0_Fsm.vhd" in Library work. -Architecture behavioral of Entity ex0_fsm is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/EX1_FSM.vhd" in Library work. -Architecture behavioral of Entity ex1_fsm is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/EX2_FSM.vhd" in Library work. -Architecture behavioral of Entity ex2_fsm is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/EX3_FSM.vhd" in Library work. -Architecture behavioral of Entity ex3_fsm is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/EX4_FSM.vhd" in Library work. -Architecture behavioral of Entity ex4_fsm is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/DMA_ARBITER.vhd" in Library work. -Architecture behavioral of Entity dma_arbiter is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/MPI_CORE_SCHEDULER.vhd" in Library work. -Architecture behavioral of Entity mpi_core_scheduler is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" in Library work. -Architecture structural of Entity core_mpi is up to date. -Compiling vhdl file "C:/Core MPI/CORE_MPI/MPI_NOC.vhd" in Library work. -Architecture structural of Entity mpi_noc is up to date. - -========================================================================= -* Design Hierarchy Analysis * -========================================================================= -Analyzing hierarchy for entity in library (architecture ) with generics. - NPROC = 2 - -Analyzing hierarchy for entity in library (architecture ) with generics. - number_of_ports = 2 - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ) with generics. - Port_num = 1 - number_of_ports = 2 - -Analyzing hierarchy for entity in library (architecture ) with generics. - Port_num = 2 - number_of_ports = 2 - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ) with generics. - number_of_crossbar_ports = 2 - -Analyzing hierarchy for entity in library (architecture ) with generics. - number_of_ports = 2 - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ) with generics. - nprocs = "0100" - pid = "0001" - -Analyzing hierarchy for entity in library (architecture ) with generics. - nprocs = "00000011" - pid = "00000001" - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ) with generics. - number_of_ports = 2 - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - -Analyzing hierarchy for entity in library (architecture ). - - -========================================================================= -* HDL Analysis * -========================================================================= -Analyzing generic Entity in library (Architecture ). - NPROC = 2 -WARNING:Xst:753 - "C:/Core MPI/CORE_MPI/MPI_NOC.vhd" line 136: Unconnected output port 'clkout' of component 'CORE_MPI'. -WARNING:Xst:753 - "C:/Core MPI/CORE_MPI/MPI_NOC.vhd" line 136: Unconnected output port 'clkout' of component 'CORE_MPI'. -Entity analyzed. Unit generated. - -Analyzing generic Entity in library (Architecture ). - number_of_ports = 2 -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port3_pulse_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port4_pulse_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port5_pulse_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port6_pulse_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port7_pulse_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port8_pulse_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port9_pulse_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port10_pulse_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port11_pulse_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port12_pulse_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port13_pulse_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port14_pulse_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port15_pulse_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port16_pulse_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port3_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port4_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port5_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port6_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port7_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port8_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port9_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port10_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port11_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port12_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port13_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port14_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port15_out' of component 'Crossbar'. -WARNING:Xst:753 - "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" line 6280: Unconnected output port 'Port16_out' of component 'Crossbar'. -Entity analyzed. Unit generated. - -Analyzing generic Entity in library (Architecture ). - Port_num = 1 - number_of_ports = 2 -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing generic Entity in library (Architecture ). - Port_num = 2 - number_of_ports = 2 -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing generic Entity in library (Architecture ). - number_of_crossbar_ports = 2 -Entity analyzed. Unit generated. - -Analyzing generic Entity in library (Architecture ). - number_of_ports = 2 -Entity analyzed. Unit generated. - -Analyzing generic Entity in library (Architecture ). - number_of_ports = 2 -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -WARNING:Xst:753 - "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" line 408: Unconnected output port 'OvFus' of component 'EX0_FSM'. -INFO:Xst:1561 - "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" line 468: Mux is complete : default of case is discarded -WARNING:Xst:753 - "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" line 522: Unconnected output port 'pid_nprocs' of component 'EX3_FSM'. -WARNING:Xst:819 - "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" line 581: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: - -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -WARNING:Xst:819 - "C:/Core MPI/CORE_MPI/Ex0_Fsm.vhd" line 82: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: - , -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -WARNING:Xst:819 - "C:/Core MPI/CORE_MPI/EX1_FSM.vhd" line 287: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: - -INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. -Entity analyzed. Unit generated. - -Analyzing generic Entity in library (Architecture ). - nprocs = "0100" - pid = "0001" -INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. -Entity analyzed. Unit generated. - -Analyzing generic Entity in library (Architecture ). - nprocs = "00000011" - pid = "00000001" -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch. -INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch. -INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch. -INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch. -INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register > in unit has a constant value of 00000011 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. -INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - - -========================================================================= -* HDL Synthesis * -========================================================================= - -Performing bidirectional port resolution... -INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. - -Synthesizing Unit . - Related source file is "C:/Core MPI/SWITCH_GENERIC_16_16/RAM_256.vhd". - Found 256x8-bit dual-port RAM for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/SWITCH_GENERIC_16_16/Crossbit.vhd". -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/SWITCH_GENERIC_16_16/Arbiter.vhd". -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/load_instr.vhd". - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 7 | - | Transitions | 39 | - | Inputs | 23 | - | Outputs | 9 | - | Clock | clk (rising_edge) | - | Reset | etloadinst$or0000 (positive) | - | Reset type | synchronous | - | Reset State | init | - | Power Up State | init | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- -WARNING:Xst:737 - Found 16-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 16-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 16-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 16-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:736 - Found 16-bit latch for signal created at line 183. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. - Using one-hot encoding for signal . -WARNING:Xst:736 - Found 1-bit latch for signal created at line 183. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 19-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 1-bit register for signal . - Found 16-bit adder for signal . - Found 1-bit register for signal . - Found 19-bit register for signal . - Found 8-bit adder for signal created at line 308. - Found 8-bit tristate buffer for signal . - Found 16-bit adder for signal created at line 203. - Found 16-bit tristate buffer for signal . - Summary: - inferred 1 Finite State Machine(s). - inferred 46 D-type flip-flop(s). - inferred 3 Adder/Subtractor(s). - inferred 24 Tristate(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/Ex0_Fsm.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 1. - Using one-hot encoding for signal . -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 32-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Summary: - inferred 70 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/EX1_FSM.vhd". - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 18 | - | Transitions | 58 | - | Inputs | 21 | - | Outputs | 22 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | fifo_select | - | Power Up State | fifo_select | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 8-bit tristate buffer for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 9-bit comparator greater for signal created at line 195. - Found 4-bit comparator less for signal created at line 267. - Found 8-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 107. - Found 8-bit register for signal . - Found 8-bit addsub for signal created at line 107. - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 268. - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 198. - Summary: - inferred 1 Finite State Machine(s). - inferred 68 D-type flip-flop(s). - inferred 4 Adder/Subtractor(s). - inferred 2 Comparator(s). - inferred 8 Tristate(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/EX2_FSM.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0000. -INFO:Xst:1799 - State execute_spawn is never reached in FSM . - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 18 | - | Transitions | 51 | - | Inputs | 20 | - | Outputs | 18 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | fetch_packet_type | - | Power Up State | fetch_packet_type | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- -WARNING:Xst:736 - Found 8-bit latch for signal created at line 244. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. - Using one-hot encoding for signal . -WARNING:Xst:736 - Found 1-bit latch for signal created at line 244. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 8-bit tristate buffer for signal . - Found 4-bit register for signal . - Found 8-bit register for signal . - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 154. - Found 9-bit comparator greater for signal created at line 151. - Found 5-bit comparator less for signal created at line 195. - Found 4-bit register for signal . - Found 4-bit adder for signal created at line 97. - Found 8-bit register for signal . - Found 8-bit subtractor for signal created at line 97. - Summary: - inferred 1 Finite State Machine(s). - inferred 40 D-type flip-flop(s). - inferred 3 Adder/Subtractor(s). - inferred 2 Comparator(s). - inferred 8 Tristate(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/EX3_FSM.vhd". -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 00000011. - Found 8-bit register for signal . - Found 8-bit up counter for signal . - Summary: - inferred 1 Counter(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/EX4_FSM.vhd". -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0000. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0000. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0000. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value 00000000. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal <7:4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 21 | - | Inputs | 9 | - | Outputs | 7 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | r_wait | - | Power Up State | r_wait | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 9 | - | Transitions | 23 | - | Inputs | 8 | - | Outputs | 11 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | cmdstart | - | Power Up State | cmdstart | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 13 | - | Inputs | 5 | - | Outputs | 7 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | s_init | - | Power Up State | s_init | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 14 | - | Transitions | 31 | - | Inputs | 12 | - | Outputs | 15 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | asynchronous | - | Reset State | init | - | Power Up State | init | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- -WARNING:Xst:737 - Found 4-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 16-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 31-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 4-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 16-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -WARNING:Xst:737 - Found 4-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 4-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 2-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 4-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 31-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 8-bit tristate buffer for signal . - Found 4-bit register for signal . - Found 8-bit 4-to-1 multiplexer for signal <$varindex0000> created at line 635. - Found 2-bit adder carry out for signal created at line 638. - Found 1-bit register for signal . - Found 4-bit comparator equal for signal created at line 641. - Found 8-bit register for signal . - Found 8-bit subtractor for signal created at line 737. - Found 8-bit register for signal . - Found 8-bit register for signal >. - Found 8-bit register for signal >. - Found 8-bit register for signal . - Found 8-bit adder for signal created at line 689. - Found 8-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 8-bit adder for signal created at line 728. - Found 4-bit adder for signal created at line 709. - Found 9-bit subtractor for signal created at line 758. - Found 4-bit comparator equal for signal created at line 711. - Found 9-bit comparator equal for signal created at line 758. - Found 8-bit comparator greatequal for signal created at line 729. - Found 8-bit comparator greatequal for signal created at line 764. - Found 8-bit comparator less for signal created at line 751. - Found 8-bit adder for signal created at line 502. - Found 8-bit adder for signal created at line 535. - Found 8-bit comparator greatequal for signal created at line 503. - Found 8-bit comparator lessequal for signal created at line 537. - Found 8-bit adder for signal created at line 637. - Found 4-bit adder for signal created at line 655. - Found 8-bit comparator greater for signal created at line 638. - Found 4-bit comparator less for signal created at line 656. - Found 8-bit register for signal . - Found 8-bit register for signal created at line 588. - Found 1-bit register for signal created at line 588. - Found 4-bit register for signal . - Found 31-bit adder for signal created at line 239. - Found 31-bit adder for signal created at line 218. - Found 4-bit adder for signal created at line 220. - Found 1-bit register for signal >. - Found 16-bit register for signal . - Found 16-bit adder for signal created at line 240. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit adder for signal created at line 325. - Found 8-bit tristate buffer for signal . - Found 8-bit tristate buffer for signal . - Summary: - inferred 4 Finite State Machine(s). - inferred 116 D-type flip-flop(s). - inferred 15 Adder/Subtractor(s). - inferred 10 Comparator(s). - inferred 8 Multiplexer(s). - inferred 24 Tristate(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/DMA_ARBITER.vhd". -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 6 | - | Transitions | 25 | - | Inputs | 7 | - | Outputs | 9 | - | Clock | clk (rising_edge) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | idle | - | Power Up State | idle | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- -WARNING:Xst:736 - Found 1-bit latch for signal created at line 294. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 310. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 294. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 310. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 294. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 310. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 294. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 310. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 295. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 319. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 295. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 319. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 295. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 319. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 295. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:736 - Found 1-bit latch for signal created at line 319. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 4-bit register for signal . - Found 1-bit 4-to-1 multiplexer for signal created at line 218. - Found 1-bit 4-to-1 multiplexer for signal created at line 209. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit 4-to-1 multiplexer for signal created at line 218. - Found 1-bit 4-to-1 multiplexer for signal created at line 209. - Found 2-bit register for signal . - Found 2-bit adder for signal created at line 186. - Found 2-bit register for signal . - Found 2-bit adder for signal created at line 141. - Found 4-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 1 Finite State Machine(s). - inferred 24 D-type flip-flop(s). - inferred 2 Adder/Subtractor(s). - inferred 4 Multiplexer(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/RAM_64.vhd". - Found 64x8-bit dual-port RAM for signal . - Found 8-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/round_robbin_machine.vhd". - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/MUX1.vhd". -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/DEMUX1.vhd". -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/MUX8.vhd". -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/SWITCH_GENERIC_16_16/Crossbar.vhd". -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:1305 - Output is never assigned. Tied to value 0. -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd". -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 3 | - | Transitions | 9 | - | Inputs | 4 | - | Outputs | 3 | - | Clock | clk (rising_edge) | - | Reset | srst (positive) | - | Reset type | synchronous | - | Reset State | state0 | - | Power Up State | state0 | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit register for signal . - Found 8-bit updown counter for signal . - Found 8-bit up counter for signal . - Found 8-bit up counter for signal . - Summary: - inferred 1 Finite State Machine(s). - inferred 3 Counter(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD". -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 2 | - | Transitions | 2 | - | Inputs | 0 | - | Outputs | 3 | - | Clock | clk (rising_edge) | - | Clock enable | priority_rotation_en (positive) | - | Reset | reset (positive) | - | Reset type | synchronous | - | Reset State | 110 | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 4-bit register for signal . - Summary: - inferred 1 Finite State Machine(s). - inferred 4 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/FIFO_64_FWFT.vhd". -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 3 | - | Transitions | 9 | - | Inputs | 4 | - | Outputs | 3 | - | Clock | clk (rising_edge) | - | Reset | srst (positive) | - | Reset type | synchronous | - | Reset State | state0 | - | Power Up State | state0 | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found 8-bit register for signal . - Found 6-bit updown counter for signal . - Found 6-bit up counter for signal . - Found 6-bit up counter for signal . - Summary: - inferred 1 Finite State Machine(s). - inferred 3 Counter(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/MPI_CORE_SCHEDULER.vhd". -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/CORE_MPI.vhd". -WARNING:Xst:1305 - Output > is never assigned. Tied to value 00. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 00011010. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value 0. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value 0. -WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value 0. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 0. -WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 16-bit tristate buffer for signal . - Found 16-bit tristate buffer for signal . - Found 1-bit register for signal >. - Found 1-bit register for signal . - Summary: - inferred 2 D-type flip-flop(s). - inferred 32 Tristate(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd". -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 00010000. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 12 | - | Inputs | 5 | - | Outputs | 6 | - | Clock | clk (rising_edge) | - | Clock enable | cmd_exec (negative) | - | Reset | reset_signal (positive) | - | Reset type | synchronous | - | Reset State | state0 | - | Power Up State | state0 | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 8 | - | Transitions | 19 | - | Inputs | 5 | - | Outputs | 8 | - | Clock | clk (rising_edge) | - | Reset | reset_signal (positive) | - | Reset type | synchronous | - | Reset State | cmdstart | - | Power Up State | cmdstart | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 8-bit register for signal . - Found 8-bit subtractor for signal created at line 495. - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 2-bit comparator greater for signal created at line 136. - Found 4-bit register for signal . - Summary: - inferred 2 Finite State Machine(s). - inferred 22 D-type flip-flop(s). - inferred 1 Adder/Subtractor(s). - inferred 1 Comparator(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd". -WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 00010001. - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 5 | - | Transitions | 12 | - | Inputs | 5 | - | Outputs | 6 | - | Clock | clk (rising_edge) | - | Clock enable | cmd_exec (negative) | - | Reset | reset_signal (positive) | - | Reset type | synchronous | - | Reset State | state0 | - | Power Up State | state0 | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- - Found finite state machine for signal . - ----------------------------------------------------------------------- - | States | 8 | - | Transitions | 19 | - | Inputs | 5 | - | Outputs | 8 | - | Clock | clk (rising_edge) | - | Reset | reset_signal (positive) | - | Reset type | synchronous | - | Reset State | cmdstart | - | Power Up State | cmdstart | - | Encoding | automatic | - | Implementation | LUT | - ----------------------------------------------------------------------- -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 1-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. -WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. -INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. - Found 8-bit register for signal . - Found 8-bit subtractor for signal created at line 495. - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 2-bit comparator greater for signal created at line 136. - Found 4-bit register for signal . - Summary: - inferred 2 Finite State Machine(s). - inferred 22 D-type flip-flop(s). - inferred 1 Adder/Subtractor(s). - inferred 1 Comparator(s). -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd". -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/SWITCH_GENERIC_16_16/Scheduler.vhd". -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/SWITCH_GENERIC_16_16/SWITCH_GEN.vhd". -Unit synthesized. - - -Synthesizing Unit . - Related source file is "C:/Core MPI/CORE_MPI/MPI_NOC.vhd". -WARNING:Xst:647 - Input .clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -WARNING:Xst:647 - Input .reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -Unit synthesized. - -INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. - -========================================================================= -HDL Synthesis Report - -Macro Statistics -# RAMs : 8 - 256x8-bit dual-port RAM : 4 - 64x8-bit dual-port RAM : 4 -# Adders/Subtractors : 56 - 16-bit adder : 10 - 2-bit adder : 4 - 2-bit adder carry out : 2 - 31-bit adder : 4 - 4-bit adder : 12 - 8-bit adder : 14 - 8-bit addsub : 2 - 8-bit subtractor : 6 - 9-bit subtractor : 2 -# Counters : 26 - 6-bit up counter : 8 - 6-bit updown counter : 4 - 8-bit up counter : 10 - 8-bit updown counter : 4 -# Registers : 239 - 1-bit register : 142 - 16-bit register : 4 - 19-bit register : 2 - 2-bit register : 4 - 32-bit register : 4 - 4-bit register : 29 - 8-bit register : 54 -# Latches : 214 - 1-bit latch : 150 - 16-bit latch : 14 - 19-bit latch : 2 - 2-bit latch : 2 - 31-bit latch : 4 - 32-bit latch : 2 - 4-bit latch : 10 - 8-bit latch : 30 -# Comparators : 30 - 2-bit comparator greater : 2 - 4-bit comparator equal : 4 - 4-bit comparator less : 4 - 5-bit comparator less : 2 - 8-bit comparator greatequal : 6 - 8-bit comparator greater : 2 - 8-bit comparator less : 2 - 8-bit comparator lessequal : 2 - 9-bit comparator equal : 2 - 9-bit comparator greater : 4 -# Multiplexers : 10 - 1-bit 4-to-1 multiplexer : 8 - 8-bit 4-to-1 multiplexer : 2 -# Tristates : 18 - 16-bit tristate buffer : 6 - 8-bit tristate buffer : 12 - -========================================================================= - -========================================================================= -* Advanced HDL Synthesis * -========================================================================= - -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------------- - State | Encoding -------------------------- - cmdstart | 000 - cmdwait | 001 - cmdread | 010 - cmdsetdest | 011 - cmdsetcount | 100 - cmdsetid | 101 - cmdpulse | 110 - cmdend | 111 -------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------- - State | Encoding ---------------------- - state0 | 000 - state1 | 001 - state2 | 010 - stpulse | 011 - state3 | 100 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------------- - State | Encoding -------------------------- - cmdstart | 000 - cmdwait | 001 - cmdread | 010 - cmdsetdest | 011 - cmdsetcount | 100 - cmdsetid | 101 - cmdpulse | 110 - cmdend | 111 -------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. ---------------------- - State | Encoding ---------------------- - state0 | 000 - state1 | 001 - state2 | 010 - stpulse | 011 - state3 | 100 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. --------------------- - State | Encoding --------------------- - state0 | 00 - state1 | 01 - state2 | 10 --------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -------------------- - State | Encoding -------------------- - 110 | 110 - 011 | 011 -------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. -Optimizing FSM on signal with user encoding. --------------------- - State | Encoding --------------------- - state0 | 00 - state1 | 01 - state2 | 10 --------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. -------------------------- - State | Encoding -------------------------- - idle | 000 - wait_ack | 001 - arbiter_ack | 011 - writing | 111 - readwrite | 010 - reading | 110 -------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------- - State | Encoding -------------------------------- - init | 00000000000001 - getportnum | 00000000000100 - decodedata | 00000000001000 - isportzero | 00000000010000 - seekmain | 00000000100000 - storemain | 00000010000000 - setmainflag | 00000001000000 - getmainreq | 00000000000010 - storerank | 00000100000000 - newrank | 00010000000000 - sendrank | 00100000000000 - regrank | 01000000000000 - sendapp | 00001000000000 - endinit | 10000000000000 -------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -Optimizing FSM on signal with one-hot encoding. --------------------- - State | Encoding --------------------- - s_init | 000001 - s_head | 000010 - s_len | 000100 - s_len2 | 001000 - s_data | 010000 - s_end | 100000 --------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -Optimizing FSM on signal with one-hot encoding. --------------------------- - State | Encoding --------------------------- - cmdstart | 000000001 - cmdpost | 000000010 - cmdpostidle | 000000100 - cmdread | 000001000 - cmdlen | 000010000 - cmdglen | 001000000 - cmddata | 010000000 - cmdend | 100000000 - cmdtimeout | 000100000 --------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. ---------------------- - State | Encoding ---------------------- - r_wait | 000 - r_dlen | 001 - r_drop | 011 - r_glen | 110 - r_start | 111 - r_end | 010 ---------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------------------- - State | Encoding -------------------------------------------- - fetch_packet_type | 000000000000000001 - decode_packet_type | 000000000000000010 - decode_packet_type2 | 000000000000000100 - fetch_addresses | 000000000000100000 - execute_spawn | unreached - execute_put1 | 000000000010000000 - execute_put2 | 000000001000000000 - execute_put3 | 000000010000000000 - execute_get1 | 000000000001000000 - execute_get2 | 000000100000000000 - execute_barrier1 | 000000000000001000 - execute_barrier2 | 000001000000000000 - execute_barrier3 | 000100000000000000 - execute_barrier4 | 000010000000000000 - execute_barrier5 | 001000000000000000 - execute_barrier6 | 010000000000000000 - execute_barrier7 | 100000000000000000 - execute_init1 | 000000000000010000 - execute_init2 | 000000000100000000 -------------------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with one-hot encoding. -Optimizing FSM on signal with one-hot encoding. -------------------------------------------- - State | Encoding -------------------------------------------- - fifo_select | 000000000000000001 - fetch_packet_type | 000000000000000010 - decode_packet_type | 000000000000000100 - fetch_addresses | 000000000000001000 - decode_packet_type2 | 000000000001000000 - execute_barrier1 | 000000000000010000 - execute_barrier2 | 000100000000000000 - execute_barrier3 | 001000000000000000 - execute_barrier4 | 010000000000000000 - execute_get1 | 000000000100000000 - execute_get2 | 000010000000000000 - execute_put1 | 000000000010000000 - execute_put2 | 000000001000000000 - execute_put3 | 000000010000000000 - execute_put4 | 000000100000000000 - execute_put5 | 000001000000000000 - execute_init1 | 000000000000100000 - execute_init2 | 100000000000000000 -------------------------------------------- -Analyzing FSM for best encoding. -Optimizing FSM on signal with gray encoding. -Optimizing FSM on signal with gray encoding. ------------------------- - State | Encoding ------------------------- - init | 000 - setadr | 011 - readptr | 010 - getbus | 001 - readmem | 110 - freebus | 111 - st_timeout | 101 ------------------------- -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block base_adrset_i. - You should achieve better results by setting this init to 1. -WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block base_adrset_i. - You should achieve better results by setting this init to 1. -WARNING:Xst:1426 - The value init of the FF/Latch origport0_0 hinder the constant cleaning in the block MPI_CORE_EX4_FSM. - You should achieve better results by setting this init to 1. -WARNING:Xst:1426 - The value init of the FF/Latch origport0_0 hinder the constant cleaning in the block MPI_CORE_EX4_FSM. - You should achieve better results by setting this init to 1. -WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block Initialized. - You should achieve better results by setting this init to 1. -WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block Initialized. - You should achieve better results by setting this init to 1. -WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block 0. - You should achieve better results by setting this init to 1. -WARNING:Xst:1426 - The value init of the FF/Latch 0 hinder the constant cleaning in the block 0. - You should achieve better results by setting this init to 1. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <7>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <6>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <5>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <4>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <3>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <2>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <0>. This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. - -Synthesizing (advanced) Unit . -INFO:Xst:3040 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): - ----------------------------------------------------------------------- - | ram_type | Block | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 8-bit | | - | mode | read-first | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 256-word x 8-bit | | - | mode | write-first | | - | clkB | connected to signal | rise | - | addrB | connected to signal | | - | doB | connected to signal | | - ----------------------------------------------------------------------- - | optimization | speed | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -Synthesizing (advanced) Unit . -INFO:Xst:3048 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 64-word x 8-bit | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 64-word x 8-bit | | - | addrB | connected to signal | | - | doB | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . - -========================================================================= -Advanced HDL Synthesis Report - -Macro Statistics -# FSMs : 15 -# RAMs : 8 - 256x8-bit dual-port block RAM : 4 - 64x8-bit dual-port distributed RAM : 4 -# Adders/Subtractors : 56 - 16-bit adder : 10 - 2-bit adder : 4 - 2-bit adder carry out : 2 - 31-bit adder : 4 - 4-bit adder : 12 - 8-bit adder : 14 - 8-bit addsub : 2 - 8-bit subtractor : 6 - 9-bit subtractor : 2 -# Counters : 26 - 6-bit up counter : 8 - 6-bit updown counter : 4 - 8-bit up counter : 10 - 8-bit updown counter : 4 -# Registers : 886 - Flip-Flops : 886 -# Latches : 214 - 1-bit latch : 150 - 16-bit latch : 14 - 19-bit latch : 2 - 2-bit latch : 2 - 31-bit latch : 4 - 32-bit latch : 2 - 4-bit latch : 10 - 8-bit latch : 30 -# Comparators : 30 - 2-bit comparator greater : 2 - 4-bit comparator equal : 4 - 4-bit comparator less : 4 - 5-bit comparator less : 2 - 8-bit comparator greatequal : 6 - 8-bit comparator greater : 2 - 8-bit comparator less : 2 - 8-bit comparator lessequal : 2 - 9-bit comparator equal : 2 - 9-bit comparator greater : 4 -# Multiplexers : 10 - 1-bit 4-to-1 multiplexer : 8 - 8-bit 4-to-1 multiplexer : 2 - -========================================================================= - -========================================================================= -* Low Level Synthesis * -========================================================================= -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1426 - The value init of the FF/Latch origport0_0 hinder the constant cleaning in the block EX4_FSM. - You should achieve better results by setting this init to 1. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1426 - The value init of the FF/Latch base_adrset_i hinder the constant cleaning in the block load_instr. - You should achieve better results by setting this init to 1. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1426 - The value init of the FF/Latch ram_data_out_0 hinder the constant cleaning in the block EX1_FSM. - You should achieve better results by setting this init to 1. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<1> Mtridata_Ram_data<1> signal will be lost. -WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<2> Mtridata_Ram_data<2> signal will be lost. -WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<3> Mtridata_Ram_data<3> signal will be lost. -WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<4> Mtridata_Ram_data<4> signal will be lost. -WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<5> Mtridata_Ram_data<5> signal will be lost. -WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<6> Mtridata_Ram_data<6> signal will be lost. -WARNING:Xst:638 - in unit EX2_FSM Conflict on KEEP property on signal Mtridata_Ram_data<0> and Mtridata_Ram_data<7> Mtridata_Ram_data<7> signal will be lost. -WARNING:Xst:1294 - Latch is equivalent to a wire in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1426 - The value init of the FF/Latch Initialized hinder the constant cleaning in the block EX4_FSM. - You should achieve better results by setting this init to 1. -WARNING:Xst:1426 - The value init of the FF/Latch ResultOut_0 hinder the constant cleaning in the block EX4_FSM. - You should achieve better results by setting this init to 1. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:638 - in unit EX4_FSM Conflict on KEEP property on signal Mtridata_tosend<6> and Mtridata_tosend<7> Mtridata_tosend<7> signal will be lost. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<1>, V_1_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<2>, V_2_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_3_mux0000, Tick_Count<3>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_4_mux0000, Tick_Count<4>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_5_mux0000, Tick_Count<5>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<6>, V_6_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<7>, V_7_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<8>, V_8_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_9_mux0000, Tick_Count<9>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_10_mux0000, Tick_Count<10>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<11>, V_11_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_12_mux0000, Tick_Count<12>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<13>, V_13_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<14>, V_14_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_15_mux0000, Tick_Count<15>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<16>, V_16_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_17_mux0000, Tick_Count<17>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<18>, V_18_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<19>, V_19_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<20>, V_20_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_21_mux0000, Tick_Count<21>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<22>, V_22_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<23>, V_23_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<24>, V_24_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<25>, V_25_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<26>, V_26_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_27_mux0000, Tick_Count<27>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_28_mux0000, Tick_Count<28>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V_29_mux0000, Tick_Count<29>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<30>, V_30_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<31>, V_31_mux0000. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: V0_1_mux0000, zero_mux0000, ClkR_Count<1>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: Tick_Count<0>. -WARNING:Xst:2170 - Unit EX0_FSM : the following signal(s) form a combinatorial loop: ClkR_Count<0>. -WARNING:Xst:2042 - Unit CORE_MPI: 32 internal tristates are replaced by logic (pull-up yes): dma_rd_address<0>, dma_rd_address<10>, dma_rd_address<11>, dma_rd_address<12>, dma_rd_address<13>, dma_rd_address<14>, dma_rd_address<15>, dma_rd_address<1>, dma_rd_address<2>, dma_rd_address<3>, dma_rd_address<4>, dma_rd_address<5>, dma_rd_address<6>, dma_rd_address<7>, dma_rd_address<8>, dma_rd_address<9>, dma_wr_address<0>, dma_wr_address<10>, dma_wr_address<11>, dma_wr_address<12>, dma_wr_address<13>, dma_wr_address<14>, dma_wr_address<15>, dma_wr_address<1>, dma_wr_address<2>, dma_wr_address<3>, dma_wr_address<4>, dma_wr_address<5>, dma_wr_address<6>, dma_wr_address<7>, dma_wr_address<8>, dma_wr_address<9>. -WARNING:Xst:2042 - Unit load_instr: 24 internal tristates are replaced by logic (pull-up yes): Ram_address_i<0>, Ram_address_i<10>, Ram_address_i<11>, Ram_address_i<12>, Ram_address_i<13>, Ram_address_i<14>, Ram_address_i<15>, Ram_address_i<1>, Ram_address_i<2>, Ram_address_i<3>, Ram_address_i<4>, Ram_address_i<5>, Ram_address_i<6>, Ram_address_i<7>, Ram_address_i<8>, Ram_address_i<9>, fifo_din_i<0>, fifo_din_i<1>, fifo_din_i<2>, fifo_din_i<3>, fifo_din_i<4>, fifo_din_i<5>, fifo_din_i<6>, fifo_din_i<7>. -WARNING:Xst:2042 - Unit EX1_FSM: 8 internal tristates are replaced by logic (pull-up yes): switch_port_in_data<0>, switch_port_in_data<1>, switch_port_in_data<2>, switch_port_in_data<3>, switch_port_in_data<4>, switch_port_in_data<5>, switch_port_in_data<6>, switch_port_in_data<7>. -WARNING:Xst:2042 - Unit EX2_FSM: 8 internal tristates are replaced by logic (pull-up yes): Ram_data<0>, Ram_data<1>, Ram_data<2>, Ram_data<3>, Ram_data<4>, Ram_data<5>, Ram_data<6>, Ram_data<7>. -WARNING:Xst:2042 - Unit EX4_FSM: 24 internal tristates are replaced by logic (pull-up yes): port_in_data<0>, port_in_data<1>, port_in_data<2>, port_in_data<3>, port_in_data<4>, port_in_data<5>, port_in_data<6>, port_in_data<7>, tosend4<0>, tosend4<1>, tosend4<2>, tosend4<3>, tosend4<4>, tosend4<5>, tosend4<6>, tosend4<7>, tosend<0>, tosend<1>, tosend<2>, tosend<3>, tosend<4>, tosend<5>, tosend<6>, tosend<7>. - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:1290 - Hierarchical block is unconnected in block . - It will be removed from the design. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed -INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed - -Mapping all equations... -Building and optimizing final netlist ... -Found area constraint ratio of 100 (+ 5) on block MPI_NOC, actual ratio is 21. -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -WARNING:Xst:2677 - Node of sequential type is unconnected in block . -FlipFlop Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/pop_state_FSM_FFd2 has been replicated 1 time(s) -FlipFlop Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/pop_state_FSM_FFd3 has been replicated 1 time(s) -FlipFlop Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/pop_state_FSM_FFd2 has been replicated 1 time(s) -FlipFlop Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/pop_state_FSM_FFd3 has been replicated 1 time(s) - -Final Macro Processing ... - -========================================================================= -Final Register Report - -Macro Statistics -# Registers : 883 - Flip-Flops : 883 - -========================================================================= - -========================================================================= -* Partition Report * -========================================================================= - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -========================================================================= -* Final Report * -========================================================================= -Final Results -RTL Top Level Output File Name : MPI_NOC.ngr -Top Level Output File Name : MPI_NOC -Output Format : NGC -Optimization Goal : Speed -Keep Hierarchy : Soft - -Design Statistics -# IOs : 150 - -Cell Usage : -# BELS : 3760 -# GND : 25 -# INV : 45 -# LUT1 : 170 -# LUT2 : 355 -# LUT2_D : 12 -# LUT2_L : 10 -# LUT3 : 632 -# LUT3_D : 13 -# LUT3_L : 16 -# LUT4 : 1592 -# LUT4_D : 79 -# LUT4_L : 78 -# MUXCY : 244 -# MUXF5 : 209 -# VCC : 16 -# XORCY : 264 -# FlipFlops/Latches : 1420 -# FD : 2 -# FDC : 24 -# FDCE : 2 -# FDE : 474 -# FDPE : 2 -# FDR : 78 -# FDRE : 228 -# FDRS : 58 -# FDRSE : 2 -# FDS : 8 -# FDSE : 5 -# LD : 296 -# LD_1 : 127 -# LDE : 114 -# RAMS : 84 -# RAM16X1D : 80 -# RAMB16_S9_S9 : 4 -# Clock Buffers : 5 -# BUFG : 4 -# BUFGP : 1 -# IO Buffers : 145 -# IBUF : 37 -# OBUF : 108 -========================================================================= - -Device utilization summary: ---------------------------- - -Selected Device : 3s1200eft256-5 - - Number of Slices: 1653 out of 8672 19% - Number of Slice Flip Flops: 1420 out of 17344 8% - Number of 4 input LUTs: 3162 out of 17344 18% - Number used as logic: 3002 - Number used as RAMs: 160 - Number of IOs: 150 - Number of bonded IOBs: 146 out of 190 76% - Number of BRAMs: 4 out of 28 14% - Number of GCLKs: 5 out of 24 20% - ---------------------------- -Partition Resource Summary: ---------------------------- - - No Partitions were found in this design. - ---------------------------- - - -========================================================================= -TIMING REPORT - -NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. - FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT - GENERATED AFTER PLACE-and-ROUTE. - -Clock Information: ------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+-------+ -Clock Signal | Clock buffer(FF name) | Load | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+-------+ -connect_core[2].hardmpi/LD_instr/instruction_ack | NONE(connect_core[2].hardmpi/Ex_EN_1) | 1 | -MPI_Node_in<1>_clk | BUFGP | 965 | -connect_core[2].hardmpi/dma_data_in_not0001(connect_core[2].hardmpi/dma_data_in_not00011:O) | NONE(*)(connect_core[2].hardmpi/dma_data_in_0) | 8 | -connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not00011:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_mux0001) | 1 | -connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not00011:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_mux0001) | 1 | -connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq00001:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_mux0001) | 1 | -connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq00001:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux0001) | 1 | -connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq00001:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_mux0001) | 1 | -connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq00001:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_mux0001) | 1 | -connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq00001:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_mux0001) | 1 | -connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq00001:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_mux0001) | 1 | -connect_core[2].hardmpi/LD_instr/fifo_wr_i_not0001(connect_core[2].hardmpi/LD_instr/fifo_wr_i_not00011:O) | NONE(*)(connect_core[2].hardmpi/LD_instr/fifo_wr_i) | 1 | -connect_core[2].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001(connect_core[2].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001:O) | NONE(*)(connect_core[2].hardmpi/LD_instr/Mtrien_Ram_address_i) | 1 | -connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0022(connect_core[2].hardmpi/LD_instr/etloadinst_FSM_Out31:O) | NONE(*)(connect_core[2].hardmpi/LD_instr/base_adrset_i) | 9 | -connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant<2>(connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux00041:O) | NONE(*)(connect_core[2].hardmpi/LD_instr/ptr_15) | 16 | -connect_core[2].hardmpi/LD_instr/count_i_not0001(connect_core[2].hardmpi/LD_instr/count_i_not000154:O) | NONE(*)(connect_core[2].hardmpi/LD_instr/count_i_0) | 18 | -connect_core[2].hardmpi/LD_instr/timeout_not0001(connect_core[2].hardmpi/LD_instr/timeout_not0001:O) | NONE(*)(connect_core[2].hardmpi/LD_instr/timeout_0) | 8 | -connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001(connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_not00011:O) | NONE(*)(connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_0) | 16 | -connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq00201(connect_core[2].hardmpi/LD_instr/etloadinst_FSM_FFd2-In31:O) | BUFG(*)(connect_core[2].hardmpi/LD_instr/ADRtmp_0) | 32 | -connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0019(connect_core[2].hardmpi/LD_instr/etloadinst_FSM_FFd3-In210:O) | NONE(*)(connect_core[2].hardmpi/LD_instr/Base_AD_8) | 8 | -connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000(connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_rd) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000(connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or00001:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_wr) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or0000(connect_core[2].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or000032:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX1_FSM/AppInitReq) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000(connect_core[2].hardmpi/MPI_CORE_EX1_FSM/Result_1_or00001:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX1_FSM/Result_1) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ex1_state_mach_FSM_FFd7 | NONE(connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_data_out_0) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or0000(connect_core[2].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or00001:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX2_FSM/switch_port_out_rd_en) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX2_FSM/ex2_state_mach_FSM_FFd18 | NONE(connect_core[2].hardmpi/MPI_CORE_EX2_FSM/Mtrien_Ram_data) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or0000(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or000010:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DS_Ack) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/WeRam_or000016:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/WeRam) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd12 | NONE(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/Result_En) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CTR) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 | BUFG | 50 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd5 | NONE(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/Initialized) | 5 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd10 | NONE(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/IsMain) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/etcmd_FSM_FFd9 | NONE(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/cport_out_rd_en) | 3 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or0000(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or000019:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DS_RDY | NONE(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_mux0001) | 9 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd9 | NONE(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/MainResp) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CM_RDY | NONE(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/EquFlag) | 1 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataRam_or0000(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataRam_or000019:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataRam_0) | 8 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/NextRank_or000019:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/nextr_0) | 8 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/Datalen_or0000(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/Datalen_or000019:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataToSend_2_0) | 5 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or0000(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or000016:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_0) | 6 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not0001(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not000164:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/timeout_i_0) | 8 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or0000(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or000019:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_0) | 4 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq00001:O) | NONE(*)(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_0) | 8 | -connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd11 | NONE(connect_core[2].hardmpi/MPI_CORE_EX4_FSM/NocMax_0) | 4 | -connect_core[1].hardmpi/LD_instr/instruction_ack | NONE(connect_core[1].hardmpi/Ex_EN_1) | 1 | -connect_core[1].hardmpi/dma_data_in_not0001(connect_core[1].hardmpi/dma_data_in_not00011:O) | NONE(*)(connect_core[1].hardmpi/dma_data_in_0) | 8 | -connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not00011:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_mux0001) | 1 | -connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not00011:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_mux0001) | 1 | -connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq00001:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_mux0001) | 1 | -connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq00001:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux0001) | 1 | -connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq00001:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_mux0001) | 1 | -connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq00001:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_mux0001) | 1 | -connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq00001:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_mux0001) | 1 | -connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq00001:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_mux0001) | 1 | -connect_core[1].hardmpi/LD_instr/fifo_wr_i_not0001(connect_core[1].hardmpi/LD_instr/fifo_wr_i_not00011:O) | NONE(*)(connect_core[1].hardmpi/LD_instr/fifo_wr_i) | 1 | -connect_core[1].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001(connect_core[1].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001:O) | NONE(*)(connect_core[1].hardmpi/LD_instr/Mtrien_Ram_address_i) | 1 | -connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0022(connect_core[1].hardmpi/LD_instr/etloadinst_FSM_Out31:O) | NONE(*)(connect_core[1].hardmpi/LD_instr/base_adrset_i) | 9 | -connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant<2>(connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux00041:O) | NONE(*)(connect_core[1].hardmpi/LD_instr/ptr_15) | 16 | -connect_core[1].hardmpi/LD_instr/count_i_not0001(connect_core[1].hardmpi/LD_instr/count_i_not000154:O) | NONE(*)(connect_core[1].hardmpi/LD_instr/count_i_0) | 18 | -connect_core[1].hardmpi/LD_instr/timeout_not0001(connect_core[1].hardmpi/LD_instr/timeout_not0001:O) | NONE(*)(connect_core[1].hardmpi/LD_instr/timeout_0) | 8 | -connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001(connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_not00011:O) | NONE(*)(connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_0) | 16 | -connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq00201(connect_core[1].hardmpi/LD_instr/etloadinst_FSM_FFd2-In31:O) | BUFG(*)(connect_core[1].hardmpi/LD_instr/ADRtmp_0) | 32 | -connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0019(connect_core[1].hardmpi/LD_instr/etloadinst_FSM_FFd3-In210:O) | NONE(*)(connect_core[1].hardmpi/LD_instr/Base_AD_8) | 8 | -connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000(connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_rd) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000(connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or00001:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_wr) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or0000(connect_core[1].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or000032:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX1_FSM/AppInitReq) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000(connect_core[1].hardmpi/MPI_CORE_EX1_FSM/Result_1_or00001:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX1_FSM/Result_1) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ex1_state_mach_FSM_FFd7 | NONE(connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_data_out_0) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or0000(connect_core[1].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or00001:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX2_FSM/switch_port_out_rd_en) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX2_FSM/ex2_state_mach_FSM_FFd18 | NONE(connect_core[1].hardmpi/MPI_CORE_EX2_FSM/Mtrien_Ram_data) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or0000(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or000010:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DS_Ack) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/WeRam_or000016:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/WeRam) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd12 | NONE(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/Result_En) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CTR) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 | BUFG | 50 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd5 | NONE(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/Initialized) | 5 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd10 | NONE(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/IsMain) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/etcmd_FSM_FFd9 | NONE(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/cport_out_rd_en) | 3 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or0000(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or000019:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DS_RDY | NONE(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_mux0001) | 9 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd9 | NONE(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/MainResp) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CM_RDY | NONE(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/EquFlag) | 1 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataRam_or0000(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataRam_or000019:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataRam_0) | 8 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/NextRank_or000019:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/nextr_0) | 8 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/Datalen_or0000(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/Datalen_or000019:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataToSend_2_0) | 5 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or0000(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or000016:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_0) | 6 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not0001(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not000164:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/timeout_i_0) | 8 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or0000(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or000019:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_0) | 4 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq00001:O) | NONE(*)(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_0) | 8 | -connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd11 | NONE(connect_core[1].hardmpi/MPI_CORE_EX4_FSM/NocMax_0) | 4 | -Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_exec_or0000(Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_exec_or00001:O) | NONE(*)(Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_exec) | 1 | -Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/dat_exec_or0000(Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/dat_exec_or00001:O) | NONE(*)(Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/dat_exec) | 1 | -Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/pop_state_cmp_eq0003(Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/pop_state_FSM_Out21:O) | NONE(*)(Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/dat_request_latch_en) | 2 | -Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmdstate_cmp_eq0001(Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_signal_or000011:O) | NONE(*)(Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_request_decoder_en)| 2 | -Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_out_pulse_or0000(Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_out_pulse_or00001:O) | NONE(*)(Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_out_pulse) | 1 | -Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_fifo_read_signal_or0000(Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_fifo_read_signal_or00001:O)| NONE(*)(Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_fifo_read_signal) | 1 | -Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_signal_or0000(Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_signal_or00001:O) | NONE(*)(Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_signal_0) | 2 | -Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_exec_or0000(Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_exec_or00001:O) | NONE(*)(Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_exec) | 1 | -Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/dat_exec_or0000(Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/dat_exec_or00001:O) | NONE(*)(Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/dat_exec) | 1 | -Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/pop_state_cmp_eq0003(Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/pop_state_FSM_FFd1-In11:O) | NONE(*)(Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/dat_request_latch_en) | 2 | -Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmdstate_cmp_eq0001(Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmdstate_FSM_Out01:O) | NONE(*)(Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_request_decoder_en)| 2 | -Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_out_pulse_or0000(Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_out_pulse_or00001:O) | NONE(*)(Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_out_pulse) | 1 | -Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_fifo_read_signal_or0000(Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_fifo_read_signal_or00001:O)| NONE(*)(Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_fifo_read_signal) | 1 | -Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_signal_or0000(Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_signal_or00001:O) | NONE(*)(Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_signal_0) | 3 | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+-------+ -(*) These 82 clock signal(s) are generated by combinatorial logic, -and XST is not able to identify which are the primary clock signals. -Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. -INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. - -Asynchronous Control Signals Information: ----------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------+-------+ -Control Signal | Buffer(FF name) | Load | -------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------+-------+ -MPI_Node_in<1>_reset | IBUF | 26 | -connect_core[1].hardmpi/CORE_SCHEDULER/mpi_core_rr_machine/fifo_selected_signal(connect_core[1].hardmpi/CORE_SCHEDULER/mpi_core_rr_machine/fifo_selected_signal:Q)| NONE(connect_core[1].hardmpi/Ex_EN_1)| 1 | -connect_core[2].hardmpi/CORE_SCHEDULER/mpi_core_rr_machine/fifo_selected_signal(connect_core[2].hardmpi/CORE_SCHEDULER/mpi_core_rr_machine/fifo_selected_signal:Q)| NONE(connect_core[2].hardmpi/Ex_EN_1)| 1 | -------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------+-------+ - -Timing Summary: ---------------- -Speed Grade: -5 - - Minimum period: 12.660ns (Maximum Frequency: 78.991MHz) - Minimum input arrival time before clock: 4.947ns - Maximum output required time after clock: 9.710ns - Maximum combinational path delay: No path found - -Timing Detail: --------------- -All values displayed in nanoseconds (ns) - -========================================================================= -Timing constraint: Default period analysis for Clock 'MPI_Node_in<1>_clk' - Clock period: 12.660ns (frequency: 78.991MHz) - Total number of paths / destination ports: 78077 / 1964 -------------------------------------------------------------------------- -Delay: 12.660ns (Levels of Logic = 26) - Source: Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FIFO/fifo_counter_6 (FF) - Destination: Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FIFO/fifo_counter_7 (FF) - Source Clock: MPI_Node_in<1>_clk rising - Destination Clock: MPI_Node_in<1>_clk rising - - Data Path: Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FIFO/fifo_counter_6 to Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FIFO/fifo_counter_7 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - FDRE:C->Q 5 0.514 0.690 fifo_counter_6 (fifo_counter_6) - LUT4:I0->O 1 0.612 0.426 full_signal_cmp_eq000013 (full_signal_cmp_eq000013) - LUT2:I1->O 7 0.612 0.671 full_signal_cmp_eq000014 (full) - end scope: 'OUTPUT_PORT_FIFO' - end scope: 'port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE' - begin scope: 'scheduler_switch2x2.Scheduler2_2' - begin scope: 'scheduler2x2.Inst_Scheduler2_2' - begin scope: 'Arbiter_1_2' - LUT3:I1->O 3 0.612 0.454 South1 (South) - end scope: 'Arbiter_1_2' - begin scope: 'Arbiter_2_2' - LUT4:I3->O 1 0.612 0.387 East1 (East) - end scope: 'Arbiter_2_2' - begin scope: 'Arbiter_3_1' - LUT4:I2->O 2 0.612 0.410 Grant (Grant) - end scope: 'Arbiter_3_1' - LUT3:I2->O 10 0.612 0.753 port_grant<1>1 (port_grant<1>) - end scope: 'scheduler2x2.Inst_Scheduler2_2' - end scope: 'scheduler_switch2x2.Scheduler2_2' - begin scope: 'crossbar_switch2x2.Switch_Crossbar2_2' - begin scope: 'crossbar2x2.Pulse_out_Crossbit2' - LUT4:I3->O 8 0.612 0.646 Data_out_1_or00001 (Data_out<1>) - end scope: 'crossbar2x2.Pulse_out_Crossbit2' - end scope: 'crossbar_switch2x2.Switch_Crossbar2_2' - begin scope: 'port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE' - begin scope: 'OUTPUT_PORT_FIFO' - LUT4:I3->O 3 0.612 0.520 fifo_counter_not0003_inv2 (fifo_counter_not0003_inv) - LUT2:I1->O 1 0.612 0.000 Mcount_fifo_counter_lut<0> (Mcount_fifo_counter_lut<0>) - MUXCY:S->O 1 0.404 0.000 Mcount_fifo_counter_cy<0> (Mcount_fifo_counter_cy<0>) - MUXCY:CI->O 1 0.051 0.000 Mcount_fifo_counter_cy<1> (Mcount_fifo_counter_cy<1>) - MUXCY:CI->O 1 0.051 0.000 Mcount_fifo_counter_cy<2> (Mcount_fifo_counter_cy<2>) - MUXCY:CI->O 1 0.051 0.000 Mcount_fifo_counter_cy<3> (Mcount_fifo_counter_cy<3>) - MUXCY:CI->O 1 0.051 0.000 Mcount_fifo_counter_cy<4> (Mcount_fifo_counter_cy<4>) - MUXCY:CI->O 1 0.051 0.000 Mcount_fifo_counter_cy<5> (Mcount_fifo_counter_cy<5>) - MUXCY:CI->O 0 0.051 0.000 Mcount_fifo_counter_cy<6> (Mcount_fifo_counter_cy<6>) - XORCY:CI->O 1 0.699 0.000 Mcount_fifo_counter_xor<7> (Result<7>) - FDRE:D 0.268 fifo_counter_7 - ---------------------------------------- - Total 12.660ns (7.702ns logic, 4.958ns route) - (60.8% logic, 39.2% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant<2>' - Clock period: 1.988ns (frequency: 502.930MHz) - Total number of paths / destination ports: 16 / 16 -------------------------------------------------------------------------- -Delay: 1.988ns (Levels of Logic = 1) - Source: connect_core[2].hardmpi/LD_instr/ptr_15 (LATCH) - Destination: connect_core[2].hardmpi/LD_instr/ptr_15 (LATCH) - Source Clock: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant<2> falling - Destination Clock: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant<2> falling - - Data Path: connect_core[2].hardmpi/LD_instr/ptr_15 to connect_core[2].hardmpi/LD_instr/ptr_15 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LDE:G->Q 3 0.588 0.520 ptr_15 (ptr_15) - LUT3:I1->O 1 0.612 0.000 ptr_15_mux00061 (ptr_15_mux0006) - LDE:D 0.268 ptr_15 - ---------------------------------------- - Total 1.988ns (1.468ns logic, 0.520ns route) - (73.8% logic, 26.2% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'connect_core[2].hardmpi/LD_instr/timeout_not0001' - Clock period: 4.635ns (frequency: 215.766MHz) - Total number of paths / destination ports: 36 / 8 -------------------------------------------------------------------------- -Delay: 4.635ns (Levels of Logic = 3) - Source: connect_core[2].hardmpi/LD_instr/timeout_2 (LATCH) - Destination: connect_core[2].hardmpi/LD_instr/timeout_6 (LATCH) - Source Clock: connect_core[2].hardmpi/LD_instr/timeout_not0001 falling - Destination Clock: connect_core[2].hardmpi/LD_instr/timeout_not0001 falling - - Data Path: connect_core[2].hardmpi/LD_instr/timeout_2 to connect_core[2].hardmpi/LD_instr/timeout_6 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 5 0.588 0.690 timeout_2 (timeout_2) - LUT4:I0->O 6 0.612 0.721 Madd_etloadinst_add0000_cy<3>11 (Madd_etloadinst_add0000_cy<3>) - LUT3:I0->O 2 0.612 0.532 Madd_etloadinst_add0000_cy<5>11 (Madd_etloadinst_add0000_cy<5>) - LUT3:I0->O 1 0.612 0.000 timeout_mux0006<6>1 (timeout_mux0006<6>) - LD:D 0.268 timeout_6 - ---------------------------------------- - Total 4.635ns (2.692ns logic, 1.943ns route) - (58.1% logic, 41.9% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001' - Clock period: 10.590ns (frequency: 94.426MHz) - Total number of paths / destination ports: 159 / 16 -------------------------------------------------------------------------- -Delay: 10.590ns (Levels of Logic = 10) - Source: connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_1 (LATCH) - Destination: connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_15 (LATCH) - Source Clock: connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 falling - Destination Clock: connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 falling - - Data Path: connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_1 to connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_15 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 7 0.588 0.671 Mtridata_Ram_address_i_1 (Mtridata_Ram_address_i<1>) - LUT2:I1->O 4 0.612 0.502 Ram_address_i<1>LogicTrst1 (Ram_address_i<1>) - LUT4_D:I3->LO 1 0.612 0.130 tb_11_and0000111 (N112) - LUT3:I2->O 3 0.612 0.454 tb_11_and000012 (V_6_and0000) - LUT4_D:I3->O 2 0.612 0.383 tb_11_and000021 (V_8_and0000) - LUT4:I3->O 4 0.612 0.502 tb_11_and000031 (V_10_and0000) - LUT4:I3->O 3 0.612 0.454 V_15_and000011 (V_13_and0000) - LUT4:I3->O 1 0.612 0.426 Mtridata_Ram_address_i_mux0000<0>39 (Mtridata_Ram_address_i_mux0000<0>39) - LUT4:I1->O 1 0.612 0.000 Mtridata_Ram_address_i_mux0000<0>67_F (N102) - MUXF5:I0->O 1 0.278 0.426 Mtridata_Ram_address_i_mux0000<0>67 (Mtridata_Ram_address_i_mux0000<0>67) - LUT2:I1->O 1 0.612 0.000 Mtridata_Ram_address_i_mux0000<0>79 (Mtridata_Ram_address_i_mux0000<0>) - LD:D 0.268 Mtridata_Ram_address_i_15 - ---------------------------------------- - Total 10.590ns (6.642ns logic, 3.948ns route) - (62.7% logic, 37.3% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq00201' - Clock period: 5.923ns (frequency: 168.836MHz) - Total number of paths / destination ports: 226 / 32 -------------------------------------------------------------------------- -Delay: 5.923ns (Levels of Logic = 19) - Source: connect_core[2].hardmpi/LD_instr/iptr_0 (LATCH) - Destination: connect_core[2].hardmpi/LD_instr/ADRtmp_15 (LATCH) - Source Clock: connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq00201 falling - Destination Clock: connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq00201 falling - - Data Path: connect_core[2].hardmpi/LD_instr/iptr_0 to connect_core[2].hardmpi/LD_instr/ADRtmp_15 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LDE:G->Q 2 0.588 0.532 iptr_0 (iptr_0) - LUT2:I0->O 1 0.612 0.000 Madd_ADRtmp_addsub0000_lut<0> (Madd_ADRtmp_addsub0000_lut<0>) - MUXCY:S->O 1 0.404 0.000 Madd_ADRtmp_addsub0000_cy<0> (Madd_ADRtmp_addsub0000_cy<0>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<1> (Madd_ADRtmp_addsub0000_cy<1>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<2> (Madd_ADRtmp_addsub0000_cy<2>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<3> (Madd_ADRtmp_addsub0000_cy<3>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<4> (Madd_ADRtmp_addsub0000_cy<4>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<5> (Madd_ADRtmp_addsub0000_cy<5>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<6> (Madd_ADRtmp_addsub0000_cy<6>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<7> (Madd_ADRtmp_addsub0000_cy<7>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<8> (Madd_ADRtmp_addsub0000_cy<8>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<9> (Madd_ADRtmp_addsub0000_cy<9>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<10> (Madd_ADRtmp_addsub0000_cy<10>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<11> (Madd_ADRtmp_addsub0000_cy<11>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<12> (Madd_ADRtmp_addsub0000_cy<12>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<13> (Madd_ADRtmp_addsub0000_cy<13>) - MUXCY:CI->O 0 0.052 0.000 Madd_ADRtmp_addsub0000_cy<14> (Madd_ADRtmp_addsub0000_cy<14>) - XORCY:CI->O 1 0.699 0.426 Madd_ADRtmp_addsub0000_xor<15> (ADRtmp_addsub0000<15>) - LUT3:I1->O 2 0.612 0.449 ADRtmp_mux0014<15> (ADRtmp_mux0014<15>) - LUT3:I1->O 1 0.612 0.000 ADRtmp_mux0016<15>1 (ADRtmp_mux0016<15>) - LDE:D 0.268 ADRtmp_15 - ---------------------------------------- - Total 5.923ns (4.516ns logic, 1.407ns route) - (76.2% logic, 23.8% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'connect_core[2].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000' - Clock period: 4.311ns (frequency: 231.941MHz) - Total number of paths / destination ports: 20 / 8 -------------------------------------------------------------------------- -Delay: 4.311ns (Levels of Logic = 5) - Source: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/nextr_1 (LATCH) - Destination: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/nextr_3 (LATCH) - Source Clock: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 rising - Destination Clock: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 rising - - Data Path: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/nextr_1 to connect_core[2].hardmpi/MPI_CORE_EX4_FSM/nextr_3 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 4 0.588 0.651 nextr_1 (nextr_1) - LUT1:I0->O 1 0.612 0.000 Madd_nextr_addsub0000_cy<1>_rt (Madd_nextr_addsub0000_cy<1>_rt) - MUXCY:S->O 1 0.404 0.000 Madd_nextr_addsub0000_cy<1> (Madd_nextr_addsub0000_cy<1>) - MUXCY:CI->O 0 0.052 0.000 Madd_nextr_addsub0000_cy<2> (Madd_nextr_addsub0000_cy<2>) - XORCY:CI->O 1 0.699 0.426 Madd_nextr_addsub0000_xor<3> (nextr_addsub0000<3>) - LUT2:I1->O 1 0.612 0.000 nextr_mux0000<3>1 (nextr_mux0000<3>) - LD_1:D 0.268 nextr_3 - ---------------------------------------- - Total 4.311ns (3.235ns logic, 1.077ns route) - (75.0% logic, 25.0% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000' - Clock period: 2.071ns (frequency: 482.777MHz) - Total number of paths / destination ports: 8 / 8 -------------------------------------------------------------------------- -Delay: 2.071ns (Levels of Logic = 1) - Source: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_0 (LATCH) - Destination: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_0 (LATCH) - Source Clock: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 falling - Destination Clock: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 falling - - Data Path: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_0 to connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_0 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 3 0.588 0.603 CmdReceived_2_0 (CmdReceived_2_0) - LUT4:I0->O 1 0.612 0.000 CmdReceived_2_mux0000<0>2 (CmdReceived_2_mux0000<0>) - LD:D 0.268 CmdReceived_2_0 - ---------------------------------------- - Total 2.071ns (1.468ns logic, 0.603ns route) - (70.9% logic, 29.1% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd21' - Clock period: 3.772ns (frequency: 265.080MHz) - Total number of paths / destination ports: 272 / 32 -------------------------------------------------------------------------- -Delay: 3.772ns (Levels of Logic = 16) - Source: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/nextadr_1 (LATCH) - Destination: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/nextadr_15 (LATCH) - Source Clock: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 falling - Destination Clock: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 falling - - Data Path: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/nextadr_1 to connect_core[2].hardmpi/MPI_CORE_EX4_FSM/nextadr_15 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 2 0.588 0.532 nextadr_1 (nextadr_1) - LUT1:I0->O 1 0.612 0.000 Madd_nextadr_add0000_cy<1>_rt (Madd_nextadr_add0000_cy<1>_rt) - MUXCY:S->O 1 0.404 0.000 Madd_nextadr_add0000_cy<1> (Madd_nextadr_add0000_cy<1>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<2> (Madd_nextadr_add0000_cy<2>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<3> (Madd_nextadr_add0000_cy<3>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<4> (Madd_nextadr_add0000_cy<4>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<5> (Madd_nextadr_add0000_cy<5>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<6> (Madd_nextadr_add0000_cy<6>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<7> (Madd_nextadr_add0000_cy<7>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<8> (Madd_nextadr_add0000_cy<8>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<9> (Madd_nextadr_add0000_cy<9>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<10> (Madd_nextadr_add0000_cy<10>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<11> (Madd_nextadr_add0000_cy<11>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<12> (Madd_nextadr_add0000_cy<12>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<13> (Madd_nextadr_add0000_cy<13>) - MUXCY:CI->O 0 0.051 0.000 Madd_nextadr_add0000_cy<14> (Madd_nextadr_add0000_cy<14>) - XORCY:CI->O 1 0.699 0.000 Madd_nextadr_add0000_xor<15> (nextadr_add0000<15>) - LD:D 0.268 nextadr_15 - ---------------------------------------- - Total 3.772ns (3.241ns logic, 0.532ns route) - (85.9% logic, 14.1% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant<2>' - Clock period: 1.988ns (frequency: 502.930MHz) - Total number of paths / destination ports: 16 / 16 -------------------------------------------------------------------------- -Delay: 1.988ns (Levels of Logic = 1) - Source: connect_core[1].hardmpi/LD_instr/ptr_15 (LATCH) - Destination: connect_core[1].hardmpi/LD_instr/ptr_15 (LATCH) - Source Clock: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant<2> falling - Destination Clock: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant<2> falling - - Data Path: connect_core[1].hardmpi/LD_instr/ptr_15 to connect_core[1].hardmpi/LD_instr/ptr_15 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LDE:G->Q 3 0.588 0.520 ptr_15 (ptr_15) - LUT3:I1->O 1 0.612 0.000 ptr_15_mux00061 (ptr_15_mux0006) - LDE:D 0.268 ptr_15 - ---------------------------------------- - Total 1.988ns (1.468ns logic, 0.520ns route) - (73.8% logic, 26.2% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'connect_core[1].hardmpi/LD_instr/timeout_not0001' - Clock period: 4.635ns (frequency: 215.766MHz) - Total number of paths / destination ports: 36 / 8 -------------------------------------------------------------------------- -Delay: 4.635ns (Levels of Logic = 3) - Source: connect_core[1].hardmpi/LD_instr/timeout_2 (LATCH) - Destination: connect_core[1].hardmpi/LD_instr/timeout_6 (LATCH) - Source Clock: connect_core[1].hardmpi/LD_instr/timeout_not0001 falling - Destination Clock: connect_core[1].hardmpi/LD_instr/timeout_not0001 falling - - Data Path: connect_core[1].hardmpi/LD_instr/timeout_2 to connect_core[1].hardmpi/LD_instr/timeout_6 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 5 0.588 0.690 timeout_2 (timeout_2) - LUT4:I0->O 6 0.612 0.721 Madd_etloadinst_add0000_cy<3>11 (Madd_etloadinst_add0000_cy<3>) - LUT3:I0->O 2 0.612 0.532 Madd_etloadinst_add0000_cy<5>11 (Madd_etloadinst_add0000_cy<5>) - LUT3:I0->O 1 0.612 0.000 timeout_mux0006<6>1 (timeout_mux0006<6>) - LD:D 0.268 timeout_6 - ---------------------------------------- - Total 4.635ns (2.692ns logic, 1.943ns route) - (58.1% logic, 41.9% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001' - Clock period: 10.590ns (frequency: 94.426MHz) - Total number of paths / destination ports: 159 / 16 -------------------------------------------------------------------------- -Delay: 10.590ns (Levels of Logic = 10) - Source: connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_1 (LATCH) - Destination: connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_15 (LATCH) - Source Clock: connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 falling - Destination Clock: connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 falling - - Data Path: connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_1 to connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_15 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 7 0.588 0.671 Mtridata_Ram_address_i_1 (Mtridata_Ram_address_i<1>) - LUT2:I1->O 4 0.612 0.502 Ram_address_i<1>LogicTrst1 (Ram_address_i<1>) - LUT4_D:I3->LO 1 0.612 0.130 tb_11_and0000111 (N112) - LUT3:I2->O 3 0.612 0.454 tb_11_and000012 (V_6_and0000) - LUT4_D:I3->O 2 0.612 0.383 tb_11_and000021 (V_8_and0000) - LUT4:I3->O 4 0.612 0.502 tb_11_and000031 (V_10_and0000) - LUT4:I3->O 3 0.612 0.454 V_15_and000011 (V_13_and0000) - LUT4:I3->O 1 0.612 0.426 Mtridata_Ram_address_i_mux0000<0>39 (Mtridata_Ram_address_i_mux0000<0>39) - LUT4:I1->O 1 0.612 0.000 Mtridata_Ram_address_i_mux0000<0>67_F (N102) - MUXF5:I0->O 1 0.278 0.426 Mtridata_Ram_address_i_mux0000<0>67 (Mtridata_Ram_address_i_mux0000<0>67) - LUT2:I1->O 1 0.612 0.000 Mtridata_Ram_address_i_mux0000<0>79 (Mtridata_Ram_address_i_mux0000<0>) - LD:D 0.268 Mtridata_Ram_address_i_15 - ---------------------------------------- - Total 10.590ns (6.642ns logic, 3.948ns route) - (62.7% logic, 37.3% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq00201' - Clock period: 5.923ns (frequency: 168.836MHz) - Total number of paths / destination ports: 226 / 32 -------------------------------------------------------------------------- -Delay: 5.923ns (Levels of Logic = 19) - Source: connect_core[1].hardmpi/LD_instr/iptr_0 (LATCH) - Destination: connect_core[1].hardmpi/LD_instr/ADRtmp_15 (LATCH) - Source Clock: connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq00201 falling - Destination Clock: connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq00201 falling - - Data Path: connect_core[1].hardmpi/LD_instr/iptr_0 to connect_core[1].hardmpi/LD_instr/ADRtmp_15 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LDE:G->Q 2 0.588 0.532 iptr_0 (iptr_0) - LUT2:I0->O 1 0.612 0.000 Madd_ADRtmp_addsub0000_lut<0> (Madd_ADRtmp_addsub0000_lut<0>) - MUXCY:S->O 1 0.404 0.000 Madd_ADRtmp_addsub0000_cy<0> (Madd_ADRtmp_addsub0000_cy<0>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<1> (Madd_ADRtmp_addsub0000_cy<1>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<2> (Madd_ADRtmp_addsub0000_cy<2>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<3> (Madd_ADRtmp_addsub0000_cy<3>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<4> (Madd_ADRtmp_addsub0000_cy<4>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<5> (Madd_ADRtmp_addsub0000_cy<5>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<6> (Madd_ADRtmp_addsub0000_cy<6>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<7> (Madd_ADRtmp_addsub0000_cy<7>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<8> (Madd_ADRtmp_addsub0000_cy<8>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<9> (Madd_ADRtmp_addsub0000_cy<9>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<10> (Madd_ADRtmp_addsub0000_cy<10>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<11> (Madd_ADRtmp_addsub0000_cy<11>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<12> (Madd_ADRtmp_addsub0000_cy<12>) - MUXCY:CI->O 1 0.052 0.000 Madd_ADRtmp_addsub0000_cy<13> (Madd_ADRtmp_addsub0000_cy<13>) - MUXCY:CI->O 0 0.052 0.000 Madd_ADRtmp_addsub0000_cy<14> (Madd_ADRtmp_addsub0000_cy<14>) - XORCY:CI->O 1 0.699 0.426 Madd_ADRtmp_addsub0000_xor<15> (ADRtmp_addsub0000<15>) - LUT3:I1->O 2 0.612 0.449 ADRtmp_mux0014<15> (ADRtmp_mux0014<15>) - LUT3:I1->O 1 0.612 0.000 ADRtmp_mux0016<15>1 (ADRtmp_mux0016<15>) - LDE:D 0.268 ADRtmp_15 - ---------------------------------------- - Total 5.923ns (4.516ns logic, 1.407ns route) - (76.2% logic, 23.8% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'connect_core[1].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000' - Clock period: 4.311ns (frequency: 231.941MHz) - Total number of paths / destination ports: 20 / 8 -------------------------------------------------------------------------- -Delay: 4.311ns (Levels of Logic = 5) - Source: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/nextr_1 (LATCH) - Destination: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/nextr_3 (LATCH) - Source Clock: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 rising - Destination Clock: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 rising - - Data Path: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/nextr_1 to connect_core[1].hardmpi/MPI_CORE_EX4_FSM/nextr_3 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 4 0.588 0.651 nextr_1 (nextr_1) - LUT1:I0->O 1 0.612 0.000 Madd_nextr_addsub0000_cy<1>_rt (Madd_nextr_addsub0000_cy<1>_rt) - MUXCY:S->O 1 0.404 0.000 Madd_nextr_addsub0000_cy<1> (Madd_nextr_addsub0000_cy<1>) - MUXCY:CI->O 0 0.052 0.000 Madd_nextr_addsub0000_cy<2> (Madd_nextr_addsub0000_cy<2>) - XORCY:CI->O 1 0.699 0.426 Madd_nextr_addsub0000_xor<3> (nextr_addsub0000<3>) - LUT2:I1->O 1 0.612 0.000 nextr_mux0000<3>1 (nextr_mux0000<3>) - LD_1:D 0.268 nextr_3 - ---------------------------------------- - Total 4.311ns (3.235ns logic, 1.077ns route) - (75.0% logic, 25.0% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000' - Clock period: 2.071ns (frequency: 482.777MHz) - Total number of paths / destination ports: 8 / 8 -------------------------------------------------------------------------- -Delay: 2.071ns (Levels of Logic = 1) - Source: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_0 (LATCH) - Destination: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_0 (LATCH) - Source Clock: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 falling - Destination Clock: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 falling - - Data Path: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_0 to connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_0 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 3 0.588 0.603 CmdReceived_2_0 (CmdReceived_2_0) - LUT4:I0->O 1 0.612 0.000 CmdReceived_2_mux0000<0>2 (CmdReceived_2_mux0000<0>) - LD:D 0.268 CmdReceived_2_0 - ---------------------------------------- - Total 2.071ns (1.468ns logic, 0.603ns route) - (70.9% logic, 29.1% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd21' - Clock period: 3.772ns (frequency: 265.080MHz) - Total number of paths / destination ports: 272 / 32 -------------------------------------------------------------------------- -Delay: 3.772ns (Levels of Logic = 16) - Source: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/nextadr_1 (LATCH) - Destination: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/nextadr_15 (LATCH) - Source Clock: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 falling - Destination Clock: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 falling - - Data Path: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/nextadr_1 to connect_core[1].hardmpi/MPI_CORE_EX4_FSM/nextadr_15 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 2 0.588 0.532 nextadr_1 (nextadr_1) - LUT1:I0->O 1 0.612 0.000 Madd_nextadr_add0000_cy<1>_rt (Madd_nextadr_add0000_cy<1>_rt) - MUXCY:S->O 1 0.404 0.000 Madd_nextadr_add0000_cy<1> (Madd_nextadr_add0000_cy<1>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<2> (Madd_nextadr_add0000_cy<2>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<3> (Madd_nextadr_add0000_cy<3>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<4> (Madd_nextadr_add0000_cy<4>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<5> (Madd_nextadr_add0000_cy<5>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<6> (Madd_nextadr_add0000_cy<6>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<7> (Madd_nextadr_add0000_cy<7>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<8> (Madd_nextadr_add0000_cy<8>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<9> (Madd_nextadr_add0000_cy<9>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<10> (Madd_nextadr_add0000_cy<10>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<11> (Madd_nextadr_add0000_cy<11>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<12> (Madd_nextadr_add0000_cy<12>) - MUXCY:CI->O 1 0.051 0.000 Madd_nextadr_add0000_cy<13> (Madd_nextadr_add0000_cy<13>) - MUXCY:CI->O 0 0.051 0.000 Madd_nextadr_add0000_cy<14> (Madd_nextadr_add0000_cy<14>) - XORCY:CI->O 1 0.699 0.000 Madd_nextadr_add0000_xor<15> (nextadr_add0000<15>) - LD:D 0.268 nextadr_15 - ---------------------------------------- - Total 3.772ns (3.241ns logic, 0.532ns route) - (85.9% logic, 14.1% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'MPI_Node_in<1>_clk' - Total number of paths / destination ports: 937 / 839 -------------------------------------------------------------------------- -Offset: 4.947ns (Levels of Logic = 9) - Source: MPI_Node_in<1>_ram_data_out<7> (PAD) - Destination: Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo_RAM_256/Mram_RAM (RAM) - Destination Clock: MPI_Node_in<1>_clk rising - - Data Path: MPI_Node_in<1>_ram_data_out<7> to Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo_RAM_256/Mram_RAM - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 4 1.106 0.529 MPI_Node_in_1__ram_data_out_7_IBUF (MPI_Node_in_1__ram_data_out_7_IBUF) - begin scope: 'connect_core[1].hardmpi' - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - begin scope: 'MPI_CORE_EX1_FSM' - LUT3:I2->O 1 0.612 0.360 switch_port_in_data<7>LogicTrst16 (switch_port_in_data<7>LogicTrst16) - LUT4:I3->O 1 0.612 0.509 switch_port_in_data<7>LogicTrst22 (switch_port_in_data<7>) - end scope: 'MPI_CORE_EX1_FSM' - LUT4:I0->O 2 0.612 0.380 switch_port_in_data<7>1 (switch_port_in_data<7>) - end scope: 'connect_core[1].hardmpi' - begin scope: 'Socsyst.switch_gen1' - begin scope: 'switch2x2.PORT1_INPUT_PORT_MODULE' - begin scope: 'INPUT_PORT_FIFO' - begin scope: 'fifo_RAM_256' - RAMB16_S9_S9:DIA7 0.227 Mram_RAM - ---------------------------------------- - Total 4.947ns (3.169ns logic, 1.778ns route) - (64.1% logic, 35.9% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant<2>' - Total number of paths / destination ports: 16 / 16 -------------------------------------------------------------------------- -Offset: 2.515ns (Levels of Logic = 4) - Source: MPI_Node_in<2>_ram_data_out<7> (PAD) - Destination: connect_core[2].hardmpi/LD_instr/ptr_15 (LATCH) - Destination Clock: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant<2> falling - - Data Path: MPI_Node_in<2>_ram_data_out<7> to connect_core[2].hardmpi/LD_instr/ptr_15 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 4 1.106 0.529 MPI_Node_in_2__ram_data_out_7_IBUF (MPI_Node_in_2__ram_data_out_7_IBUF) - begin scope: 'connect_core[2].hardmpi' - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - begin scope: 'LD_instr' - LUT3:I2->O 1 0.612 0.000 ptr_7_mux00041 (ptr_7_mux0004) - LDE:D 0.268 ptr_7 - ---------------------------------------- - Total 2.515ns (1.986ns logic, 0.529ns route) - (79.0% logic, 21.0% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0022' - Total number of paths / destination ports: 8 / 8 -------------------------------------------------------------------------- -Offset: 1.731ns (Levels of Logic = 2) - Source: MPI_Node_in<2>_instruction<0> (PAD) - Destination: connect_core[2].hardmpi/LD_instr/Base_Adr_8 (LATCH) - Destination Clock: connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0022 falling - - Data Path: MPI_Node_in<2>_instruction<0> to connect_core[2].hardmpi/LD_instr/Base_Adr_8 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 1 1.106 0.357 MPI_Node_in_2__instruction_0_IBUF (MPI_Node_in_2__instruction_0_IBUF) - begin scope: 'connect_core[2].hardmpi' - begin scope: 'LD_instr' - LDE:D 0.268 Base_Adr_8 - ---------------------------------------- - Total 1.731ns (1.374ns logic, 0.357ns route) - (79.4% logic, 20.6% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant<2>' - Total number of paths / destination ports: 16 / 16 -------------------------------------------------------------------------- -Offset: 2.515ns (Levels of Logic = 4) - Source: MPI_Node_in<1>_ram_data_out<7> (PAD) - Destination: connect_core[1].hardmpi/LD_instr/ptr_15 (LATCH) - Destination Clock: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant<2> falling - - Data Path: MPI_Node_in<1>_ram_data_out<7> to connect_core[1].hardmpi/LD_instr/ptr_15 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 4 1.106 0.529 MPI_Node_in_1__ram_data_out_7_IBUF (MPI_Node_in_1__ram_data_out_7_IBUF) - begin scope: 'connect_core[1].hardmpi' - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - begin scope: 'LD_instr' - LUT3:I2->O 1 0.612 0.000 ptr_7_mux00041 (ptr_7_mux0004) - LDE:D 0.268 ptr_7 - ---------------------------------------- - Total 2.515ns (1.986ns logic, 0.529ns route) - (79.0% logic, 21.0% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0022' - Total number of paths / destination ports: 8 / 8 -------------------------------------------------------------------------- -Offset: 1.731ns (Levels of Logic = 2) - Source: MPI_Node_in<1>_instruction<0> (PAD) - Destination: connect_core[1].hardmpi/LD_instr/Base_Adr_8 (LATCH) - Destination Clock: connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0022 falling - - Data Path: MPI_Node_in<1>_instruction<0> to connect_core[1].hardmpi/LD_instr/Base_Adr_8 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 1 1.106 0.357 MPI_Node_in_1__instruction_0_IBUF (MPI_Node_in_1__instruction_0_IBUF) - begin scope: 'connect_core[1].hardmpi' - begin scope: 'LD_instr' - LDE:D 0.268 Base_Adr_8 - ---------------------------------------- - Total 1.731ns (1.374ns logic, 0.357ns route) - (79.4% logic, 20.6% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000' - Total number of paths / destination ports: 18 / 17 -------------------------------------------------------------------------- -Offset: 9.111ns (Levels of Logic = 8) - Source: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux0001 (LATCH) - Destination: MPI_Node_Out<1>_ram_en (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 falling - - Data Path: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux0001 to MPI_Node_Out<1>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.387 dma_rd_grant_2_mux0001 (dma_rd_grant_2_mux0001) - LUT4:I2->O 116 0.612 1.098 dma_rd_grant_2_mux00041 (dma_rd_grant<2>) - end scope: 'MPI_CORE_DMA_ARBITER' - begin scope: 'LD_instr' - LUT4:I3->O 1 0.612 0.426 Ram_rd_en1 (Ram_rd_en) - end scope: 'LD_instr' - LUT4:I1->O 1 0.612 0.000 ram_en_or0000351 (ram_en_or0000351) - MUXF5:I1->O 1 0.278 0.360 ram_en_or000035_f5 (ram_en_or000035) - LUT4:I3->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__ram_en_OBUF (MPI_Node_Out<1>_ram_en) - ---------------------------------------- - Total 9.111ns (6.483ns logic, 2.628ns route) - (71.2% logic, 28.8% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000' - Total number of paths / destination ports: 1 / 1 -------------------------------------------------------------------------- -Offset: 6.336ns (Levels of Logic = 5) - Source: connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_rd (LATCH) - Destination: MPI_Node_Out<1>_ram_en (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000 rising - - Data Path: connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_rd to MPI_Node_Out<1>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.360 ram_rd (ram_rd) - end scope: 'MPI_CORE_EX1_FSM' - LUT4:I3->O 1 0.612 0.000 ram_en_or0000352 (ram_en_or0000352) - MUXF5:I0->O 1 0.278 0.360 ram_en_or000035_f5 (ram_en_or000035) - LUT4:I3->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__ram_en_OBUF (MPI_Node_Out<1>_ram_en) - ---------------------------------------- - Total 6.336ns (5.259ns logic, 1.077ns route) - (83.0% logic, 17.0% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001' - Total number of paths / destination ports: 34 / 17 -------------------------------------------------------------------------- -Offset: 8.079ns (Levels of Logic = 6) - Source: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_mux0001 (LATCH) - Destination: MPI_Node_Out<1>_ram_en (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 rising - - Data Path: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_mux0001 to MPI_Node_Out<1>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.387 dma_rd_grant_0_mux0001 (dma_rd_grant_0_mux0001) - LUT4:I2->O 36 0.612 1.104 dma_rd_grant_0_mux00041 (dma_rd_grant<0>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I2->O 1 0.612 0.000 ram_en_or0000352 (ram_en_or0000352) - MUXF5:I0->O 1 0.278 0.360 ram_en_or000035_f5 (ram_en_or000035) - LUT4:I3->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__ram_en_OBUF (MPI_Node_Out<1>_ram_en) - ---------------------------------------- - Total 8.079ns (5.871ns logic, 2.208ns route) - (72.7% logic, 27.3% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000' - Total number of paths / destination ports: 34 / 17 -------------------------------------------------------------------------- -Offset: 8.117ns (Levels of Logic = 6) - Source: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_mux0001 (LATCH) - Destination: MPI_Node_Out<1>_ram_en (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 falling - - Data Path: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_mux0001 to MPI_Node_Out<1>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.387 dma_rd_grant_3_mux0001 (dma_rd_grant_3_mux0001) - LUT4:I2->O 34 0.612 1.142 dma_rd_grant_3_mux00041 (dma_rd_grant<3>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I1->O 1 0.612 0.000 ram_en_or0000352 (ram_en_or0000352) - MUXF5:I0->O 1 0.278 0.360 ram_en_or000035_f5 (ram_en_or000035) - LUT4:I3->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__ram_en_OBUF (MPI_Node_Out<1>_ram_en) - ---------------------------------------- - Total 8.117ns (5.871ns logic, 2.246ns route) - (72.3% logic, 27.7% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000' - Total number of paths / destination ports: 34 / 17 -------------------------------------------------------------------------- -Offset: 8.200ns (Levels of Logic = 6) - Source: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_mux0001 (LATCH) - Destination: MPI_Node_Out<1>_ram_en (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 falling - - Data Path: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_mux0001 to MPI_Node_Out<1>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.387 dma_rd_grant_1_mux0001 (dma_rd_grant_1_mux0001) - LUT4:I2->O 34 0.612 1.225 dma_rd_grant_1_mux00041 (dma_rd_grant<1>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I0->O 1 0.612 0.000 ram_en_or0000351 (ram_en_or0000351) - MUXF5:I1->O 1 0.278 0.360 ram_en_or000035_f5 (ram_en_or000035) - LUT4:I3->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__ram_en_OBUF (MPI_Node_Out<1>_ram_en) - ---------------------------------------- - Total 8.200ns (5.871ns logic, 2.329ns route) - (71.6% logic, 28.4% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000' - Total number of paths / destination ports: 34 / 18 -------------------------------------------------------------------------- -Offset: 7.351ns (Levels of Logic = 6) - Source: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_mux0001 (LATCH) - Destination: MPI_Node_Out<1>_ram_address_wr<15> (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 falling - - Data Path: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_mux0001 to MPI_Node_Out<1>_ram_address_wr<15> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.509 dma_wr_grant_2_mux0001 (dma_wr_grant_2_mux0001) - LUT4:I0->O 38 0.612 1.226 dma_wr_grant_2_mux00041 (dma_wr_grant<2>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I0->O 1 0.612 0.000 dma_wr_address<9>LogicTrst_G (N107) - MUXF5:I1->O 1 0.278 0.357 dma_wr_address<9>LogicTrst (dma_wr_address<9>) - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__ram_address_wr_9_OBUF (MPI_Node_Out<1>_ram_address_wr<9>) - ---------------------------------------- - Total 7.351ns (5.259ns logic, 2.092ns route) - (71.5% logic, 28.5% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000' - Total number of paths / destination ports: 2 / 2 -------------------------------------------------------------------------- -Offset: 6.147ns (Levels of Logic = 4) - Source: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/WeRam (LATCH) - Destination: MPI_Node_Out<1>_ram_en (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000 rising - - Data Path: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/WeRam to MPI_Node_Out<1>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.360 WeRam (WeRam) - end scope: 'MPI_CORE_EX4_FSM' - LUT4:I3->O 2 0.612 0.449 ram_en_or00001_SW0 (N66) - LUT4:I1->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__ram_en_OBUF (MPI_Node_Out<1>_ram_en) - ---------------------------------------- - Total 6.147ns (4.981ns logic, 1.166ns route) - (81.0% logic, 19.0% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000' - Total number of paths / destination ports: 34 / 18 -------------------------------------------------------------------------- -Offset: 8.012ns (Levels of Logic = 5) - Source: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_mux0001 (LATCH) - Destination: MPI_Node_Out<1>_ram_en (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 falling - - Data Path: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_mux0001 to MPI_Node_Out<1>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.509 dma_wr_grant_3_mux0001 (dma_wr_grant_3_mux0001) - LUT4:I0->O 37 0.612 1.104 dma_wr_grant_3_mux00041 (dma_wr_grant<3>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I2->O 2 0.612 0.449 ram_en_or00001_SW0 (N66) - LUT4:I1->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__ram_en_OBUF (MPI_Node_Out<1>_ram_en) - ---------------------------------------- - Total 8.012ns (5.593ns logic, 2.419ns route) - (69.8% logic, 30.2% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000' - Total number of paths / destination ports: 2 / 2 -------------------------------------------------------------------------- -Offset: 6.213ns (Levels of Logic = 4) - Source: connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_wr (LATCH) - Destination: MPI_Node_Out<1>_ram_en (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000 rising - - Data Path: connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_wr to MPI_Node_Out<1>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.426 ram_wr (ram_wr) - end scope: 'MPI_CORE_EX1_FSM' - LUT4:I1->O 2 0.612 0.449 ram_en_or00001_SW0 (N66) - LUT4:I1->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__ram_en_OBUF (MPI_Node_Out<1>_ram_en) - ---------------------------------------- - Total 6.213ns (4.981ns logic, 1.232ns route) - (80.2% logic, 19.8% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001' - Total number of paths / destination ports: 18 / 18 -------------------------------------------------------------------------- -Offset: 8.082ns (Levels of Logic = 5) - Source: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_mux0001 (LATCH) - Destination: MPI_Node_Out<1>_ram_en (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 rising - - Data Path: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_mux0001 to MPI_Node_Out<1>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.509 dma_wr_grant_0_mux0001 (dma_wr_grant_0_mux0001) - LUT4:I0->O 23 0.612 1.174 dma_wr_grant_0_mux00042 (dma_wr_grant<0>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I0->O 2 0.612 0.449 ram_en_or00001_SW0 (N66) - LUT4:I1->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__ram_en_OBUF (MPI_Node_Out<1>_ram_en) - ---------------------------------------- - Total 8.082ns (5.593ns logic, 2.489ns route) - (69.2% logic, 30.8% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000' - Total number of paths / destination ports: 34 / 18 -------------------------------------------------------------------------- -Offset: 7.268ns (Levels of Logic = 6) - Source: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_mux0001 (LATCH) - Destination: MPI_Node_Out<1>_ram_address_wr<15> (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 falling - - Data Path: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_mux0001 to MPI_Node_Out<1>_ram_address_wr<15> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.509 dma_wr_grant_1_mux0001 (dma_wr_grant_1_mux0001) - LUT4:I0->O 38 0.612 1.143 dma_wr_grant_1_mux00041 (dma_wr_grant<1>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I1->O 1 0.612 0.000 dma_wr_address<9>LogicTrst_F (N106) - MUXF5:I0->O 1 0.278 0.357 dma_wr_address<9>LogicTrst (dma_wr_address<9>) - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__ram_address_wr_9_OBUF (MPI_Node_Out<1>_ram_address_wr<9>) - ---------------------------------------- - Total 7.268ns (5.259ns logic, 2.009ns route) - (72.4% logic, 27.6% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'MPI_Node_in<1>_clk' - Total number of paths / destination ports: 1566 / 74 -------------------------------------------------------------------------- -Offset: 9.710ns (Levels of Logic = 8) - Source: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dmac_state_FSM_FFd2 (FF) - Destination: MPI_Node_Out<1>_ram_en (PAD) - Source Clock: MPI_Node_in<1>_clk rising - - Data Path: connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dmac_state_FSM_FFd2 to MPI_Node_Out<1>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - FDRS:C->Q 18 0.514 1.060 dmac_state_FSM_FFd2 (dmac_state_FSM_FFd2) - LUT4:I0->O 116 0.612 1.098 dma_rd_grant_2_mux00041 (dma_rd_grant<2>) - end scope: 'MPI_CORE_DMA_ARBITER' - begin scope: 'LD_instr' - LUT4:I3->O 1 0.612 0.426 Ram_rd_en1 (Ram_rd_en) - end scope: 'LD_instr' - LUT4:I1->O 1 0.612 0.000 ram_en_or0000351 (ram_en_or0000351) - MUXF5:I1->O 1 0.278 0.360 ram_en_or000035_f5 (ram_en_or000035) - LUT4:I3->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__ram_en_OBUF (MPI_Node_Out<1>_ram_en) - ---------------------------------------- - Total 9.710ns (6.409ns logic, 3.301ns route) - (66.0% logic, 34.0% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000' - Total number of paths / destination ports: 34 / 18 -------------------------------------------------------------------------- -Offset: 7.351ns (Levels of Logic = 6) - Source: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_mux0001 (LATCH) - Destination: MPI_Node_Out<2>_ram_address_wr<15> (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 falling - - Data Path: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_mux0001 to MPI_Node_Out<2>_ram_address_wr<15> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.509 dma_wr_grant_2_mux0001 (dma_wr_grant_2_mux0001) - LUT4:I0->O 38 0.612 1.226 dma_wr_grant_2_mux00041 (dma_wr_grant<2>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I0->O 1 0.612 0.000 dma_wr_address<9>LogicTrst_G (N107) - MUXF5:I1->O 1 0.278 0.357 dma_wr_address<9>LogicTrst (dma_wr_address<9>) - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__ram_address_wr_9_OBUF (MPI_Node_Out<2>_ram_address_wr<9>) - ---------------------------------------- - Total 7.351ns (5.259ns logic, 2.092ns route) - (71.5% logic, 28.5% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000' - Total number of paths / destination ports: 2 / 2 -------------------------------------------------------------------------- -Offset: 6.147ns (Levels of Logic = 4) - Source: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/WeRam (LATCH) - Destination: MPI_Node_Out<2>_ram_en (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000 rising - - Data Path: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/WeRam to MPI_Node_Out<2>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.360 WeRam (WeRam) - end scope: 'MPI_CORE_EX4_FSM' - LUT4:I3->O 2 0.612 0.449 ram_en_or00001_SW0 (N66) - LUT4:I1->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__ram_en_OBUF (MPI_Node_Out<2>_ram_en) - ---------------------------------------- - Total 6.147ns (4.981ns logic, 1.166ns route) - (81.0% logic, 19.0% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000' - Total number of paths / destination ports: 34 / 18 -------------------------------------------------------------------------- -Offset: 8.012ns (Levels of Logic = 5) - Source: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_mux0001 (LATCH) - Destination: MPI_Node_Out<2>_ram_en (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 falling - - Data Path: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_mux0001 to MPI_Node_Out<2>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.509 dma_wr_grant_3_mux0001 (dma_wr_grant_3_mux0001) - LUT4:I0->O 37 0.612 1.104 dma_wr_grant_3_mux00041 (dma_wr_grant<3>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I2->O 2 0.612 0.449 ram_en_or00001_SW0 (N66) - LUT4:I1->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__ram_en_OBUF (MPI_Node_Out<2>_ram_en) - ---------------------------------------- - Total 8.012ns (5.593ns logic, 2.419ns route) - (69.8% logic, 30.2% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000' - Total number of paths / destination ports: 2 / 2 -------------------------------------------------------------------------- -Offset: 6.213ns (Levels of Logic = 4) - Source: connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_wr (LATCH) - Destination: MPI_Node_Out<2>_ram_en (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000 rising - - Data Path: connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_wr to MPI_Node_Out<2>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.426 ram_wr (ram_wr) - end scope: 'MPI_CORE_EX1_FSM' - LUT4:I1->O 2 0.612 0.449 ram_en_or00001_SW0 (N66) - LUT4:I1->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__ram_en_OBUF (MPI_Node_Out<2>_ram_en) - ---------------------------------------- - Total 6.213ns (4.981ns logic, 1.232ns route) - (80.2% logic, 19.8% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001' - Total number of paths / destination ports: 18 / 18 -------------------------------------------------------------------------- -Offset: 8.082ns (Levels of Logic = 5) - Source: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_mux0001 (LATCH) - Destination: MPI_Node_Out<2>_ram_en (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 rising - - Data Path: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_mux0001 to MPI_Node_Out<2>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.509 dma_wr_grant_0_mux0001 (dma_wr_grant_0_mux0001) - LUT4:I0->O 23 0.612 1.174 dma_wr_grant_0_mux00042 (dma_wr_grant<0>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I0->O 2 0.612 0.449 ram_en_or00001_SW0 (N66) - LUT4:I1->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__ram_en_OBUF (MPI_Node_Out<2>_ram_en) - ---------------------------------------- - Total 8.082ns (5.593ns logic, 2.489ns route) - (69.2% logic, 30.8% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000' - Total number of paths / destination ports: 34 / 18 -------------------------------------------------------------------------- -Offset: 7.268ns (Levels of Logic = 6) - Source: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_mux0001 (LATCH) - Destination: MPI_Node_Out<2>_ram_address_wr<15> (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 falling - - Data Path: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_mux0001 to MPI_Node_Out<2>_ram_address_wr<15> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.509 dma_wr_grant_1_mux0001 (dma_wr_grant_1_mux0001) - LUT4:I0->O 38 0.612 1.143 dma_wr_grant_1_mux00041 (dma_wr_grant<1>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I1->O 1 0.612 0.000 dma_wr_address<9>LogicTrst_F (N106) - MUXF5:I0->O 1 0.278 0.357 dma_wr_address<9>LogicTrst (dma_wr_address<9>) - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__ram_address_wr_9_OBUF (MPI_Node_Out<2>_ram_address_wr<9>) - ---------------------------------------- - Total 7.268ns (5.259ns logic, 2.009ns route) - (72.4% logic, 27.6% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000' - Total number of paths / destination ports: 18 / 17 -------------------------------------------------------------------------- -Offset: 9.111ns (Levels of Logic = 8) - Source: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux0001 (LATCH) - Destination: MPI_Node_Out<2>_ram_en (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 falling - - Data Path: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_mux0001 to MPI_Node_Out<2>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.387 dma_rd_grant_2_mux0001 (dma_rd_grant_2_mux0001) - LUT4:I2->O 116 0.612 1.098 dma_rd_grant_2_mux00041 (dma_rd_grant<2>) - end scope: 'MPI_CORE_DMA_ARBITER' - begin scope: 'LD_instr' - LUT4:I3->O 1 0.612 0.426 Ram_rd_en1 (Ram_rd_en) - end scope: 'LD_instr' - LUT4:I1->O 1 0.612 0.000 ram_en_or0000351 (ram_en_or0000351) - MUXF5:I1->O 1 0.278 0.360 ram_en_or000035_f5 (ram_en_or000035) - LUT4:I3->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__ram_en_OBUF (MPI_Node_Out<2>_ram_en) - ---------------------------------------- - Total 9.111ns (6.483ns logic, 2.628ns route) - (71.2% logic, 28.8% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000' - Total number of paths / destination ports: 1 / 1 -------------------------------------------------------------------------- -Offset: 6.336ns (Levels of Logic = 5) - Source: connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_rd (LATCH) - Destination: MPI_Node_Out<2>_ram_en (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000 rising - - Data Path: connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_rd to MPI_Node_Out<2>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.360 ram_rd (ram_rd) - end scope: 'MPI_CORE_EX1_FSM' - LUT4:I3->O 1 0.612 0.000 ram_en_or0000352 (ram_en_or0000352) - MUXF5:I0->O 1 0.278 0.360 ram_en_or000035_f5 (ram_en_or000035) - LUT4:I3->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__ram_en_OBUF (MPI_Node_Out<2>_ram_en) - ---------------------------------------- - Total 6.336ns (5.259ns logic, 1.077ns route) - (83.0% logic, 17.0% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001' - Total number of paths / destination ports: 34 / 17 -------------------------------------------------------------------------- -Offset: 8.079ns (Levels of Logic = 6) - Source: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_mux0001 (LATCH) - Destination: MPI_Node_Out<2>_ram_en (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 rising - - Data Path: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_mux0001 to MPI_Node_Out<2>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD_1:G->Q 1 0.588 0.387 dma_rd_grant_0_mux0001 (dma_rd_grant_0_mux0001) - LUT4:I2->O 36 0.612 1.104 dma_rd_grant_0_mux00041 (dma_rd_grant<0>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I2->O 1 0.612 0.000 ram_en_or0000352 (ram_en_or0000352) - MUXF5:I0->O 1 0.278 0.360 ram_en_or000035_f5 (ram_en_or000035) - LUT4:I3->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__ram_en_OBUF (MPI_Node_Out<2>_ram_en) - ---------------------------------------- - Total 8.079ns (5.871ns logic, 2.208ns route) - (72.7% logic, 27.3% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000' - Total number of paths / destination ports: 34 / 17 -------------------------------------------------------------------------- -Offset: 8.117ns (Levels of Logic = 6) - Source: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_mux0001 (LATCH) - Destination: MPI_Node_Out<2>_ram_en (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 falling - - Data Path: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_mux0001 to MPI_Node_Out<2>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.387 dma_rd_grant_3_mux0001 (dma_rd_grant_3_mux0001) - LUT4:I2->O 34 0.612 1.142 dma_rd_grant_3_mux00041 (dma_rd_grant<3>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I1->O 1 0.612 0.000 ram_en_or0000352 (ram_en_or0000352) - MUXF5:I0->O 1 0.278 0.360 ram_en_or000035_f5 (ram_en_or000035) - LUT4:I3->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__ram_en_OBUF (MPI_Node_Out<2>_ram_en) - ---------------------------------------- - Total 8.117ns (5.871ns logic, 2.246ns route) - (72.3% logic, 27.7% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000' - Total number of paths / destination ports: 34 / 17 -------------------------------------------------------------------------- -Offset: 8.200ns (Levels of Logic = 6) - Source: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_mux0001 (LATCH) - Destination: MPI_Node_Out<2>_ram_en (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 falling - - Data Path: connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_mux0001 to MPI_Node_Out<2>_ram_en - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.387 dma_rd_grant_1_mux0001 (dma_rd_grant_1_mux0001) - LUT4:I2->O 34 0.612 1.225 dma_rd_grant_1_mux00041 (dma_rd_grant<1>) - end scope: 'MPI_CORE_DMA_ARBITER' - LUT4:I0->O 1 0.612 0.000 ram_en_or0000351 (ram_en_or0000351) - MUXF5:I1->O 1 0.278 0.360 ram_en_or000035_f5 (ram_en_or000035) - LUT4:I3->O 1 0.612 0.357 ram_en_or000046 (ram_en) - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__ram_en_OBUF (MPI_Node_Out<2>_ram_en) - ---------------------------------------- - Total 8.200ns (5.871ns logic, 2.329ns route) - (71.6% logic, 28.4% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd21' - Total number of paths / destination ports: 16 / 16 -------------------------------------------------------------------------- -Offset: 5.364ns (Levels of Logic = 5) - Source: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/AdrRam_15 (LATCH) - Destination: MPI_Node_Out<1>_ram_address_wr<15> (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 falling - - Data Path: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/AdrRam_15 to MPI_Node_Out<1>_ram_address_wr<15> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.360 AdrRam_15 (AdrRam_15) - end scope: 'MPI_CORE_EX4_FSM' - LUT4:I3->O 1 0.612 0.000 dma_wr_address<15>LogicTrst_F (N124) - MUXF5:I0->O 1 0.278 0.357 dma_wr_address<15>LogicTrst (dma_wr_address<15>) - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__ram_address_wr_15_OBUF (MPI_Node_Out<1>_ram_address_wr<15>) - ---------------------------------------- - Total 5.364ns (4.647ns logic, 0.717ns route) - (86.6% logic, 13.4% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/dma_data_in_not0001' - Total number of paths / destination ports: 8 / 8 -------------------------------------------------------------------------- -Offset: 4.114ns (Levels of Logic = 3) - Source: connect_core[2].hardmpi/dma_data_in_7 (LATCH) - Destination: MPI_Node_Out<2>_ram_data_in<7> (PAD) - Source Clock: connect_core[2].hardmpi/dma_data_in_not0001 falling - - Data Path: connect_core[2].hardmpi/dma_data_in_7 to MPI_Node_Out<2>_ram_data_in<7> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.357 dma_data_in_7 (dma_data_in_7) - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__ram_data_in_7_OBUF (MPI_Node_Out<2>_ram_data_in<7>) - ---------------------------------------- - Total 4.114ns (3.757ns logic, 0.357ns route) - (91.3% logic, 8.7% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/dma_data_in_not0001' - Total number of paths / destination ports: 8 / 8 -------------------------------------------------------------------------- -Offset: 4.114ns (Levels of Logic = 3) - Source: connect_core[1].hardmpi/dma_data_in_7 (LATCH) - Destination: MPI_Node_Out<1>_ram_data_in<7> (PAD) - Source Clock: connect_core[1].hardmpi/dma_data_in_not0001 falling - - Data Path: connect_core[1].hardmpi/dma_data_in_7 to MPI_Node_Out<1>_ram_data_in<7> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.357 dma_data_in_7 (dma_data_in_7) - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__ram_data_in_7_OBUF (MPI_Node_Out<1>_ram_data_in<7>) - ---------------------------------------- - Total 4.114ns (3.757ns logic, 0.357ns route) - (91.3% logic, 8.7% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000' - Total number of paths / destination ports: 1 / 1 -------------------------------------------------------------------------- -Offset: 4.114ns (Levels of Logic = 2) - Source: connect_core[2].hardmpi/MPI_CORE_EX1_FSM/Result_1 (LATCH) - Destination: MPI_Node_Out<2>_PushOut<5> (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000 falling - - Data Path: connect_core[2].hardmpi/MPI_CORE_EX1_FSM/Result_1 to MPI_Node_Out<2>_PushOut<5> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.357 Result_1 (Result_1) - end scope: 'MPI_CORE_EX1_FSM' - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__PushOut_5_OBUF (MPI_Node_Out<2>_PushOut<5>) - ---------------------------------------- - Total 4.114ns (3.757ns logic, 0.357ns route) - (91.3% logic, 8.7% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd5' - Total number of paths / destination ports: 1 / 1 -------------------------------------------------------------------------- -Offset: 4.400ns (Levels of Logic = 2) - Source: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/Initialized (LATCH) - Destination: MPI_Node_Out<2>_PushOut<4> (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd5 falling - - Data Path: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/Initialized to MPI_Node_Out<2>_PushOut<4> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 8 0.588 0.643 Initialized (Initialized) - end scope: 'MPI_CORE_EX4_FSM' - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__PushOut_4_OBUF (MPI_Node_Out<2>_PushOut<4>) - ---------------------------------------- - Total 4.400ns (3.757ns logic, 0.643ns route) - (85.4% logic, 14.6% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd10' - Total number of paths / destination ports: 1 / 1 -------------------------------------------------------------------------- -Offset: 4.114ns (Levels of Logic = 2) - Source: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/IsMain (LATCH) - Destination: MPI_Node_Out<2>_PushOut<1> (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd10 falling - - Data Path: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/IsMain to MPI_Node_Out<2>_PushOut<1> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.357 IsMain (IsMain) - end scope: 'MPI_CORE_EX4_FSM' - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__PushOut_1_OBUF (MPI_Node_Out<2>_PushOut<1>) - ---------------------------------------- - Total 4.114ns (3.757ns logic, 0.357ns route) - (91.3% logic, 8.7% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd21' - Total number of paths / destination ports: 16 / 16 -------------------------------------------------------------------------- -Offset: 5.364ns (Levels of Logic = 5) - Source: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/AdrRam_15 (LATCH) - Destination: MPI_Node_Out<2>_ram_address_wr<15> (PAD) - Source Clock: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd21 falling - - Data Path: connect_core[2].hardmpi/MPI_CORE_EX4_FSM/AdrRam_15 to MPI_Node_Out<2>_ram_address_wr<15> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.360 AdrRam_15 (AdrRam_15) - end scope: 'MPI_CORE_EX4_FSM' - LUT4:I3->O 1 0.612 0.000 dma_wr_address<15>LogicTrst_F (N124) - MUXF5:I0->O 1 0.278 0.357 dma_wr_address<15>LogicTrst (dma_wr_address<15>) - begin scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'MPI_CORE_DMA_ARBITER' - end scope: 'connect_core[2].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_2__ram_address_wr_15_OBUF (MPI_Node_Out<2>_ram_address_wr<15>) - ---------------------------------------- - Total 5.364ns (4.647ns logic, 0.717ns route) - (86.6% logic, 13.4% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000' - Total number of paths / destination ports: 1 / 1 -------------------------------------------------------------------------- -Offset: 4.114ns (Levels of Logic = 2) - Source: connect_core[1].hardmpi/MPI_CORE_EX1_FSM/Result_1 (LATCH) - Destination: MPI_Node_Out<1>_PushOut<5> (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000 falling - - Data Path: connect_core[1].hardmpi/MPI_CORE_EX1_FSM/Result_1 to MPI_Node_Out<1>_PushOut<5> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.357 Result_1 (Result_1) - end scope: 'MPI_CORE_EX1_FSM' - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__PushOut_5_OBUF (MPI_Node_Out<1>_PushOut<5>) - ---------------------------------------- - Total 4.114ns (3.757ns logic, 0.357ns route) - (91.3% logic, 8.7% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd5' - Total number of paths / destination ports: 1 / 1 -------------------------------------------------------------------------- -Offset: 4.400ns (Levels of Logic = 2) - Source: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/Initialized (LATCH) - Destination: MPI_Node_Out<1>_PushOut<4> (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd5 falling - - Data Path: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/Initialized to MPI_Node_Out<1>_PushOut<4> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 8 0.588 0.643 Initialized (Initialized) - end scope: 'MPI_CORE_EX4_FSM' - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__PushOut_4_OBUF (MPI_Node_Out<1>_PushOut<4>) - ---------------------------------------- - Total 4.400ns (3.757ns logic, 0.643ns route) - (85.4% logic, 14.6% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd10' - Total number of paths / destination ports: 1 / 1 -------------------------------------------------------------------------- -Offset: 4.114ns (Levels of Logic = 2) - Source: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/IsMain (LATCH) - Destination: MPI_Node_Out<1>_PushOut<1> (PAD) - Source Clock: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd10 falling - - Data Path: connect_core[1].hardmpi/MPI_CORE_EX4_FSM/IsMain to MPI_Node_Out<1>_PushOut<1> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - LD:G->Q 1 0.588 0.357 IsMain (IsMain) - end scope: 'MPI_CORE_EX4_FSM' - end scope: 'connect_core[1].hardmpi' - OBUF:I->O 3.169 MPI_Node_Out_1__PushOut_1_OBUF (MPI_Node_Out<1>_PushOut<1>) - ---------------------------------------- - Total 4.114ns (3.757ns logic, 0.357ns route) - (91.3% logic, 8.7% route) - -========================================================================= - - -Total REAL time to Xst completion: 44.00 secs -Total CPU time to Xst completion: 43.34 secs - ---> - -Total memory usage is 444436 kilobytes - -Number of errors : 0 ( 0 filtered) -Number of warnings : 903 ( 0 filtered) -Number of infos : 161 ( 0 filtered) - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.twr =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.twr (revision 17) +++ (revision ) @@ -1,169 +1,0 @@ --------------------------------------------------------------------------------- -Release 12.3 Trace (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 5 --n 3 -fastpaths -xml MPI_NOC.twx MPI_NOC.ncd -o MPI_NOC.twr MPI_NOC.pcf - -Design file: MPI_NOC.ncd -Physical constraint file: MPI_NOC.pcf -Device,package,speed: xc3s1200e,ft256,-5 (PRODUCTION 1.27 2010-09-15) -Report level: verbose report - -Environment Variable Effect --------------------- ------ -NONE No environment variables were set --------------------------------------------------------------------------------- - -INFO:Timing:2698 - No timing constraints found, doing default enumeration. -INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths - option. All paths that are not constrained will be reported in the - unconstrained paths section(s) of the report. -INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on - a 50 Ohm transmission line loading model. For the details of this model, - and for more information on accounting for different loading conditions, - please see the device datasheet. -INFO:Timing:3390 - This architecture does not support a default System Jitter - value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock - Uncertainty calculation. -INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and - 'Phase Error' calculations, these terms will be zero in the Clock - Uncertainty calculation. Please make appropriate modification to - SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase - Error. - - - -Data Sheet report: ------------------ -All values displayed in nanoseconds (ns) - -Setup/Hold to clock MPI_Node_in<1>_clk -------------------------------+------------+------------+------------------------+--------+ - |Max Setup to|Max Hold to | | Clock | -Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | -------------------------------+------------+------------+------------------------+--------+ -MPI_Node_in<1>_hold_ack | 2.737(R)| -0.159(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_instruction_en | 4.071(R)| 0.589(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<0>| 6.042(R)| -0.041(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<1>| 4.190(R)| -0.166(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<2>| 4.777(R)| -0.006(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<3>| 4.383(R)| 0.591(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<4>| 4.671(R)| 0.293(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<5>| 4.470(R)| 0.402(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<6>| 6.090(R)| 0.591(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<7>| 5.841(R)| -0.048(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_reset | 9.188(R)| 0.148(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_hold_ack | 4.640(R)| -0.950(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_instruction_en | 8.374(R)| -0.871(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<0>| 5.374(R)| 0.149(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<1>| 3.634(R)| 0.474(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<2>| 5.147(R)| -0.980(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<3>| 4.588(R)| -0.194(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<4>| 5.776(R)| -0.884(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<5>| 3.649(R)| 0.450(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<6>| 5.812(R)| -0.893(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<7>| 5.546(R)| -0.839(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -------------------------------+------------+------------+------------------------+--------+ - -Clock MPI_Node_in<1>_clk to Pad --------------------------------------+------------+------------------------+--------+ - | clk (edge) | | Clock | -Destination | to PAD |Internal Clock(s) | Phase | --------------------------------------+------------+------------------------+--------+ -MPI_Node_Out<1>_PushOut<0> | 7.289(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_hold_req | 9.680(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_instruction_fifo_full| 11.178(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<0> | 11.669(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<1> | 12.874(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<2> | 12.627(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<3> | 11.998(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<4> | 13.100(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<5> | 12.859(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<6> | 12.910(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<7> | 12.246(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<8> | 12.194(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<9> | 12.015(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<10> | 12.437(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<11> | 11.483(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<12> | 12.212(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<13> | 12.018(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<14> | 11.796(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<15> | 13.558(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<0> | 14.283(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<1> | 14.529(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<2> | 14.372(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<3> | 14.983(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<4> | 14.650(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<5> | 14.999(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<6> | 15.106(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<7> | 15.639(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<8> | 14.610(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<9> | 14.425(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<10> | 14.894(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<11> | 15.789(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<12> | 15.984(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<13> | 15.947(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<14> | 15.771(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<15> | 15.665(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_en | 17.135(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_we | 16.121(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_PushOut<0> | 8.016(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_hold_req | 9.038(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_instruction_fifo_full| 11.815(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<0> | 13.058(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<1> | 13.810(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<2> | 13.248(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<3> | 13.606(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<4> | 13.555(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<5> | 12.665(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<6> | 13.107(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<7> | 12.666(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<8> | 13.650(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<9> | 12.619(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<10> | 12.100(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<11> | 12.102(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<12> | 12.822(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<13> | 13.308(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<14> | 13.226(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<15> | 13.183(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<0> | 13.658(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<1> | 13.390(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<2> | 12.521(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<3> | 13.593(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<4> | 12.522(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<5> | 13.983(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<6> | 12.378(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<7> | 13.778(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<8> | 12.307(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<9> | 11.844(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<10> | 12.358(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<11> | 12.050(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<12> | 12.818(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<13> | 11.906(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<14> | 12.734(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<15> | 12.445(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_en | 15.705(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_we | 14.082(R)|MPI_Node_in_1__clk_BUFGP| 0.000| --------------------------------------+------------+------------------------+--------+ - -Clock to Setup on destination clock MPI_Node_in<1>_clk -------------------+---------+---------+---------+---------+ - | Src:Rise| Src:Fall| Src:Rise| Src:Fall| -Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| -------------------+---------+---------+---------+---------+ -MPI_Node_in<1>_clk| 10.668| | | | -------------------+---------+---------+---------+---------+ - - -Analysis completed Fri Aug 03 10:17:12 2012 --------------------------------------------------------------------------------- - -Trace Settings: -------------------------- -Trace Settings - -Peak Memory Usage: 245 MB - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.twx =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.twx (revision 17) +++ (revision ) @@ -1,338 +1,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -]> -Release 12.3 Trace (nt64)Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 5 --n 3 -fastpaths -xml MPI_NOC.twx MPI_NOC.ncd -o MPI_NOC.twr MPI_NOC.pcf - -MPI_NOC.ncdMPI_NOC.ncdMPI_NOC.pcfMPI_NOC.pcfxc3s1200e-5PRODUCTION 1.27 2010-09-153INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.MPI_Node_in<1>_clkMPI_Node_in<1>_hold_ack2.737-0.159MPI_Node_in<1>_instruction_en4.0710.589MPI_Node_in<1>_ram_data_out<0>6.042-0.041MPI_Node_in<1>_ram_data_out<1>4.190-0.166MPI_Node_in<1>_ram_data_out<2>4.777-0.006MPI_Node_in<1>_ram_data_out<3>4.3830.591MPI_Node_in<1>_ram_data_out<4>4.6710.293MPI_Node_in<1>_ram_data_out<5>4.4700.402MPI_Node_in<1>_ram_data_out<6>6.0900.591MPI_Node_in<1>_ram_data_out<7>5.841-0.048MPI_Node_in<1>_reset9.1880.148MPI_Node_in<2>_hold_ack4.640-0.950MPI_Node_in<2>_instruction_en8.374-0.871MPI_Node_in<2>_ram_data_out<0>5.3740.149MPI_Node_in<2>_ram_data_out<1>3.6340.474MPI_Node_in<2>_ram_data_out<2>5.147-0.980MPI_Node_in<2>_ram_data_out<3>4.588-0.194MPI_Node_in<2>_ram_data_out<4>5.776-0.884MPI_Node_in<2>_ram_data_out<5>3.6490.450MPI_Node_in<2>_ram_data_out<6>5.812-0.893MPI_Node_in<2>_ram_data_out<7>5.546-0.839MPI_Node_in<1>_clkMPI_Node_in<1>_clkMPI_Node_in<1>_clk10.668Fri Aug 03 10:17:12 2012 TraceTrace Settings - -Peak Memory Usage: 245 MB - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.unroutes =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.unroutes (revision 17) +++ (revision ) @@ -1,9 +1,0 @@ -Release 12.3 - par M.70d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -Fri Aug 03 10:17:02 2012 - -All signals are completely routed. - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.xst =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC.xst (revision 17) +++ (revision ) @@ -1,56 +1,0 @@ -set -tmpdir "xst/projnav.tmp" -set -xsthdpdir "xst" -run --ifn MPI_NOC.prj --ifmt mixed --ofn MPI_NOC --ofmt NGC --p xc3s1200e-5-ft256 --top MPI_NOC --opt_mode Speed --opt_level 1 --iuc NO --keep_hierarchy Soft --netlist_hierarchy As_Optimized --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case Maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style LUT --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract Yes --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract Yes --resource_sharing YES --async_to_sync NO --mult_style LUT --iobuf YES --max_fanout 100000 --bufg 24 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob Auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_map.map =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_map.map (revision 17) +++ (revision ) @@ -1,400 +1,0 @@ -Release 12.3 Map M.70d (nt64) -Xilinx Map Application Log File for Design 'MPI_NOC' - -Design Information ------------------- -Command Line : map -intstyle ise -p xc3s1200e-ft256-5 -cm area -ir off -pr off --c 100 -o MPI_NOC_map.ncd MPI_NOC.ngd MPI_NOC.pcf -Target Device : xc3s1200e -Target Package : ft256 -Target Speed : -5 -Mapper Version : spartan3e -- $Revision: 1.52 $ -Mapped Date : Fri Aug 03 10:15:46 2012 - -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:54 - 'xc3s1200e' is a WebPack part. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. ----------------------------------------------------------------------- -Mapping design into LUTs... -Running directed packing... -Running delay-based LUT packing... -Running related packing... -Updating timing models... -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/dma_rd_grant<3> is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/dma_rd_grant<3> is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/pop_state_cmp_eq0003 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0019 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0019 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/LD_instr/count_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/LD_instr/count_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/dat_exec_or0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/pop_state_cmp_eq0003 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_exec_or0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_signal_or0000 - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmdstate_cmp_eq0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmdstate_cmp_eq0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_signal_or0000 - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/LD_instr/timeout_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/dma_data_in_not0001 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_out_pulse_or00 - 00 is sourced by a combinatorial pin. This is not good design practice. Use - the CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_out_pulse_or00 - 00 is sourced by a combinatorial pin. This is not good design practice. Use - the CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/dma_data_in_not0001 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/LD_instr/fifo_wr_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/dat_exec_or0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_exec_or0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/LD_instr/fifo_wr_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_fifo_read_signal_or - 0000 is sourced by a combinatorial pin. This is not good design practice. Use - the CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_fifo_read_signal_or - 0000 is sourced by a combinatorial pin. This is not good design practice. Use - the CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced - by a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced - by a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/LD_instr/timeout_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0022 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0022 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. - -Design Summary --------------- - -Design Summary: -Number of errors: 0 -Number of warnings: 80 -Logic Utilization: - Total Number Slice Registers: 1,420 out of 17,344 8% - Number used as Flip Flops: 883 - Number used as Latches: 537 - Number of 4 input LUTs: 2,986 out of 17,344 17% -Logic Distribution: - Number of occupied Slices: 1,832 out of 8,672 21% - Number of Slices containing only related logic: 1,832 out of 1,832 100% - Number of Slices containing unrelated logic: 0 out of 1,832 0% - *See NOTES below for an explanation of the effects of unrelated logic. - Total Number of 4 input LUTs: 3,188 out of 17,344 18% - Number used as logic: 2,826 - Number used as a route-thru: 202 - Number used for Dual Port RAMs: 160 - (Two LUTs used per Dual Port RAM) - - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - - Number of bonded IOBs: 146 out of 190 76% - Number of RAMB16s: 4 out of 28 14% - Number of BUFGMUXs: 5 out of 24 20% - -Average Fanout of Non-Clock Nets: 3.61 - -Peak Memory Usage: 289 MB -Total REAL time to MAP completion: 10 secs -Total CPU time to MAP completion: 5 secs - -NOTES: - - Related logic is defined as being logic that shares connectivity - e.g. two - LUTs are "related" if they share common inputs. When assembling slices, - Map gives priority to combine logic that is related. Doing so results in - the best timing performance. - - Unrelated logic shares no connectivity. Map will only begin packing - unrelated logic into a slice once 99% of the slices are occupied through - related logic packing. - - Note that once logic distribution reaches the 99% level through related - logic packing, this does not mean the device is completely utilized. - Unrelated logic packing will then begin, continuing until all usable LUTs - and FFs are occupied. Depending on your timing budget, increased levels of - unrelated logic packing may adversely affect the overall timing performance - of your design. - -Mapping completed. -See MAP report file "MPI_NOC_map.mrp" for details. Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_map.mrp =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_map.mrp (revision 17) +++ (revision ) @@ -1,704 +1,0 @@ -Release 12.3 Map M.70d (nt64) -Xilinx Mapping Report File for Design 'MPI_NOC' - -Design Information ------------------- -Command Line : map -intstyle ise -p xc3s1200e-ft256-5 -cm area -ir off -pr off --c 100 -o MPI_NOC_map.ncd MPI_NOC.ngd MPI_NOC.pcf -Target Device : xc3s1200e -Target Package : ft256 -Target Speed : -5 -Mapper Version : spartan3e -- $Revision: 1.52 $ -Mapped Date : Fri Aug 03 10:15:46 2012 - -Design Summary --------------- -Number of errors: 0 -Number of warnings: 80 -Logic Utilization: - Total Number Slice Registers: 1,420 out of 17,344 8% - Number used as Flip Flops: 883 - Number used as Latches: 537 - Number of 4 input LUTs: 2,986 out of 17,344 17% -Logic Distribution: - Number of occupied Slices: 1,832 out of 8,672 21% - Number of Slices containing only related logic: 1,832 out of 1,832 100% - Number of Slices containing unrelated logic: 0 out of 1,832 0% - *See NOTES below for an explanation of the effects of unrelated logic. - Total Number of 4 input LUTs: 3,188 out of 17,344 18% - Number used as logic: 2,826 - Number used as a route-thru: 202 - Number used for Dual Port RAMs: 160 - (Two LUTs used per Dual Port RAM) - - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - - Number of bonded IOBs: 146 out of 190 76% - Number of RAMB16s: 4 out of 28 14% - Number of BUFGMUXs: 5 out of 24 20% - -Average Fanout of Non-Clock Nets: 3.61 - -Peak Memory Usage: 289 MB -Total REAL time to MAP completion: 10 secs -Total CPU time to MAP completion: 5 secs - -NOTES: - - Related logic is defined as being logic that shares connectivity - e.g. two - LUTs are "related" if they share common inputs. When assembling slices, - Map gives priority to combine logic that is related. Doing so results in - the best timing performance. - - Unrelated logic shares no connectivity. Map will only begin packing - unrelated logic into a slice once 99% of the slices are occupied through - related logic packing. - - Note that once logic distribution reaches the 99% level through related - logic packing, this does not mean the device is completely utilized. - Unrelated logic packing will then begin, continuing until all usable LUTs - and FFs are occupied. Depending on your timing budget, increased levels of - unrelated logic packing may adversely affect the overall timing performance - of your design. - -Table of Contents ------------------ -Section 1 - Errors -Section 2 - Warnings -Section 3 - Informational -Section 4 - Removed Logic Summary -Section 5 - Removed Logic -Section 6 - IOB Properties -Section 7 - RPMs -Section 8 - Guide Report -Section 9 - Area Group and Partition Summary -Section 10 - Timing Report -Section 11 - Configuration String Information -Section 12 - Control Set Information -Section 13 - Utilization by Hierarchy - -Section 1 - Errors ------------------- - -Section 2 - Warnings --------------------- -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/dma_rd_grant<3> is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/dma_rd_grant<3> is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/pop_state_cmp_eq0003 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/LD_instr/Mtrien_Ram_address_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CTR_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/LD_instr/Mtridata_Ram_address_i_not0001 is sourced by - a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0019 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0019 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/LD_instr/count_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/LD_instr/count_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_1_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_0_not0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_2_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_rd_grant_3_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataRam_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/dat_exec_or0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/pop_state_cmp_eq0003 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DS_Ack_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/Datalen_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_exec_or0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_signal_or0000 - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX1_FSM/AppInitReq_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmdstate_cmp_eq0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmdstate_cmp_eq0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_signal_or0000 - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_0_not0001 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_1_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/LD_instr/timeout_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/dma_data_in_not0001 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_2_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/dma_wr_grant_3_cmp_eq0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/WeRam_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/NextRank_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_data_out_pulse_or00 - 00 is sourced by a combinatorial pin. This is not good design practice. Use - the CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_data_out_pulse_or00 - 00 is sourced by a combinatorial pin. This is not good design practice. Use - the CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/dma_data_in_not0001 is sourced by a combinatorial - pin. This is not good design practice. Use the CE pin to control the loading - of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/DataToSend_0_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/PortNum_i_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/LD_instr/fifo_wr_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/timeout_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/dat_exec_or0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_exec_or0000 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/RankAsked_i_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX1_FSM/Result_1_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/LD_instr/fifo_wr_i_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/cmd_fifo_read_signal_or - 0000 is sourced by a combinatorial pin. This is not good design practice. Use - the CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/cmd_fifo_read_signal_or - 0000 is sourced by a combinatorial pin. This is not good design practice. Use - the CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX2_FSM/fifo_wr_en_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced - by a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX4_FSM/CmdReceived_2_cmp_eq0000 is sourced - by a combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/LD_instr/timeout_not0001 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/LD_instr/etloadinst_cmp_eq0022 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/LD_instr/etloadinst_cmp_eq0022 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[1].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_rd_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - connect_core[2].hardmpi/MPI_CORE_EX1_FSM/ram_wr_or0000 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. - -Section 3 - Informational -------------------------- -INFO:Security:54 - 'xc3s1200e' is a WebPack part. -INFO:LIT:243 - Logical network MPI_Node_in<2>_clk has no load. -INFO:LIT:395 - The above info message is repeated 95 more times for the - following (max. 5 shown): - MPI_Node_in<2>_packet_ack, - MPI_Node_in<1>_packet_ack, - MPI_Node_in<2>_reset, - connect_core[2].hardmpi/MyRank<0>, - connect_core[2].hardmpi/MyRank<1> - To see the details of these info messages, please use the -detail switch. -INFO:MapLib:562 - No environment variables are currently set. -INFO:LIT:244 - All of the single ended outputs in this design are using slew - rate limited output drivers. The delay on speed critical single ended outputs - can be dramatically reduced by designating them as fast outputs. - -Section 4 - Removed Logic Summary ---------------------------------- - 41 block(s) optimized away - -Section 5 - Removed Logic -------------------------- - -Optimized Block(s): -TYPE BLOCK -GND - Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI -FO/XST_GND -VCC - Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI -FO/XST_VCC -GND - Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI -FO/fifo_RAM_256/XST_GND -VCC - Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI -FO/fifo_RAM_256/XST_VCC -GND - Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI -FO/XST_GND -VCC - Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI -FO/XST_VCC -GND - Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI -FO/fifo_RAM_256/XST_GND -VCC - Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_PORT_FI -FO/fifo_RAM_256/XST_VCC -GND - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_GND -VCC - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_VCC -GND - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo_RAM -_256/XST_GND -VCC - Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo_RAM -_256/XST_VCC -GND Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/XST_GND -VCC Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/XST_VCC -GND - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_GND -VCC - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_VCC -GND - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo_RAM -_256/XST_GND -VCC - Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo_RAM -_256/XST_VCC -VCC Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/XST_VCC -GND connect_core[1].hardmpi/Instruction_Fifo2/XST_GND -GND connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/XST_GND -GND connect_core[1].hardmpi/LD_instr/XST_GND -VCC connect_core[1].hardmpi/LD_instr/XST_VCC -GND connect_core[1].hardmpi/MPI_CORE_DMA_ARBITER/XST_GND -GND connect_core[1].hardmpi/MPI_CORE_EX1_FSM/XST_GND -VCC connect_core[1].hardmpi/MPI_CORE_EX1_FSM/XST_VCC -GND connect_core[1].hardmpi/MPI_CORE_EX2_FSM/XST_GND -GND connect_core[1].hardmpi/MPI_CORE_EX4_FSM/XST_GND -VCC connect_core[1].hardmpi/MPI_CORE_EX4_FSM/XST_VCC -GND connect_core[1].hardmpi/XST_GND -GND connect_core[2].hardmpi/Instruction_Fifo2/XST_GND -GND connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/XST_GND -GND connect_core[2].hardmpi/LD_instr/XST_GND -VCC connect_core[2].hardmpi/LD_instr/XST_VCC -GND connect_core[2].hardmpi/MPI_CORE_DMA_ARBITER/XST_GND -GND connect_core[2].hardmpi/MPI_CORE_EX1_FSM/XST_GND -VCC connect_core[2].hardmpi/MPI_CORE_EX1_FSM/XST_VCC -GND connect_core[2].hardmpi/MPI_CORE_EX2_FSM/XST_GND -GND connect_core[2].hardmpi/MPI_CORE_EX4_FSM/XST_GND -VCC connect_core[2].hardmpi/MPI_CORE_EX4_FSM/XST_VCC -GND connect_core[2].hardmpi/XST_GND - -To enable printing of redundant blocks removed and signals merged, set the -detailed map report option and rerun map. - -Section 6 - IOB Properties --------------------------- - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | -| | | | | Term | Strength | Rate | | | Delay | -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -| MPI_Node_Out<1>_PushOut<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_PushOut<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_PushOut<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_PushOut<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_PushOut<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_PushOut<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_PushOut<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_PushOut<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_barrier_completed | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_hold_req | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_instruction_fifo_f | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ull | | | | | | | | | | -| MPI_Node_Out<1>_packet_received | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_rd<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_address_wr<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_data_in<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_data_in<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_data_in<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_data_in<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_data_in<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_data_in<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_data_in<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_data_in<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<1>_ram_we | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_PushOut<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_PushOut<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_PushOut<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_PushOut<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_PushOut<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_PushOut<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_PushOut<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_PushOut<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_barrier_completed | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_hold_req | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_instruction_fifo_f | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| ull | | | | | | | | | | -| MPI_Node_Out<2>_packet_received | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_rd<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_address_wr<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_data_in<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_data_in<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_data_in<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_data_in<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_data_in<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_data_in<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_data_in<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_data_in<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_Out<2>_ram_we | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | -| MPI_Node_in<1>_clk | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_hold_ack | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_instruction<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_instruction<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_instruction<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_instruction<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_instruction<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_instruction<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_instruction<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_instruction<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_instruction_en | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_ram_data_out<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_ram_data_out<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_ram_data_out<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_ram_data_out<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_ram_data_out<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_ram_data_out<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_ram_data_out<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_ram_data_out<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<1>_reset | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_hold_ack | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_instruction<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_instruction<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_instruction<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_instruction<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_instruction<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_instruction<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_instruction<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_instruction<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_instruction_en | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_ram_data_out<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_ram_data_out<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_ram_data_out<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_ram_data_out<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_ram_data_out<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_ram_data_out<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_ram_data_out<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -| MPI_Node_in<2>_ram_data_out<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ - -Section 7 - RPMs ----------------- - -Section 8 - Guide Report ------------------------- -Guide not run on this design. - -Section 9 - Area Group and Partition Summary --------------------------------------------- - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -Area Group Information ----------------------- - - No area groups were found in this design. - ----------------------- - -Section 10 - Timing Report --------------------------- -This design was not run using timing mode. - -Section 11 - Configuration String Details ------------------------------------------ -Use the "-detail" map option to print out Configuration Strings - -Section 12 - Control Set Information ------------------------------------- -No control set information for this architecture. - -Section 13 - Utilization by Hierarchy -------------------------------------- -Use the "-detail" map option to print out the Utilization by Hierarchy section. Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_pad.csv =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_pad.csv (revision 17) +++ (revision ) @@ -1,287 +1,0 @@ -#Release 12.3 - par M.70d (nt64) -#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -#Fri Aug 03 10:17:01 2012 - -# -## NOTE: This file is designed to be imported into a spreadsheet program -# such as Microsoft Excel for viewing, printing and sorting. The | -# character is used as the data field separator. This file is also designed -# to support parsing. -# -#INPUT FILE: MPI_NOC_map.ncd -#OUTPUT FILE: MPI_NOC_pad.csv -#PART TYPE: xc3s1200e -#SPEED GRADE: -5 -#PACKAGE: ft256 -# -# Pinout by Pin Number: -# -# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, -Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity, -A1,,,GND,,,,,,,,,,,, -A2,,,TDI,,,,,,,,,,,, -A3,,IBUF,IP,UNUSED,,0,,,,,,,,, -A4,MPI_Node_Out<1>_ram_address_wr<14>,IOB,IO_L17N_0/VREF_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -A5,MPI_Node_Out<1>_ram_address_wr<13>,IOB,IO_L17P_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -A6,,,VCCAUX,,,,,,,,2.5,,,, -A7,MPI_Node_Out<1>_ram_address_wr<3>,IOB,IO,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -A8,,DIFFMI,IP_L10P_0/GCLK8,UNUSED,,0,,,,,,,,, -A9,MPI_Node_Out<1>_ram_address_wr<0>,IOB,IO_L09N_0/GCLK7,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -A10,MPI_Node_Out<2>_ram_address_rd<15>,IOB,IO_L09P_0/GCLK6,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -A11,,,VCCAUX,,,,,,,,2.5,,,, -A12,MPI_Node_Out<2>_ram_address_rd<4>,IOB,IO,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -A13,,DIFFS,IO_L03N_0/VREF_0,UNUSED,,0,,,,,,,,, -A14,,DIFFS,IO_L01N_0,UNUSED,,0,,,,,,,,, -A15,,,TCK,,,,,,,,,,,, -A16,,,GND,,,,,,,,,,,, -B1,MPI_Node_in<2>_ram_data_out<6>,IBUF,IO_L01P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE, -B2,MPI_Node_Out<1>_ram_data_in<5>,IOB,IO_L01N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -B3,MPI_Node_Out<1>_ram_data_in<3>,IOB,IO_L19N_0/HSWAP,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -B4,MPI_Node_Out<1>_ram_address_wr<15>,IOB,IO,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -B5,,,VCCO_0,,,0,,,,,2.50,,,, -B6,MPI_Node_Out<1>_ram_address_wr<10>,IOB,IO,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -B7,MPI_Node_Out<1>_ram_address_wr<6>,IOB,IO_L13P_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -B8,MPI_Node_in<1>_clk,IBUF,IP_L10N_0/GCLK9,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE, -B9,,,GND,,,,,,,,,,,, -B10,MPI_Node_Out<2>_ram_address_rd<9>,IOB,IO,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -B11,MPI_Node_Out<2>_ram_address_rd<5>,IOB,IO_L05N_0/VREF_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -B12,,,VCCO_0,,,0,,,,,2.50,,,, -B13,,DIFFM,IO_L03P_0,UNUSED,,0,,,,,,,,, -B14,,DIFFM,IO_L01P_0,UNUSED,,0,,,,,,,,, -B15,,,TMS,,,,,,,,,,,, -B16,,IBUF,IP,UNUSED,,1,,,,,,,,, -C1,MPI_Node_Out<1>_ram_data_in<6>,IOB,IO_L02P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -C2,MPI_Node_Out<1>_ram_data_in<7>,IOB,IO_L02N_3/VREF_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -C3,MPI_Node_Out<1>_ram_data_in<2>,IOB,IO_L19P_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -C4,MPI_Node_Out<1>_ram_data_in<1>,IOB,IO_L18N_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -C5,MPI_Node_Out<2>_ram_address_wr<5>,IOB,IO_L18P_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -C6,MPI_Node_Out<1>_ram_address_wr<11>,IOB,IO_L15P_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -C7,MPI_Node_Out<1>_ram_address_wr<7>,IOB,IO_L13N_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -C8,MPI_Node_Out<1>_ram_address_wr<1>,IOB,IO_L11P_0/GCLK10,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -C9,,DIFFSI,IP_L07N_0,UNUSED,,0,,,,,,,,, -C10,,DIFFMI,IP_L07P_0,UNUSED,,0,,,,,,,,, -C11,MPI_Node_Out<2>_ram_address_rd<7>,IOB,IO_L05P_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -C12,,DIFFSI,IP_L02N_0,UNUSED,,0,,,,,,,,, -C13,,IBUF,IP,UNUSED,,0,,,,,,,,, -C14,,,TDO,,,,,,,,,,,, -C15,,DIFFS,IO_L19N_1/LDC2,UNUSED,,1,,,,,,,,, -C16,,DIFFM,IO_L19P_1/LDC1,UNUSED,,1,,,,,,,,, -D1,MPI_Node_Out<2>_ram_address_wr<7>,IOB,IO_L05P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -D2,MPI_Node_in<2>_ram_data_out<0>,IBUF,IP,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE, -D3,,,PROG_B,,,,,,,,,,,, -D4,,,VCCINT,,,,,,,,1.2,,,, -D5,,DIFFMI,IP_L16P_0,UNUSED,,0,,,,,,,,, -D6,MPI_Node_Out<1>_ram_address_wr<12>,IOB,IO_L15N_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -D7,MPI_Node_Out<1>_ram_address_wr<9>,IOB,IO_L14N_0/VREF_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -D8,MPI_Node_Out<1>_ram_address_wr<2>,IOB,IO_L11N_0/GCLK11,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -D9,MPI_Node_Out<2>_ram_address_rd<14>,IOB,IO/VREF_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -D10,MPI_Node_Out<2>_ram_address_rd<10>,IOB,IO_L06P_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -D11,MPI_Node_Out<2>_ram_address_rd<2>,IOB,IO_L04P_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -D12,,DIFFMI,IP_L02P_0,UNUSED,,0,,,,,,,,, -D13,,,VCCINT,,,,,,,,1.2,,,, -D14,,DIFFS,IO_L18N_1/LDC0,UNUSED,,1,,,,,,,,, -D15,,DIFFM,IO_L18P_1/HDC,UNUSED,,1,,,,,,,,, -D16,,IBUF,IP/VREF_1,UNUSED,,1,,,,,,,,, -E1,MPI_Node_in<2>_ram_data_out<5>,IBUF,IO_L05N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE, -E2,,,VCCO_3,,,3,,,,,2.50,,,, -E3,MPI_Node_Out<2>_ram_address_wr<0>,IOB,IO_L03P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -E4,MPI_Node_Out<2>_ram_address_wr<1>,IOB,IO_L03N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -E5,,,VCCINT,,,,,,,,1.2,,,, -E6,,DIFFSI,IP_L16N_0,UNUSED,,0,,,,,,,,, -E7,MPI_Node_Out<1>_ram_address_wr<8>,IOB,IO_L14P_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -E8,MPI_Node_Out<1>_ram_address_wr<4>,IOB,IO_L12P_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -E9,MPI_Node_Out<2>_ram_address_rd<12>,IOB,IO_L08P_0/GCLK4,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -E10,MPI_Node_Out<2>_ram_address_rd<11>,IOB,IO_L06N_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -E11,MPI_Node_Out<2>_ram_address_rd<6>,IOB,IO_L04N_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -E12,,,VCCINT,,,,,,,,1.2,,,, -E13,MPI_Node_Out<2>_ram_address_rd<8>,IOB,IO_L17P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -E14,,IBUF,IP,UNUSED,,1,,,,,,,,, -E15,,,VCCO_1,,,1,,,,,2.50,,,, -E16,MPI_Node_Out<2>_ram_address_rd<0>,IOB,IO_L17N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -F1,,,VCCAUX,,,,,,,,2.5,,,, -F2,MPI_Node_in<2>_ram_data_out<2>,IBUF,IP,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE, -F3,MPI_Node_Out<2>_ram_address_wr<2>,IOB,IO_L04P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -F4,MPI_Node_Out<2>_ram_address_wr<3>,IOB,IO_L04N_3/VREF_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -F5,MPI_Node_in<2>_ram_data_out<1>,IBUF,IP,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE, -F6,,,GND,,,,,,,,,,,, -F7,,,VCCO_0,,,0,,,,,2.50,,,, -F8,MPI_Node_Out<1>_ram_address_wr<5>,IOB,IO_L12N_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -F9,MPI_Node_Out<2>_ram_address_rd<13>,IOB,IO_L08N_0/GCLK5,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -F10,,,VCCO_0,,,0,,,,,2.50,,,, -F11,,,GND,,,,,,,,,,,, -F12,MPI_Node_Out<2>_ram_address_rd<1>,IOB,IO_L16N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -F13,,DIFFM,IO_L16P_1,UNUSED,,1,,,,,,,,, -F14,MPI_Node_Out<2>_ram_address_rd<3>,IOB,IO_L15P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -F15,,DIFFS,IO_L15N_1,UNUSED,,1,,,,,,,,, -F16,,,VCCAUX,,,,,,,,2.5,,,, -G1,MPI_Node_in<2>_ram_data_out<3>,IBUF,IP/VREF_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE, -G2,MPI_Node_Out<2>_ram_address_wr<9>,IOB,IO_L07N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -G3,MPI_Node_Out<1>_ram_data_in<0>,IOB,IO_L07P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -G4,MPI_Node_Out<2>_ram_address_wr<8>,IOB,IO_L06N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -G5,MPI_Node_Out<2>_ram_address_wr<6>,IOB,IO_L06P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -G6,,,VCCO_3,,,3,,,,,2.50,,,, -G7,,,GND,,,,,,,,,,,, -G8,,,GND,,,,,,,,,,,, -G9,,,GND,,,,,,,,,,,, -G10,,,GND,,,,,,,,,,,, -G11,,,VCCO_1,,,1,,,,,2.50,,,, -G12,,IBUF,IP,UNUSED,,1,,,,,,,,, -G13,MPI_Node_Out<2>_hold_req,IOB,IO_L14P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -G14,,DIFFS,IO_L14N_1/A0,UNUSED,,1,,,,,,,,, -G15,MPI_Node_Out<2>_ram_en,IOB,IO_L13P_1/A2,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -G16,,DIFFS,IO_L13N_1/A1,UNUSED,,1,,,,,,,,, -H1,MPI_Node_in<2>_ram_data_out<4>,IBUF,IP,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE, -H2,,,GND,,,,,,,,,,,, -H3,MPI_Node_Out<2>_ram_address_wr<12>,IOB,IO_L09P_3/LHCLK2,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -H4,MPI_Node_Out<2>_ram_address_wr<13>,IOB,IO_L09N_3/LHCLK3/IRDY2,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -H5,MPI_Node_Out<2>_ram_address_wr<10>,IOB,IO_L08P_3/LHCLK0,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -H6,MPI_Node_Out<2>_ram_address_wr<11>,IOB,IO_L08N_3/LHCLK1,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -H7,,,GND,,,,,,,,,,,, -H8,,,GND,,,,,,,,,,,, -H9,,,GND,,,,,,,,,,,, -H10,,,GND,,,,,,,,,,,, -H11,,DIFFS,IO_L12N_1/A3/RHCLK7,UNUSED,,1,,,,,,,,, -H12,,DIFFM,IO_L12P_1/A4/RHCLK6,UNUSED,,1,,,,,,,,, -H13,,IBUF,IP/VREF_1,UNUSED,,1,,,,,,,,, -H14,MPI_Node_in<2>_instruction<6>,IBUF,IO_L11N_1/A5/RHCLK5,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -H15,MPI_Node_in<2>_instruction<7>,IBUF,IO_L11P_1/A6/RHCLK4/IRDY1,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -H16,MPI_Node_in<2>_instruction<3>,IBUF,IP,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -J1,MPI_Node_Out<2>_ram_data_in<0>,IOB,IO_L12P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -J2,MPI_Node_Out<2>_ram_address_wr<14>,IOB,IO_L10P_3/LHCLK4/TRDY2,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -J3,MPI_Node_Out<2>_ram_address_wr<15>,IOB,IO_L10N_3/LHCLK5,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -J4,MPI_Node_Out<1>_ram_data_in<4>,IOB,IO_L11N_3/LHCLK7,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -J5,MPI_Node_Out<2>_ram_address_wr<4>,IOB,IO_L11P_3/LHCLK6,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -J6,MPI_Node_in<2>_ram_data_out<7>,IBUF,IP,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE, -J7,,,GND,,,,,,,,,,,, -J8,,,GND,,,,,,,,,,,, -J9,,,GND,,,,,,,,,,,, -J10,,,GND,,,,,,,,,,,, -J11,,IBUF,IP,UNUSED,,1,,,,,,,,, -J12,MPI_Node_in<2>_instruction<4>,IBUF,IP,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -J13,MPI_Node_in<2>_instruction<2>,IBUF,IO_L10N_1/A7/RHCLK3/TRDY1,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -J14,MPI_Node_in<2>_instruction<0>,IBUF,IO_L10P_1/A8/RHCLK2,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -J15,,,GND,,,,,,,,,,,, -J16,,DIFFS,IO_L09N_1/A9/RHCLK1,UNUSED,,1,,,,,,,,, -K1,MPI_Node_Out<2>_ram_data_in<1>,IOB,IO_L12N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -K2,MPI_Node_Out<2>_ram_data_in<2>,IOB,IO_L13P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -K3,MPI_Node_Out<2>_ram_data_in<3>,IOB,IO_L13N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -K4,,IBUF,IP,UNUSED,,3,,,,,,,,, -K5,MPI_Node_Out<2>_ram_data_in<6>,IOB,IO_L15P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -K6,,,VCCO_3,,,3,,,,,2.50,,,, -K7,,,GND,,,,,,,,,,,, -K8,,,GND,,,,,,,,,,,, -K9,,,GND,,,,,,,,,,,, -K10,,,GND,,,,,,,,,,,, -K11,,,VCCO_1,,,1,,,,,2.50,,,, -K12,,DIFFS,IO_L07N_1/A11,UNUSED,,1,,,,,,,,, -K13,MPI_Node_in<2>_instruction<1>,IBUF,IO_L07P_1/A12,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -K14,,DIFFS,IO_L08N_1/VREF_1,UNUSED,,1,,,,,,,,, -K15,,DIFFM,IO_L08P_1,UNUSED,,1,,,,,,,,, -K16,MPI_Node_in<2>_instruction<5>,IBUF,IO_L09P_1/A10/RHCLK0,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -L1,,,VCCAUX,,,,,,,,2.5,,,, -L2,MPI_Node_Out<2>_ram_data_in<5>,IOB,IO_L14N_3/VREF_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -L3,MPI_Node_Out<2>_ram_data_in<4>,IOB,IO_L14P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -L4,MPI_Node_Out<2>_PushOut<5>,IOB,IO_L17N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -L5,MPI_Node_Out<2>_ram_data_in<7>,IOB,IO_L15N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -L6,,,GND,,,,,,,,,,,, -L7,,,VCCO_2,,,2,,,,,2.50,,,, -L8,MPI_Node_Out<1>_ram_address_rd<9>,IOB,IO_L09N_2/D6/GCLK13,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -L9,MPI_Node_Out<1>_ram_address_rd<11>,IOB,IO_L13P_2/M0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -L10,,,VCCO_2,,,2,,,,,2.50,,,, -L11,,,GND,,,,,,,,,,,, -L12,,DIFFM,IO_L05P_1,UNUSED,,1,,,,,,,,, -L13,MPI_Node_Out<1>_instruction_fifo_full,IOB,IO_L05N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -L14,,DIFFM,IO_L06P_1,UNUSED,,1,,,,,,,,, -L15,,DIFFS,IO_L06N_1,UNUSED,,1,,,,,,,,, -L16,,,VCCAUX,,,,,,,,2.5,,,, -M1,MPI_Node_Out<2>_PushOut<0>,IOB,IO_L16P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -M2,,,VCCO_3,,,3,,,,,2.50,,,, -M3,,IBUF,IP,UNUSED,,3,,,,,,,,, -M4,MPI_Node_Out<2>_PushOut<4>,IOB,IO_L17P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -M5,,,VCCINT,,,,,,,,1.2,,,, -M6,MPI_Node_Out<1>_ram_address_rd<5>,IOB,IO_L05P_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -M7,MPI_Node_Out<1>_ram_address_rd<6>,IOB,IO,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -M8,MPI_Node_Out<1>_ram_address_rd<3>,IOB,IO_L09P_2/D7/GCLK12,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -M9,MPI_Node_Out<1>_hold_req,IOB,IO_L13N_2/DIN/D0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -M10,MPI_Node_Out<1>_PushOut<0>,IOB,IO_L15N_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -M11,MPI_Node_in<2>_instruction_en,IBUF,IP_L17N_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -M12,,,VCCINT,,,,,,,,1.2,,,, -M13,MPI_Node_in<1>_instruction<3>,IBUF,IP,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -M14,MPI_Node_in<1>_instruction<6>,IBUF,IP,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -M15,,,VCCO_1,,,1,,,,,2.50,,,, -M16,MPI_Node_Out<1>_ram_en,IOB,IO_L04N_1/VREF_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -N1,MPI_Node_Out<2>_PushOut<1>,IOB,IO_L16N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -N2,,IBUF,IP/VREF_3,UNUSED,,3,,,,,,,,, -N3,,IBUF,IP,UNUSED,,3,,,,,,,,, -N4,,,VCCINT,,,,,,,,1.2,,,, -N5,MPI_Node_Out<1>_PushOut<2>,IOB,IO_L03N_2/MOSI/CSI_B,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -N6,MPI_Node_Out<1>_ram_address_rd<2>,IOB,IO_L05N_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -N7,MPI_Node_Out<1>_ram_address_rd<0>,IOB,IO_L07P_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -N8,MPI_Node_Out<1>_ram_address_rd<13>,IOB,IO_L10P_2/D4/GCLK14,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -N9,MPI_Node_Out<1>_ram_address_rd<10>,IOB,IO_L12N_2/D1/GCLK3,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -N10,MPI_Node_in<1>_hold_ack,IBUF,IO_L15P_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -N11,MPI_Node_in<1>_instruction<5>,IBUF,IP_L17P_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -N12,MPI_Node_in<1>_instruction<2>,IBUF,IO_L18N_2/A20,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -N13,,,VCCINT,,,,,,,,1.2,,,, -N14,MPI_Node_in<1>_instruction<4>,IBUF,IO_L03P_1,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -N15,MPI_Node_in<1>_instruction<1>,IBUF,IO_L03N_1/VREF_1,INPUT,LVCMOS25*,1,,,,NONE,,UNLOCATED,NO,NONE, -N16,MPI_Node_Out<2>_instruction_fifo_full,IOB,IO_L04P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P1,MPI_Node_Out<2>_PushOut<3>,IOB,IO_L18N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P2,MPI_Node_Out<1>_PushOut<1>,IOB,IO_L18P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P3,MPI_Node_Out<1>_PushOut<4>,IOB,IO_L01P_2/CSO_B,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P4,MPI_Node_Out<2>_PushOut<2>,IOB,IO_L01N_2/INIT_B,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P5,MPI_Node_Out<1>_PushOut<3>,IOB,IO_L03P_2/DOUT/BUSY,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P6,MPI_Node_Out<2>_ram_we,IOB,IO_L06N_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P7,MPI_Node_Out<1>_ram_address_rd<8>,IOB,IO_L07N_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P8,MPI_Node_Out<1>_ram_we,IOB,IO_L10N_2/D3/GCLK15,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P9,MPI_Node_Out<1>_ram_address_rd<12>,IOB,IO_L12P_2/D2/GCLK2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P10,MPI_Node_Out<1>_ram_address_rd<15>,IOB,IO_L14P_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P11,MPI_Node_in<1>_instruction_en,IBUF,IO_L16N_2/A22,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -P12,MPI_Node_in<1>_instruction<0>,IBUF,IO_L18P_2/A21,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -P13,,IOB,IO/VREF_2,UNUSED,,2,,,,,,,,, -P14,MPI_Node_Out<1>_PushOut<6>,IOB,IO_L20P_2/VS0/A17,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -P15,,DIFFS,IO_L02N_1/A13,UNUSED,,1,,,,,,,,, -P16,MPI_Node_Out<1>_barrier_completed,IOB,IO_L02P_1/A14,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -R1,MPI_Node_Out<2>_PushOut<7>,IOB,IO_L19N_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -R2,MPI_Node_Out<2>_PushOut<6>,IOB,IO_L19P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -R3,MPI_Node_in<1>_ram_data_out<2>,IBUF,IP_L02N_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -R4,MPI_Node_Out<1>_ram_address_rd<4>,IOB,IO/VREF_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -R5,,,VCCO_2,,,2,,,,,2.50,,,, -R6,MPI_Node_Out<1>_ram_address_rd<7>,IOB,IO_L06P_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -R7,MPI_Node_in<1>_ram_data_out<3>,IBUF,IP_L08P_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -R8,,,GND,,,,,,,,,,,, -R9,MPI_Node_in<1>_ram_data_out<6>,IBUF,IP_L11N_2/M2/GCLK1,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -R10,MPI_Node_in<1>_ram_data_out<7>,IBUF,IO_L14N_2/VREF_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -R11,MPI_Node_in<2>_hold_ack,IBUF,IO_L16P_2/A23,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -R12,,,VCCO_2,,,2,,,,,2.50,,,, -R13,MPI_Node_Out<1>_PushOut<7>,IOB,IO_L19N_2/VS1/A18,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -R14,,DIFFS,IO_L20N_2/CCLK,UNUSED,,2,,,,,,,,, -R15,MPI_Node_Out<2>_barrier_completed,IOB,IO_L01N_1/A15,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -R16,MPI_Node_Out<2>_packet_received,IOB,IO_L01P_1/A16,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -T1,,,GND,,,,,,,,,,,, -T2,MPI_Node_in<1>_ram_data_out<0>,IBUF,IP,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -T3,MPI_Node_in<1>_ram_data_out<1>,IBUF,IP_L02P_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -T4,MPI_Node_Out<1>_packet_received,IOB,IO_L04P_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -T5,MPI_Node_Out<1>_ram_address_rd<1>,IOB,IO_L04N_2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -T6,,,VCCAUX,,,,,,,,2.5,,,, -T7,MPI_Node_in<1>_ram_data_out<4>,IBUF,IP_L08N_2/VREF_2,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -T8,MPI_Node_Out<1>_PushOut<5>,IOB,IO/D5,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -T9,MPI_Node_in<1>_ram_data_out<5>,IBUF,IP_L11P_2/RDWR_B/GCLK0,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -T10,MPI_Node_Out<1>_ram_address_rd<14>,IOB,IO/M1,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, -T11,,,VCCAUX,,,,,,,,2.5,,,, -T12,,IOB,IO,UNUSED,,2,,,,,,,,, -T13,MPI_Node_in<1>_instruction<7>,IBUF,IO_L19P_2/VS2/A19,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -T14,MPI_Node_in<1>_reset,IBUF,IP,INPUT,LVCMOS25*,2,,,,NONE,,UNLOCATED,NO,NONE, -T15,,,DONE,,,,,,,,,,,, -T16,,,GND,,,,,,,,,,,, - -# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, -# -#* Default value. -#** This default Pullup/Pulldown value can be overridden in Bitgen. -#****** Special VCCO requirements may apply. Please consult the device -# family datasheet for specific guideline on VCCO requirements. -# -# -# Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_pad.txt =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_pad.txt (revision 17) +++ (revision ) @@ -1,286 +1,0 @@ -Release 12.3 - par M.70d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -Fri Aug 03 10:17:01 2012 - - -INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: -1. The _pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. -2. The _pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. -3. The .pad file designed for parsing by customers. It uses the "|" as a data field separator. - -INPUT FILE: MPI_NOC_map.ncd -OUTPUT FILE: MPI_NOC_pad.txt -PART TYPE: xc3s1200e -SPEED GRADE: -5 -PACKAGE: ft256 - -Pinout by Pin Number: - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -|Pin Number|Signal Name |Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity| -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -|A1 | | |GND | | | | | | | | | | | | -|A2 | | |TDI | | | | | | | | | | | | -|A3 | |IBUF |IP |UNUSED | |0 | | | | | | | | | -|A4 |MPI_Node_Out<1>_ram_address_wr<14> |IOB |IO_L17N_0/VREF_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|A5 |MPI_Node_Out<1>_ram_address_wr<13> |IOB |IO_L17P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|A6 | | |VCCAUX | | | | | | | |2.5 | | | | -|A7 |MPI_Node_Out<1>_ram_address_wr<3> |IOB |IO |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|A8 | |DIFFMI |IP_L10P_0/GCLK8 |UNUSED | |0 | | | | | | | | | -|A9 |MPI_Node_Out<1>_ram_address_wr<0> |IOB |IO_L09N_0/GCLK7 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|A10 |MPI_Node_Out<2>_ram_address_rd<15> |IOB |IO_L09P_0/GCLK6 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|A11 | | |VCCAUX | | | | | | | |2.5 | | | | -|A12 |MPI_Node_Out<2>_ram_address_rd<4> |IOB |IO |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|A13 | |DIFFS |IO_L03N_0/VREF_0 |UNUSED | |0 | | | | | | | | | -|A14 | |DIFFS |IO_L01N_0 |UNUSED | |0 | | | | | | | | | -|A15 | | |TCK | | | | | | | | | | | | -|A16 | | |GND | | | | | | | | | | | | -|B1 |MPI_Node_in<2>_ram_data_out<6> |IBUF |IO_L01P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE | -|B2 |MPI_Node_Out<1>_ram_data_in<5> |IOB |IO_L01N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|B3 |MPI_Node_Out<1>_ram_data_in<3> |IOB |IO_L19N_0/HSWAP |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|B4 |MPI_Node_Out<1>_ram_address_wr<15> |IOB |IO |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|B5 | | |VCCO_0 | | |0 | | | | |2.50 | | | | -|B6 |MPI_Node_Out<1>_ram_address_wr<10> |IOB |IO |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|B7 |MPI_Node_Out<1>_ram_address_wr<6> |IOB |IO_L13P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|B8 |MPI_Node_in<1>_clk |IBUF |IP_L10N_0/GCLK9 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE | -|B9 | | |GND | | | | | | | | | | | | -|B10 |MPI_Node_Out<2>_ram_address_rd<9> |IOB |IO |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|B11 |MPI_Node_Out<2>_ram_address_rd<5> |IOB |IO_L05N_0/VREF_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|B12 | | |VCCO_0 | | |0 | | | | |2.50 | | | | -|B13 | |DIFFM |IO_L03P_0 |UNUSED | |0 | | | | | | | | | -|B14 | |DIFFM |IO_L01P_0 |UNUSED | |0 | | | | | | | | | -|B15 | | |TMS | | | | | | | | | | | | -|B16 | |IBUF |IP |UNUSED | |1 | | | | | | | | | -|C1 |MPI_Node_Out<1>_ram_data_in<6> |IOB |IO_L02P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|C2 |MPI_Node_Out<1>_ram_data_in<7> |IOB |IO_L02N_3/VREF_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|C3 |MPI_Node_Out<1>_ram_data_in<2> |IOB |IO_L19P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|C4 |MPI_Node_Out<1>_ram_data_in<1> |IOB |IO_L18N_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|C5 |MPI_Node_Out<2>_ram_address_wr<5> |IOB |IO_L18P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|C6 |MPI_Node_Out<1>_ram_address_wr<11> |IOB |IO_L15P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|C7 |MPI_Node_Out<1>_ram_address_wr<7> |IOB |IO_L13N_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|C8 |MPI_Node_Out<1>_ram_address_wr<1> |IOB |IO_L11P_0/GCLK10 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|C9 | |DIFFSI |IP_L07N_0 |UNUSED | |0 | | | | | | | | | -|C10 | |DIFFMI |IP_L07P_0 |UNUSED | |0 | | | | | | | | | -|C11 |MPI_Node_Out<2>_ram_address_rd<7> |IOB |IO_L05P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|C12 | |DIFFSI |IP_L02N_0 |UNUSED | |0 | | | | | | | | | -|C13 | |IBUF |IP |UNUSED | |0 | | | | | | | | | -|C14 | | |TDO | | | | | | | | | | | | -|C15 | |DIFFS |IO_L19N_1/LDC2 |UNUSED | |1 | | | | | | | | | -|C16 | |DIFFM |IO_L19P_1/LDC1 |UNUSED | |1 | | | | | | | | | -|D1 |MPI_Node_Out<2>_ram_address_wr<7> |IOB |IO_L05P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|D2 |MPI_Node_in<2>_ram_data_out<0> |IBUF |IP |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE | -|D3 | | |PROG_B | | | | | | | | | | | | -|D4 | | |VCCINT | | | | | | | |1.2 | | | | -|D5 | |DIFFMI |IP_L16P_0 |UNUSED | |0 | | | | | | | | | -|D6 |MPI_Node_Out<1>_ram_address_wr<12> |IOB |IO_L15N_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|D7 |MPI_Node_Out<1>_ram_address_wr<9> |IOB |IO_L14N_0/VREF_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|D8 |MPI_Node_Out<1>_ram_address_wr<2> |IOB |IO_L11N_0/GCLK11 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|D9 |MPI_Node_Out<2>_ram_address_rd<14> |IOB |IO/VREF_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|D10 |MPI_Node_Out<2>_ram_address_rd<10> |IOB |IO_L06P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|D11 |MPI_Node_Out<2>_ram_address_rd<2> |IOB |IO_L04P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|D12 | |DIFFMI |IP_L02P_0 |UNUSED | |0 | | | | | | | | | -|D13 | | |VCCINT | | | | | | | |1.2 | | | | -|D14 | |DIFFS |IO_L18N_1/LDC0 |UNUSED | |1 | | | | | | | | | -|D15 | |DIFFM |IO_L18P_1/HDC |UNUSED | |1 | | | | | | | | | -|D16 | |IBUF |IP/VREF_1 |UNUSED | |1 | | | | | | | | | -|E1 |MPI_Node_in<2>_ram_data_out<5> |IBUF |IO_L05N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE | -|E2 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|E3 |MPI_Node_Out<2>_ram_address_wr<0> |IOB |IO_L03P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|E4 |MPI_Node_Out<2>_ram_address_wr<1> |IOB |IO_L03N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|E5 | | |VCCINT | | | | | | | |1.2 | | | | -|E6 | |DIFFSI |IP_L16N_0 |UNUSED | |0 | | | | | | | | | -|E7 |MPI_Node_Out<1>_ram_address_wr<8> |IOB |IO_L14P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|E8 |MPI_Node_Out<1>_ram_address_wr<4> |IOB |IO_L12P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|E9 |MPI_Node_Out<2>_ram_address_rd<12> |IOB |IO_L08P_0/GCLK4 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|E10 |MPI_Node_Out<2>_ram_address_rd<11> |IOB |IO_L06N_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|E11 |MPI_Node_Out<2>_ram_address_rd<6> |IOB |IO_L04N_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|E12 | | |VCCINT | | | | | | | |1.2 | | | | -|E13 |MPI_Node_Out<2>_ram_address_rd<8> |IOB |IO_L17P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|E14 | |IBUF |IP |UNUSED | |1 | | | | | | | | | -|E15 | | |VCCO_1 | | |1 | | | | |2.50 | | | | -|E16 |MPI_Node_Out<2>_ram_address_rd<0> |IOB |IO_L17N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|F1 | | |VCCAUX | | | | | | | |2.5 | | | | -|F2 |MPI_Node_in<2>_ram_data_out<2> |IBUF |IP |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE | -|F3 |MPI_Node_Out<2>_ram_address_wr<2> |IOB |IO_L04P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|F4 |MPI_Node_Out<2>_ram_address_wr<3> |IOB |IO_L04N_3/VREF_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|F5 |MPI_Node_in<2>_ram_data_out<1> |IBUF |IP |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE | -|F6 | | |GND | | | | | | | | | | | | -|F7 | | |VCCO_0 | | |0 | | | | |2.50 | | | | -|F8 |MPI_Node_Out<1>_ram_address_wr<5> |IOB |IO_L12N_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|F9 |MPI_Node_Out<2>_ram_address_rd<13> |IOB |IO_L08N_0/GCLK5 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|F10 | | |VCCO_0 | | |0 | | | | |2.50 | | | | -|F11 | | |GND | | | | | | | | | | | | -|F12 |MPI_Node_Out<2>_ram_address_rd<1> |IOB |IO_L16N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|F13 | |DIFFM |IO_L16P_1 |UNUSED | |1 | | | | | | | | | -|F14 |MPI_Node_Out<2>_ram_address_rd<3> |IOB |IO_L15P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|F15 | |DIFFS |IO_L15N_1 |UNUSED | |1 | | | | | | | | | -|F16 | | |VCCAUX | | | | | | | |2.5 | | | | -|G1 |MPI_Node_in<2>_ram_data_out<3> |IBUF |IP/VREF_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE | -|G2 |MPI_Node_Out<2>_ram_address_wr<9> |IOB |IO_L07N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|G3 |MPI_Node_Out<1>_ram_data_in<0> |IOB |IO_L07P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|G4 |MPI_Node_Out<2>_ram_address_wr<8> |IOB |IO_L06N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|G5 |MPI_Node_Out<2>_ram_address_wr<6> |IOB |IO_L06P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|G6 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|G7 | | |GND | | | | | | | | | | | | -|G8 | | |GND | | | | | | | | | | | | -|G9 | | |GND | | | | | | | | | | | | -|G10 | | |GND | | | | | | | | | | | | -|G11 | | |VCCO_1 | | |1 | | | | |2.50 | | | | -|G12 | |IBUF |IP |UNUSED | |1 | | | | | | | | | -|G13 |MPI_Node_Out<2>_hold_req |IOB |IO_L14P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|G14 | |DIFFS |IO_L14N_1/A0 |UNUSED | |1 | | | | | | | | | -|G15 |MPI_Node_Out<2>_ram_en |IOB |IO_L13P_1/A2 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|G16 | |DIFFS |IO_L13N_1/A1 |UNUSED | |1 | | | | | | | | | -|H1 |MPI_Node_in<2>_ram_data_out<4> |IBUF |IP |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE | -|H2 | | |GND | | | | | | | | | | | | -|H3 |MPI_Node_Out<2>_ram_address_wr<12> |IOB |IO_L09P_3/LHCLK2 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|H4 |MPI_Node_Out<2>_ram_address_wr<13> |IOB |IO_L09N_3/LHCLK3/IRDY2 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|H5 |MPI_Node_Out<2>_ram_address_wr<10> |IOB |IO_L08P_3/LHCLK0 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|H6 |MPI_Node_Out<2>_ram_address_wr<11> |IOB |IO_L08N_3/LHCLK1 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|H7 | | |GND | | | | | | | | | | | | -|H8 | | |GND | | | | | | | | | | | | -|H9 | | |GND | | | | | | | | | | | | -|H10 | | |GND | | | | | | | | | | | | -|H11 | |DIFFS |IO_L12N_1/A3/RHCLK7 |UNUSED | |1 | | | | | | | | | -|H12 | |DIFFM |IO_L12P_1/A4/RHCLK6 |UNUSED | |1 | | | | | | | | | -|H13 | |IBUF |IP/VREF_1 |UNUSED | |1 | | | | | | | | | -|H14 |MPI_Node_in<2>_instruction<6> |IBUF |IO_L11N_1/A5/RHCLK5 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|H15 |MPI_Node_in<2>_instruction<7> |IBUF |IO_L11P_1/A6/RHCLK4/IRDY1|INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|H16 |MPI_Node_in<2>_instruction<3> |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|J1 |MPI_Node_Out<2>_ram_data_in<0> |IOB |IO_L12P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|J2 |MPI_Node_Out<2>_ram_address_wr<14> |IOB |IO_L10P_3/LHCLK4/TRDY2 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|J3 |MPI_Node_Out<2>_ram_address_wr<15> |IOB |IO_L10N_3/LHCLK5 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|J4 |MPI_Node_Out<1>_ram_data_in<4> |IOB |IO_L11N_3/LHCLK7 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|J5 |MPI_Node_Out<2>_ram_address_wr<4> |IOB |IO_L11P_3/LHCLK6 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|J6 |MPI_Node_in<2>_ram_data_out<7> |IBUF |IP |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE | -|J7 | | |GND | | | | | | | | | | | | -|J8 | | |GND | | | | | | | | | | | | -|J9 | | |GND | | | | | | | | | | | | -|J10 | | |GND | | | | | | | | | | | | -|J11 | |IBUF |IP |UNUSED | |1 | | | | | | | | | -|J12 |MPI_Node_in<2>_instruction<4> |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|J13 |MPI_Node_in<2>_instruction<2> |IBUF |IO_L10N_1/A7/RHCLK3/TRDY1|INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|J14 |MPI_Node_in<2>_instruction<0> |IBUF |IO_L10P_1/A8/RHCLK2 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|J15 | | |GND | | | | | | | | | | | | -|J16 | |DIFFS |IO_L09N_1/A9/RHCLK1 |UNUSED | |1 | | | | | | | | | -|K1 |MPI_Node_Out<2>_ram_data_in<1> |IOB |IO_L12N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|K2 |MPI_Node_Out<2>_ram_data_in<2> |IOB |IO_L13P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|K3 |MPI_Node_Out<2>_ram_data_in<3> |IOB |IO_L13N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|K4 | |IBUF |IP |UNUSED | |3 | | | | | | | | | -|K5 |MPI_Node_Out<2>_ram_data_in<6> |IOB |IO_L15P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|K6 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|K7 | | |GND | | | | | | | | | | | | -|K8 | | |GND | | | | | | | | | | | | -|K9 | | |GND | | | | | | | | | | | | -|K10 | | |GND | | | | | | | | | | | | -|K11 | | |VCCO_1 | | |1 | | | | |2.50 | | | | -|K12 | |DIFFS |IO_L07N_1/A11 |UNUSED | |1 | | | | | | | | | -|K13 |MPI_Node_in<2>_instruction<1> |IBUF |IO_L07P_1/A12 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|K14 | |DIFFS |IO_L08N_1/VREF_1 |UNUSED | |1 | | | | | | | | | -|K15 | |DIFFM |IO_L08P_1 |UNUSED | |1 | | | | | | | | | -|K16 |MPI_Node_in<2>_instruction<5> |IBUF |IO_L09P_1/A10/RHCLK0 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|L1 | | |VCCAUX | | | | | | | |2.5 | | | | -|L2 |MPI_Node_Out<2>_ram_data_in<5> |IOB |IO_L14N_3/VREF_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|L3 |MPI_Node_Out<2>_ram_data_in<4> |IOB |IO_L14P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|L4 |MPI_Node_Out<2>_PushOut<5> |IOB |IO_L17N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|L5 |MPI_Node_Out<2>_ram_data_in<7> |IOB |IO_L15N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|L6 | | |GND | | | | | | | | | | | | -|L7 | | |VCCO_2 | | |2 | | | | |2.50 | | | | -|L8 |MPI_Node_Out<1>_ram_address_rd<9> |IOB |IO_L09N_2/D6/GCLK13 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|L9 |MPI_Node_Out<1>_ram_address_rd<11> |IOB |IO_L13P_2/M0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|L10 | | |VCCO_2 | | |2 | | | | |2.50 | | | | -|L11 | | |GND | | | | | | | | | | | | -|L12 | |DIFFM |IO_L05P_1 |UNUSED | |1 | | | | | | | | | -|L13 |MPI_Node_Out<1>_instruction_fifo_full|IOB |IO_L05N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|L14 | |DIFFM |IO_L06P_1 |UNUSED | |1 | | | | | | | | | -|L15 | |DIFFS |IO_L06N_1 |UNUSED | |1 | | | | | | | | | -|L16 | | |VCCAUX | | | | | | | |2.5 | | | | -|M1 |MPI_Node_Out<2>_PushOut<0> |IOB |IO_L16P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|M2 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|M3 | |IBUF |IP |UNUSED | |3 | | | | | | | | | -|M4 |MPI_Node_Out<2>_PushOut<4> |IOB |IO_L17P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|M5 | | |VCCINT | | | | | | | |1.2 | | | | -|M6 |MPI_Node_Out<1>_ram_address_rd<5> |IOB |IO_L05P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|M7 |MPI_Node_Out<1>_ram_address_rd<6> |IOB |IO |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|M8 |MPI_Node_Out<1>_ram_address_rd<3> |IOB |IO_L09P_2/D7/GCLK12 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|M9 |MPI_Node_Out<1>_hold_req |IOB |IO_L13N_2/DIN/D0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|M10 |MPI_Node_Out<1>_PushOut<0> |IOB |IO_L15N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|M11 |MPI_Node_in<2>_instruction_en |IBUF |IP_L17N_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|M12 | | |VCCINT | | | | | | | |1.2 | | | | -|M13 |MPI_Node_in<1>_instruction<3> |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|M14 |MPI_Node_in<1>_instruction<6> |IBUF |IP |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|M15 | | |VCCO_1 | | |1 | | | | |2.50 | | | | -|M16 |MPI_Node_Out<1>_ram_en |IOB |IO_L04N_1/VREF_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|N1 |MPI_Node_Out<2>_PushOut<1> |IOB |IO_L16N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|N2 | |IBUF |IP/VREF_3 |UNUSED | |3 | | | | | | | | | -|N3 | |IBUF |IP |UNUSED | |3 | | | | | | | | | -|N4 | | |VCCINT | | | | | | | |1.2 | | | | -|N5 |MPI_Node_Out<1>_PushOut<2> |IOB |IO_L03N_2/MOSI/CSI_B |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|N6 |MPI_Node_Out<1>_ram_address_rd<2> |IOB |IO_L05N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|N7 |MPI_Node_Out<1>_ram_address_rd<0> |IOB |IO_L07P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|N8 |MPI_Node_Out<1>_ram_address_rd<13> |IOB |IO_L10P_2/D4/GCLK14 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|N9 |MPI_Node_Out<1>_ram_address_rd<10> |IOB |IO_L12N_2/D1/GCLK3 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|N10 |MPI_Node_in<1>_hold_ack |IBUF |IO_L15P_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|N11 |MPI_Node_in<1>_instruction<5> |IBUF |IP_L17P_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|N12 |MPI_Node_in<1>_instruction<2> |IBUF |IO_L18N_2/A20 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|N13 | | |VCCINT | | | | | | | |1.2 | | | | -|N14 |MPI_Node_in<1>_instruction<4> |IBUF |IO_L03P_1 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|N15 |MPI_Node_in<1>_instruction<1> |IBUF |IO_L03N_1/VREF_1 |INPUT |LVCMOS25* |1 | | | |NONE | |UNLOCATED |NO |NONE | -|N16 |MPI_Node_Out<2>_instruction_fifo_full|IOB |IO_L04P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P1 |MPI_Node_Out<2>_PushOut<3> |IOB |IO_L18N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P2 |MPI_Node_Out<1>_PushOut<1> |IOB |IO_L18P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P3 |MPI_Node_Out<1>_PushOut<4> |IOB |IO_L01P_2/CSO_B |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P4 |MPI_Node_Out<2>_PushOut<2> |IOB |IO_L01N_2/INIT_B |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P5 |MPI_Node_Out<1>_PushOut<3> |IOB |IO_L03P_2/DOUT/BUSY |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P6 |MPI_Node_Out<2>_ram_we |IOB |IO_L06N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P7 |MPI_Node_Out<1>_ram_address_rd<8> |IOB |IO_L07N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P8 |MPI_Node_Out<1>_ram_we |IOB |IO_L10N_2/D3/GCLK15 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P9 |MPI_Node_Out<1>_ram_address_rd<12> |IOB |IO_L12P_2/D2/GCLK2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P10 |MPI_Node_Out<1>_ram_address_rd<15> |IOB |IO_L14P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P11 |MPI_Node_in<1>_instruction_en |IBUF |IO_L16N_2/A22 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|P12 |MPI_Node_in<1>_instruction<0> |IBUF |IO_L18P_2/A21 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|P13 | |IOB |IO/VREF_2 |UNUSED | |2 | | | | | | | | | -|P14 |MPI_Node_Out<1>_PushOut<6> |IOB |IO_L20P_2/VS0/A17 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|P15 | |DIFFS |IO_L02N_1/A13 |UNUSED | |1 | | | | | | | | | -|P16 |MPI_Node_Out<1>_barrier_completed |IOB |IO_L02P_1/A14 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|R1 |MPI_Node_Out<2>_PushOut<7> |IOB |IO_L19N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|R2 |MPI_Node_Out<2>_PushOut<6> |IOB |IO_L19P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|R3 |MPI_Node_in<1>_ram_data_out<2> |IBUF |IP_L02N_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|R4 |MPI_Node_Out<1>_ram_address_rd<4> |IOB |IO/VREF_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|R5 | | |VCCO_2 | | |2 | | | | |2.50 | | | | -|R6 |MPI_Node_Out<1>_ram_address_rd<7> |IOB |IO_L06P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|R7 |MPI_Node_in<1>_ram_data_out<3> |IBUF |IP_L08P_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|R8 | | |GND | | | | | | | | | | | | -|R9 |MPI_Node_in<1>_ram_data_out<6> |IBUF |IP_L11N_2/M2/GCLK1 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|R10 |MPI_Node_in<1>_ram_data_out<7> |IBUF |IO_L14N_2/VREF_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|R11 |MPI_Node_in<2>_hold_ack |IBUF |IO_L16P_2/A23 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|R12 | | |VCCO_2 | | |2 | | | | |2.50 | | | | -|R13 |MPI_Node_Out<1>_PushOut<7> |IOB |IO_L19N_2/VS1/A18 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|R14 | |DIFFS |IO_L20N_2/CCLK |UNUSED | |2 | | | | | | | | | -|R15 |MPI_Node_Out<2>_barrier_completed |IOB |IO_L01N_1/A15 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|R16 |MPI_Node_Out<2>_packet_received |IOB |IO_L01P_1/A16 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|T1 | | |GND | | | | | | | | | | | | -|T2 |MPI_Node_in<1>_ram_data_out<0> |IBUF |IP |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|T3 |MPI_Node_in<1>_ram_data_out<1> |IBUF |IP_L02P_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|T4 |MPI_Node_Out<1>_packet_received |IOB |IO_L04P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|T5 |MPI_Node_Out<1>_ram_address_rd<1> |IOB |IO_L04N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|T6 | | |VCCAUX | | | | | | | |2.5 | | | | -|T7 |MPI_Node_in<1>_ram_data_out<4> |IBUF |IP_L08N_2/VREF_2 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|T8 |MPI_Node_Out<1>_PushOut<5> |IOB |IO/D5 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|T9 |MPI_Node_in<1>_ram_data_out<5> |IBUF |IP_L11P_2/RDWR_B/GCLK0 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|T10 |MPI_Node_Out<1>_ram_address_rd<14> |IOB |IO/M1 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|T11 | | |VCCAUX | | | | | | | |2.5 | | | | -|T12 | |IOB |IO |UNUSED | |2 | | | | | | | | | -|T13 |MPI_Node_in<1>_instruction<7> |IBUF |IO_L19P_2/VS2/A19 |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|T14 |MPI_Node_in<1>_reset |IBUF |IP |INPUT |LVCMOS25* |2 | | | |NONE | |UNLOCATED |NO |NONE | -|T15 | | |DONE | | | | | | | | | | | | -|T16 | | |GND | | | | | | | | | | | | -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -* Default value. -** This default Pullup/Pulldown value can be overridden in Bitgen. -****** Special VCCO requirements may apply. Please consult the device - family datasheet for specific guideline on VCCO requirements. - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_preroute.twr =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_preroute.twr (revision 17) +++ (revision ) @@ -1,173 +1,0 @@ --------------------------------------------------------------------------------- -Release 12.3 Trace (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 5 --n 3 -fastpaths -xml MPI_NOC_preroute.twx MPI_NOC_map.ncd -o -MPI_NOC_preroute.twr MPI_NOC.pcf -ucf MPI_NOC.ucf - -Design file: MPI_NOC_map.ncd -Physical constraint file: MPI_NOC.pcf -Device,package,speed: xc3s1200e,ft256,-5 (PRODUCTION 1.27 2010-09-15) -Report level: verbose report - -Environment Variable Effect --------------------- ------ -NONE No environment variables were set --------------------------------------------------------------------------------- - -INFO:Timing:2698 - No timing constraints found, doing default enumeration. -INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths - option. All paths that are not constrained will be reported in the - unconstrained paths section(s) of the report. -INFO:Timing:3284 - This timing report was generated using estimated delay - information. For accurate numbers, please refer to the post Place and Route - timing report. -INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on - a 50 Ohm transmission line loading model. For the details of this model, - and for more information on accounting for different loading conditions, - please see the device datasheet. -INFO:Timing:3390 - This architecture does not support a default System Jitter - value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock - Uncertainty calculation. -INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and - 'Phase Error' calculations, these terms will be zero in the Clock - Uncertainty calculation. Please make appropriate modification to - SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase - Error. - - - -Data Sheet report: ------------------ -All values displayed in nanoseconds (ns) - -Setup/Hold to clock MPI_Node_in<1>_clk -------------------------------+------------+------------+------------------------+--------+ - |Max Setup to|Max Hold to | | Clock | -Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | -------------------------------+------------+------------+------------------------+--------+ -MPI_Node_in<1>_hold_ack | 1.337(R)| 1.112(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_instruction_en | 0.903(R)| 1.122(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<0>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<1>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<2>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<3>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<4>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<5>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<6>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_ram_data_out<7>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<1>_reset | 0.466(R)| 1.712(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_hold_ack | 1.337(R)| 1.112(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_instruction_en | 0.903(R)| 1.122(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<0>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<1>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<2>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<3>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<4>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<5>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<6>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_in<2>_ram_data_out<7>| 1.323(R)| 1.335(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -------------------------------+------------+------------+------------------------+--------+ - -Clock MPI_Node_in<1>_clk to Pad --------------------------------------+------------+------------------------+--------+ - | clk (edge) | | Clock | -Destination | to PAD |Internal Clock(s) | Phase | --------------------------------------+------------+------------------------+--------+ -MPI_Node_Out<1>_PushOut<0> | 6.286(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_hold_req | 6.998(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_instruction_fifo_full| 7.713(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<0> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<1> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<2> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<3> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<4> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<5> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<6> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<7> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<8> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<9> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<10> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<11> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<12> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<13> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<14> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_rd<15> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<0> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<1> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<2> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<3> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<4> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<5> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<6> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<7> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<8> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<9> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<10> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<11> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<12> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<13> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<14> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_address_wr<15> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_en | 9.415(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<1>_ram_we | 8.425(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_PushOut<0> | 6.286(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_hold_req | 6.998(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_instruction_fifo_full| 7.713(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<0> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<1> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<2> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<3> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<4> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<5> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<6> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<7> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<8> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<9> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<10> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<11> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<12> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<13> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<14> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_rd<15> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<0> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<1> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<2> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<3> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<4> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<5> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<6> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<7> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<8> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<9> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<10> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<11> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<12> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<13> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<14> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_address_wr<15> | 7.991(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_en | 9.415(R)|MPI_Node_in_1__clk_BUFGP| 0.000| -MPI_Node_Out<2>_ram_we | 8.425(R)|MPI_Node_in_1__clk_BUFGP| 0.000| --------------------------------------+------------+------------------------+--------+ - -Clock to Setup on destination clock MPI_Node_in<1>_clk -------------------+---------+---------+---------+---------+ - | Src:Rise| Src:Fall| Src:Rise| Src:Fall| -Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| -------------------+---------+---------+---------+---------+ -MPI_Node_in<1>_clk| 8.699| | | | -------------------+---------+---------+---------+---------+ - - -Analysis completed Fri Aug 03 10:19:46 2012 --------------------------------------------------------------------------------- - -Trace Settings: -------------------------- -Trace Settings - -Peak Memory Usage: 238 MB - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_preroute.twx =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_preroute.twx (revision 17) +++ (revision ) @@ -1,339 +1,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -]> -Release 12.3 Trace (nt64)Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 5 --n 3 -fastpaths -xml MPI_NOC_preroute.twx MPI_NOC_map.ncd -o -MPI_NOC_preroute.twr MPI_NOC.pcf -ucf MPI_NOC.ucf - -MPI_NOC_map.ncdMPI_NOC_map.ncdMPI_NOC.pcfMPI_NOC.pcfxc3s1200e-5PRODUCTION 1.27 2010-09-153INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3284 - This timing report was generated using estimated delay information. For accurate numbers, please refer to the post Place and Route timing report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.MPI_Node_in<1>_clkMPI_Node_in<1>_hold_ack1.3371.112MPI_Node_in<1>_instruction_en0.9031.122MPI_Node_in<1>_ram_data_out<0>1.3231.335MPI_Node_in<1>_ram_data_out<1>1.3231.335MPI_Node_in<1>_ram_data_out<2>1.3231.335MPI_Node_in<1>_ram_data_out<3>1.3231.335MPI_Node_in<1>_ram_data_out<4>1.3231.335MPI_Node_in<1>_ram_data_out<5>1.3231.335MPI_Node_in<1>_ram_data_out<6>1.3231.335MPI_Node_in<1>_ram_data_out<7>1.3231.335MPI_Node_in<1>_reset0.4661.712MPI_Node_in<2>_hold_ack1.3371.112MPI_Node_in<2>_instruction_en0.9031.122MPI_Node_in<2>_ram_data_out<0>1.3231.335MPI_Node_in<2>_ram_data_out<1>1.3231.335MPI_Node_in<2>_ram_data_out<2>1.3231.335MPI_Node_in<2>_ram_data_out<3>1.3231.335MPI_Node_in<2>_ram_data_out<4>1.3231.335MPI_Node_in<2>_ram_data_out<5>1.3231.335MPI_Node_in<2>_ram_data_out<6>1.3231.335MPI_Node_in<2>_ram_data_out<7>1.3231.335MPI_Node_in<1>_clkMPI_Node_in<1>_clkMPI_Node_in<1>_clk8.699Fri Aug 03 10:19:46 2012 TraceTrace Settings - -Peak Memory Usage: 238 MB - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_summary.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_summary.html (revision 17) +++ (revision ) @@ -1,198 +1,0 @@ -Xilinx Design Summary - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MPICORETEST Project Status (08/03/2012 - 19:01:09)
Project File:MPI_CORE_COMPONENTS.xiseParser Errors: No Errors
Module Name:MPI_NOCImplementation State:Synthesized (Stopped)
Target Device:xc6slx100t-3fgg484
  • Errors:
 
Product Version:ISE 12.3
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 - 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: - -System Settings -
  • Final Timing Score:
 
- - - - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers1,42017,3448% 
    Number used as Flip Flops883   
    Number used as Latches537   
Number of 4 input LUTs2,98617,34417% 
Number of occupied Slices1,8328,67221% 
    Number of Slices containing only related logic1,8321,832100% 
    Number of Slices containing unrelated logic01,8320% 
Total Number of 4 input LUTs3,18817,34418% 
    Number used as logic2,826   
    Number used as a route-thru202   
    Number used for Dual Port RAMs160   
Number of bonded IOBs14619076% 
Number of RAMB16s42814% 
Number of BUFGMUXs52420% 
Average Fanout of Non-Clock Nets3.61   
- - - - 
- - - - - - - - - - - - - - - - - -
Performance Summary [-]
Final Timing Score:0 (Setup: 0, Hold: 0)Pinout Data:Pinout Report
Routing Results: -All Signals Completely RoutedClock Data:Clock Report
Timing Constraints: -All Constraints Met  
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Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentFri 3. Aug 10:15:28 2012   
Translation ReportCurrentFri 3. Aug 10:15:38 2012   
Map ReportCurrentFri 3. Aug 10:15:57 2012   
Place and Route ReportCurrentFri 3. Aug 10:17:02 2012   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentFri 3. Aug 10:17:12 2012   
Bitgen Report     
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- - -
Secondary Reports [-]
Report NameStatusGenerated
- - -
Date Generated: 08/03/2012 - 19:02:25
- Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_vhdl.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MPI_NOC_vhdl.prj (revision 17) +++ (revision ) @@ -1,42 +1,0 @@ -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\CoreTypes.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\RAM_256.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\Arbiter.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER9_9.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER8_8.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER7_7.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER6_6.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER5_5.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER4_4.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER3_3.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER2_2.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER16_16.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER15_15.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER14_14.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER13_13.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER12_12.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER11_11.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER10_10.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\FIFO_256_FWFT.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\Crossbit.vhd" -vhdl work "C:\Core MPI\CORE_MPI\round_robbin_machine.vhd" -vhdl work "C:\Core MPI\CORE_MPI\RAM_64.vhd" -vhdl work "C:\Core MPI\CORE_MPI\Packet_type.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MUX8.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MUX1.vhd" -vhdl work "C:\Core MPI\CORE_MPI\DEMUX1.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\Scheduler.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\OUTPUT_PORT_MODULE.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\INPUT_PORT_MODULE.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\Crossbar.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MPI_CORE_SCHEDULER.vhd" -vhdl work "C:\Core MPI\CORE_MPI\load_instr.vhd" -vhdl work "C:\Core MPI\CORE_MPI\FIFO_64_FWFT.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX4_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX3_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX2_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX1_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\Ex0_Fsm.vhd" -vhdl work "C:\Core MPI\CORE_MPI\DMA_ARBITER.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SWITCH_GEN.vhd" -vhdl work "C:\Core MPI\CORE_MPI\CORE_MPI.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MPI_NOC.vhd" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.bld =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.bld (revision 17) +++ (revision ) @@ -1,61 +1,0 @@ -Release 12.3 ngdbuild M.70d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -Command Line: d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe --intstyle ise -dd _ngo -nt timestamp -i -p xc6slx100-fgg484-3 MultiMPITest.ngc -MultiMPITest.ngd - -Reading NGO file "C:/Core MPI/CORE_MPI/MultiMPITest.ngc" ... -Gathering constraint information from source properties... -Done. - -Resolving constraint associations... -Checking Constraint Associations... -Done... - -Checking expanded design ... -WARNING:NgdBuild:452 - logical net 'MPI_Node_Out[2]_PushOut<7>' has no driver -WARNING:NgdBuild:452 - logical net 'MPI_Node_Out[2]_PushOut<6>' has no driver -WARNING:NgdBuild:452 - logical net 'MPI_Node_Out[2]_PushOut<5>' has no driver -WARNING:NgdBuild:452 - logical net 'MPI_Node_Out[2]_PushOut<3>' has no driver -WARNING:NgdBuild:452 - logical net 'MPI_Node_Out[2]_PushOut<2>' has no driver -WARNING:NgdBuild:452 - logical net 'MPI_Node_Out[2]_PushOut<1>' has no driver -WARNING:NgdBuild:452 - logical net 'uut/connect_core[2].hardmpi/packet_ack' has - no driver -WARNING:NgdBuild:452 - logical net 'uut/connect_core[2].hardmpi/MyRank<3>' has - no driver -WARNING:NgdBuild:452 - logical net 'uut/connect_core[2].hardmpi/MyRank<2>' has - no driver -WARNING:NgdBuild:452 - logical net 'uut/connect_core[2].hardmpi/MyRank<1>' has - no driver -WARNING:NgdBuild:452 - logical net 'uut/connect_core[2].hardmpi/MyRank<0>' has - no driver -WARNING:NgdBuild:452 - logical net 'uut/connect_core[1].hardmpi/packet_ack' has - no driver -WARNING:NgdBuild:452 - logical net 'uut/connect_core[1].hardmpi/MyRank<3>' has - no driver -WARNING:NgdBuild:452 - logical net 'uut/connect_core[1].hardmpi/MyRank<2>' has - no driver -WARNING:NgdBuild:452 - logical net 'uut/connect_core[1].hardmpi/MyRank<1>' has - no driver -WARNING:NgdBuild:452 - logical net 'uut/connect_core[1].hardmpi/MyRank<0>' has - no driver - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -NGDBUILD Design Results Summary: - Number of errors: 0 - Number of warnings: 16 - -Total memory usage is 166880 kilobytes - -Writing NGD file "MultiMPITest.ngd" ... -Total REAL time to NGDBUILD completion: 5 sec -Total CPU time to NGDBUILD completion: 4 sec - -Writing NGDBUILD log file "MultiMPITest.bld"... Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.cmd_log =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.cmd_log (revision 17) +++ (revision ) @@ -1,39 +1,0 @@ -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx100t-fgg484-3 "MultiMPITest.ngc" MultiMPITest.ngd -map -intstyle ise -p xc6slx100t-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o MultiMPITest_map.ncd MultiMPITest.ngd MultiMPITest.pcf -par -w -intstyle ise -ol high -mt off MultiMPITest_map.ncd MultiMPITest.ncd MultiMPITest.pcf -trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MultiMPITest.twx MultiMPITest.ncd -o MultiMPITest.twr MultiMPITest.pcf -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx4-tqg144-3 "MultiMPITest.ngc" MultiMPITest.ngd -map -intstyle ise -p xc6slx4-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o MultiMPITest_map.ncd MultiMPITest.ngd MultiMPITest.pcf -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-tqg144-3 "MultiMPITest.ngc" MultiMPITest.ngd -map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o MultiMPITest_map.ncd MultiMPITest.ngd MultiMPITest.pcf -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx100-fgg484-3 "MultiMPITest.ngc" MultiMPITest.ngd -map -intstyle ise -p xc6slx100-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o MultiMPITest_map.ncd MultiMPITest.ngd MultiMPITest.pcf -par -w -intstyle ise -ol high -mt off MultiMPITest_map.ncd MultiMPITest.ncd MultiMPITest.pcf -trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MultiMPITest.twx MultiMPITest.ncd -o MultiMPITest.twr MultiMPITest.pcf -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx100-fgg484-3 "MultiMPITest.ngc" MultiMPITest.ngd -map -intstyle ise -p xc6slx100-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o MultiMPITest_map.ncd MultiMPITest.ngd MultiMPITest.pcf -par -w -intstyle ise -ol high -mt off MultiMPITest_map.ncd MultiMPITest.ncd MultiMPITest.pcf -trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml MultiMPITest.twx MultiMPITest.ncd -o MultiMPITest.twr MultiMPITest.pcf -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/MultiMPITest.xst" -ofn "C:/Core MPI/CORE_MPI/MultiMPITest.syr" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.lso =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.lso (revision 17) +++ (revision ) @@ -1,1 +1,0 @@ -work Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.pcf =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.pcf (revision 17) +++ (revision ) @@ -1,4 +1,0 @@ -//! ************************************************************************** -// Written by: Map M.70d on Tue Aug 14 16:11:04 2012 -//! ************************************************************************** - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.prj (revision 17) +++ (revision ) @@ -1,45 +1,0 @@ -vhdl NocLib "../SWITCH_GENERIC_16_16/CoreTypes.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/RAM_256.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Arbiter.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Crossbit.vhd" -vhdl work "round_robbin_machine.vhd" -vhdl work "RAM_64.vhd" -vhdl work "Packet_type.vhd" -vhdl work "MUX8.vhd" -vhdl work "DEMUX1.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Scheduler.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Crossbar.vhd" -vhdl work "MPI_CORE_SCHEDULER.vhd" -vhdl work "load_instr.vhd" -vhdl work "FIFO_64_FWFT.vhd" -vhdl work "EX4_FSM.vhd" -vhdl work "EX3_FSM.vhd" -vhdl work "EX2_FSM.vhd" -vhdl work "EX1_FSM.vhd" -vhdl work "Ex0_Fsm.vhd" -vhdl work "DMA_ARBITER.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" -vhdl work "RAM_32_32.vhd" -vhdl work "MPI_RMA.vhd" -vhdl work "CORE_MPI.vhd" -vhdl work "PE.vhd" -vhdl work "MPI_NOC.vhd" -vhdl work "MultiMPITest.vhd" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.ptwx =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.ptwx (revision 17) +++ (revision ) @@ -1,332 +1,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -]> -Autotimespec constraint for clock net clkm_BUFGPAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd1_BUFGAutotimespec constraint for clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd1_BUFGAutotimespec constraint for clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_oAutotimespec constraint for clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_oAutotimespec constraint for clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o4INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.twr =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.twr (revision 17) +++ (revision ) @@ -1,72 +1,0 @@ --------------------------------------------------------------------------------- -Release 12.3 Trace (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3 --n 3 -fastpaths -xml MultiMPITest.twx MultiMPITest.ncd -o MultiMPITest.twr -MultiMPITest.pcf - -Design file: MultiMPITest.ncd -Physical constraint file: MultiMPITest.pcf -Device,package,speed: xc6slx100,fgg484,C,-3 (PRODUCTION 1.12c 2010-09-15) -Report level: verbose report - -Environment Variable Effect --------------------- ------ -NONE No environment variables were set --------------------------------------------------------------------------------- - -INFO:Timing:2698 - No timing constraints found, doing default enumeration. -INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths - option. All paths that are not constrained will be reported in the - unconstrained paths section(s) of the report. -INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on - a 50 Ohm transmission line loading model. For the details of this model, - and for more information on accounting for different loading conditions, - please see the device datasheet. - - - -Data Sheet report: ------------------ -All values displayed in nanoseconds (ns) - -Setup/Hold to clock clkm -------------+------------+------------+------------+------------+------------------+--------+ - |Max Setup to| Process |Max Hold to | Process | | Clock | -Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | -------------+------------+------------+------------+------------+------------------+--------+ -reset | 16.672(R)| SLOW | 0.529(R)| SLOW |clkm_BUFGP | 0.000| -------------+------------+------------+------------+------------+------------------+--------+ - -Clock clkm to Pad -------------+-----------------+------------+-----------------+------------+------------------+--------+ - |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock | -Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase | -------------+-----------------+------------+-----------------+------------+------------------+--------+ -result<0> | 8.688(R)| SLOW | 4.230(R)| FAST |clkm_BUFGP | 0.000| -result<1> | 9.023(R)| SLOW | 4.224(R)| FAST |clkm_BUFGP | 0.000| -result<4> | 8.935(R)| SLOW | 4.334(R)| FAST |clkm_BUFGP | 0.000| -result<5> | 12.060(R)| SLOW | 5.801(R)| FAST |clkm_BUFGP | 0.000| -------------+-----------------+------------+-----------------+------------+------------------+--------+ - -Clock to Setup on destination clock clkm ----------------+---------+---------+---------+---------+ - | Src:Rise| Src:Fall| Src:Rise| Src:Fall| -Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ----------------+---------+---------+---------+---------+ -clkm | 9.399| | | | ----------------+---------+---------+---------+---------+ - - -Analysis completed Tue Aug 14 16:12:09 2012 --------------------------------------------------------------------------------- - -Trace Settings: -------------------------- -Trace Settings - -Peak Memory Usage: 420 MB - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.twx =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.twx (revision 17) +++ (revision ) @@ -1,339 +1,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -]> -Release 12.3 Trace (nt64)Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3 --n 3 -fastpaths -xml MultiMPITest.twx MultiMPITest.ncd -o MultiMPITest.twr -MultiMPITest.pcf - -MultiMPITest.ncdMultiMPITest.ncdMultiMPITest.pcfMultiMPITest.pcfxc6slx100C-3PRODUCTION 1.12c 2010-09-1513INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.clkmreset16.6720.529clkmclkmclkm9.399Tue Aug 14 16:12:09 2012 TraceTrace Settings - -Peak Memory Usage: 420 MB - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.unroutes =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.unroutes (revision 17) +++ (revision ) @@ -1,20 +1,0 @@ -Release 12.3 - par M.70d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -Tue Aug 14 16:11:52 2012 - -All signals are completely routed. - -WARNING:ParHelpers:361 - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC - warnings. - - uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O - uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O - uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O - uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O - uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O - uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O - uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O - uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.xpi =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.xpi (revision 17) +++ (revision ) @@ -1,3 +1,0 @@ -PROGRAM=PAR -STATE=ROUTED -TIMESPECS_MET=OFF Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.xst =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest.xst (revision 17) +++ (revision ) @@ -1,53 +1,0 @@ -set -tmpdir "xst/projnav.tmp" -set -xsthdpdir "xst" -run --ifn MultiMPITest.prj --ifmt mixed --ofn MultiMPITest --ofmt NGC --p xc6slx100-3-fgg484 --top MultiMPITest --opt_mode Speed --opt_level 1 --power NO --iuc NO --keep_hierarchy Soft --netlist_hierarchy As_Optimized --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case Maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --dsp_utilization_ratio 100 --lc Auto --reduce_control_sets Auto --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style LUT --ram_extract Yes --ram_style Auto --rom_extract Yes --shreg_extract YES --rom_style Auto --auto_bram_packing NO --resource_sharing YES --async_to_sync NO --shreg_min_size 2 --use_dsp48 Auto --iobuf YES --max_fanout 100000 --bufg 16 --register_duplication YES --register_balancing No --optimize_primitives NO --use_clock_enable Auto --use_sync_set Auto --use_sync_reset Auto --iob Auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_beh.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_beh.prj (revision 17) +++ (revision ) @@ -1,42 +1,0 @@ -vhdl NocLib "../SWITCH_GENERIC_16_16/CoreTypes.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/RAM_256.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Arbiter.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Crossbit.vhd" -vhdl work "round_robbin_machine.vhd" -vhdl work "Packet_type.vhd" -vhdl work "MUX8.vhd" -vhdl work "MUX1.vhd" -vhdl work "DEMUX1.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Scheduler.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Crossbar.vhd" -vhdl work "MPI_CORE_SCHEDULER.vhd" -vhdl work "load_instr.vhd" -vhdl work "FIFO_64_FWFT.vhd" -vhdl work "EX4_FSM.vhd" -vhdl work "EX3_FSM.vhd" -vhdl work "EX2_FSM.vhd" -vhdl work "EX1_FSM.vhd" -vhdl work "Ex0_Fsm.vhd" -vhdl work "DMA_ARBITER.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" -vhdl work "RAM_32_32.vhd" -vhdl work "MPI_RMA.vhd" -vhdl work "CORE_MPI.vhd" -vhdl work "PE.vhd" -vhdl work "MPI_NOC.vhd" -vhdl work "MultiMPITest.vhd" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_envsettings.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_envsettings.html (revision 17) +++ (revision ) @@ -1,532 +1,0 @@ -Xilinx System Settings Report - -
System Settings

- - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Environment Settings
Environment Variablexstngdbuildmappar
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Pathd:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
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D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
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D:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files (x86)\PC Connectivity Solution\;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
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c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox;
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C:\modeltech_6.5\win32		d:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
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C:\Program Files\Common Files\Microsoft Shared\Windows Live;
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C:\Program Files (x86)\CMake 2.8\bin;
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c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox;
C:\modeltech_6.6b\win32		d:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
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D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
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C:\Program Files\Common Files\Microsoft Shared\Windows Live;
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C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\CMake 2.8\bin;
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C:\qtsdk\qtcreator\bin;
C:\Program Files (x86)\Graphviz 2.28\bin;
C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox;
C:\modeltech_6.6b\win32		d:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
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D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
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C:\Program Files\Common Files\Microsoft Shared\Windows Live;
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C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\CMake 2.8\bin;
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C:\qtsdk\qtcreator\bin;
C:\Program Files (x86)\Graphviz 2.28\bin;
C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox;
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XILINXd:\Xilinx\12.3\ISE_DS\ISE\d:\Xilinx\12.3\ISE_DS\ISE\d:\Xilinx\12.3\ISE_DS\ISE\d:\Xilinx\12.3\ISE_DS\ISE\
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- - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn MultiMPITest.prj 
-ifmt mixedMixed
-ofn MultiMPITest 
-ofmt NGCNGC
-p xc6slx100-3-fgg484 
-top MultiMPITest 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-powerPower ReductionNONo
-iucUse synthesis Constraints FileNONo
-keep_hierarchyKeep HierarchySoftNo
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNo
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYes
-write_timing_constraintsWrite Timing ConstraintsNONo
-cross_clock_analysisCross Clock AnalysisNONo
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100
-bram_utilization_ratioBRAM Utilization Ratio100100
-dsp_utilization_ratioDSP Utilization Ratio100100
-reduce_control_sets AutoAuto
-fsm_extract YESYes
-fsm_encoding AutoAuto
-safe_implementation NoNo
-fsm_style LUTLUT
-ram_extract YesYes
-ram_style AutoAuto
-rom_extract YesYes
-shreg_extract YESYes
-rom_style AutoAuto
-auto_bram_packing NONo
-resource_sharing YESYes
-async_to_sync NONo
-use_dsp48 AutoAuto
-iobuf YESYes
-max_fanout 100000100000
-bufg 1616
-register_duplication YESYes
-register_balancing NoNo
-optimize_primitives NONo
-use_clock_enable AutoAuto
-use_sync_set AutoAuto
-use_sync_reset AutoAuto
-iob AutoAuto
-equivalent_register_removal YESYes
-slice_utilization_ratio_maxmargin 50
- - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
Translation Property Settings
Switch NameProperty NameValueDefault Value
-intstyle iseNone
-dd _ngoNone
-p xc6slx100-fgg484-3None
- - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Map Property Settings
Switch NameProperty NameValueDefault Value
-olPlace & Route Effort Level (Overall)highhigh
-xtExtra Cost Tables00
-irUse RLOC ConstraintsOFFOFF
-tStarting Placer Cost Table (1-100) Map10
-intstyle iseNone
-lcLUT Combiningoffoff
-o MultiMPITest_map.ncdNone
-w truefalse
-prPack I/O Registers/Latches into IOBsoffoff
-p xc6slx100-fgg484-3None
- - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Place and Route Property Settings
Switch NameProperty NameValueDefault Value
-intstyle ise 
-mtEnable Multi-Threadingoffoff
-olPlace & Route Effort Level (Overall)highstd
-w truefalse
- - 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHzIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHzIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHzIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHz
HostGAMOM-PCGAMOM-PCGAMOM-PCGAMOM-PC
OS NameMicrosoft Microsoft Microsoft Microsoft
OS ReleaseService Pack 1 (build 7601)Service Pack 1 (build 7601)Service Pack 1 (build 7601)Service Pack 1 (build 7601)
- Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_map.map =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_map.map (revision 17) +++ (revision ) @@ -1,486 +1,0 @@ -Release 12.3 Map M.70d (nt64) -Xilinx Map Application Log File for Design 'MultiMPITest' - -Design Information ------------------- -Command Line : map -intstyle ise -p xc6slx100-fgg484-3 -w -logic_opt off -ol -high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr -off -lc off -power off -o MultiMPITest_map.ncd MultiMPITest.ngd MultiMPITest.pcf - -Target Device : xc6slx100 -Target Package : fgg484 -Target Speed : -3 -Mapper Version : spartan6 -- $Revision: 1.52 $ -Mapped Date : Tue Aug 14 16:09:02 2012 - -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:56 - Part 'xc6slx100' is not a WebPack part. -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. ----------------------------------------------------------------------- -Mapping design into LUTs... -Running directed packing... -Running delay-based LUT packing... -Updating timing models... -INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report - (.mrp). -Running timing-driven placement... -Total REAL time at the beginning of Placer: 19 secs -Total CPU time at the beginning of Placer: 17 secs - -Phase 1.1 Initial Placement Analysis -Phase 1.1 Initial Placement Analysis (Checksum:1bc559d) REAL time: 24 secs - -Phase 2.7 Design Feasibility Check -Phase 2.7 Design Feasibility Check (Checksum:1bc559d) REAL time: 25 secs - -Phase 3.31 Local Placement Optimization -Phase 3.31 Local Placement Optimization (Checksum:1bc559d) REAL time: 25 secs - -Phase 4.2 Initial Placement for Architecture Specific Features -...... -Phase 4.2 Initial Placement for Architecture Specific Features -(Checksum:3f0f921f) REAL time: 33 secs - -Phase 5.36 Local Placement Optimization -Phase 5.36 Local Placement Optimization (Checksum:3f0f921f) REAL time: 33 secs - -Phase 6.30 Global Clock Region Assignment -Phase 6.30 Global Clock Region Assignment (Checksum:3f0f921f) REAL time: 33 secs - -Phase 7.3 Local Placement Optimization -.... -Phase 7.3 Local Placement Optimization (Checksum:49665fbf) REAL time: 34 secs - -Phase 8.5 Local Placement Optimization -Phase 8.5 Local Placement Optimization (Checksum:49665fbf) REAL time: 34 secs - -Phase 9.8 Global Placement -........................................................ -......................................................................................................................................................................................... -......................................................... -....................................... -Phase 9.8 Global Placement (Checksum:1156e879) REAL time: 1 mins 19 secs - -Phase 10.5 Local Placement Optimization -Phase 10.5 Local Placement Optimization (Checksum:1156e879) REAL time: 1 mins 19 secs - -Phase 11.18 Placement Optimization -Phase 11.18 Placement Optimization (Checksum:7caf5c44) REAL time: 1 mins 58 secs - -Phase 12.5 Local Placement Optimization -Phase 12.5 Local Placement Optimization (Checksum:7caf5c44) REAL time: 1 mins 58 secs - -Phase 13.34 Placement Validation -Phase 13.34 Placement Validation (Checksum:1a5ac37f) REAL time: 1 mins 58 secs - -Total REAL time to Placer completion: 1 mins 58 secs -Total CPU time to Placer completion: 1 mins 54 secs -Running post-placement packing... -Writing output files... -WARNING:PhysDesignRules:372 - Gated clock. Clock net PE2/N315 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net PE1/etPutGet_FSM_FFd7 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd7 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - PE1/etPutGet[3]_PWR_594_o_Mux_268_o is sourced by a combinatorial pin. This - is not good design practice. Use the CE pin to control the loading of data - into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_132_o_Mux_355_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_132_o_Mux_355_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_38_o_Mux_199_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_38_o_Mux_199_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_278_o_Mux_43_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_278_o_Mux_43_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_o - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_o - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - PE2/etPutGet[3]_PWR_639_o_Mux_268_o is sourced by a combinatorial pin. This - is not good design practice. Use the CE pin to control the loading of data - into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/N117 is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/N117 is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. - -Design Summary --------------- - -Design Summary: -Number of errors: 0 -Number of warnings: 83 -Slice Logic Utilization: - Number of Slice Registers: 1,515 out of 126,576 1% - Number used as Flip Flops: 1,137 - Number used as Latches: 378 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 0 - Number of Slice LUTs: 3,025 out of 63,288 4% - Number used as logic: 2,942 out of 63,288 4% - Number using O6 output only: 2,058 - Number using O5 output only: 294 - Number using O5 and O6: 590 - Number used as ROM: 0 - Number used as Memory: 48 out of 15,616 1% - Number used as Dual Port RAM: 48 - Number using O6 output only: 48 - Number using O5 output only: 0 - Number using O5 and O6: 0 - Number used as Single Port RAM: 0 - Number used as Shift Register: 0 - Number used exclusively as route-thrus: 35 - Number with same-slice register load: 7 - Number with same-slice carry load: 28 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 1,099 out of 15,822 6% - Number of LUT Flip Flop pairs used: 3,230 - Number with an unused Flip Flop: 1,806 out of 3,230 55% - Number with an unused LUT: 205 out of 3,230 6% - Number of fully used LUT-FF pairs: 1,219 out of 3,230 37% - Number of unique control sets: 226 - Number of slice register sites lost - to control set restrictions: 749 out of 126,576 1% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - -IO Utilization: - Number of bonded IOBs: 10 out of 326 3% - -Specific Feature Utilization: - Number of RAMB16BWERs: 64 out of 268 23% - Number of RAMB8BWERs: 4 out of 536 1% - Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% - Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% - Number of BUFG/BUFGMUXs: 3 out of 16 18% - Number used as BUFGs: 3 - Number used as BUFGMUX: 0 - Number of DCM/DCM_CLKGENs: 0 out of 12 0% - Number of ILOGIC2/ISERDES2s: 0 out of 506 0% - Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 506 0% - Number of OLOGIC2/OSERDES2s: 0 out of 506 0% - Number of BSCANs: 0 out of 4 0% - Number of BUFHs: 0 out of 384 0% - Number of BUFPLLs: 0 out of 8 0% - Number of BUFPLL_MCBs: 0 out of 4 0% - Number of DSP48A1s: 0 out of 180 0% - Number of ICAPs: 0 out of 1 0% - Number of MCBs: 0 out of 4 0% - Number of PCILOGICSEs: 0 out of 2 0% - Number of PLL_ADVs: 0 out of 6 0% - Number of PMVs: 0 out of 1 0% - Number of STARTUPs: 0 out of 1 0% - Number of SUSPEND_SYNCs: 0 out of 1 0% - -Average Fanout of Non-Clock Nets: 4.55 - -Peak Memory Usage: 596 MB -Total REAL time to MAP completion: 2 mins 3 secs -Total CPU time to MAP completion: 1 mins 58 secs - -Mapping completed. -See MAP report file "MultiMPITest_map.mrp" for details. Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_map.mrp =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_map.mrp (revision 17) +++ (revision ) @@ -1,620 +1,0 @@ -Release 12.3 Map M.70d (nt64) -Xilinx Mapping Report File for Design 'MultiMPITest' - -Design Information ------------------- -Command Line : map -intstyle ise -p xc6slx100-fgg484-3 -w -logic_opt off -ol -high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr -off -lc off -power off -o MultiMPITest_map.ncd MultiMPITest.ngd MultiMPITest.pcf - -Target Device : xc6slx100 -Target Package : fgg484 -Target Speed : -3 -Mapper Version : spartan6 -- $Revision: 1.52 $ -Mapped Date : Tue Aug 14 16:09:02 2012 - -Design Summary --------------- -Number of errors: 0 -Number of warnings: 83 -Slice Logic Utilization: - Number of Slice Registers: 1,515 out of 126,576 1% - Number used as Flip Flops: 1,137 - Number used as Latches: 378 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 0 - Number of Slice LUTs: 3,025 out of 63,288 4% - Number used as logic: 2,942 out of 63,288 4% - Number using O6 output only: 2,058 - Number using O5 output only: 294 - Number using O5 and O6: 590 - Number used as ROM: 0 - Number used as Memory: 48 out of 15,616 1% - Number used as Dual Port RAM: 48 - Number using O6 output only: 48 - Number using O5 output only: 0 - Number using O5 and O6: 0 - Number used as Single Port RAM: 0 - Number used as Shift Register: 0 - Number used exclusively as route-thrus: 35 - Number with same-slice register load: 7 - Number with same-slice carry load: 28 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 1,099 out of 15,822 6% - Number of LUT Flip Flop pairs used: 3,230 - Number with an unused Flip Flop: 1,806 out of 3,230 55% - Number with an unused LUT: 205 out of 3,230 6% - Number of fully used LUT-FF pairs: 1,219 out of 3,230 37% - Number of unique control sets: 226 - Number of slice register sites lost - to control set restrictions: 749 out of 126,576 1% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - -IO Utilization: - Number of bonded IOBs: 10 out of 326 3% - -Specific Feature Utilization: - Number of RAMB16BWERs: 64 out of 268 23% - Number of RAMB8BWERs: 4 out of 536 1% - Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% - Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% - Number of BUFG/BUFGMUXs: 3 out of 16 18% - Number used as BUFGs: 3 - Number used as BUFGMUX: 0 - Number of DCM/DCM_CLKGENs: 0 out of 12 0% - Number of ILOGIC2/ISERDES2s: 0 out of 506 0% - Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 506 0% - Number of OLOGIC2/OSERDES2s: 0 out of 506 0% - Number of BSCANs: 0 out of 4 0% - Number of BUFHs: 0 out of 384 0% - Number of BUFPLLs: 0 out of 8 0% - Number of BUFPLL_MCBs: 0 out of 4 0% - Number of DSP48A1s: 0 out of 180 0% - Number of ICAPs: 0 out of 1 0% - Number of MCBs: 0 out of 4 0% - Number of PCILOGICSEs: 0 out of 2 0% - Number of PLL_ADVs: 0 out of 6 0% - Number of PMVs: 0 out of 1 0% - Number of STARTUPs: 0 out of 1 0% - Number of SUSPEND_SYNCs: 0 out of 1 0% - -Average Fanout of Non-Clock Nets: 4.55 - -Peak Memory Usage: 596 MB -Total REAL time to MAP completion: 2 mins 3 secs -Total CPU time to MAP completion: 1 mins 58 secs - -Table of Contents ------------------ -Section 1 - Errors -Section 2 - Warnings -Section 3 - Informational -Section 4 - Removed Logic Summary -Section 5 - Removed Logic -Section 6 - IOB Properties -Section 7 - RPMs -Section 8 - Guide Report -Section 9 - Area Group and Partition Summary -Section 10 - Timing Report -Section 11 - Configuration String Information -Section 12 - Control Set Information -Section 13 - Utilization by Hierarchy - -Section 1 - Errors ------------------- - -Section 2 - Warnings --------------------- -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. -WARNING:PhysDesignRules:372 - Gated clock. Clock net PE2/N315 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net PE1/etPutGet_FSM_FFd7 is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd7 is sourced by a - combinatorial pin. This is not good design practice. Use the CE pin to - control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - PE1/etPutGet[3]_PWR_594_o_Mux_268_o is sourced by a combinatorial pin. This - is not good design practice. Use the CE pin to control the loading of data - into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_132_o_Mux_355_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_132_o_Mux_355_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_38_o_Mux_199_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_38_o_Mux_199_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_278_o_Mux_43_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_278_o_Mux_43_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_o - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_o - is sourced by a combinatorial pin. This is not good design practice. Use the - CE pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - PE2/etPutGet[3]_PWR_639_o_Mux_268_o is sourced by a combinatorial pin. This - is not good design practice. Use the CE pin to control the loading of data - into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[2].hardmpi/LD_instr/N117 is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/N117 is sourced by a combinatorial pin. - This is not good design practice. Use the CE pin to control the loading of - data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:372 - Gated clock. Clock net - uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o is - sourced by a combinatorial pin. This is not good design practice. Use the CE - pin to control the loading of data into the flip-flop. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. -WARNING:PhysDesignRules:367 - The signal - - is incomplete. The signal does not drive any load pins in the design. - -Section 3 - Informational -------------------------- -INFO:Security:56 - Part 'xc6slx100' is not a WebPack part. -INFO:LIT:243 - Logical network MPI_Node_Out[2]_PushOut<7> has no load. -INFO:LIT:395 - The above info message is repeated 23 more times for the - following (max. 5 shown): - MPI_Node_Out[2]_PushOut<6>, - MPI_Node_Out[2]_PushOut<5>, - MPI_Node_Out[2]_PushOut<3>, - MPI_Node_Out[2]_PushOut<2>, - MPI_Node_Out[2]_PushOut<1> - To see the details of these info messages, please use the -detail switch. -INFO:MapLib:562 - No environment variables are currently set. -INFO:LIT:244 - All of the single ended outputs in this design are using slew - rate limited output drivers. The delay on speed critical single ended outputs - can be dramatically reduced by designating them as fast outputs. -INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: - 0.000 to 85.000 Celsius) -INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to - 1.260 Volts) -INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report - (.mrp). -INFO:Pack:1650 - Map created a placed design. - -Section 4 - Removed Logic Summary ---------------------------------- - 45 block(s) optimized away - -Section 5 - Removed Logic -------------------------- - -Optimized Block(s): -TYPE BLOCK -GND PE1/Inst_RAM_v/XST_GND -VCC PE1/Inst_RAM_v/XST_VCC -GND PE1/XST_GND -VCC PE1/XST_VCC -GND PE2/Inst_RAM_v/XST_GND -VCC PE2/Inst_RAM_v/XST_VCC -GND PE2/XST_GND -VCC PE2/XST_VCC -GND - uut/Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_POR -T_FIFO/XST_GND -VCC - uut/Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_POR -T_FIFO/XST_VCC -GND - uut/Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_POR -T_FIFO/fifo_RAM_256/XST_GND -VCC - uut/Socsyst.switch_gen1/port_out_switch2x2.PORT1_OUTPUT_PORT_MODULE/OUTPUT_POR -T_FIFO/fifo_RAM_256/XST_VCC -GND - uut/Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_POR -T_FIFO/XST_GND -VCC - uut/Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_POR -T_FIFO/XST_VCC -GND - uut/Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_POR -T_FIFO/fifo_RAM_256/XST_GND -VCC - uut/Socsyst.switch_gen1/port_out_switch2x2.PORT2_OUTPUT_PORT_MODULE/OUTPUT_POR -T_FIFO/fifo_RAM_256/XST_VCC -GND - uut/Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_ -GND -VCC - uut/Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_ -VCC -GND - uut/Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo -_RAM_256/XST_GND -VCC - uut/Socsyst.switch_gen1/switch2x2.PORT1_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo -_RAM_256/XST_VCC -GND - uut/Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_ -GND -VCC - uut/Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/XST_ -VCC -GND - uut/Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo -_RAM_256/XST_GND -VCC - uut/Socsyst.switch_gen1/switch2x2.PORT2_INPUT_PORT_MODULE/INPUT_PORT_FIFO/fifo -_RAM_256/XST_VCC -GND uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/XST_GND -GND uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/XST_GND -GND uut/connect_core[1].hardmpi/LD_instr/XST_GND -VCC uut/connect_core[1].hardmpi/LD_instr/XST_VCC -GND uut/connect_core[1].hardmpi/MPI_CORE_EX1_FSM/XST_GND -VCC uut/connect_core[1].hardmpi/MPI_CORE_EX1_FSM/XST_VCC -GND uut/connect_core[1].hardmpi/MPI_CORE_EX2_FSM/XST_GND -VCC uut/connect_core[1].hardmpi/MPI_CORE_EX2_FSM/XST_VCC -GND uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/XST_GND -VCC uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/XST_VCC -GND uut/connect_core[1].hardmpi/XST_GND -GND uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/XST_GND -GND uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/XST_GND -GND uut/connect_core[2].hardmpi/LD_instr/XST_GND -VCC uut/connect_core[2].hardmpi/LD_instr/XST_VCC -GND uut/connect_core[2].hardmpi/MPI_CORE_EX1_FSM/XST_GND -VCC uut/connect_core[2].hardmpi/MPI_CORE_EX1_FSM/XST_VCC -GND uut/connect_core[2].hardmpi/MPI_CORE_EX2_FSM/XST_GND -VCC uut/connect_core[2].hardmpi/MPI_CORE_EX2_FSM/XST_VCC -GND uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/XST_GND -VCC uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/XST_VCC - -To enable printing of redundant blocks removed and signals merged, set the -detailed map report option and rerun map. - -Section 6 - IOB Properties --------------------------- - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | -| | | | | Term | Strength | Rate | | | Delay | -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -| clkm | IOB | INPUT | LVCMOS25 | | | | | | | -| reset | IOB | INPUT | LVCMOS25 | | | | | | | -| result<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| result<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| result<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| result<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| result<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| result<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| result<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| result<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ - -Section 7 - RPMs ----------------- - -Section 8 - Guide Report ------------------------- -Guide not run on this design. - -Section 9 - Area Group and Partition Summary --------------------------------------------- - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -Area Group Information ----------------------- - - No area groups were found in this design. - ----------------------- - -Section 10 - Timing Report --------------------------- -A logic-level (pre-route) timing report can be generated by using Xilinx static -timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the -mapped NCD and PCF files. Please note that this timing report will be generated -using estimated delay information. For accurate numbers, please generate a -timing report with the post Place and Route NCD file. - -For more information about the Timing Analyzer, consult the Xilinx Timing -Analyzer Reference Manual; for more information about TRCE, consult the Xilinx -Command Line Tools User Guide "TRACE" chapter. - -Section 11 - Configuration String Details ------------------------------------------ -Use the "-detail" map option to print out Configuration Strings - -Section 12 - Control Set Information ------------------------------------- -Use the "-detail" map option to print out Control Set Information. - -Section 13 - Utilization by Hierarchy -------------------------------------- -Use the "-detail" map option to print out the Utilization by Hierarchy section. Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_pad.csv =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_pad.csv (revision 17) +++ (revision ) @@ -1,515 +1,0 @@ -#Release 12.3 - par M.70d (nt64) -#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -#Tue Aug 14 16:11:52 2012 - -# -## NOTE: This file is designed to be imported into a spreadsheet program -# such as Microsoft Excel for viewing, printing and sorting. The | -# character is used as the data field separator. This file is also designed -# to support parsing. -# -#INPUT FILE: MultiMPITest_map.ncd -#OUTPUT FILE: MultiMPITest_pad.csv -#PART TYPE: xc6slx100 -#SPEED GRADE: -3 -#PACKAGE: fgg484 -# -# Pinout by Pin Number: -# -# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, -Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity, -A1,,,GND,,,,,,,,,,,, -A2,,IOBM,IO_L83P_3,UNUSED,,3,,,,,,,,, -A3,,IOBM,IO_L1P_HSWAPEN_0,UNUSED,,0,,,,,,,,, -A4,,IOBS,IO_L1N_VREF_0,UNUSED,,0,,,,,,,,, -A5,,IOBS,IO_L2N_0,UNUSED,,0,,,,,,,,, -A6,,IOBS,IO_L4N_0,UNUSED,,0,,,,,,,,, -A7,,IOBS,IO_L5N_0,UNUSED,,0,,,,,,,,, -A8,,IOBS,IO_L6N_0,UNUSED,,0,,,,,,,,, -A9,,IOBS,IO_L8N_VREF_0,UNUSED,,0,,,,,,,,, -A10,,IOBS,IO_L34N_GCLK18_0,UNUSED,,0,,,,,,,,, -A11,,IOBS,IO_L35N_GCLK16_0,UNUSED,,0,,,,,,,,, -A12,,IOBS,IO_L37N_GCLK12_0,UNUSED,,0,,,,,,,,, -A13,,IOBS,IO_L38N_VREF_0,UNUSED,,0,,,,,,,,, -A14,,IOBS,IO_L50N_0,UNUSED,,0,,,,,,,,, -A15,,IOBS,IO_L51N_0,UNUSED,,0,,,,,,,,, -A16,,IOBS,IO_L63N_SCP6_0,UNUSED,,0,,,,,,,,, -A17,,IOBS,IO_L64N_SCP4_0,UNUSED,,0,,,,,,,,, -A18,,IOBS,IO_L65N_SCP2_0,UNUSED,,0,,,,,,,,, -A19,,,TDO,,,,,,,,,,,, -A20,,IOBM,IO_L20P_1,UNUSED,,1,,,,,,,,, -A21,,IOBS,IO_L20N_1,UNUSED,,1,,,,,,,,, -A22,,,GND,,,,,,,,,,,, -AA1,,,PROGRAM_B_2,,,,,,,,,,,, -AA2,,IOBM,IO_L64P_D8_2,UNUSED,,2,,,,,,,,, -AA3,,,VCCO_2,,,2,,,,,any******,,,, -AA4,,IOBM,IO_L57P_2,UNUSED,,2,,,,,,,,, -AA5,,,GND,,,,,,,,,,,, -AA6,,IOBM,IO_L49P_D3_2,UNUSED,,2,,,,,,,,, -AA7,,,VCCO_2,,,2,,,,,any******,,,, -AA8,,IOBM,IO_L45P_2,UNUSED,,2,,,,,,,,, -AA9,,,GND,,,,,,,,,,,, -AA10,,IOBM,IO_L41P_2,UNUSED,,2,,,,,,,,, -AA11,,,VCCO_2,,,2,,,,,any******,,,, -AA12,,IOBM,IO_L31P_GCLK31_D14_2,UNUSED,,2,,,,,,,,, -AA13,,,GND,,,,,,,,,,,, -AA14,,IOBM,IO_L16P_2,UNUSED,,2,,,,,,,,, -AA15,,,VCCO_2,,,2,,,,,any******,,,, -AA16,,IOBM,IO_L19P_2,UNUSED,,2,,,,,,,,, -AA17,,,GND,,,,,,,,,,,, -AA18,,IOBM,IO_L14P_D11_2,UNUSED,,2,,,,,,,,, -AA19,,,VCCO_2,,,2,,,,,any******,,,, -AA20,,IOBM,IO_L3P_D0_DIN_MISO_MISO1_2,UNUSED,,2,,,,,,,,, -AA21,,IOBM,IO_L2P_CMPCLK_2,UNUSED,,2,,,,,,,,, -AA22,,IOBS,IO_L1N_M0_CMPMISO_2,UNUSED,,2,,,,,,,,, -AB1,,,GND,,,,,,,,,,,, -AB2,,IOBS,IO_L64N_D9_2,UNUSED,,2,,,,,,,,, -AB3,,IOBS,IO_L58N_2,UNUSED,,2,,,,,,,,, -AB4,,IOBS,IO_L57N_2,UNUSED,,2,,,,,,,,, -AB5,,,NC,,,,,,,,,,,, -AB6,,IOBS,IO_L49N_D4_2,UNUSED,,2,,,,,,,,, -AB7,,IOBS,IO_L48N_RDWR_B_VREF_2,UNUSED,,2,,,,,,,,, -AB8,,IOBS,IO_L45N_2,UNUSED,,2,,,,,,,,, -AB9,,IOBS,IO_L43N_2,UNUSED,,2,,,,,,,,, -AB10,,IOBS,IO_L41N_VREF_2,UNUSED,,2,,,,,,,,, -AB11,,IOBS,IO_L32N_GCLK28_2,UNUSED,,2,,,,,,,,, -AB12,,IOBS,IO_L31N_GCLK30_D15_2,UNUSED,,2,,,,,,,,, -AB13,,IOBS,IO_L30N_GCLK0_USERCCLK_2,UNUSED,,2,,,,,,,,, -AB14,,IOBS,IO_L16N_VREF_2,UNUSED,,2,,,,,,,,, -AB15,,IOBS,IO_L21N_2,UNUSED,,2,,,,,,,,, -AB16,,IOBS,IO_L19N_2,UNUSED,,2,,,,,,,,, -AB17,,IOBS,IO_L15N_2,UNUSED,,2,,,,,,,,, -AB18,,IOBS,IO_L14N_D12_2,UNUSED,,2,,,,,,,,, -AB19,,IOBS,IO_L5N_2,UNUSED,,2,,,,,,,,, -AB20,,IOBS,IO_L3N_MOSI_CSI_B_MISO0_2,UNUSED,,2,,,,,,,,, -AB21,,IOBS,IO_L2N_CMPMOSI_2,UNUSED,,2,,,,,,,,, -AB22,,,GND,,,,,,,,,,,, -B1,,IOBS,IO_L60N_3,UNUSED,,3,,,,,,,,, -B2,,IOBM,IO_L60P_3,UNUSED,,3,,,,,,,,, -B3,,IOBS,IO_L83N_VREF_3,UNUSED,,3,,,,,,,,, -B4,,,VCCO_0,,,0,,,,,any******,,,, -B5,,,GND,,,,,,,,,,,, -B6,,IOBM,IO_L4P_0,UNUSED,,0,,,,,,,,, -B7,,,VCCO_0,,,0,,,,,any******,,,, -B8,,IOBM,IO_L6P_0,UNUSED,,0,,,,,,,,, -B9,,,GND,,,,,,,,,,,, -B10,,IOBM,IO_L34P_GCLK19_0,UNUSED,,0,,,,,,,,, -B11,,,VCCO_0,,,0,,,,,any******,,,, -B12,,IOBM,IO_L37P_GCLK13_0,UNUSED,,0,,,,,,,,, -B13,,,GND,,,,,,,,,,,, -B14,,IOBM,IO_L50P_0,UNUSED,,0,,,,,,,,, -B15,,,VCCO_0,,,0,,,,,any******,,,, -B16,,IOBM,IO_L63P_SCP7_0,UNUSED,,0,,,,,,,,, -B17,,,GND,,,,,,,,,,,, -B18,,IOBM,IO_L65P_SCP3_0,UNUSED,,0,,,,,,,,, -B19,,,VCCO_0,,,0,,,,,any******,,,, -B20,,IOBS,IO_L1N_A24_VREF_1,UNUSED,,1,,,,,,,,, -B21,,IOBM,IO_L19P_1,UNUSED,,1,,,,,,,,, -B22,,IOBS,IO_L19N_1,UNUSED,,1,,,,,,,,, -C1,,IOBS,IO_L54N_M3A11_3,UNUSED,,3,,,,,,,,, -C2,,,VCCO_3,,,3,,,,,2.50,,,, -C3,,IOBM,IO_L54P_M3RESET_3,UNUSED,,3,,,,,,,,, -C4,,IOBS,IO_L81N_3,UNUSED,,3,,,,,,,,, -C5,,IOBM,IO_L2P_0,UNUSED,,0,,,,,,,,, -C6,,IOBS,IO_L3N_0,UNUSED,,0,,,,,,,,, -C7,,IOBM,IO_L5P_0,UNUSED,,0,,,,,,,,, -C8,,IOBS,IO_L7N_0,UNUSED,,0,,,,,,,,, -C9,,IOBM,IO_L8P_0,UNUSED,,0,,,,,,,,, -C10,,IOBS,IO_L33N_0,UNUSED,,0,,,,,,,,, -C11,,IOBM,IO_L35P_GCLK17_0,UNUSED,,0,,,,,,,,, -C12,,IOBS,IO_L36N_GCLK14_0,UNUSED,,0,,,,,,,,, -C13,,IOBM,IO_L38P_0,UNUSED,,0,,,,,,,,, -C14,,IOBS,IO_L49N_0,UNUSED,,0,,,,,,,,, -C15,,IOBM,IO_L51P_0,UNUSED,,0,,,,,,,,, -C16,,IOBS,IO_L62N_VREF_0,UNUSED,,0,,,,,,,,, -C17,,IOBM,IO_L64P_SCP5_0,UNUSED,,0,,,,,,,,, -C18,,,TMS,,,,,,,,,,,, -C19,,IOBM,IO_L1P_A25_1,UNUSED,,1,,,,,,,,, -C20,,IOBM,IO_L32P_A17_M1A8_1,UNUSED,,1,,,,,,,,, -C21,,,VCCO_1,,,1,,,,,any******,,,, -C22,,IOBS,IO_L32N_A16_M1A9_1,UNUSED,,1,,,,,,,,, -D1,,IOBS,IO_L53N_M3A12_3,UNUSED,,3,,,,,,,,, -D2,,IOBM,IO_L53P_M3CKE_3,UNUSED,,3,,,,,,,,, -D3,,IOBM,IO_L81P_3,UNUSED,,3,,,,,,,,, -D4,,,GND,,,,,,,,,,,, -D5,,IOBM,IO_L58P_3,UNUSED,,3,,,,,,,,, -D6,,IOBM,IO_L3P_0,UNUSED,,0,,,,,,,,, -D7,,IOBM,IO_L32P_0,UNUSED,,0,,,,,,,,, -D8,,IOBS,IO_L32N_0,UNUSED,,0,,,,,,,,, -D9,,IOBM,IO_L7P_0,UNUSED,,0,,,,,,,,, -D10,,IOBM,IO_L33P_0,UNUSED,,0,,,,,,,,, -D11,,IOBM,IO_L36P_GCLK15_0,UNUSED,,0,,,,,,,,, -D12,,IOBS,IO_L43N_0,UNUSED,,0,,,,,,,,, -D13,,IOBS,IO_L45N_0,UNUSED,,0,,,,,,,,, -D14,,IOBM,IO_L49P_0,UNUSED,,0,,,,,,,,, -D15,,IOBM,IO_L62P_0,UNUSED,,0,,,,,,,,, -D16,,,VCCAUX,,,,,,,,2.5,,,, -D17,,IOBS,IO_L66N_SCP0_0,UNUSED,,0,,,,,,,,, -D18,,,GND,,,,,,,,,,,, -D19,,IOBM,IO_L29P_A23_M1A13_1,UNUSED,,1,,,,,,,,, -D20,,IOBS,IO_L29N_A22_M1A14_1,UNUSED,,1,,,,,,,,, -D21,,IOBM,IO_L31P_A19_M1CKE_1,UNUSED,,1,,,,,,,,, -D22,,IOBS,IO_L31N_A18_M1A12_1,UNUSED,,1,,,,,,,,, -E1,,IOBS,IO_L52N_M3A9_3,UNUSED,,3,,,,,,,,, -E2,,,GND,,,,,,,,,,,, -E3,,IOBM,IO_L52P_M3A8_3,UNUSED,,3,,,,,,,,, -E4,,IOBS,IO_L58N_3,UNUSED,,3,,,,,,,,, -E5,,IOBM,IO_L82P_3,UNUSED,,3,,,,,,,,, -E6,,IOBS,IO_L82N_3,UNUSED,,3,,,,,,,,, -E7,,,GND,,,,,,,,,,,, -E8,,IOBM,IO_L14P_0,UNUSED,,0,,,,,,,,, -E9,,,VCCO_0,,,0,,,,,any******,,,, -E10,,IOBM,IO_L17P_0,UNUSED,,0,,,,,,,,, -E11,,,GND,,,,,,,,,,,, -E12,,IOBM,IO_L43P_0,UNUSED,,0,,,,,,,,, -E13,,,VCCO_0,,,0,,,,,any******,,,, -E14,,IOBM,IO_L47P_0,UNUSED,,0,,,,,,,,, -E15,,,GND,,,,,,,,,,,, -E16,,IOBM,IO_L66P_SCP1_0,UNUSED,,0,,,,,,,,, -E17,,,VCCO_0,,,0,,,,,any******,,,, -E18,,,TDI,,,,,,,,,,,, -E19,,,VCCO_1,,,1,,,,,any******,,,, -E20,,IOBM,IO_L35P_A11_M1A7_1,UNUSED,,1,,,,,,,,, -E21,,,GND,,,,,,,,,,,, -E22,,IOBS,IO_L35N_A10_M1A2_1,UNUSED,,1,,,,,,,,, -F1,,IOBS,IO_L50N_M3BA2_3,UNUSED,,3,,,,,,,,, -F2,,IOBM,IO_L50P_M3WE_3,UNUSED,,3,,,,,,,,, -F3,,IOBS,IO_L51N_M3A4_3,UNUSED,,3,,,,,,,,, -F4,,,VCCO_3,,,3,,,,,2.50,,,, -F5,,IOBS,IO_L55N_M3A14_3,UNUSED,,3,,,,,,,,, -F6,,,VCCO_3,,,3,,,,,2.50,,,, -F7,,IOBS,IO_L80N_3,UNUSED,,3,,,,,,,,, -F8,,IOBS,IO_L14N_0,UNUSED,,0,,,,,,,,, -F9,,IOBS,IO_L15N_0,UNUSED,,0,,,,,,,,, -F10,,IOBS,IO_L17N_0,UNUSED,,0,,,,,,,,, -F11,,,VCCAUX,,,,,,,,2.5,,,, -F12,,IOBS,IO_L44N_0,UNUSED,,0,,,,,,,,, -F13,,IOBM,IO_L45P_0,UNUSED,,0,,,,,,,,, -F14,,IOBM,IO_L48P_0,UNUSED,,0,,,,,,,,, -F15,,IOBS,IO_L47N_0,UNUSED,,0,,,,,,,,, -F16,,IOBM,IO_L10P_1,UNUSED,,1,,,,,,,,, -F17,,IOBS,IO_L10N_1,UNUSED,,1,,,,,,,,, -F18,,IOBM,IO_L30P_A21_M1RESET_1,UNUSED,,1,,,,,,,,, -F19,,IOBS,IO_L30N_A20_M1A11_1,UNUSED,,1,,,,,,,,, -F20,,IOBS,IO_L33N_A14_M1A4_1,UNUSED,,1,,,,,,,,, -F21,,IOBM,IO_L37P_A7_M1A0_1,UNUSED,,1,,,,,,,,, -F22,,IOBS,IO_L37N_A6_M1A1_1,UNUSED,,1,,,,,,,,, -G1,,IOBS,IO_L48N_M3BA1_3,UNUSED,,3,,,,,,,,, -G2,,,VCCO_3,,,3,,,,,2.50,,,, -G3,,IOBM,IO_L48P_M3BA0_3,UNUSED,,3,,,,,,,,, -G4,,IOBM,IO_L51P_M3A10_3,UNUSED,,3,,,,,,,,, -G5,,,GND,,,,,,,,,,,, -G6,,IOBM,IO_L55P_M3A13_3,UNUSED,,3,,,,,,,,, -G7,,IOBM,IO_L80P_3,UNUSED,,3,,,,,,,,, -G8,,IOBM,IO_L15P_0,UNUSED,,0,,,,,,,,, -G9,,IOBM,IO_L16P_0,UNUSED,,0,,,,,,,,, -G10,,,VCCO_0,,,0,,,,,any******,,,, -G11,,IOBM,IO_L18P_0,UNUSED,,0,,,,,,,,, -G12,,,VCCAUX,,,,,,,,2.5,,,, -G13,,IOBS,IO_L46N_0,UNUSED,,0,,,,,,,,, -G14,,,VCCO_0,,,0,,,,,any******,,,, -G15,,,TCK,,,,,,,,,,,, -G16,,IOBM,IO_L9P_1,UNUSED,,1,,,,,,,,, -G17,,IOBS,IO_L9N_1,UNUSED,,1,,,,,,,,, -G18,,,GND,,,,,,,,,,,, -G19,,IOBM,IO_L33P_A15_M1A10_1,UNUSED,,1,,,,,,,,, -G20,,IOBM,IO_L39P_M1A3_1,UNUSED,,1,,,,,,,,, -G21,,,VCCO_1,,,1,,,,,any******,,,, -G22,,IOBS,IO_L39N_M1ODT_1,UNUSED,,1,,,,,,,,, -H1,,IOBS,IO_L47N_M3A1_3,UNUSED,,3,,,,,,,,, -H2,,IOBM,IO_L47P_M3A0_3,UNUSED,,3,,,,,,,,, -H3,,IOBS,IO_L46N_M3CLKN_3,UNUSED,,3,,,,,,,,, -H4,,IOBM,IO_L46P_M3CLK_3,UNUSED,,3,,,,,,,,, -H5,,IOBS,IO_L49N_M3A2_3,UNUSED,,3,,,,,,,,, -H6,,IOBM,IO_L49P_M3A7_3,UNUSED,,3,,,,,,,,, -H7,,,GND,,,,,,,,,,,, -H8,,IOBS,IO_L59N_3,UNUSED,,3,,,,,,,,, -H9,,,VCCAUX,,,,,,,,2.5,,,, -H10,,IOBS,IO_L16N_0,UNUSED,,0,,,,,,,,, -H11,,IOBS,IO_L18N_0,UNUSED,,0,,,,,,,,, -H12,,IOBM,IO_L44P_0,UNUSED,,0,,,,,,,,, -H13,,IOBM,IO_L46P_0,UNUSED,,0,,,,,,,,, -H14,,IOBS,IO_L48N_0,UNUSED,,0,,,,,,,,, -H15,,,VCCAUX,,,,,,,,2.5,,,, -H16,,IOBM,IO_L28P_1,UNUSED,,1,,,,,,,,, -H17,,IOBS,IO_L28N_VREF_1,UNUSED,,1,,,,,,,,, -H18,,IOBS,IO_L34N_A12_M1BA2_1,UNUSED,,1,,,,,,,,, -H19,,IOBM,IO_L34P_A13_M1WE_1,UNUSED,,1,,,,,,,,, -H20,,IOBM,IO_L38P_A5_M1CLK_1,UNUSED,,1,,,,,,,,, -H21,,IOBM,IO_L41P_GCLK9_IRDY1_M1RASN_1,UNUSED,,1,,,,,,,,, -H22,,IOBS,IO_L41N_GCLK8_M1CASN_1,UNUSED,,1,,,,,,,,, -J1,,IOBS,IO_L41N_GCLK26_M3DQ5_3,UNUSED,,3,,,,,,,,, -J2,,,GND,,,,,,,,,,,, -J3,,IOBM,IO_L41P_GCLK27_M3DQ4_3,UNUSED,,3,,,,,,,,, -J4,,IOBS,IO_L44N_GCLK20_M3A6_3,UNUSED,,3,,,,,,,,, -J5,,,VCCO_3,,,3,,,,,2.50,,,, -J6,,IOBS,IO_L45N_M3ODT_3,UNUSED,,3,,,,,,,,, -J7,,IOBM,IO_L59P_3,UNUSED,,3,,,,,,,,, -J8,,,VCCINT,,,,,,,,1.2,,,, -J9,,,GND,,,,,,,,,,,, -J10,,,VCCINT,,,,,,,,1.2,,,, -J11,,,GND,,,,,,,,,,,, -J12,,,VCCINT,,,,,,,,1.2,,,, -J13,,,GND,,,,,,,,,,,, -J14,,,VCCINT,,,,,,,,1.2,,,, -J15,,,GND,,,,,,,,,,,, -J16,,IOBS,IO_L21N_1,UNUSED,,1,,,,,,,,, -J17,,IOBM,IO_L36P_A9_M1BA0_1,UNUSED,,1,,,,,,,,, -J18,,,VCCO_1,,,1,,,,,any******,,,, -J19,,IOBS,IO_L38N_A4_M1CLKN_1,UNUSED,,1,,,,,,,,, -J20,,IOBM,IO_L43P_GCLK5_M1DQ4_1,UNUSED,,1,,,,,,,,, -J21,,,GND,,,,,,,,,,,, -J22,,IOBS,IO_L43N_GCLK4_M1DQ5_1,UNUSED,,1,,,,,,,,, -K1,,IOBS,IO_L40N_M3DQ7_3,UNUSED,,3,,,,,,,,, -K2,,IOBM,IO_L40P_M3DQ6_3,UNUSED,,3,,,,,,,,, -K3,,IOBM,IO_L44P_GCLK21_M3A5_3,UNUSED,,3,,,,,,,,, -K4,,IOBS,IO_L43N_GCLK22_IRDY2_M3CASN_3,UNUSED,,3,,,,,,,,, -K5,,IOBM,IO_L43P_GCLK23_M3RASN_3,UNUSED,,3,,,,,,,,, -K6,,IOBM,IO_L45P_M3A3_3,UNUSED,,3,,,,,,,,, -K7,,IOBM,IO_L57P_3,UNUSED,,3,,,,,,,,, -K8,,IOBS,IO_L57N_VREF_3,UNUSED,,3,,,,,,,,, -K9,,,VCCINT,,,,,,,,1.2,,,, -K10,,,GND,,,,,,,,,,,, -K11,,,VCCINT,,,,,,,,1.2,,,, -K12,,,GND,,,,,,,,,,,, -K13,,,VCCINT,,,,,,,,1.2,,,, -K14,,,GND,,,,,,,,,,,, -K15,,,VCCAUX,,,,,,,,2.5,,,, -K16,,IOBM,IO_L21P_1,UNUSED,,1,,,,,,,,, -K17,,IOBS,IO_L36N_A8_M1BA1_1,UNUSED,,1,,,,,,,,, -K18,,IOBS,IO_L61N_1,UNUSED,,1,,,,,,,,, -K19,,IOBS,IO_L40N_GCLK10_M1A6_1,UNUSED,,1,,,,,,,,, -K20,,IOBM,IO_L40P_GCLK11_M1A5_1,UNUSED,,1,,,,,,,,, -K21,,IOBM,IO_L44P_A3_M1DQ6_1,UNUSED,,1,,,,,,,,, -K22,,IOBS,IO_L44N_A2_M1DQ7_1,UNUSED,,1,,,,,,,,, -L1,,IOBS,IO_L39N_M3LDQSN_3,UNUSED,,3,,,,,,,,, -L2,,,VCCO_3,,,3,,,,,2.50,,,, -L3,,IOBM,IO_L39P_M3LDQS_3,UNUSED,,3,,,,,,,,, -L4,clkm,IOB,IO_L42N_GCLK24_M3LDM_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE, -L5,,,GND,,,,,,,,,,,, -L6,result<7>,IOB,IO_L25N_3,OUTPUT,LVCMOS25*,3,12,,,,,UNLOCATED,NO,NONE, -L7,,,VCCO_3,,,3,,,,,2.50,,,, -L8,,,VCCAUX,,,,,,,,2.5,,,, -L9,,,GND,,,,,,,,,,,, -L10,,,VCCINT,,,,,,,,1.2,,,, -L11,,,GND,,,,,,,,,,,, -L12,,,VCCINT,,,,,,,,1.2,,,, -L13,,,GND,,,,,,,,,,,, -L14,,,VCCINT,,,,,,,,1.2,,,, -L15,,IOBS,IO_L58N_1,UNUSED,,1,,,,,,,,, -L16,,,VCCO_1,,,1,,,,,any******,,,, -L17,,IOBM,IO_L61P_1,UNUSED,,1,,,,,,,,, -L18,,,GND,,,,,,,,,,,, -L19,,IOBS,IO_L42N_GCLK6_TRDY1_M1LDM_1,UNUSED,,1,,,,,,,,, -L20,,IOBM,IO_L45P_A1_M1LDQS_1,UNUSED,,1,,,,,,,,, -L21,,,VCCO_1,,,1,,,,,any******,,,, -L22,,IOBS,IO_L45N_A0_M1LDQSN_1,UNUSED,,1,,,,,,,,, -M1,,IOBS,IO_L38N_M3DQ3_3,UNUSED,,3,,,,,,,,, -M2,,IOBM,IO_L38P_M3DQ2_3,UNUSED,,3,,,,,,,,, -M3,,IOBM,IO_L42P_GCLK25_TRDY2_M3UDM_3,UNUSED,,3,,,,,,,,, -M4,,IOBS,IO_L31N_VREF_3,UNUSED,,3,,,,,,,,, -M5,result<4>,IOB,IO_L31P_3,OUTPUT,LVCMOS25*,3,12,,,,,UNLOCATED,NO,NONE, -M6,result<3>,IOB,IO_L25P_3,OUTPUT,LVCMOS25*,3,12,,,,,UNLOCATED,NO,NONE, -M7,reset,IOB,IO_L23P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE, -M8,result<2>,IOB,IO_L23N_3,OUTPUT,LVCMOS25*,3,12,,,,,UNLOCATED,NO,NONE, -M9,,,VCCINT,,,,,,,,1.2,,,, -M10,,,GND,,,,,,,,,,,, -M11,,,VCCINT,,,,,,,,1.2,,,, -M12,,,GND,,,,,,,,,,,, -M13,,,VCCINT,,,,,,,,1.2,,,, -M14,,,GND,,,,,,,,,,,, -M15,,,VCCAUX,,,,,,,,2.5,,,, -M16,,IOBM,IO_L58P_1,UNUSED,,1,,,,,,,,, -M17,,IOBM,IO_L71P_1,UNUSED,,1,,,,,,,,, -M18,,IOBS,IO_L71N_1,UNUSED,,1,,,,,,,,, -M19,,IOBM,IO_L53P_1,UNUSED,,1,,,,,,,,, -M20,,IOBM,IO_L42P_GCLK7_M1UDM_1,UNUSED,,1,,,,,,,,, -M21,,IOBM,IO_L46P_FCS_B_M1DQ2_1,UNUSED,,1,,,,,,,,, -M22,,IOBS,IO_L46N_FOE_B_M1DQ3_1,UNUSED,,1,,,,,,,,, -N1,,IOBS,IO_L37N_M3DQ1_3,UNUSED,,3,,,,,,,,, -N2,,,GND,,,,,,,,,,,, -N3,,IOBM,IO_L37P_M3DQ0_3,UNUSED,,3,,,,,,,,, -N4,result<6>,IOB,IO_L26N_3,OUTPUT,LVCMOS25*,3,12,,,,,UNLOCATED,NO,NONE, -N5,,,VCCO_3,,,3,,,,,2.50,,,, -N6,,IOBM,IO_L11P_3,UNUSED,,3,,,,,,,,, -N7,,IOBS,IO_L11N_3,UNUSED,,3,,,,,,,,, -N8,,,VCCAUX,,,,,,,,2.5,,,, -N9,,,GND,,,,,,,,,,,, -N10,,,VCCINT,,,,,,,,1.2,,,, -N11,,,GND,,,,,,,,,,,, -N12,,,VCCINT,,,,,,,,1.2,,,, -N13,,,GND,,,,,,,,,,,, -N14,,,VCCINT,,,,,,,,1.2,,,, -N15,,,SUSPEND,,,,,,,,,,,, -N16,,IOBS,IO_L72N_1,UNUSED,,1,,,,,,,,, -N17,,,GND,,,,,,,,,,,, -N18,,,VCCO_1,,,1,,,,,any******,,,, -N19,,IOBS,IO_L53N_VREF_1,UNUSED,,1,,,,,,,,, -N20,,IOBM,IO_L47P_FWE_B_M1DQ0_1,UNUSED,,1,,,,,,,,, -N21,,,GND,,,,,,,,,,,, -N22,,IOBS,IO_L47N_LDC_M1DQ1_1,UNUSED,,1,,,,,,,,, -P1,result<5>,IOB,IO_L36N_M3DQ9_3,OUTPUT,LVCMOS25*,3,12,,,,,UNLOCATED,NO,NONE, -P2,,IOBM,IO_L36P_M3DQ8_3,UNUSED,,3,,,,,,,,, -P3,,IOBM,IO_L26P_3,UNUSED,,3,,,,,,,,, -P4,result<0>,IOB,IO_L24N_3,OUTPUT,LVCMOS25*,3,12,,,,,UNLOCATED,NO,NONE, -P5,,IOBS,IO_L8N_3,UNUSED,,3,,,,,,,,, -P6,,IOBM,IO_L8P_3,UNUSED,,3,,,,,,,,, -P7,,IOBS,IO_L7N_3,UNUSED,,3,,,,,,,,, -P8,,IOBM,IO_L7P_3,UNUSED,,3,,,,,,,,, -P9,,,VCCINT,,,,,,,,1.2,,,, -P10,,,GND,,,,,,,,,,,, -P11,,,VCCINT,,,,,,,,1.2,,,, -P12,,,GND,,,,,,,,,,,, -P13,,,VCCINT,,,,,,,,1.2,,,, -P14,,,GND,,,,,,,,,,,, -P15,,,RFUSE,,,,,,,,,,,, -P16,,,VFS,,,,,,,,,,,, -P17,,IOBM,IO_L72P_1,UNUSED,,1,,,,,,,,, -P18,,IOBM,IO_L73P_1,UNUSED,,1,,,,,,,,, -P19,,IOBM,IO_L59P_1,UNUSED,,1,,,,,,,,, -P20,,IOBS,IO_L59N_1,UNUSED,,1,,,,,,,,, -P21,,IOBM,IO_L48P_HDC_M1DQ8_1,UNUSED,,1,,,,,,,,, -P22,,IOBS,IO_L48N_M1DQ9_1,UNUSED,,1,,,,,,,,, -R1,,IOBS,IO_L35N_M3DQ11_3,UNUSED,,3,,,,,,,,, -R2,,,VCCO_3,,,3,,,,,2.50,,,, -R3,,IOBM,IO_L35P_M3DQ10_3,UNUSED,,3,,,,,,,,, -R4,,IOBM,IO_L24P_3,UNUSED,,3,,,,,,,,, -R5,,,GND,,,,,,,,,,,, -R6,,,VCCAUX,,,,,,,,2.5,,,, -R7,,IOBS,IO_L60N_2,UNUSED,,2,,,,,,,,, -R8,,IOBS,IO_L59N_2,UNUSED,,2,,,,,,,,, -R9,,IOBM,IO_L59P_2,UNUSED,,2,,,,,,,,, -R10,,,VCCAUX,,,,,,,,2.5,,,, -R11,,IOBM,IO_L40P_2,UNUSED,,2,,,,,,,,, -R12,,,VCCAUX,,,,,,,,2.5,,,, -R13,,IOBS,IO_L23N_2,UNUSED,,2,,,,,,,,, -R14,,,VCCINT,,,,,,,,1.2,,,, -R15,,IOBS,IO_L10N_2,UNUSED,,2,,,,,,,,, -R16,,IOBM,IO_L10P_2,UNUSED,,2,,,,,,,,, -R17,,,VBATT,,,,,,,,,,,, -R18,,,GND,,,,,,,,,,,, -R19,,IOBS,IO_L73N_1,UNUSED,,1,,,,,,,,, -R20,,IOBM,IO_L49P_M1DQ10_1,UNUSED,,1,,,,,,,,, -R21,,,VCCO_1,,,1,,,,,any******,,,, -R22,,IOBS,IO_L49N_M1DQ11_1,UNUSED,,1,,,,,,,,, -T1,result<1>,IOB,IO_L34N_M3UDQSN_3,OUTPUT,LVCMOS25*,3,12,,,,,UNLOCATED,NO,NONE, -T2,,IOBM,IO_L34P_M3UDQS_3,UNUSED,,3,,,,,,,,, -T3,,IOBS,IO_L9N_3,UNUSED,,3,,,,,,,,, -T4,,IOBM,IO_L9P_3,UNUSED,,3,,,,,,,,, -T5,,IOBS,IO_L65N_CSO_B_2,UNUSED,,2,,,,,,,,, -T6,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,, -T7,,IOBM,IO_L60P_2,UNUSED,,2,,,,,,,,, -T8,,,NC,,,,,,,,,,,, -T9,,,VCCO_2,,,2,,,,,any******,,,, -T10,,,NC,,,,,,,,,,,, -T11,,IOBS,IO_L40N_2,UNUSED,,2,,,,,,,,, -T12,,,NC,,,,,,,,,,,, -T13,,,VCCO_2,,,2,,,,,any******,,,, -T14,,IOBM,IO_L23P_2,UNUSED,,2,,,,,,,,, -T15,,IOBS,IO_L7N_2,UNUSED,,2,,,,,,,,, -T16,,IOBM,IO_L7P_2,UNUSED,,2,,,,,,,,, -T17,,IOBS,IO_L4N_VREF_2,UNUSED,,2,,,,,,,,, -T18,,IOBM,IO_L4P_2,UNUSED,,2,,,,,,,,, -T19,,IOBM,IO_L74P_AWAKE_1,UNUSED,,1,,,,,,,,, -T20,,IOBS,IO_L74N_DOUT_BUSY_1,UNUSED,,1,,,,,,,,, -T21,,IOBM,IO_L50P_M1UDQS_1,UNUSED,,1,,,,,,,,, -T22,,IOBS,IO_L50N_M1UDQSN_1,UNUSED,,1,,,,,,,,, -U1,,IOBS,IO_L33N_M3DQ13_3,UNUSED,,3,,,,,,,,, -U2,,,GND,,,,,,,,,,,, -U3,,IOBM,IO_L33P_M3DQ12_3,UNUSED,,3,,,,,,,,, -U4,,IOBM,IO_L10P_3,UNUSED,,3,,,,,,,,, -U5,,,VCCO_3,,,3,,,,,2.50,,,, -U6,,IOBM,IO_L63P_2,UNUSED,,2,,,,,,,,, -U7,,,GND,,,,,,,,,,,, -U8,,,NC,,,,,,,,,,,, -U9,,IOBM,IO_L50P_2,UNUSED,,2,,,,,,,,, -U10,,,NC,,,,,,,,,,,, -U11,,,VCCAUX,,,,,,,,2.5,,,, -U12,,,NC,,,,,,,,,,,, -U13,,IOBS,IO_L12N_D2_MISO3_2,UNUSED,,2,,,,,,,,, -U14,,IOBM,IO_L12P_D1_MISO2_2,UNUSED,,2,,,,,,,,, -U15,,IOBM,IO_L13P_M1_2,UNUSED,,2,,,,,,,,, -U16,,IOBS,IO_L8N_2,UNUSED,,2,,,,,,,,, -U17,,IOBM,IO_L8P_2,UNUSED,,2,,,,,,,,, -U18,,,VCCO_1,,,1,,,,,any******,,,, -U19,,IOBM,IO_L70P_1,UNUSED,,1,,,,,,,,, -U20,,IOBM,IO_L51P_M1DQ12_1,UNUSED,,1,,,,,,,,, -U21,,,GND,,,,,,,,,,,, -U22,,IOBS,IO_L51N_M1DQ13_1,UNUSED,,1,,,,,,,,, -V1,,IOBS,IO_L32N_M3DQ15_3,UNUSED,,3,,,,,,,,, -V2,,IOBM,IO_L32P_M3DQ14_3,UNUSED,,3,,,,,,,,, -V3,,IOBS,IO_L10N_3,UNUSED,,3,,,,,,,,, -V4,,,GND,,,,,,,,,,,, -V5,,IOBS,IO_L63N_2,UNUSED,,2,,,,,,,,, -V6,,,VCCAUX,,,,,,,,2.5,,,, -V7,,IOBS,IO_L46N_2,UNUSED,,2,,,,,,,,, -V8,,,VCCO_2,,,2,,,,,any******,,,, -V9,,IOBS,IO_L50N_2,UNUSED,,2,,,,,,,,, -V10,,,GND,,,,,,,,,,,, -V11,,IOBM,IO_L42P_2,UNUSED,,2,,,,,,,,, -V12,,,VCCO_2,,,2,,,,,any******,,,, -V13,,IOBM,IO_L18P_2,UNUSED,,2,,,,,,,,, -V14,,,GND,,,,,,,,,,,, -V15,,IOBS,IO_L13N_D10_2,UNUSED,,2,,,,,,,,, -V16,,,VCCO_2,,,2,,,,,any******,,,, -V17,,IOBM,IO_L11P_2,UNUSED,,2,,,,,,,,, -V18,,IOBS,IO_L9N_2,UNUSED,,2,,,,,,,,, -V19,,IOBM,IO_L9P_2,UNUSED,,2,,,,,,,,, -V20,,IOBS,IO_L70N_1,UNUSED,,1,,,,,,,,, -V21,,IOBM,IO_L52P_M1DQ14_1,UNUSED,,1,,,,,,,,, -V22,,IOBS,IO_L52N_M1DQ15_1,UNUSED,,1,,,,,,,,, -W1,,IOBS,IO_L2N_3,UNUSED,,3,,,,,,,,, -W2,,,VCCO_3,,,3,,,,,2.50,,,, -W3,,IOBM,IO_L2P_3,UNUSED,,3,,,,,,,,, -W4,,IOBM,IO_L62P_D5_2,UNUSED,,2,,,,,,,,, -W5,,,VCCO_2,,,2,,,,,any******,,,, -W6,,,NC,,,,,,,,,,,, -W7,,,GND,,,,,,,,,,,, -W8,,IOBM,IO_L46P_2,UNUSED,,2,,,,,,,,, -W9,,IOBM,IO_L47P_2,UNUSED,,2,,,,,,,,, -W10,,IOBM,IO_L44P_2,UNUSED,,2,,,,,,,,, -W11,,IOBS,IO_L42N_2,UNUSED,,2,,,,,,,,, -W12,,IOBM,IO_L29P_GCLK3_2,UNUSED,,2,,,,,,,,, -W13,,IOBS,IO_L18N_2,UNUSED,,2,,,,,,,,, -W14,,IOBM,IO_L20P_2,UNUSED,,2,,,,,,,,, -W15,,,NC,,,,,,,,,,,, -W16,,,GND,,,,,,,,,,,, -W17,,IOBS,IO_L11N_2,UNUSED,,2,,,,,,,,, -W18,,IOBM,IO_L6P_2,UNUSED,,2,,,,,,,,, -W19,,,GND,,,,,,,,,,,, -W20,,IOBM,IO_L60P_1,UNUSED,,1,,,,,,,,, -W21,,,VCCO_1,,,1,,,,,any******,,,, -W22,,IOBS,IO_L60N_1,UNUSED,,1,,,,,,,,, -Y1,,IOBS,IO_L1N_VREF_3,UNUSED,,3,,,,,,,,, -Y2,,IOBM,IO_L1P_3,UNUSED,,3,,,,,,,,, -Y3,,IOBM,IO_L58P_2,UNUSED,,2,,,,,,,,, -Y4,,IOBS,IO_L62N_D6_2,UNUSED,,2,,,,,,,,, -Y5,,,NC,,,,,,,,,,,, -Y6,,,NC,,,,,,,,,,,, -Y7,,IOBM,IO_L48P_D7_2,UNUSED,,2,,,,,,,,, -Y8,,IOBS,IO_L47N_2,UNUSED,,2,,,,,,,,, -Y9,,IOBM,IO_L43P_2,UNUSED,,2,,,,,,,,, -Y10,,IOBS,IO_L44N_2,UNUSED,,2,,,,,,,,, -Y11,,IOBM,IO_L32P_GCLK29_2,UNUSED,,2,,,,,,,,, -Y12,,IOBS,IO_L29N_GCLK2_2,UNUSED,,2,,,,,,,,, -Y13,,IOBM,IO_L30P_GCLK1_D13_2,UNUSED,,2,,,,,,,,, -Y14,,IOBS,IO_L20N_2,UNUSED,,2,,,,,,,,, -Y15,,IOBM,IO_L21P_2,UNUSED,,2,,,,,,,,, -Y16,,,NC,,,,,,,,,,,, -Y17,,IOBM,IO_L15P_2,UNUSED,,2,,,,,,,,, -Y18,,IOBS,IO_L6N_2,UNUSED,,2,,,,,,,,, -Y19,,IOBM,IO_L5P_2,UNUSED,,2,,,,,,,,, -Y20,,,CMPCS_B_2,,,,,,,,,,,, -Y21,,IOBM,IO_L1P_CCLK_2,UNUSED,,2,,,,,,,,, -Y22,,,DONE_2,,,,,,,,,,,, - -# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, -# -#* Default value. -#** This default Pullup/Pulldown value can be overridden in Bitgen. -#****** Special VCCO requirements may apply. Please consult the device -# family datasheet for specific guideline on VCCO requirements. -# -# -# Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_pad.txt =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_pad.txt (revision 17) +++ (revision ) @@ -1,514 +1,0 @@ -Release 12.3 - par M.70d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -Tue Aug 14 16:11:52 2012 - - -INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: -1. The _pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. -2. The _pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. -3. The .pad file designed for parsing by customers. It uses the "|" as a data field separator. - -INPUT FILE: MultiMPITest_map.ncd -OUTPUT FILE: MultiMPITest_pad.txt -PART TYPE: xc6slx100 -SPEED GRADE: -3 -PACKAGE: fgg484 - -Pinout by Pin Number: - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity| -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -|A1 | | |GND | | | | | | | | | | | | -|A2 | |IOBM |IO_L83P_3 |UNUSED | |3 | | | | | | | | | -|A3 | |IOBM |IO_L1P_HSWAPEN_0 |UNUSED | |0 | | | | | | | | | -|A4 | |IOBS |IO_L1N_VREF_0 |UNUSED | |0 | | | | | | | | | -|A5 | |IOBS |IO_L2N_0 |UNUSED | |0 | | | | | | | | | -|A6 | |IOBS |IO_L4N_0 |UNUSED | |0 | | | | | | | | | -|A7 | |IOBS |IO_L5N_0 |UNUSED | |0 | | | | | | | | | -|A8 | |IOBS |IO_L6N_0 |UNUSED | |0 | | | | | | | | | -|A9 | |IOBS |IO_L8N_VREF_0 |UNUSED | |0 | | | | | | | | | -|A10 | |IOBS |IO_L34N_GCLK18_0 |UNUSED | |0 | | | | | | | | | -|A11 | |IOBS |IO_L35N_GCLK16_0 |UNUSED | |0 | | | | | | | | | -|A12 | |IOBS |IO_L37N_GCLK12_0 |UNUSED | |0 | | | | | | | | | -|A13 | |IOBS |IO_L38N_VREF_0 |UNUSED | |0 | | | | | | | | | -|A14 | |IOBS |IO_L50N_0 |UNUSED | |0 | | | | | | | | | -|A15 | |IOBS |IO_L51N_0 |UNUSED | |0 | | | | | | | | | -|A16 | |IOBS |IO_L63N_SCP6_0 |UNUSED | |0 | | | | | | | | | -|A17 | |IOBS |IO_L64N_SCP4_0 |UNUSED | |0 | | | | | | | | | -|A18 | |IOBS |IO_L65N_SCP2_0 |UNUSED | |0 | | | | | | | | | -|A19 | | |TDO | | | | | | | | | | | | -|A20 | |IOBM |IO_L20P_1 |UNUSED | |1 | | | | | | | | | -|A21 | |IOBS |IO_L20N_1 |UNUSED | |1 | | | | | | | | | -|A22 | | |GND | | | | | | | | | | | | -|AA1 | | |PROGRAM_B_2 | | | | | | | | | | | | -|AA2 | |IOBM |IO_L64P_D8_2 |UNUSED | |2 | | | | | | | | | -|AA3 | | |VCCO_2 | | |2 | | | | |any******| | | | -|AA4 | |IOBM |IO_L57P_2 |UNUSED | |2 | | | | | | | | | -|AA5 | | |GND | | | | | | | | | | | | -|AA6 | |IOBM |IO_L49P_D3_2 |UNUSED | |2 | | | | | | | | | -|AA7 | | |VCCO_2 | | |2 | | | | |any******| | | | -|AA8 | |IOBM |IO_L45P_2 |UNUSED | |2 | | | | | | | | | -|AA9 | | |GND | | | | | | | | | | | | -|AA10 | |IOBM |IO_L41P_2 |UNUSED | |2 | | | | | | | | | -|AA11 | | |VCCO_2 | | |2 | | | | |any******| | | | -|AA12 | |IOBM |IO_L31P_GCLK31_D14_2 |UNUSED | |2 | | | | | | | | | -|AA13 | | |GND | | | | | | | | | | | | -|AA14 | |IOBM |IO_L16P_2 |UNUSED | |2 | | | | | | | | | -|AA15 | | |VCCO_2 | | |2 | | | | |any******| | | | -|AA16 | |IOBM |IO_L19P_2 |UNUSED | |2 | | | | | | | | | -|AA17 | | |GND | | | | | | | | | | | | -|AA18 | |IOBM |IO_L14P_D11_2 |UNUSED | |2 | | | | | | | | | -|AA19 | | |VCCO_2 | | |2 | | | | |any******| | | | -|AA20 | |IOBM |IO_L3P_D0_DIN_MISO_MISO1_2 |UNUSED | |2 | | | | | | | | | -|AA21 | |IOBM |IO_L2P_CMPCLK_2 |UNUSED | |2 | | | | | | | | | -|AA22 | |IOBS |IO_L1N_M0_CMPMISO_2 |UNUSED | |2 | | | | | | | | | -|AB1 | | |GND | | | | | | | | | | | | -|AB2 | |IOBS |IO_L64N_D9_2 |UNUSED | |2 | | | | | | | | | -|AB3 | |IOBS |IO_L58N_2 |UNUSED | |2 | | | | | | | | | -|AB4 | |IOBS |IO_L57N_2 |UNUSED | |2 | | | | | | | | | -|AB5 | | |NC | | | | | | | | | | | | -|AB6 | |IOBS |IO_L49N_D4_2 |UNUSED | |2 | | | | | | | | | -|AB7 | |IOBS |IO_L48N_RDWR_B_VREF_2 |UNUSED | |2 | | | | | | | | | -|AB8 | |IOBS |IO_L45N_2 |UNUSED | |2 | | | | | | | | | -|AB9 | |IOBS |IO_L43N_2 |UNUSED | |2 | | | | | | | | | -|AB10 | |IOBS |IO_L41N_VREF_2 |UNUSED | |2 | | | | | | | | | -|AB11 | |IOBS |IO_L32N_GCLK28_2 |UNUSED | |2 | | | | | | | | | -|AB12 | |IOBS |IO_L31N_GCLK30_D15_2 |UNUSED | |2 | | | | | | | | | -|AB13 | |IOBS |IO_L30N_GCLK0_USERCCLK_2 |UNUSED | |2 | | | | | | | | | -|AB14 | |IOBS |IO_L16N_VREF_2 |UNUSED | |2 | | | | | | | | | -|AB15 | |IOBS |IO_L21N_2 |UNUSED | |2 | | | | | | | | | -|AB16 | |IOBS |IO_L19N_2 |UNUSED | |2 | | | | | | | | | -|AB17 | |IOBS |IO_L15N_2 |UNUSED | |2 | | | | | | | | | -|AB18 | |IOBS |IO_L14N_D12_2 |UNUSED | |2 | | | | | | | | | -|AB19 | |IOBS |IO_L5N_2 |UNUSED | |2 | | | | | | | | | -|AB20 | |IOBS |IO_L3N_MOSI_CSI_B_MISO0_2 |UNUSED | |2 | | | | | | | | | -|AB21 | |IOBS |IO_L2N_CMPMOSI_2 |UNUSED | |2 | | | | | | | | | -|AB22 | | |GND | | | | | | | | | | | | -|B1 | |IOBS |IO_L60N_3 |UNUSED | |3 | | | | | | | | | -|B2 | |IOBM |IO_L60P_3 |UNUSED | |3 | | | | | | | | | -|B3 | |IOBS |IO_L83N_VREF_3 |UNUSED | |3 | | | | | | | | | -|B4 | | |VCCO_0 | | |0 | | | | |any******| | | | -|B5 | | |GND | | | | | | | | | | | | -|B6 | |IOBM |IO_L4P_0 |UNUSED | |0 | | | | | | | | | -|B7 | | |VCCO_0 | | |0 | | | | |any******| | | | -|B8 | |IOBM |IO_L6P_0 |UNUSED | |0 | | | | | | | | | -|B9 | | |GND | | | | | | | | | | | | -|B10 | |IOBM |IO_L34P_GCLK19_0 |UNUSED | |0 | | | | | | | | | -|B11 | | |VCCO_0 | | |0 | | | | |any******| | | | -|B12 | |IOBM |IO_L37P_GCLK13_0 |UNUSED | |0 | | | | | | | | | -|B13 | | |GND | | | | | | | | | | | | -|B14 | |IOBM |IO_L50P_0 |UNUSED | |0 | | | | | | | | | -|B15 | | |VCCO_0 | | |0 | | | | |any******| | | | -|B16 | |IOBM |IO_L63P_SCP7_0 |UNUSED | |0 | | | | | | | | | -|B17 | | |GND | | | | | | | | | | | | -|B18 | |IOBM |IO_L65P_SCP3_0 |UNUSED | |0 | | | | | | | | | -|B19 | | |VCCO_0 | | |0 | | | | |any******| | | | -|B20 | |IOBS |IO_L1N_A24_VREF_1 |UNUSED | |1 | | | | | | | | | -|B21 | |IOBM |IO_L19P_1 |UNUSED | |1 | | | | | | | | | -|B22 | |IOBS |IO_L19N_1 |UNUSED | |1 | | | | | | | | | -|C1 | |IOBS |IO_L54N_M3A11_3 |UNUSED | |3 | | | | | | | | | -|C2 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|C3 | |IOBM |IO_L54P_M3RESET_3 |UNUSED | |3 | | | | | | | | | -|C4 | |IOBS |IO_L81N_3 |UNUSED | |3 | | | | | | | | | -|C5 | |IOBM |IO_L2P_0 |UNUSED | |0 | | | | | | | | | -|C6 | |IOBS |IO_L3N_0 |UNUSED | |0 | | | | | | | | | -|C7 | |IOBM |IO_L5P_0 |UNUSED | |0 | | | | | | | | | -|C8 | |IOBS |IO_L7N_0 |UNUSED | |0 | | | | | | | | | -|C9 | |IOBM |IO_L8P_0 |UNUSED | |0 | | | | | | | | | -|C10 | |IOBS |IO_L33N_0 |UNUSED | |0 | | | | | | | | | -|C11 | |IOBM |IO_L35P_GCLK17_0 |UNUSED | |0 | | | | | | | | | -|C12 | |IOBS |IO_L36N_GCLK14_0 |UNUSED | |0 | | | | | | | | | -|C13 | |IOBM |IO_L38P_0 |UNUSED | |0 | | | | | | | | | -|C14 | |IOBS |IO_L49N_0 |UNUSED | |0 | | | | | | | | | -|C15 | |IOBM |IO_L51P_0 |UNUSED | |0 | | | | | | | | | -|C16 | |IOBS |IO_L62N_VREF_0 |UNUSED | |0 | | | | | | | | | -|C17 | |IOBM |IO_L64P_SCP5_0 |UNUSED | |0 | | | | | | | | | -|C18 | | |TMS | | | | | | | | | | | | -|C19 | |IOBM |IO_L1P_A25_1 |UNUSED | |1 | | | | | | | | | -|C20 | |IOBM |IO_L32P_A17_M1A8_1 |UNUSED | |1 | | | | | | | | | -|C21 | | |VCCO_1 | | |1 | | | | |any******| | | | -|C22 | |IOBS |IO_L32N_A16_M1A9_1 |UNUSED | |1 | | | | | | | | | -|D1 | |IOBS |IO_L53N_M3A12_3 |UNUSED | |3 | | | | | | | | | -|D2 | |IOBM |IO_L53P_M3CKE_3 |UNUSED | |3 | | | | | | | | | -|D3 | |IOBM |IO_L81P_3 |UNUSED | |3 | | | | | | | | | -|D4 | | |GND | | | | | | | | | | | | -|D5 | |IOBM |IO_L58P_3 |UNUSED | |3 | | | | | | | | | -|D6 | |IOBM |IO_L3P_0 |UNUSED | |0 | | | | | | | | | -|D7 | |IOBM |IO_L32P_0 |UNUSED | |0 | | | | | | | | | -|D8 | |IOBS |IO_L32N_0 |UNUSED | |0 | | | | | | | | | -|D9 | |IOBM |IO_L7P_0 |UNUSED | |0 | | | | | | | | | -|D10 | |IOBM |IO_L33P_0 |UNUSED | |0 | | | | | | | | | -|D11 | |IOBM |IO_L36P_GCLK15_0 |UNUSED | |0 | | | | | | | | | -|D12 | |IOBS |IO_L43N_0 |UNUSED | |0 | | | | | | | | | -|D13 | |IOBS |IO_L45N_0 |UNUSED | |0 | | | | | | | | | -|D14 | |IOBM |IO_L49P_0 |UNUSED | |0 | | | | | | | | | -|D15 | |IOBM |IO_L62P_0 |UNUSED | |0 | | | | | | | | | -|D16 | | |VCCAUX | | | | | | | |2.5 | | | | -|D17 | |IOBS |IO_L66N_SCP0_0 |UNUSED | |0 | | | | | | | | | -|D18 | | |GND | | | | | | | | | | | | -|D19 | |IOBM |IO_L29P_A23_M1A13_1 |UNUSED | |1 | | | | | | | | | -|D20 | |IOBS |IO_L29N_A22_M1A14_1 |UNUSED | |1 | | | | | | | | | -|D21 | |IOBM |IO_L31P_A19_M1CKE_1 |UNUSED | |1 | | | | | | | | | -|D22 | |IOBS |IO_L31N_A18_M1A12_1 |UNUSED | |1 | | | | | | | | | -|E1 | |IOBS |IO_L52N_M3A9_3 |UNUSED | |3 | | | | | | | | | -|E2 | | |GND | | | | | | | | | | | | -|E3 | |IOBM |IO_L52P_M3A8_3 |UNUSED | |3 | | | | | | | | | -|E4 | |IOBS |IO_L58N_3 |UNUSED | |3 | | | | | | | | | -|E5 | |IOBM |IO_L82P_3 |UNUSED | |3 | | | | | | | | | -|E6 | |IOBS |IO_L82N_3 |UNUSED | |3 | | | | | | | | | -|E7 | | |GND | | | | | | | | | | | | -|E8 | |IOBM |IO_L14P_0 |UNUSED | |0 | | | | | | | | | -|E9 | | |VCCO_0 | | |0 | | | | |any******| | | | -|E10 | |IOBM |IO_L17P_0 |UNUSED | |0 | | | | | | | | | -|E11 | | |GND | | | | | | | | | | | | -|E12 | |IOBM |IO_L43P_0 |UNUSED | |0 | | | | | | | | | -|E13 | | |VCCO_0 | | |0 | | | | |any******| | | | -|E14 | |IOBM |IO_L47P_0 |UNUSED | |0 | | | | | | | | | -|E15 | | |GND | | | | | | | | | | | | -|E16 | |IOBM |IO_L66P_SCP1_0 |UNUSED | |0 | | | | | | | | | -|E17 | | |VCCO_0 | | |0 | | | | |any******| | | | -|E18 | | |TDI | | | | | | | | | | | | -|E19 | | |VCCO_1 | | |1 | | | | |any******| | | | -|E20 | |IOBM |IO_L35P_A11_M1A7_1 |UNUSED | |1 | | | | | | | | | -|E21 | | |GND | | | | | | | | | | | | -|E22 | |IOBS |IO_L35N_A10_M1A2_1 |UNUSED | |1 | | | | | | | | | -|F1 | |IOBS |IO_L50N_M3BA2_3 |UNUSED | |3 | | | | | | | | | -|F2 | |IOBM |IO_L50P_M3WE_3 |UNUSED | |3 | | | | | | | | | -|F3 | |IOBS |IO_L51N_M3A4_3 |UNUSED | |3 | | | | | | | | | -|F4 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|F5 | |IOBS |IO_L55N_M3A14_3 |UNUSED | |3 | | | | | | | | | -|F6 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|F7 | |IOBS |IO_L80N_3 |UNUSED | |3 | | | | | | | | | -|F8 | |IOBS |IO_L14N_0 |UNUSED | |0 | | | | | | | | | -|F9 | |IOBS |IO_L15N_0 |UNUSED | |0 | | | | | | | | | -|F10 | |IOBS |IO_L17N_0 |UNUSED | |0 | | | | | | | | | -|F11 | | |VCCAUX | | | | | | | |2.5 | | | | -|F12 | |IOBS |IO_L44N_0 |UNUSED | |0 | | | | | | | | | -|F13 | |IOBM |IO_L45P_0 |UNUSED | |0 | | | | | | | | | -|F14 | |IOBM |IO_L48P_0 |UNUSED | |0 | | | | | | | | | -|F15 | |IOBS |IO_L47N_0 |UNUSED | |0 | | | | | | | | | -|F16 | |IOBM |IO_L10P_1 |UNUSED | |1 | | | | | | | | | -|F17 | |IOBS |IO_L10N_1 |UNUSED | |1 | | | | | | | | | -|F18 | |IOBM |IO_L30P_A21_M1RESET_1 |UNUSED | |1 | | | | | | | | | -|F19 | |IOBS |IO_L30N_A20_M1A11_1 |UNUSED | |1 | | | | | | | | | -|F20 | |IOBS |IO_L33N_A14_M1A4_1 |UNUSED | |1 | | | | | | | | | -|F21 | |IOBM |IO_L37P_A7_M1A0_1 |UNUSED | |1 | | | | | | | | | -|F22 | |IOBS |IO_L37N_A6_M1A1_1 |UNUSED | |1 | | | | | | | | | -|G1 | |IOBS |IO_L48N_M3BA1_3 |UNUSED | |3 | | | | | | | | | -|G2 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|G3 | |IOBM |IO_L48P_M3BA0_3 |UNUSED | |3 | | | | | | | | | -|G4 | |IOBM |IO_L51P_M3A10_3 |UNUSED | |3 | | | | | | | | | -|G5 | | |GND | | | | | | | | | | | | -|G6 | |IOBM |IO_L55P_M3A13_3 |UNUSED | |3 | | | | | | | | | -|G7 | |IOBM |IO_L80P_3 |UNUSED | |3 | | | | | | | | | -|G8 | |IOBM |IO_L15P_0 |UNUSED | |0 | | | | | | | | | -|G9 | |IOBM |IO_L16P_0 |UNUSED | |0 | | | | | | | | | -|G10 | | |VCCO_0 | | |0 | | | | |any******| | | | -|G11 | |IOBM |IO_L18P_0 |UNUSED | |0 | | | | | | | | | -|G12 | | |VCCAUX | | | | | | | |2.5 | | | | -|G13 | |IOBS |IO_L46N_0 |UNUSED | |0 | | | | | | | | | -|G14 | | |VCCO_0 | | |0 | | | | |any******| | | | -|G15 | | |TCK | | | | | | | | | | | | -|G16 | |IOBM |IO_L9P_1 |UNUSED | |1 | | | | | | | | | -|G17 | |IOBS |IO_L9N_1 |UNUSED | |1 | | | | | | | | | -|G18 | | |GND | | | | | | | | | | | | -|G19 | |IOBM |IO_L33P_A15_M1A10_1 |UNUSED | |1 | | | | | | | | | -|G20 | |IOBM |IO_L39P_M1A3_1 |UNUSED | |1 | | | | | | | | | -|G21 | | |VCCO_1 | | |1 | | | | |any******| | | | -|G22 | |IOBS |IO_L39N_M1ODT_1 |UNUSED | |1 | | | | | | | | | -|H1 | |IOBS |IO_L47N_M3A1_3 |UNUSED | |3 | | | | | | | | | -|H2 | |IOBM |IO_L47P_M3A0_3 |UNUSED | |3 | | | | | | | | | -|H3 | |IOBS |IO_L46N_M3CLKN_3 |UNUSED | |3 | | | | | | | | | -|H4 | |IOBM |IO_L46P_M3CLK_3 |UNUSED | |3 | | | | | | | | | -|H5 | |IOBS |IO_L49N_M3A2_3 |UNUSED | |3 | | | | | | | | | -|H6 | |IOBM |IO_L49P_M3A7_3 |UNUSED | |3 | | | | | | | | | -|H7 | | |GND | | | | | | | | | | | | -|H8 | |IOBS |IO_L59N_3 |UNUSED | |3 | | | | | | | | | -|H9 | | |VCCAUX | | | | | | | |2.5 | | | | -|H10 | |IOBS |IO_L16N_0 |UNUSED | |0 | | | | | | | | | -|H11 | |IOBS |IO_L18N_0 |UNUSED | |0 | | | | | | | | | -|H12 | |IOBM |IO_L44P_0 |UNUSED | |0 | | | | | | | | | -|H13 | |IOBM |IO_L46P_0 |UNUSED | |0 | | | | | | | | | -|H14 | |IOBS |IO_L48N_0 |UNUSED | |0 | | | | | | | | | -|H15 | | |VCCAUX | | | | | | | |2.5 | | | | -|H16 | |IOBM |IO_L28P_1 |UNUSED | |1 | | | | | | | | | -|H17 | |IOBS |IO_L28N_VREF_1 |UNUSED | |1 | | | | | | | | | -|H18 | |IOBS |IO_L34N_A12_M1BA2_1 |UNUSED | |1 | | | | | | | | | -|H19 | |IOBM |IO_L34P_A13_M1WE_1 |UNUSED | |1 | | | | | | | | | -|H20 | |IOBM |IO_L38P_A5_M1CLK_1 |UNUSED | |1 | | | | | | | | | -|H21 | |IOBM |IO_L41P_GCLK9_IRDY1_M1RASN_1 |UNUSED | |1 | | | | | | | | | -|H22 | |IOBS |IO_L41N_GCLK8_M1CASN_1 |UNUSED | |1 | | | | | | | | | -|J1 | |IOBS |IO_L41N_GCLK26_M3DQ5_3 |UNUSED | |3 | | | | | | | | | -|J2 | | |GND | | | | | | | | | | | | -|J3 | |IOBM |IO_L41P_GCLK27_M3DQ4_3 |UNUSED | |3 | | | | | | | | | -|J4 | |IOBS |IO_L44N_GCLK20_M3A6_3 |UNUSED | |3 | | | | | | | | | -|J5 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|J6 | |IOBS |IO_L45N_M3ODT_3 |UNUSED | |3 | | | | | | | | | -|J7 | |IOBM |IO_L59P_3 |UNUSED | |3 | | | | | | | | | -|J8 | | |VCCINT | | | | | | | |1.2 | | | | -|J9 | | |GND | | | | | | | | | | | | -|J10 | | |VCCINT | | | | | | | |1.2 | | | | -|J11 | | |GND | | | | | | | | | | | | -|J12 | | |VCCINT | | | | | | | |1.2 | | | | -|J13 | | |GND | | | | | | | | | | | | -|J14 | | |VCCINT | | | | | | | |1.2 | | | | -|J15 | | |GND | | | | | | | | | | | | -|J16 | |IOBS |IO_L21N_1 |UNUSED | |1 | | | | | | | | | -|J17 | |IOBM |IO_L36P_A9_M1BA0_1 |UNUSED | |1 | | | | | | | | | -|J18 | | |VCCO_1 | | |1 | | | | |any******| | | | -|J19 | |IOBS |IO_L38N_A4_M1CLKN_1 |UNUSED | |1 | | | | | | | | | -|J20 | |IOBM |IO_L43P_GCLK5_M1DQ4_1 |UNUSED | |1 | | | | | | | | | -|J21 | | |GND | | | | | | | | | | | | -|J22 | |IOBS |IO_L43N_GCLK4_M1DQ5_1 |UNUSED | |1 | | | | | | | | | -|K1 | |IOBS |IO_L40N_M3DQ7_3 |UNUSED | |3 | | | | | | | | | -|K2 | |IOBM |IO_L40P_M3DQ6_3 |UNUSED | |3 | | | | | | | | | -|K3 | |IOBM |IO_L44P_GCLK21_M3A5_3 |UNUSED | |3 | | | | | | | | | -|K4 | |IOBS |IO_L43N_GCLK22_IRDY2_M3CASN_3|UNUSED | |3 | | | | | | | | | -|K5 | |IOBM |IO_L43P_GCLK23_M3RASN_3 |UNUSED | |3 | | | | | | | | | -|K6 | |IOBM |IO_L45P_M3A3_3 |UNUSED | |3 | | | | | | | | | -|K7 | |IOBM |IO_L57P_3 |UNUSED | |3 | | | | | | | | | -|K8 | |IOBS |IO_L57N_VREF_3 |UNUSED | |3 | | | | | | | | | -|K9 | | |VCCINT | | | | | | | |1.2 | | | | -|K10 | | |GND | | | | | | | | | | | | -|K11 | | |VCCINT | | | | | | | |1.2 | | | | -|K12 | | |GND | | | | | | | | | | | | -|K13 | | |VCCINT | | | | | | | |1.2 | | | | -|K14 | | |GND | | | | | | | | | | | | -|K15 | | |VCCAUX | | | | | | | |2.5 | | | | -|K16 | |IOBM |IO_L21P_1 |UNUSED | |1 | | | | | | | | | -|K17 | |IOBS |IO_L36N_A8_M1BA1_1 |UNUSED | |1 | | | | | | | | | -|K18 | |IOBS |IO_L61N_1 |UNUSED | |1 | | | | | | | | | -|K19 | |IOBS |IO_L40N_GCLK10_M1A6_1 |UNUSED | |1 | | | | | | | | | -|K20 | |IOBM |IO_L40P_GCLK11_M1A5_1 |UNUSED | |1 | | | | | | | | | -|K21 | |IOBM |IO_L44P_A3_M1DQ6_1 |UNUSED | |1 | | | | | | | | | -|K22 | |IOBS |IO_L44N_A2_M1DQ7_1 |UNUSED | |1 | | | | | | | | | -|L1 | |IOBS |IO_L39N_M3LDQSN_3 |UNUSED | |3 | | | | | | | | | -|L2 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|L3 | |IOBM |IO_L39P_M3LDQS_3 |UNUSED | |3 | | | | | | | | | -|L4 |clkm |IOB |IO_L42N_GCLK24_M3LDM_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE | -|L5 | | |GND | | | | | | | | | | | | -|L6 |result<7> |IOB |IO_L25N_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |UNLOCATED |NO |NONE | -|L7 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|L8 | | |VCCAUX | | | | | | | |2.5 | | | | -|L9 | | |GND | | | | | | | | | | | | -|L10 | | |VCCINT | | | | | | | |1.2 | | | | -|L11 | | |GND | | | | | | | | | | | | -|L12 | | |VCCINT | | | | | | | |1.2 | | | | -|L13 | | |GND | | | | | | | | | | | | -|L14 | | |VCCINT | | | | | | | |1.2 | | | | -|L15 | |IOBS |IO_L58N_1 |UNUSED | |1 | | | | | | | | | -|L16 | | |VCCO_1 | | |1 | | | | |any******| | | | -|L17 | |IOBM |IO_L61P_1 |UNUSED | |1 | | | | | | | | | -|L18 | | |GND | | | | | | | | | | | | -|L19 | |IOBS |IO_L42N_GCLK6_TRDY1_M1LDM_1 |UNUSED | |1 | | | | | | | | | -|L20 | |IOBM |IO_L45P_A1_M1LDQS_1 |UNUSED | |1 | | | | | | | | | -|L21 | | |VCCO_1 | | |1 | | | | |any******| | | | -|L22 | |IOBS |IO_L45N_A0_M1LDQSN_1 |UNUSED | |1 | | | | | | | | | -|M1 | |IOBS |IO_L38N_M3DQ3_3 |UNUSED | |3 | | | | | | | | | -|M2 | |IOBM |IO_L38P_M3DQ2_3 |UNUSED | |3 | | | | | | | | | -|M3 | |IOBM |IO_L42P_GCLK25_TRDY2_M3UDM_3 |UNUSED | |3 | | | | | | | | | -|M4 | |IOBS |IO_L31N_VREF_3 |UNUSED | |3 | | | | | | | | | -|M5 |result<4> |IOB |IO_L31P_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |UNLOCATED |NO |NONE | -|M6 |result<3> |IOB |IO_L25P_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |UNLOCATED |NO |NONE | -|M7 |reset |IOB |IO_L23P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE | -|M8 |result<2> |IOB |IO_L23N_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |UNLOCATED |NO |NONE | -|M9 | | |VCCINT | | | | | | | |1.2 | | | | -|M10 | | |GND | | | | | | | | | | | | -|M11 | | |VCCINT | | | | | | | |1.2 | | | | -|M12 | | |GND | | | | | | | | | | | | -|M13 | | |VCCINT | | | | | | | |1.2 | | | | -|M14 | | |GND | | | | | | | | | | | | -|M15 | | |VCCAUX | | | | | | | |2.5 | | | | -|M16 | |IOBM |IO_L58P_1 |UNUSED | |1 | | | | | | | | | -|M17 | |IOBM |IO_L71P_1 |UNUSED | |1 | | | | | | | | | -|M18 | |IOBS |IO_L71N_1 |UNUSED | |1 | | | | | | | | | -|M19 | |IOBM |IO_L53P_1 |UNUSED | |1 | | | | | | | | | -|M20 | |IOBM |IO_L42P_GCLK7_M1UDM_1 |UNUSED | |1 | | | | | | | | | -|M21 | |IOBM |IO_L46P_FCS_B_M1DQ2_1 |UNUSED | |1 | | | | | | | | | -|M22 | |IOBS |IO_L46N_FOE_B_M1DQ3_1 |UNUSED | |1 | | | | | | | | | -|N1 | |IOBS |IO_L37N_M3DQ1_3 |UNUSED | |3 | | | | | | | | | -|N2 | | |GND | | | | | | | | | | | | -|N3 | |IOBM |IO_L37P_M3DQ0_3 |UNUSED | |3 | | | | | | | | | -|N4 |result<6> |IOB |IO_L26N_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |UNLOCATED |NO |NONE | -|N5 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|N6 | |IOBM |IO_L11P_3 |UNUSED | |3 | | | | | | | | | -|N7 | |IOBS |IO_L11N_3 |UNUSED | |3 | | | | | | | | | -|N8 | | |VCCAUX | | | | | | | |2.5 | | | | -|N9 | | |GND | | | | | | | | | | | | -|N10 | | |VCCINT | | | | | | | |1.2 | | | | -|N11 | | |GND | | | | | | | | | | | | -|N12 | | |VCCINT | | | | | | | |1.2 | | | | -|N13 | | |GND | | | | | | | | | | | | -|N14 | | |VCCINT | | | | | | | |1.2 | | | | -|N15 | | |SUSPEND | | | | | | | | | | | | -|N16 | |IOBS |IO_L72N_1 |UNUSED | |1 | | | | | | | | | -|N17 | | |GND | | | | | | | | | | | | -|N18 | | |VCCO_1 | | |1 | | | | |any******| | | | -|N19 | |IOBS |IO_L53N_VREF_1 |UNUSED | |1 | | | | | | | | | -|N20 | |IOBM |IO_L47P_FWE_B_M1DQ0_1 |UNUSED | |1 | | | | | | | | | -|N21 | | |GND | | | | | | | | | | | | -|N22 | |IOBS |IO_L47N_LDC_M1DQ1_1 |UNUSED | |1 | | | | | | | | | -|P1 |result<5> |IOB |IO_L36N_M3DQ9_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |UNLOCATED |NO |NONE | -|P2 | |IOBM |IO_L36P_M3DQ8_3 |UNUSED | |3 | | | | | | | | | -|P3 | |IOBM |IO_L26P_3 |UNUSED | |3 | | | | | | | | | -|P4 |result<0> |IOB |IO_L24N_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |UNLOCATED |NO |NONE | -|P5 | |IOBS |IO_L8N_3 |UNUSED | |3 | | | | | | | | | -|P6 | |IOBM |IO_L8P_3 |UNUSED | |3 | | | | | | | | | -|P7 | |IOBS |IO_L7N_3 |UNUSED | |3 | | | | | | | | | -|P8 | |IOBM |IO_L7P_3 |UNUSED | |3 | | | | | | | | | -|P9 | | |VCCINT | | | | | | | |1.2 | | | | -|P10 | | |GND | | | | | | | | | | | | -|P11 | | |VCCINT | | | | | | | |1.2 | | | | -|P12 | | |GND | | | | | | | | | | | | -|P13 | | |VCCINT | | | | | | | |1.2 | | | | -|P14 | | |GND | | | | | | | | | | | | -|P15 | | |RFUSE | | | | | | | | | | | | -|P16 | | |VFS | | | | | | | | | | | | -|P17 | |IOBM |IO_L72P_1 |UNUSED | |1 | | | | | | | | | -|P18 | |IOBM |IO_L73P_1 |UNUSED | |1 | | | | | | | | | -|P19 | |IOBM |IO_L59P_1 |UNUSED | |1 | | | | | | | | | -|P20 | |IOBS |IO_L59N_1 |UNUSED | |1 | | | | | | | | | -|P21 | |IOBM |IO_L48P_HDC_M1DQ8_1 |UNUSED | |1 | | | | | | | | | -|P22 | |IOBS |IO_L48N_M1DQ9_1 |UNUSED | |1 | | | | | | | | | -|R1 | |IOBS |IO_L35N_M3DQ11_3 |UNUSED | |3 | | | | | | | | | -|R2 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|R3 | |IOBM |IO_L35P_M3DQ10_3 |UNUSED | |3 | | | | | | | | | -|R4 | |IOBM |IO_L24P_3 |UNUSED | |3 | | | | | | | | | -|R5 | | |GND | | | | | | | | | | | | -|R6 | | |VCCAUX | | | | | | | |2.5 | | | | -|R7 | |IOBS |IO_L60N_2 |UNUSED | |2 | | | | | | | | | -|R8 | |IOBS |IO_L59N_2 |UNUSED | |2 | | | | | | | | | -|R9 | |IOBM |IO_L59P_2 |UNUSED | |2 | | | | | | | | | -|R10 | | |VCCAUX | | | | | | | |2.5 | | | | -|R11 | |IOBM |IO_L40P_2 |UNUSED | |2 | | | | | | | | | -|R12 | | |VCCAUX | | | | | | | |2.5 | | | | -|R13 | |IOBS |IO_L23N_2 |UNUSED | |2 | | | | | | | | | -|R14 | | |VCCINT | | | | | | | |1.2 | | | | -|R15 | |IOBS |IO_L10N_2 |UNUSED | |2 | | | | | | | | | -|R16 | |IOBM |IO_L10P_2 |UNUSED | |2 | | | | | | | | | -|R17 | | |VBATT | | | | | | | | | | | | -|R18 | | |GND | | | | | | | | | | | | -|R19 | |IOBS |IO_L73N_1 |UNUSED | |1 | | | | | | | | | -|R20 | |IOBM |IO_L49P_M1DQ10_1 |UNUSED | |1 | | | | | | | | | -|R21 | | |VCCO_1 | | |1 | | | | |any******| | | | -|R22 | |IOBS |IO_L49N_M1DQ11_1 |UNUSED | |1 | | | | | | | | | -|T1 |result<1> |IOB |IO_L34N_M3UDQSN_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |UNLOCATED |NO |NONE | -|T2 | |IOBM |IO_L34P_M3UDQS_3 |UNUSED | |3 | | | | | | | | | -|T3 | |IOBS |IO_L9N_3 |UNUSED | |3 | | | | | | | | | -|T4 | |IOBM |IO_L9P_3 |UNUSED | |3 | | | | | | | | | -|T5 | |IOBS |IO_L65N_CSO_B_2 |UNUSED | |2 | | | | | | | | | -|T6 | |IOBM |IO_L65P_INIT_B_2 |UNUSED | |2 | | | | | | | | | -|T7 | |IOBM |IO_L60P_2 |UNUSED | |2 | | | | | | | | | -|T8 | | |NC | | | | | | | | | | | | -|T9 | | |VCCO_2 | | |2 | | | | |any******| | | | -|T10 | | |NC | | | | | | | | | | | | -|T11 | |IOBS |IO_L40N_2 |UNUSED | |2 | | | | | | | | | -|T12 | | |NC | | | | | | | | | | | | -|T13 | | |VCCO_2 | | |2 | | | | |any******| | | | -|T14 | |IOBM |IO_L23P_2 |UNUSED | |2 | | | | | | | | | -|T15 | |IOBS |IO_L7N_2 |UNUSED | |2 | | | | | | | | | -|T16 | |IOBM |IO_L7P_2 |UNUSED | |2 | | | | | | | | | -|T17 | |IOBS |IO_L4N_VREF_2 |UNUSED | |2 | | | | | | | | | -|T18 | |IOBM |IO_L4P_2 |UNUSED | |2 | | | | | | | | | -|T19 | |IOBM |IO_L74P_AWAKE_1 |UNUSED | |1 | | | | | | | | | -|T20 | |IOBS |IO_L74N_DOUT_BUSY_1 |UNUSED | |1 | | | | | | | | | -|T21 | |IOBM |IO_L50P_M1UDQS_1 |UNUSED | |1 | | | | | | | | | -|T22 | |IOBS |IO_L50N_M1UDQSN_1 |UNUSED | |1 | | | | | | | | | -|U1 | |IOBS |IO_L33N_M3DQ13_3 |UNUSED | |3 | | | | | | | | | -|U2 | | |GND | | | | | | | | | | | | -|U3 | |IOBM |IO_L33P_M3DQ12_3 |UNUSED | |3 | | | | | | | | | -|U4 | |IOBM |IO_L10P_3 |UNUSED | |3 | | | | | | | | | -|U5 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|U6 | |IOBM |IO_L63P_2 |UNUSED | |2 | | | | | | | | | -|U7 | | |GND | | | | | | | | | | | | -|U8 | | |NC | | | | | | | | | | | | -|U9 | |IOBM |IO_L50P_2 |UNUSED | |2 | | | | | | | | | -|U10 | | |NC | | | | | | | | | | | | -|U11 | | |VCCAUX | | | | | | | |2.5 | | | | -|U12 | | |NC | | | | | | | | | | | | -|U13 | |IOBS |IO_L12N_D2_MISO3_2 |UNUSED | |2 | | | | | | | | | -|U14 | |IOBM |IO_L12P_D1_MISO2_2 |UNUSED | |2 | | | | | | | | | -|U15 | |IOBM |IO_L13P_M1_2 |UNUSED | |2 | | | | | | | | | -|U16 | |IOBS |IO_L8N_2 |UNUSED | |2 | | | | | | | | | -|U17 | |IOBM |IO_L8P_2 |UNUSED | |2 | | | | | | | | | -|U18 | | |VCCO_1 | | |1 | | | | |any******| | | | -|U19 | |IOBM |IO_L70P_1 |UNUSED | |1 | | | | | | | | | -|U20 | |IOBM |IO_L51P_M1DQ12_1 |UNUSED | |1 | | | | | | | | | -|U21 | | |GND | | | | | | | | | | | | -|U22 | |IOBS |IO_L51N_M1DQ13_1 |UNUSED | |1 | | | | | | | | | -|V1 | |IOBS |IO_L32N_M3DQ15_3 |UNUSED | |3 | | | | | | | | | -|V2 | |IOBM |IO_L32P_M3DQ14_3 |UNUSED | |3 | | | | | | | | | -|V3 | |IOBS |IO_L10N_3 |UNUSED | |3 | | | | | | | | | -|V4 | | |GND | | | | | | | | | | | | -|V5 | |IOBS |IO_L63N_2 |UNUSED | |2 | | | | | | | | | -|V6 | | |VCCAUX | | | | | | | |2.5 | | | | -|V7 | |IOBS |IO_L46N_2 |UNUSED | |2 | | | | | | | | | -|V8 | | |VCCO_2 | | |2 | | | | |any******| | | | -|V9 | |IOBS |IO_L50N_2 |UNUSED | |2 | | | | | | | | | -|V10 | | |GND | | | | | | | | | | | | -|V11 | |IOBM |IO_L42P_2 |UNUSED | |2 | | | | | | | | | -|V12 | | |VCCO_2 | | |2 | | | | |any******| | | | -|V13 | |IOBM |IO_L18P_2 |UNUSED | |2 | | | | | | | | | -|V14 | | |GND | | | | | | | | | | | | -|V15 | |IOBS |IO_L13N_D10_2 |UNUSED | |2 | | | | | | | | | -|V16 | | |VCCO_2 | | |2 | | | | |any******| | | | -|V17 | |IOBM |IO_L11P_2 |UNUSED | |2 | | | | | | | | | -|V18 | |IOBS |IO_L9N_2 |UNUSED | |2 | | | | | | | | | -|V19 | |IOBM |IO_L9P_2 |UNUSED | |2 | | | | | | | | | -|V20 | |IOBS |IO_L70N_1 |UNUSED | |1 | | | | | | | | | -|V21 | |IOBM |IO_L52P_M1DQ14_1 |UNUSED | |1 | | | | | | | | | -|V22 | |IOBS |IO_L52N_M1DQ15_1 |UNUSED | |1 | | | | | | | | | -|W1 | |IOBS |IO_L2N_3 |UNUSED | |3 | | | | | | | | | -|W2 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|W3 | |IOBM |IO_L2P_3 |UNUSED | |3 | | | | | | | | | -|W4 | |IOBM |IO_L62P_D5_2 |UNUSED | |2 | | | | | | | | | -|W5 | | |VCCO_2 | | |2 | | | | |any******| | | | -|W6 | | |NC | | | | | | | | | | | | -|W7 | | |GND | | | | | | | | | | | | -|W8 | |IOBM |IO_L46P_2 |UNUSED | |2 | | | | | | | | | -|W9 | |IOBM |IO_L47P_2 |UNUSED | |2 | | | | | | | | | -|W10 | |IOBM |IO_L44P_2 |UNUSED | |2 | | | | | | | | | -|W11 | |IOBS |IO_L42N_2 |UNUSED | |2 | | | | | | | | | -|W12 | |IOBM |IO_L29P_GCLK3_2 |UNUSED | |2 | | | | | | | | | -|W13 | |IOBS |IO_L18N_2 |UNUSED | |2 | | | | | | | | | -|W14 | |IOBM |IO_L20P_2 |UNUSED | |2 | | | | | | | | | -|W15 | | |NC | | | | | | | | | | | | -|W16 | | |GND | | | | | | | | | | | | -|W17 | |IOBS |IO_L11N_2 |UNUSED | |2 | | | | | | | | | -|W18 | |IOBM |IO_L6P_2 |UNUSED | |2 | | | | | | | | | -|W19 | | |GND | | | | | | | | | | | | -|W20 | |IOBM |IO_L60P_1 |UNUSED | |1 | | | | | | | | | -|W21 | | |VCCO_1 | | |1 | | | | |any******| | | | -|W22 | |IOBS |IO_L60N_1 |UNUSED | |1 | | | | | | | | | -|Y1 | |IOBS |IO_L1N_VREF_3 |UNUSED | |3 | | | | | | | | | -|Y2 | |IOBM |IO_L1P_3 |UNUSED | |3 | | | | | | | | | -|Y3 | |IOBM |IO_L58P_2 |UNUSED | |2 | | | | | | | | | -|Y4 | |IOBS |IO_L62N_D6_2 |UNUSED | |2 | | | | | | | | | -|Y5 | | |NC | | | | | | | | | | | | -|Y6 | | |NC | | | | | | | | | | | | -|Y7 | |IOBM |IO_L48P_D7_2 |UNUSED | |2 | | | | | | | | | -|Y8 | |IOBS |IO_L47N_2 |UNUSED | |2 | | | | | | | | | -|Y9 | |IOBM |IO_L43P_2 |UNUSED | |2 | | | | | | | | | -|Y10 | |IOBS |IO_L44N_2 |UNUSED | |2 | | | | | | | | | -|Y11 | |IOBM |IO_L32P_GCLK29_2 |UNUSED | |2 | | | | | | | | | -|Y12 | |IOBS |IO_L29N_GCLK2_2 |UNUSED | |2 | | | | | | | | | -|Y13 | |IOBM |IO_L30P_GCLK1_D13_2 |UNUSED | |2 | | | | | | | | | -|Y14 | |IOBS |IO_L20N_2 |UNUSED | |2 | | | | | | | | | -|Y15 | |IOBM |IO_L21P_2 |UNUSED | |2 | | | | | | | | | -|Y16 | | |NC | | | | | | | | | | | | -|Y17 | |IOBM |IO_L15P_2 |UNUSED | |2 | | | | | | | | | -|Y18 | |IOBS |IO_L6N_2 |UNUSED | |2 | | | | | | | | | -|Y19 | |IOBM |IO_L5P_2 |UNUSED | |2 | | | | | | | | | -|Y20 | | |CMPCS_B_2 | | | | | | | | | | | | -|Y21 | |IOBM |IO_L1P_CCLK_2 |UNUSED | |2 | | | | | | | | | -|Y22 | | |DONE_2 | | | | | | | | | | | | -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -* Default value. -** This default Pullup/Pulldown value can be overridden in Bitgen. -****** Special VCCO requirements may apply. Please consult the device - family datasheet for specific guideline on VCCO requirements. - - Index: /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_summary.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_summary.html (revision 17) +++ /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_summary.html (revision 18) @@ -3,10 +3,9 @@ - + - @@ -14,5 +13,5 @@ - + @@ -20,11 +19,10 @@ - + - + @@ -33,5 +31,5 @@ +  @@ -39,16 +37,11 @@ - + - + - +
MultiMPITest Project Status (11/05/2012 - 16:48:15)
MultiMPITest Project Status
Project File: MPI_CORE_COMPONENTS.xise Parser Errors: No Errors
MultiMPITest Implementation State:Placed and RoutedNew
xc6slx100-3fgg484
  • Errors:
 -No Errors 
Product Version:ISE 12.3
  • Warnings:
109 Warnings (71 new) 
  • Routing Results:
 -All Signals Completely Routed
Xilinx Default (unlocked)
  • Timing Constraints:
 -X -4 Failing Constraints 
Environment: - -System Settings - 
  • Final Timing Score:
293  (Timing Report)  
@@ -58,453 +51,19 @@  
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
Current Warnings [-]
Translation WarningsNew
WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<7>' has no driver 
WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<6>' has no driver 
WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<5>' has no driver 
WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<3>' has no driver 
WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<2>' has no driver 
WARNING:NgdBuild:452: - logical net 'MPI_Node_Out[2]_PushOut<1>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/packet_ack' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank<3>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank<2>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank<1>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[2].hardmpi/MyRank<0>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/packet_ack' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank<3>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank<2>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank<1>' has no driver 
WARNING:NgdBuild:452: - logical net 'uut/connect_core[1].hardmpi/MyRank<0>' has no driver 
Map Warnings (Only the first 50 listed)New
WARNING:PhysDesignRules:372: - Gated clock. Clock net PE2/N315 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net PE1/etPutGet_FSM_FFd7 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd7 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net PE1/etPutGet[3]_PWR_594_o_Mux_268_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
WARNING:PhysDesignRules:372: - Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.New
Place and Route WarningsNew
WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:Par:288: - The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:Par:288: - The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. 
WARNING:ParHelpers:361: - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. 
WARNING:Par:283: - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. 
No Warnings Found
- 
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers1,515126,5761% 
    Number used as Flip Flops1,137   
    Number used as Latches378   
    Number used as Latch-thrus0   
    Number used as AND/OR logics0   
Number of Slice LUTs3,02563,2884% 
    Number used as logic2,94263,2884% 
        Number using O6 output only2,058   
        Number using O5 output only294   
        Number using O5 and O6590   
        Number used as ROM0   
    Number used as Memory4815,6161% 
        Number used as Dual Port RAM48   
            Number using O6 output only48   
            Number using O5 output only0   
            Number using O5 and O60   
        Number used as Single Port RAM0   
        Number used as Shift Register0   
    Number used exclusively as route-thrus35   
        Number with same-slice register load7   
        Number with same-slice carry load28   
        Number with other load0   
Number of occupied Slices1,09915,8226% 
Number of LUT Flip Flop pairs used3,230   
    Number with an unused Flip Flop1,8063,23055% 
    Number with an unused LUT2053,2306% 
    Number of fully used LUT-FF pairs1,2193,23037% 
    Number of unique control sets226   
    Number of slice register sites lost
        to control set restrictions		749126,5761% 
Number of bonded IOBs103263% 
Number of RAMB16BWERs6426823% 
Number of RAMB8BWERs45361% 
Number of BUFIO2/BUFIO2_2CLKs0320% 
Number of BUFIO2FB/BUFIO2FB_2CLKs0320% 
Number of BUFG/BUFGMUXs31618% 
    Number used as BUFGs3   
    Number used as BUFGMUX0   
Number of DCM/DCM_CLKGENs0120% 
Number of ILOGIC2/ISERDES2s05060% 
Number of IODELAY2/IODRP2/IODRP2_MCBs05060% 
Number of OLOGIC2/OSERDES2s05060% 
Number of BSCANs040% 
Number of BUFHs03840% 
Number of BUFPLLs080% 
Number of BUFPLL_MCBs040% 
Number of DSP48A1s01800% 
Number of ICAPs010% 
Number of MCBs040% 
Number of PCILOGICSEs020% 
Number of PLL_ADVs060% 
Number of PMVs010% 
Number of STARTUPs010% 
Number of SUSPEND_SYNCs010% 
Average Fanout of Non-Clock Nets4.55   
- 
- - - - - - - - - - - - - - - - - -
Performance Summary [-]
Final Timing Score:293 (Setup: 293, Hold: 0)Pinout Data:Pinout Report
Routing Results: -All Signals Completely RoutedClock Data:Clock Report
Timing Constraints: -X -4 Failing Constraints  
- 
- - -
Failing Constraints [-]
All Constraints Were Met
- 
- - -
Clock Report [-]
Data Not Yet Available
+ + + +  
@@ -512,9 +71,9 @@ - - - + + + - +
Detailed Reports [-]
ErrorsWarningsInfos
Synthesis Report     
Translation ReportCurrentTue 14. Aug 17:08:57 2012016 Warnings (0 new)0
Map ReportCurrentTue 14. Aug 17:11:06 2012083 Warnings (71 new)8 Infos (0 new)
Place and Route ReportCurrentTue 14. Aug 17:11:54 2012010 Warnings (0 new)4 Infos (0 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing ReportCurrentTue 14. Aug 17:12:09 2012003 Infos (0 new)
Post-PAR Static Timing Report     
Bitgen Report     
@@ -522,10 +81,10 @@ Secondary Reports [-] Report NameStatusGenerated -ISIM Simulator LogCurrentFri 16. Nov 14:35:18 2012 -WebTalk ReportCurrentFri 17. Aug 16:33:25 2012 -WebTalk Log FileCurrentFri 17. Aug 16:33:28 2012 +ISIM Simulator LogOut of DateTue 27. Nov 11:49:23 2012 +WebTalk ReportOut of DateFri 17. Aug 16:33:25 2012 +WebTalk Log FileOut of DateFri 17. Aug 16:33:28 2012 -
Date Generated: 11/19/2012 - 14:25:38
+
Date Generated: 11/29/2012 - 18:13:05
Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_summary.xml =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_summary.xml (revision 17) +++ (revision ) @@ -1,10 +1,0 @@ - - - - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_usage.xml =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_usage.xml (revision 17) +++ (revision ) @@ -1,77 +1,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_vhdl.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/MultiMPITest_vhdl.prj (revision 17) +++ (revision ) @@ -1,45 +1,0 @@ -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\CoreTypes.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\RAM_256.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\Arbiter.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER9_9.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER8_8.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER7_7.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER6_6.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER5_5.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER4_4.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER3_3.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER2_2.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER16_16.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER15_15.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER14_14.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER13_13.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER12_12.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER11_11.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER10_10.VHD" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\FIFO_256_FWFT.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\Crossbit.vhd" -vhdl work "C:\Core MPI\CORE_MPI\round_robbin_machine.vhd" -vhdl work "C:\Core MPI\CORE_MPI\RAM_64.vhd" -vhdl work "C:\Core MPI\CORE_MPI\Packet_type.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MUX8.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MUX1.vhd" -vhdl work "C:\Core MPI\CORE_MPI\DEMUX1.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\Scheduler.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\OUTPUT_PORT_MODULE.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\INPUT_PORT_MODULE.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\Crossbar.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MPI_CORE_SCHEDULER.vhd" -vhdl work "C:\Core MPI\CORE_MPI\load_instr.vhd" -vhdl work "C:\Core MPI\CORE_MPI\FIFO_64_FWFT.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX4_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX3_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX2_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\EX1_FSM.vhd" -vhdl work "C:\Core MPI\CORE_MPI\Ex0_Fsm.vhd" -vhdl work "C:\Core MPI\CORE_MPI\DMA_ARBITER.vhd" -vhdl NocLib "C:\Core MPI\SWITCH_GENERIC_16_16\SWITCH_GEN.vhd" -vhdl work "C:\Core MPI\CORE_MPI\RAM_32_32.vhd" -vhdl work "C:\Core MPI\CORE_MPI\CORE_MPI.vhd" -vhdl work "C:\Core MPI\CORE_MPI\PE.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MPI_NOC.vhd" -vhdl work "C:\Core MPI\CORE_MPI\MultiMPITest.vhd" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v.cmd_log =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v.cmd_log (revision 17) +++ (revision ) @@ -1,5 +1,0 @@ -vhdtdtfi -prj MPI_CORE_COMPONENTS -o "C:/Core MPI/CORE_MPI/RAM_v.vhi" -lib work "C:/Core MPI/CORE_MPI//RAM_32_32.vhd" -module RAM_v -template d:/Xilinx/12.3/ISE_DS/ISE//data/vhdlinst.tft -deleteonerror -vhdtdtfi -prj MPI_CORE_COMPONENTS -o "C:/Core MPI/CORE_MPI/RAM_v.vhi" -lib work "C:/Core MPI/CORE_MPI//RAM_32_32.vhd" -module RAM_v -template d:/Xilinx/12.3/ISE_DS/ISE//data/vhdlinst.tft -deleteonerror -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/RAM_v.xst" -ofn "C:/Core MPI/CORE_MPI/RAM_v.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/RAM_v.xst" -ofn "C:/Core MPI/CORE_MPI/RAM_v.syr" -xst -intstyle ise -ifn "C:/Core MPI/CORE_MPI/RAM_v.xst" -ofn "C:/Core MPI/CORE_MPI/RAM_v.syr" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v.lso =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v.lso (revision 17) +++ (revision ) @@ -1,1 +1,0 @@ -work Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v.prj (revision 17) +++ (revision ) @@ -1,2 +1,0 @@ -vhdl NocLib "../SWITCH_GENERIC_16_16/CoreTypes.vhd" -vhdl work "RAM_32_32.vhd" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v.syr =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v.syr (revision 17) +++ (revision ) @@ -1,495 +1,0 @@ -Release 12.3 - xst M.70d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. ---> Parameter TMPDIR set to xst/projnav.tmp - - -Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.09 secs - ---> Parameter xsthdpdir set to xst - - -Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.09 secs - ---> Reading design: RAM_v.prj - -TABLE OF CONTENTS - 1) Synthesis Options Summary - 2) HDL Parsing - 3) HDL Elaboration - 4) HDL Synthesis - 4.1) HDL Synthesis Report - 5) Advanced HDL Synthesis - 5.1) Advanced HDL Synthesis Report - 6) Low Level Synthesis - 7) Partition Report - 8) Design Summary - 8.1) Primitive and Black Box Usage - 8.2) Device utilization summary - 8.3) Partition Resource Summary - 8.4) Timing Report - 8.4.1) Clock Information - 8.4.2) Asynchronous Control Signals Information - 8.4.3) Timing Summary - 8.4.4) Timing Details - 8.4.5) Cross Clock Domains Report - - -========================================================================= -* Synthesis Options Summary * -========================================================================= ----- Source Parameters -Input File Name : "RAM_v.prj" -Input Format : mixed -Ignore Synthesis Constraint File : NO - ----- Target Parameters -Output File Name : "RAM_v" -Output Format : NGC -Target Device : xc6slx100-3-fgg484 - ----- Source Options -Top Module Name : RAM_v -Automatic FSM Extraction : YES -FSM Encoding Algorithm : Auto -Safe Implementation : No -FSM Style : LUT -RAM Extraction : Yes -RAM Style : Auto -ROM Extraction : Yes -Shift Register Extraction : YES -ROM Style : Auto -Resource Sharing : YES -Asynchronous To Synchronous : NO -Shift Register Minimum Size : 2 -Use DSP Block : Auto -Automatic Register Balancing : No - ----- Target Options -LUT Combining : Auto -Reduce Control Sets : Auto -Add IO Buffers : YES -Global Maximum Fanout : 100000 -Add Generic Clock Buffer(BUFG) : 16 -Register Duplication : YES -Optimize Instantiated Primitives : NO -Use Clock Enable : Auto -Use Synchronous Set : Auto -Use Synchronous Reset : Auto -Pack IO Registers into IOBs : Auto -Equivalent register Removal : YES - ----- General Options -Optimization Goal : Speed -Optimization Effort : 1 -Power Reduction : NO -Keep Hierarchy : Soft -Netlist Hierarchy : As_Optimized -RTL Output : Yes -Global Optimization : AllClockNets -Read Cores : YES -Write Timing Constraints : NO -Cross Clock Analysis : NO -Hierarchy Separator : / -Bus Delimiter : <> -Case Specifier : Maintain -Slice Utilization Ratio : 100 -BRAM Utilization Ratio : 100 -DSP48 Utilization Ratio : 100 -Auto BRAM Packing : NO -Slice Utilization Ratio Delta : 5 - -========================================================================= - - -========================================================================= -* HDL Parsing * -========================================================================= -Parsing VHDL file "\Core MPI\CORE_MPI\../SWITCH_GENERIC_16_16/CoreTypes.vhd" into library NocLib -Parsing package . -Parsing package body . -Parsing VHDL file "\Core MPI\CORE_MPI\RAM_32_32.vhd" into library work -Parsing entity . -Parsing architecture of entity . - -========================================================================= -* HDL Elaboration * -========================================================================= - -Elaborating entity (architecture ) with generics from library . - -========================================================================= -* HDL Synthesis * -========================================================================= - -Synthesizing Unit . - Related source file is "/core mpi/core_mpi/ram_32_32.vhd". - width = 32 - Size = 16 - Found 65536x32-bit dual-port RAM for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 32-bit register for signal . - Found 32-bit register for signal . - Summary: - inferred 1 RAM(s). - inferred 66 D-type flip-flop(s). - inferred 1 Multiplexer(s). -Unit synthesized. - -========================================================================= -HDL Synthesis Report - -Macro Statistics -# RAMs : 1 - 65536x32-bit dual-port RAM : 1 -# Registers : 4 - 1-bit register : 2 - 32-bit register : 2 -# Multiplexers : 1 - 32-bit 2-to-1 multiplexer : 1 - -========================================================================= - -========================================================================= -* Advanced HDL Synthesis * -========================================================================= - - -Synthesizing (advanced) Unit . -INFO:Xst:3031 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 65536-word x 32-bit | | - | clkA | connected to signal | rise | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - ----------------------------------------------------------------------- - | Port B | - | aspect ratio | 65536-word x 32-bit | | - | addrB | connected to signal | | - | doB | connected to internal node | | - ----------------------------------------------------------------------- -Unit synthesized (advanced). - -========================================================================= -Advanced HDL Synthesis Report - -Macro Statistics -# RAMs : 1 - 65536x32-bit dual-port distributed RAM : 1 -# Registers : 66 - Flip-Flops : 66 -# Multiplexers : 1 - 32-bit 2-to-1 multiplexer : 1 - -========================================================================= - -========================================================================= -* Low Level Synthesis * -========================================================================= - -Optimizing unit ... - -Mapping all equations... -Building and optimizing final netlist ... -Found area constraint ratio of 100 (+ 5) on block RAM_v, actual ratio is 52. - -Final Macro Processing ... - -========================================================================= -Final Register Report - -Macro Statistics -# Registers : 66 - Flip-Flops : 66 - -========================================================================= - -========================================================================= -* Partition Report * -========================================================================= - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -========================================================================= -* Design Summary * -========================================================================= - -Top Level Output File Name : RAM_v.ngc - -Primitive and Black Box Usage: ------------------------------- -# BELS : 12007 -# GND : 1 -# LUT2 : 4 -# LUT3 : 34 -# LUT4 : 32 -# LUT6 : 11936 -# FlipFlops/Latches : 66 -# FDE : 64 -# FDR : 2 -# RAMS : 12288 -# RAM64M : 10240 -# RAM64X1D : 2048 -# Clock Buffers : 2 -# BUFGP : 2 -# IO Buffers : 99 -# IBUF : 67 -# OBUF : 32 - -Device utilization summary: ---------------------------- - -Selected Device : 6slx100fgg484-3 - - -Slice Logic Utilization: - Number of Slice Registers: 66 out of 126576 0% - Number of Slice LUTs: 57062 out of 63288 90% - Number used as Logic: 12006 out of 63288 18% - Number used as Memory: 45056 out of 15616 288% (*) - Number used as RAM: 45056 - -Slice Logic Distribution: - Number of LUT Flip Flop pairs used: 57062 - Number with an unused Flip Flop: 56996 out of 57062 99% - Number with an unused LUT: 0 out of 57062 0% - Number of fully used LUT-FF pairs: 66 out of 57062 0% - Number of unique control sets: 4 - -IO Utilization: - Number of IOs: 101 - Number of bonded IOBs: 101 out of 326 30% - -Specific Feature Utilization: - Number of BUFG/BUFGCTRLs: 2 out of 16 12% - -WARNING:Xst:1336 - (*) More than 100% of Device resources are used - ---------------------------- -Partition Resource Summary: ---------------------------- - - No Partitions were found in this design. - ---------------------------- - - -========================================================================= -Timing Report - -NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. - FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT - GENERATED AFTER PLACE-and-ROUTE. - -Clock Information: ------------------- ------------------------------------+------------------------+-------+ -Clock Signal | Clock buffer(FF name) | Load | ------------------------------------+------------------------+-------+ -clka | BUFGP | 12321 | -clkb | BUFGP | 33 | ------------------------------------+------------------------+-------+ - -Asynchronous Control Signals Information: ----------------------------------------- -No asynchronous control signals found in this design - -Timing Summary: ---------------- -Speed Grade: -3 - - Minimum period: 6.754ns (Maximum Frequency: 148.055MHz) - Minimum input arrival time before clock: 16.914ns - Maximum output required time after clock: 5.602ns - Maximum combinational path delay: No path found - -Timing Details: ---------------- -All values displayed in nanoseconds (ns) - -========================================================================= -Timing constraint: Default period analysis for Clock 'clka' - Clock period: 6.754ns (frequency: 148.055MHz) - Total number of paths / destination ports: 32769 / 33 -------------------------------------------------------------------------- -Delay: 6.754ns (Levels of Logic = 5) - Source: Mram_RAM427 (RAM) - Destination: doa_1 (FF) - Source Clock: clka rising - Destination Clock: clka rising - - Data Path: Mram_RAM427 to doa_1 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - RAM64M:WCLK->DOB 1 1.131 0.856 Mram_RAM427 (N3586) - LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX1_2229 (inst_LPM_MUX1_2229) - LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX1_178 (inst_LPM_MUX1_178) - LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX1_122 (inst_LPM_MUX1_122) - LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX1_7 (inst_LPM_MUX1_7) - LUT6:I2->O 2 0.254 0.000 addrb<15>110 (_n0028<1>) - FDE:D 0.074 doa_1 - ---------------------------------------- - Total 6.754ns (2.475ns logic, 4.279ns route) - (36.6% logic, 63.4% route) - -========================================================================= -Timing constraint: Default period analysis for Clock 'clkb' - Clock period: 2.278ns (frequency: 439.057MHz) - Total number of paths / destination ports: 1 / 1 -------------------------------------------------------------------------- -Delay: 2.278ns (Levels of Logic = 1) - Source: Lrb (FF) - Destination: Lrb (FF) - Source Clock: clkb rising - Destination Clock: clkb rising - - Data Path: Lrb to Lrb - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - FDR:C->Q 34 0.525 1.429 Lrb (Lrb) - LUT2:I0->O 1 0.250 0.000 Lrb_glue_set (Lrb_glue_set) - FDR:D 0.074 Lrb - ---------------------------------------- - Total 2.278ns (0.849ns logic, 1.429ns route) - (37.3% logic, 62.7% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'clka' - Total number of paths / destination ports: 300386 / 131138 -------------------------------------------------------------------------- -Offset: 16.914ns (Levels of Logic = 7) - Source: addrb<5> (PAD) - Destination: doa_30 (FF) - Destination Clock: clka rising - - Data Path: addrb<5> to doa_30 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 32768 1.228 9.827 addrb_5_IBUF (addrb_5_IBUF) - RAM64X1D:DPRA5->DPO 1 0.235 0.856 Mram_RAM106671 (N64172) - LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_2229 (inst_LPM_MUX30_2229) - LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_178 (inst_LPM_MUX30_178) - LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_122 (inst_LPM_MUX30_122) - LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_7 (inst_LPM_MUX30_7) - LUT6:I2->O 2 0.254 0.000 addrb<15>301 (_n0028<30>) - FDE:D 0.074 doa_30 - ---------------------------------------- - Total 16.914ns (2.807ns logic, 14.107ns route) - (16.6% logic, 83.4% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'clkb' - Total number of paths / destination ports: 34146 / 66 -------------------------------------------------------------------------- -Offset: 16.914ns (Levels of Logic = 7) - Source: addrb<5> (PAD) - Destination: dout_30 (FF) - Destination Clock: clkb rising - - Data Path: addrb<5> to dout_30 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 32768 1.228 9.827 addrb_5_IBUF (addrb_5_IBUF) - RAM64X1D:DPRA5->DPO 1 0.235 0.856 Mram_RAM106671 (N64172) - LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_2229 (inst_LPM_MUX30_2229) - LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_178 (inst_LPM_MUX30_178) - LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_122 (inst_LPM_MUX30_122) - LUT6:I2->O 1 0.254 0.856 inst_LPM_MUX30_7 (inst_LPM_MUX30_7) - LUT6:I2->O 2 0.254 0.000 addrb<15>301 (_n0028<30>) - FDE:D 0.074 dout_30 - ---------------------------------------- - Total 16.914ns (2.807ns logic, 14.107ns route) - (16.6% logic, 83.4% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'clkb' - Total number of paths / destination ports: 64 / 32 -------------------------------------------------------------------------- -Offset: 5.602ns (Levels of Logic = 2) - Source: Lrb (FF) - Destination: dob<31> (PAD) - Source Clock: clkb rising - - Data Path: Lrb to dob<31> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - FDR:C->Q 34 0.525 1.549 Lrb (Lrb) - LUT4:I1->O 1 0.235 0.579 Mmux_dob321 (dob_9_OBUF) - OBUF:I->O 2.715 dob_9_OBUF (dob<9>) - ---------------------------------------- - Total 5.602ns (3.475ns logic, 2.127ns route) - (62.0% logic, 38.0% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'clka' - Total number of paths / destination ports: 64 / 32 -------------------------------------------------------------------------- -Offset: 5.497ns (Levels of Logic = 2) - Source: Lra (FF) - Destination: dob<31> (PAD) - Source Clock: clka rising - - Data Path: Lra to dob<31> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - FDR:C->Q 34 0.525 1.429 Lra (Lra) - LUT4:I2->O 1 0.250 0.579 Mmux_dob321 (dob_9_OBUF) - OBUF:I->O 2.715 dob_9_OBUF (dob<9>) - ---------------------------------------- - Total 5.497ns (3.490ns logic, 2.007ns route) - (63.5% logic, 36.5% route) - -========================================================================= - -Cross Clock Domains Report: --------------------------- - -Clock to Setup on destination clock clka ----------------+---------+---------+---------+---------+ - | Src:Rise| Src:Fall| Src:Rise| Src:Fall| -Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ----------------+---------+---------+---------+---------+ -clka | 6.754| | | | -clkb | 3.241| | | | ----------------+---------+---------+---------+---------+ - -Clock to Setup on destination clock clkb ----------------+---------+---------+---------+---------+ - | Src:Rise| Src:Fall| Src:Rise| Src:Fall| -Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ----------------+---------+---------+---------+---------+ -clka | 6.754| | | | -clkb | 2.278| | | | ----------------+---------+---------+---------+---------+ - -========================================================================= - - -Total REAL time to Xst completion: 587.00 secs -Total CPU time to Xst completion: 587.28 secs - ---> - -Total memory usage is 1227976 kilobytes - -Number of errors : 0 ( 0 filtered) -Number of warnings : 1 ( 0 filtered) -Number of infos : 1 ( 0 filtered) - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v.xst =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v.xst (revision 17) +++ (revision ) @@ -1,53 +1,0 @@ -set -tmpdir "xst/projnav.tmp" -set -xsthdpdir "xst" -run --ifn RAM_v.prj --ifmt mixed --ofn RAM_v --ofmt NGC --p xc6slx100-3-fgg484 --top RAM_v --opt_mode Speed --opt_level 1 --power NO --iuc NO --keep_hierarchy Soft --netlist_hierarchy As_Optimized --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case Maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --dsp_utilization_ratio 100 --lc Auto --reduce_control_sets Auto --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style LUT --ram_extract Yes --ram_style Auto --rom_extract Yes --shreg_extract YES --rom_style Auto --auto_bram_packing NO --resource_sharing YES --async_to_sync NO --shreg_min_size 2 --use_dsp48 Auto --iobuf YES --max_fanout 100000 --bufg 16 --register_duplication YES --register_balancing No --optimize_primitives NO --use_clock_enable Auto --use_sync_set Auto --use_sync_reset Auto --iob Auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v_envsettings.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v_envsettings.html (revision 17) +++ (revision ) @@ -1,394 +1,0 @@ -Xilinx System Settings Report - -
System Settings

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Environment Settings
Environment Variablexstngdbuildmappar
PATHEXT.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		< data not available >< data not available >< data not available >
Pathd:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
D:\Xilinx\12.3\ISE_DS\common\bin\nt64;
D:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files (x86)\PC Connectivity Solution\;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\CMake 2.8\bin;
C:\qtsdk\mingw\bin;
C:\qtsdk\qtcreator\bin;
C:\Program Files (x86)\Graphviz 2.28\bin;
C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox;
C:\modeltech_6.6b\win32;
C:\modeltech_6.5\win32		< data not available >< data not available >< data not available >
XILINXd:\Xilinx\12.3\ISE_DS\ISE\< data not available >< data not available >< data not available >
XILINX_DSPD:\Xilinx\12.3\ISE_DS\ISE< data not available >< data not available >< data not available >
XILINX_EDKD:\Xilinx\12.3\ISE_DS\EDK< data not available >< data not available >< data not available >
XILINX_PLANAHEADD:\Xilinx\12.3\ISE_DS\PlanAhead< data not available >< data not available >< data not available >
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Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn RAM_v.prj 
-ifmt mixedMixed
-ofn RAM_v 
-ofmt NGCNGC
-p xc6slx100-3-fgg484 
-top RAM_v 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-powerPower ReductionNONo
-iucUse synthesis Constraints FileNONo
-keep_hierarchyKeep HierarchySoftNo
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNo
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYes
-write_timing_constraintsWrite Timing ConstraintsNONo
-cross_clock_analysisCross Clock AnalysisNONo
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100
-bram_utilization_ratioBRAM Utilization Ratio100100
-dsp_utilization_ratioDSP Utilization Ratio100100
-reduce_control_sets AutoAuto
-fsm_extract YESYes
-fsm_encoding AutoAuto
-safe_implementation NoNo
-fsm_style LUTLUT
-ram_extract YesYes
-ram_style AutoAuto
-rom_extract YesYes
-shreg_extract YESYes
-rom_style AutoAuto
-auto_bram_packing NONo
-resource_sharing YESYes
-async_to_sync NONo
-use_dsp48 AutoAuto
-iobuf YESYes
-max_fanout 100000100000
-bufg 1616
-register_duplication YESYes
-register_balancing NoNo
-optimize_primitives NONo
-use_clock_enable AutoAuto
-use_sync_set AutoAuto
-use_sync_reset AutoAuto
-iob AutoAuto
-equivalent_register_removal YESYes
-slice_utilization_ratio_maxmargin 50
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Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHz<  data not available  ><  data not available  ><  data not available  >
HostGAMOM-PC<  data not available  ><  data not available  ><  data not available  >
OS NameMicrosoft <  data not available  ><  data not available  ><  data not available  >
OS ReleaseService Pack 1 (build 7601)<  data not available  ><  data not available  ><  data not available  >
- Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v_summary.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v_summary.html (revision 17) +++ (revision ) @@ -1,125 +1,0 @@ -Xilinx Design Summary - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MultiMPITest Project Status (11/05/2012 - 16:48:15)
Project File:MPI_CORE_COMPONENTS.xiseParser Errors: No Errors
Module Name:RAM_vImplementation State:Synthesized
Target Device:xc6slx100-3fgg484
  • Errors:
 -No Errors
Product Version:ISE 12.3
  • Warnings:
1 Warning (1 new)
Design Goal:Balanced
  • Routing Results:
 - 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: - -System Settings -
  • Final Timing Score:
  
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Current Warnings [-]
Synthesis WarningsNew
WARNING:Xst:1336: - (*) More than 100% of Device resources are usedNew
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Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers661265760%
Number of Slice LUTs570626328890%
Number of fully used LUT-FF pairs66570620%
Number of bonded IOBs10132630%
Number of BUFG/BUFGCTRLs21612%
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Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentMon 5. Nov 16:48:13 201201 Warning (1 new)1 Info (1 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
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Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateMon 5. Nov 15:29:30 2012
WebTalk ReportOut of DateFri 17. Aug 16:33:25 2012
WebTalk Log FileOut of DateFri 17. Aug 16:33:28 2012
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Date Generated: 11/05/2012 - 16:59:03
- Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v_vhdl.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/RAM_v_vhdl.prj (revision 17) +++ (revision ) @@ -1,1 +1,0 @@ -vhdl work "C:\Core MPI\CORE_MPI\RAM_32_32.vhd" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/_xmsgs/map.xmsgs =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/_xmsgs/map.xmsgs (revision 17) +++ (revision ) @@ -1,288 +1,0 @@ - - - -Logical network MPI_Node_Out[2]_PushOut<7> has no load. - - -The above info message is repeated 23 more times for the following (max. 5 shown): -MPI_Node_Out[2]_PushOut<6>, -MPI_Node_Out[2]_PushOut<5>, -MPI_Node_Out[2]_PushOut<3>, -MPI_Node_Out[2]_PushOut<2>, -MPI_Node_Out[2]_PushOut<1> -To see the details of these info messages, please use the -detail switch. - - -No environment variables are currently set. - - -All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. - - -Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) - - -Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) - - -The Interim Design Summary has been generated in the MAP Report (.mrp). - - -Map created a placed design. - - -Gated clock. Clock net PE2/N315 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net PE1/etPutGet_FSM_FFd7 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/ex4_ram_wr is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/etcmd[3]_PWR_534_o_Mux_739_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/Mram_dma_wr_grant[4]_GND_656_o_Mux_42_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_99_o_Mux_295_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2_FSM_FFd7 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_290_o_Mux_59_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_148_o_Mux_387_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_72_o_Mux_259_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net PE1/etPutGet[3]_PWR_594_o_Mux_268_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_93_o_Mux_287_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_105_o_Mux_303_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_44_o_Mux_211_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_66_o_Mux_251_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_90_o_Mux_283_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_102_o_Mux_299_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_291_o_Mux_61_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_299_o_Mux_77_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_69_o_Mux_255_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_84_o_Mux_275_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_81_o_Mux_271_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_124_o_Mux_339_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_432_o_Mux_383_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_164_o_Mux_419_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_60_o_Mux_243_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_87_o_Mux_279_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_96_o_Mux_291_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_132_o_Mux_355_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_132_o_Mux_355_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_39_o_Mux_201_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_38_o_Mux_199_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_38_o_Mux_199_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_278_o_Mux_43_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_278_o_Mux_43_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_140_o_Mux_371_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/MPI_CORE_EX4_FSM/stInit2[3]_PWR_316_o_Mux_111_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net PE2/etPutGet[3]_PWR_639_o_Mux_268_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_63_o_Mux_247_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[2].hardmpi/LD_instr/N117 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/N117 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_108_o_Mux_307_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_75_o_Mux_263_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -Gated clock. Clock net uut/connect_core[1].hardmpi/LD_instr/etloadinst[2]_PWR_78_o_Mux_267_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. - - -The signal <uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O> is incomplete. The signal does not drive any load pins in the design. - - -The signal <uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O> is incomplete. The signal does not drive any load pins in the design. - - -The signal <uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O> is incomplete. The signal does not drive any load pins in the design. - - -The signal <uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O> is incomplete. The signal does not drive any load pins in the design. - - -The signal <uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O> is incomplete. The signal does not drive any load pins in the design. - - -The signal <uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O> is incomplete. The signal does not drive any load pins in the design. - - -The signal <uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O> is incomplete. The signal does not drive any load pins in the design. - - -The signal <uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O> is incomplete. The signal does not drive any load pins in the design. - - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/_xmsgs/ngdbuild.xmsgs =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/_xmsgs/ngdbuild.xmsgs (revision 17) +++ (revision ) @@ -1,57 +1,0 @@ - - - -logical net 'MPI_Node_Out[2]_PushOut<7>' has no driver - - -logical net 'MPI_Node_Out[2]_PushOut<6>' has no driver - - -logical net 'MPI_Node_Out[2]_PushOut<5>' has no driver - - -logical net 'MPI_Node_Out[2]_PushOut<3>' has no driver - - -logical net 'MPI_Node_Out[2]_PushOut<2>' has no driver - - -logical net 'MPI_Node_Out[2]_PushOut<1>' has no driver - - -logical net 'uut/connect_core[2].hardmpi/packet_ack' has no driver - - -logical net 'uut/connect_core[2].hardmpi/MyRank<3>' has no driver - - -logical net 'uut/connect_core[2].hardmpi/MyRank<2>' has no driver - - -logical net 'uut/connect_core[2].hardmpi/MyRank<1>' has no driver - - -logical net 'uut/connect_core[2].hardmpi/MyRank<0>' has no driver - - -logical net 'uut/connect_core[1].hardmpi/packet_ack' has no driver - - -logical net 'uut/connect_core[1].hardmpi/MyRank<3>' has no driver - - -logical net 'uut/connect_core[1].hardmpi/MyRank<2>' has no driver - - -logical net 'uut/connect_core[1].hardmpi/MyRank<1>' has no driver - - -logical net 'uut/connect_core[1].hardmpi/MyRank<0>' has no driver - - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/_xmsgs/par.xmsgs =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/_xmsgs/par.xmsgs (revision 17) +++ (revision ) @@ -1,51 +1,0 @@ - - - -No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". - - -The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. - - -The signal uut/connect_core[2].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. - - -The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. - - -The signal uut/connect_core[2].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. - - -The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. - - -The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. - - -The signal uut/connect_core[1].hardmpi/Instruction_Fifo2/fifo_RAM_64/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal. - - -The signal uut/connect_core[1].hardmpi/Instruction_Fifo1/fifo_RAM_64/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal. - - -N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. - -The Clock Report is not displayed in the non timing-driven mode. - - -N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. - -There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. - - - -There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. - - - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/_xmsgs/pn_parser.xmsgs =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/_xmsgs/pn_parser.xmsgs (revision 17) +++ (revision ) @@ -1,24 +1,0 @@ - - - - - - - - - - -Parsing VHDL file "C:/Core MPI/CORE_MPI/Packet_type.vhd" into library work - - -"C:/Core MPI/CORE_MPI/Packet_type.vhd" Line 37. Syntax error near "constantMPI_WTICK". - - -Parsing VHDL file "C:/Core MPI/SWITCH_GENERIC_16_16/CoreTypes.vhd" into library NocLib - - -"C:/Core MPI/SWITCH_GENERIC_16_16/CoreTypes.vhd" Line 228. Syntax error near "begin". - - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/_xmsgs/trce.xmsgs =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/_xmsgs/trce.xmsgs (revision 17) +++ (revision ) @@ -1,15 +1,0 @@ - - - -No timing constraints found, doing default enumeration. - -To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. - -The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/_xmsgs/xst.xmsgs =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/_xmsgs/xst.xmsgs (revision 17) +++ (revision ) @@ -1,15 +1,0 @@ - - - -HDL ADVISOR - The RAM <Mram_RAM> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. - - - (*) More than 100% of Device resources are used - - - - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/compxlib.log =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/compxlib.log (revision 17) +++ (revision ) @@ -1,57 +1,0 @@ - ____ ____ - / /\/ / - /___/ \ / VENDOR : Xilinx Inc. - \ \ \/ VERSION : 12.3 (M.70d) - \ \ APPLICATION : d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe - / / CONTENTS : Compilation Log - /___/ /\ FILENAME : compxlib.log - \ \ / \ - \___\/\___\ - -Release 12.3 - d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe 12.3 (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -Processing command line ... -Reading the compxlib configuration file - 'compxlib.cfg' ... -WARNING:Compxlib - The legacy option '-exclude_deprecated' will be obsolete in version 13.1. Please use the option '-exclude_superseded' for the same. -Library Source Paths => 'd:/Xilinx/12.3/ISE_DS/ISE' -Current Working Directory => 'C:\Core MPI\CORE_MPI' -Compilation Mode = FAST -Execute Mode = ON -Scheduling library installation & compilation for architectures: spartan6 - -Scheduling library installation & compilation for libraries: simprim unisim xilinxcorelib edk - -Signature:- ------------------------------------------------------------------------------- -d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe -s mti_se -l vhdl -p "C:/Core MPI/CORE_MPI" -arch spartan6 -lib unisim -lib simprim -lib xilinxcorelib -lib edk -exclude_deprecated -intstyle ise ------------------------------------------------------------------------------- -ERROR:Compxlib - COMPXLIB[sim]: Unable to automatically find executables for simulator 'mti_se' from the following paths: - C:/Core MPI/CORE_MPI - d:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64 - d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64 - D:\Xilinx\12.3\ISE_DS\PlanAhead\bin - D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64 - D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64 - D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64 - D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64 - D:\Xilinx\12.3\ISE_DS\common\bin\nt64 - D:\Xilinx\12.3\ISE_DS\common\lib\nt64 - C:\Program Files\Common Files\Microsoft Shared\Windows Live - C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live - C:\Windows\system32 - C:\Windows - C:\Windows\System32\Wbem - C:\Windows\System32\WindowsPowerShell\v1.0\ - C:\Program Files (x86)\Windows Live\Shared - C:\Program Files (x86)\CMake 2.8\bin - C:\qtsdk\mingw\bin - C:\qtsdk\qtcreator\bin - C:\Program Files (x86)\Graphviz 2.28\bin - C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\ - C:\Program Files\Microsoft SQL Server\100\Tools\Binn\ - C:\Program Files\Microsoft SQL Server\100\DTS\Binn\ - c:\altera\90sp1\quartus\bin - C:\Program Files\Oracle\VirtualBox - C:\modeltech_6.6b\win32. -Simulator 'mti_se' is ignored. Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/fuse.log =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/fuse.log (revision 17) +++ (revision ) @@ -1,96 +1,0 @@ -Running: d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib secureip -o C:/Core MPI/CORE_MPI/MultiMPITest_isim_beh.exe -prj C:/Core MPI/CORE_MPI/MultiMPITest_beh.prj work.MultiMPITest -ISim M.70d (signature 0x16fbe694) -Number of CPUs detected in this system: 8 -Turning on mult-threading, number of parallel sub-compilation jobs: 16 -Determining compilation order of HDL files -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/CoreTypes.vhd" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/RAM_256.vhd" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/Arbiter.vhd" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/Crossbit.vhd" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/round_robbin_machine.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/Packet_type.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/MUX8.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/MUX1.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/DEMUX1.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/Scheduler.vhd" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/Crossbar.vhd" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/MPI_CORE_SCHEDULER.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/load_instr.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/FIFO_64_FWFT.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/EX4_FSM.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/EX3_FSM.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/EX2_FSM.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/EX1_FSM.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/Ex0_Fsm.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/DMA_ARBITER.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" into library NocLib -Parsing VHDL file "C:/Core MPI/CORE_MPI/RAM_32_32.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/MPI_RMA.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/CORE_MPI.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/PE.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/MPI_NOC.vhd" into library work -Parsing VHDL file "C:/Core MPI/CORE_MPI/MultiMPITest.vhd" into library work -Starting static elaboration -WARNING:HDLCompiler:1242 - "N:/M.70d/rtf/vhdl/src/ieee/numeric_std.vhd" Line 3181: Warning: "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0" -Completed static elaboration -Using precompiled package standard from library std -Using precompiled package std_logic_1164 from library ieee -Using precompiled package numeric_std from library ieee -Using precompiled package std_logic_arith from library ieee -Using precompiled package std_logic_unsigned from library ieee -Compiling package coretypes -Compiling package packet_type -Compiling package mpi_rma -Compiling architecture behavioral of entity ram_256 [ram_256_default] -Compiling architecture behavioral of entity fifo_256_fwft [fifo_256_fwft_default] -Compiling architecture behavioral of entity input_port_module [\INPUT_PORT_MODULE(4,1)\] -Compiling architecture behavioral of entity input_port_module [\INPUT_PORT_MODULE(4,2)\] -Compiling architecture behavioral of entity input_port_module [\INPUT_PORT_MODULE(4,3)\] -Compiling architecture behavioral of entity input_port_module [\INPUT_PORT_MODULE(4,4)\] -Compiling architecture behavioral_description of entity output_port_module [output_port_module_default] -Compiling architecture behavioral of entity crossbit [\Crossbit(4)\] -Compiling architecture behavioral of entity crossbar [\Crossbar(4)\] -Compiling architecture behavioral of entity arbiter [arbiter_default] -Compiling architecture behavioral of entity scheduler4_4 [scheduler4_4_default] -Compiling architecture behavioral of entity scheduler [\Scheduler(4)\] -Compiling architecture behavioral of entity switch_gen [\SWITCH_GEN(4)\] -Compiling architecture behavioral of entity fifo_64_fwft [fifo_64_fwft_default] -Compiling architecture behavioral of entity load_instr [load_instr_default] -Compiling architecture behavioral of entity ex0_fsm [\Ex0_Fsm(7,0,31,0,31,0)\] -Compiling architecture behavioral of entity ex1_fsm [ex1_fsm_default] -Compiling architecture behavioral of entity ex2_fsm [\EX2_FSM(('0','0','0','1'),('0',...] -Compiling architecture behavioral of entity ex3_fsm [\EX3_FSM(('0','0','0','0','0','0...] -Compiling architecture behavioral of entity ex4_fsm [ex4_fsm_default] -Compiling architecture behavioral of entity dma_arbiter [dma_arbiter_default] -Compiling architecture behavioral of entity round_robbin_machine [round_robbin_machine_default] -Compiling architecture behavioral of entity mux1 [mux1_default] -Compiling architecture behavioral of entity demux1 [demux1_default] -Compiling architecture behavioral of entity mux8 [mux8_default] -Compiling architecture behavioral of entity mpi_core_scheduler [mpi_core_scheduler_default] -Compiling architecture structural of entity core_mpi [core_mpi_default] -Compiling architecture structural of entity mpi_noc [\MPI_NOC(4)\] -Compiling architecture behavioral of entity ram_v [\RAM_v(8,16)\] -Compiling architecture behavioral of entity pe [\PE(1)\] -Compiling architecture behavioral of entity pe [\PE(0)\] -Compiling architecture behavior of entity multimpitest -Time Resolution for simulation is 1ps. -Waiting for 20 sub-compilation(s) to finish... -Compiled 71 VHDL Units -Built simulation executable C:/Core MPI/CORE_MPI/MultiMPITest_isim_beh.exe -Fuse Memory Usage: 42976 KB -Fuse CPU Usage: 1512 ms Index: /PROJECT_CORE_MPI/CORE_MPI/TRUNK/iseconfig/MPI_CORE_COMPONENTS.projectmgr =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/iseconfig/MPI_CORE_COMPONENTS.projectmgr (revision 17) +++ /PROJECT_CORE_MPI/CORE_MPI/TRUNK/iseconfig/MPI_CORE_COMPONENTS.projectmgr (revision 18) @@ -164,11 +164,11 @@ - C:\Core MPI\CORE_MPI\DMA_ARBITER.vhd - - 0 + C:\Core MPI\SWITCH_GENERIC_16_16\CoreTypes.vhd + + 17 0 000000ff00000000000000010000000000000000010000000000000000000000000000000000000307000000040101000100000000000000000000000064ffffffff000000810000000000000004000001f90000000100000000000000440000000100000000000000660000000100000000000000640000000100000000 false - C:\Core MPI\CORE_MPI\DMA_ARBITER.vhd + C:\Core MPI\SWITCH_GENERIC_16_16\CoreTypes.vhd @@ -243,5 +243,5 @@ - MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd) + xc6slx100-3fgg484 0 @@ -249,5 +249,5 @@ 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002c1000000020000000000000000000000000000000064ffffffff000000810000000000000002000002c10000000100000000000000000000000100000000 false - MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd) + xc6slx100-3fgg484 @@ -257,5 +257,5 @@ - Compile HDL Simulation Libraries + 0 @@ -263,5 +263,5 @@ 000000ff0000000000000001000000010000000000000000000000000000000000000000000000010d000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010d0000000100000000 false - Compile HDL Simulation Libraries + Index: /PROJECT_CORE_MPI/CORE_MPI/TRUNK/iseconfig/MultiMPITest.xreport =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/iseconfig/MultiMPITest.xreport (revision 17) +++ /PROJECT_CORE_MPI/CORE_MPI/TRUNK/iseconfig/MultiMPITest.xreport (revision 18) @@ -2,5 +2,5 @@
- 2012-11-19T10:27:50 + 2012-11-29T18:13:05 MultiMPITest 2012-11-05T16:48:15 Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/isim.cmd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/isim.cmd (revision 17) +++ (revision ) @@ -1,2 +1,0 @@ -onerror {resume} -run 200 ns; Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/test_xbar_8x8_stx_beh.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/test_xbar_8x8_stx_beh.prj (revision 17) +++ (revision ) @@ -1,23 +1,0 @@ -vhdl NocLib "../SWITCH_GENERIC_16_16/CoreTypes.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/RAM_256.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Arbiter.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD" -vhdl NocLib "../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Crossbit.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Scheduler.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/Crossbar.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" -vhdl NocLib "../SWITCH_GENERIC_16_16/test_xbar_8x8.vhd" Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/webtalk_pn.xml =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/webtalk_pn.xml (revision 17) +++ (revision ) @@ -1,51 +1,0 @@ - - - - -
- - - - -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - Index: OJECT_CORE_MPI/CORE_MPI/TRUNK/xilinxsim.ini =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/TRUNK/xilinxsim.ini (revision 17) +++ (revision ) @@ -1,2 +1,0 @@ -NocLib=isim/NocLib -work=isim/work