Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Arbiter.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Arbiter.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Arbiter.vhd	(revision 20)
@@ -0,0 +1,83 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: Kiegaing Emmanuel GEL EN5
+-- 
+-- Create Date:    18:18:09 03/19/2011 
+-- Design Name: 
+-- Module Name:    Arbiter - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+-- cellule d'arbitrage de l'ordonnanceur du crossbar
+-- Dependencies: 
+--
+-- Revision: 1.0
+-- a été ajouté le signal fifo_full pour inclure la codition buffer pas plein dans
+-- la cellules d'arbitrage
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Arbiter is
+    Port ( P: in  STD_LOGIC;--vecteur de priorité
+			  Fifo_full : in STD_LOGIC;
+           Request : in  STD_LOGIC;-- demande de permission
+           West : in  STD_LOGIC;-- verouillage ouest
+           North : in  STD_LOGIC;--etc
+           Grant : out  STD_LOGIC;-- validation de la transition
+           East : out  STD_LOGIC;
+           South : out  STD_LOGIC);
+end Arbiter;
+
+architecture Behavioral of Arbiter is
+-- modelisation comportementale 3 LUT après synthèse
+-- ce module peut aussi facilement s'implémenter en flot de données
+signal grant_signal : STD_LOGIC; 
+--signal not_fifo_full : STD_LOGIC;
+signal Mask : STD_LOGIC;
+begin
+--Grant<=grant_signal; -- Grant n'a pas été déclarée InOut
+Mask <= P AND (not Fifo_full);
+process(Mask, Request, North, West)-- genere de la logique purement combinatoire
+begin
+if Mask ='0' then --cellule inactive
+Grant <= '0';-- pas d'autorisation
+South <= '1';
+East <= '1';
+   else
+	Grant <= Request And North And West;
+	South <= (North) And (Not (Request And North And West));	
+	East  <= (West)  And (Not (Request And North And West));
+end if;
+end process;
+
+end Behavioral;
+--modélidation flot de données elle semble plus efficace 3 LUT
+--architecture Behavioral of Arbiter is
+--signal x, x1, x2, x3, x4, x5: STD_LOGIC; 
+--begin
+----equations logiques de la cellule
+--x  <= Mask And Request;
+--x1 <= North;
+--x2 <= West;
+--x3 <= x And x1 And x2;
+--x4 <= x1 And (Not x3);
+--x5 <= x2 And (Not x3);
+--South <= x4 Or (Not Mask);
+--East  <= x5 Or (Not Mask);
+--Grant <= x3;
+--
+--end Behavioral;
+
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Backup_prj.bat
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Backup_prj.bat	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Backup_prj.bat	(revision 20)
@@ -0,0 +1,34 @@
+@Echo off
+rem Fichier permettant de copier l'ensemble des
+rem sources du projet vers une autre destination
+rem
+Echo donner le chemin de destination des fichiers à copier svp (defaut=D:\Core_MPI\NOC)
+set Dest=
+set /P Dest="Defaut D:\SCORE_MPI\NOC"
+
+if "%Dest%" == "" goto defaut
+if "%Dest%" == " " goto defaut
+ goto normal
+:defaut
+set dest=D:\SCORE_MPI\NOC
+:normal
+echo la destination est
+echo "%Dest%"
+
+If exist %Dest% goto lancecopie
+Echo Attention la destination n'existe pas
+Echo nous tentons de la créer
+MD %Dest%
+If exist %Dest%\nul goto lancecopie
+Echo Création impossible du dossier. 
+Echo le dossier parent n'existe pas ou le chemin est invalide
+Echo vous devez le faire vous-même ou donner un chemin valide.
+goto fin
+:lancecopie
+copy *.vhd %Dest%\
+copy *.wcfg %Dest%\
+copy *.prj %Dest%\
+copy *.ucf %Dest%\
+:fin
+pause
+Echo fin de la copie
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/CoreTypes.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/CoreTypes.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/CoreTypes.vhd	(revision 20)
@@ -0,0 +1,232 @@
+  --	Package File Template
+--
+--	Purpose: This package defines supplemental types, subtypes, 
+--		 constants, and components 
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package CoreTypes is
+CONSTANT Word :POSITIVE:= 8;
+CONSTANT ADRLEN:POSITIVE:=16;
+CONSTANT LZFILL :std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0');--indique le nombre de zero à utiliser pour completer le bus de données lorsque la longueur restante du bus d'adresse est inférueure à la largeur du bus de données
+CONSTANT IADR0 : NATURAL :=2; --Adresse basse de l'instruction
+CONSTANT IADR1 : natural :=3;
+CONSTANT CORE_BASE_ADR :natural range 0 to 65535:=4096;
+CONSTANT CORE_UPPER_ADR : natural range 0 to 255:=16;
+CONSTANT CORE_GET_ADR:natural:=CORE_BASE_ADR+526;
+CONSTANT CORE_PUT_ADR :natural:=CORE_BASE_ADR+516;
+CONSTANT core_INIT_ADR : natural:=CORE_BASE_ADR+512;
+CONSTANT CORE_WCREATE_ADR : natural := CORE_BASE_ADR+536;
+CONSTANT CORE_WCOMPL_ADR : natural := CORE_BASE_ADR+546;
+CONSTANT CORE_WPOST_ADR : natural := CORE_BASE_ADR+556;
+CONSTANT CORE_WWAIT_ADR : natural := CORE_BASE_ADR+566;
+CONSTANT CORE_Rank2port_BASE :NATURAL:=32;
+CONSTANT WIN0_ADR :natural :=4;
+CONSTANT WIN1_ADR :natural :=14;
+CONSTANT WIN2_ADR :natural :=24;
+CONSTANT WIN3_ADR :natural :=34;
+CONSTANT GETPORTID : std_logic_vector(3 downto 0):="0001";
+  
+  type Typ_PortIO is
+   array(natural range <>) of std_logic_vector( Word-1 downto 0);
+	
+	type memory is 
+	array (natural range <>) of std_logic_vector(word-1 downto 0);
+	
+type Core_io is
+	record
+		Instr_en :std_logic;  -- active une instruction MPI
+		Instr_ack :std_logic;-- signal la prise en compte de l'instruction
+		Ready   :std_logic;-- indique que la dernière fonction est terminée
+		InitOk :std_logic; -- l'initialisation est terminée
+		Hold_Req :std_logic;--Demande DMA 
+		Hold_Ack :std_logic;-- Autorisation DMA
+		MemBusy :std_logic;-- active le refus de DMA (1 -> ignoré la requête DMA) 
+		RamSel :std_logic;-- indique le statut de la RAM (0 ->dispo 1->occupé par Core_MPI)
+		IntState1 : natural range 0 to 255; --permet de stocker l'état des MAE interne dans les procédures
+		IntState2 : natural range 0 to 255;
+		Instruction :std_logic_vector (word-1 downto 0);
+		WinId :natural range  0 to 255; --stocke le dernier Id utilisé par WinCreate
+		IsMain : std_logic; -- indique si la librairie est principal
+		Rank : natural range 0 to 16; --donne le rang du processus courant
+end record;
+
+type typ_dpram is
+record
+			  
+           
+	    clk_wr :  STD_LOGIC;
+	    clk_rd :  STD_LOGIC;
+		we     :  STD_LOGIC;
+		ena    :  STD_LOGIC;
+		enb    :  STD_LOGIC;
+		addr_wr:  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
+		addr_rd :  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
+		data_in  :  STD_LOGIC_VECTOR (Word-1 downto 0);
+		data_out :  STD_LOGIC_VECTOR (Word-1 downto 0); 
+			  
+           		  
+end record;        
+type Typ_MPIPort_in is
+record
+			  instruction :   STD_LOGIC_VECTOR (Word -1 downto 0);
+           instruction_en :  STD_LOGIC;
+           		  
+
+			  packet_ack : std_logic;
+           ram_data_out :  STD_LOGIC_VECTOR (Word-1 downto 0);
+			  
+			  hold_ack       :  STD_Logic;  --autorisation par l'application
+			  clk :  STD_LOGIC;
+           reset :  STD_LOGIC;
+           		  
+end record;
+type Typ_MPIPort_out is
+record		  
+          
+			  
+           ram_we :  STD_LOGIC;
+			  ram_en :  STD_LOGIC;
+			  ram_data_in : STD_LOGIC_VECTOR (WORD-1 downto 0);
+           ram_address_rd :  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
+			  ram_address_wr :  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
+			  packet_received : STD_LOGIC;
+			  barrier_completed : STD_LOGIC;
+           instruction_fifo_full : STD_LOGIC;
+			  PushOut :  STD_LOGIC_VECTOR (WORD-1 downto 0);
+			   
+           hold_req       : STD_Logic;  --requete vers application
+end record;
+
+Type Ar_MPIPort_In is array (positive range <>) of Typ_MPIPort_in;
+Type Ar_MPIPort_out is array (positive range <>) of Typ_MPIPort_out;
+
+-- Declare constants
+
+--  constant <constant_name>		: time := <time_unit> ns;
+--  constant <constant_name>		: integer := <value>;
+-- 
+-- Declare functions and procedure
+Component  SWITCH_GEN is     
+ generic(number_of_ports : positive := 8);
+     port(
+	        -- ports d'entree
+           Port_in : in typ_portIO(1 to number_of_ports) ;
+--			  
+			 
+			  -- port de sortie
+			  Port_out : out  typ_portIO(1 to number_of_ports);
+--			  
+			  -- signaux de controle
+			  cmd_in_en : in std_logic_vector(number_of_ports downto 1);
+			  data_in_en : in std_logic_vector(number_of_ports downto 1);
+			  data_out_en : in std_logic_vector(number_of_ports downto 1);
+			  fifo_in_full : out std_logic_vector(number_of_ports downto 1);
+			  fifo_in_empty : out std_logic_vector(number_of_ports downto 1);
+			  data_available : out std_logic_vector(number_of_ports downto 1);
+			  clk       : in   STD_LOGIC;
+			  reset     : in   STD_LOGIC);
+end component SWITCH_GEN;
+-- déclaration des fonctions utilisées
+ 
+ FUNCTION all_ones(s1:std_logic_vector) return std_logic; 
+  --This function returns if the input vector has all ones and no zeros
+ FUNCTION all_zeros(s1:std_logic_vector) return std_logic; 
+  --This function returns if the input vector has all zeros and no ones
+ FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector; 
+  --This function increments an std_logic_vector type by '1', without 
+  --using any arithmatic
+
+  FUNCTION dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector; 
+  --This function decrements an std_logic_vector type by '1', without 
+  --using any arithmatic
+  FUNCTION Rol_Vec(s1:std_logic_vector) return std_logic_vector;
+  --renvoie un std_logic_vector de taille ADRLEN
+  Function Stdlv (s1 : natural ) return std_logic_vector;
+end CoreTypes;
+
+
+Package body CoreTypes is
+
+
+FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is 
+                  --this function increments a std_logic_vector type by '1' 
+        VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
+        VARIABLE tb : std_logic_vector(s1'high downto s1'low); 
+        BEGIN 
+        tb(s1'low) := en; 
+        V := s1; 
+        for i in (V'low + 1) to V'high loop 
+            tb(i) := V(i - 1) and tb(i -1); 
+        end loop; 
+        for i in V'low to V'high loop 
+            if(tb(i) = '1') then 
+                V(i) := not(V(i)); 
+            end if; 
+        end loop; 
+        return V; 
+        end incr_vec; -- end function
+
+FUNCTION  dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is 
+                  --this function decrements a std_logic_vector type by '1' 
+        VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
+        VARIABLE tb : std_logic_vector(s1'high downto s1'low); 
+        BEGIN 
+        tb(s1'low) := not(en); 
+        V := s1; 
+        for i in (V'low + 1) to V'high loop 
+            tb(i) := V(i - 1) or tb(i -1); 
+        end loop; 
+        for i in V'low to V'high loop 
+            if(tb(i) = '0') then 
+                V(i) := not(V(i)); 
+            end if; 
+        end loop; 
+        return V; 
+        end dcr_vec; -- end function
+FUNCTION all_ones(s1:std_logic_vector) return std_logic is 
+                  --this function tells if all bits of a vector are '1' 
+                  --return value Z is '1', then vector has all 1 bits 
+        --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
+        VARIABLE Z : std_logic; 
+        BEGIN 
+        Z := s1(s1'low); 
+        FOR i IN (s1'low+1) to s1'high LOOP 
+            Z := Z AND s1(i); 
+        END LOOP; 
+        RETURN Z; 
+        END all_ones; -- end function
+FUNCTION all_zeros(s1:std_logic_vector) return std_logic is 
+                  --this function tells if all bits of a vector are '0' 
+                  --return value Z if '1', then vector has all 0 bits 
+        --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
+        VARIABLE Z : std_logic; 
+        BEGIN 
+        Z := '0'; 
+        FOR i IN (s1'low) to s1'high LOOP 
+            Z := Z OR s1(i); 
+        END LOOP; 
+        RETURN not(Z); 
+        END all_zeros; -- end function
+		  
+FUNCTION Rol_Vec(s1:std_logic_vector) return std_logic_vector is
+--cette fonction fait roter un STD_logic d'un pas vers la gauche
+VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
+        VARIABLE lb : std_logic :=s1(s1'left);
+        BEGIN 
+     
+        for i in V'left  downto (V'right+1) loop 
+            V(i) := s1(i - 1) ; 
+        end loop; 
+        V(V'right):=lb;
+        return V; 
+        end Rol_vec;
+ Function Stdlv (s1 : natural ) return std_logic_vector is
+VARIABLE V : std_logic_vector(ADRLEN-1 downto 0)
+ begin
+	V:=std_logic_vector(to_unsigned(s1,ADRLEN));
+	return V;
+ end stdlv;
+end CoreTypes;
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Crossbar.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Crossbar.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Crossbar.vhd	(revision 20)
@@ -0,0 +1,3876 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL
+-- 
+-- Create Date:    11:48:18 06/19/2011 
+-- Design Name: 
+-- Module Name:    Crossbar - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: module implémentant les crossbar
+-- ce module instacie les crossbar 1 bit du fichier crossbit.vhd
+--  
+-- CROSSBAR GENERIQUE
+-- Revision: 1.0
+-- a été retiré les signaux inutilisées comme fp, port_source, etc...
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library NocLib ;
+use NocLib.CoreTypes.all;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Crossbar is
+    generic
+	      (
+			  number_of_crossbar_ports: positive := 4
+			);
+    Port ( Port1_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port2_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port3_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port4_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+			  Port5_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port6_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port7_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port8_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+			  Port9_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port10_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port11_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port12_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+			  Port13_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port14_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port15_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port16_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+			  
+			  Port1_pulse_in : in std_logic;
+			  Port2_pulse_in : in std_logic;
+			  Port3_pulse_in : in std_logic;
+			  Port4_pulse_in : in std_logic;
+			  Port5_pulse_in : in std_logic;
+			  Port6_pulse_in : in std_logic;
+			  Port7_pulse_in : in std_logic;
+			  Port8_pulse_in : in std_logic;
+			  Port9_pulse_in : in std_logic;
+			  Port10_pulse_in : in std_logic;
+			  Port11_pulse_in : in std_logic;
+			  Port12_pulse_in : in std_logic;
+			  Port13_pulse_in : in std_logic;
+			  Port14_pulse_in : in std_logic;
+			  Port15_pulse_in : in std_logic;
+			  Port16_pulse_in : in std_logic;
+			  
+			  Port1_pulse_out : out std_logic;
+			  Port2_pulse_out : out std_logic;
+			  Port3_pulse_out : out std_logic;
+			  Port4_pulse_out : out std_logic;
+			  Port5_pulse_out : out std_logic;
+			  Port6_pulse_out : out std_logic;
+			  Port7_pulse_out : out std_logic;
+			  Port8_pulse_out : out std_logic;
+			  Port9_pulse_out : out std_logic;
+			  Port10_pulse_out : out std_logic;
+			  Port11_pulse_out : out std_logic;
+			  Port12_pulse_out : out std_logic;
+			  Port13_pulse_out : out std_logic;
+			  Port14_pulse_out : out std_logic;
+			  Port15_pulse_out : out std_logic;
+			  Port16_pulse_out : out std_logic;
+			  
+			  Port1_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port2_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port3_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port4_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
+			  Port5_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port6_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port7_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port8_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
+			  Port9_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port10_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port11_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port12_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
+			  Port13_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port14_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port15_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port16_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
+			  
+           Ctrl : in  STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1)
+            );        
+end Crossbar;
+
+architecture Behavioral of Crossbar is
+
+-- declaration du crossbar un bit instanciés pour former les crossbars
+COMPONENT Crossbit
+	generic
+	      (
+			  number_of_ports : positive := 4
+			);
+    Port ( Control : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
+           Data_In : in  STD_LOGIC_VECTOR (number_of_ports downto 1);
+           Data_out : out  STD_LOGIC_VECTOR (number_of_ports downto 1));
+	END COMPONENT;	
+	
+begin
+-- La matrice interconnectee
+-- le circuit genere depend du parametre generique nombre de ports
+
+--======================crossbar 2 ports=======================
+
+crossbar2x2 : if number_of_crossbar_ports = 2 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7)
+
+           );
+-- crossbit du pulse_out 2 ports 
+
+   Pulse_out_Crossbit2: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out 
+
+           );
+end generate crossbar2x2;
+
+
+--======================crossbar 3 ports=======================
+
+crossbar3x3 : if number_of_crossbar_ports = 3 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7)
+
+           );
+-- crossbit du pulse_out 3 ports 
+
+   Pulse_out_Crossbit3: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out 
+
+           );
+end generate crossbar3x3;
+
+
+--======================crossbar 4 ports=======================
+
+crossbar4x4 : if number_of_crossbar_ports = 4 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7)
+
+           );
+-- crossbit du pulse_out 4 ports 
+
+   Pulse_out_Crossbit4: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out 
+
+           );
+end generate crossbar4x4;
+
+
+--======================crossbar 5 ports=======================
+
+crossbar5x5 : if number_of_crossbar_ports = 5 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7)
+
+           );
+-- crossbit du pulse_out 5 ports 
+
+   Pulse_out_Crossbit5: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out 
+
+           );
+end generate crossbar5x5;
+
+
+--======================crossbar 6 ports=======================
+
+crossbar6x6 : if number_of_crossbar_ports = 6 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7)
+
+           );
+-- crossbit du pulse_out 6 ports 
+
+   Pulse_out_Crossbit6: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out 
+
+           );
+end generate crossbar6x6;
+
+
+--======================crossbar 7 ports=======================
+
+crossbar7x7 : if number_of_crossbar_ports = 7 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7)
+
+           );
+-- crossbit du pulse_out 7 ports 
+
+   Pulse_out_Crossbit7: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out 
+
+           );
+end generate crossbar7x7;
+
+
+--======================crossbar 8 ports=======================
+
+crossbar8x8 : if number_of_crossbar_ports = 8 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7)
+
+           );
+-- crossbit du pulse_out 8 ports 
+
+   Pulse_out_Crossbit8: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out 
+
+           );
+end generate crossbar8x8;
+
+
+--======================crossbar 9 ports=======================
+
+crossbar9x9 : if number_of_crossbar_ports = 9 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7)
+
+           );
+-- crossbit du pulse_out 9 ports 
+
+   Pulse_out_Crossbit9: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out 
+
+           );
+end generate crossbar9x9;
+
+
+--======================crossbar 10 ports=======================
+
+crossbar10x10 : if number_of_crossbar_ports = 10 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_In(10) => Port10_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0),
+       Data_out(10)=> Port10_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_In(10) => Port10_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1),
+       Data_out(10)=> Port10_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_In(10) => Port10_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2),
+       Data_out(10)=> Port10_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_In(10) => Port10_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3),
+       Data_out(10)=> Port10_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_In(10) => Port10_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4),
+       Data_out(10)=> Port10_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_In(10) => Port10_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5),
+       Data_out(10)=> Port10_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_In(10) => Port10_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6),
+       Data_out(10)=> Port10_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_In(10) => Port10_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7),
+       Data_out(10)=> Port10_out(7)
+
+           );
+-- crossbit du pulse_out 10 ports 
+
+   Pulse_out_Crossbit10: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_In(10) => Port10_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out,
+       Data_out(10) => Port10_pulse_out 
+
+           );
+end generate crossbar10x10;
+
+
+--======================crossbar 11 ports=======================
+
+crossbar11x11 : if number_of_crossbar_ports = 11 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_In(10) => Port10_in(0),
+       Data_In(11) => Port11_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0),
+       Data_out(10)=> Port10_out(0),
+       Data_out(11)=> Port11_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_In(10) => Port10_in(1),
+       Data_In(11) => Port11_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1),
+       Data_out(10)=> Port10_out(1),
+       Data_out(11)=> Port11_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_In(10) => Port10_in(2),
+       Data_In(11) => Port11_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2),
+       Data_out(10)=> Port10_out(2),
+       Data_out(11)=> Port11_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_In(10) => Port10_in(3),
+       Data_In(11) => Port11_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3),
+       Data_out(10)=> Port10_out(3),
+       Data_out(11)=> Port11_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_In(10) => Port10_in(4),
+       Data_In(11) => Port11_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4),
+       Data_out(10)=> Port10_out(4),
+       Data_out(11)=> Port11_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_In(10) => Port10_in(5),
+       Data_In(11) => Port11_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5),
+       Data_out(10)=> Port10_out(5),
+       Data_out(11)=> Port11_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_In(10) => Port10_in(6),
+       Data_In(11) => Port11_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6),
+       Data_out(10)=> Port10_out(6),
+       Data_out(11)=> Port11_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_In(10) => Port10_in(7),
+       Data_In(11) => Port11_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7),
+       Data_out(10)=> Port10_out(7),
+       Data_out(11)=> Port11_out(7)
+
+           );
+-- crossbit du pulse_out 11 ports 
+
+   Pulse_out_Crossbit11: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_In(10) => Port10_pulse_in,
+       Data_In(11) => Port11_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out,
+       Data_out(10) => Port10_pulse_out,
+       Data_out(11) => Port11_pulse_out 
+
+           );
+end generate crossbar11x11;
+
+
+--======================crossbar 12 ports=======================
+
+crossbar12x12 : if number_of_crossbar_ports = 12 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_In(10) => Port10_in(0),
+       Data_In(11) => Port11_in(0),
+       Data_In(12) => Port12_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0),
+       Data_out(10)=> Port10_out(0),
+       Data_out(11)=> Port11_out(0),
+       Data_out(12)=> Port12_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_In(10) => Port10_in(1),
+       Data_In(11) => Port11_in(1),
+       Data_In(12) => Port12_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1),
+       Data_out(10)=> Port10_out(1),
+       Data_out(11)=> Port11_out(1),
+       Data_out(12)=> Port12_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_In(10) => Port10_in(2),
+       Data_In(11) => Port11_in(2),
+       Data_In(12) => Port12_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2),
+       Data_out(10)=> Port10_out(2),
+       Data_out(11)=> Port11_out(2),
+       Data_out(12)=> Port12_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_In(10) => Port10_in(3),
+       Data_In(11) => Port11_in(3),
+       Data_In(12) => Port12_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3),
+       Data_out(10)=> Port10_out(3),
+       Data_out(11)=> Port11_out(3),
+       Data_out(12)=> Port12_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_In(10) => Port10_in(4),
+       Data_In(11) => Port11_in(4),
+       Data_In(12) => Port12_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4),
+       Data_out(10)=> Port10_out(4),
+       Data_out(11)=> Port11_out(4),
+       Data_out(12)=> Port12_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_In(10) => Port10_in(5),
+       Data_In(11) => Port11_in(5),
+       Data_In(12) => Port12_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5),
+       Data_out(10)=> Port10_out(5),
+       Data_out(11)=> Port11_out(5),
+       Data_out(12)=> Port12_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_In(10) => Port10_in(6),
+       Data_In(11) => Port11_in(6),
+       Data_In(12) => Port12_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6),
+       Data_out(10)=> Port10_out(6),
+       Data_out(11)=> Port11_out(6),
+       Data_out(12)=> Port12_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_In(10) => Port10_in(7),
+       Data_In(11) => Port11_in(7),
+       Data_In(12) => Port12_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7),
+       Data_out(10)=> Port10_out(7),
+       Data_out(11)=> Port11_out(7),
+       Data_out(12)=> Port12_out(7)
+
+           );
+-- crossbit du pulse_out 12 ports 
+
+   Pulse_out_Crossbit12: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_In(10) => Port10_pulse_in,
+       Data_In(11) => Port11_pulse_in,
+       Data_In(12) => Port12_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out,
+       Data_out(10) => Port10_pulse_out,
+       Data_out(11) => Port11_pulse_out,
+       Data_out(12) => Port12_pulse_out 
+
+           );
+end generate crossbar12x12;
+
+
+--======================crossbar 13 ports=======================
+
+crossbar13x13 : if number_of_crossbar_ports = 13 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_In(10) => Port10_in(0),
+       Data_In(11) => Port11_in(0),
+       Data_In(12) => Port12_in(0),
+       Data_In(13) => Port13_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0),
+       Data_out(10)=> Port10_out(0),
+       Data_out(11)=> Port11_out(0),
+       Data_out(12)=> Port12_out(0),
+       Data_out(13)=> Port13_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_In(10) => Port10_in(1),
+       Data_In(11) => Port11_in(1),
+       Data_In(12) => Port12_in(1),
+       Data_In(13) => Port13_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1),
+       Data_out(10)=> Port10_out(1),
+       Data_out(11)=> Port11_out(1),
+       Data_out(12)=> Port12_out(1),
+       Data_out(13)=> Port13_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_In(10) => Port10_in(2),
+       Data_In(11) => Port11_in(2),
+       Data_In(12) => Port12_in(2),
+       Data_In(13) => Port13_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2),
+       Data_out(10)=> Port10_out(2),
+       Data_out(11)=> Port11_out(2),
+       Data_out(12)=> Port12_out(2),
+       Data_out(13)=> Port13_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_In(10) => Port10_in(3),
+       Data_In(11) => Port11_in(3),
+       Data_In(12) => Port12_in(3),
+       Data_In(13) => Port13_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3),
+       Data_out(10)=> Port10_out(3),
+       Data_out(11)=> Port11_out(3),
+       Data_out(12)=> Port12_out(3),
+       Data_out(13)=> Port13_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_In(10) => Port10_in(4),
+       Data_In(11) => Port11_in(4),
+       Data_In(12) => Port12_in(4),
+       Data_In(13) => Port13_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4),
+       Data_out(10)=> Port10_out(4),
+       Data_out(11)=> Port11_out(4),
+       Data_out(12)=> Port12_out(4),
+       Data_out(13)=> Port13_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_In(10) => Port10_in(5),
+       Data_In(11) => Port11_in(5),
+       Data_In(12) => Port12_in(5),
+       Data_In(13) => Port13_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5),
+       Data_out(10)=> Port10_out(5),
+       Data_out(11)=> Port11_out(5),
+       Data_out(12)=> Port12_out(5),
+       Data_out(13)=> Port13_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_In(10) => Port10_in(6),
+       Data_In(11) => Port11_in(6),
+       Data_In(12) => Port12_in(6),
+       Data_In(13) => Port13_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6),
+       Data_out(10)=> Port10_out(6),
+       Data_out(11)=> Port11_out(6),
+       Data_out(12)=> Port12_out(6),
+       Data_out(13)=> Port13_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_In(10) => Port10_in(7),
+       Data_In(11) => Port11_in(7),
+       Data_In(12) => Port12_in(7),
+       Data_In(13) => Port13_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7),
+       Data_out(10)=> Port10_out(7),
+       Data_out(11)=> Port11_out(7),
+       Data_out(12)=> Port12_out(7),
+       Data_out(13)=> Port13_out(7)
+
+           );
+-- crossbit du pulse_out 13 ports 
+
+   Pulse_out_Crossbit13: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_In(10) => Port10_pulse_in,
+       Data_In(11) => Port11_pulse_in,
+       Data_In(12) => Port12_pulse_in,
+       Data_In(13) => Port13_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out,
+       Data_out(10) => Port10_pulse_out,
+       Data_out(11) => Port11_pulse_out,
+       Data_out(12) => Port12_pulse_out,
+       Data_out(13) => Port13_pulse_out 
+
+           );
+end generate crossbar13x13;
+
+
+--======================crossbar 14 ports=======================
+
+crossbar14x14 : if number_of_crossbar_ports = 14 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_In(10) => Port10_in(0),
+       Data_In(11) => Port11_in(0),
+       Data_In(12) => Port12_in(0),
+       Data_In(13) => Port13_in(0),
+       Data_In(14) => Port14_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0),
+       Data_out(10)=> Port10_out(0),
+       Data_out(11)=> Port11_out(0),
+       Data_out(12)=> Port12_out(0),
+       Data_out(13)=> Port13_out(0),
+       Data_out(14)=> Port14_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_In(10) => Port10_in(1),
+       Data_In(11) => Port11_in(1),
+       Data_In(12) => Port12_in(1),
+       Data_In(13) => Port13_in(1),
+       Data_In(14) => Port14_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1),
+       Data_out(10)=> Port10_out(1),
+       Data_out(11)=> Port11_out(1),
+       Data_out(12)=> Port12_out(1),
+       Data_out(13)=> Port13_out(1),
+       Data_out(14)=> Port14_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_In(10) => Port10_in(2),
+       Data_In(11) => Port11_in(2),
+       Data_In(12) => Port12_in(2),
+       Data_In(13) => Port13_in(2),
+       Data_In(14) => Port14_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2),
+       Data_out(10)=> Port10_out(2),
+       Data_out(11)=> Port11_out(2),
+       Data_out(12)=> Port12_out(2),
+       Data_out(13)=> Port13_out(2),
+       Data_out(14)=> Port14_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_In(10) => Port10_in(3),
+       Data_In(11) => Port11_in(3),
+       Data_In(12) => Port12_in(3),
+       Data_In(13) => Port13_in(3),
+       Data_In(14) => Port14_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3),
+       Data_out(10)=> Port10_out(3),
+       Data_out(11)=> Port11_out(3),
+       Data_out(12)=> Port12_out(3),
+       Data_out(13)=> Port13_out(3),
+       Data_out(14)=> Port14_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_In(10) => Port10_in(4),
+       Data_In(11) => Port11_in(4),
+       Data_In(12) => Port12_in(4),
+       Data_In(13) => Port13_in(4),
+       Data_In(14) => Port14_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4),
+       Data_out(10)=> Port10_out(4),
+       Data_out(11)=> Port11_out(4),
+       Data_out(12)=> Port12_out(4),
+       Data_out(13)=> Port13_out(4),
+       Data_out(14)=> Port14_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_In(10) => Port10_in(5),
+       Data_In(11) => Port11_in(5),
+       Data_In(12) => Port12_in(5),
+       Data_In(13) => Port13_in(5),
+       Data_In(14) => Port14_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5),
+       Data_out(10)=> Port10_out(5),
+       Data_out(11)=> Port11_out(5),
+       Data_out(12)=> Port12_out(5),
+       Data_out(13)=> Port13_out(5),
+       Data_out(14)=> Port14_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_In(10) => Port10_in(6),
+       Data_In(11) => Port11_in(6),
+       Data_In(12) => Port12_in(6),
+       Data_In(13) => Port13_in(6),
+       Data_In(14) => Port14_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6),
+       Data_out(10)=> Port10_out(6),
+       Data_out(11)=> Port11_out(6),
+       Data_out(12)=> Port12_out(6),
+       Data_out(13)=> Port13_out(6),
+       Data_out(14)=> Port14_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_In(10) => Port10_in(7),
+       Data_In(11) => Port11_in(7),
+       Data_In(12) => Port12_in(7),
+       Data_In(13) => Port13_in(7),
+       Data_In(14) => Port14_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7),
+       Data_out(10)=> Port10_out(7),
+       Data_out(11)=> Port11_out(7),
+       Data_out(12)=> Port12_out(7),
+       Data_out(13)=> Port13_out(7),
+       Data_out(14)=> Port14_out(7)
+
+           );
+-- crossbit du pulse_out 14 ports 
+
+   Pulse_out_Crossbit14: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_In(10) => Port10_pulse_in,
+       Data_In(11) => Port11_pulse_in,
+       Data_In(12) => Port12_pulse_in,
+       Data_In(13) => Port13_pulse_in,
+       Data_In(14) => Port14_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out,
+       Data_out(10) => Port10_pulse_out,
+       Data_out(11) => Port11_pulse_out,
+       Data_out(12) => Port12_pulse_out,
+       Data_out(13) => Port13_pulse_out,
+       Data_out(14) => Port14_pulse_out 
+
+           );
+end generate crossbar14x14;
+
+
+--======================crossbar 15 ports=======================
+
+crossbar15x15 : if number_of_crossbar_ports = 15 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_In(10) => Port10_in(0),
+       Data_In(11) => Port11_in(0),
+       Data_In(12) => Port12_in(0),
+       Data_In(13) => Port13_in(0),
+       Data_In(14) => Port14_in(0),
+       Data_In(15) => Port15_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0),
+       Data_out(10)=> Port10_out(0),
+       Data_out(11)=> Port11_out(0),
+       Data_out(12)=> Port12_out(0),
+       Data_out(13)=> Port13_out(0),
+       Data_out(14)=> Port14_out(0),
+       Data_out(15)=> Port15_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_In(10) => Port10_in(1),
+       Data_In(11) => Port11_in(1),
+       Data_In(12) => Port12_in(1),
+       Data_In(13) => Port13_in(1),
+       Data_In(14) => Port14_in(1),
+       Data_In(15) => Port15_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1),
+       Data_out(10)=> Port10_out(1),
+       Data_out(11)=> Port11_out(1),
+       Data_out(12)=> Port12_out(1),
+       Data_out(13)=> Port13_out(1),
+       Data_out(14)=> Port14_out(1),
+       Data_out(15)=> Port15_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_In(10) => Port10_in(2),
+       Data_In(11) => Port11_in(2),
+       Data_In(12) => Port12_in(2),
+       Data_In(13) => Port13_in(2),
+       Data_In(14) => Port14_in(2),
+       Data_In(15) => Port15_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2),
+       Data_out(10)=> Port10_out(2),
+       Data_out(11)=> Port11_out(2),
+       Data_out(12)=> Port12_out(2),
+       Data_out(13)=> Port13_out(2),
+       Data_out(14)=> Port14_out(2),
+       Data_out(15)=> Port15_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_In(10) => Port10_in(3),
+       Data_In(11) => Port11_in(3),
+       Data_In(12) => Port12_in(3),
+       Data_In(13) => Port13_in(3),
+       Data_In(14) => Port14_in(3),
+       Data_In(15) => Port15_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3),
+       Data_out(10)=> Port10_out(3),
+       Data_out(11)=> Port11_out(3),
+       Data_out(12)=> Port12_out(3),
+       Data_out(13)=> Port13_out(3),
+       Data_out(14)=> Port14_out(3),
+       Data_out(15)=> Port15_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_In(10) => Port10_in(4),
+       Data_In(11) => Port11_in(4),
+       Data_In(12) => Port12_in(4),
+       Data_In(13) => Port13_in(4),
+       Data_In(14) => Port14_in(4),
+       Data_In(15) => Port15_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4),
+       Data_out(10)=> Port10_out(4),
+       Data_out(11)=> Port11_out(4),
+       Data_out(12)=> Port12_out(4),
+       Data_out(13)=> Port13_out(4),
+       Data_out(14)=> Port14_out(4),
+       Data_out(15)=> Port15_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_In(10) => Port10_in(5),
+       Data_In(11) => Port11_in(5),
+       Data_In(12) => Port12_in(5),
+       Data_In(13) => Port13_in(5),
+       Data_In(14) => Port14_in(5),
+       Data_In(15) => Port15_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5),
+       Data_out(10)=> Port10_out(5),
+       Data_out(11)=> Port11_out(5),
+       Data_out(12)=> Port12_out(5),
+       Data_out(13)=> Port13_out(5),
+       Data_out(14)=> Port14_out(5),
+       Data_out(15)=> Port15_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_In(10) => Port10_in(6),
+       Data_In(11) => Port11_in(6),
+       Data_In(12) => Port12_in(6),
+       Data_In(13) => Port13_in(6),
+       Data_In(14) => Port14_in(6),
+       Data_In(15) => Port15_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6),
+       Data_out(10)=> Port10_out(6),
+       Data_out(11)=> Port11_out(6),
+       Data_out(12)=> Port12_out(6),
+       Data_out(13)=> Port13_out(6),
+       Data_out(14)=> Port14_out(6),
+       Data_out(15)=> Port15_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_In(10) => Port10_in(7),
+       Data_In(11) => Port11_in(7),
+       Data_In(12) => Port12_in(7),
+       Data_In(13) => Port13_in(7),
+       Data_In(14) => Port14_in(7),
+       Data_In(15) => Port15_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7),
+       Data_out(10)=> Port10_out(7),
+       Data_out(11)=> Port11_out(7),
+       Data_out(12)=> Port12_out(7),
+       Data_out(13)=> Port13_out(7),
+       Data_out(14)=> Port14_out(7),
+       Data_out(15)=> Port15_out(7)
+
+           );
+-- crossbit du pulse_out 15 ports 
+
+   Pulse_out_Crossbit15: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_In(10) => Port10_pulse_in,
+       Data_In(11) => Port11_pulse_in,
+       Data_In(12) => Port12_pulse_in,
+       Data_In(13) => Port13_pulse_in,
+       Data_In(14) => Port14_pulse_in,
+       Data_In(15) => Port15_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out,
+       Data_out(10) => Port10_pulse_out,
+       Data_out(11) => Port11_pulse_out,
+       Data_out(12) => Port12_pulse_out,
+       Data_out(13) => Port13_pulse_out,
+       Data_out(14) => Port14_pulse_out,
+       Data_out(15) => Port15_pulse_out 
+
+           );
+end generate crossbar15x15;
+
+
+--======================crossbar 16 ports=======================
+
+crossbar16x16 : if number_of_crossbar_ports = 16 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_In(10) => Port10_in(0),
+       Data_In(11) => Port11_in(0),
+       Data_In(12) => Port12_in(0),
+       Data_In(13) => Port13_in(0),
+       Data_In(14) => Port14_in(0),
+       Data_In(15) => Port15_in(0),
+       Data_In(16) => Port16_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0),
+       Data_out(10)=> Port10_out(0),
+       Data_out(11)=> Port11_out(0),
+       Data_out(12)=> Port12_out(0),
+       Data_out(13)=> Port13_out(0),
+       Data_out(14)=> Port14_out(0),
+       Data_out(15)=> Port15_out(0),
+       Data_out(16)=> Port16_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_In(10) => Port10_in(1),
+       Data_In(11) => Port11_in(1),
+       Data_In(12) => Port12_in(1),
+       Data_In(13) => Port13_in(1),
+       Data_In(14) => Port14_in(1),
+       Data_In(15) => Port15_in(1),
+       Data_In(16) => Port16_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1),
+       Data_out(10)=> Port10_out(1),
+       Data_out(11)=> Port11_out(1),
+       Data_out(12)=> Port12_out(1),
+       Data_out(13)=> Port13_out(1),
+       Data_out(14)=> Port14_out(1),
+       Data_out(15)=> Port15_out(1),
+       Data_out(16)=> Port16_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_In(10) => Port10_in(2),
+       Data_In(11) => Port11_in(2),
+       Data_In(12) => Port12_in(2),
+       Data_In(13) => Port13_in(2),
+       Data_In(14) => Port14_in(2),
+       Data_In(15) => Port15_in(2),
+       Data_In(16) => Port16_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2),
+       Data_out(10)=> Port10_out(2),
+       Data_out(11)=> Port11_out(2),
+       Data_out(12)=> Port12_out(2),
+       Data_out(13)=> Port13_out(2),
+       Data_out(14)=> Port14_out(2),
+       Data_out(15)=> Port15_out(2),
+       Data_out(16)=> Port16_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_In(10) => Port10_in(3),
+       Data_In(11) => Port11_in(3),
+       Data_In(12) => Port12_in(3),
+       Data_In(13) => Port13_in(3),
+       Data_In(14) => Port14_in(3),
+       Data_In(15) => Port15_in(3),
+       Data_In(16) => Port16_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3),
+       Data_out(10)=> Port10_out(3),
+       Data_out(11)=> Port11_out(3),
+       Data_out(12)=> Port12_out(3),
+       Data_out(13)=> Port13_out(3),
+       Data_out(14)=> Port14_out(3),
+       Data_out(15)=> Port15_out(3),
+       Data_out(16)=> Port16_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_In(10) => Port10_in(4),
+       Data_In(11) => Port11_in(4),
+       Data_In(12) => Port12_in(4),
+       Data_In(13) => Port13_in(4),
+       Data_In(14) => Port14_in(4),
+       Data_In(15) => Port15_in(4),
+       Data_In(16) => Port16_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4),
+       Data_out(10)=> Port10_out(4),
+       Data_out(11)=> Port11_out(4),
+       Data_out(12)=> Port12_out(4),
+       Data_out(13)=> Port13_out(4),
+       Data_out(14)=> Port14_out(4),
+       Data_out(15)=> Port15_out(4),
+       Data_out(16)=> Port16_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_In(10) => Port10_in(5),
+       Data_In(11) => Port11_in(5),
+       Data_In(12) => Port12_in(5),
+       Data_In(13) => Port13_in(5),
+       Data_In(14) => Port14_in(5),
+       Data_In(15) => Port15_in(5),
+       Data_In(16) => Port16_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5),
+       Data_out(10)=> Port10_out(5),
+       Data_out(11)=> Port11_out(5),
+       Data_out(12)=> Port12_out(5),
+       Data_out(13)=> Port13_out(5),
+       Data_out(14)=> Port14_out(5),
+       Data_out(15)=> Port15_out(5),
+       Data_out(16)=> Port16_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_In(10) => Port10_in(6),
+       Data_In(11) => Port11_in(6),
+       Data_In(12) => Port12_in(6),
+       Data_In(13) => Port13_in(6),
+       Data_In(14) => Port14_in(6),
+       Data_In(15) => Port15_in(6),
+       Data_In(16) => Port16_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6),
+       Data_out(10)=> Port10_out(6),
+       Data_out(11)=> Port11_out(6),
+       Data_out(12)=> Port12_out(6),
+       Data_out(13)=> Port13_out(6),
+       Data_out(14)=> Port14_out(6),
+       Data_out(15)=> Port15_out(6),
+       Data_out(16)=> Port16_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_In(10) => Port10_in(7),
+       Data_In(11) => Port11_in(7),
+       Data_In(12) => Port12_in(7),
+       Data_In(13) => Port13_in(7),
+       Data_In(14) => Port14_in(7),
+       Data_In(15) => Port15_in(7),
+       Data_In(16) => Port16_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7),
+       Data_out(10)=> Port10_out(7),
+       Data_out(11)=> Port11_out(7),
+       Data_out(12)=> Port12_out(7),
+       Data_out(13)=> Port13_out(7),
+       Data_out(14)=> Port14_out(7),
+       Data_out(15)=> Port15_out(7),
+       Data_out(16)=> Port16_out(7)
+
+           );
+-- crossbit du pulse_out 16 ports 
+
+   Pulse_out_Crossbit16: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_In(10) => Port10_pulse_in,
+       Data_In(11) => Port11_pulse_in,
+       Data_In(12) => Port12_pulse_in,
+       Data_In(13) => Port13_pulse_in,
+       Data_In(14) => Port14_pulse_in,
+       Data_In(15) => Port15_pulse_in,
+       Data_In(16) => Port16_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out,
+       Data_out(10) => Port10_pulse_out,
+       Data_out(11) => Port11_pulse_out,
+       Data_out(12) => Port12_pulse_out,
+       Data_out(13) => Port13_pulse_out,
+       Data_out(14) => Port14_pulse_out,
+       Data_out(15) => Port15_pulse_out,
+       Data_out(16) => Port16_pulse_out 
+
+           );
+end generate crossbar16x16;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Crossbar_summary.html
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Crossbar_summary.html	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Crossbar_summary.html	(revision 20)
@@ -0,0 +1,73 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>GENERIC_16_16 Project Status</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>GENERIC_16_16.ise</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>New</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>Crossbar</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc3s1200e-4fg320</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 11.1</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD>Xilinx Default (unlocked)</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 06/19/2011 - 14:29:40</center>
+</BODY></HTML>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Crossbit.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Crossbit.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Crossbit.vhd	(revision 20)
@@ -0,0 +1,288 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: Kiegaing Emmanuel GEL EN 5
+-- 
+-- Create Date:    01:47 05/06/2011
+-- Design Name: 
+-- Module Name:    Crossbar - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: module implémentant un crosbar d'un bit
+-- ces modules seront instanciés pour faire le switch
+-- module generique
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Crossbit is
+    generic
+	      (
+			  number_of_ports: positive := 4
+			);
+    Port ( Control : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
+			  Data_In : in  STD_LOGIC_VECTOR (number_of_ports downto 1);
+           Data_out : out  STD_LOGIC_VECTOR (number_of_ports downto 1)
+			  );
+end Crossbit;
+
+architecture Behavioral of Crossbit is
+
+begin
+-- element de commutation utilisee dans la matrice interconnecte
+-- le circuit genere depend du parametre generique nombre de ports
+--======================crossbit 2 ports=======================
+
+crossbit2x2 : if number_of_ports = 2 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(3)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(4)));
+end generate crossbit2x2;
+
+
+--======================crossbit 3 ports=======================
+
+crossbit3x3 : if number_of_ports = 3 generate
+
+ 
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(4)) OR (Data_in(3) And Control(7)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(5)) OR (Data_in(3) And Control(8)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(9)));
+end generate crossbit3x3;
+
+
+--======================crossbit 4 ports=======================
+
+crossbit4x4 : if number_of_ports = 4 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(5)) OR (Data_in(3) And Control(9)) OR (Data_in(4) And Control(13)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(10)) OR (Data_in(4) And Control(14)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(11)) OR (Data_in(4) And Control(15)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(12)) OR (Data_in(4) And Control(16)));
+end generate crossbit4x4;
+
+
+--======================crossbit 5 ports=======================
+
+crossbit5x5 : if number_of_ports = 5 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(11)) OR (Data_in(4) And Control(16)) OR (Data_in(5) And Control(21)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(12)) OR (Data_in(4) And Control(17)) OR (Data_in(5) And Control(22)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(13)) OR (Data_in(4) And Control(18)) OR (Data_in(5) And Control(23)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(14)) OR (Data_in(4) And Control(19)) OR (Data_in(5) And Control(24)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(20)) OR (Data_in(5) And Control(25)));
+end generate crossbit5x5;
+
+
+--======================crossbit 6 ports=======================
+
+crossbit6x6 : if number_of_ports = 6 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(13)) OR (Data_in(4) And Control(19)) OR (Data_in(5) And Control(25)) OR (Data_in(6) And Control(31)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(14)) OR (Data_in(4) And Control(20)) OR (Data_in(5) And Control(26)) OR (Data_in(6) And Control(32)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(21)) OR (Data_in(5) And Control(27)) OR (Data_in(6) And Control(33)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(16)) OR (Data_in(4) And Control(22)) OR (Data_in(5) And Control(28)) OR (Data_in(6) And Control(34)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(23)) OR (Data_in(5) And Control(29)) OR (Data_in(6) And Control(35)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(24)) OR (Data_in(5) And Control(30)) OR (Data_in(6) And Control(36)));
+end generate crossbit6x6;
+
+
+--======================crossbit 7 ports=======================
+
+crossbit7x7 : if number_of_ports = 7 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(22)) OR (Data_in(5) And Control(29)) OR (Data_in(6) And Control(36)) OR (Data_in(7) And Control(43)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(16)) OR (Data_in(4) And Control(23)) OR (Data_in(5) And Control(30)) OR (Data_in(6) And Control(37)) OR (Data_in(7) And Control(44)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(24)) OR (Data_in(5) And Control(31)) OR (Data_in(6) And Control(38)) OR (Data_in(7) And Control(45)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(25)) OR (Data_in(5) And Control(32)) OR (Data_in(6) And Control(39)) OR (Data_in(7) And Control(46)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(26)) OR (Data_in(5) And Control(33)) OR (Data_in(6) And Control(40)) OR (Data_in(7) And Control(47)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(27)) OR (Data_in(5) And Control(34)) OR (Data_in(6) And Control(41)) OR (Data_in(7) And Control(48)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(35)) OR (Data_in(6) And Control(42)) OR (Data_in(7) And Control(49)));
+end generate crossbit7x7;
+
+
+--======================crossbit 8 ports=======================
+
+crossbit8x8 : if number_of_ports = 8 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(25)) OR (Data_in(5) And Control(33)) OR (Data_in(6) And Control(41)) OR (Data_in(7) And Control(49)) OR (Data_in(8) And Control(57)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(26)) OR (Data_in(5) And Control(34)) OR (Data_in(6) And Control(42)) OR (Data_in(7) And Control(50)) OR (Data_in(8) And Control(58)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(27)) OR (Data_in(5) And Control(35)) OR (Data_in(6) And Control(43)) OR (Data_in(7) And Control(51)) OR (Data_in(8) And Control(59)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(36)) OR (Data_in(6) And Control(44)) OR (Data_in(7) And Control(52)) OR (Data_in(8) And Control(60)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(29)) OR (Data_in(5) And Control(37)) OR (Data_in(6) And Control(45)) OR (Data_in(7) And Control(53)) OR (Data_in(8) And Control(61)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(30)) OR (Data_in(5) And Control(38)) OR (Data_in(6) And Control(46)) OR (Data_in(7) And Control(54)) OR (Data_in(8) And Control(62)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(39)) OR (Data_in(6) And Control(47)) OR (Data_in(7) And Control(55)) OR (Data_in(8) And Control(63)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(40)) OR (Data_in(6) And Control(48)) OR (Data_in(7) And Control(56)) OR (Data_in(8) And Control(64)));
+end generate crossbit8x8;
+
+
+--======================crossbit 9 ports=======================
+
+crossbit9x9 : if number_of_ports = 9 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(37)) OR (Data_in(6) And Control(46)) OR (Data_in(7) And Control(55)) OR (Data_in(8) And Control(64)) OR (Data_in(9) And Control(73)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(29)) OR (Data_in(5) And Control(38)) OR (Data_in(6) And Control(47)) OR (Data_in(7) And Control(56)) OR (Data_in(8) And Control(65)) OR (Data_in(9) And Control(74)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(30)) OR (Data_in(5) And Control(39)) OR (Data_in(6) And Control(48)) OR (Data_in(7) And Control(57)) OR (Data_in(8) And Control(66)) OR (Data_in(9) And Control(75)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(40)) OR (Data_in(6) And Control(49)) OR (Data_in(7) And Control(58)) OR (Data_in(8) And Control(67)) OR (Data_in(9) And Control(76)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(41)) OR (Data_in(6) And Control(50)) OR (Data_in(7) And Control(59)) OR (Data_in(8) And Control(68)) OR (Data_in(9) And Control(77)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(33)) OR (Data_in(5) And Control(42)) OR (Data_in(6) And Control(51)) OR (Data_in(7) And Control(60)) OR (Data_in(8) And Control(69)) OR (Data_in(9) And Control(78)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(43)) OR (Data_in(6) And Control(52)) OR (Data_in(7) And Control(61)) OR (Data_in(8) And Control(70)) OR (Data_in(9) And Control(79)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(44)) OR (Data_in(6) And Control(53)) OR (Data_in(7) And Control(62)) OR (Data_in(8) And Control(71)) OR (Data_in(9) And Control(80)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(54)) OR (Data_in(7) And Control(63)) OR (Data_in(8) And Control(72)) OR (Data_in(9) And Control(81)));
+end generate crossbit9x9;
+
+
+--======================crossbit 10 ports=======================
+
+crossbit10x10 : if number_of_ports = 10 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(41)) OR (Data_in(6) And Control(51)) OR (Data_in(7) And Control(61)) OR (Data_in(8) And Control(71)) OR (Data_in(9) And Control(81)) OR (Data_in(10) And Control(91)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(42)) OR (Data_in(6) And Control(52)) OR (Data_in(7) And Control(62)) OR (Data_in(8) And Control(72)) OR (Data_in(9) And Control(82)) OR (Data_in(10) And Control(92)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(33)) OR (Data_in(5) And Control(43)) OR (Data_in(6) And Control(53)) OR (Data_in(7) And Control(63)) OR (Data_in(8) And Control(73)) OR (Data_in(9) And Control(83)) OR (Data_in(10) And Control(93)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(44)) OR (Data_in(6) And Control(54)) OR (Data_in(7) And Control(64)) OR (Data_in(8) And Control(74)) OR (Data_in(9) And Control(84)) OR (Data_in(10) And Control(94)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(55)) OR (Data_in(7) And Control(65)) OR (Data_in(8) And Control(75)) OR (Data_in(9) And Control(85)) OR (Data_in(10) And Control(95)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(46)) OR (Data_in(6) And Control(56)) OR (Data_in(7) And Control(66)) OR (Data_in(8) And Control(76)) OR (Data_in(9) And Control(86)) OR (Data_in(10) And Control(96)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(47)) OR (Data_in(6) And Control(57)) OR (Data_in(7) And Control(67)) OR (Data_in(8) And Control(77)) OR (Data_in(9) And Control(87)) OR (Data_in(10) And Control(97)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(48)) OR (Data_in(6) And Control(58)) OR (Data_in(7) And Control(68)) OR (Data_in(8) And Control(78)) OR (Data_in(9) And Control(88)) OR (Data_in(10) And Control(98)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(59)) OR (Data_in(7) And Control(69)) OR (Data_in(8) And Control(79)) OR (Data_in(9) And Control(89)) OR (Data_in(10) And Control(99)));
+  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(60)) OR (Data_in(7) And Control(70)) OR (Data_in(8) And Control(80)) OR (Data_in(9) And Control(90)) OR (Data_in(10) And Control(100)));
+end generate crossbit10x10;
+
+
+--======================crossbit 11 ports=======================
+
+crossbit11x11 : if number_of_ports = 11 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(56)) OR (Data_in(7) And Control(67)) OR (Data_in(8) And Control(78)) OR (Data_in(9) And Control(89)) OR (Data_in(10) And Control(100)) OR (Data_in(11) And Control(111)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(46)) OR (Data_in(6) And Control(57)) OR (Data_in(7) And Control(68)) OR (Data_in(8) And Control(79)) OR (Data_in(9) And Control(90)) OR (Data_in(10) And Control(101)) OR (Data_in(11) And Control(112)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(47)) OR (Data_in(6) And Control(58)) OR (Data_in(7) And Control(69)) OR (Data_in(8) And Control(80)) OR (Data_in(9) And Control(91)) OR (Data_in(10) And Control(102)) OR (Data_in(11) And Control(113)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(48)) OR (Data_in(6) And Control(59)) OR (Data_in(7) And Control(70)) OR (Data_in(8) And Control(81)) OR (Data_in(9) And Control(92)) OR (Data_in(10) And Control(103)) OR (Data_in(11) And Control(114)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(60)) OR (Data_in(7) And Control(71)) OR (Data_in(8) And Control(82)) OR (Data_in(9) And Control(93)) OR (Data_in(10) And Control(104)) OR (Data_in(11) And Control(115)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(61)) OR (Data_in(7) And Control(72)) OR (Data_in(8) And Control(83)) OR (Data_in(9) And Control(94)) OR (Data_in(10) And Control(105)) OR (Data_in(11) And Control(116)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(51)) OR (Data_in(6) And Control(62)) OR (Data_in(7) And Control(73)) OR (Data_in(8) And Control(84)) OR (Data_in(9) And Control(95)) OR (Data_in(10) And Control(106)) OR (Data_in(11) And Control(117)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(52)) OR (Data_in(6) And Control(63)) OR (Data_in(7) And Control(74)) OR (Data_in(8) And Control(85)) OR (Data_in(9) And Control(96)) OR (Data_in(10) And Control(107)) OR (Data_in(11) And Control(118)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(64)) OR (Data_in(7) And Control(75)) OR (Data_in(8) And Control(86)) OR (Data_in(9) And Control(97)) OR (Data_in(10) And Control(108)) OR (Data_in(11) And Control(119)));
+  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(65)) OR (Data_in(7) And Control(76)) OR (Data_in(8) And Control(87)) OR (Data_in(9) And Control(98)) OR (Data_in(10) And Control(109)) OR (Data_in(11) And Control(120)));
+  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(77)) OR (Data_in(8) And Control(88)) OR (Data_in(9) And Control(99)) OR (Data_in(10) And Control(110)) OR (Data_in(11) And Control(121)));
+end generate crossbit11x11;
+
+
+--======================crossbit 12 ports=======================
+
+crossbit12x12 : if number_of_ports = 12 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(61)) OR (Data_in(7) And Control(73)) OR (Data_in(8) And Control(85)) OR (Data_in(9) And Control(97)) OR (Data_in(10) And Control(109)) OR (Data_in(11) And Control(121)) OR (Data_in(12) And Control(133)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(62)) OR (Data_in(7) And Control(74)) OR (Data_in(8) And Control(86)) OR (Data_in(9) And Control(98)) OR (Data_in(10) And Control(110)) OR (Data_in(11) And Control(122)) OR (Data_in(12) And Control(134)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(51)) OR (Data_in(6) And Control(63)) OR (Data_in(7) And Control(75)) OR (Data_in(8) And Control(87)) OR (Data_in(9) And Control(99)) OR (Data_in(10) And Control(111)) OR (Data_in(11) And Control(123)) OR (Data_in(12) And Control(135)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(52)) OR (Data_in(6) And Control(64)) OR (Data_in(7) And Control(76)) OR (Data_in(8) And Control(88)) OR (Data_in(9) And Control(100)) OR (Data_in(10) And Control(112)) OR (Data_in(11) And Control(124)) OR (Data_in(12) And Control(136)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(65)) OR (Data_in(7) And Control(77)) OR (Data_in(8) And Control(89)) OR (Data_in(9) And Control(101)) OR (Data_in(10) And Control(113)) OR (Data_in(11) And Control(125)) OR (Data_in(12) And Control(137)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(78)) OR (Data_in(8) And Control(90)) OR (Data_in(9) And Control(102)) OR (Data_in(10) And Control(114)) OR (Data_in(11) And Control(126)) OR (Data_in(12) And Control(138)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(67)) OR (Data_in(7) And Control(79)) OR (Data_in(8) And Control(91)) OR (Data_in(9) And Control(103)) OR (Data_in(10) And Control(115)) OR (Data_in(11) And Control(127)) OR (Data_in(12) And Control(139)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(56)) OR (Data_in(6) And Control(68)) OR (Data_in(7) And Control(80)) OR (Data_in(8) And Control(92)) OR (Data_in(9) And Control(104)) OR (Data_in(10) And Control(116)) OR (Data_in(11) And Control(128)) OR (Data_in(12) And Control(140)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(69)) OR (Data_in(7) And Control(81)) OR (Data_in(8) And Control(93)) OR (Data_in(9) And Control(105)) OR (Data_in(10) And Control(117)) OR (Data_in(11) And Control(129)) OR (Data_in(12) And Control(141)));
+  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(70)) OR (Data_in(7) And Control(82)) OR (Data_in(8) And Control(94)) OR (Data_in(9) And Control(106)) OR (Data_in(10) And Control(118)) OR (Data_in(11) And Control(130)) OR (Data_in(12) And Control(142)));
+  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(83)) OR (Data_in(8) And Control(95)) OR (Data_in(9) And Control(107)) OR (Data_in(10) And Control(119)) OR (Data_in(11) And Control(131)) OR (Data_in(12) And Control(143)));
+  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(84)) OR (Data_in(8) And Control(96)) OR (Data_in(9) And Control(108)) OR (Data_in(10) And Control(120)) OR (Data_in(11) And Control(132)) OR (Data_in(12) And Control(144)));
+end generate crossbit12x12;
+
+
+--======================crossbit 13 ports=======================
+
+crossbit13x13 : if number_of_ports = 13 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(79)) OR (Data_in(8) And Control(92)) OR (Data_in(9) And Control(105)) OR (Data_in(10) And Control(118)) OR (Data_in(11) And Control(131)) OR (Data_in(12) And Control(144)) OR (Data_in(13) And Control(157)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(67)) OR (Data_in(7) And Control(80)) OR (Data_in(8) And Control(93)) OR (Data_in(9) And Control(106)) OR (Data_in(10) And Control(119)) OR (Data_in(11) And Control(132)) OR (Data_in(12) And Control(145)) OR (Data_in(13) And Control(158)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(68)) OR (Data_in(7) And Control(81)) OR (Data_in(8) And Control(94)) OR (Data_in(9) And Control(107)) OR (Data_in(10) And Control(120)) OR (Data_in(11) And Control(133)) OR (Data_in(12) And Control(146)) OR (Data_in(13) And Control(159)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(56)) OR (Data_in(6) And Control(69)) OR (Data_in(7) And Control(82)) OR (Data_in(8) And Control(95)) OR (Data_in(9) And Control(108)) OR (Data_in(10) And Control(121)) OR (Data_in(11) And Control(134)) OR (Data_in(12) And Control(147)) OR (Data_in(13) And Control(160)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(70)) OR (Data_in(7) And Control(83)) OR (Data_in(8) And Control(96)) OR (Data_in(9) And Control(109)) OR (Data_in(10) And Control(122)) OR (Data_in(11) And Control(135)) OR (Data_in(12) And Control(148)) OR (Data_in(13) And Control(161)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(84)) OR (Data_in(8) And Control(97)) OR (Data_in(9) And Control(110)) OR (Data_in(10) And Control(123)) OR (Data_in(11) And Control(136)) OR (Data_in(12) And Control(149)) OR (Data_in(13) And Control(162)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(85)) OR (Data_in(8) And Control(98)) OR (Data_in(9) And Control(111)) OR (Data_in(10) And Control(124)) OR (Data_in(11) And Control(137)) OR (Data_in(12) And Control(150)) OR (Data_in(13) And Control(163)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(73)) OR (Data_in(7) And Control(86)) OR (Data_in(8) And Control(99)) OR (Data_in(9) And Control(112)) OR (Data_in(10) And Control(125)) OR (Data_in(11) And Control(138)) OR (Data_in(12) And Control(151)) OR (Data_in(13) And Control(164)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(74)) OR (Data_in(7) And Control(87)) OR (Data_in(8) And Control(100)) OR (Data_in(9) And Control(113)) OR (Data_in(10) And Control(126)) OR (Data_in(11) And Control(139)) OR (Data_in(12) And Control(152)) OR (Data_in(13) And Control(165)));
+  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(75)) OR (Data_in(7) And Control(88)) OR (Data_in(8) And Control(101)) OR (Data_in(9) And Control(114)) OR (Data_in(10) And Control(127)) OR (Data_in(11) And Control(140)) OR (Data_in(12) And Control(153)) OR (Data_in(13) And Control(166)));
+  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(89)) OR (Data_in(8) And Control(102)) OR (Data_in(9) And Control(115)) OR (Data_in(10) And Control(128)) OR (Data_in(11) And Control(141)) OR (Data_in(12) And Control(154)) OR (Data_in(13) And Control(167)));
+  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(90)) OR (Data_in(8) And Control(103)) OR (Data_in(9) And Control(116)) OR (Data_in(10) And Control(129)) OR (Data_in(11) And Control(142)) OR (Data_in(12) And Control(155)) OR (Data_in(13) And Control(168)));
+  Data_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(104)) OR (Data_in(9) And Control(117)) OR (Data_in(10) And Control(130)) OR (Data_in(11) And Control(143)) OR (Data_in(12) And Control(156)) OR (Data_in(13) And Control(169)));
+end generate crossbit13x13;
+
+
+--======================crossbit 14 ports=======================
+
+crossbit14x14 : if number_of_ports = 14 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(85)) OR (Data_in(8) And Control(99)) OR (Data_in(9) And Control(113)) OR (Data_in(10) And Control(127)) OR (Data_in(11) And Control(141)) OR (Data_in(12) And Control(155)) OR (Data_in(13) And Control(169)) OR (Data_in(14) And Control(183)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(86)) OR (Data_in(8) And Control(100)) OR (Data_in(9) And Control(114)) OR (Data_in(10) And Control(128)) OR (Data_in(11) And Control(142)) OR (Data_in(12) And Control(156)) OR (Data_in(13) And Control(170)) OR (Data_in(14) And Control(184)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(73)) OR (Data_in(7) And Control(87)) OR (Data_in(8) And Control(101)) OR (Data_in(9) And Control(115)) OR (Data_in(10) And Control(129)) OR (Data_in(11) And Control(143)) OR (Data_in(12) And Control(157)) OR (Data_in(13) And Control(171)) OR (Data_in(14) And Control(185)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(74)) OR (Data_in(7) And Control(88)) OR (Data_in(8) And Control(102)) OR (Data_in(9) And Control(116)) OR (Data_in(10) And Control(130)) OR (Data_in(11) And Control(144)) OR (Data_in(12) And Control(158)) OR (Data_in(13) And Control(172)) OR (Data_in(14) And Control(186)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(75)) OR (Data_in(7) And Control(89)) OR (Data_in(8) And Control(103)) OR (Data_in(9) And Control(117)) OR (Data_in(10) And Control(131)) OR (Data_in(11) And Control(145)) OR (Data_in(12) And Control(159)) OR (Data_in(13) And Control(173)) OR (Data_in(14) And Control(187)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(90)) OR (Data_in(8) And Control(104)) OR (Data_in(9) And Control(118)) OR (Data_in(10) And Control(132)) OR (Data_in(11) And Control(146)) OR (Data_in(12) And Control(160)) OR (Data_in(13) And Control(174)) OR (Data_in(14) And Control(188)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(105)) OR (Data_in(9) And Control(119)) OR (Data_in(10) And Control(133)) OR (Data_in(11) And Control(147)) OR (Data_in(12) And Control(161)) OR (Data_in(13) And Control(175)) OR (Data_in(14) And Control(189)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(92)) OR (Data_in(8) And Control(106)) OR (Data_in(9) And Control(120)) OR (Data_in(10) And Control(134)) OR (Data_in(11) And Control(148)) OR (Data_in(12) And Control(162)) OR (Data_in(13) And Control(176)) OR (Data_in(14) And Control(190)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(79)) OR (Data_in(7) And Control(93)) OR (Data_in(8) And Control(107)) OR (Data_in(9) And Control(121)) OR (Data_in(10) And Control(135)) OR (Data_in(11) And Control(149)) OR (Data_in(12) And Control(163)) OR (Data_in(13) And Control(177)) OR (Data_in(14) And Control(191)));
+  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(80)) OR (Data_in(7) And Control(94)) OR (Data_in(8) And Control(108)) OR (Data_in(9) And Control(122)) OR (Data_in(10) And Control(136)) OR (Data_in(11) And Control(150)) OR (Data_in(12) And Control(164)) OR (Data_in(13) And Control(178)) OR (Data_in(14) And Control(192)));
+  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(95)) OR (Data_in(8) And Control(109)) OR (Data_in(9) And Control(123)) OR (Data_in(10) And Control(137)) OR (Data_in(11) And Control(151)) OR (Data_in(12) And Control(165)) OR (Data_in(13) And Control(179)) OR (Data_in(14) And Control(193)));
+  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(96)) OR (Data_in(8) And Control(110)) OR (Data_in(9) And Control(124)) OR (Data_in(10) And Control(138)) OR (Data_in(11) And Control(152)) OR (Data_in(12) And Control(166)) OR (Data_in(13) And Control(180)) OR (Data_in(14) And Control(194)));
+  Data_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(111)) OR (Data_in(9) And Control(125)) OR (Data_in(10) And Control(139)) OR (Data_in(11) And Control(153)) OR (Data_in(12) And Control(167)) OR (Data_in(13) And Control(181)) OR (Data_in(14) And Control(195)));
+  Data_out(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(112)) OR (Data_in(9) And Control(126)) OR (Data_in(10) And Control(140)) OR (Data_in(11) And Control(154)) OR (Data_in(12) And Control(168)) OR (Data_in(13) And Control(182)) OR (Data_in(14) And Control(196)));
+end generate crossbit14x14;
+
+
+--======================crossbit 15 ports=======================
+
+crossbit15x15 : if number_of_ports = 15 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(106)) OR (Data_in(9) And Control(121)) OR (Data_in(10) And Control(136)) OR (Data_in(11) And Control(151)) OR (Data_in(12) And Control(166)) OR (Data_in(13) And Control(181)) OR (Data_in(14) And Control(196)) OR (Data_in(15) And Control(211)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(92)) OR (Data_in(8) And Control(107)) OR (Data_in(9) And Control(122)) OR (Data_in(10) And Control(137)) OR (Data_in(11) And Control(152)) OR (Data_in(12) And Control(167)) OR (Data_in(13) And Control(182)) OR (Data_in(14) And Control(197)) OR (Data_in(15) And Control(212)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(93)) OR (Data_in(8) And Control(108)) OR (Data_in(9) And Control(123)) OR (Data_in(10) And Control(138)) OR (Data_in(11) And Control(153)) OR (Data_in(12) And Control(168)) OR (Data_in(13) And Control(183)) OR (Data_in(14) And Control(198)) OR (Data_in(15) And Control(213)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(79)) OR (Data_in(7) And Control(94)) OR (Data_in(8) And Control(109)) OR (Data_in(9) And Control(124)) OR (Data_in(10) And Control(139)) OR (Data_in(11) And Control(154)) OR (Data_in(12) And Control(169)) OR (Data_in(13) And Control(184)) OR (Data_in(14) And Control(199)) OR (Data_in(15) And Control(214)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(80)) OR (Data_in(7) And Control(95)) OR (Data_in(8) And Control(110)) OR (Data_in(9) And Control(125)) OR (Data_in(10) And Control(140)) OR (Data_in(11) And Control(155)) OR (Data_in(12) And Control(170)) OR (Data_in(13) And Control(185)) OR (Data_in(14) And Control(200)) OR (Data_in(15) And Control(215)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(96)) OR (Data_in(8) And Control(111)) OR (Data_in(9) And Control(126)) OR (Data_in(10) And Control(141)) OR (Data_in(11) And Control(156)) OR (Data_in(12) And Control(171)) OR (Data_in(13) And Control(186)) OR (Data_in(14) And Control(201)) OR (Data_in(15) And Control(216)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(112)) OR (Data_in(9) And Control(127)) OR (Data_in(10) And Control(142)) OR (Data_in(11) And Control(157)) OR (Data_in(12) And Control(172)) OR (Data_in(13) And Control(187)) OR (Data_in(14) And Control(202)) OR (Data_in(15) And Control(217)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(113)) OR (Data_in(9) And Control(128)) OR (Data_in(10) And Control(143)) OR (Data_in(11) And Control(158)) OR (Data_in(12) And Control(173)) OR (Data_in(13) And Control(188)) OR (Data_in(14) And Control(203)) OR (Data_in(15) And Control(218)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(99)) OR (Data_in(8) And Control(114)) OR (Data_in(9) And Control(129)) OR (Data_in(10) And Control(144)) OR (Data_in(11) And Control(159)) OR (Data_in(12) And Control(174)) OR (Data_in(13) And Control(189)) OR (Data_in(14) And Control(204)) OR (Data_in(15) And Control(219)));
+  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(85)) OR (Data_in(7) And Control(100)) OR (Data_in(8) And Control(115)) OR (Data_in(9) And Control(130)) OR (Data_in(10) And Control(145)) OR (Data_in(11) And Control(160)) OR (Data_in(12) And Control(175)) OR (Data_in(13) And Control(190)) OR (Data_in(14) And Control(205)) OR (Data_in(15) And Control(220)));
+  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(71)) OR (Data_in(6) And Control(86)) OR (Data_in(7) And Control(101)) OR (Data_in(8) And Control(116)) OR (Data_in(9) And Control(131)) OR (Data_in(10) And Control(146)) OR (Data_in(11) And Control(161)) OR (Data_in(12) And Control(176)) OR (Data_in(13) And Control(191)) OR (Data_in(14) And Control(206)) OR (Data_in(15) And Control(221)));
+  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(57)) OR (Data_in(5) And Control(72)) OR (Data_in(6) And Control(87)) OR (Data_in(7) And Control(102)) OR (Data_in(8) And Control(117)) OR (Data_in(9) And Control(132)) OR (Data_in(10) And Control(147)) OR (Data_in(11) And Control(162)) OR (Data_in(12) And Control(177)) OR (Data_in(13) And Control(192)) OR (Data_in(14) And Control(207)) OR (Data_in(15) And Control(222)));
+  Data_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(43)) OR (Data_in(4) And Control(58)) OR (Data_in(5) And Control(73)) OR (Data_in(6) And Control(88)) OR (Data_in(7) And Control(103)) OR (Data_in(8) And Control(118)) OR (Data_in(9) And Control(133)) OR (Data_in(10) And Control(148)) OR (Data_in(11) And Control(163)) OR (Data_in(12) And Control(178)) OR (Data_in(13) And Control(193)) OR (Data_in(14) And Control(208)) OR (Data_in(15) And Control(223)));
+  Data_out(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(29)) OR (Data_in(3) And Control(44)) OR (Data_in(4) And Control(59)) OR (Data_in(5) And Control(74)) OR (Data_in(6) And Control(89)) OR (Data_in(7) And Control(104)) OR (Data_in(8) And Control(119)) OR (Data_in(9) And Control(134)) OR (Data_in(10) And Control(149)) OR (Data_in(11) And Control(164)) OR (Data_in(12) And Control(179)) OR (Data_in(13) And Control(194)) OR (Data_in(14) And Control(209)) OR (Data_in(15) And Control(224)));
+  Data_out(15) <= ((Data_in(1) And Control(15)) OR (Data_in(2) And Control(30)) OR (Data_in(3) And Control(45)) OR (Data_in(4) And Control(60)) OR (Data_in(5) And Control(75)) OR (Data_in(6) And Control(90)) OR (Data_in(7) And Control(105)) OR (Data_in(8) And Control(120)) OR (Data_in(9) And Control(135)) OR (Data_in(10) And Control(150)) OR (Data_in(11) And Control(165)) OR (Data_in(12) And Control(180)) OR (Data_in(13) And Control(195)) OR (Data_in(14) And Control(210)) OR (Data_in(15) And Control(225)));
+end generate crossbit15x15;
+
+
+--======================crossbit 16 ports=======================
+
+crossbit16x16 : if number_of_ports = 16 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(113)) OR (Data_in(9) And Control(129)) OR (Data_in(10) And Control(145)) OR (Data_in(11) And Control(161)) OR (Data_in(12) And Control(177)) OR (Data_in(13) And Control(193)) OR (Data_in(14) And Control(209)) OR (Data_in(15) And Control(225)) OR (Data_in(16) And Control(241)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(114)) OR (Data_in(9) And Control(130)) OR (Data_in(10) And Control(146)) OR (Data_in(11) And Control(162)) OR (Data_in(12) And Control(178)) OR (Data_in(13) And Control(194)) OR (Data_in(14) And Control(210)) OR (Data_in(15) And Control(226)) OR (Data_in(16) And Control(242)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(99)) OR (Data_in(8) And Control(115)) OR (Data_in(9) And Control(131)) OR (Data_in(10) And Control(147)) OR (Data_in(11) And Control(163)) OR (Data_in(12) And Control(179)) OR (Data_in(13) And Control(195)) OR (Data_in(14) And Control(211)) OR (Data_in(15) And Control(227)) OR (Data_in(16) And Control(243)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(100)) OR (Data_in(8) And Control(116)) OR (Data_in(9) And Control(132)) OR (Data_in(10) And Control(148)) OR (Data_in(11) And Control(164)) OR (Data_in(12) And Control(180)) OR (Data_in(13) And Control(196)) OR (Data_in(14) And Control(212)) OR (Data_in(15) And Control(228)) OR (Data_in(16) And Control(244)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(85)) OR (Data_in(7) And Control(101)) OR (Data_in(8) And Control(117)) OR (Data_in(9) And Control(133)) OR (Data_in(10) And Control(149)) OR (Data_in(11) And Control(165)) OR (Data_in(12) And Control(181)) OR (Data_in(13) And Control(197)) OR (Data_in(14) And Control(213)) OR (Data_in(15) And Control(229)) OR (Data_in(16) And Control(245)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(86)) OR (Data_in(7) And Control(102)) OR (Data_in(8) And Control(118)) OR (Data_in(9) And Control(134)) OR (Data_in(10) And Control(150)) OR (Data_in(11) And Control(166)) OR (Data_in(12) And Control(182)) OR (Data_in(13) And Control(198)) OR (Data_in(14) And Control(214)) OR (Data_in(15) And Control(230)) OR (Data_in(16) And Control(246)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(71)) OR (Data_in(6) And Control(87)) OR (Data_in(7) And Control(103)) OR (Data_in(8) And Control(119)) OR (Data_in(9) And Control(135)) OR (Data_in(10) And Control(151)) OR (Data_in(11) And Control(167)) OR (Data_in(12) And Control(183)) OR (Data_in(13) And Control(199)) OR (Data_in(14) And Control(215)) OR (Data_in(15) And Control(231)) OR (Data_in(16) And Control(247)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(72)) OR (Data_in(6) And Control(88)) OR (Data_in(7) And Control(104)) OR (Data_in(8) And Control(120)) OR (Data_in(9) And Control(136)) OR (Data_in(10) And Control(152)) OR (Data_in(11) And Control(168)) OR (Data_in(12) And Control(184)) OR (Data_in(13) And Control(200)) OR (Data_in(14) And Control(216)) OR (Data_in(15) And Control(232)) OR (Data_in(16) And Control(248)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(57)) OR (Data_in(5) And Control(73)) OR (Data_in(6) And Control(89)) OR (Data_in(7) And Control(105)) OR (Data_in(8) And Control(121)) OR (Data_in(9) And Control(137)) OR (Data_in(10) And Control(153)) OR (Data_in(11) And Control(169)) OR (Data_in(12) And Control(185)) OR (Data_in(13) And Control(201)) OR (Data_in(14) And Control(217)) OR (Data_in(15) And Control(233)) OR (Data_in(16) And Control(249)));
+  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(58)) OR (Data_in(5) And Control(74)) OR (Data_in(6) And Control(90)) OR (Data_in(7) And Control(106)) OR (Data_in(8) And Control(122)) OR (Data_in(9) And Control(138)) OR (Data_in(10) And Control(154)) OR (Data_in(11) And Control(170)) OR (Data_in(12) And Control(186)) OR (Data_in(13) And Control(202)) OR (Data_in(14) And Control(218)) OR (Data_in(15) And Control(234)) OR (Data_in(16) And Control(250)));
+  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(43)) OR (Data_in(4) And Control(59)) OR (Data_in(5) And Control(75)) OR (Data_in(6) And Control(91)) OR (Data_in(7) And Control(107)) OR (Data_in(8) And Control(123)) OR (Data_in(9) And Control(139)) OR (Data_in(10) And Control(155)) OR (Data_in(11) And Control(171)) OR (Data_in(12) And Control(187)) OR (Data_in(13) And Control(203)) OR (Data_in(14) And Control(219)) OR (Data_in(15) And Control(235)) OR (Data_in(16) And Control(251)));
+  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(44)) OR (Data_in(4) And Control(60)) OR (Data_in(5) And Control(76)) OR (Data_in(6) And Control(92)) OR (Data_in(7) And Control(108)) OR (Data_in(8) And Control(124)) OR (Data_in(9) And Control(140)) OR (Data_in(10) And Control(156)) OR (Data_in(11) And Control(172)) OR (Data_in(12) And Control(188)) OR (Data_in(13) And Control(204)) OR (Data_in(14) And Control(220)) OR (Data_in(15) And Control(236)) OR (Data_in(16) And Control(252)));
+  Data_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(29)) OR (Data_in(3) And Control(45)) OR (Data_in(4) And Control(61)) OR (Data_in(5) And Control(77)) OR (Data_in(6) And Control(93)) OR (Data_in(7) And Control(109)) OR (Data_in(8) And Control(125)) OR (Data_in(9) And Control(141)) OR (Data_in(10) And Control(157)) OR (Data_in(11) And Control(173)) OR (Data_in(12) And Control(189)) OR (Data_in(13) And Control(205)) OR (Data_in(14) And Control(221)) OR (Data_in(15) And Control(237)) OR (Data_in(16) And Control(253)));
+  Data_out(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(30)) OR (Data_in(3) And Control(46)) OR (Data_in(4) And Control(62)) OR (Data_in(5) And Control(78)) OR (Data_in(6) And Control(94)) OR (Data_in(7) And Control(110)) OR (Data_in(8) And Control(126)) OR (Data_in(9) And Control(142)) OR (Data_in(10) And Control(158)) OR (Data_in(11) And Control(174)) OR (Data_in(12) And Control(190)) OR (Data_in(13) And Control(206)) OR (Data_in(14) And Control(222)) OR (Data_in(15) And Control(238)) OR (Data_in(16) And Control(254)));
+  Data_out(15) <= ((Data_in(1) And Control(15)) OR (Data_in(2) And Control(31)) OR (Data_in(3) And Control(47)) OR (Data_in(4) And Control(63)) OR (Data_in(5) And Control(79)) OR (Data_in(6) And Control(95)) OR (Data_in(7) And Control(111)) OR (Data_in(8) And Control(127)) OR (Data_in(9) And Control(143)) OR (Data_in(10) And Control(159)) OR (Data_in(11) And Control(175)) OR (Data_in(12) And Control(191)) OR (Data_in(13) And Control(207)) OR (Data_in(14) And Control(223)) OR (Data_in(15) And Control(239)) OR (Data_in(16) And Control(255)));
+  Data_out(16) <= ((Data_in(1) And Control(16)) OR (Data_in(2) And Control(32)) OR (Data_in(3) And Control(48)) OR (Data_in(4) And Control(64)) OR (Data_in(5) And Control(80)) OR (Data_in(6) And Control(96)) OR (Data_in(7) And Control(112)) OR (Data_in(8) And Control(128)) OR (Data_in(9) And Control(144)) OR (Data_in(10) And Control(160)) OR (Data_in(11) And Control(176)) OR (Data_in(12) And Control(192)) OR (Data_in(13) And Control(208)) OR (Data_in(14) And Control(224)) OR (Data_in(15) And Control(240)) OR (Data_in(16) And Control(256)));
+end generate crossbit16x16;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/FIFO_256_FWFT.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/FIFO_256_FWFT.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/FIFO_256_FWFT.vhd	(revision 20)
@@ -0,0 +1,232 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL/GAMOM 
+-- 
+-- Create Date:    19:51:54 04/19/2011 
+-- Design Name: 
+-- Module Name:    FIFO_64 - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--FIFO 64 Octets utisé pour les modules d'entrée 
+-- ce fifo est de type fwft first word falls throught ce qui 
+-- signifie que l'on a toujours la donnée au sommet de la pile en 
+-- sortie du fifo. 
+-- Dependencies:  RAM_64.vhd
+-- 
+-- Revision: 30-07-2012
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- le signal counter_en a été supprimé
+----------------------------------------------------------------------------------
+library IEEE;
+
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--Library NocLib;
+--use NocLib.CoreTypes.all;
+use work.CoreTypes.all;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity FIFO_256_FWFT is
+    Port ( clk : in  STD_LOGIC;
+           din : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           rd_en : in  STD_LOGIC;
+           srst : in  STD_LOGIC;
+           wr_en : in  STD_LOGIC;
+           dout : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           empty : out  STD_LOGIC;
+           full : out  STD_LOGIC);
+end FIFO_256_FWFT;
+
+architecture Behavioral of FIFO_256_FWFT is
+-- declaration de la ram 256 octets
+COMPONENT RAM_256
+	PORT(
+		clka : IN std_logic;
+		clkb : IN std_logic;
+		wea : IN std_logic;
+		ena : IN std_logic;
+		enb : IN std_logic;
+		addra : IN std_logic_vector(Word-1 downto 0);
+		addrb : IN std_logic_vector(Word-1 downto 0);
+		dia : IN std_logic_vector(Word-1 downto 0);          
+		dob : OUT std_logic_vector(Word-1 downto 0)
+		);
+END COMPONENT;
+type fsm_states is (state0, state1, state2, state3);-- definition du type etat pour le codage des etats des fsm
+signal fwft_fsm_state : fsm_states;
+type ram_type is array (255 downto 0) of std_logic_vector (Word-1 downto 0);
+	signal RAM: ram_type;
+-- declaration des signeaux des compteurs
+signal push_address_counter: std_logic_vector(Word-1 downto 0);
+signal pop_address_counter : std_logic_vector(Word-1 downto 0);
+signal fifo_counter : std_logic_vector(Word-1 downto 0);
+--autre signaux
+signal empty_signal: std_logic:='1';
+signal rd_ready : std_logic:='0';
+signal full_signal  : std_logic;
+signal wr_en_signal : std_logic;--_vector(0 downto 0);
+signal rd_en_signal : std_logic;
+signal clk_signal :  std_logic;
+signal dob_signal : std_logic_vector(Word-1 downto 0);
+signal dout_signal : std_logic_vector(Word-1 downto 0);
+signal doa_signal : std_logic_vector(Word-1 downto 0);
+signal counter_en : std_logic; 
+
+begin
+
+-- ram instantiation de la bloc ram 256 octets du FIFO
+fifo_RAM_256: RAM_256 PORT MAP(
+		clka => clk_signal,
+		clkb => clk_signal,
+		wea => wr_en_signal,
+		ena => '1',
+		enb => '1',
+		addra => push_address_counter,
+		addrb => pop_address_counter,
+		dia => din,
+		dob => doa_signal
+	);
+		
+-- circuiterie des signaux de validation et d'etat du fifo
+wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein
+rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide
+full_signal <= '1' when fifo_counter = "11111111" else
+				   '0';
+--empty_signal <= '1' when fifo_counter = "000000"  else
+--					 '0';
+empty_signal <= '1' when rd_ready='0' or unsigned(fifo_counter) = 0  else
+					 '0';
+clk_signal <= clk;
+full <= full_signal;
+empty <= empty_signal ;
+
+-- sortie du fifo fwft
+dout <= dout_signal;
+
+-- le processus des transistion
+fwft_fsm_nsl : process(clk_signal)
+ begin
+    if rising_edge(clk_signal) then
+	   if srst = '1' then
+		   fwft_fsm_state  <= state0;
+		else
+		   case fwft_fsm_state  is
+					when state0 => if wr_en_signal = '1' then  --tampon vide seule l'écriture est possible
+											fwft_fsm_state  <= state1;
+										end if;
+										
+										
+					when state1 => --if rd_en_signal = '1' and wr_en_signal='1'  then  --écriture seule dans le tampon
+											
+											fwft_fsm_state  <= state2;
+										--end if;
+										
+					when state2 => if rd_en_signal = '1' and wr_en_signal='1'  then
+											fwft_fsm_state  <= state2;
+										elsif rd_en_signal='1' and wr_en_signal='0' and unsigned(fifo_counter) = 1 then --lecture avec écriture
+											fwft_fsm_state  <= state0;
+										elsif unsigned(fifo_counter) = 0 then
+											fwft_fsm_state  <= state0;
+										end if;
+										
+					when state3 => if rd_en_signal = '1' then  --écriture seule dans le tampon
+											fwft_fsm_state  <= state0;
+										elsif wr_en_signal='1' then
+											fwft_fsm_state  <= state2;
+										end if;
+
+					when others => fwft_fsm_state <= state0;
+										
+										
+			end case;
+	   end if;
+	end if;
+ end process;
+ -- actions associées à la fsm
+ -- mux qui oriente les sortie doa et dob vers out
+ with fwft_fsm_state select
+    dout_signal <= dob_signal when state0, 
+	                dob_signal when state1, --la sortie est la donnée en entrée
+	                dob_signal when state2, -- la sortie vient de la RAM
+						 dob_signal when state3,
+						 doa_signal when others;
+ -- counter_en
+ with fwft_fsm_state select
+    counter_en   <= '0' when state0, 
+	                 '1' when state1,
+	                 '1' when state2,
+						  '1' when state3,	
+						  '0' when others;
+						  
+with fwft_fsm_state select
+    rd_ready   <= '0' when state0, 
+	                 '0' when state1,
+	                 '1' when state2,
+						  '1' when state3,	
+						  '0' when others;
+doa_latch_process : process(clk_signal)
+begin
+  if rising_edge(clk_signal) then
+		if wr_en_signal ='1'  then
+			doa_signal <= din;
+		end if;
+  end if;
+end process;
+	               
+-- processus de comptage des adresses d'empilement
+push_process : process(clk_signal)
+ begin
+ if rising_edge(clk_signal) then
+   if srst = '1' then
+	 push_address_counter <= (others =>'0');
+	elsif wr_en_signal ='1'   then
+			RAM(conv_integer(push_address_counter)) <=din;
+	   	push_address_counter <= push_address_counter +1;
+	 end if;
+ end if;
+end process;
+ 
+ -- processus de comptage des adresses depilement du fifo
+pop_process : process(clk_signal)
+ begin
+ if rising_edge(clk_signal) then
+   if srst = '1' then
+	  pop_address_counter <= (others =>'0'); --pour avoir un décalage entre la valeur lue et celle qui est écrite
+	elsif rd_en_signal ='1'  then
+		pop_address_counter <= pop_address_counter+1;
+	end if;
+	
+ end if;
+ end process;
+ dob_signal<=RAM(conv_integer(pop_address_counter));
+ -- processus de comptage des octets dans le fifo
+ fifo_counter_process : process(clk_signal)
+variable count : std_logic_vector(word-1 downto 0):= (others=>'0');
+begin
+ if rising_edge(clk_signal) then
+   if srst = '1' then
+	 fifo_counter <= (others =>'0');
+	 count:=(others =>'0');
+	else
+	 if wr_en_signal ='1'  and rd_en_signal ='0' then 
+		--fifo_counter <= fifo_counter +1;
+		count:=count+1;
+	  end if;
+	 if rd_en_signal ='1' and wr_en_signal ='0' and counter_en='1' then
+		--fifo_counter <= fifo_counter - 1;
+		count:=count-1;		
+	 end if;
+	 fifo_counter<=count;
+  end if;
+ end if;
+end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/FIFO_256_FWFT_guide.ncd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/FIFO_256_FWFT_guide.ncd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/FIFO_256_FWFT_guide.ncd	(revision 20)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
+###4376:XlxV32DM    315f    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114ceNqNW0sW5aiO3BIYYyBrHb0AMHj4Zj2q8/beGCQDcWVn1yQr0hhLIaEfN8t12ZBPVf+LKperXNdmi7lx8dnfmJ8bev7f//7nCPqP+rP/+x+t/Z/jn//V2v3Z/vkfrY8/YfvXBBMPa4zS9ya+vnJdxW/7jY1Lp4QPu7kbX+oUsdcq3zj7cxexufQt5On7+k2Z836+KZ/7fqs8iHOV+cZO+VPaL9jLN6wa/MGnupJq/3WM+7E8jBuJ2yDRLyRG86/RRpnIr+2kxmZNo82rsElYpU6broJJ2IVO2+WLEbHvaqecDwlrfbnmKz7nWS2WT+VdN7Mq7yTMtCTfacD9Bq35lDDTfPmzSPuxPIwbzabSbDrNZlt41tvNcwz01kFaML588M8u+zBW/DbWpUK4X7PkY9qHLOFstqN/9hTxQcax1QgSruQ042hVnISZ3ETkMlnGd/lYXsZMdkayVScb98P1bGzr65OP7zE/uL7RbAfN51dg2eklJkW94JCIFB9FzAc9+HRJ+PJXO9ab7ieEldAqxDmQPPIAZhICkYD7MYkFPL6AEQp4fABSGTcSj8nj9y+PN6QFY0u47eKGKcqXKSoVGUSLEp5EjbOqF6pK/samuHwO0nrOAfXUbtJ6ziGbylFazznocKe4HvXD9U/w8yFJ6xuJfpCo1XfcOGgfDupJdY9BzEF9pziBmIP6RnHiB1NQL3kN+oz5nGdfFruxfHxuFemJmO1+kZ1xv2HHEiTMfpDB5S/wI8aN5zC5/PHl8p60YLz5eDy7xMla27e1NhXdcuBVjBJmrwmup1DEjrzy9FeQ8EFR3VJUR8zsVvaWU+dV14vlZcxsK1r/sA1RnvfD9SOlx8/vMT+4vvGcJp7XAJUaz3ouffo+fAqKiqeEff2b/p2enRAfxGv9w0m4ZnpKDEXEzEshHt7wBadmBx68j5uERykTD2k/toNWMmY7nj+l0WqXNPv7OU7NYRY7HPXUHCaWGt362e4F1a6/cbad1ZrzlYSLL6U1E08fsGL27tEHrJi1DuStiJkFTSw0LfOkpV60dFVLN7QsVPCxVm+YtSoqGAmnJxPFXcJchDgqMhAnX2zTIp9Rwqx1BBYisqAmFspgwV5fto4+uFnrN8xa16JhF7HppY6h5gMx16u11AkvmLTKScJPzzXb+pq0zIuWvmrph5a5/jlr9YZZK6f2XcLJUUHnnZLwpkr7i1E1rNhprtp71YGY48Cp1qo7IQsQv9/W3yxFNbGUFpZsZckOlpI/9czKG2ZW6jm1Euay99JZxFOjlyQ8NX5PbRX1pEX48ujdJzNL/Yafc+xjkfA9D6FRSJYwn9M9ZwcdUoKO6v+1vmm5DS392hKZqqUxMamrN+M+9DrR987l0MFLuLZIW29xQpKwVR0b2q9JMTXRzksew7pZn9WsywGRm3HKWvc6J2sJZ2VaN2xS5wZx1PvWohHth5htb9XkMfukxSF5zKOFWrVwoAXjWs21r9T05SWcTJcqUU+C2LuOa15xEs6+a33ZbhPEj4ffxCqylZ20XKurvWq5Dy13sJUHLT1ouZkesxBXR+lSK2qiAbOUmvZrUk5Nqtu+PGoHW4TfWqBXhFpvfX6SdwlHRzNFXw4JF/Iwe5VdxhTzqPJuWrhJC/WlhfGoxZrlGLPUQRUt4btWalxe5ZSwuVYPQjwqOmUfj/FThVS+PMaALeJvrl48xJqn61mwJ6lGtb1iltKp8lSrcerxjlOq41jKDbhOICVjTdxu5CGIre0TOU01M2KeGER/XBJm2+zucBLOlH+8kjGzEPyhHxbixEL88rgNbHUCCyfYKqV8SdjlbptM5+wNO5U2CY9zk4YWacrdm+RxVf7SuUzHfe2QNU9Xar4TcBlTkiTh0+9tvU+1RhfwU/3eQ2C65ohTf2SPr2oy3jPdstTIIh6dQtQS5rqo6CRi7iQq+yIuVFE4fRYJ51DCvP4Nn3c7J2Bfu80ZN5by6ObtSzfvauZqVe2dMep7ypSdYruWMH+35knzidU3rpXUNl9iFX+25/VJnjGur1V6mjHbMfgYZruZe4xc5pPan+N61P9Hnvr3HScrrcfv4fpmh6nD24N0pth6hVgOvrQqwqa+K2LnuxR7dkXCmz6JNWckXGu9qyeaGs9YyqlDO9xXN27Ulucq/Q0zN9lvQcTUdyZv7RfOKoo4WVWo1wkSnmrCIuGRlUafmqYO7LBfkcWow6xay/jRWtkiYe5LvfdRwjzv8nwRApj7Sk9Z5RV7GU81ZZHwyFoTS/qPrpGlsaP/uf/iboYsjXnl+Sz7eDXS2U4KXWffvZaEnc4H9S1awnxS73GhhDmSMOZIUmoEmSMmY5Wp861n92v9I//L+lpPlnk943qG2/M9lONrPe+P6xvvd7fniGYP0/RGtB9EVwJaKrC6Cxr4dwOAr9yJ1/eVvYA5uKjcQx5iJn6n9UzMcd9dT4oGUJTlw/Vv7+8v70ciyhBRiEeq7IZ8k4fx2/d2eM77jdTb8Q8f5IiMH0f14KiELfHrci8NcP2me0rWfBBg/WF7smiDJWE98ofrm6PdDflJKWttPHSojra1WZQu1PtmD8S1murt+eXzKT1nRa0vWlrPgjPG9ZGIxPdZnsmQXT6b9yfSTftxDYXPg+0R6KLaADG/n/+Cizq32fCODIvfe5OvdlG7JC/vx/jte4yZn42+z/wwHo7eazeuvRijPMw/Y37fKoxw60GK8Jwx8lPP3/bcKQgY5X3zP/uyP65/e/+R9+X7zF87SNPvJnyUaj9mtYa7hfVI4ebtuYVwFCFcRXhuMc/48bOxdIz0vUep6qlt0kHZasm+3p/HF47+tMtZoD6AfYUxP08c1Ok5Y9yPnyP2xBLu9yY/ysPv4/rG0j1TOoilJPdTk9x7tx4Fb52DhFmO2xclzD6KzwvIXZBHDzz6lccAvDGu1dLRfzFQ3Od+pB+ux+cob6YzdfgzfcnD7+P6Zgc/2UH8MRJH5g2sHVX/CrOaPbDuV9b5Oe73tn+myPO2f0RvVuDNaj0tEU4Dvs/fi+N75ksfxo3Fe2oXqZa8/pLiI9H/jCU8jCkAe9/b86z6mCOZnFbBipZwfATtmENsbViX9c6f2xeOlOLe3r9ofXxqrx623tZHSKERUqiGFKohhW5POChpxuO497Dz6K/WMMby8vff5HeBBgX+FO3B33/sM5LHNT9njPtVoXYaN3d7uX4QtFoPAstfeei/Uc6pSOtR/r+tR39CeZDvN/9l++D3cf3b/sxPO0hxhCOz1spnSwubidxT7XBOHNlhhPHu9/X/jn4ZTT0R4L/tx3ZkPJ0zBedMQXpd/RzOlVbrOUXM8r99D59rwF7BOabv79Tj2HCK65EPXN/slKYiJ0sDLpbyAFa4VEKsnoajY3zf5e69LBXiqVO0Eo6jc7RrtFu9hvHb/vy8sXAOFryVRzWsl6F0U+jU1QxvJDyS/MobYiy8zdOBdrkPkhvxKC5Xb954SM2Nh5LXj+JufR/lYcxRSIe1SMPvsfy4vvE8Dd+9ly9SntJug3ZKQ+m3re3e93osSk5g4Zy9YRpN+3Xou213DfCciQAZywDX5pebcfKuqWBbr2tK87mpDTJcQtE40HIkBjzOYj8b+P5BUy5u3hAbihCn7ZkE8VOYQsmF+FBrbDjAp/C5hbNtfxukDRqkDaZAGqZGWtSfpjo8PECM35tKRi197+19NTVIp5rGk0m2sxp6aWogeoWju10Rc6zRV582In78D6ZtvL+jim6vjYqEp8y5Dp3UWhExHkOpHtue55AzDrDT8Zupl2mcA95RH8ZcoVY7H1/fY/1x/Zv+rN/rc9Kv2Xn6V2a7+PPUJ9ZQfuddneoZA/G47lzrCX4/UJt55TNLeNQDkAEgKvmf69WynB7GTcttePO+Xp/m5s1mRC3LjRjNnhVlAsTPSJLaecTPiJIw7v/U83BqHVjf/Yw51hEh49G/AQ8wQvVw/YqY5eMoGmyPEohRns0918vlSx7eH9e/7e/mqGRGo7vDvzPbW6NbS576wkEFo1rD/ToxiNw42Gznf4yJ+KIwFVJPJ4inqVw3NJUQCkqO/XeKl2GKl6X149JhxSz/VBwsJdwOE4kdJhIBngd4fsJEAvc/Ib2d4Mjt3xDNja5aZ/0ZZt2M3/jD/Vh/XP/GD37vhz+S/81/9hf/wfXNUfdpIhNeJjJcB3m4NEm/g1TA66UAYg1De742fSYacM1aoFNkPP1gw8APNoz0vdGBr9+/YCLBeJo4LQeB8TTkz3DpAAdlzTSMx21eX79nngj8HFxRX7QPrsf9cT1+D+V92/+59qbb01Pl9MXX8/2X9Zku2ZDPv62fOvND8hfu7QzchvJ61B/Xv8l3TROZ00516HqdoXVL3VOzv/FtEd227VQoIXb+7Kkm9Ek34oN+GcRNMeJhKCqJaLTm/Xp71Ga4/wffIjZX###2032:XlxV32DM    188d     7d8eNq9VzmS5TYMvYwPQJDipk6m7HQCT+ADSCIVTtUEjn7N3Q1u0hOav0N3l0r/ERCx8AEk83n6mLXivxCOfObzTDHHgr1KhFiprArWKu+Ih5xUJpQPPOQpJIPygaW9oPKG2MZ0FHyqo+rzlwkxhSbP8dhn+lvX192e1JdymY+ssi1482mf5YPHXUGLSlP9T/aE/u/fP93hVrWa10+isC7nx79EftUf/xC5VeuX0WYbWdtVWtCLrJ5ZHHjoD1yteLYSmhWfHlaIzMuQ8WZL1MKPIYWajtTcpXAsMwzp1rg8W0ipOibm+4S741qlms6QmvxQLX0jncuZ3AyP701PjLQ/5nMhmxke3+8hnTN8Jb7jEa/t8w97A3+Kp9N5YOnvmH/gd/kcWObnnT8yfqnvenkO+g8s8yP1K5ECE2lpRLLqQSTHdHU3XaOgK3uhZ3joD2yjTtxBuCh316LSGbEP2hds46Fm+t6qiuloRSz1pX9Sv0YZOUrfojTHm3IZ6eZ3pUe2ael1us/wSCfX5fEV3nt3kPOTanJNKc4wB1TL01ILVOKLLupYZvOP7sd032d4LJwLrTuP+Hyny9nL05s5vrpnaN3zXf7GfBIP/1Wn47t8DSz1t8ve83uZj4FlvKOcB5bxXLtjx5VI2913l2e5kKpE4orxve5IHVFsi7UiOPql95HO6BQqg21fKIGvPtIdkXgk4jM+bOvzc3829eyLA0t/h9xfFd3sx/DsawOP74M4BgRxDFjEQg08iMILRzN7Mj6p/+77Mb/Mx6f1eJOv4b/Ul/msRNnvY0BYHkRZuK8uZhtZ2Xt3d7ZZHeUh8dVeBAsk5sNImuE7yw1XL4+7+y/+Ky+V6PZJHecMD30p16LoJJbzD3n1MoGX4SsveadUz4Oq8DIIL4XcCMZKLOcf8uplZi9t30np4eVWO4O6t5jUmRjMdYCkGebVrdj45Gb42ntDelTimJ9R3Qu9aluGxCG2vTSr3c7wtRersXc/57870WFmWN2Vaubz9bNAxzKe6yzRcc3zCQdsO2PDfQJpGwNfX2q9nulIMzz6rbNHnuERlex/A49+NHDxMimofze7Bmz3afORuyCsBGEloBWCXDw5Z9iKuRln+wpQP0S4lLYZvnvtc9Md+O7195UnaYg1zmIdX3nBEyV4pD4dZRquVsxtxaSvLlYhPK+zu9jXdrHv7XfftmV/p2ZEX6Hw+AHj4R536h4n0He08v+rYlXwAnoW9CyM47zx/p5akJaDtGbj0HynTTmTndGelaymbCNnuVTN5bXtTzA3gn675DvtZL5LHpqcq8q0S0xc6jG8VG9t2A1zEmOGoPY7qA2TlWAck7PBuH0mcfOgd4BeEHq4iGA/o/0TxjXoE4w70M8w7p/2coTvFehtQg9JBPET7SA4UYBfGBBoCEVbFOinTdKQXK1RE6inFxDYcAsMoQDyahQKYMEDjp/CGQeZRpPO3OMexz2WAQ9ESAgwhZBywAzawGDEcSM82yAbOyo6qYjZwSVJ4AKQhR6sw6xlWBlkQxa0pwy8R3bkIBVxgYAVmoChxqMAviCNAqxhWCrNzHsY1RpSTISasKgEmTIK54bx0LyEgU0O7HLgkANJDmQxkCDkAHk36QQB+psJBLC0i4a6DRDJsiXgM/DREqx5gHxbg8aBJRZ3GA/MtAFKwYNXfMYCAfDFbsACMOEcjPu7qvjv27e/Xj64le9RzuSd8Z8v+yKqFlaz+oUfrn7PbfsXMU9+v6it7ppWx3T0i+LH8xP5YUXL2Fp+9tVzN/C8MXq27x1jr65JQkmHZgvsGtNo+fiDIvH5rsh8vQ6sljfi1W3rdqyZTeqiwndzy29ec74nfCcmw/L6zk3EvH459/GTSs74FUv8v+cCeifQ7wSmpIrdyt0t0twzXNnKuP+Xni9di/+va7xqf79+MFXVxw+WECdZFcC5rqgs8Flevr22csLh98HZLe/MKeY3R5BzeZsSYflhS5jlhy+xlh+xBPzBBv8D8GjiTg==
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/FIFO_DP.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/FIFO_DP.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/FIFO_DP.vhd	(revision 20)
@@ -0,0 +1,102 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    16:32:59 10/23/2012 
+-- Design Name: 
+-- Module Name:    FIFO_DP - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity fifo_dp is
+GENERIC
+(
+ADDRESS_WIDTH : integer:=8;---8 bit
+DATA_WIDTH : integer:=8 ---8 bit
+);
+
+port ( clk : in std_logic;
+reset : in std_logic;
+enr : in std_logic; --enable read,should be '0' when not in use.
+enw : in std_logic; --enable write,should be '0' when not in use.
+dataout : out std_logic_vector(DATA_WIDTH-1 downto 0); --output data
+datain : in std_logic_vector (DATA_WIDTH-1 downto 0); --input data
+empty : out std_logic; --set as '1' when the queue is empty
+err : out std_logic;
+full : out std_logic --set as '1' when the queue is full
+);
+end fifo;
+
+architecture Behavioral of fifo_dp is
+
+type memory_type is array (0 to ((2**ADDRESS_WIDTH)-1)) of std_logic_vector(DATA_WIDTH-1 downto 0);
+
+
+-----distributed-------
+signal memory : memory_type ;-- :=(others => (others => '0')); --memory for queue.----- 
+signal readptr,writeptr : std_logic_vector(ADDRESS_WIDTH-1 downto 0); --read and write pointers.
+signal full0 : std_logic;
+signal empty0 : std_logic;
+
+begin
+full <= full0;
+empty <= empty0; 
+
+fifo0: process(clk,reset)
+begin
+if reset='1' then
+
+readptr <= (others => '0');
+writeptr <= (others => '0');
+empty0 <='1';
+full0<='0';
+err<='0';
+
+
+elsif rising_edge(clk) then 
+
+if (writeptr + '1' = readptr) then 
+full0<='1';
+else
+full0<='0';
+end if ;
+
+if (readptr = writeptr ) then 
+empty0<='1';
+else
+empty0<='0';
+end if ; 
+
+if (empty0='0' and enr='1') or (full0='0' and enw='1') then 
+err<='1';
+end if ; 
+
+if enw='1' and full0='0' then 
+memory (conv_integer(writeptr)) <= datain ;
+writeptr <= writeptr + '1' ;
+end if ; 
+
+if enr='1' and empty0='0' then 
+dataout <= memory (conv_integer(readptr));
+readptr <= readptr + '1' ;
+end if ; 
+
+end if; 
+
+end process;
+end Behavioral;
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16.gise
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16.gise	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16.gise	(revision 20)
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="GENERIC_16_16.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_NCD" xil_pn:name="FIFO_256_FWFT_guide.ncd" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="OUTPUT_PORT_MODULE.sym" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GENERIQUE_guide.ncd" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GEN_guide.ncd" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16.xise
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16.xise	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16.xise	(revision 20)
@@ -0,0 +1,515 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="Crossbit.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="Crossbar.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="Scheduler.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="Arbiter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER2_2.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER3_3.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER4_4.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER5_5.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER6_6.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER7_7.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER8_8.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER9_9.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER10_10.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER11_11.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER12_12.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER13_13.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER14_14.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER15_15.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER16_16.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="RAM_256.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="FIFO_256_FWFT.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="INPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="OUTPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SWITCH_GENERIQUE.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="test_xbar_8x8.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="PostMapSimulation"/>
+      <association xil_pn:name="PostRouteSimulation"/>
+      <association xil_pn:name="PostTranslateSimulation"/>
+    </file>
+    <file xil_pn:name="conv.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="stimuli1.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="C:/RomSwitch/testport5.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="CoreTypes.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../CORE_MPI/sim_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="Proto_receiv.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="FIFO_DP.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="proto_send.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="AES Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="Test_fifo.wcfg" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Custom Waveform Configuration File Translate" xil_pn:value="test_xbar_8x8.wcfg" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc3s1200e" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../CORE_MPI/sim_fifo.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
+    <property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="testbench" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="ft256" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="testbench_map.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="testbench_timesim.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="testbench_synthesis.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="testbench_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="testbench" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.test_xbar_8x8" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.test_xbar_16x16" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="180 ns" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.test_xbar_8x8" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.test_xbar_16x16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="d:/Xilinx/12.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Waveform Database Filename Post-Translate" xil_pn:value="test_xbar_8x8_isim_beh.wdb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="GENERIC_16_16" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="Architecture|test_xbar_16x16|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Architecture|test_xbar_16x16|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-07-11T16:58:22" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6E6D9310BD824CB7AA37132338EEB7D5" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries>
+    <library xil_pn:name="NoClib"/>
+    <library xil_pn:name="typesconv"/>
+  </libraries>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys	(revision 20)
@@ -0,0 +1,24 @@
+CommandLine-Map
+
+s
+CommandLine-Ngdbuild
+
+s
+CommandLine-Par
+
+s
+CommandLine-Xst
+
+s
+Previous-NGD
+
+s
+Previous-NGM
+
+s
+Previous-Packed-NCD
+
+s
+Previous-Routed-NCD
+
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ISE_VERSION_LAST_SAVED_WITH
+11.1
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys	(revision 20)
@@ -0,0 +1,6 @@
+ISE_VERSION_LAST_SAVED_WITH
+11.1
+s
+XISE_FILE
+GENERIC_16_16.xise
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/XSLTProcess.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys	(revision 20)
@@ -0,0 +1,21 @@
+ISE_VERSION_CREATED_WITH
+11.1
+s
+ISE_VERSION_LAST_SAVED_WITH
+11.1
+s
+LastRepoDir
+C:\Documents and Settings\GENERAL\Bureau\GENERIC_16_16\
+s
+OBJSTORE_VERSION
+1.3
+s
+PROJECT_CREATION_TIMESTAMP
+2011-06-19T11:17:23
+s
+REGISTRY_VERSION
+1.1
+s
+REPOSITORY_VERSION
+1.1
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/bitgen.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/bitinit.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/common/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/common/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/common/regkeys	(revision 20)
@@ -0,0 +1,15 @@
+IncrementalMessagingEnabled
+false
+s
+MessageCaptureEnabled
+true
+s
+MessageFilterFile
+filter.filter
+s
+MessageFilteringEnabled
+false
+s
+RunOnce
+#/PnAutoRun/Scripts/RunOnce_tcl
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/cpldfit.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/dumpngdio.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/fuse/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/fuse/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/fuse/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/fuse.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/hprep6.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/idem/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/idem/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/idem/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/idem.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/libgen/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/libgen/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/libgen/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/libgen.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/map/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/map/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/map/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/map.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/netgen/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/netgen/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/netgen/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/netgen.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/ngc2edif.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/ngcbuild.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/ngdbuild.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/par/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/par/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/par/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/par.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/platgen/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/platgen/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/platgen/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/platgen.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/runner/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/runner/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/runner/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/runner.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/simgen/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/simgen/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/simgen/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/simgen.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/taengine/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/taengine/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/taengine/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/taengine.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/trce/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/trce/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/trce/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/trce.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/tsim/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/tsim/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/tsim/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/tsim.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/vhpcomp.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/vlogcomp.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/xpwr.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/xst/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/xst/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/xst/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/xst.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/version
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/version	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16_xdb/tmp/ise/version	(revision 20)
@@ -0,0 +1,10 @@
+REPOSITORY_VERSION
+1.1
+REGISTRY_VERSION
+1.1
+OBJSTORE_VERSION
+1.3
+ISE_VERSION_CREATED_WITH
+11.1
+ISE_VERSION_LAST_SAVED_WITH
+11.1
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.cmd_log
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.cmd_log	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.cmd_log	(revision 20)
@@ -0,0 +1,2 @@
+xst -ise "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/GENERIC_16_16.ise" -intstyle ise -ifn "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.xst" -ofn "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.syr" 
+xst -ise "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/GENERIC_16_16.ise" -intstyle ise -ifn "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.xst" -ofn "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.syr" 
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.ngc
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.ngc	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.ngc	(revision 20)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.5e
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Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.prj
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.prj	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.prj	(revision 20)
@@ -0,0 +1,3 @@
+vhdl work "RAM_256.vhd"
+vhdl work "FIFO_256_FWFT.vhd"
+vhdl work "INPUT_PORT_MODULE.vhd"
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.stx
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.stx	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.stx	(revision 20)
@@ -0,0 +1,38 @@
+Release 11.1 - xst L.33 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
+--> Parameter TMPDIR set to C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.17 secs
+ 
+--> Parameter xsthdpdir set to C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.17 secs
+ 
+--> 
+=========================================================================
+*                          HDL Compilation                              *
+=========================================================================
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/RAM_256.vhd" in Library work.
+Architecture behavioral of Entity ram_256 is up to date.
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/FIFO_256_FWFT.vhd" in Library work.
+Architecture behavioral of Entity fifo_256_fwft is up to date.
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.vhd" in Library work.
+Entity <input_port_module> compiled.
+Entity <INPUT_PORT_MODULE> (Architecture <Behavioral>) compiled.
+
+
+Total REAL time to Xst completion: 1.00 secs
+Total CPU time to Xst completion: 0.83 secs
+ 
+--> 
+
+Total memory usage is 120796 kilobytes
+
+Number of errors   :    0 (   0 filtered)
+Number of warnings :    0 (   0 filtered)
+Number of infos    :    0 (   0 filtered)
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.syr
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.syr	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.syr	(revision 20)
@@ -0,0 +1,552 @@
+Release 11.1 - xst L.33 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
+--> Parameter TMPDIR set to xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.18 secs
+ 
+--> Parameter xsthdpdir set to xst
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.18 secs
+ 
+--> Reading design: INPUT_PORT_MODULE.prj
+
+TABLE OF CONTENTS
+  1) Synthesis Options Summary
+  2) HDL Compilation
+  3) Design Hierarchy Analysis
+  4) HDL Analysis
+  5) HDL Synthesis
+     5.1) HDL Synthesis Report
+  6) Advanced HDL Synthesis
+     6.1) Advanced HDL Synthesis Report
+  7) Low Level Synthesis
+  8) Partition Report
+  9) Final Report
+	9.1) Device utilization summary
+	9.2) Partition Resource Summary
+	9.3) TIMING REPORT
+
+
+=========================================================================
+*                      Synthesis Options Summary                        *
+=========================================================================
+---- Source Parameters
+Input File Name                    : "INPUT_PORT_MODULE.prj"
+Input Format                       : mixed
+Ignore Synthesis Constraint File   : NO
+
+---- Target Parameters
+Output File Name                   : "INPUT_PORT_MODULE"
+Output Format                      : NGC
+Target Device                      : xc3s1200e-4-fg320
+
+---- Source Options
+Top Module Name                    : INPUT_PORT_MODULE
+Automatic FSM Extraction           : YES
+FSM Encoding Algorithm             : Auto
+Safe Implementation                : No
+FSM Style                          : lut
+RAM Extraction                     : Yes
+RAM Style                          : Auto
+ROM Extraction                     : Yes
+Mux Style                          : Auto
+Decoder Extraction                 : YES
+Priority Encoder Extraction        : YES
+Shift Register Extraction          : YES
+Logical Shifter Extraction         : YES
+XOR Collapsing                     : YES
+ROM Style                          : Auto
+Mux Extraction                     : YES
+Resource Sharing                   : YES
+Asynchronous To Synchronous        : NO
+Automatic Register Balancing       : No
+
+---- Target Options
+Add IO Buffers                     : YES
+Add Generic Clock Buffer(BUFG)     : 24
+Register Duplication               : YES
+Slice Packing                      : YES
+Optimize Instantiated Primitives   : NO
+Use Clock Enable                   : Yes
+Use Synchronous Set                : Yes
+Use Synchronous Reset              : Yes
+Pack IO Registers into IOBs        : auto
+Equivalent register Removal        : YES
+
+---- General Options
+Optimization Goal                  : Speed
+Optimization Effort                : 1
+Library Search Order               : INPUT_PORT_MODULE.lso
+Keep Hierarchy                     : NO
+Netlist Hierarchy                  : as_optimized
+RTL Output                         : Yes
+Global Optimization                : AllClockNets
+Read Cores                         : YES
+Write Timing Constraints           : NO
+Cross Clock Analysis               : NO
+Hierarchy Separator                : /
+Bus Delimiter                      : <>
+Case Specifier                     : maintain
+Slice Utilization Ratio            : 100
+BRAM Utilization Ratio             : 100
+Verilog 2001                       : YES
+Auto BRAM Packing                  : NO
+Slice Utilization Ratio Delta      : 5
+
+=========================================================================
+
+
+=========================================================================
+*                          HDL Compilation                              *
+=========================================================================
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/RAM_256.vhd" in Library work.
+Architecture behavioral of Entity ram_256 is up to date.
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/FIFO_256_FWFT.vhd" in Library work.
+Architecture behavioral of Entity fifo_256_fwft is up to date.
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.vhd" in Library work.
+Entity <input_port_module> compiled.
+Entity <input_port_module> (Architecture <behavioral>) compiled.
+
+=========================================================================
+*                     Design Hierarchy Analysis                         *
+=========================================================================
+Analyzing hierarchy for entity <INPUT_PORT_MODULE> in library <work> (architecture <behavioral>) with generics.
+	number_of_ports = 4
+
+Analyzing hierarchy for entity <FIFO_256_FWFT> in library <work> (architecture <behavioral>).
+
+Analyzing hierarchy for entity <RAM_256> in library <work> (architecture <behavioral>).
+
+
+=========================================================================
+*                            HDL Analysis                               *
+=========================================================================
+Analyzing generic Entity <INPUT_PORT_MODULE> in library <work> (Architecture <behavioral>).
+	number_of_ports = 4
+Entity <INPUT_PORT_MODULE> analyzed. Unit <INPUT_PORT_MODULE> generated.
+
+Analyzing Entity <FIFO_256_FWFT> in library <work> (Architecture <behavioral>).
+Entity <FIFO_256_FWFT> analyzed. Unit <FIFO_256_FWFT> generated.
+
+Analyzing Entity <RAM_256> in library <work> (Architecture <behavioral>).
+Entity <RAM_256> analyzed. Unit <RAM_256> generated.
+
+
+=========================================================================
+*                           HDL Synthesis                               *
+=========================================================================
+
+Performing bidirectional port resolution...
+
+Synthesizing Unit <RAM_256>.
+    Related source file is "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/RAM_256.vhd".
+    Found 256x8-bit dual-port RAM <Mram_RAM> for signal <RAM>.
+    Found 8-bit register for signal <dob>.
+    Summary:
+	inferred   1 RAM(s).
+	inferred   8 D-type flip-flop(s).
+Unit <RAM_256> synthesized.
+
+
+Synthesizing Unit <FIFO_256_FWFT>.
+    Related source file is "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/FIFO_256_FWFT.vhd".
+    Found finite state machine <FSM_0> for signal <fwft_fsm_state>.
+    -----------------------------------------------------------------------
+    | States             | 3                                              |
+    | Transitions        | 8                                              |
+    | Inputs             | 3                                              |
+    | Outputs            | 4                                              |
+    | Clock              | clk (rising_edge)                              |
+    | Reset              | srst (positive)                                |
+    | Reset type         | synchronous                                    |
+    | Reset State        | state0                                         |
+    | Power Up State     | state0                                         |
+    | Encoding           | automatic                                      |
+    | Implementation     | LUT                                            |
+    -----------------------------------------------------------------------
+    Found 8-bit register for signal <doa_signal>.
+    Found 8-bit updown counter for signal <fifo_counter>.
+    Found 8-bit up counter for signal <pop_address_counter>.
+    Found 8-bit up counter for signal <push_address_counter>.
+    Summary:
+	inferred   1 Finite State Machine(s).
+	inferred   3 Counter(s).
+	inferred   8 D-type flip-flop(s).
+Unit <FIFO_256_FWFT> synthesized.
+
+
+Synthesizing Unit <INPUT_PORT_MODULE>.
+    Related source file is "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.vhd".
+    Found finite state machine <FSM_1> for signal <pop_state>.
+    -----------------------------------------------------------------------
+    | States             | 4                                              |
+    | Transitions        | 9                                              |
+    | Inputs             | 4                                              |
+    | Outputs            | 5                                              |
+    | Clock              | clk (rising_edge)                              |
+    | Reset              | reset_signal (positive)                        |
+    | Reset type         | synchronous                                    |
+    | Reset State        | state0                                         |
+    | Power Up State     | state0                                         |
+    | Encoding           | automatic                                      |
+    | Implementation     | LUT                                            |
+    -----------------------------------------------------------------------
+    Found 8-bit register for signal <data_counter>.
+    Found 8-bit subtractor for signal <data_counter$share0000> created at line 434.
+    Found 1-bit register for signal <empty_latch>.
+    Found 8-bit register for signal <pipeline_latch>.
+    Found 5-bit comparator greater for signal <port_granted$cmp_gt0000> created at line 110.
+    Found 4-bit register for signal <request_latch>.
+    Summary:
+	inferred   1 Finite State Machine(s).
+	inferred  21 D-type flip-flop(s).
+	inferred   1 Adder/Subtractor(s).
+	inferred   1 Comparator(s).
+Unit <INPUT_PORT_MODULE> synthesized.
+
+INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
+
+=========================================================================
+HDL Synthesis Report
+
+Macro Statistics
+# RAMs                                                 : 1
+ 256x8-bit dual-port RAM                               : 1
+# Adders/Subtractors                                   : 1
+ 8-bit subtractor                                      : 1
+# Counters                                             : 3
+ 8-bit up counter                                      : 2
+ 8-bit updown counter                                  : 1
+# Registers                                            : 6
+ 1-bit register                                        : 1
+ 4-bit register                                        : 1
+ 8-bit register                                        : 4
+# Comparators                                          : 1
+ 5-bit comparator greater                              : 1
+
+=========================================================================
+
+=========================================================================
+*                       Advanced HDL Synthesis                          *
+=========================================================================
+
+Analyzing FSM <FSM_1> for best encoding.
+Choose code 2 with characteristics nb_luts=8,nb_literals=21,nb_ffs=2,depth=2 ...
+Optimizing FSM <pop_state/FSM> on signal <pop_state[1:2]> with gray encoding.
+--------------------
+ State  | Encoding
+--------------------
+ state0 | 00
+ state1 | 01
+ state2 | 11
+ state3 | 10
+--------------------
+Analyzing FSM <FSM_0> for best encoding.
+Choose code 7 with characteristics nb_luts=5,nb_literals=16,nb_ffs=2,depth=2 ...
+Optimizing FSM <INPUT_PORT_FIFO/fwft_fsm_state/FSM> on signal <fwft_fsm_state[1:2]> with user encoding.
+--------------------
+ State  | Encoding
+--------------------
+ state0 | 00
+ state1 | 01
+ state2 | 10
+--------------------
+
+Synthesizing (advanced) Unit <RAM_256>.
+INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dob>
+    -----------------------------------------------------------------------
+    | ram_type           | Block                               |          |
+    -----------------------------------------------------------------------
+    | Port A                                                              |
+    |     aspect ratio   | 256-word x 8-bit                    |          |
+    |     mode           | read-first                          |          |
+    |     clkA           | connected to signal <clka>          | rise     |
+    |     weA            | connected to signal <wea>           | high     |
+    |     addrA          | connected to signal <addra>         |          |
+    |     diA            | connected to signal <dia>           |          |
+    -----------------------------------------------------------------------
+    | optimization       | speed                               |          |
+    -----------------------------------------------------------------------
+    | Port B                                                              |
+    |     aspect ratio   | 256-word x 8-bit                    |          |
+    |     mode           | write-first                         |          |
+    |     clkB           | connected to signal <clkb>          | rise     |
+    |     addrB          | connected to signal <addrb>         |          |
+    |     doB            | connected to signal <dob>           |          |
+    -----------------------------------------------------------------------
+    | optimization       | speed                               |          |
+    -----------------------------------------------------------------------
+Unit <RAM_256> synthesized (advanced).
+
+=========================================================================
+Advanced HDL Synthesis Report
+
+Macro Statistics
+# FSMs                                                 : 2
+# RAMs                                                 : 1
+ 256x8-bit dual-port block RAM                         : 1
+# Adders/Subtractors                                   : 1
+ 8-bit subtractor                                      : 1
+# Counters                                             : 3
+ 8-bit up counter                                      : 2
+ 8-bit updown counter                                  : 1
+# Registers                                            : 29
+ Flip-Flops                                            : 29
+# Comparators                                          : 1
+ 5-bit comparator greater                              : 1
+
+=========================================================================
+
+=========================================================================
+*                         Low Level Synthesis                           *
+=========================================================================
+
+Optimizing unit <INPUT_PORT_MODULE> ...
+
+Optimizing unit <FIFO_256_FWFT> ...
+
+Mapping all equations...
+Building and optimizing final netlist ...
+Found area constraint ratio of 100 (+ 5) on block INPUT_PORT_MODULE, actual ratio is 0.
+
+Final Macro Processing ...
+
+=========================================================================
+Final Register Report
+
+Macro Statistics
+# Registers                                            : 57
+ Flip-Flops                                            : 57
+
+=========================================================================
+
+=========================================================================
+*                           Partition Report                             *
+=========================================================================
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+=========================================================================
+*                            Final Report                               *
+=========================================================================
+Final Results
+RTL Top Level Output File Name     : INPUT_PORT_MODULE.ngr
+Top Level Output File Name         : INPUT_PORT_MODULE
+Output Format                      : NGC
+Optimization Goal                  : Speed
+Keep Hierarchy                     : NO
+
+Design Statistics
+# IOs                              : 31
+
+Cell Usage :
+# BELS                             : 142
+#      GND                         : 1
+#      INV                         : 2
+#      LUT1                        : 14
+#      LUT2                        : 4
+#      LUT3                        : 20
+#      LUT3_D                      : 1
+#      LUT3_L                      : 2
+#      LUT4                        : 44
+#      LUT4_D                      : 5
+#      LUT4_L                      : 2
+#      MUXCY                       : 21
+#      MUXF5                       : 1
+#      VCC                         : 1
+#      XORCY                       : 24
+# FlipFlops/Latches                : 57
+#      FDE                         : 8
+#      FDR                         : 3
+#      FDRE                        : 37
+#      FDRS                        : 9
+# RAMS                             : 1
+#      RAMB16_S9_S9                : 1
+# Clock Buffers                    : 1
+#      BUFGP                       : 1
+# IO Buffers                       : 30
+#      IBUF                        : 14
+#      OBUF                        : 16
+=========================================================================
+
+Device utilization summary:
+---------------------------
+
+Selected Device : 3s1200efg320-4 
+
+ Number of Slices:                       49  out of   8672     0%  
+ Number of Slice Flip Flops:             57  out of  17344     0%  
+ Number of 4 input LUTs:                 94  out of  17344     0%  
+ Number of IOs:                          31
+ Number of bonded IOBs:                  31  out of    250    12%  
+ Number of BRAMs:                         1  out of     28     3%  
+ Number of GCLKs:                         1  out of     24     4%  
+
+---------------------------
+Partition Resource Summary:
+---------------------------
+
+  No Partitions were found in this design.
+
+---------------------------
+
+
+=========================================================================
+TIMING REPORT
+
+NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
+      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
+      GENERATED AFTER PLACE-and-ROUTE.
+
+Clock Information:
+------------------
+-----------------------------------+------------------------+-------+
+Clock Signal                       | Clock buffer(FF name)  | Load  |
+-----------------------------------+------------------------+-------+
+clk                                | BUFGP                  | 58    |
+-----------------------------------+------------------------+-------+
+
+Asynchronous Control Signals Information:
+----------------------------------------
+No asynchronous control signals found in this design
+
+Timing Summary:
+---------------
+Speed Grade: -4
+
+   Minimum period: 7.226ns (Maximum Frequency: 138.389MHz)
+   Minimum input arrival time before clock: 9.258ns
+   Maximum output required time after clock: 7.556ns
+   Maximum combinational path delay: 8.635ns
+
+Timing Detail:
+--------------
+All values displayed in nanoseconds (ns)
+
+=========================================================================
+Timing constraint: Default period analysis for Clock 'clk'
+  Clock period: 7.226ns (frequency: 138.389MHz)
+  Total number of paths / destination ports: 1824 / 119
+-------------------------------------------------------------------------
+Delay:               7.226ns (Levels of Logic = 11)
+  Source:            pop_state_FSM_FFd1 (FF)
+  Destination:       INPUT_PORT_FIFO/fifo_counter_7 (FF)
+  Source Clock:      clk rising
+  Destination Clock: clk rising
+
+  Data Path: pop_state_FSM_FFd1 to INPUT_PORT_FIFO/fifo_counter_7
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FDRE:C->Q            18   0.591   1.103  pop_state_FSM_FFd1 (pop_state_FSM_FFd1)
+     LUT4_D:I2->O          1   0.704   0.455  INPUT_PORT_FIFO/rd_en_signal1_SW5 (N14)
+     LUT3:I2->O           14   0.704   1.035  INPUT_PORT_FIFO/rd_en_signal1 (INPUT_PORT_FIFO/rd_en_signal)
+     LUT3:I2->O            1   0.704   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0>)
+     MUXCY:S->O            1   0.464   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5>)
+     MUXCY:CI->O           0   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6>)
+     XORCY:CI->O           1   0.804   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_xor<7> (INPUT_PORT_FIFO/Result<7>)
+     FDRE:D                    0.308          INPUT_PORT_FIFO/fifo_counter_7
+    ----------------------------------------
+    Total                      7.226ns (4.633ns logic, 2.593ns route)
+                                       (64.1% logic, 35.9% route)
+
+=========================================================================
+Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
+  Total number of paths / destination ports: 528 / 134
+-------------------------------------------------------------------------
+Offset:              9.258ns (Levels of Logic = 13)
+  Source:            grant<1> (PAD)
+  Destination:       INPUT_PORT_FIFO/fifo_counter_7 (FF)
+  Destination Clock: clk rising
+
+  Data Path: grant<1> to INPUT_PORT_FIFO/fifo_counter_7
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     IBUF:I->O             1   1.218   0.595  grant_1_IBUF (grant_1_IBUF)
+     LUT4:I0->O           16   0.704   1.209  port_granted1 (port_granted)
+     LUT4_D:I0->O          1   0.704   0.455  INPUT_PORT_FIFO/rd_en_signal1_SW5 (N14)
+     LUT3:I2->O           14   0.704   1.035  INPUT_PORT_FIFO/rd_en_signal1 (INPUT_PORT_FIFO/rd_en_signal)
+     LUT3:I2->O            1   0.704   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0>)
+     MUXCY:S->O            1   0.464   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5>)
+     MUXCY:CI->O           0   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6>)
+     XORCY:CI->O           1   0.804   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_xor<7> (INPUT_PORT_FIFO/Result<7>)
+     FDRE:D                    0.308          INPUT_PORT_FIFO/fifo_counter_7
+    ----------------------------------------
+    Total                      9.258ns (5.964ns logic, 3.294ns route)
+                                       (64.4% logic, 35.6% route)
+
+=========================================================================
+Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
+  Total number of paths / destination ports: 53 / 16
+-------------------------------------------------------------------------
+Offset:              7.556ns (Levels of Logic = 3)
+  Source:            pop_state_FSM_FFd1 (FF)
+  Destination:       request<4> (PAD)
+  Source Clock:      clk rising
+
+  Data Path: pop_state_FSM_FFd1 to request<4>
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FDRE:C->Q            18   0.591   1.243  pop_state_FSM_FFd1 (pop_state_FSM_FFd1)
+     LUT4:I0->O            4   0.704   0.622  request_decoder_and00001 (request_decoder_and0000)
+     LUT3:I2->O            1   0.704   0.420  request_decoder<4>1 (request_4_OBUF)
+     OBUF:I->O                 3.272          request_4_OBUF (request<4>)
+    ----------------------------------------
+    Total                      7.556ns (5.271ns logic, 2.285ns route)
+                                       (69.8% logic, 30.2% route)
+
+=========================================================================
+Timing constraint: Default path analysis
+  Total number of paths / destination ports: 8 / 2
+-------------------------------------------------------------------------
+Delay:               8.635ns (Levels of Logic = 4)
+  Source:            grant<1> (PAD)
+  Destination:       data_out_pulse (PAD)
+
+  Data Path: grant<1> to data_out_pulse
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     IBUF:I->O             1   1.218   0.595  grant_1_IBUF (grant_1_IBUF)
+     LUT4:I0->O           16   0.704   1.209  port_granted1 (port_granted)
+     LUT4:I0->O           11   0.704   0.933  data_out_pulse1 (data_out_pulse_OBUF)
+     OBUF:I->O                 3.272          data_out_pulse_OBUF (data_out_pulse)
+    ----------------------------------------
+    Total                      8.635ns (5.898ns logic, 2.737ns route)
+                                       (68.3% logic, 31.7% route)
+
+=========================================================================
+
+
+Total REAL time to Xst completion: 10.00 secs
+Total CPU time to Xst completion: 9.84 secs
+ 
+--> 
+
+Total memory usage is 137348 kilobytes
+
+Number of errors   :    0 (   0 filtered)
+Number of warnings :    0 (   0 filtered)
+Number of infos    :    2 (   0 filtered)
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.vhd	(revision 20)
@@ -0,0 +1,796 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL/GAMOM Roland CHristian
+-- 
+-- Create Date:    03:47:50 04/24/2011 
+-- Design Name: 
+-- Module Name:    INPUT_PORT_MODULE - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+-- Module de gestion des entrées des ports du switch crossbar
+-- il supose qu'une donnée est empilée à chaque cycle d'horloge
+-- Dependencies: 
+-- FIFO_64_FWFT.vhd
+-- RAM_64.vhd
+-- Revision: 1
+-- remplacement du fifo ordinaire par un fifo fwft
+-- Revision 1.01 - File Created
+-- Additional Comments: 
+-- modifié le 14/05/20011  pour eviter une écriture multiple dans le FIFO de sortie
+-- si le FIFO d'entrée vient a se vider pendant le transfert d'un packet
+-- le machine a état on été re modeliser et sont maintenant du type FSMD
+-- remodéliation pour plus de vitesse
+--inclusion du signal priority rotation pour eviter la perte du grant pendant une transmission
+--02-08-2012 :Prise en compte du signal Port_Granted dans un process
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE ieee.numeric_std.ALL;
+use work.Coretypes.all;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+
+entity INPUT_PORT_MODULE is
+    generic(number_of_ports : positive := 4;
+	 
+	 Port_num: natural:=1);  -- port_num est l'id du port
+    Port ( data_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           data_in_en : in  STD_LOGIC; -- signaler la présence des données en entrée
+			  cmd_in_en : STD_LOGIC;    --permet d'identifier les données qui sont dans le tampon
+           reset : in  STD_LOGIC;
+			  clk   : in  STD_LOGIC;
+			  request : out  STD_LOGIC_VECTOR (number_of_ports downto 1); --demande de canal de transmission
+           grant : in  STD_LOGIC_VECTOR (number_of_ports  downto 1);	 -- autorisation de transmission		  
+           fifo_full : out  STD_LOGIC; -- signaler que les données ne peuvent plus être acceptées en entrée
+			  fifo_empty : out  STD_LOGIC; -- le tampon d'entrée est vide
+			  priority_rotation : out std_logic;  -- reserver le canal de transmission
+           data_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); --données vers le réseau crossbar
+			  data_out_pulse : out std_logic); -- permet de ...
+       
+end INPUT_PORT_MODULE;
+
+architecture Behavioral of INPUT_PORT_MODULE is
+
+-- declaration du fifo 64 octet utilisé pour chaque port
+component FIFO_256_FWFT
+	port (
+	clk: IN std_logic;
+	din: IN std_logic_VECTOR(Word-1 downto 0);
+	rd_en: IN std_logic;
+	srst: IN std_logic;
+	wr_en: IN std_logic;
+	dout: OUT std_logic_VECTOR(Word-1 downto 0);
+	empty: OUT std_logic;
+	full: OUT std_logic);
+end component;
+
+--definition du type etat pour les fsm
+type fsm_states is (state0, CmdOn, WaitGrant, ReqPort, state1, state2,stpulse, state3);-- definition du type etat pour le codage des etats des fsm
+type fsm_states2 is(cmdstart,cmdwait,cmdread,cmdSetDest,cmdSetCount,cmdSetId,cmdpulse,CmdEnd);
+signal pop_state : fsm_states;
+signal cmdstate : fsm_states2;
+signal cmd_exec : std_logic:='0';  --indique que le port est en train d'exécuter une commande
+signal dat_exec :std_logic:='0'; -- indique le port est en train de transférer des données
+signal readOk : std_logic:='0'; --indique s'il est possible de lire les données
+-- signaux utilisés dans les fsm
+signal request_decoder : STD_LOGIC_VECTOR(number_of_ports  downto 1);
+signal request_decoder_en : std_logic;
+signal request_latch : STD_LOGIC_VECTOR(4 downto 1);   -- pourquoi pas 3 downto 0 ?
+signal request_latch_en : std_logic;
+signal pipeline_latch : std_logic_vector(Word-1 downto 0);
+signal pipeline_latch_en : std_logic;
+signal request_word :  std_logic_vector(5 downto 1);
+signal port_granted : std_logic;
+signal rd_en_signal : std_logic;
+--signaux utilisés dans la MAE de gestion des commandes
+signal cmd_request_latch_en :std_logic;
+signal cmd_pipeline_latch_en :std_logic;
+signal cmd_fifo_read_signal :std_logic;
+signal cmd_request_decoder_en :std_logic;
+signal cmd_data_out_pulse :std_logic;
+signal cmd_priority_rotation :std_logic;
+--signaux utilisés dans la MAE de transfert des données
+signal dat_request_latch_en :std_logic;
+signal dat_pipeline_latch_en :std_logic;
+signal dat_fifo_read_signal :std_logic;
+signal dat_request_decoder_en :std_logic;
+signal dat_data_out_pulse :std_logic;
+signal dat_priority_rotation :std_logic;
+-- signaux utilisés pour les connections entre composants
+signal clk_signal : std_logic;
+signal reset_signal : std_logic;
+signal fifo_empty_signal : std_logic;
+signal fifo_read_signal : std_logic;
+signal fifo_out_signal,cmd_data_signal : std_logic_vector(Word-1 downto 0);
+signal push_dout : std_logic_vector(Word-1 downto 0);
+signal empty_latch : std_logic ;
+signal PORT_ID :std_logic_vector(Word-1 downto 0):=STD_LOGIC_VECTOR(to_unsigned(number_of_ports-1,4))& STD_LOGIC_VECTOR(to_unsigned(port_num-1,4));
+-- signaux du compteur de données
+signal data_counter : std_logic_vector(Word-1 downto 0);
+
+begin
+-- instantiation du FIFO_256
+ INPUT_PORT_FIFO : FIFO_256_FWFT
+		port map (
+			clk => clk_signal,
+			din => data_in,
+			rd_en => fifo_read_signal,
+			srst => reset_signal,
+			wr_en => data_in_en,
+			dout => fifo_out_signal,
+			empty => fifo_empty_signal,
+			full => fifo_full);
+-- connections avec les ports de l'entité
+
+data_out <= pipeline_latch ;--when cmd_exec='0' else cmd_data_signal;
+fifo_empty <= fifo_empty_signal;
+reset_signal <= reset;
+grant_proc:process(clk)
+begin
+if rising_edge(clk) then
+	if unsigned(grant)> 0 then
+		port_granted <= '1';   		--il faut veiller à ce que ce port soit vraiment autorisé
+	else 
+		Port_granted<='0'; 	 		--ceci présuppose que la valeur qu'il reçoit est forcément la sienne
+	end if;
+end if;		
+end process;			 
+rd_en_signal <= not(empty_latch) ;
+request <= request_decoder;
+request_word <=  request_latch & request_decoder_en;
+clk_signal <= clk;
+
+
+
+WITH cmd_exec SELECT
+    request_latch_en <=  dat_request_latch_en   WHEN '0',
+								  cmd_request_latch_en  WHEN others;
+								  
+WITH cmd_exec SELECT
+		pipeline_latch_en  <=  dat_pipeline_latch_en   WHEN '0',
+								    cmd_pipeline_latch_en  WHEN others;
+								      
+WITH cmd_exec SELECT    
+		fifo_read_signal <=dat_fifo_read_signal WHEN '0', 
+		
+								cmd_fifo_read_signal WHEN others;
+WITH cmd_exec SELECT
+		request_decoder_en <=dat_request_decoder_en WHEN '0',
+									cmd_request_decoder_en WHEN others; 
+WITH cmd_exec SELECT
+		data_out_pulse <=dat_data_out_pulse WHEN '0',
+							  cmd_data_out_pulse WHEN others;
+WITH cmd_exec SELECT
+		priority_rotation<=dat_priority_rotation WHEN '0',
+								 cmd_priority_rotation WHEN others;
+
+
+--processus permettant de latcher le signal empty
+-- evite une perte de données en cas d'arret au cours d'une transmission
+empty_latch_process : process(clk)
+begin
+ if rising_edge(clk) then
+	if reset_signal = '1' then
+	    empty_latch <= '1';
+	else
+	 empty_latch <= fifo_empty_signal;
+   end if;
+ end if;	
+
+end process;
+-- decodeur de requete en fonction de l'adresse destination
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+switch2x2 : if number_of_ports = 2 generate
+
+with request_word select
+      request_decoder <="01" when "00001",
+                        "10" when "00011",
+                        "00" when others;
+
+end generate switch2x2;
+
+
+-- switch 3 ports
+switch3x3 : if number_of_ports = 3 generate
+
+with request_word select
+      request_decoder <="001" when "00001",
+                        "010" when "00011",
+                        "100" when "00101",
+                        "000" when others;
+
+end generate switch3x3;
+
+
+-- switch 4 ports
+switch4x4 : if number_of_ports = 4 generate
+
+with request_word select
+      request_decoder <="0001" when "00001",
+                        "0010" when "00011",
+                        "0100" when "00101",
+                        "1000" when "00111",
+                        "0000" when others;
+
+end generate switch4x4;
+
+
+-- switch 5 ports
+switch5x5 : if number_of_ports = 5 generate
+
+with request_word select
+      request_decoder <="00001" when "00001",
+                        "00010" when "00011",
+                        "00100" when "00101",
+                        "01000" when "00111",
+                        "10000" when "01001",
+                        "00000" when others;
+
+end generate switch5x5;
+
+
+-- switch 6 ports
+switch6x6 : if number_of_ports = 6 generate
+
+with request_word select
+      request_decoder <="000001" when "00001",
+                        "000010" when "00011",
+                        "000100" when "00101",
+                        "001000" when "00111",
+                        "010000" when "01001",
+                        "100000" when "01011",
+                        "000000" when others;
+
+end generate switch6x6;
+
+
+-- switch 7 ports
+switch7x7 : if number_of_ports = 7 generate
+
+with request_word select
+      request_decoder <="0000001" when "00001",
+                        "0000010" when "00011",
+                        "0000100" when "00101",
+                        "0001000" when "00111",
+                        "0010000" when "01001",
+                        "0100000" when "01011",
+                        "1000000" when "01101",
+                        "0000000" when others;
+
+end generate switch7x7;
+
+
+-- switch 8 ports
+switch8x8 : if number_of_ports = 8 generate
+
+with request_word select
+      request_decoder <="00000001" when "00001",
+                        "00000010" when "00011",
+                        "00000100" when "00101",
+                        "00001000" when "00111",
+                        "00010000" when "01001",
+                        "00100000" when "01011",
+                        "01000000" when "01101",
+                        "10000000" when "01111",
+                        "00000000" when others;
+
+end generate switch8x8;
+
+
+-- switch 9 ports
+switch9x9 : if number_of_ports = 9 generate
+
+with request_word select
+      request_decoder <="000000001" when "00001",
+                        "000000010" when "00011",
+                        "000000100" when "00101",
+                        "000001000" when "00111",
+                        "000010000" when "01001",
+                        "000100000" when "01011",
+                        "001000000" when "01101",
+                        "010000000" when "01111",
+                        "100000000" when "10001",
+                        "000000000" when others;
+
+end generate switch9x9;
+
+
+-- switch 10 ports
+switch10x10 : if number_of_ports = 10 generate
+
+with request_word select
+      request_decoder <="0000000001" when "00001",
+                        "0000000010" when "00011",
+                        "0000000100" when "00101",
+                        "0000001000" when "00111",
+                        "0000010000" when "01001",
+                        "0000100000" when "01011",
+                        "0001000000" when "01101",
+                        "0010000000" when "01111",
+                        "0100000000" when "10001",
+                        "1000000000" when "10011",
+                        "0000000000" when others;
+
+end generate switch10x10;
+
+
+-- switch 11 ports
+switch11x11 : if number_of_ports = 11 generate
+
+with request_word select
+      request_decoder <="00000000001" when "00001",
+                        "00000000010" when "00011",
+                        "00000000100" when "00101",
+                        "00000001000" when "00111",
+                        "00000010000" when "01001",
+                        "00000100000" when "01011",
+                        "00001000000" when "01101",
+                        "00010000000" when "01111",
+                        "00100000000" when "10001",
+                        "01000000000" when "10011",
+                        "10000000000" when "10101",
+                        "00000000000" when others;
+
+end generate switch11x11;
+
+
+-- switch 12 ports
+switch12x12 : if number_of_ports = 12 generate
+
+with request_word select
+      request_decoder <="000000000001" when "00001",
+                        "000000000010" when "00011",
+                        "000000000100" when "00101",
+                        "000000001000" when "00111",
+                        "000000010000" when "01001",
+                        "000000100000" when "01011",
+                        "000001000000" when "01101",
+                        "000010000000" when "01111",
+                        "000100000000" when "10001",
+                        "001000000000" when "10011",
+                        "010000000000" when "10101",
+                        "100000000000" when "10111",
+                        "000000000000" when others;
+
+end generate switch12x12;
+
+
+-- switch 13 ports
+switch13x13 : if number_of_ports = 13 generate
+
+with request_word select
+      request_decoder <="0000000000001" when "00001",
+                        "0000000000010" when "00011",
+                        "0000000000100" when "00101",
+                        "0000000001000" when "00111",
+                        "0000000010000" when "01001",
+                        "0000000100000" when "01011",
+                        "0000001000000" when "01101",
+                        "0000010000000" when "01111",
+                        "0000100000000" when "10001",
+                        "0001000000000" when "10011",
+                        "0010000000000" when "10101",
+                        "0100000000000" when "10111",
+                        "1000000000000" when "11001",
+                        "0000000000000" when others;
+
+end generate switch13x13;
+
+
+-- switch 14 ports
+switch14x14 : if number_of_ports = 14 generate
+
+with request_word select
+      request_decoder <="00000000000001" when "00001",
+                        "00000000000010" when "00011",
+                        "00000000000100" when "00101",
+                        "00000000001000" when "00111",
+                        "00000000010000" when "01001",
+                        "00000000100000" when "01011",
+                        "00000001000000" when "01101",
+                        "00000010000000" when "01111",
+                        "00000100000000" when "10001",
+                        "00001000000000" when "10011",
+                        "00010000000000" when "10101",
+                        "00100000000000" when "10111",
+                        "01000000000000" when "11001",
+                        "10000000000000" when "11011",
+                        "00000000000000" when others;
+
+end generate switch14x14;
+
+
+-- switch 15 ports
+switch15x15 : if number_of_ports = 15 generate
+
+with request_word select
+      request_decoder <="000000000000001" when "00001",
+                        "000000000000010" when "00011",
+                        "000000000000100" when "00101",
+                        "000000000001000" when "00111",
+                        "000000000010000" when "01001",
+                        "000000000100000" when "01011",
+                        "000000001000000" when "01101",
+                        "000000010000000" when "01111",
+                        "000000100000000" when "10001",
+                        "000001000000000" when "10011",
+                        "000010000000000" when "10101",
+                        "000100000000000" when "10111",
+                        "001000000000000" when "11001",
+                        "010000000000000" when "11011",
+                        "100000000000000" when "11101",
+                        "000000000000000" when others;
+
+end generate switch15x15;
+
+
+-- switch 16 ports
+switch16x16 : if number_of_ports = 16 generate
+
+with request_word select
+      request_decoder <="0000000000000001" when "00001",
+                        "0000000000000010" when "00011",
+                        "0000000000000100" when "00101",
+                        "0000000000001000" when "00111",
+                        "0000000000010000" when "01001",
+                        "0000000000100000" when "01011",
+                        "0000000001000000" when "01101",
+                        "0000000010000000" when "01111",
+                        "0000000100000000" when "10001",
+                        "0000001000000000" when "10011",
+                        "0000010000000000" when "10101",
+                        "0000100000000000" when "10111",
+                        "0001000000000000" when "11001",
+                        "0010000000000000" when "11011",
+                        "0100000000000000" when "11101",
+                        "1000000000000000" when "11111",
+                        "0000000000000000" when others;
+
+end generate switch16x16;									
+--latch du fifo de sortie ??
+pipeline_latch_process : process(clk)
+begin
+	if rising_edge(clk) then 
+	  if reset_signal = '1' then 
+	   pipeline_latch <= (others => '0');
+		 elsif pipeline_latch_en = '1' and cmd_exec='0' then
+		  pipeline_latch <= push_dout;
+		  elsif pipeline_latch_en = '1' and cmd_exec='1' then
+		  pipeline_latch <= cmd_data_signal;
+	  end if;
+	end if;
+end process;
+
+--latch qui memorise l'adresse de destination du packet
+
+request_latch_process : process(clk)
+begin
+	if rising_edge(clk) then
+		if reset_signal = '1' then
+		  request_latch <= (others => '0');
+		  elsif request_latch_en = '1' and cmd_in_en='0' then  --si la lecture de la destination est autorisée
+		  request_latch <=fifo_out_signal(3 downto 0); --fifo_out_signal(3) & fifo_out_signal(2) & fifo_out_signal(1) & fifo_out_signal(0);
+		  elsif cmd_in_en='1' and request_latch_en='1' then  --c'est une commande le port de dest est le même que le port d'entrée
+		   request_latch<=Port_ID(3 downto 0);  --car les ports commencent à 0
+		end if;
+	end if;
+end process;
+
+-- machine à etat de mealy qui depile les donnees dans le fifo
+--
+-- processus determinant l'etat futur
+pop_fsm_nsl : process(clk)
+begin 
+	if rising_edge(clk) then 
+	 if reset_signal = '1' then
+		pop_state <= state0;
+		data_counter <= (others => '0');
+	  elsif cmd_exec='0' then  --il ne faut pas exécuter cette MAE
+										-- lorsque l'autre est en cours 
+	  
+		  case pop_state is
+			when state0 => if cmd_in_en='0'  then --il ne faut pas exécuter les deux MAE ...
+									if fifo_empty_signal  ='0' then -- pile pas vide on doit dépiler									
+										pop_state <= WaitGrant;
+									end if;
+								else
+									pop_state <= CmdOn;
+								end if;
+			when CmdOn => if fifo_empty_signal='1' then
+								pop_state <= state0;
+								end if;
+			when WaitGrant => if port_granted = '1' then
+										--
+										pop_state <= ReqPort;
+								end if;					
+			when ReqPort => --if port_granted = '1' then
+										--
+										pop_state <= state1;
+								--end if;
+		
+			when state1 => if port_granted ='1' then --lecture de la longueur des données
+										data_counter <= fifo_out_signal;
+										if unsigned(fifo_out_signal)<=3 then 
+												ReadOk<='1';
+										else
+												readOk<='1';
+										end if;
+										pop_state <= state2;
+							      end if;
+										
+			when state2 => if port_granted='1' then 
+										if rd_en_signal ='1' and unsigned(data_counter)<= 3 then
+											data_counter <= data_counter - 1;
+											pop_state <= stpulse;
+											ReadOk<='1';
+										elsif rd_en_signal ='1' then
+										  data_counter <= data_counter - 1;
+										  pop_state <= state2;
+										  ReadOk<='1';
+										end if;
+									else
+										ReadOk<='0';
+									end if;
+			
+			when stpulse =>	if port_granted='1' then 
+											pop_state <= state3;		--pousser la dernière donnée dehors		
+											data_counter <= data_counter - 1;
+									end if;
+			
+			when state3 => 	
+										data_counter <= data_counter - 1;
+										pop_state <= state0;
+																						
+			when others => pop_state <= state0;
+		   end case;
+	 end if;
+	end if;
+end process;
+
+-- actions associées à chaque etat de la fsm de mealy
+pop_fsm_action : process(pop_state, fifo_out_signal,fifo_empty_signal, rd_en_signal,readok, port_granted )
+  begin   
+-- code fonctionnel	
+	case pop_state is
+		when state0 =>    dat_request_latch_en <= '0';  
+								dat_pipeline_latch_en <= rd_en_signal;
+								dat_fifo_read_signal <='0';
+								dat_request_decoder_en <= '0';
+								dat_data_out_pulse <= '0';
+								dat_priority_rotation <= '1';
+								dat_exec<='0';
+								push_dout<=fifo_out_signal;
+		when CmdOn =>		dat_request_latch_en <= '0';  
+								dat_pipeline_latch_en <= rd_en_signal;
+								dat_fifo_read_signal <='0';
+								dat_request_decoder_en <= '0';
+								dat_data_out_pulse <= '0';
+								dat_priority_rotation <= '1';
+								dat_exec<='0';
+								push_dout<=fifo_out_signal;
+		when WaitGrant =>	
+								dat_request_latch_en <='1'; --autoriser l'identification du port de destination
+								dat_pipeline_latch_en <= Port_granted; --pour le transmettre à travers le réseau
+								dat_fifo_read_signal <= '0';
+								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+								dat_data_out_pulse <= '0';     --transmettre le signal pour le dernier mot
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0);
+		when ReqPort =>	
+								dat_request_latch_en <='1'; --autoriser l'identification du port de destination
+								dat_pipeline_latch_en <= Port_granted; --pour le transmettre à travers le réseau
+								dat_fifo_read_signal <= Port_granted;
+								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+								dat_data_out_pulse <= '0';     --transmettre le signal pour le dernier mot
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0);
+							
+		when state1 =>    dat_request_latch_en <= '0';
+								dat_pipeline_latch_en <= rd_en_signal and port_granted;   
+								dat_fifo_read_signal <= rd_en_signal and port_granted;
+								dat_request_decoder_en <= '1';
+								dat_data_out_pulse <= '1';
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								push_dout<=fifo_out_signal;
+								
+	  when state2 =>    dat_request_latch_en <= '0';
+								dat_pipeline_latch_en <= rd_en_signal;  --autoriser la lecture du fifo en sortie
+								dat_fifo_read_signal <= readok;   
+								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+								dat_data_out_pulse <= readOk;
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								push_dout<=fifo_out_signal;
+								
+	  when stpulse =>    dat_request_latch_en <= '0'; --pousser la dernière donnée 
+								dat_pipeline_latch_en <= '0';  --autoriser la lecture du fifo en sortie
+								dat_fifo_read_signal <='0';   
+								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+								dat_data_out_pulse <= '1';  -- pousser le dernier mot
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								push_dout<=fifo_out_signal;
+								
+		when state3 =>    dat_request_latch_en <= '0';
+								dat_pipeline_latch_en <= '0';
+								dat_priority_rotation <= '1';    -- libérer la priorité
+								dat_fifo_read_signal <= '0';
+								dat_request_decoder_en <= '0';   --libérer le décodeur
+								dat_data_out_pulse <= '0';
+								dat_exec<='0';
+								push_dout<=fifo_out_signal;
+		
+		when others =>    dat_request_latch_en <= '0';
+								dat_pipeline_latch_en <= '0';
+								dat_priority_rotation <= '1';
+								dat_fifo_read_signal <= '0';
+								dat_request_decoder_en <= '0';
+								dat_data_out_pulse <= '0';
+								dat_exec<='0';
+								push_dout<=fifo_out_signal;
+										
+		end case;
+ end process; 
+ -- traitement des commandes reçues par le switch
+fsm_cmd:process(clk,cmd_in_en)
+variable timeout : natural:=0;
+variable cmdcode : natural range 0 to 255;
+begin
+if rising_edge(clk) then
+   if reset_signal = '1' then
+	   cmdstate<=cmdstart;
+	else -- il ne faut pas traiter les cmdes et les données en même temps 
+	case cmdstate is
+	
+	   when cmdstart  =>
+				if cmd_in_en='1' and dat_exec='0' and fifo_empty_signal='0' then 
+				cmdstate<=cmdwait;
+				end if;
+		when cmdwait => if fifo_empty_signal='0' and port_granted ='1' then
+								
+									cmdstate<=cmdread;
+							else 
+								cmdstate<=cmdstart;
+							end if;
+		when cmdread =>
+				if port_granted ='1'then -- ne pas modifier l'état des priorités si on ne l'avait pas
+					cmdcode:= to_integer(unsigned(fifo_out_signal));
+					if cmdcode=1 then --code de getportid
+							cmdstate<=cmdsetdest;
+					else
+						if port_granted='1' then
+							cmdstate<=cmdend;
+						end if;
+					end if;
+				end if;
+		when cmdsetdest =>
+				if port_granted='1' then
+					cmdstate<=cmdsetcount;
+				end if;
+		when cmdsetcount =>
+				if port_granted='1' then
+					cmdstate<=cmdsetID;
+				end if;
+		when cmdsetID=>
+			if port_granted='1' then
+			cmdstate <=cmdpulse;
+			end if;
+		when cmdpulse =>
+			if port_granted='1' then
+			cmdstate <=cmdEnd;
+			end if;
+		when cmdend  =>
+			
+				cmdstate<=cmdstart; 
+			
+				
+	  
+	end case;
+  	end if;		
+end if;
+end process fsm_cmd;
+
+cmdaffect:process (cmdstate,fifo_empty_signal, port_granted, PORT_ID)
+begin
+case cmdstate is
+
+	when cmdstart =>
+						cmd_exec<='0';
+						cmd_pipeline_latch_en <='0';
+						cmd_priority_rotation <= '1';
+						cmd_request_latch_en<='0';
+						cmd_fifo_read_signal <= '0';
+						cmd_request_decoder_en <= '0';
+						cmd_data_signal<=(others=>'0');
+						cmd_data_out_pulse <= '0';
+	when cmdwait =>
+						cmd_exec<='1';
+						cmd_pipeline_latch_en <='0';
+						cmd_fifo_read_signal <= '0';
+						cmd_priority_rotation <= '1';    --sans priorité
+						cmd_request_latch_en<='0';
+						cmd_request_decoder_en <= not(fifo_empty_signal);   --demande d'émission
+						cmd_data_signal<=(others=>'0');
+						cmd_data_out_pulse <= '0';
+	when cmdread =>
+						cmd_exec<='1';
+						cmd_pipeline_latch_en <= '1';
+						cmd_fifo_read_signal <= '0';
+						cmd_request_latch_en<='1';    --mémoriser l'adresse de destination
+						cmd_request_decoder_en <= '1';                   --demande d'émission
+						cmd_data_out_pulse <= '0';
+						cmd_priority_rotation <= '0';                    --avec priorité
+						--cmd_data_signal<=(others=>'0');
+						cmd_data_signal<=Port_ID;  
+	when cmdsetdest  =>
+						--cmd_request_decoder_en <= '1';
+						cmd_exec<='1';
+						cmd_pipeline_latch_en <='1';
+						cmd_fifo_read_signal <='0';
+						cmd_request_latch_en<='0';
+						cmd_request_decoder_en <= '1';          --autoriser le decodeur à activer le dernier bit de request
+						cmd_data_out_pulse <= '0';
+						cmd_priority_rotation <= '0';
+						cmd_data_signal<=Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
+						
+	when cmdSetId =>
+						--cmd_request_decoder_en <= '1';
+						cmd_exec<='1';
+						cmd_pipeline_latch_en <='1';
+						cmd_fifo_read_signal <='0';
+						cmd_request_latch_en<='0';
+						cmd_request_decoder_en <= '1';          --autoriser le decodeur à activer le dernier bit de request
+						cmd_data_out_pulse <= '1';
+						cmd_priority_rotation <= '0';
+						cmd_data_signal<=Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
+											
+	when cmdsetcount =>
+								 
+						cmd_exec<='1';   
+						cmd_pipeline_latch_en <='1';
+						cmd_fifo_read_signal <='1';
+						cmd_request_latch_en<='0';
+						cmd_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+						cmd_data_out_pulse <= port_granted;
+						cmd_priority_rotation <= '0';
+						cmd_data_signal<=STD_LOGIC_VECTOR(to_unsigned(3,8));
+	
+	when cmdpulse =>	cmd_exec<='1';
+						cmd_pipeline_latch_en <='0';
+						cmd_fifo_read_signal <='0';
+						cmd_request_latch_en<='0';
+						cmd_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+						cmd_data_out_pulse <= port_granted;     --s'assurer que la dernière donnée est bien lue
+						cmd_priority_rotation <= '0';
+								--cmd_data_signal<=Port_ID ;
+						cmd_data_signal<=Port_ID; 
+						
+	when cmdend =>
+								cmd_exec<='0';
+								cmd_request_latch_en <= '0';
+								cmd_pipeline_latch_en <= '0';
+								cmd_fifo_read_signal <= '0';
+								cmd_request_latch_en<='0';
+								cmd_request_decoder_en <= '0';
+								cmd_data_out_pulse <= '0';
+								cmd_priority_rotation <= '1';
+								cmd_data_signal<=(others=>'0');
+								
+								
+end case ;
+end process cmdaffect;
+
+end Behavioral;
+
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.vhi
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.vhi	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.vhi	(revision 20)
@@ -0,0 +1,39 @@
+
+-- VHDL Instantiation Created from source file INPUT_PORT_MODULE.vhd -- 15:22:33 06/19/2011
+--
+-- Notes: 
+-- 1) This instantiation template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the instantiated module
+-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
+
+	COMPONENT INPUT_PORT_MODULE
+	PORT(
+		data_in : IN std_logic_vector(7 downto 0);
+		data_in_en : IN std_logic;
+		reset : IN std_logic;
+		clk : IN std_logic;
+		grant : IN std_logic_vector(4 downto 1);          
+		request : OUT std_logic_vector(4 downto 1);
+		fifo_full : OUT std_logic;
+		fifo_empty : OUT std_logic;
+		priority_rotation : OUT std_logic;
+		data_out : OUT std_logic_vector(7 downto 0);
+		data_out_pulse : OUT std_logic
+		);
+	END COMPONENT;
+
+	Inst_INPUT_PORT_MODULE: INPUT_PORT_MODULE PORT MAP(
+		data_in => ,
+		data_in_en => ,
+		reset => ,
+		clk => ,
+		request => ,
+		grant => ,
+		fifo_full => ,
+		fifo_empty => ,
+		priority_rotation => ,
+		data_out => ,
+		data_out_pulse => 
+	);
+
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.xst
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.xst	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.xst	(revision 20)
@@ -0,0 +1,55 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn INPUT_PORT_MODULE.prj
+-ifmt mixed
+-ofn INPUT_PORT_MODULE
+-ofmt NGC
+-p xc3s1200e-4-fg320
+-top INPUT_PORT_MODULE
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso INPUT_PORT_MODULE.lso
+-keep_hierarchy NO
+-netlist_hierarchy as_optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract YES
+-resource_sharing YES
+-async_to_sync NO
+-iobuf YES
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE_summary.html
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE_summary.html	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE_summary.html	(revision 20)
@@ -0,0 +1,107 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>GENERIC_16_16 Project Status (06/19/2011 - 19:25:38)</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>GENERIC_16_16.ise</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>Synthesized</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>INPUT_PORT_MODULE</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc3s1200e-4fg320</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 11.1</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD>Xilinx Default (unlocked)</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>
+<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
+<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slices</TD>
+<TD ALIGN=RIGHT>49</TD>
+<TD ALIGN=RIGHT>8672</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
+<TD ALIGN=RIGHT>57</TD>
+<TD ALIGN=RIGHT>17344</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
+<TD ALIGN=RIGHT>94</TD>
+<TD ALIGN=RIGHT>17344</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
+<TD ALIGN=RIGHT>31</TD>
+<TD ALIGN=RIGHT>250</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>12%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BRAMs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>28</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>3%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of GCLKs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>24</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>4%</TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16\INPUT_PORT_MODULE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>dim. 19. juin 14:27:18 2011</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 06/19/2011 - 19:26:32</center>
+</BODY></HTML>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE_vhdl.prj
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE_vhdl.prj	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE_vhdl.prj	(revision 20)
@@ -0,0 +1,3 @@
+vhdl work "C:\Documents and Settings\GENERAL\Bureau\GENERIC_16_16\RAM_256.vhd"
+vhdl work "C:\Documents and Settings\GENERAL\Bureau\GENERIC_16_16\FIFO_256_FWFT.vhd"
+vhdl work "C:\Documents and Settings\GENERAL\Bureau\GENERIC_16_16\INPUT_PORT_MODULE.vhd"
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE_xst.xrpt
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE_xst.xrpt	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE_xst.xrpt	(revision 20)
@@ -0,0 +1,133 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="nt" product="ISE" version="11.1">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="Xst" timeStamp="Sun Jun 19 14:27:08 2011">
+    <section stringID="User_Env">
+      <table stringID="User_EnvVar">
+        <column stringID="variable"/>
+        <column stringID="value"/>
+        <row stringID="row" value="0">
+          <item stringID="variable" value="XILINX"/>
+          <item stringID="value" value="C:\Xilinx\11.1\ISE"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="variable" value="XILINX_PLANAHEAD"/>
+          <item stringID="value" value="C:\Xilinx\11.1\PlanAhead"/>
+        </row>
+      </table>
+      <item stringID="User_EnvOs" value="OS Information">
+        <item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
+        <item stringID="User_EnvOsrelease" value="Service Pack 2  (build 2600)"/>
+      </item>
+      <item stringID="User_EnvHost" value="get-1c498a90fcb"/>
+      <table stringID="User_EnvCpu">
+        <column stringID="arch"/>
+        <column stringID="speed"/>
+        <row stringID="row" value="0">
+          <item stringID="arch" value="        Intel(R) Pentium(R) M processor 1400MHz"/>
+          <item stringID="speed" value="1398 MHz"/>
+        </row>
+      </table>
+    </section>
+    <section stringID="XST_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_RAMS" value="1"></item>
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="1"></item>
+      <item dataType="int" stringID="XST_COUNTERS" value="3"></item>
+      <item dataType="int" stringID="XST_REGISTERS" value="6">
+        <item dataType="int" stringID="XST_1BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_4BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_8BIT_REGISTER" value="4"/>
+      </item>
+      <item dataType="int" stringID="XST_COMPARATORS" value="1"></item>
+    </section>
+    <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_FSMS" value="2"/>
+      <item dataType="int" stringID="XST_RAMS" value="1"></item>
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="1"></item>
+      <item dataType="int" stringID="XST_COUNTERS" value="3"></item>
+      <item dataType="int" stringID="XST_REGISTERS" value="29">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="29"/>
+      </item>
+      <item dataType="int" stringID="XST_COMPARATORS" value="1"></item>
+    </section>
+    <section stringID="XST_FINAL_REGISTER_REPORT">
+      <item dataType="int" stringID="XST_REGISTERS" value="57">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="57"/>
+      </item>
+    </section>
+    <section stringID="XST_PARTITION_REPORT">
+      <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
+        <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+      </section>
+    </section>
+    <section stringID="XST_FINAL_REPORT">
+      <section stringID="XST_FINAL_RESULTS">
+        <item stringID="XST_RTL_TOP_LEVEL_OUTPUT_FILE_NAME" value="INPUT_PORT_MODULE.ngr"/>
+        <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="INPUT_PORT_MODULE"/>
+        <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
+        <item stringID="XST_OPTIMIZATION_GOAL" value="Speed"/>
+        <item stringID="XST_KEEP_HIERARCHY" value="NO"/>
+      </section>
+      <section stringID="XST_DESIGN_STATISTICS">
+        <item stringID="XST_IOS" value="31"/>
+      </section>
+      <section stringID="XST_CELL_USAGE">
+        <item dataType="int" stringID="XST_BELS" value="142">
+          <item dataType="int" stringID="XST_GND" value="1"/>
+          <item dataType="int" stringID="XST_INV" value="2"/>
+          <item dataType="int" stringID="XST_LUT1" value="14"/>
+          <item dataType="int" stringID="XST_LUT2" value="4"/>
+          <item dataType="int" stringID="XST_LUT3" value="20"/>
+          <item dataType="int" stringID="XST_LUT3D" value="1"/>
+          <item dataType="int" stringID="XST_LUT3L" value="2"/>
+          <item dataType="int" stringID="XST_LUT4" value="44"/>
+          <item dataType="int" stringID="XST_LUT4D" value="5"/>
+          <item dataType="int" stringID="XST_LUT4L" value="2"/>
+          <item dataType="int" stringID="XST_MUXCY" value="21"/>
+          <item dataType="int" stringID="XST_MUXF5" value="1"/>
+          <item dataType="int" stringID="XST_VCC" value="1"/>
+          <item dataType="int" stringID="XST_XORCY" value="24"/>
+        </item>
+        <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="57">
+          <item dataType="int" stringID="XST_FDE" value="8"/>
+          <item dataType="int" stringID="XST_FDR" value="3"/>
+          <item dataType="int" stringID="XST_FDRE" value="37"/>
+          <item dataType="int" stringID="XST_FDRS" value="9"/>
+        </item>
+        <item dataType="int" stringID="XST_RAMS" value="1">
+          <item dataType="int" stringID="XST_RAMB16S9S9" value="1"/>
+        </item>
+        <item dataType="int" stringID="XST_CLOCK_BUFFERS" value="1">
+          <item dataType="int" stringID="XST_BUFGP" value="1"/>
+        </item>
+        <item dataType="int" stringID="XST_IO_BUFFERS" value="30">
+          <item dataType="int" stringID="XST_IBUF" value="14"/>
+          <item dataType="int" stringID="XST_OBUF" value="16"/>
+        </item>
+      </section>
+    </section>
+    <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
+      <item stringID="XST_SELECTED_DEVICE" value="3s1200efg320-4"/>
+      <item AVAILABLE="8672" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="49"/>
+      <item AVAILABLE="17344" dataType="int" label="Number of Slice Flip Flops" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="57"/>
+      <item AVAILABLE="17344" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="94"/>
+      <item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="31"/>
+      <item AVAILABLE="250" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="31"/>
+      <item AVAILABLE="28" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="1"/>
+      <item AVAILABLE="24" dataType="int" label="Number of GCLKs" stringID="XST_NUMBER_OF_GCLKS" value="1"/>
+    </section>
+    <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
+      <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+    </section>
+    <section stringID="XST_ERRORS_STATISTICS">
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="2"/>
+    </section>
+  </application>
+
+</document>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/OUTPUT_PORT_MODULE.cmd_log
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/OUTPUT_PORT_MODULE.cmd_log	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/OUTPUT_PORT_MODULE.cmd_log	(revision 20)
@@ -0,0 +1,3 @@
+vhdtdtfi -lib work RAM_256.vhd -lib work FIFO_256_FWFT.vhd -lib work OUTPUT_PORT_MODULE.vhd -prj GENERIC_16_16 -o OUTPUT_PORT_MODULE.spl -module OUTPUT_PORT_MODULE -template d:/Xilinx/12.3/ISE_DS/ISE//data/splfile.tft -deleteonerror 
+spl2sym -intstyle ise -family virtex5 OUTPUT_PORT_MODULE.spl {C:/Core MPI/SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.sym} 
+vhdtdtfi -prj GENERIC_16_16 -o "C:/Core MPI/SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhi" -lib work "C:/Core MPI/SWITCH_GENERIC_16_16//OUTPUT_PORT_MODULE.vhd" -module OUTPUT_PORT_MODULE -template d:/Xilinx/12.3/ISE_DS/ISE//data/vhdlinst.tft -deleteonerror 
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/OUTPUT_PORT_MODULE.sym
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/OUTPUT_PORT_MODULE.sym	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/OUTPUT_PORT_MODULE.sym	(revision 20)
@@ -0,0 +1,35 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="OUTPUT_PORT_MODULE">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2012-2-10T16:50:49</timestamp>
+    <pin polarity="Input" x="0" y="-288" name="reset" />
+    <pin polarity="Input" x="0" y="-224" name="clk" />
+    <pin polarity="Input" x="0" y="-160" name="wr_en" />
+    <pin polarity="Input" x="0" y="-96" name="rd_out_en" />
+    <pin polarity="Input" x="0" y="-32" name="data_in(7:0)" />
+    <pin polarity="Output" x="432" y="-288" name="fifo_full" />
+    <pin polarity="Output" x="432" y="-160" name="data_avalaible" />
+    <pin polarity="Output" x="432" y="-32" name="data_out(7:0)" />
+    <graph>
+        <rect width="304" x="64" y="-320" height="320" />
+        <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="216" y="-328" type="symbol" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin reset" />
+        <line x2="0" y1="-288" y2="-288" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin clk" />
+        <line x2="0" y1="-224" y2="-224" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin wr_en" />
+        <line x2="0" y1="-160" y2="-160" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin rd_out_en" />
+        <line x2="0" y1="-96" y2="-96" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin data_in(7:0)" />
+        <rect width="64" x="0" y="-44" height="24" />
+        <line x2="0" y1="-32" y2="-32" x1="64" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-288" type="pin fifo_full" />
+        <line x2="432" y1="-288" y2="-288" x1="368" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-160" type="pin data_avalaible" />
+        <line x2="432" y1="-160" y2="-160" x1="368" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-32" type="pin data_out(7:0)" />
+        <rect width="64" x="368" y="-44" height="24" />
+        <line x2="432" y1="-32" y2="-32" x1="368" />
+    </graph>
+</symbol>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/OUTPUT_PORT_MODULE.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/OUTPUT_PORT_MODULE.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/OUTPUT_PORT_MODULE.vhd	(revision 20)
@@ -0,0 +1,75 @@
+
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    09:29:48 04/18/2011 
+-- Design Name: 
+-- Module Name:    OUTPUT_PORT_MODULE - Behavioral_description 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description:
+-- cette version du module de sortie se limite à une instance du fifo ordinaire 
+-- les données son emise en sortie à chaque cycle d'horloge
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+Library NocLib;
+use NocLib.CoreTypes.all;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity OUTPUT_PORT_MODULE is
+    Port ( data_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           reset : in  STD_LOGIC;
+           clk : in  STD_LOGIC;
+           wr_en : in  STD_LOGIC;
+           data_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+			  fifo_full : out std_logic;
+			  data_avalaible : out std_logic;
+			  rd_out_en : in  STD_LOGIC);
+end OUTPUT_PORT_MODULE;
+
+architecture Behavioral_description of OUTPUT_PORT_MODULE is
+-- declaration du FIFO 64 octets
+component FIFO_256_FWFT
+	port (
+	clk: IN std_logic;
+	din: IN std_logic_VECTOR(Word-1 downto 0);
+	rd_en: IN std_logic;
+	srst: IN std_logic;
+	wr_en: IN std_logic;
+	dout: OUT std_logic_VECTOR(Word-1 downto 0);
+	empty: OUT std_logic;
+	full: OUT std_logic);
+end component;
+--definition du type etat pour les fsm
+signal empty_signal : std_logic;	
+begin
+-- instantiation du FIFO_64
+ OUTPUT_PORT_FIFO : FIFO_256_FWFT
+		port map (
+			clk => clk,
+			din => data_in,
+			rd_en => rd_out_en,
+			srst => reset,
+			wr_en => wr_en,
+			dout => data_out,
+			empty => empty_signal,
+			full => fifo_full);
+			
+data_avalaible <= not empty_signal;
+
+end Behavioral_description;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/PortRam.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/PortRam.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/PortRam.vhd	(revision 20)
@@ -0,0 +1,74 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: GAMOM NGOUNOU ROland Christian
+-- 
+-- Create Date:    12:49:02 02/02/2012 
+-- Design Name: 
+-- Module Name:    Portdata - arch_portdata 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use ieee.numeric_std.all;
+--USE ieee.std_logic_arith.all;
+
+
+entity Portdata is
+generic (N:Natural:=8);
+    Port ( clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+           wr_en : in  STD_LOGIC;
+           rd_en : in  STD_LOGIC;
+           datain : in  STD_LOGIC_VECTOR (N-1 downto 0);
+           dataout : out  STD_LOGIC_VECTOR (N-1 downto 0);
+           address : in  STD_LOGIC_VECTOR (3 downto 0));
+end Portdata;
+
+architecture arch_portdata of Portdata is
+
+Type Ram_type is array (0 to 3) of std_logic_vector (N-1 downto 0);
+constant zero : integer :=0;
+constant Zero_log:STD_LOGIC_VECTOR:=STD_LOGIC_VECTOR(to_unsigned(zero,N));
+constant portid:STD_LOGIC_VECTOR:="00000001";
+signal RAM : Ram_type;
+
+constant max_address : natural:=15;
+signal address_counter : natural := 0;
+begin
+
+dataout <= RAM(address_counter);
+process (clk)
+  begin
+     if rising_edge(clk) then
+        if reset = '1' then
+            address_counter <= 0;
+				for address_counter in 1 to max_address 			--la mémoire d'adresse 0 contient 
+				loop															-- l'ID du port
+					RAM(address_counter)<=(others=>'0');
+				end loop;
+				RAM(0)<=portid;                                -- portid est une valeur fixé par le générateur de port
+        elsif rd_en='1' and wr_en='0' then 
+		     
+			  RAM(to_integer(unsigned(address)))<=datain;
+		  
+		  elsif rd_en='0' and wr_en='1' then
+			 dataout <= RAM(to_integer(unsigned(address)));
+			  
+		  end if;
+    end if;
+  end process;
+end arch_portdata;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Proto_receiv.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Proto_receiv.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Proto_receiv.vhd	(revision 20)
@@ -0,0 +1,149 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    17:03:41 10/22/2012 
+-- Design Name: 
+-- Module Name:    Proto_receiv - ReceiveProto 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use work.CoreTypes.all;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Proto_receiv is
+ generic (sizemem : natural := 64);
+ port (
+ clk,reset : in std_logic;
+ fifo_empty,fifo_full : in std_logic;
+ rcv_start : in std_logic; --début de la réception
+ rcv_ack :in std_logic;   -- acquittement de la réception
+ rcv_comp : out std_logic; -- fin de la réception
+  pop : out std_logic:='0';
+ fifo_out : in std_logic_vector(Word-1 downto 0);
+ mem :out memory(0 to sizemem-1));
+end Proto_receiv;
+
+architecture ReceiveProto of Proto_receiv is
+type typ_receiv is (r_wait,r_head,r_len,r_glen,r_data,r_pulse,r_end);
+
+			 signal spush,spop :  std_logic:='0';
+          SIGNAL data_in:  std_logic_vector(7 downto 0);
+			 signal etrec :typ_receiv;
+begin
+
+proc_receiv : process (clk,reset)
+variable dlen,i: natural range 0 to 255 :=0;
+
+	begin
+	if reset='1' then 
+				 etrec<=r_wait;
+				 
+				else  
+						if rising_edge(clk) then -- le process s'exécute sur chaque front 
+															-- montant de l'horloge
+						case etrec is
+						when r_wait  =>
+							
+							i:=0;
+							if fifo_empty='0' and rcv_start='1' then
+							
+							etrec<=r_head;
+							mem(0)<=fifo_out;
+							
+							end if;
+						when r_head  =>
+							mem(0)<=fifo_out;  --l'en-tête
+							
+							etrec<=r_len;
+							
+						
+						when r_len =>
+								dlen:=to_integer(unsigned(fifo_out));
+								mem(1)<=fifo_out; -- la longueur
+								etrec<=r_data;
+								
+								i:=1;
+								
+						when r_data  =>
+								if fifo_empty='0' then
+									if i<dlen-3 then
+										i:=i+1;
+										mem(i)<=fifo_out;
+										
+										
+									else
+										etrec<=r_pulse;
+										
+										mem(i+1)<=fifo_out;
+									end if;
+									-- time out à prévoir ici
+								end if;
+						when r_pulse =>
+								etrec<=r_end;
+								
+						when r_end  =>
+								if rcv_ack='1' then
+									etrec<=r_wait;
+								end if;
+								
+						when others =>
+								
+								
+								etrec<=r_wait;
+						end case;
+						end if;
+				end if;
+	end process;
+	
+	pop<=spop;
+	
+rec_value : process (etrec)
+begin
+case etrec is
+					when r_wait  =>
+						spop<='0';
+						rcv_comp<='0';
+					when r_head  =>
+							
+							spop<='1';
+							rcv_comp<='0';
+--					when r_sync =>
+--							spop<='1';
+--							rcv_comp<='0';
+					when r_len =>
+							spop<='1';
+					when r_data =>
+							spop<='1';
+					when r_pulse =>
+								spop<='0';
+								rcv_comp<='1';
+					when r_end =>
+							spop<='0';
+							rcv_comp<='1';
+					when others =>
+							spop<='0';
+							rcv_comp<='0';
+				end case;
+	end process;
+end ReceiveProto;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/RAM_256.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/RAM_256.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/RAM_256.vhd	(revision 20)
@@ -0,0 +1,68 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    18:54:08 04/19/2011 
+-- Design Name: 
+-- Module Name:    RAM_64 - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: SYNTHESE d'une RAM 256 octet par inferation
+-- la ram possède un port d'écriture et un port de lecture
+-- le port primaire est à lecture et ecrite et le port secondaire à lecture seule
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--Library NocLib;
+--use NocLib.CoreTypes.all;
+use work.CoreTypes.all;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity RAM_256 is
+    Port ( clka, clkb : in std_logic;
+			  wea : in std_logic;
+			  ena, enb : in std_logic;
+			  addra, addrb : in std_logic_vector(Word-1 downto 0);
+			  dia : in std_logic_vector(Word-1 downto 0);
+			  dob : out std_logic_vector(Word-1 downto 0));
+end RAM_256;
+
+architecture Behavioral of RAM_256 is
+	type ram_type is array (255 downto 0) of std_logic_vector (Word-1 downto 0);
+	signal RAM: ram_type;
+begin
+ process (clka)
+	begin
+		if clka'event and clka = '1' then
+			if ena = '1' then
+				if wea = '1' then
+					RAM(conv_integer(addra)) <= dia;
+				end if;
+			end if;
+		 end if;
+ end process;
+ 
+ process (clkb)
+	begin
+		if clkb'event and clkb = '1' then
+			if enb = '1' then
+				dob <= RAM(conv_integer(addrb)) ;
+			end if;
+		end if;
+ end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER10_10.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER10_10.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER10_10.VHD	(revision 20)
@@ -0,0 +1,1212 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler10_10 is
+    Port ( Request : in  STD_LOGIC_VECTOR (100 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (10 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (10 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (100 downto 1));
+end Scheduler10_10;
+
+architecture Behavioral of Scheduler10_10 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(19 downto 1) of STD_LOGIC_VECTOR(10 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (19 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(100 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(100 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 1023 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(11)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(12)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(13)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(14)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(15)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(16)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(17)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(18)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) or Signal_grant(19)(9); --  Grant(1,9)
+Grant(10)  <= Signal_grant(10)(10) ;                      --  Grant(1,10)
+Grant(11)  <= Signal_grant(2)(1) or Signal_grant(12)(1); --  Grant(2,1)
+Grant(12)  <= Signal_grant(3)(2) or Signal_grant(13)(2); --  Grant(2,2)
+Grant(13)  <= Signal_grant(4)(3) or Signal_grant(14)(3); --  Grant(2,3)
+Grant(14)  <= Signal_grant(5)(4) or Signal_grant(15)(4); --  Grant(2,4)
+Grant(15)  <= Signal_grant(6)(5) or Signal_grant(16)(5); --  Grant(2,5)
+Grant(16)  <= Signal_grant(7)(6) or Signal_grant(17)(6); --  Grant(2,6)
+Grant(17)  <= Signal_grant(8)(7) or Signal_grant(18)(7); --  Grant(2,7)
+Grant(18)  <= Signal_grant(9)(8) or Signal_grant(19)(8); --  Grant(2,8)
+Grant(19)  <= Signal_grant(10)(9) ;                      --  Grant(2,9)
+Grant(20)  <= Signal_grant(1)(10) or Signal_grant(11)(10); --  Grant(2,10)
+Grant(21)  <= Signal_grant(3)(1) or Signal_grant(13)(1); --  Grant(3,1)
+Grant(22)  <= Signal_grant(4)(2) or Signal_grant(14)(2); --  Grant(3,2)
+Grant(23)  <= Signal_grant(5)(3) or Signal_grant(15)(3); --  Grant(3,3)
+Grant(24)  <= Signal_grant(6)(4) or Signal_grant(16)(4); --  Grant(3,4)
+Grant(25)  <= Signal_grant(7)(5) or Signal_grant(17)(5); --  Grant(3,5)
+Grant(26)  <= Signal_grant(8)(6) or Signal_grant(18)(6); --  Grant(3,6)
+Grant(27)  <= Signal_grant(9)(7) or Signal_grant(19)(7); --  Grant(3,7)
+Grant(28)  <= Signal_grant(10)(8) ;                      --  Grant(3,8)
+Grant(29)  <= Signal_grant(1)(9) or Signal_grant(11)(9); --  Grant(3,9)
+Grant(30)  <= Signal_grant(2)(10) or Signal_grant(12)(10); --  Grant(3,10)
+Grant(31)  <= Signal_grant(4)(1) or Signal_grant(14)(1); --  Grant(4,1)
+Grant(32)  <= Signal_grant(5)(2) or Signal_grant(15)(2); --  Grant(4,2)
+Grant(33)  <= Signal_grant(6)(3) or Signal_grant(16)(3); --  Grant(4,3)
+Grant(34)  <= Signal_grant(7)(4) or Signal_grant(17)(4); --  Grant(4,4)
+Grant(35)  <= Signal_grant(8)(5) or Signal_grant(18)(5); --  Grant(4,5)
+Grant(36)  <= Signal_grant(9)(6) or Signal_grant(19)(6); --  Grant(4,6)
+Grant(37)  <= Signal_grant(10)(7) ;                      --  Grant(4,7)
+Grant(38)  <= Signal_grant(1)(8) or Signal_grant(11)(8); --  Grant(4,8)
+Grant(39)  <= Signal_grant(2)(9) or Signal_grant(12)(9); --  Grant(4,9)
+Grant(40)  <= Signal_grant(3)(10) or Signal_grant(13)(10); --  Grant(4,10)
+Grant(41)  <= Signal_grant(5)(1) or Signal_grant(15)(1); --  Grant(5,1)
+Grant(42)  <= Signal_grant(6)(2) or Signal_grant(16)(2); --  Grant(5,2)
+Grant(43)  <= Signal_grant(7)(3) or Signal_grant(17)(3); --  Grant(5,3)
+Grant(44)  <= Signal_grant(8)(4) or Signal_grant(18)(4); --  Grant(5,4)
+Grant(45)  <= Signal_grant(9)(5) or Signal_grant(19)(5); --  Grant(5,5)
+Grant(46)  <= Signal_grant(10)(6) ;                      --  Grant(5,6)
+Grant(47)  <= Signal_grant(1)(7) or Signal_grant(11)(7); --  Grant(5,7)
+Grant(48)  <= Signal_grant(2)(8) or Signal_grant(12)(8); --  Grant(5,8)
+Grant(49)  <= Signal_grant(3)(9) or Signal_grant(13)(9); --  Grant(5,9)
+Grant(50)  <= Signal_grant(4)(10) or Signal_grant(14)(10); --  Grant(5,10)
+Grant(51)  <= Signal_grant(6)(1) or Signal_grant(16)(1); --  Grant(6,1)
+Grant(52)  <= Signal_grant(7)(2) or Signal_grant(17)(2); --  Grant(6,2)
+Grant(53)  <= Signal_grant(8)(3) or Signal_grant(18)(3); --  Grant(6,3)
+Grant(54)  <= Signal_grant(9)(4) or Signal_grant(19)(4); --  Grant(6,4)
+Grant(55)  <= Signal_grant(10)(5) ;                      --  Grant(6,5)
+Grant(56)  <= Signal_grant(1)(6) or Signal_grant(11)(6); --  Grant(6,6)
+Grant(57)  <= Signal_grant(2)(7) or Signal_grant(12)(7); --  Grant(6,7)
+Grant(58)  <= Signal_grant(3)(8) or Signal_grant(13)(8); --  Grant(6,8)
+Grant(59)  <= Signal_grant(4)(9) or Signal_grant(14)(9); --  Grant(6,9)
+Grant(60)  <= Signal_grant(5)(10) or Signal_grant(15)(10); --  Grant(6,10)
+Grant(61)  <= Signal_grant(7)(1) or Signal_grant(17)(1); --  Grant(7,1)
+Grant(62)  <= Signal_grant(8)(2) or Signal_grant(18)(2); --  Grant(7,2)
+Grant(63)  <= Signal_grant(9)(3) or Signal_grant(19)(3); --  Grant(7,3)
+Grant(64)  <= Signal_grant(10)(4) ;                      --  Grant(7,4)
+Grant(65)  <= Signal_grant(1)(5) or Signal_grant(11)(5); --  Grant(7,5)
+Grant(66)  <= Signal_grant(2)(6) or Signal_grant(12)(6); --  Grant(7,6)
+Grant(67)  <= Signal_grant(3)(7) or Signal_grant(13)(7); --  Grant(7,7)
+Grant(68)  <= Signal_grant(4)(8) or Signal_grant(14)(8); --  Grant(7,8)
+Grant(69)  <= Signal_grant(5)(9) or Signal_grant(15)(9); --  Grant(7,9)
+Grant(70)  <= Signal_grant(6)(10) or Signal_grant(16)(10); --  Grant(7,10)
+Grant(71)  <= Signal_grant(8)(1) or Signal_grant(18)(1); --  Grant(8,1)
+Grant(72)  <= Signal_grant(9)(2) or Signal_grant(19)(2); --  Grant(8,2)
+Grant(73)  <= Signal_grant(10)(3) ;                      --  Grant(8,3)
+Grant(74)  <= Signal_grant(1)(4) or Signal_grant(11)(4); --  Grant(8,4)
+Grant(75)  <= Signal_grant(2)(5) or Signal_grant(12)(5); --  Grant(8,5)
+Grant(76)  <= Signal_grant(3)(6) or Signal_grant(13)(6); --  Grant(8,6)
+Grant(77)  <= Signal_grant(4)(7) or Signal_grant(14)(7); --  Grant(8,7)
+Grant(78)  <= Signal_grant(5)(8) or Signal_grant(15)(8); --  Grant(8,8)
+Grant(79)  <= Signal_grant(6)(9) or Signal_grant(16)(9); --  Grant(8,9)
+Grant(80)  <= Signal_grant(7)(10) or Signal_grant(17)(10); --  Grant(8,10)
+Grant(81)  <= Signal_grant(9)(1) or Signal_grant(19)(1); --  Grant(9,1)
+Grant(82)  <= Signal_grant(10)(2) ;                      --  Grant(9,2)
+Grant(83)  <= Signal_grant(1)(3) or Signal_grant(11)(3); --  Grant(9,3)
+Grant(84)  <= Signal_grant(2)(4) or Signal_grant(12)(4); --  Grant(9,4)
+Grant(85)  <= Signal_grant(3)(5) or Signal_grant(13)(5); --  Grant(9,5)
+Grant(86)  <= Signal_grant(4)(6) or Signal_grant(14)(6); --  Grant(9,6)
+Grant(87)  <= Signal_grant(5)(7) or Signal_grant(15)(7); --  Grant(9,7)
+Grant(88)  <= Signal_grant(6)(8) or Signal_grant(16)(8); --  Grant(9,8)
+Grant(89)  <= Signal_grant(7)(9) or Signal_grant(17)(9); --  Grant(9,9)
+Grant(90)  <= Signal_grant(8)(10) or Signal_grant(18)(10); --  Grant(9,10)
+Grant(91)  <= Signal_grant(10)(1) ;                      --  Grant(10,1)
+Grant(92)  <= Signal_grant(1)(2) or Signal_grant(11)(2); --  Grant(10,2)
+Grant(93)  <= Signal_grant(2)(3) or Signal_grant(12)(3); --  Grant(10,3)
+Grant(94)  <= Signal_grant(3)(4) or Signal_grant(13)(4); --  Grant(10,4)
+Grant(95)  <= Signal_grant(4)(5) or Signal_grant(14)(5); --  Grant(10,5)
+Grant(96)  <= Signal_grant(5)(6) or Signal_grant(15)(6); --  Grant(10,6)
+Grant(97)  <= Signal_grant(6)(7) or Signal_grant(16)(7); --  Grant(10,7)
+Grant(98)  <= Signal_grant(7)(8) or Signal_grant(17)(8); --  Grant(10,8)
+Grant(99)  <= Signal_grant(8)(9) or Signal_grant(18)(9); --  Grant(10,9)
+Grant(100)  <= Signal_grant(9)(10) or Signal_grant(19)(10); --  Grant(10,10)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(92), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(83), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(74), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(65), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(56), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(47), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(38), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(29), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+Arbiter_1_10 : Arbiter
+
+PORT MAP (Request => Request(20), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(10),  
+South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(1)(1), West => east_2_west(1)(10), P => Signal_priority(18), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+Arbiter_2_10 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10),  
+South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(2)(1), West => east_2_west(2)(10), P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+Arbiter_3_10 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10),  
+South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(3)(1), West => east_2_west(3)(10), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+Arbiter_4_10 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10),  
+South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(4)(1), West => east_2_west(4)(10), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+Arbiter_5_10 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10),  
+South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(5)(1), West => east_2_west(5)(10), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+Arbiter_6_10 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10),  
+South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(6)(1), West => east_2_west(6)(10), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+Arbiter_7_10 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10),  
+South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(7)(1), West => east_2_west(7)(10), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+Arbiter_8_10 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10),  
+South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(8)(1), West => east_2_west(8)(10), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+Arbiter_9_10 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10),  
+South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(9)(1), West => east_2_west(9)(10), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+Arbiter_10_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10),  
+South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(10)(1), West => east_2_west(10)(10), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+Arbiter_11_10 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10),  
+South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(11)(1), West => east_2_west(11)(10), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+Arbiter_12_10 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10),  
+South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(12)(1), West => east_2_west(12)(10), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+Arbiter_13_10 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10),  
+South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(13)(1), West => east_2_west(13)(10), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+Arbiter_14_10 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10),  
+South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(14)(1), West => east_2_west(14)(10), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+Arbiter_15_10 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10),  
+South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(15)(1), West => east_2_west(15)(10), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+Arbiter_16_10 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10),  
+South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(16)(1), West => east_2_west(16)(10), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+Arbiter_17_10 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10),  
+South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); 
+
+-------------------------- Diagonale n° 18 
+
+
+Arbiter_18_1 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(17)(1), West => east_2_west(17)(10), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); 
+
+Arbiter_18_2 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); 
+
+Arbiter_18_3 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); 
+
+Arbiter_18_4 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); 
+
+Arbiter_18_5 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); 
+
+Arbiter_18_6 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); 
+
+Arbiter_18_7 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); 
+
+Arbiter_18_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); 
+
+Arbiter_18_9 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); 
+
+Arbiter_18_10 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10),  
+South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); 
+
+-------------------------- Diagonale n° 19 
+
+
+Arbiter_19_1 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(18)(1), West => east_2_west(18)(10), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); 
+
+Arbiter_19_2 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); 
+
+Arbiter_19_3 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); 
+
+Arbiter_19_4 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); 
+
+Arbiter_19_5 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); 
+
+Arbiter_19_6 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); 
+
+Arbiter_19_7 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); 
+
+Arbiter_19_8 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); 
+
+Arbiter_19_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); 
+
+Arbiter_19_10 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10),  
+South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "1111111111000000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "1111111111000000000" => Signal_priority <= "0111111111100000000";
+		       when "0111111111100000000" => Signal_priority <= "0011111111110000000";
+		       when "0011111111110000000" => Signal_priority <= "0001111111111000000";
+		       when "0001111111111000000" => Signal_priority <= "0000111111111100000";
+		       when "0000111111111100000" => Signal_priority <= "0000011111111110000";
+		       when "0000011111111110000" => Signal_priority <= "0000001111111111000";
+		       when "0000001111111111000" => Signal_priority <= "0000000111111111100";
+		       when "0000000111111111100" => Signal_priority <= "0000000011111111110";
+		       when "0000000011111111110" => Signal_priority <= "0000000001111111111";
+		       when "0000000001111111111" => Signal_priority <= "1111111111000000000";
+		       when others    => Signal_priority <= "1111111111000000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER11_11.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER11_11.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER11_11.VHD	(revision 20)
@@ -0,0 +1,1445 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler11_11 is
+    Port ( Request : in  STD_LOGIC_VECTOR (121 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (11 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (11 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (121 downto 1));
+end Scheduler11_11;
+
+architecture Behavioral of Scheduler11_11 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(21 downto 1) of STD_LOGIC_VECTOR(11 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (21 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(121 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(121 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 2047 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(12)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(13)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(14)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(15)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(16)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(17)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(18)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(19)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) or Signal_grant(20)(9); --  Grant(1,9)
+Grant(10)  <= Signal_grant(10)(10) or Signal_grant(21)(10); --  Grant(1,10)
+Grant(11)  <= Signal_grant(11)(11) ;                      --  Grant(1,11)
+Grant(12)  <= Signal_grant(2)(1) or Signal_grant(13)(1); --  Grant(2,1)
+Grant(13)  <= Signal_grant(3)(2) or Signal_grant(14)(2); --  Grant(2,2)
+Grant(14)  <= Signal_grant(4)(3) or Signal_grant(15)(3); --  Grant(2,3)
+Grant(15)  <= Signal_grant(5)(4) or Signal_grant(16)(4); --  Grant(2,4)
+Grant(16)  <= Signal_grant(6)(5) or Signal_grant(17)(5); --  Grant(2,5)
+Grant(17)  <= Signal_grant(7)(6) or Signal_grant(18)(6); --  Grant(2,6)
+Grant(18)  <= Signal_grant(8)(7) or Signal_grant(19)(7); --  Grant(2,7)
+Grant(19)  <= Signal_grant(9)(8) or Signal_grant(20)(8); --  Grant(2,8)
+Grant(20)  <= Signal_grant(10)(9) or Signal_grant(21)(9); --  Grant(2,9)
+Grant(21)  <= Signal_grant(11)(10) ;                      --  Grant(2,10)
+Grant(22)  <= Signal_grant(1)(11) or Signal_grant(12)(11); --  Grant(2,11)
+Grant(23)  <= Signal_grant(3)(1) or Signal_grant(14)(1); --  Grant(3,1)
+Grant(24)  <= Signal_grant(4)(2) or Signal_grant(15)(2); --  Grant(3,2)
+Grant(25)  <= Signal_grant(5)(3) or Signal_grant(16)(3); --  Grant(3,3)
+Grant(26)  <= Signal_grant(6)(4) or Signal_grant(17)(4); --  Grant(3,4)
+Grant(27)  <= Signal_grant(7)(5) or Signal_grant(18)(5); --  Grant(3,5)
+Grant(28)  <= Signal_grant(8)(6) or Signal_grant(19)(6); --  Grant(3,6)
+Grant(29)  <= Signal_grant(9)(7) or Signal_grant(20)(7); --  Grant(3,7)
+Grant(30)  <= Signal_grant(10)(8) or Signal_grant(21)(8); --  Grant(3,8)
+Grant(31)  <= Signal_grant(11)(9) ;                      --  Grant(3,9)
+Grant(32)  <= Signal_grant(1)(10) or Signal_grant(12)(10); --  Grant(3,10)
+Grant(33)  <= Signal_grant(2)(11) or Signal_grant(13)(11); --  Grant(3,11)
+Grant(34)  <= Signal_grant(4)(1) or Signal_grant(15)(1); --  Grant(4,1)
+Grant(35)  <= Signal_grant(5)(2) or Signal_grant(16)(2); --  Grant(4,2)
+Grant(36)  <= Signal_grant(6)(3) or Signal_grant(17)(3); --  Grant(4,3)
+Grant(37)  <= Signal_grant(7)(4) or Signal_grant(18)(4); --  Grant(4,4)
+Grant(38)  <= Signal_grant(8)(5) or Signal_grant(19)(5); --  Grant(4,5)
+Grant(39)  <= Signal_grant(9)(6) or Signal_grant(20)(6); --  Grant(4,6)
+Grant(40)  <= Signal_grant(10)(7) or Signal_grant(21)(7); --  Grant(4,7)
+Grant(41)  <= Signal_grant(11)(8) ;                      --  Grant(4,8)
+Grant(42)  <= Signal_grant(1)(9) or Signal_grant(12)(9); --  Grant(4,9)
+Grant(43)  <= Signal_grant(2)(10) or Signal_grant(13)(10); --  Grant(4,10)
+Grant(44)  <= Signal_grant(3)(11) or Signal_grant(14)(11); --  Grant(4,11)
+Grant(45)  <= Signal_grant(5)(1) or Signal_grant(16)(1); --  Grant(5,1)
+Grant(46)  <= Signal_grant(6)(2) or Signal_grant(17)(2); --  Grant(5,2)
+Grant(47)  <= Signal_grant(7)(3) or Signal_grant(18)(3); --  Grant(5,3)
+Grant(48)  <= Signal_grant(8)(4) or Signal_grant(19)(4); --  Grant(5,4)
+Grant(49)  <= Signal_grant(9)(5) or Signal_grant(20)(5); --  Grant(5,5)
+Grant(50)  <= Signal_grant(10)(6) or Signal_grant(21)(6); --  Grant(5,6)
+Grant(51)  <= Signal_grant(11)(7) ;                      --  Grant(5,7)
+Grant(52)  <= Signal_grant(1)(8) or Signal_grant(12)(8); --  Grant(5,8)
+Grant(53)  <= Signal_grant(2)(9) or Signal_grant(13)(9); --  Grant(5,9)
+Grant(54)  <= Signal_grant(3)(10) or Signal_grant(14)(10); --  Grant(5,10)
+Grant(55)  <= Signal_grant(4)(11) or Signal_grant(15)(11); --  Grant(5,11)
+Grant(56)  <= Signal_grant(6)(1) or Signal_grant(17)(1); --  Grant(6,1)
+Grant(57)  <= Signal_grant(7)(2) or Signal_grant(18)(2); --  Grant(6,2)
+Grant(58)  <= Signal_grant(8)(3) or Signal_grant(19)(3); --  Grant(6,3)
+Grant(59)  <= Signal_grant(9)(4) or Signal_grant(20)(4); --  Grant(6,4)
+Grant(60)  <= Signal_grant(10)(5) or Signal_grant(21)(5); --  Grant(6,5)
+Grant(61)  <= Signal_grant(11)(6) ;                      --  Grant(6,6)
+Grant(62)  <= Signal_grant(1)(7) or Signal_grant(12)(7); --  Grant(6,7)
+Grant(63)  <= Signal_grant(2)(8) or Signal_grant(13)(8); --  Grant(6,8)
+Grant(64)  <= Signal_grant(3)(9) or Signal_grant(14)(9); --  Grant(6,9)
+Grant(65)  <= Signal_grant(4)(10) or Signal_grant(15)(10); --  Grant(6,10)
+Grant(66)  <= Signal_grant(5)(11) or Signal_grant(16)(11); --  Grant(6,11)
+Grant(67)  <= Signal_grant(7)(1) or Signal_grant(18)(1); --  Grant(7,1)
+Grant(68)  <= Signal_grant(8)(2) or Signal_grant(19)(2); --  Grant(7,2)
+Grant(69)  <= Signal_grant(9)(3) or Signal_grant(20)(3); --  Grant(7,3)
+Grant(70)  <= Signal_grant(10)(4) or Signal_grant(21)(4); --  Grant(7,4)
+Grant(71)  <= Signal_grant(11)(5) ;                      --  Grant(7,5)
+Grant(72)  <= Signal_grant(1)(6) or Signal_grant(12)(6); --  Grant(7,6)
+Grant(73)  <= Signal_grant(2)(7) or Signal_grant(13)(7); --  Grant(7,7)
+Grant(74)  <= Signal_grant(3)(8) or Signal_grant(14)(8); --  Grant(7,8)
+Grant(75)  <= Signal_grant(4)(9) or Signal_grant(15)(9); --  Grant(7,9)
+Grant(76)  <= Signal_grant(5)(10) or Signal_grant(16)(10); --  Grant(7,10)
+Grant(77)  <= Signal_grant(6)(11) or Signal_grant(17)(11); --  Grant(7,11)
+Grant(78)  <= Signal_grant(8)(1) or Signal_grant(19)(1); --  Grant(8,1)
+Grant(79)  <= Signal_grant(9)(2) or Signal_grant(20)(2); --  Grant(8,2)
+Grant(80)  <= Signal_grant(10)(3) or Signal_grant(21)(3); --  Grant(8,3)
+Grant(81)  <= Signal_grant(11)(4) ;                      --  Grant(8,4)
+Grant(82)  <= Signal_grant(1)(5) or Signal_grant(12)(5); --  Grant(8,5)
+Grant(83)  <= Signal_grant(2)(6) or Signal_grant(13)(6); --  Grant(8,6)
+Grant(84)  <= Signal_grant(3)(7) or Signal_grant(14)(7); --  Grant(8,7)
+Grant(85)  <= Signal_grant(4)(8) or Signal_grant(15)(8); --  Grant(8,8)
+Grant(86)  <= Signal_grant(5)(9) or Signal_grant(16)(9); --  Grant(8,9)
+Grant(87)  <= Signal_grant(6)(10) or Signal_grant(17)(10); --  Grant(8,10)
+Grant(88)  <= Signal_grant(7)(11) or Signal_grant(18)(11); --  Grant(8,11)
+Grant(89)  <= Signal_grant(9)(1) or Signal_grant(20)(1); --  Grant(9,1)
+Grant(90)  <= Signal_grant(10)(2) or Signal_grant(21)(2); --  Grant(9,2)
+Grant(91)  <= Signal_grant(11)(3) ;                      --  Grant(9,3)
+Grant(92)  <= Signal_grant(1)(4) or Signal_grant(12)(4); --  Grant(9,4)
+Grant(93)  <= Signal_grant(2)(5) or Signal_grant(13)(5); --  Grant(9,5)
+Grant(94)  <= Signal_grant(3)(6) or Signal_grant(14)(6); --  Grant(9,6)
+Grant(95)  <= Signal_grant(4)(7) or Signal_grant(15)(7); --  Grant(9,7)
+Grant(96)  <= Signal_grant(5)(8) or Signal_grant(16)(8); --  Grant(9,8)
+Grant(97)  <= Signal_grant(6)(9) or Signal_grant(17)(9); --  Grant(9,9)
+Grant(98)  <= Signal_grant(7)(10) or Signal_grant(18)(10); --  Grant(9,10)
+Grant(99)  <= Signal_grant(8)(11) or Signal_grant(19)(11); --  Grant(9,11)
+Grant(100)  <= Signal_grant(10)(1) or Signal_grant(21)(1); --  Grant(10,1)
+Grant(101)  <= Signal_grant(11)(2) ;                      --  Grant(10,2)
+Grant(102)  <= Signal_grant(1)(3) or Signal_grant(12)(3); --  Grant(10,3)
+Grant(103)  <= Signal_grant(2)(4) or Signal_grant(13)(4); --  Grant(10,4)
+Grant(104)  <= Signal_grant(3)(5) or Signal_grant(14)(5); --  Grant(10,5)
+Grant(105)  <= Signal_grant(4)(6) or Signal_grant(15)(6); --  Grant(10,6)
+Grant(106)  <= Signal_grant(5)(7) or Signal_grant(16)(7); --  Grant(10,7)
+Grant(107)  <= Signal_grant(6)(8) or Signal_grant(17)(8); --  Grant(10,8)
+Grant(108)  <= Signal_grant(7)(9) or Signal_grant(18)(9); --  Grant(10,9)
+Grant(109)  <= Signal_grant(8)(10) or Signal_grant(19)(10); --  Grant(10,10)
+Grant(110)  <= Signal_grant(9)(11) or Signal_grant(20)(11); --  Grant(10,11)
+Grant(111)  <= Signal_grant(11)(1) ;                      --  Grant(11,1)
+Grant(112)  <= Signal_grant(1)(2) or Signal_grant(12)(2); --  Grant(11,2)
+Grant(113)  <= Signal_grant(2)(3) or Signal_grant(13)(3); --  Grant(11,3)
+Grant(114)  <= Signal_grant(3)(4) or Signal_grant(14)(4); --  Grant(11,4)
+Grant(115)  <= Signal_grant(4)(5) or Signal_grant(15)(5); --  Grant(11,5)
+Grant(116)  <= Signal_grant(5)(6) or Signal_grant(16)(6); --  Grant(11,6)
+Grant(117)  <= Signal_grant(6)(7) or Signal_grant(17)(7); --  Grant(11,7)
+Grant(118)  <= Signal_grant(7)(8) or Signal_grant(18)(8); --  Grant(11,8)
+Grant(119)  <= Signal_grant(8)(9) or Signal_grant(19)(9); --  Grant(11,9)
+Grant(120)  <= Signal_grant(9)(10) or Signal_grant(20)(10); --  Grant(11,10)
+Grant(121)  <= Signal_grant(10)(11) or Signal_grant(21)(11); --  Grant(11,11)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(112), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(102), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(92), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(82), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(72), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(62), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(52), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(42), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+Arbiter_1_10 : Arbiter
+
+PORT MAP (Request => Request(32), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(10),  
+South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); 
+
+Arbiter_1_11 : Arbiter
+
+PORT MAP (Request => Request(22), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(11),  
+South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(1)(1), West => east_2_west(1)(11), P => Signal_priority(20), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+Arbiter_2_10 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10),  
+South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); 
+
+Arbiter_2_11 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11),  
+South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(2)(1), West => east_2_west(2)(11), P => Signal_priority(19), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+Arbiter_3_10 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10),  
+South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); 
+
+Arbiter_3_11 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11),  
+South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(3)(1), West => east_2_west(3)(11), P => Signal_priority(18), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+Arbiter_4_10 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10),  
+South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); 
+
+Arbiter_4_11 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11),  
+South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(4)(1), West => east_2_west(4)(11), P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+Arbiter_5_10 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10),  
+South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); 
+
+Arbiter_5_11 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11),  
+South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(5)(1), West => east_2_west(5)(11), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+Arbiter_6_10 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10),  
+South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); 
+
+Arbiter_6_11 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11),  
+South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(6)(1), West => east_2_west(6)(11), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+Arbiter_7_10 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10),  
+South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); 
+
+Arbiter_7_11 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11),  
+South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(7)(1), West => east_2_west(7)(11), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+Arbiter_8_10 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10),  
+South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); 
+
+Arbiter_8_11 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11),  
+South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(8)(1), West => east_2_west(8)(11), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+Arbiter_9_10 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10),  
+South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); 
+
+Arbiter_9_11 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11),  
+South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(9)(1), West => east_2_west(9)(11), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+Arbiter_10_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10),  
+South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); 
+
+Arbiter_10_11 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11),  
+South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(10)(1), West => east_2_west(10)(11), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+Arbiter_11_10 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10),  
+South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); 
+
+Arbiter_11_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11),  
+South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(11)(1), West => east_2_west(11)(11), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+Arbiter_12_10 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10),  
+South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); 
+
+Arbiter_12_11 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11),  
+South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(12)(1), West => east_2_west(12)(11), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+Arbiter_13_10 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10),  
+South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); 
+
+Arbiter_13_11 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11),  
+South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(13)(1), West => east_2_west(13)(11), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+Arbiter_14_10 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10),  
+South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); 
+
+Arbiter_14_11 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11),  
+South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(14)(1), West => east_2_west(14)(11), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+Arbiter_15_10 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10),  
+South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); 
+
+Arbiter_15_11 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11),  
+South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(15)(1), West => east_2_west(15)(11), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+Arbiter_16_10 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10),  
+South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); 
+
+Arbiter_16_11 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11),  
+South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(16)(1), West => east_2_west(16)(11), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+Arbiter_17_10 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10),  
+South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); 
+
+Arbiter_17_11 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11),  
+South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); 
+
+-------------------------- Diagonale n° 18 
+
+
+Arbiter_18_1 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(17)(1), West => east_2_west(17)(11), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); 
+
+Arbiter_18_2 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); 
+
+Arbiter_18_3 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); 
+
+Arbiter_18_4 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); 
+
+Arbiter_18_5 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); 
+
+Arbiter_18_6 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); 
+
+Arbiter_18_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); 
+
+Arbiter_18_8 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); 
+
+Arbiter_18_9 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); 
+
+Arbiter_18_10 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10),  
+South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); 
+
+Arbiter_18_11 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11),  
+South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); 
+
+-------------------------- Diagonale n° 19 
+
+
+Arbiter_19_1 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(18)(1), West => east_2_west(18)(11), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); 
+
+Arbiter_19_2 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); 
+
+Arbiter_19_3 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); 
+
+Arbiter_19_4 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); 
+
+Arbiter_19_5 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); 
+
+Arbiter_19_6 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); 
+
+Arbiter_19_7 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); 
+
+Arbiter_19_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); 
+
+Arbiter_19_9 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); 
+
+Arbiter_19_10 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10),  
+South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); 
+
+Arbiter_19_11 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11),  
+South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); 
+
+-------------------------- Diagonale n° 20 
+
+
+Arbiter_20_1 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(19)(1), West => east_2_west(19)(11), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); 
+
+Arbiter_20_2 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); 
+
+Arbiter_20_3 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); 
+
+Arbiter_20_4 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); 
+
+Arbiter_20_5 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); 
+
+Arbiter_20_6 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); 
+
+Arbiter_20_7 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); 
+
+Arbiter_20_8 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); 
+
+Arbiter_20_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); 
+
+Arbiter_20_10 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10),  
+South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); 
+
+Arbiter_20_11 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11),  
+South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); 
+
+-------------------------- Diagonale n° 21 
+
+
+Arbiter_21_1 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(20)(1), West => east_2_west(20)(11), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); 
+
+Arbiter_21_2 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); 
+
+Arbiter_21_3 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); 
+
+Arbiter_21_4 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); 
+
+Arbiter_21_5 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); 
+
+Arbiter_21_6 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); 
+
+Arbiter_21_7 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); 
+
+Arbiter_21_8 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); 
+
+Arbiter_21_9 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); 
+
+Arbiter_21_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10),  
+South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); 
+
+Arbiter_21_11 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11),  
+South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "111111111110000000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "111111111110000000000" => Signal_priority <= "011111111111000000000";
+		       when "011111111111000000000" => Signal_priority <= "001111111111100000000";
+		       when "001111111111100000000" => Signal_priority <= "000111111111110000000";
+		       when "000111111111110000000" => Signal_priority <= "000011111111111000000";
+		       when "000011111111111000000" => Signal_priority <= "000001111111111100000";
+		       when "000001111111111100000" => Signal_priority <= "000000111111111110000";
+		       when "000000111111111110000" => Signal_priority <= "000000011111111111000";
+		       when "000000011111111111000" => Signal_priority <= "000000001111111111100";
+		       when "000000001111111111100" => Signal_priority <= "000000000111111111110";
+		       when "000000000111111111110" => Signal_priority <= "000000000011111111111";
+		       when "000000000011111111111" => Signal_priority <= "111111111110000000000";
+		       when others    => Signal_priority <= "111111111110000000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER12_12.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER12_12.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER12_12.VHD	(revision 20)
@@ -0,0 +1,1700 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler12_12 is
+    Port ( Request : in  STD_LOGIC_VECTOR (144 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (12 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (12 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (144 downto 1));
+end Scheduler12_12;
+
+architecture Behavioral of Scheduler12_12 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(23 downto 1) of STD_LOGIC_VECTOR(12 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (23 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(144 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(144 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 4095 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(13)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(14)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(15)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(16)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(17)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(18)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(19)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(20)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) or Signal_grant(21)(9); --  Grant(1,9)
+Grant(10)  <= Signal_grant(10)(10) or Signal_grant(22)(10); --  Grant(1,10)
+Grant(11)  <= Signal_grant(11)(11) or Signal_grant(23)(11); --  Grant(1,11)
+Grant(12)  <= Signal_grant(12)(12) ;                      --  Grant(1,12)
+Grant(13)  <= Signal_grant(2)(1) or Signal_grant(14)(1); --  Grant(2,1)
+Grant(14)  <= Signal_grant(3)(2) or Signal_grant(15)(2); --  Grant(2,2)
+Grant(15)  <= Signal_grant(4)(3) or Signal_grant(16)(3); --  Grant(2,3)
+Grant(16)  <= Signal_grant(5)(4) or Signal_grant(17)(4); --  Grant(2,4)
+Grant(17)  <= Signal_grant(6)(5) or Signal_grant(18)(5); --  Grant(2,5)
+Grant(18)  <= Signal_grant(7)(6) or Signal_grant(19)(6); --  Grant(2,6)
+Grant(19)  <= Signal_grant(8)(7) or Signal_grant(20)(7); --  Grant(2,7)
+Grant(20)  <= Signal_grant(9)(8) or Signal_grant(21)(8); --  Grant(2,8)
+Grant(21)  <= Signal_grant(10)(9) or Signal_grant(22)(9); --  Grant(2,9)
+Grant(22)  <= Signal_grant(11)(10) or Signal_grant(23)(10); --  Grant(2,10)
+Grant(23)  <= Signal_grant(12)(11) ;                      --  Grant(2,11)
+Grant(24)  <= Signal_grant(1)(12) or Signal_grant(13)(12); --  Grant(2,12)
+Grant(25)  <= Signal_grant(3)(1) or Signal_grant(15)(1); --  Grant(3,1)
+Grant(26)  <= Signal_grant(4)(2) or Signal_grant(16)(2); --  Grant(3,2)
+Grant(27)  <= Signal_grant(5)(3) or Signal_grant(17)(3); --  Grant(3,3)
+Grant(28)  <= Signal_grant(6)(4) or Signal_grant(18)(4); --  Grant(3,4)
+Grant(29)  <= Signal_grant(7)(5) or Signal_grant(19)(5); --  Grant(3,5)
+Grant(30)  <= Signal_grant(8)(6) or Signal_grant(20)(6); --  Grant(3,6)
+Grant(31)  <= Signal_grant(9)(7) or Signal_grant(21)(7); --  Grant(3,7)
+Grant(32)  <= Signal_grant(10)(8) or Signal_grant(22)(8); --  Grant(3,8)
+Grant(33)  <= Signal_grant(11)(9) or Signal_grant(23)(9); --  Grant(3,9)
+Grant(34)  <= Signal_grant(12)(10) ;                      --  Grant(3,10)
+Grant(35)  <= Signal_grant(1)(11) or Signal_grant(13)(11); --  Grant(3,11)
+Grant(36)  <= Signal_grant(2)(12) or Signal_grant(14)(12); --  Grant(3,12)
+Grant(37)  <= Signal_grant(4)(1) or Signal_grant(16)(1); --  Grant(4,1)
+Grant(38)  <= Signal_grant(5)(2) or Signal_grant(17)(2); --  Grant(4,2)
+Grant(39)  <= Signal_grant(6)(3) or Signal_grant(18)(3); --  Grant(4,3)
+Grant(40)  <= Signal_grant(7)(4) or Signal_grant(19)(4); --  Grant(4,4)
+Grant(41)  <= Signal_grant(8)(5) or Signal_grant(20)(5); --  Grant(4,5)
+Grant(42)  <= Signal_grant(9)(6) or Signal_grant(21)(6); --  Grant(4,6)
+Grant(43)  <= Signal_grant(10)(7) or Signal_grant(22)(7); --  Grant(4,7)
+Grant(44)  <= Signal_grant(11)(8) or Signal_grant(23)(8); --  Grant(4,8)
+Grant(45)  <= Signal_grant(12)(9) ;                      --  Grant(4,9)
+Grant(46)  <= Signal_grant(1)(10) or Signal_grant(13)(10); --  Grant(4,10)
+Grant(47)  <= Signal_grant(2)(11) or Signal_grant(14)(11); --  Grant(4,11)
+Grant(48)  <= Signal_grant(3)(12) or Signal_grant(15)(12); --  Grant(4,12)
+Grant(49)  <= Signal_grant(5)(1) or Signal_grant(17)(1); --  Grant(5,1)
+Grant(50)  <= Signal_grant(6)(2) or Signal_grant(18)(2); --  Grant(5,2)
+Grant(51)  <= Signal_grant(7)(3) or Signal_grant(19)(3); --  Grant(5,3)
+Grant(52)  <= Signal_grant(8)(4) or Signal_grant(20)(4); --  Grant(5,4)
+Grant(53)  <= Signal_grant(9)(5) or Signal_grant(21)(5); --  Grant(5,5)
+Grant(54)  <= Signal_grant(10)(6) or Signal_grant(22)(6); --  Grant(5,6)
+Grant(55)  <= Signal_grant(11)(7) or Signal_grant(23)(7); --  Grant(5,7)
+Grant(56)  <= Signal_grant(12)(8) ;                      --  Grant(5,8)
+Grant(57)  <= Signal_grant(1)(9) or Signal_grant(13)(9); --  Grant(5,9)
+Grant(58)  <= Signal_grant(2)(10) or Signal_grant(14)(10); --  Grant(5,10)
+Grant(59)  <= Signal_grant(3)(11) or Signal_grant(15)(11); --  Grant(5,11)
+Grant(60)  <= Signal_grant(4)(12) or Signal_grant(16)(12); --  Grant(5,12)
+Grant(61)  <= Signal_grant(6)(1) or Signal_grant(18)(1); --  Grant(6,1)
+Grant(62)  <= Signal_grant(7)(2) or Signal_grant(19)(2); --  Grant(6,2)
+Grant(63)  <= Signal_grant(8)(3) or Signal_grant(20)(3); --  Grant(6,3)
+Grant(64)  <= Signal_grant(9)(4) or Signal_grant(21)(4); --  Grant(6,4)
+Grant(65)  <= Signal_grant(10)(5) or Signal_grant(22)(5); --  Grant(6,5)
+Grant(66)  <= Signal_grant(11)(6) or Signal_grant(23)(6); --  Grant(6,6)
+Grant(67)  <= Signal_grant(12)(7) ;                      --  Grant(6,7)
+Grant(68)  <= Signal_grant(1)(8) or Signal_grant(13)(8); --  Grant(6,8)
+Grant(69)  <= Signal_grant(2)(9) or Signal_grant(14)(9); --  Grant(6,9)
+Grant(70)  <= Signal_grant(3)(10) or Signal_grant(15)(10); --  Grant(6,10)
+Grant(71)  <= Signal_grant(4)(11) or Signal_grant(16)(11); --  Grant(6,11)
+Grant(72)  <= Signal_grant(5)(12) or Signal_grant(17)(12); --  Grant(6,12)
+Grant(73)  <= Signal_grant(7)(1) or Signal_grant(19)(1); --  Grant(7,1)
+Grant(74)  <= Signal_grant(8)(2) or Signal_grant(20)(2); --  Grant(7,2)
+Grant(75)  <= Signal_grant(9)(3) or Signal_grant(21)(3); --  Grant(7,3)
+Grant(76)  <= Signal_grant(10)(4) or Signal_grant(22)(4); --  Grant(7,4)
+Grant(77)  <= Signal_grant(11)(5) or Signal_grant(23)(5); --  Grant(7,5)
+Grant(78)  <= Signal_grant(12)(6) ;                      --  Grant(7,6)
+Grant(79)  <= Signal_grant(1)(7) or Signal_grant(13)(7); --  Grant(7,7)
+Grant(80)  <= Signal_grant(2)(8) or Signal_grant(14)(8); --  Grant(7,8)
+Grant(81)  <= Signal_grant(3)(9) or Signal_grant(15)(9); --  Grant(7,9)
+Grant(82)  <= Signal_grant(4)(10) or Signal_grant(16)(10); --  Grant(7,10)
+Grant(83)  <= Signal_grant(5)(11) or Signal_grant(17)(11); --  Grant(7,11)
+Grant(84)  <= Signal_grant(6)(12) or Signal_grant(18)(12); --  Grant(7,12)
+Grant(85)  <= Signal_grant(8)(1) or Signal_grant(20)(1); --  Grant(8,1)
+Grant(86)  <= Signal_grant(9)(2) or Signal_grant(21)(2); --  Grant(8,2)
+Grant(87)  <= Signal_grant(10)(3) or Signal_grant(22)(3); --  Grant(8,3)
+Grant(88)  <= Signal_grant(11)(4) or Signal_grant(23)(4); --  Grant(8,4)
+Grant(89)  <= Signal_grant(12)(5) ;                      --  Grant(8,5)
+Grant(90)  <= Signal_grant(1)(6) or Signal_grant(13)(6); --  Grant(8,6)
+Grant(91)  <= Signal_grant(2)(7) or Signal_grant(14)(7); --  Grant(8,7)
+Grant(92)  <= Signal_grant(3)(8) or Signal_grant(15)(8); --  Grant(8,8)
+Grant(93)  <= Signal_grant(4)(9) or Signal_grant(16)(9); --  Grant(8,9)
+Grant(94)  <= Signal_grant(5)(10) or Signal_grant(17)(10); --  Grant(8,10)
+Grant(95)  <= Signal_grant(6)(11) or Signal_grant(18)(11); --  Grant(8,11)
+Grant(96)  <= Signal_grant(7)(12) or Signal_grant(19)(12); --  Grant(8,12)
+Grant(97)  <= Signal_grant(9)(1) or Signal_grant(21)(1); --  Grant(9,1)
+Grant(98)  <= Signal_grant(10)(2) or Signal_grant(22)(2); --  Grant(9,2)
+Grant(99)  <= Signal_grant(11)(3) or Signal_grant(23)(3); --  Grant(9,3)
+Grant(100)  <= Signal_grant(12)(4) ;                      --  Grant(9,4)
+Grant(101)  <= Signal_grant(1)(5) or Signal_grant(13)(5); --  Grant(9,5)
+Grant(102)  <= Signal_grant(2)(6) or Signal_grant(14)(6); --  Grant(9,6)
+Grant(103)  <= Signal_grant(3)(7) or Signal_grant(15)(7); --  Grant(9,7)
+Grant(104)  <= Signal_grant(4)(8) or Signal_grant(16)(8); --  Grant(9,8)
+Grant(105)  <= Signal_grant(5)(9) or Signal_grant(17)(9); --  Grant(9,9)
+Grant(106)  <= Signal_grant(6)(10) or Signal_grant(18)(10); --  Grant(9,10)
+Grant(107)  <= Signal_grant(7)(11) or Signal_grant(19)(11); --  Grant(9,11)
+Grant(108)  <= Signal_grant(8)(12) or Signal_grant(20)(12); --  Grant(9,12)
+Grant(109)  <= Signal_grant(10)(1) or Signal_grant(22)(1); --  Grant(10,1)
+Grant(110)  <= Signal_grant(11)(2) or Signal_grant(23)(2); --  Grant(10,2)
+Grant(111)  <= Signal_grant(12)(3) ;                      --  Grant(10,3)
+Grant(112)  <= Signal_grant(1)(4) or Signal_grant(13)(4); --  Grant(10,4)
+Grant(113)  <= Signal_grant(2)(5) or Signal_grant(14)(5); --  Grant(10,5)
+Grant(114)  <= Signal_grant(3)(6) or Signal_grant(15)(6); --  Grant(10,6)
+Grant(115)  <= Signal_grant(4)(7) or Signal_grant(16)(7); --  Grant(10,7)
+Grant(116)  <= Signal_grant(5)(8) or Signal_grant(17)(8); --  Grant(10,8)
+Grant(117)  <= Signal_grant(6)(9) or Signal_grant(18)(9); --  Grant(10,9)
+Grant(118)  <= Signal_grant(7)(10) or Signal_grant(19)(10); --  Grant(10,10)
+Grant(119)  <= Signal_grant(8)(11) or Signal_grant(20)(11); --  Grant(10,11)
+Grant(120)  <= Signal_grant(9)(12) or Signal_grant(21)(12); --  Grant(10,12)
+Grant(121)  <= Signal_grant(11)(1) or Signal_grant(23)(1); --  Grant(11,1)
+Grant(122)  <= Signal_grant(12)(2) ;                      --  Grant(11,2)
+Grant(123)  <= Signal_grant(1)(3) or Signal_grant(13)(3); --  Grant(11,3)
+Grant(124)  <= Signal_grant(2)(4) or Signal_grant(14)(4); --  Grant(11,4)
+Grant(125)  <= Signal_grant(3)(5) or Signal_grant(15)(5); --  Grant(11,5)
+Grant(126)  <= Signal_grant(4)(6) or Signal_grant(16)(6); --  Grant(11,6)
+Grant(127)  <= Signal_grant(5)(7) or Signal_grant(17)(7); --  Grant(11,7)
+Grant(128)  <= Signal_grant(6)(8) or Signal_grant(18)(8); --  Grant(11,8)
+Grant(129)  <= Signal_grant(7)(9) or Signal_grant(19)(9); --  Grant(11,9)
+Grant(130)  <= Signal_grant(8)(10) or Signal_grant(20)(10); --  Grant(11,10)
+Grant(131)  <= Signal_grant(9)(11) or Signal_grant(21)(11); --  Grant(11,11)
+Grant(132)  <= Signal_grant(10)(12) or Signal_grant(22)(12); --  Grant(11,12)
+Grant(133)  <= Signal_grant(12)(1) ;                      --  Grant(12,1)
+Grant(134)  <= Signal_grant(1)(2) or Signal_grant(13)(2); --  Grant(12,2)
+Grant(135)  <= Signal_grant(2)(3) or Signal_grant(14)(3); --  Grant(12,3)
+Grant(136)  <= Signal_grant(3)(4) or Signal_grant(15)(4); --  Grant(12,4)
+Grant(137)  <= Signal_grant(4)(5) or Signal_grant(16)(5); --  Grant(12,5)
+Grant(138)  <= Signal_grant(5)(6) or Signal_grant(17)(6); --  Grant(12,6)
+Grant(139)  <= Signal_grant(6)(7) or Signal_grant(18)(7); --  Grant(12,7)
+Grant(140)  <= Signal_grant(7)(8) or Signal_grant(19)(8); --  Grant(12,8)
+Grant(141)  <= Signal_grant(8)(9) or Signal_grant(20)(9); --  Grant(12,9)
+Grant(142)  <= Signal_grant(9)(10) or Signal_grant(21)(10); --  Grant(12,10)
+Grant(143)  <= Signal_grant(10)(11) or Signal_grant(22)(11); --  Grant(12,11)
+Grant(144)  <= Signal_grant(11)(12) or Signal_grant(23)(12); --  Grant(12,12)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(134), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(123), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(112), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(101), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(90), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(79), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(68), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(57), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+Arbiter_1_10 : Arbiter
+
+PORT MAP (Request => Request(46), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(10),  
+South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); 
+
+Arbiter_1_11 : Arbiter
+
+PORT MAP (Request => Request(35), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(11),  
+South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); 
+
+Arbiter_1_12 : Arbiter
+
+PORT MAP (Request => Request(24), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(12),  
+South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(1)(1), West => east_2_west(1)(12), P => Signal_priority(22), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+Arbiter_2_10 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10),  
+South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); 
+
+Arbiter_2_11 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11),  
+South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); 
+
+Arbiter_2_12 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12),  
+South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(2)(1), West => east_2_west(2)(12), P => Signal_priority(21), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+Arbiter_3_10 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10),  
+South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); 
+
+Arbiter_3_11 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11),  
+South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); 
+
+Arbiter_3_12 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12),  
+South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(3)(1), West => east_2_west(3)(12), P => Signal_priority(20), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+Arbiter_4_10 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10),  
+South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); 
+
+Arbiter_4_11 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11),  
+South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); 
+
+Arbiter_4_12 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12),  
+South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(4)(1), West => east_2_west(4)(12), P => Signal_priority(19), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+Arbiter_5_10 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10),  
+South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); 
+
+Arbiter_5_11 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11),  
+South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); 
+
+Arbiter_5_12 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12),  
+South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(5)(1), West => east_2_west(5)(12), P => Signal_priority(18), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+Arbiter_6_10 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10),  
+South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); 
+
+Arbiter_6_11 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11),  
+South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); 
+
+Arbiter_6_12 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12),  
+South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(6)(1), West => east_2_west(6)(12), P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+Arbiter_7_10 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10),  
+South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); 
+
+Arbiter_7_11 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11),  
+South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); 
+
+Arbiter_7_12 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12),  
+South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(7)(1), West => east_2_west(7)(12), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+Arbiter_8_10 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10),  
+South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); 
+
+Arbiter_8_11 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11),  
+South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); 
+
+Arbiter_8_12 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12),  
+South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(8)(1), West => east_2_west(8)(12), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+Arbiter_9_10 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10),  
+South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); 
+
+Arbiter_9_11 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11),  
+South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); 
+
+Arbiter_9_12 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12),  
+South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(9)(1), West => east_2_west(9)(12), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+Arbiter_10_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10),  
+South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); 
+
+Arbiter_10_11 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11),  
+South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); 
+
+Arbiter_10_12 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12),  
+South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(10)(1), West => east_2_west(10)(12), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+Arbiter_11_10 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10),  
+South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); 
+
+Arbiter_11_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11),  
+South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); 
+
+Arbiter_11_12 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12),  
+South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(11)(1), West => east_2_west(11)(12), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(122), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+Arbiter_12_10 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10),  
+South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); 
+
+Arbiter_12_11 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11),  
+South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); 
+
+Arbiter_12_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12),  
+South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(12)(1), West => east_2_west(12)(12), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+Arbiter_13_10 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10),  
+South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); 
+
+Arbiter_13_11 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11),  
+South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); 
+
+Arbiter_13_12 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12),  
+South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(13)(1), West => east_2_west(13)(12), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+Arbiter_14_10 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10),  
+South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); 
+
+Arbiter_14_11 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11),  
+South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); 
+
+Arbiter_14_12 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12),  
+South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(14)(1), West => east_2_west(14)(12), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+Arbiter_15_10 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10),  
+South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); 
+
+Arbiter_15_11 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11),  
+South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); 
+
+Arbiter_15_12 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12),  
+South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(15)(1), West => east_2_west(15)(12), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+Arbiter_16_10 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10),  
+South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); 
+
+Arbiter_16_11 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11),  
+South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); 
+
+Arbiter_16_12 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12),  
+South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(16)(1), West => east_2_west(16)(12), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+Arbiter_17_10 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10),  
+South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); 
+
+Arbiter_17_11 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11),  
+South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); 
+
+Arbiter_17_12 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12),  
+South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); 
+
+-------------------------- Diagonale n° 18 
+
+
+Arbiter_18_1 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(17)(1), West => east_2_west(17)(12), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); 
+
+Arbiter_18_2 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); 
+
+Arbiter_18_3 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); 
+
+Arbiter_18_4 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); 
+
+Arbiter_18_5 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); 
+
+Arbiter_18_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); 
+
+Arbiter_18_7 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); 
+
+Arbiter_18_8 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); 
+
+Arbiter_18_9 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); 
+
+Arbiter_18_10 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10),  
+South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); 
+
+Arbiter_18_11 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11),  
+South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); 
+
+Arbiter_18_12 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12),  
+South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); 
+
+-------------------------- Diagonale n° 19 
+
+
+Arbiter_19_1 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(18)(1), West => east_2_west(18)(12), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); 
+
+Arbiter_19_2 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); 
+
+Arbiter_19_3 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); 
+
+Arbiter_19_4 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); 
+
+Arbiter_19_5 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); 
+
+Arbiter_19_6 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); 
+
+Arbiter_19_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); 
+
+Arbiter_19_8 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); 
+
+Arbiter_19_9 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); 
+
+Arbiter_19_10 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10),  
+South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); 
+
+Arbiter_19_11 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11),  
+South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); 
+
+Arbiter_19_12 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12),  
+South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); 
+
+-------------------------- Diagonale n° 20 
+
+
+Arbiter_20_1 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(19)(1), West => east_2_west(19)(12), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); 
+
+Arbiter_20_2 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); 
+
+Arbiter_20_3 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); 
+
+Arbiter_20_4 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); 
+
+Arbiter_20_5 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); 
+
+Arbiter_20_6 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); 
+
+Arbiter_20_7 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); 
+
+Arbiter_20_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); 
+
+Arbiter_20_9 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); 
+
+Arbiter_20_10 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10),  
+South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); 
+
+Arbiter_20_11 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11),  
+South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); 
+
+Arbiter_20_12 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12),  
+South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); 
+
+-------------------------- Diagonale n° 21 
+
+
+Arbiter_21_1 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(20)(1), West => east_2_west(20)(12), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); 
+
+Arbiter_21_2 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); 
+
+Arbiter_21_3 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); 
+
+Arbiter_21_4 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); 
+
+Arbiter_21_5 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); 
+
+Arbiter_21_6 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); 
+
+Arbiter_21_7 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); 
+
+Arbiter_21_8 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); 
+
+Arbiter_21_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); 
+
+Arbiter_21_10 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10),  
+South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); 
+
+Arbiter_21_11 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11),  
+South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); 
+
+Arbiter_21_12 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12),  
+South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); 
+
+-------------------------- Diagonale n° 22 
+
+
+Arbiter_22_1 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(21)(1), West => east_2_west(21)(12), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); 
+
+Arbiter_22_2 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); 
+
+Arbiter_22_3 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); 
+
+Arbiter_22_4 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); 
+
+Arbiter_22_5 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); 
+
+Arbiter_22_6 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); 
+
+Arbiter_22_7 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); 
+
+Arbiter_22_8 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); 
+
+Arbiter_22_9 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); 
+
+Arbiter_22_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10),  
+South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); 
+
+Arbiter_22_11 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11),  
+South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); 
+
+Arbiter_22_12 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12),  
+South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); 
+
+-------------------------- Diagonale n° 23 
+
+
+Arbiter_23_1 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(22)(1), West => east_2_west(22)(12), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); 
+
+Arbiter_23_2 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); 
+
+Arbiter_23_3 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); 
+
+Arbiter_23_4 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); 
+
+Arbiter_23_5 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); 
+
+Arbiter_23_6 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); 
+
+Arbiter_23_7 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); 
+
+Arbiter_23_8 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); 
+
+Arbiter_23_9 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); 
+
+Arbiter_23_10 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10),  
+South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); 
+
+Arbiter_23_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11),  
+South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); 
+
+Arbiter_23_12 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12),  
+South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "11111111111100000000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "11111111111100000000000" => Signal_priority <= "01111111111110000000000";
+		       when "01111111111110000000000" => Signal_priority <= "00111111111111000000000";
+		       when "00111111111111000000000" => Signal_priority <= "00011111111111100000000";
+		       when "00011111111111100000000" => Signal_priority <= "00001111111111110000000";
+		       when "00001111111111110000000" => Signal_priority <= "00000111111111111000000";
+		       when "00000111111111111000000" => Signal_priority <= "00000011111111111100000";
+		       when "00000011111111111100000" => Signal_priority <= "00000001111111111110000";
+		       when "00000001111111111110000" => Signal_priority <= "00000000111111111111000";
+		       when "00000000111111111111000" => Signal_priority <= "00000000011111111111100";
+		       when "00000000011111111111100" => Signal_priority <= "00000000001111111111110";
+		       when "00000000001111111111110" => Signal_priority <= "00000000000111111111111";
+		       when "00000000000111111111111" => Signal_priority <= "11111111111100000000000";
+		       when others    => Signal_priority <= "11111111111100000000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER13_13.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER13_13.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER13_13.VHD	(revision 20)
@@ -0,0 +1,1977 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler13_13 is
+    Port ( Request : in  STD_LOGIC_VECTOR (169 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (13 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (13 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (169 downto 1));
+end Scheduler13_13;
+
+architecture Behavioral of Scheduler13_13 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(25 downto 1) of STD_LOGIC_VECTOR(13 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (25 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(169 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(169 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 8191 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(14)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(15)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(16)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(17)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(18)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(19)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(20)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(21)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) or Signal_grant(22)(9); --  Grant(1,9)
+Grant(10)  <= Signal_grant(10)(10) or Signal_grant(23)(10); --  Grant(1,10)
+Grant(11)  <= Signal_grant(11)(11) or Signal_grant(24)(11); --  Grant(1,11)
+Grant(12)  <= Signal_grant(12)(12) or Signal_grant(25)(12); --  Grant(1,12)
+Grant(13)  <= Signal_grant(13)(13) ;                      --  Grant(1,13)
+Grant(14)  <= Signal_grant(2)(1) or Signal_grant(15)(1); --  Grant(2,1)
+Grant(15)  <= Signal_grant(3)(2) or Signal_grant(16)(2); --  Grant(2,2)
+Grant(16)  <= Signal_grant(4)(3) or Signal_grant(17)(3); --  Grant(2,3)
+Grant(17)  <= Signal_grant(5)(4) or Signal_grant(18)(4); --  Grant(2,4)
+Grant(18)  <= Signal_grant(6)(5) or Signal_grant(19)(5); --  Grant(2,5)
+Grant(19)  <= Signal_grant(7)(6) or Signal_grant(20)(6); --  Grant(2,6)
+Grant(20)  <= Signal_grant(8)(7) or Signal_grant(21)(7); --  Grant(2,7)
+Grant(21)  <= Signal_grant(9)(8) or Signal_grant(22)(8); --  Grant(2,8)
+Grant(22)  <= Signal_grant(10)(9) or Signal_grant(23)(9); --  Grant(2,9)
+Grant(23)  <= Signal_grant(11)(10) or Signal_grant(24)(10); --  Grant(2,10)
+Grant(24)  <= Signal_grant(12)(11) or Signal_grant(25)(11); --  Grant(2,11)
+Grant(25)  <= Signal_grant(13)(12) ;                      --  Grant(2,12)
+Grant(26)  <= Signal_grant(1)(13) or Signal_grant(14)(13); --  Grant(2,13)
+Grant(27)  <= Signal_grant(3)(1) or Signal_grant(16)(1); --  Grant(3,1)
+Grant(28)  <= Signal_grant(4)(2) or Signal_grant(17)(2); --  Grant(3,2)
+Grant(29)  <= Signal_grant(5)(3) or Signal_grant(18)(3); --  Grant(3,3)
+Grant(30)  <= Signal_grant(6)(4) or Signal_grant(19)(4); --  Grant(3,4)
+Grant(31)  <= Signal_grant(7)(5) or Signal_grant(20)(5); --  Grant(3,5)
+Grant(32)  <= Signal_grant(8)(6) or Signal_grant(21)(6); --  Grant(3,6)
+Grant(33)  <= Signal_grant(9)(7) or Signal_grant(22)(7); --  Grant(3,7)
+Grant(34)  <= Signal_grant(10)(8) or Signal_grant(23)(8); --  Grant(3,8)
+Grant(35)  <= Signal_grant(11)(9) or Signal_grant(24)(9); --  Grant(3,9)
+Grant(36)  <= Signal_grant(12)(10) or Signal_grant(25)(10); --  Grant(3,10)
+Grant(37)  <= Signal_grant(13)(11) ;                      --  Grant(3,11)
+Grant(38)  <= Signal_grant(1)(12) or Signal_grant(14)(12); --  Grant(3,12)
+Grant(39)  <= Signal_grant(2)(13) or Signal_grant(15)(13); --  Grant(3,13)
+Grant(40)  <= Signal_grant(4)(1) or Signal_grant(17)(1); --  Grant(4,1)
+Grant(41)  <= Signal_grant(5)(2) or Signal_grant(18)(2); --  Grant(4,2)
+Grant(42)  <= Signal_grant(6)(3) or Signal_grant(19)(3); --  Grant(4,3)
+Grant(43)  <= Signal_grant(7)(4) or Signal_grant(20)(4); --  Grant(4,4)
+Grant(44)  <= Signal_grant(8)(5) or Signal_grant(21)(5); --  Grant(4,5)
+Grant(45)  <= Signal_grant(9)(6) or Signal_grant(22)(6); --  Grant(4,6)
+Grant(46)  <= Signal_grant(10)(7) or Signal_grant(23)(7); --  Grant(4,7)
+Grant(47)  <= Signal_grant(11)(8) or Signal_grant(24)(8); --  Grant(4,8)
+Grant(48)  <= Signal_grant(12)(9) or Signal_grant(25)(9); --  Grant(4,9)
+Grant(49)  <= Signal_grant(13)(10) ;                      --  Grant(4,10)
+Grant(50)  <= Signal_grant(1)(11) or Signal_grant(14)(11); --  Grant(4,11)
+Grant(51)  <= Signal_grant(2)(12) or Signal_grant(15)(12); --  Grant(4,12)
+Grant(52)  <= Signal_grant(3)(13) or Signal_grant(16)(13); --  Grant(4,13)
+Grant(53)  <= Signal_grant(5)(1) or Signal_grant(18)(1); --  Grant(5,1)
+Grant(54)  <= Signal_grant(6)(2) or Signal_grant(19)(2); --  Grant(5,2)
+Grant(55)  <= Signal_grant(7)(3) or Signal_grant(20)(3); --  Grant(5,3)
+Grant(56)  <= Signal_grant(8)(4) or Signal_grant(21)(4); --  Grant(5,4)
+Grant(57)  <= Signal_grant(9)(5) or Signal_grant(22)(5); --  Grant(5,5)
+Grant(58)  <= Signal_grant(10)(6) or Signal_grant(23)(6); --  Grant(5,6)
+Grant(59)  <= Signal_grant(11)(7) or Signal_grant(24)(7); --  Grant(5,7)
+Grant(60)  <= Signal_grant(12)(8) or Signal_grant(25)(8); --  Grant(5,8)
+Grant(61)  <= Signal_grant(13)(9) ;                      --  Grant(5,9)
+Grant(62)  <= Signal_grant(1)(10) or Signal_grant(14)(10); --  Grant(5,10)
+Grant(63)  <= Signal_grant(2)(11) or Signal_grant(15)(11); --  Grant(5,11)
+Grant(64)  <= Signal_grant(3)(12) or Signal_grant(16)(12); --  Grant(5,12)
+Grant(65)  <= Signal_grant(4)(13) or Signal_grant(17)(13); --  Grant(5,13)
+Grant(66)  <= Signal_grant(6)(1) or Signal_grant(19)(1); --  Grant(6,1)
+Grant(67)  <= Signal_grant(7)(2) or Signal_grant(20)(2); --  Grant(6,2)
+Grant(68)  <= Signal_grant(8)(3) or Signal_grant(21)(3); --  Grant(6,3)
+Grant(69)  <= Signal_grant(9)(4) or Signal_grant(22)(4); --  Grant(6,4)
+Grant(70)  <= Signal_grant(10)(5) or Signal_grant(23)(5); --  Grant(6,5)
+Grant(71)  <= Signal_grant(11)(6) or Signal_grant(24)(6); --  Grant(6,6)
+Grant(72)  <= Signal_grant(12)(7) or Signal_grant(25)(7); --  Grant(6,7)
+Grant(73)  <= Signal_grant(13)(8) ;                      --  Grant(6,8)
+Grant(74)  <= Signal_grant(1)(9) or Signal_grant(14)(9); --  Grant(6,9)
+Grant(75)  <= Signal_grant(2)(10) or Signal_grant(15)(10); --  Grant(6,10)
+Grant(76)  <= Signal_grant(3)(11) or Signal_grant(16)(11); --  Grant(6,11)
+Grant(77)  <= Signal_grant(4)(12) or Signal_grant(17)(12); --  Grant(6,12)
+Grant(78)  <= Signal_grant(5)(13) or Signal_grant(18)(13); --  Grant(6,13)
+Grant(79)  <= Signal_grant(7)(1) or Signal_grant(20)(1); --  Grant(7,1)
+Grant(80)  <= Signal_grant(8)(2) or Signal_grant(21)(2); --  Grant(7,2)
+Grant(81)  <= Signal_grant(9)(3) or Signal_grant(22)(3); --  Grant(7,3)
+Grant(82)  <= Signal_grant(10)(4) or Signal_grant(23)(4); --  Grant(7,4)
+Grant(83)  <= Signal_grant(11)(5) or Signal_grant(24)(5); --  Grant(7,5)
+Grant(84)  <= Signal_grant(12)(6) or Signal_grant(25)(6); --  Grant(7,6)
+Grant(85)  <= Signal_grant(13)(7) ;                      --  Grant(7,7)
+Grant(86)  <= Signal_grant(1)(8) or Signal_grant(14)(8); --  Grant(7,8)
+Grant(87)  <= Signal_grant(2)(9) or Signal_grant(15)(9); --  Grant(7,9)
+Grant(88)  <= Signal_grant(3)(10) or Signal_grant(16)(10); --  Grant(7,10)
+Grant(89)  <= Signal_grant(4)(11) or Signal_grant(17)(11); --  Grant(7,11)
+Grant(90)  <= Signal_grant(5)(12) or Signal_grant(18)(12); --  Grant(7,12)
+Grant(91)  <= Signal_grant(6)(13) or Signal_grant(19)(13); --  Grant(7,13)
+Grant(92)  <= Signal_grant(8)(1) or Signal_grant(21)(1); --  Grant(8,1)
+Grant(93)  <= Signal_grant(9)(2) or Signal_grant(22)(2); --  Grant(8,2)
+Grant(94)  <= Signal_grant(10)(3) or Signal_grant(23)(3); --  Grant(8,3)
+Grant(95)  <= Signal_grant(11)(4) or Signal_grant(24)(4); --  Grant(8,4)
+Grant(96)  <= Signal_grant(12)(5) or Signal_grant(25)(5); --  Grant(8,5)
+Grant(97)  <= Signal_grant(13)(6) ;                      --  Grant(8,6)
+Grant(98)  <= Signal_grant(1)(7) or Signal_grant(14)(7); --  Grant(8,7)
+Grant(99)  <= Signal_grant(2)(8) or Signal_grant(15)(8); --  Grant(8,8)
+Grant(100)  <= Signal_grant(3)(9) or Signal_grant(16)(9); --  Grant(8,9)
+Grant(101)  <= Signal_grant(4)(10) or Signal_grant(17)(10); --  Grant(8,10)
+Grant(102)  <= Signal_grant(5)(11) or Signal_grant(18)(11); --  Grant(8,11)
+Grant(103)  <= Signal_grant(6)(12) or Signal_grant(19)(12); --  Grant(8,12)
+Grant(104)  <= Signal_grant(7)(13) or Signal_grant(20)(13); --  Grant(8,13)
+Grant(105)  <= Signal_grant(9)(1) or Signal_grant(22)(1); --  Grant(9,1)
+Grant(106)  <= Signal_grant(10)(2) or Signal_grant(23)(2); --  Grant(9,2)
+Grant(107)  <= Signal_grant(11)(3) or Signal_grant(24)(3); --  Grant(9,3)
+Grant(108)  <= Signal_grant(12)(4) or Signal_grant(25)(4); --  Grant(9,4)
+Grant(109)  <= Signal_grant(13)(5) ;                      --  Grant(9,5)
+Grant(110)  <= Signal_grant(1)(6) or Signal_grant(14)(6); --  Grant(9,6)
+Grant(111)  <= Signal_grant(2)(7) or Signal_grant(15)(7); --  Grant(9,7)
+Grant(112)  <= Signal_grant(3)(8) or Signal_grant(16)(8); --  Grant(9,8)
+Grant(113)  <= Signal_grant(4)(9) or Signal_grant(17)(9); --  Grant(9,9)
+Grant(114)  <= Signal_grant(5)(10) or Signal_grant(18)(10); --  Grant(9,10)
+Grant(115)  <= Signal_grant(6)(11) or Signal_grant(19)(11); --  Grant(9,11)
+Grant(116)  <= Signal_grant(7)(12) or Signal_grant(20)(12); --  Grant(9,12)
+Grant(117)  <= Signal_grant(8)(13) or Signal_grant(21)(13); --  Grant(9,13)
+Grant(118)  <= Signal_grant(10)(1) or Signal_grant(23)(1); --  Grant(10,1)
+Grant(119)  <= Signal_grant(11)(2) or Signal_grant(24)(2); --  Grant(10,2)
+Grant(120)  <= Signal_grant(12)(3) or Signal_grant(25)(3); --  Grant(10,3)
+Grant(121)  <= Signal_grant(13)(4) ;                      --  Grant(10,4)
+Grant(122)  <= Signal_grant(1)(5) or Signal_grant(14)(5); --  Grant(10,5)
+Grant(123)  <= Signal_grant(2)(6) or Signal_grant(15)(6); --  Grant(10,6)
+Grant(124)  <= Signal_grant(3)(7) or Signal_grant(16)(7); --  Grant(10,7)
+Grant(125)  <= Signal_grant(4)(8) or Signal_grant(17)(8); --  Grant(10,8)
+Grant(126)  <= Signal_grant(5)(9) or Signal_grant(18)(9); --  Grant(10,9)
+Grant(127)  <= Signal_grant(6)(10) or Signal_grant(19)(10); --  Grant(10,10)
+Grant(128)  <= Signal_grant(7)(11) or Signal_grant(20)(11); --  Grant(10,11)
+Grant(129)  <= Signal_grant(8)(12) or Signal_grant(21)(12); --  Grant(10,12)
+Grant(130)  <= Signal_grant(9)(13) or Signal_grant(22)(13); --  Grant(10,13)
+Grant(131)  <= Signal_grant(11)(1) or Signal_grant(24)(1); --  Grant(11,1)
+Grant(132)  <= Signal_grant(12)(2) or Signal_grant(25)(2); --  Grant(11,2)
+Grant(133)  <= Signal_grant(13)(3) ;                      --  Grant(11,3)
+Grant(134)  <= Signal_grant(1)(4) or Signal_grant(14)(4); --  Grant(11,4)
+Grant(135)  <= Signal_grant(2)(5) or Signal_grant(15)(5); --  Grant(11,5)
+Grant(136)  <= Signal_grant(3)(6) or Signal_grant(16)(6); --  Grant(11,6)
+Grant(137)  <= Signal_grant(4)(7) or Signal_grant(17)(7); --  Grant(11,7)
+Grant(138)  <= Signal_grant(5)(8) or Signal_grant(18)(8); --  Grant(11,8)
+Grant(139)  <= Signal_grant(6)(9) or Signal_grant(19)(9); --  Grant(11,9)
+Grant(140)  <= Signal_grant(7)(10) or Signal_grant(20)(10); --  Grant(11,10)
+Grant(141)  <= Signal_grant(8)(11) or Signal_grant(21)(11); --  Grant(11,11)
+Grant(142)  <= Signal_grant(9)(12) or Signal_grant(22)(12); --  Grant(11,12)
+Grant(143)  <= Signal_grant(10)(13) or Signal_grant(23)(13); --  Grant(11,13)
+Grant(144)  <= Signal_grant(12)(1) or Signal_grant(25)(1); --  Grant(12,1)
+Grant(145)  <= Signal_grant(13)(2) ;                      --  Grant(12,2)
+Grant(146)  <= Signal_grant(1)(3) or Signal_grant(14)(3); --  Grant(12,3)
+Grant(147)  <= Signal_grant(2)(4) or Signal_grant(15)(4); --  Grant(12,4)
+Grant(148)  <= Signal_grant(3)(5) or Signal_grant(16)(5); --  Grant(12,5)
+Grant(149)  <= Signal_grant(4)(6) or Signal_grant(17)(6); --  Grant(12,6)
+Grant(150)  <= Signal_grant(5)(7) or Signal_grant(18)(7); --  Grant(12,7)
+Grant(151)  <= Signal_grant(6)(8) or Signal_grant(19)(8); --  Grant(12,8)
+Grant(152)  <= Signal_grant(7)(9) or Signal_grant(20)(9); --  Grant(12,9)
+Grant(153)  <= Signal_grant(8)(10) or Signal_grant(21)(10); --  Grant(12,10)
+Grant(154)  <= Signal_grant(9)(11) or Signal_grant(22)(11); --  Grant(12,11)
+Grant(155)  <= Signal_grant(10)(12) or Signal_grant(23)(12); --  Grant(12,12)
+Grant(156)  <= Signal_grant(11)(13) or Signal_grant(24)(13); --  Grant(12,13)
+Grant(157)  <= Signal_grant(13)(1) ;                      --  Grant(13,1)
+Grant(158)  <= Signal_grant(1)(2) or Signal_grant(14)(2); --  Grant(13,2)
+Grant(159)  <= Signal_grant(2)(3) or Signal_grant(15)(3); --  Grant(13,3)
+Grant(160)  <= Signal_grant(3)(4) or Signal_grant(16)(4); --  Grant(13,4)
+Grant(161)  <= Signal_grant(4)(5) or Signal_grant(17)(5); --  Grant(13,5)
+Grant(162)  <= Signal_grant(5)(6) or Signal_grant(18)(6); --  Grant(13,6)
+Grant(163)  <= Signal_grant(6)(7) or Signal_grant(19)(7); --  Grant(13,7)
+Grant(164)  <= Signal_grant(7)(8) or Signal_grant(20)(8); --  Grant(13,8)
+Grant(165)  <= Signal_grant(8)(9) or Signal_grant(21)(9); --  Grant(13,9)
+Grant(166)  <= Signal_grant(9)(10) or Signal_grant(22)(10); --  Grant(13,10)
+Grant(167)  <= Signal_grant(10)(11) or Signal_grant(23)(11); --  Grant(13,11)
+Grant(168)  <= Signal_grant(11)(12) or Signal_grant(24)(12); --  Grant(13,12)
+Grant(169)  <= Signal_grant(12)(13) or Signal_grant(25)(13); --  Grant(13,13)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(158), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(146), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(134), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(122), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(110), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(98), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(86), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(74), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+Arbiter_1_10 : Arbiter
+
+PORT MAP (Request => Request(62), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(10),  
+South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); 
+
+Arbiter_1_11 : Arbiter
+
+PORT MAP (Request => Request(50), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(11),  
+South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); 
+
+Arbiter_1_12 : Arbiter
+
+PORT MAP (Request => Request(38), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(12),  
+South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); 
+
+Arbiter_1_13 : Arbiter
+
+PORT MAP (Request => Request(26), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(13),  
+South => south_2_north(1)(13), East => east_2_west(1)(13) , Grant => Signal_grant(1)(13)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(1)(1), West => east_2_west(1)(13), P => Signal_priority(24), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(24), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(24), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(24), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(24), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(24), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(24), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(24), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(24), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+Arbiter_2_10 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(24), Fifo_full => Fifo_full(10),  
+South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); 
+
+Arbiter_2_11 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(24), Fifo_full => Fifo_full(11),  
+South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); 
+
+Arbiter_2_12 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(24), Fifo_full => Fifo_full(12),  
+South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); 
+
+Arbiter_2_13 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(1)(13), West => east_2_west(1)(12), P => Signal_priority(24), Fifo_full => Fifo_full(13),  
+South => south_2_north(2)(13), East => east_2_west(2)(13) , Grant => Signal_grant(2)(13)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(2)(1), West => east_2_west(2)(13), P => Signal_priority(23), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(23), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(23), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(23), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(23), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(23), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(23), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(23), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(23), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+Arbiter_3_10 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(23), Fifo_full => Fifo_full(10),  
+South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); 
+
+Arbiter_3_11 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(23), Fifo_full => Fifo_full(11),  
+South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); 
+
+Arbiter_3_12 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(23), Fifo_full => Fifo_full(12),  
+South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); 
+
+Arbiter_3_13 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(2)(13), West => east_2_west(2)(12), P => Signal_priority(23), Fifo_full => Fifo_full(13),  
+South => south_2_north(3)(13), East => east_2_west(3)(13) , Grant => Signal_grant(3)(13)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(3)(1), West => east_2_west(3)(13), P => Signal_priority(22), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+Arbiter_4_10 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10),  
+South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); 
+
+Arbiter_4_11 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11),  
+South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); 
+
+Arbiter_4_12 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12),  
+South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); 
+
+Arbiter_4_13 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(3)(13), West => east_2_west(3)(12), P => Signal_priority(22), Fifo_full => Fifo_full(13),  
+South => south_2_north(4)(13), East => east_2_west(4)(13) , Grant => Signal_grant(4)(13)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(4)(1), West => east_2_west(4)(13), P => Signal_priority(21), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+Arbiter_5_10 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10),  
+South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); 
+
+Arbiter_5_11 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11),  
+South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); 
+
+Arbiter_5_12 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12),  
+South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); 
+
+Arbiter_5_13 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(4)(13), West => east_2_west(4)(12), P => Signal_priority(21), Fifo_full => Fifo_full(13),  
+South => south_2_north(5)(13), East => east_2_west(5)(13) , Grant => Signal_grant(5)(13)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(5)(1), West => east_2_west(5)(13), P => Signal_priority(20), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(151), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+Arbiter_6_10 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10),  
+South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); 
+
+Arbiter_6_11 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11),  
+South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); 
+
+Arbiter_6_12 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12),  
+South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); 
+
+Arbiter_6_13 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(5)(13), West => east_2_west(5)(12), P => Signal_priority(20), Fifo_full => Fifo_full(13),  
+South => south_2_north(6)(13), East => east_2_west(6)(13) , Grant => Signal_grant(6)(13)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(6)(1), West => east_2_west(6)(13), P => Signal_priority(19), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(152), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+Arbiter_7_10 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10),  
+South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); 
+
+Arbiter_7_11 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11),  
+South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); 
+
+Arbiter_7_12 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12),  
+South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); 
+
+Arbiter_7_13 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(6)(13), West => east_2_west(6)(12), P => Signal_priority(19), Fifo_full => Fifo_full(13),  
+South => south_2_north(7)(13), East => east_2_west(7)(13) , Grant => Signal_grant(7)(13)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(7)(1), West => east_2_west(7)(13), P => Signal_priority(18), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+Arbiter_8_10 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10),  
+South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); 
+
+Arbiter_8_11 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11),  
+South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); 
+
+Arbiter_8_12 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12),  
+South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); 
+
+Arbiter_8_13 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(7)(13), West => east_2_west(7)(12), P => Signal_priority(18), Fifo_full => Fifo_full(13),  
+South => south_2_north(8)(13), East => east_2_west(8)(13) , Grant => Signal_grant(8)(13)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(8)(1), West => east_2_west(8)(13), P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+Arbiter_9_10 : Arbiter
+
+PORT MAP (Request => Request(166), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10),  
+South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); 
+
+Arbiter_9_11 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11),  
+South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); 
+
+Arbiter_9_12 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12),  
+South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); 
+
+Arbiter_9_13 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(8)(13), West => east_2_west(8)(12), P => Signal_priority(17), Fifo_full => Fifo_full(13),  
+South => south_2_north(9)(13), East => east_2_west(9)(13) , Grant => Signal_grant(9)(13)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(9)(1), West => east_2_west(9)(13), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+Arbiter_10_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10),  
+South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); 
+
+Arbiter_10_11 : Arbiter
+
+PORT MAP (Request => Request(167), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11),  
+South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); 
+
+Arbiter_10_12 : Arbiter
+
+PORT MAP (Request => Request(155), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12),  
+South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); 
+
+Arbiter_10_13 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(9)(13), West => east_2_west(9)(12), P => Signal_priority(16), Fifo_full => Fifo_full(13),  
+South => south_2_north(10)(13), East => east_2_west(10)(13) , Grant => Signal_grant(10)(13)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(10)(1), West => east_2_west(10)(13), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+Arbiter_11_10 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10),  
+South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); 
+
+Arbiter_11_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11),  
+South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); 
+
+Arbiter_11_12 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12),  
+South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); 
+
+Arbiter_11_13 : Arbiter
+
+PORT MAP (Request => Request(156), North => south_2_north(10)(13), West => east_2_west(10)(12), P => Signal_priority(15), Fifo_full => Fifo_full(13),  
+South => south_2_north(11)(13), East => east_2_west(11)(13) , Grant => Signal_grant(11)(13)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(11)(1), West => east_2_west(11)(13), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+Arbiter_12_10 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10),  
+South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); 
+
+Arbiter_12_11 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11),  
+South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); 
+
+Arbiter_12_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12),  
+South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); 
+
+Arbiter_12_13 : Arbiter
+
+PORT MAP (Request => Request(169), North => south_2_north(11)(13), West => east_2_west(11)(12), P => Signal_priority(14), Fifo_full => Fifo_full(13),  
+South => south_2_north(12)(13), East => east_2_west(12)(13) , Grant => Signal_grant(12)(13)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(157), North => south_2_north(12)(1), West => east_2_west(12)(13), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(145), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+Arbiter_13_10 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10),  
+South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); 
+
+Arbiter_13_11 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11),  
+South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); 
+
+Arbiter_13_12 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12),  
+South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); 
+
+Arbiter_13_13 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(12)(13), West => east_2_west(12)(12), P => Signal_priority(13), Fifo_full => Fifo_full(13),  
+South => south_2_north(13)(13), East => east_2_west(13)(13) , Grant => Signal_grant(13)(13)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(13)(1), West => east_2_west(13)(13), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(158), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(146), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(122), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+Arbiter_14_10 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10),  
+South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); 
+
+Arbiter_14_11 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11),  
+South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); 
+
+Arbiter_14_12 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12),  
+South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); 
+
+Arbiter_14_13 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(13)(13), West => east_2_west(13)(12), P => Signal_priority(12), Fifo_full => Fifo_full(13),  
+South => south_2_north(14)(13), East => east_2_west(14)(13) , Grant => Signal_grant(14)(13)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(14)(1), West => east_2_west(14)(13), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+Arbiter_15_10 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10),  
+South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); 
+
+Arbiter_15_11 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11),  
+South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); 
+
+Arbiter_15_12 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12),  
+South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); 
+
+Arbiter_15_13 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(14)(13), West => east_2_west(14)(12), P => Signal_priority(11), Fifo_full => Fifo_full(13),  
+South => south_2_north(15)(13), East => east_2_west(15)(13) , Grant => Signal_grant(15)(13)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(15)(1), West => east_2_west(15)(13), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+Arbiter_16_10 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10),  
+South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); 
+
+Arbiter_16_11 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11),  
+South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); 
+
+Arbiter_16_12 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12),  
+South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); 
+
+Arbiter_16_13 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(15)(13), West => east_2_west(15)(12), P => Signal_priority(10), Fifo_full => Fifo_full(13),  
+South => south_2_north(16)(13), East => east_2_west(16)(13) , Grant => Signal_grant(16)(13)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(16)(1), West => east_2_west(16)(13), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+Arbiter_17_10 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10),  
+South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); 
+
+Arbiter_17_11 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11),  
+South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); 
+
+Arbiter_17_12 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12),  
+South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); 
+
+Arbiter_17_13 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(16)(13), West => east_2_west(16)(12), P => Signal_priority(9), Fifo_full => Fifo_full(13),  
+South => south_2_north(17)(13), East => east_2_west(17)(13) , Grant => Signal_grant(17)(13)); 
+
+-------------------------- Diagonale n° 18 
+
+
+Arbiter_18_1 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(17)(1), West => east_2_west(17)(13), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); 
+
+Arbiter_18_2 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); 
+
+Arbiter_18_3 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); 
+
+Arbiter_18_4 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); 
+
+Arbiter_18_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); 
+
+Arbiter_18_6 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); 
+
+Arbiter_18_7 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); 
+
+Arbiter_18_8 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); 
+
+Arbiter_18_9 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); 
+
+Arbiter_18_10 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10),  
+South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); 
+
+Arbiter_18_11 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11),  
+South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); 
+
+Arbiter_18_12 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12),  
+South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); 
+
+Arbiter_18_13 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(17)(13), West => east_2_west(17)(12), P => Signal_priority(8), Fifo_full => Fifo_full(13),  
+South => south_2_north(18)(13), East => east_2_west(18)(13) , Grant => Signal_grant(18)(13)); 
+
+-------------------------- Diagonale n° 19 
+
+
+Arbiter_19_1 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(18)(1), West => east_2_west(18)(13), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); 
+
+Arbiter_19_2 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); 
+
+Arbiter_19_3 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); 
+
+Arbiter_19_4 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); 
+
+Arbiter_19_5 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); 
+
+Arbiter_19_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); 
+
+Arbiter_19_7 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); 
+
+Arbiter_19_8 : Arbiter
+
+PORT MAP (Request => Request(151), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); 
+
+Arbiter_19_9 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); 
+
+Arbiter_19_10 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10),  
+South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); 
+
+Arbiter_19_11 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11),  
+South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); 
+
+Arbiter_19_12 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12),  
+South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); 
+
+Arbiter_19_13 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(18)(13), West => east_2_west(18)(12), P => Signal_priority(7), Fifo_full => Fifo_full(13),  
+South => south_2_north(19)(13), East => east_2_west(19)(13) , Grant => Signal_grant(19)(13)); 
+
+-------------------------- Diagonale n° 20 
+
+
+Arbiter_20_1 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(19)(1), West => east_2_west(19)(13), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); 
+
+Arbiter_20_2 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); 
+
+Arbiter_20_3 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); 
+
+Arbiter_20_4 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); 
+
+Arbiter_20_5 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); 
+
+Arbiter_20_6 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); 
+
+Arbiter_20_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); 
+
+Arbiter_20_8 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); 
+
+Arbiter_20_9 : Arbiter
+
+PORT MAP (Request => Request(152), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); 
+
+Arbiter_20_10 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10),  
+South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); 
+
+Arbiter_20_11 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11),  
+South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); 
+
+Arbiter_20_12 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12),  
+South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); 
+
+Arbiter_20_13 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(19)(13), West => east_2_west(19)(12), P => Signal_priority(6), Fifo_full => Fifo_full(13),  
+South => south_2_north(20)(13), East => east_2_west(20)(13) , Grant => Signal_grant(20)(13)); 
+
+-------------------------- Diagonale n° 21 
+
+
+Arbiter_21_1 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(20)(1), West => east_2_west(20)(13), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); 
+
+Arbiter_21_2 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); 
+
+Arbiter_21_3 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); 
+
+Arbiter_21_4 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); 
+
+Arbiter_21_5 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); 
+
+Arbiter_21_6 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); 
+
+Arbiter_21_7 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); 
+
+Arbiter_21_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); 
+
+Arbiter_21_9 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); 
+
+Arbiter_21_10 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10),  
+South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); 
+
+Arbiter_21_11 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11),  
+South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); 
+
+Arbiter_21_12 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12),  
+South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); 
+
+Arbiter_21_13 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(20)(13), West => east_2_west(20)(12), P => Signal_priority(5), Fifo_full => Fifo_full(13),  
+South => south_2_north(21)(13), East => east_2_west(21)(13) , Grant => Signal_grant(21)(13)); 
+
+-------------------------- Diagonale n° 22 
+
+
+Arbiter_22_1 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(21)(1), West => east_2_west(21)(13), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); 
+
+Arbiter_22_2 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); 
+
+Arbiter_22_3 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); 
+
+Arbiter_22_4 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); 
+
+Arbiter_22_5 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); 
+
+Arbiter_22_6 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); 
+
+Arbiter_22_7 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); 
+
+Arbiter_22_8 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); 
+
+Arbiter_22_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); 
+
+Arbiter_22_10 : Arbiter
+
+PORT MAP (Request => Request(166), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10),  
+South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); 
+
+Arbiter_22_11 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11),  
+South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); 
+
+Arbiter_22_12 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12),  
+South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); 
+
+Arbiter_22_13 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(21)(13), West => east_2_west(21)(12), P => Signal_priority(4), Fifo_full => Fifo_full(13),  
+South => south_2_north(22)(13), East => east_2_west(22)(13) , Grant => Signal_grant(22)(13)); 
+
+-------------------------- Diagonale n° 23 
+
+
+Arbiter_23_1 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(22)(1), West => east_2_west(22)(13), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); 
+
+Arbiter_23_2 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); 
+
+Arbiter_23_3 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); 
+
+Arbiter_23_4 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); 
+
+Arbiter_23_5 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); 
+
+Arbiter_23_6 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); 
+
+Arbiter_23_7 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); 
+
+Arbiter_23_8 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); 
+
+Arbiter_23_9 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); 
+
+Arbiter_23_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10),  
+South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); 
+
+Arbiter_23_11 : Arbiter
+
+PORT MAP (Request => Request(167), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11),  
+South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); 
+
+Arbiter_23_12 : Arbiter
+
+PORT MAP (Request => Request(155), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12),  
+South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); 
+
+Arbiter_23_13 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(22)(13), West => east_2_west(22)(12), P => Signal_priority(3), Fifo_full => Fifo_full(13),  
+South => south_2_north(23)(13), East => east_2_west(23)(13) , Grant => Signal_grant(23)(13)); 
+
+-------------------------- Diagonale n° 24 
+
+
+Arbiter_24_1 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(23)(1), West => east_2_west(23)(13), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(24)(1), East => east_2_west(24)(1) , Grant => Signal_grant(24)(1)); 
+
+Arbiter_24_2 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(23)(2), West => east_2_west(23)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(24)(2), East => east_2_west(24)(2) , Grant => Signal_grant(24)(2)); 
+
+Arbiter_24_3 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(23)(3), West => east_2_west(23)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(24)(3), East => east_2_west(24)(3) , Grant => Signal_grant(24)(3)); 
+
+Arbiter_24_4 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(23)(4), West => east_2_west(23)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(24)(4), East => east_2_west(24)(4) , Grant => Signal_grant(24)(4)); 
+
+Arbiter_24_5 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(23)(5), West => east_2_west(23)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(24)(5), East => east_2_west(24)(5) , Grant => Signal_grant(24)(5)); 
+
+Arbiter_24_6 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(23)(6), West => east_2_west(23)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(24)(6), East => east_2_west(24)(6) , Grant => Signal_grant(24)(6)); 
+
+Arbiter_24_7 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(23)(7), West => east_2_west(23)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(24)(7), East => east_2_west(24)(7) , Grant => Signal_grant(24)(7)); 
+
+Arbiter_24_8 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(23)(8), West => east_2_west(23)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(24)(8), East => east_2_west(24)(8) , Grant => Signal_grant(24)(8)); 
+
+Arbiter_24_9 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(23)(9), West => east_2_west(23)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(24)(9), East => east_2_west(24)(9) , Grant => Signal_grant(24)(9)); 
+
+Arbiter_24_10 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(23)(10), West => east_2_west(23)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10),  
+South => south_2_north(24)(10), East => east_2_west(24)(10) , Grant => Signal_grant(24)(10)); 
+
+Arbiter_24_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(23)(11), West => east_2_west(23)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11),  
+South => south_2_north(24)(11), East => east_2_west(24)(11) , Grant => Signal_grant(24)(11)); 
+
+Arbiter_24_12 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(23)(12), West => east_2_west(23)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12),  
+South => south_2_north(24)(12), East => east_2_west(24)(12) , Grant => Signal_grant(24)(12)); 
+
+Arbiter_24_13 : Arbiter
+
+PORT MAP (Request => Request(156), North => south_2_north(23)(13), West => east_2_west(23)(12), P => Signal_priority(2), Fifo_full => Fifo_full(13),  
+South => south_2_north(24)(13), East => east_2_west(24)(13) , Grant => Signal_grant(24)(13)); 
+
+-------------------------- Diagonale n° 25 
+
+
+Arbiter_25_1 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(24)(1), West => east_2_west(24)(13), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(25)(1), East => east_2_west(25)(1) , Grant => Signal_grant(25)(1)); 
+
+Arbiter_25_2 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(24)(2), West => east_2_west(24)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(25)(2), East => east_2_west(25)(2) , Grant => Signal_grant(25)(2)); 
+
+Arbiter_25_3 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(24)(3), West => east_2_west(24)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(25)(3), East => east_2_west(25)(3) , Grant => Signal_grant(25)(3)); 
+
+Arbiter_25_4 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(24)(4), West => east_2_west(24)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(25)(4), East => east_2_west(25)(4) , Grant => Signal_grant(25)(4)); 
+
+Arbiter_25_5 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(24)(5), West => east_2_west(24)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(25)(5), East => east_2_west(25)(5) , Grant => Signal_grant(25)(5)); 
+
+Arbiter_25_6 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(24)(6), West => east_2_west(24)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(25)(6), East => east_2_west(25)(6) , Grant => Signal_grant(25)(6)); 
+
+Arbiter_25_7 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(24)(7), West => east_2_west(24)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(25)(7), East => east_2_west(25)(7) , Grant => Signal_grant(25)(7)); 
+
+Arbiter_25_8 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(24)(8), West => east_2_west(24)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(25)(8), East => east_2_west(25)(8) , Grant => Signal_grant(25)(8)); 
+
+Arbiter_25_9 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(24)(9), West => east_2_west(24)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(25)(9), East => east_2_west(25)(9) , Grant => Signal_grant(25)(9)); 
+
+Arbiter_25_10 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(24)(10), West => east_2_west(24)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10),  
+South => south_2_north(25)(10), East => east_2_west(25)(10) , Grant => Signal_grant(25)(10)); 
+
+Arbiter_25_11 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(24)(11), West => east_2_west(24)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11),  
+South => south_2_north(25)(11), East => east_2_west(25)(11) , Grant => Signal_grant(25)(11)); 
+
+Arbiter_25_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(24)(12), West => east_2_west(24)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12),  
+South => south_2_north(25)(12), East => east_2_west(25)(12) , Grant => Signal_grant(25)(12)); 
+
+Arbiter_25_13 : Arbiter
+
+PORT MAP (Request => Request(169), North => south_2_north(24)(13), West => east_2_west(24)(12), P => Signal_priority(1), Fifo_full => Fifo_full(13),  
+South => south_2_north(25)(13), East => east_2_west(25)(13) , Grant => Signal_grant(25)(13)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "1111111111111000000000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "1111111111111000000000000" => Signal_priority <= "0111111111111100000000000";
+		       when "0111111111111100000000000" => Signal_priority <= "0011111111111110000000000";
+		       when "0011111111111110000000000" => Signal_priority <= "0001111111111111000000000";
+		       when "0001111111111111000000000" => Signal_priority <= "0000111111111111100000000";
+		       when "0000111111111111100000000" => Signal_priority <= "0000011111111111110000000";
+		       when "0000011111111111110000000" => Signal_priority <= "0000001111111111111000000";
+		       when "0000001111111111111000000" => Signal_priority <= "0000000111111111111100000";
+		       when "0000000111111111111100000" => Signal_priority <= "0000000011111111111110000";
+		       when "0000000011111111111110000" => Signal_priority <= "0000000001111111111111000";
+		       when "0000000001111111111111000" => Signal_priority <= "0000000000111111111111100";
+		       when "0000000000111111111111100" => Signal_priority <= "0000000000011111111111110";
+		       when "0000000000011111111111110" => Signal_priority <= "0000000000001111111111111";
+		       when "0000000000001111111111111" => Signal_priority <= "1111111111111000000000000";
+		       when others    => Signal_priority <= "1111111111111000000000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER14_14.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER14_14.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER14_14.VHD	(revision 20)
@@ -0,0 +1,2276 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler14_14 is
+    Port ( Request : in  STD_LOGIC_VECTOR (196 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (14 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (14 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (196 downto 1));
+end Scheduler14_14;
+
+architecture Behavioral of Scheduler14_14 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(27 downto 1) of STD_LOGIC_VECTOR(14 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (27 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(196 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(196 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 16383 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(15)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(16)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(17)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(18)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(19)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(20)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(21)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(22)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) or Signal_grant(23)(9); --  Grant(1,9)
+Grant(10)  <= Signal_grant(10)(10) or Signal_grant(24)(10); --  Grant(1,10)
+Grant(11)  <= Signal_grant(11)(11) or Signal_grant(25)(11); --  Grant(1,11)
+Grant(12)  <= Signal_grant(12)(12) or Signal_grant(26)(12); --  Grant(1,12)
+Grant(13)  <= Signal_grant(13)(13) or Signal_grant(27)(13); --  Grant(1,13)
+Grant(14)  <= Signal_grant(14)(14) ;                      --  Grant(1,14)
+Grant(15)  <= Signal_grant(2)(1) or Signal_grant(16)(1); --  Grant(2,1)
+Grant(16)  <= Signal_grant(3)(2) or Signal_grant(17)(2); --  Grant(2,2)
+Grant(17)  <= Signal_grant(4)(3) or Signal_grant(18)(3); --  Grant(2,3)
+Grant(18)  <= Signal_grant(5)(4) or Signal_grant(19)(4); --  Grant(2,4)
+Grant(19)  <= Signal_grant(6)(5) or Signal_grant(20)(5); --  Grant(2,5)
+Grant(20)  <= Signal_grant(7)(6) or Signal_grant(21)(6); --  Grant(2,6)
+Grant(21)  <= Signal_grant(8)(7) or Signal_grant(22)(7); --  Grant(2,7)
+Grant(22)  <= Signal_grant(9)(8) or Signal_grant(23)(8); --  Grant(2,8)
+Grant(23)  <= Signal_grant(10)(9) or Signal_grant(24)(9); --  Grant(2,9)
+Grant(24)  <= Signal_grant(11)(10) or Signal_grant(25)(10); --  Grant(2,10)
+Grant(25)  <= Signal_grant(12)(11) or Signal_grant(26)(11); --  Grant(2,11)
+Grant(26)  <= Signal_grant(13)(12) or Signal_grant(27)(12); --  Grant(2,12)
+Grant(27)  <= Signal_grant(14)(13) ;                      --  Grant(2,13)
+Grant(28)  <= Signal_grant(1)(14) or Signal_grant(15)(14); --  Grant(2,14)
+Grant(29)  <= Signal_grant(3)(1) or Signal_grant(17)(1); --  Grant(3,1)
+Grant(30)  <= Signal_grant(4)(2) or Signal_grant(18)(2); --  Grant(3,2)
+Grant(31)  <= Signal_grant(5)(3) or Signal_grant(19)(3); --  Grant(3,3)
+Grant(32)  <= Signal_grant(6)(4) or Signal_grant(20)(4); --  Grant(3,4)
+Grant(33)  <= Signal_grant(7)(5) or Signal_grant(21)(5); --  Grant(3,5)
+Grant(34)  <= Signal_grant(8)(6) or Signal_grant(22)(6); --  Grant(3,6)
+Grant(35)  <= Signal_grant(9)(7) or Signal_grant(23)(7); --  Grant(3,7)
+Grant(36)  <= Signal_grant(10)(8) or Signal_grant(24)(8); --  Grant(3,8)
+Grant(37)  <= Signal_grant(11)(9) or Signal_grant(25)(9); --  Grant(3,9)
+Grant(38)  <= Signal_grant(12)(10) or Signal_grant(26)(10); --  Grant(3,10)
+Grant(39)  <= Signal_grant(13)(11) or Signal_grant(27)(11); --  Grant(3,11)
+Grant(40)  <= Signal_grant(14)(12) ;                      --  Grant(3,12)
+Grant(41)  <= Signal_grant(1)(13) or Signal_grant(15)(13); --  Grant(3,13)
+Grant(42)  <= Signal_grant(2)(14) or Signal_grant(16)(14); --  Grant(3,14)
+Grant(43)  <= Signal_grant(4)(1) or Signal_grant(18)(1); --  Grant(4,1)
+Grant(44)  <= Signal_grant(5)(2) or Signal_grant(19)(2); --  Grant(4,2)
+Grant(45)  <= Signal_grant(6)(3) or Signal_grant(20)(3); --  Grant(4,3)
+Grant(46)  <= Signal_grant(7)(4) or Signal_grant(21)(4); --  Grant(4,4)
+Grant(47)  <= Signal_grant(8)(5) or Signal_grant(22)(5); --  Grant(4,5)
+Grant(48)  <= Signal_grant(9)(6) or Signal_grant(23)(6); --  Grant(4,6)
+Grant(49)  <= Signal_grant(10)(7) or Signal_grant(24)(7); --  Grant(4,7)
+Grant(50)  <= Signal_grant(11)(8) or Signal_grant(25)(8); --  Grant(4,8)
+Grant(51)  <= Signal_grant(12)(9) or Signal_grant(26)(9); --  Grant(4,9)
+Grant(52)  <= Signal_grant(13)(10) or Signal_grant(27)(10); --  Grant(4,10)
+Grant(53)  <= Signal_grant(14)(11) ;                      --  Grant(4,11)
+Grant(54)  <= Signal_grant(1)(12) or Signal_grant(15)(12); --  Grant(4,12)
+Grant(55)  <= Signal_grant(2)(13) or Signal_grant(16)(13); --  Grant(4,13)
+Grant(56)  <= Signal_grant(3)(14) or Signal_grant(17)(14); --  Grant(4,14)
+Grant(57)  <= Signal_grant(5)(1) or Signal_grant(19)(1); --  Grant(5,1)
+Grant(58)  <= Signal_grant(6)(2) or Signal_grant(20)(2); --  Grant(5,2)
+Grant(59)  <= Signal_grant(7)(3) or Signal_grant(21)(3); --  Grant(5,3)
+Grant(60)  <= Signal_grant(8)(4) or Signal_grant(22)(4); --  Grant(5,4)
+Grant(61)  <= Signal_grant(9)(5) or Signal_grant(23)(5); --  Grant(5,5)
+Grant(62)  <= Signal_grant(10)(6) or Signal_grant(24)(6); --  Grant(5,6)
+Grant(63)  <= Signal_grant(11)(7) or Signal_grant(25)(7); --  Grant(5,7)
+Grant(64)  <= Signal_grant(12)(8) or Signal_grant(26)(8); --  Grant(5,8)
+Grant(65)  <= Signal_grant(13)(9) or Signal_grant(27)(9); --  Grant(5,9)
+Grant(66)  <= Signal_grant(14)(10) ;                      --  Grant(5,10)
+Grant(67)  <= Signal_grant(1)(11) or Signal_grant(15)(11); --  Grant(5,11)
+Grant(68)  <= Signal_grant(2)(12) or Signal_grant(16)(12); --  Grant(5,12)
+Grant(69)  <= Signal_grant(3)(13) or Signal_grant(17)(13); --  Grant(5,13)
+Grant(70)  <= Signal_grant(4)(14) or Signal_grant(18)(14); --  Grant(5,14)
+Grant(71)  <= Signal_grant(6)(1) or Signal_grant(20)(1); --  Grant(6,1)
+Grant(72)  <= Signal_grant(7)(2) or Signal_grant(21)(2); --  Grant(6,2)
+Grant(73)  <= Signal_grant(8)(3) or Signal_grant(22)(3); --  Grant(6,3)
+Grant(74)  <= Signal_grant(9)(4) or Signal_grant(23)(4); --  Grant(6,4)
+Grant(75)  <= Signal_grant(10)(5) or Signal_grant(24)(5); --  Grant(6,5)
+Grant(76)  <= Signal_grant(11)(6) or Signal_grant(25)(6); --  Grant(6,6)
+Grant(77)  <= Signal_grant(12)(7) or Signal_grant(26)(7); --  Grant(6,7)
+Grant(78)  <= Signal_grant(13)(8) or Signal_grant(27)(8); --  Grant(6,8)
+Grant(79)  <= Signal_grant(14)(9) ;                      --  Grant(6,9)
+Grant(80)  <= Signal_grant(1)(10) or Signal_grant(15)(10); --  Grant(6,10)
+Grant(81)  <= Signal_grant(2)(11) or Signal_grant(16)(11); --  Grant(6,11)
+Grant(82)  <= Signal_grant(3)(12) or Signal_grant(17)(12); --  Grant(6,12)
+Grant(83)  <= Signal_grant(4)(13) or Signal_grant(18)(13); --  Grant(6,13)
+Grant(84)  <= Signal_grant(5)(14) or Signal_grant(19)(14); --  Grant(6,14)
+Grant(85)  <= Signal_grant(7)(1) or Signal_grant(21)(1); --  Grant(7,1)
+Grant(86)  <= Signal_grant(8)(2) or Signal_grant(22)(2); --  Grant(7,2)
+Grant(87)  <= Signal_grant(9)(3) or Signal_grant(23)(3); --  Grant(7,3)
+Grant(88)  <= Signal_grant(10)(4) or Signal_grant(24)(4); --  Grant(7,4)
+Grant(89)  <= Signal_grant(11)(5) or Signal_grant(25)(5); --  Grant(7,5)
+Grant(90)  <= Signal_grant(12)(6) or Signal_grant(26)(6); --  Grant(7,6)
+Grant(91)  <= Signal_grant(13)(7) or Signal_grant(27)(7); --  Grant(7,7)
+Grant(92)  <= Signal_grant(14)(8) ;                      --  Grant(7,8)
+Grant(93)  <= Signal_grant(1)(9) or Signal_grant(15)(9); --  Grant(7,9)
+Grant(94)  <= Signal_grant(2)(10) or Signal_grant(16)(10); --  Grant(7,10)
+Grant(95)  <= Signal_grant(3)(11) or Signal_grant(17)(11); --  Grant(7,11)
+Grant(96)  <= Signal_grant(4)(12) or Signal_grant(18)(12); --  Grant(7,12)
+Grant(97)  <= Signal_grant(5)(13) or Signal_grant(19)(13); --  Grant(7,13)
+Grant(98)  <= Signal_grant(6)(14) or Signal_grant(20)(14); --  Grant(7,14)
+Grant(99)  <= Signal_grant(8)(1) or Signal_grant(22)(1); --  Grant(8,1)
+Grant(100)  <= Signal_grant(9)(2) or Signal_grant(23)(2); --  Grant(8,2)
+Grant(101)  <= Signal_grant(10)(3) or Signal_grant(24)(3); --  Grant(8,3)
+Grant(102)  <= Signal_grant(11)(4) or Signal_grant(25)(4); --  Grant(8,4)
+Grant(103)  <= Signal_grant(12)(5) or Signal_grant(26)(5); --  Grant(8,5)
+Grant(104)  <= Signal_grant(13)(6) or Signal_grant(27)(6); --  Grant(8,6)
+Grant(105)  <= Signal_grant(14)(7) ;                      --  Grant(8,7)
+Grant(106)  <= Signal_grant(1)(8) or Signal_grant(15)(8); --  Grant(8,8)
+Grant(107)  <= Signal_grant(2)(9) or Signal_grant(16)(9); --  Grant(8,9)
+Grant(108)  <= Signal_grant(3)(10) or Signal_grant(17)(10); --  Grant(8,10)
+Grant(109)  <= Signal_grant(4)(11) or Signal_grant(18)(11); --  Grant(8,11)
+Grant(110)  <= Signal_grant(5)(12) or Signal_grant(19)(12); --  Grant(8,12)
+Grant(111)  <= Signal_grant(6)(13) or Signal_grant(20)(13); --  Grant(8,13)
+Grant(112)  <= Signal_grant(7)(14) or Signal_grant(21)(14); --  Grant(8,14)
+Grant(113)  <= Signal_grant(9)(1) or Signal_grant(23)(1); --  Grant(9,1)
+Grant(114)  <= Signal_grant(10)(2) or Signal_grant(24)(2); --  Grant(9,2)
+Grant(115)  <= Signal_grant(11)(3) or Signal_grant(25)(3); --  Grant(9,3)
+Grant(116)  <= Signal_grant(12)(4) or Signal_grant(26)(4); --  Grant(9,4)
+Grant(117)  <= Signal_grant(13)(5) or Signal_grant(27)(5); --  Grant(9,5)
+Grant(118)  <= Signal_grant(14)(6) ;                      --  Grant(9,6)
+Grant(119)  <= Signal_grant(1)(7) or Signal_grant(15)(7); --  Grant(9,7)
+Grant(120)  <= Signal_grant(2)(8) or Signal_grant(16)(8); --  Grant(9,8)
+Grant(121)  <= Signal_grant(3)(9) or Signal_grant(17)(9); --  Grant(9,9)
+Grant(122)  <= Signal_grant(4)(10) or Signal_grant(18)(10); --  Grant(9,10)
+Grant(123)  <= Signal_grant(5)(11) or Signal_grant(19)(11); --  Grant(9,11)
+Grant(124)  <= Signal_grant(6)(12) or Signal_grant(20)(12); --  Grant(9,12)
+Grant(125)  <= Signal_grant(7)(13) or Signal_grant(21)(13); --  Grant(9,13)
+Grant(126)  <= Signal_grant(8)(14) or Signal_grant(22)(14); --  Grant(9,14)
+Grant(127)  <= Signal_grant(10)(1) or Signal_grant(24)(1); --  Grant(10,1)
+Grant(128)  <= Signal_grant(11)(2) or Signal_grant(25)(2); --  Grant(10,2)
+Grant(129)  <= Signal_grant(12)(3) or Signal_grant(26)(3); --  Grant(10,3)
+Grant(130)  <= Signal_grant(13)(4) or Signal_grant(27)(4); --  Grant(10,4)
+Grant(131)  <= Signal_grant(14)(5) ;                      --  Grant(10,5)
+Grant(132)  <= Signal_grant(1)(6) or Signal_grant(15)(6); --  Grant(10,6)
+Grant(133)  <= Signal_grant(2)(7) or Signal_grant(16)(7); --  Grant(10,7)
+Grant(134)  <= Signal_grant(3)(8) or Signal_grant(17)(8); --  Grant(10,8)
+Grant(135)  <= Signal_grant(4)(9) or Signal_grant(18)(9); --  Grant(10,9)
+Grant(136)  <= Signal_grant(5)(10) or Signal_grant(19)(10); --  Grant(10,10)
+Grant(137)  <= Signal_grant(6)(11) or Signal_grant(20)(11); --  Grant(10,11)
+Grant(138)  <= Signal_grant(7)(12) or Signal_grant(21)(12); --  Grant(10,12)
+Grant(139)  <= Signal_grant(8)(13) or Signal_grant(22)(13); --  Grant(10,13)
+Grant(140)  <= Signal_grant(9)(14) or Signal_grant(23)(14); --  Grant(10,14)
+Grant(141)  <= Signal_grant(11)(1) or Signal_grant(25)(1); --  Grant(11,1)
+Grant(142)  <= Signal_grant(12)(2) or Signal_grant(26)(2); --  Grant(11,2)
+Grant(143)  <= Signal_grant(13)(3) or Signal_grant(27)(3); --  Grant(11,3)
+Grant(144)  <= Signal_grant(14)(4) ;                      --  Grant(11,4)
+Grant(145)  <= Signal_grant(1)(5) or Signal_grant(15)(5); --  Grant(11,5)
+Grant(146)  <= Signal_grant(2)(6) or Signal_grant(16)(6); --  Grant(11,6)
+Grant(147)  <= Signal_grant(3)(7) or Signal_grant(17)(7); --  Grant(11,7)
+Grant(148)  <= Signal_grant(4)(8) or Signal_grant(18)(8); --  Grant(11,8)
+Grant(149)  <= Signal_grant(5)(9) or Signal_grant(19)(9); --  Grant(11,9)
+Grant(150)  <= Signal_grant(6)(10) or Signal_grant(20)(10); --  Grant(11,10)
+Grant(151)  <= Signal_grant(7)(11) or Signal_grant(21)(11); --  Grant(11,11)
+Grant(152)  <= Signal_grant(8)(12) or Signal_grant(22)(12); --  Grant(11,12)
+Grant(153)  <= Signal_grant(9)(13) or Signal_grant(23)(13); --  Grant(11,13)
+Grant(154)  <= Signal_grant(10)(14) or Signal_grant(24)(14); --  Grant(11,14)
+Grant(155)  <= Signal_grant(12)(1) or Signal_grant(26)(1); --  Grant(12,1)
+Grant(156)  <= Signal_grant(13)(2) or Signal_grant(27)(2); --  Grant(12,2)
+Grant(157)  <= Signal_grant(14)(3) ;                      --  Grant(12,3)
+Grant(158)  <= Signal_grant(1)(4) or Signal_grant(15)(4); --  Grant(12,4)
+Grant(159)  <= Signal_grant(2)(5) or Signal_grant(16)(5); --  Grant(12,5)
+Grant(160)  <= Signal_grant(3)(6) or Signal_grant(17)(6); --  Grant(12,6)
+Grant(161)  <= Signal_grant(4)(7) or Signal_grant(18)(7); --  Grant(12,7)
+Grant(162)  <= Signal_grant(5)(8) or Signal_grant(19)(8); --  Grant(12,8)
+Grant(163)  <= Signal_grant(6)(9) or Signal_grant(20)(9); --  Grant(12,9)
+Grant(164)  <= Signal_grant(7)(10) or Signal_grant(21)(10); --  Grant(12,10)
+Grant(165)  <= Signal_grant(8)(11) or Signal_grant(22)(11); --  Grant(12,11)
+Grant(166)  <= Signal_grant(9)(12) or Signal_grant(23)(12); --  Grant(12,12)
+Grant(167)  <= Signal_grant(10)(13) or Signal_grant(24)(13); --  Grant(12,13)
+Grant(168)  <= Signal_grant(11)(14) or Signal_grant(25)(14); --  Grant(12,14)
+Grant(169)  <= Signal_grant(13)(1) or Signal_grant(27)(1); --  Grant(13,1)
+Grant(170)  <= Signal_grant(14)(2) ;                      --  Grant(13,2)
+Grant(171)  <= Signal_grant(1)(3) or Signal_grant(15)(3); --  Grant(13,3)
+Grant(172)  <= Signal_grant(2)(4) or Signal_grant(16)(4); --  Grant(13,4)
+Grant(173)  <= Signal_grant(3)(5) or Signal_grant(17)(5); --  Grant(13,5)
+Grant(174)  <= Signal_grant(4)(6) or Signal_grant(18)(6); --  Grant(13,6)
+Grant(175)  <= Signal_grant(5)(7) or Signal_grant(19)(7); --  Grant(13,7)
+Grant(176)  <= Signal_grant(6)(8) or Signal_grant(20)(8); --  Grant(13,8)
+Grant(177)  <= Signal_grant(7)(9) or Signal_grant(21)(9); --  Grant(13,9)
+Grant(178)  <= Signal_grant(8)(10) or Signal_grant(22)(10); --  Grant(13,10)
+Grant(179)  <= Signal_grant(9)(11) or Signal_grant(23)(11); --  Grant(13,11)
+Grant(180)  <= Signal_grant(10)(12) or Signal_grant(24)(12); --  Grant(13,12)
+Grant(181)  <= Signal_grant(11)(13) or Signal_grant(25)(13); --  Grant(13,13)
+Grant(182)  <= Signal_grant(12)(14) or Signal_grant(26)(14); --  Grant(13,14)
+Grant(183)  <= Signal_grant(14)(1) ;                      --  Grant(14,1)
+Grant(184)  <= Signal_grant(1)(2) or Signal_grant(15)(2); --  Grant(14,2)
+Grant(185)  <= Signal_grant(2)(3) or Signal_grant(16)(3); --  Grant(14,3)
+Grant(186)  <= Signal_grant(3)(4) or Signal_grant(17)(4); --  Grant(14,4)
+Grant(187)  <= Signal_grant(4)(5) or Signal_grant(18)(5); --  Grant(14,5)
+Grant(188)  <= Signal_grant(5)(6) or Signal_grant(19)(6); --  Grant(14,6)
+Grant(189)  <= Signal_grant(6)(7) or Signal_grant(20)(7); --  Grant(14,7)
+Grant(190)  <= Signal_grant(7)(8) or Signal_grant(21)(8); --  Grant(14,8)
+Grant(191)  <= Signal_grant(8)(9) or Signal_grant(22)(9); --  Grant(14,9)
+Grant(192)  <= Signal_grant(9)(10) or Signal_grant(23)(10); --  Grant(14,10)
+Grant(193)  <= Signal_grant(10)(11) or Signal_grant(24)(11); --  Grant(14,11)
+Grant(194)  <= Signal_grant(11)(12) or Signal_grant(25)(12); --  Grant(14,12)
+Grant(195)  <= Signal_grant(12)(13) or Signal_grant(26)(13); --  Grant(14,13)
+Grant(196)  <= Signal_grant(13)(14) or Signal_grant(27)(14); --  Grant(14,14)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(184), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(171), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(158), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(145), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(132), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(119), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(106), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(93), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+Arbiter_1_10 : Arbiter
+
+PORT MAP (Request => Request(80), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(10),  
+South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); 
+
+Arbiter_1_11 : Arbiter
+
+PORT MAP (Request => Request(67), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(11),  
+South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); 
+
+Arbiter_1_12 : Arbiter
+
+PORT MAP (Request => Request(54), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(12),  
+South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); 
+
+Arbiter_1_13 : Arbiter
+
+PORT MAP (Request => Request(41), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(13),  
+South => south_2_north(1)(13), East => east_2_west(1)(13) , Grant => Signal_grant(1)(13)); 
+
+Arbiter_1_14 : Arbiter
+
+PORT MAP (Request => Request(28), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(14),  
+South => south_2_north(1)(14), East => east_2_west(1)(14) , Grant => Signal_grant(1)(14)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(1)(1), West => east_2_west(1)(14), P => Signal_priority(26), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(26), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(185), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(26), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(172), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(26), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(26), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(146), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(26), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(26), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(26), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(26), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+Arbiter_2_10 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(26), Fifo_full => Fifo_full(10),  
+South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); 
+
+Arbiter_2_11 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(26), Fifo_full => Fifo_full(11),  
+South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); 
+
+Arbiter_2_12 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(26), Fifo_full => Fifo_full(12),  
+South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); 
+
+Arbiter_2_13 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(1)(13), West => east_2_west(1)(12), P => Signal_priority(26), Fifo_full => Fifo_full(13),  
+South => south_2_north(2)(13), East => east_2_west(2)(13) , Grant => Signal_grant(2)(13)); 
+
+Arbiter_2_14 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(1)(14), West => east_2_west(1)(13), P => Signal_priority(26), Fifo_full => Fifo_full(14),  
+South => south_2_north(2)(14), East => east_2_west(2)(14) , Grant => Signal_grant(2)(14)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(2)(1), West => east_2_west(2)(14), P => Signal_priority(25), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(25), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(25), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(186), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(25), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(173), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(25), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(25), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(25), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(25), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(25), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+Arbiter_3_10 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(25), Fifo_full => Fifo_full(10),  
+South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); 
+
+Arbiter_3_11 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(25), Fifo_full => Fifo_full(11),  
+South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); 
+
+Arbiter_3_12 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(25), Fifo_full => Fifo_full(12),  
+South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); 
+
+Arbiter_3_13 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(2)(13), West => east_2_west(2)(12), P => Signal_priority(25), Fifo_full => Fifo_full(13),  
+South => south_2_north(3)(13), East => east_2_west(3)(13) , Grant => Signal_grant(3)(13)); 
+
+Arbiter_3_14 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(2)(14), West => east_2_west(2)(13), P => Signal_priority(25), Fifo_full => Fifo_full(14),  
+South => south_2_north(3)(14), East => east_2_west(3)(14) , Grant => Signal_grant(3)(14)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(3)(1), West => east_2_west(3)(14), P => Signal_priority(24), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(24), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(24), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(24), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(187), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(24), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(174), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(24), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(24), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(24), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(24), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+Arbiter_4_10 : Arbiter
+
+PORT MAP (Request => Request(122), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(24), Fifo_full => Fifo_full(10),  
+South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); 
+
+Arbiter_4_11 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(24), Fifo_full => Fifo_full(11),  
+South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); 
+
+Arbiter_4_12 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(24), Fifo_full => Fifo_full(12),  
+South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); 
+
+Arbiter_4_13 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(3)(13), West => east_2_west(3)(12), P => Signal_priority(24), Fifo_full => Fifo_full(13),  
+South => south_2_north(4)(13), East => east_2_west(4)(13) , Grant => Signal_grant(4)(13)); 
+
+Arbiter_4_14 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(3)(14), West => east_2_west(3)(13), P => Signal_priority(24), Fifo_full => Fifo_full(14),  
+South => south_2_north(4)(14), East => east_2_west(4)(14) , Grant => Signal_grant(4)(14)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(4)(1), West => east_2_west(4)(14), P => Signal_priority(23), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(23), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(23), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(23), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(23), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(188), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(23), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(175), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(23), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(23), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(23), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+Arbiter_5_10 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(23), Fifo_full => Fifo_full(10),  
+South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); 
+
+Arbiter_5_11 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(23), Fifo_full => Fifo_full(11),  
+South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); 
+
+Arbiter_5_12 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(23), Fifo_full => Fifo_full(12),  
+South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); 
+
+Arbiter_5_13 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(4)(13), West => east_2_west(4)(12), P => Signal_priority(23), Fifo_full => Fifo_full(13),  
+South => south_2_north(5)(13), East => east_2_west(5)(13) , Grant => Signal_grant(5)(13)); 
+
+Arbiter_5_14 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(4)(14), West => east_2_west(4)(13), P => Signal_priority(23), Fifo_full => Fifo_full(14),  
+South => south_2_north(5)(14), East => east_2_west(5)(14) , Grant => Signal_grant(5)(14)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(5)(1), West => east_2_west(5)(14), P => Signal_priority(22), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(189), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(176), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+Arbiter_6_10 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10),  
+South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); 
+
+Arbiter_6_11 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11),  
+South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); 
+
+Arbiter_6_12 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12),  
+South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); 
+
+Arbiter_6_13 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(5)(13), West => east_2_west(5)(12), P => Signal_priority(22), Fifo_full => Fifo_full(13),  
+South => south_2_north(6)(13), East => east_2_west(6)(13) , Grant => Signal_grant(6)(13)); 
+
+Arbiter_6_14 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(5)(14), West => east_2_west(5)(13), P => Signal_priority(22), Fifo_full => Fifo_full(14),  
+South => south_2_north(6)(14), East => east_2_west(6)(14) , Grant => Signal_grant(6)(14)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(6)(1), West => east_2_west(6)(14), P => Signal_priority(21), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(190), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(177), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+Arbiter_7_10 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10),  
+South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); 
+
+Arbiter_7_11 : Arbiter
+
+PORT MAP (Request => Request(151), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11),  
+South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); 
+
+Arbiter_7_12 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12),  
+South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); 
+
+Arbiter_7_13 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(6)(13), West => east_2_west(6)(12), P => Signal_priority(21), Fifo_full => Fifo_full(13),  
+South => south_2_north(7)(13), East => east_2_west(7)(13) , Grant => Signal_grant(7)(13)); 
+
+Arbiter_7_14 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(6)(14), West => east_2_west(6)(13), P => Signal_priority(21), Fifo_full => Fifo_full(14),  
+South => south_2_north(7)(14), East => east_2_west(7)(14) , Grant => Signal_grant(7)(14)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(7)(1), West => east_2_west(7)(14), P => Signal_priority(20), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(191), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+Arbiter_8_10 : Arbiter
+
+PORT MAP (Request => Request(178), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10),  
+South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); 
+
+Arbiter_8_11 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11),  
+South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); 
+
+Arbiter_8_12 : Arbiter
+
+PORT MAP (Request => Request(152), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12),  
+South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); 
+
+Arbiter_8_13 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(7)(13), West => east_2_west(7)(12), P => Signal_priority(20), Fifo_full => Fifo_full(13),  
+South => south_2_north(8)(13), East => east_2_west(8)(13) , Grant => Signal_grant(8)(13)); 
+
+Arbiter_8_14 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(7)(14), West => east_2_west(7)(13), P => Signal_priority(20), Fifo_full => Fifo_full(14),  
+South => south_2_north(8)(14), East => east_2_west(8)(14) , Grant => Signal_grant(8)(14)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(8)(1), West => east_2_west(8)(14), P => Signal_priority(19), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+Arbiter_9_10 : Arbiter
+
+PORT MAP (Request => Request(192), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10),  
+South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); 
+
+Arbiter_9_11 : Arbiter
+
+PORT MAP (Request => Request(179), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11),  
+South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); 
+
+Arbiter_9_12 : Arbiter
+
+PORT MAP (Request => Request(166), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12),  
+South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); 
+
+Arbiter_9_13 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(8)(13), West => east_2_west(8)(12), P => Signal_priority(19), Fifo_full => Fifo_full(13),  
+South => south_2_north(9)(13), East => east_2_west(9)(13) , Grant => Signal_grant(9)(13)); 
+
+Arbiter_9_14 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(8)(14), West => east_2_west(8)(13), P => Signal_priority(19), Fifo_full => Fifo_full(14),  
+South => south_2_north(9)(14), East => east_2_west(9)(14) , Grant => Signal_grant(9)(14)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(9)(1), West => east_2_west(9)(14), P => Signal_priority(18), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+Arbiter_10_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10),  
+South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); 
+
+Arbiter_10_11 : Arbiter
+
+PORT MAP (Request => Request(193), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11),  
+South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); 
+
+Arbiter_10_12 : Arbiter
+
+PORT MAP (Request => Request(180), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12),  
+South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); 
+
+Arbiter_10_13 : Arbiter
+
+PORT MAP (Request => Request(167), North => south_2_north(9)(13), West => east_2_west(9)(12), P => Signal_priority(18), Fifo_full => Fifo_full(13),  
+South => south_2_north(10)(13), East => east_2_west(10)(13) , Grant => Signal_grant(10)(13)); 
+
+Arbiter_10_14 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(9)(14), West => east_2_west(9)(13), P => Signal_priority(18), Fifo_full => Fifo_full(14),  
+South => south_2_north(10)(14), East => east_2_west(10)(14) , Grant => Signal_grant(10)(14)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(10)(1), West => east_2_west(10)(14), P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+Arbiter_11_10 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10),  
+South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); 
+
+Arbiter_11_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11),  
+South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); 
+
+Arbiter_11_12 : Arbiter
+
+PORT MAP (Request => Request(194), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12),  
+South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); 
+
+Arbiter_11_13 : Arbiter
+
+PORT MAP (Request => Request(181), North => south_2_north(10)(13), West => east_2_west(10)(12), P => Signal_priority(17), Fifo_full => Fifo_full(13),  
+South => south_2_north(11)(13), East => east_2_west(11)(13) , Grant => Signal_grant(11)(13)); 
+
+Arbiter_11_14 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(10)(14), West => east_2_west(10)(13), P => Signal_priority(17), Fifo_full => Fifo_full(14),  
+South => south_2_north(11)(14), East => east_2_west(11)(14) , Grant => Signal_grant(11)(14)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(155), North => south_2_north(11)(1), West => east_2_west(11)(14), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+Arbiter_12_10 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10),  
+South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); 
+
+Arbiter_12_11 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11),  
+South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); 
+
+Arbiter_12_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12),  
+South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); 
+
+Arbiter_12_13 : Arbiter
+
+PORT MAP (Request => Request(195), North => south_2_north(11)(13), West => east_2_west(11)(12), P => Signal_priority(16), Fifo_full => Fifo_full(13),  
+South => south_2_north(12)(13), East => east_2_west(12)(13) , Grant => Signal_grant(12)(13)); 
+
+Arbiter_12_14 : Arbiter
+
+PORT MAP (Request => Request(182), North => south_2_north(11)(14), West => east_2_west(11)(13), P => Signal_priority(16), Fifo_full => Fifo_full(14),  
+South => south_2_north(12)(14), East => east_2_west(12)(14) , Grant => Signal_grant(12)(14)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(169), North => south_2_north(12)(1), West => east_2_west(12)(14), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(156), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+Arbiter_13_10 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10),  
+South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); 
+
+Arbiter_13_11 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11),  
+South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); 
+
+Arbiter_13_12 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12),  
+South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); 
+
+Arbiter_13_13 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(12)(13), West => east_2_west(12)(12), P => Signal_priority(15), Fifo_full => Fifo_full(13),  
+South => south_2_north(13)(13), East => east_2_west(13)(13) , Grant => Signal_grant(13)(13)); 
+
+Arbiter_13_14 : Arbiter
+
+PORT MAP (Request => Request(196), North => south_2_north(12)(14), West => east_2_west(12)(13), P => Signal_priority(15), Fifo_full => Fifo_full(14),  
+South => south_2_north(13)(14), East => east_2_west(13)(14) , Grant => Signal_grant(13)(14)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(183), North => south_2_north(13)(1), West => east_2_west(13)(14), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(170), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(157), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+Arbiter_14_10 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10),  
+South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); 
+
+Arbiter_14_11 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11),  
+South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); 
+
+Arbiter_14_12 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12),  
+South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); 
+
+Arbiter_14_13 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(13)(13), West => east_2_west(13)(12), P => Signal_priority(14), Fifo_full => Fifo_full(13),  
+South => south_2_north(14)(13), East => east_2_west(14)(13) , Grant => Signal_grant(14)(13)); 
+
+Arbiter_14_14 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(13)(14), West => east_2_west(13)(13), P => Signal_priority(14), Fifo_full => Fifo_full(14),  
+South => south_2_north(14)(14), East => east_2_west(14)(14) , Grant => Signal_grant(14)(14)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(14)(1), West => east_2_west(14)(14), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(184), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(171), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(158), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(145), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+Arbiter_15_10 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10),  
+South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); 
+
+Arbiter_15_11 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11),  
+South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); 
+
+Arbiter_15_12 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12),  
+South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); 
+
+Arbiter_15_13 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(14)(13), West => east_2_west(14)(12), P => Signal_priority(13), Fifo_full => Fifo_full(13),  
+South => south_2_north(15)(13), East => east_2_west(15)(13) , Grant => Signal_grant(15)(13)); 
+
+Arbiter_15_14 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(14)(14), West => east_2_west(14)(13), P => Signal_priority(13), Fifo_full => Fifo_full(14),  
+South => south_2_north(15)(14), East => east_2_west(15)(14) , Grant => Signal_grant(15)(14)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(15)(1), West => east_2_west(15)(14), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(185), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(172), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(146), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+Arbiter_16_10 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10),  
+South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); 
+
+Arbiter_16_11 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11),  
+South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); 
+
+Arbiter_16_12 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12),  
+South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); 
+
+Arbiter_16_13 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(15)(13), West => east_2_west(15)(12), P => Signal_priority(12), Fifo_full => Fifo_full(13),  
+South => south_2_north(16)(13), East => east_2_west(16)(13) , Grant => Signal_grant(16)(13)); 
+
+Arbiter_16_14 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(15)(14), West => east_2_west(15)(13), P => Signal_priority(12), Fifo_full => Fifo_full(14),  
+South => south_2_north(16)(14), East => east_2_west(16)(14) , Grant => Signal_grant(16)(14)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(16)(1), West => east_2_west(16)(14), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(186), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(173), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+Arbiter_17_10 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10),  
+South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); 
+
+Arbiter_17_11 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11),  
+South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); 
+
+Arbiter_17_12 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12),  
+South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); 
+
+Arbiter_17_13 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(16)(13), West => east_2_west(16)(12), P => Signal_priority(11), Fifo_full => Fifo_full(13),  
+South => south_2_north(17)(13), East => east_2_west(17)(13) , Grant => Signal_grant(17)(13)); 
+
+Arbiter_17_14 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(16)(14), West => east_2_west(16)(13), P => Signal_priority(11), Fifo_full => Fifo_full(14),  
+South => south_2_north(17)(14), East => east_2_west(17)(14) , Grant => Signal_grant(17)(14)); 
+
+-------------------------- Diagonale n° 18 
+
+
+Arbiter_18_1 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(17)(1), West => east_2_west(17)(14), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); 
+
+Arbiter_18_2 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); 
+
+Arbiter_18_3 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); 
+
+Arbiter_18_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); 
+
+Arbiter_18_5 : Arbiter
+
+PORT MAP (Request => Request(187), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); 
+
+Arbiter_18_6 : Arbiter
+
+PORT MAP (Request => Request(174), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); 
+
+Arbiter_18_7 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); 
+
+Arbiter_18_8 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); 
+
+Arbiter_18_9 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); 
+
+Arbiter_18_10 : Arbiter
+
+PORT MAP (Request => Request(122), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10),  
+South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); 
+
+Arbiter_18_11 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11),  
+South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); 
+
+Arbiter_18_12 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12),  
+South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); 
+
+Arbiter_18_13 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(17)(13), West => east_2_west(17)(12), P => Signal_priority(10), Fifo_full => Fifo_full(13),  
+South => south_2_north(18)(13), East => east_2_west(18)(13) , Grant => Signal_grant(18)(13)); 
+
+Arbiter_18_14 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(17)(14), West => east_2_west(17)(13), P => Signal_priority(10), Fifo_full => Fifo_full(14),  
+South => south_2_north(18)(14), East => east_2_west(18)(14) , Grant => Signal_grant(18)(14)); 
+
+-------------------------- Diagonale n° 19 
+
+
+Arbiter_19_1 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(18)(1), West => east_2_west(18)(14), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); 
+
+Arbiter_19_2 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); 
+
+Arbiter_19_3 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); 
+
+Arbiter_19_4 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); 
+
+Arbiter_19_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); 
+
+Arbiter_19_6 : Arbiter
+
+PORT MAP (Request => Request(188), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); 
+
+Arbiter_19_7 : Arbiter
+
+PORT MAP (Request => Request(175), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); 
+
+Arbiter_19_8 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); 
+
+Arbiter_19_9 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); 
+
+Arbiter_19_10 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10),  
+South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); 
+
+Arbiter_19_11 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11),  
+South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); 
+
+Arbiter_19_12 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12),  
+South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); 
+
+Arbiter_19_13 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(18)(13), West => east_2_west(18)(12), P => Signal_priority(9), Fifo_full => Fifo_full(13),  
+South => south_2_north(19)(13), East => east_2_west(19)(13) , Grant => Signal_grant(19)(13)); 
+
+Arbiter_19_14 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(18)(14), West => east_2_west(18)(13), P => Signal_priority(9), Fifo_full => Fifo_full(14),  
+South => south_2_north(19)(14), East => east_2_west(19)(14) , Grant => Signal_grant(19)(14)); 
+
+-------------------------- Diagonale n° 20 
+
+
+Arbiter_20_1 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(19)(1), West => east_2_west(19)(14), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); 
+
+Arbiter_20_2 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); 
+
+Arbiter_20_3 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); 
+
+Arbiter_20_4 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); 
+
+Arbiter_20_5 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); 
+
+Arbiter_20_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); 
+
+Arbiter_20_7 : Arbiter
+
+PORT MAP (Request => Request(189), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); 
+
+Arbiter_20_8 : Arbiter
+
+PORT MAP (Request => Request(176), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); 
+
+Arbiter_20_9 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); 
+
+Arbiter_20_10 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10),  
+South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); 
+
+Arbiter_20_11 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11),  
+South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); 
+
+Arbiter_20_12 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12),  
+South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); 
+
+Arbiter_20_13 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(19)(13), West => east_2_west(19)(12), P => Signal_priority(8), Fifo_full => Fifo_full(13),  
+South => south_2_north(20)(13), East => east_2_west(20)(13) , Grant => Signal_grant(20)(13)); 
+
+Arbiter_20_14 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(19)(14), West => east_2_west(19)(13), P => Signal_priority(8), Fifo_full => Fifo_full(14),  
+South => south_2_north(20)(14), East => east_2_west(20)(14) , Grant => Signal_grant(20)(14)); 
+
+-------------------------- Diagonale n° 21 
+
+
+Arbiter_21_1 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(20)(1), West => east_2_west(20)(14), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); 
+
+Arbiter_21_2 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); 
+
+Arbiter_21_3 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); 
+
+Arbiter_21_4 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); 
+
+Arbiter_21_5 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); 
+
+Arbiter_21_6 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); 
+
+Arbiter_21_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); 
+
+Arbiter_21_8 : Arbiter
+
+PORT MAP (Request => Request(190), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); 
+
+Arbiter_21_9 : Arbiter
+
+PORT MAP (Request => Request(177), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); 
+
+Arbiter_21_10 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10),  
+South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); 
+
+Arbiter_21_11 : Arbiter
+
+PORT MAP (Request => Request(151), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11),  
+South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); 
+
+Arbiter_21_12 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12),  
+South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); 
+
+Arbiter_21_13 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(20)(13), West => east_2_west(20)(12), P => Signal_priority(7), Fifo_full => Fifo_full(13),  
+South => south_2_north(21)(13), East => east_2_west(21)(13) , Grant => Signal_grant(21)(13)); 
+
+Arbiter_21_14 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(20)(14), West => east_2_west(20)(13), P => Signal_priority(7), Fifo_full => Fifo_full(14),  
+South => south_2_north(21)(14), East => east_2_west(21)(14) , Grant => Signal_grant(21)(14)); 
+
+-------------------------- Diagonale n° 22 
+
+
+Arbiter_22_1 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(21)(1), West => east_2_west(21)(14), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); 
+
+Arbiter_22_2 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); 
+
+Arbiter_22_3 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); 
+
+Arbiter_22_4 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); 
+
+Arbiter_22_5 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); 
+
+Arbiter_22_6 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); 
+
+Arbiter_22_7 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); 
+
+Arbiter_22_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); 
+
+Arbiter_22_9 : Arbiter
+
+PORT MAP (Request => Request(191), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); 
+
+Arbiter_22_10 : Arbiter
+
+PORT MAP (Request => Request(178), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10),  
+South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); 
+
+Arbiter_22_11 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11),  
+South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); 
+
+Arbiter_22_12 : Arbiter
+
+PORT MAP (Request => Request(152), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12),  
+South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); 
+
+Arbiter_22_13 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(21)(13), West => east_2_west(21)(12), P => Signal_priority(6), Fifo_full => Fifo_full(13),  
+South => south_2_north(22)(13), East => east_2_west(22)(13) , Grant => Signal_grant(22)(13)); 
+
+Arbiter_22_14 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(21)(14), West => east_2_west(21)(13), P => Signal_priority(6), Fifo_full => Fifo_full(14),  
+South => south_2_north(22)(14), East => east_2_west(22)(14) , Grant => Signal_grant(22)(14)); 
+
+-------------------------- Diagonale n° 23 
+
+
+Arbiter_23_1 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(22)(1), West => east_2_west(22)(14), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); 
+
+Arbiter_23_2 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); 
+
+Arbiter_23_3 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); 
+
+Arbiter_23_4 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); 
+
+Arbiter_23_5 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); 
+
+Arbiter_23_6 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); 
+
+Arbiter_23_7 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); 
+
+Arbiter_23_8 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); 
+
+Arbiter_23_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); 
+
+Arbiter_23_10 : Arbiter
+
+PORT MAP (Request => Request(192), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10),  
+South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); 
+
+Arbiter_23_11 : Arbiter
+
+PORT MAP (Request => Request(179), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11),  
+South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); 
+
+Arbiter_23_12 : Arbiter
+
+PORT MAP (Request => Request(166), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12),  
+South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); 
+
+Arbiter_23_13 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(22)(13), West => east_2_west(22)(12), P => Signal_priority(5), Fifo_full => Fifo_full(13),  
+South => south_2_north(23)(13), East => east_2_west(23)(13) , Grant => Signal_grant(23)(13)); 
+
+Arbiter_23_14 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(22)(14), West => east_2_west(22)(13), P => Signal_priority(5), Fifo_full => Fifo_full(14),  
+South => south_2_north(23)(14), East => east_2_west(23)(14) , Grant => Signal_grant(23)(14)); 
+
+-------------------------- Diagonale n° 24 
+
+
+Arbiter_24_1 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(23)(1), West => east_2_west(23)(14), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(24)(1), East => east_2_west(24)(1) , Grant => Signal_grant(24)(1)); 
+
+Arbiter_24_2 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(23)(2), West => east_2_west(23)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(24)(2), East => east_2_west(24)(2) , Grant => Signal_grant(24)(2)); 
+
+Arbiter_24_3 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(23)(3), West => east_2_west(23)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(24)(3), East => east_2_west(24)(3) , Grant => Signal_grant(24)(3)); 
+
+Arbiter_24_4 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(23)(4), West => east_2_west(23)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(24)(4), East => east_2_west(24)(4) , Grant => Signal_grant(24)(4)); 
+
+Arbiter_24_5 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(23)(5), West => east_2_west(23)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(24)(5), East => east_2_west(24)(5) , Grant => Signal_grant(24)(5)); 
+
+Arbiter_24_6 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(23)(6), West => east_2_west(23)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(24)(6), East => east_2_west(24)(6) , Grant => Signal_grant(24)(6)); 
+
+Arbiter_24_7 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(23)(7), West => east_2_west(23)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(24)(7), East => east_2_west(24)(7) , Grant => Signal_grant(24)(7)); 
+
+Arbiter_24_8 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(23)(8), West => east_2_west(23)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(24)(8), East => east_2_west(24)(8) , Grant => Signal_grant(24)(8)); 
+
+Arbiter_24_9 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(23)(9), West => east_2_west(23)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(24)(9), East => east_2_west(24)(9) , Grant => Signal_grant(24)(9)); 
+
+Arbiter_24_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(23)(10), West => east_2_west(23)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10),  
+South => south_2_north(24)(10), East => east_2_west(24)(10) , Grant => Signal_grant(24)(10)); 
+
+Arbiter_24_11 : Arbiter
+
+PORT MAP (Request => Request(193), North => south_2_north(23)(11), West => east_2_west(23)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11),  
+South => south_2_north(24)(11), East => east_2_west(24)(11) , Grant => Signal_grant(24)(11)); 
+
+Arbiter_24_12 : Arbiter
+
+PORT MAP (Request => Request(180), North => south_2_north(23)(12), West => east_2_west(23)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12),  
+South => south_2_north(24)(12), East => east_2_west(24)(12) , Grant => Signal_grant(24)(12)); 
+
+Arbiter_24_13 : Arbiter
+
+PORT MAP (Request => Request(167), North => south_2_north(23)(13), West => east_2_west(23)(12), P => Signal_priority(4), Fifo_full => Fifo_full(13),  
+South => south_2_north(24)(13), East => east_2_west(24)(13) , Grant => Signal_grant(24)(13)); 
+
+Arbiter_24_14 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(23)(14), West => east_2_west(23)(13), P => Signal_priority(4), Fifo_full => Fifo_full(14),  
+South => south_2_north(24)(14), East => east_2_west(24)(14) , Grant => Signal_grant(24)(14)); 
+
+-------------------------- Diagonale n° 25 
+
+
+Arbiter_25_1 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(24)(1), West => east_2_west(24)(14), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(25)(1), East => east_2_west(25)(1) , Grant => Signal_grant(25)(1)); 
+
+Arbiter_25_2 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(24)(2), West => east_2_west(24)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(25)(2), East => east_2_west(25)(2) , Grant => Signal_grant(25)(2)); 
+
+Arbiter_25_3 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(24)(3), West => east_2_west(24)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(25)(3), East => east_2_west(25)(3) , Grant => Signal_grant(25)(3)); 
+
+Arbiter_25_4 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(24)(4), West => east_2_west(24)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(25)(4), East => east_2_west(25)(4) , Grant => Signal_grant(25)(4)); 
+
+Arbiter_25_5 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(24)(5), West => east_2_west(24)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(25)(5), East => east_2_west(25)(5) , Grant => Signal_grant(25)(5)); 
+
+Arbiter_25_6 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(24)(6), West => east_2_west(24)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(25)(6), East => east_2_west(25)(6) , Grant => Signal_grant(25)(6)); 
+
+Arbiter_25_7 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(24)(7), West => east_2_west(24)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(25)(7), East => east_2_west(25)(7) , Grant => Signal_grant(25)(7)); 
+
+Arbiter_25_8 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(24)(8), West => east_2_west(24)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(25)(8), East => east_2_west(25)(8) , Grant => Signal_grant(25)(8)); 
+
+Arbiter_25_9 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(24)(9), West => east_2_west(24)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(25)(9), East => east_2_west(25)(9) , Grant => Signal_grant(25)(9)); 
+
+Arbiter_25_10 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(24)(10), West => east_2_west(24)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10),  
+South => south_2_north(25)(10), East => east_2_west(25)(10) , Grant => Signal_grant(25)(10)); 
+
+Arbiter_25_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(24)(11), West => east_2_west(24)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11),  
+South => south_2_north(25)(11), East => east_2_west(25)(11) , Grant => Signal_grant(25)(11)); 
+
+Arbiter_25_12 : Arbiter
+
+PORT MAP (Request => Request(194), North => south_2_north(24)(12), West => east_2_west(24)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12),  
+South => south_2_north(25)(12), East => east_2_west(25)(12) , Grant => Signal_grant(25)(12)); 
+
+Arbiter_25_13 : Arbiter
+
+PORT MAP (Request => Request(181), North => south_2_north(24)(13), West => east_2_west(24)(12), P => Signal_priority(3), Fifo_full => Fifo_full(13),  
+South => south_2_north(25)(13), East => east_2_west(25)(13) , Grant => Signal_grant(25)(13)); 
+
+Arbiter_25_14 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(24)(14), West => east_2_west(24)(13), P => Signal_priority(3), Fifo_full => Fifo_full(14),  
+South => south_2_north(25)(14), East => east_2_west(25)(14) , Grant => Signal_grant(25)(14)); 
+
+-------------------------- Diagonale n° 26 
+
+
+Arbiter_26_1 : Arbiter
+
+PORT MAP (Request => Request(155), North => south_2_north(25)(1), West => east_2_west(25)(14), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(26)(1), East => east_2_west(26)(1) , Grant => Signal_grant(26)(1)); 
+
+Arbiter_26_2 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(25)(2), West => east_2_west(25)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(26)(2), East => east_2_west(26)(2) , Grant => Signal_grant(26)(2)); 
+
+Arbiter_26_3 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(25)(3), West => east_2_west(25)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(26)(3), East => east_2_west(26)(3) , Grant => Signal_grant(26)(3)); 
+
+Arbiter_26_4 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(25)(4), West => east_2_west(25)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(26)(4), East => east_2_west(26)(4) , Grant => Signal_grant(26)(4)); 
+
+Arbiter_26_5 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(25)(5), West => east_2_west(25)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(26)(5), East => east_2_west(26)(5) , Grant => Signal_grant(26)(5)); 
+
+Arbiter_26_6 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(25)(6), West => east_2_west(25)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(26)(6), East => east_2_west(26)(6) , Grant => Signal_grant(26)(6)); 
+
+Arbiter_26_7 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(25)(7), West => east_2_west(25)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(26)(7), East => east_2_west(26)(7) , Grant => Signal_grant(26)(7)); 
+
+Arbiter_26_8 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(25)(8), West => east_2_west(25)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(26)(8), East => east_2_west(26)(8) , Grant => Signal_grant(26)(8)); 
+
+Arbiter_26_9 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(25)(9), West => east_2_west(25)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(26)(9), East => east_2_west(26)(9) , Grant => Signal_grant(26)(9)); 
+
+Arbiter_26_10 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(25)(10), West => east_2_west(25)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10),  
+South => south_2_north(26)(10), East => east_2_west(26)(10) , Grant => Signal_grant(26)(10)); 
+
+Arbiter_26_11 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(25)(11), West => east_2_west(25)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11),  
+South => south_2_north(26)(11), East => east_2_west(26)(11) , Grant => Signal_grant(26)(11)); 
+
+Arbiter_26_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(25)(12), West => east_2_west(25)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12),  
+South => south_2_north(26)(12), East => east_2_west(26)(12) , Grant => Signal_grant(26)(12)); 
+
+Arbiter_26_13 : Arbiter
+
+PORT MAP (Request => Request(195), North => south_2_north(25)(13), West => east_2_west(25)(12), P => Signal_priority(2), Fifo_full => Fifo_full(13),  
+South => south_2_north(26)(13), East => east_2_west(26)(13) , Grant => Signal_grant(26)(13)); 
+
+Arbiter_26_14 : Arbiter
+
+PORT MAP (Request => Request(182), North => south_2_north(25)(14), West => east_2_west(25)(13), P => Signal_priority(2), Fifo_full => Fifo_full(14),  
+South => south_2_north(26)(14), East => east_2_west(26)(14) , Grant => Signal_grant(26)(14)); 
+
+-------------------------- Diagonale n° 27 
+
+
+Arbiter_27_1 : Arbiter
+
+PORT MAP (Request => Request(169), North => south_2_north(26)(1), West => east_2_west(26)(14), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(27)(1), East => east_2_west(27)(1) , Grant => Signal_grant(27)(1)); 
+
+Arbiter_27_2 : Arbiter
+
+PORT MAP (Request => Request(156), North => south_2_north(26)(2), West => east_2_west(26)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(27)(2), East => east_2_west(27)(2) , Grant => Signal_grant(27)(2)); 
+
+Arbiter_27_3 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(26)(3), West => east_2_west(26)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(27)(3), East => east_2_west(27)(3) , Grant => Signal_grant(27)(3)); 
+
+Arbiter_27_4 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(26)(4), West => east_2_west(26)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(27)(4), East => east_2_west(27)(4) , Grant => Signal_grant(27)(4)); 
+
+Arbiter_27_5 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(26)(5), West => east_2_west(26)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(27)(5), East => east_2_west(27)(5) , Grant => Signal_grant(27)(5)); 
+
+Arbiter_27_6 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(26)(6), West => east_2_west(26)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(27)(6), East => east_2_west(27)(6) , Grant => Signal_grant(27)(6)); 
+
+Arbiter_27_7 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(26)(7), West => east_2_west(26)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(27)(7), East => east_2_west(27)(7) , Grant => Signal_grant(27)(7)); 
+
+Arbiter_27_8 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(26)(8), West => east_2_west(26)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(27)(8), East => east_2_west(27)(8) , Grant => Signal_grant(27)(8)); 
+
+Arbiter_27_9 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(26)(9), West => east_2_west(26)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(27)(9), East => east_2_west(27)(9) , Grant => Signal_grant(27)(9)); 
+
+Arbiter_27_10 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(26)(10), West => east_2_west(26)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10),  
+South => south_2_north(27)(10), East => east_2_west(27)(10) , Grant => Signal_grant(27)(10)); 
+
+Arbiter_27_11 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(26)(11), West => east_2_west(26)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11),  
+South => south_2_north(27)(11), East => east_2_west(27)(11) , Grant => Signal_grant(27)(11)); 
+
+Arbiter_27_12 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(26)(12), West => east_2_west(26)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12),  
+South => south_2_north(27)(12), East => east_2_west(27)(12) , Grant => Signal_grant(27)(12)); 
+
+Arbiter_27_13 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(26)(13), West => east_2_west(26)(12), P => Signal_priority(1), Fifo_full => Fifo_full(13),  
+South => south_2_north(27)(13), East => east_2_west(27)(13) , Grant => Signal_grant(27)(13)); 
+
+Arbiter_27_14 : Arbiter
+
+PORT MAP (Request => Request(196), North => south_2_north(26)(14), West => east_2_west(26)(13), P => Signal_priority(1), Fifo_full => Fifo_full(14),  
+South => south_2_north(27)(14), East => east_2_west(27)(14) , Grant => Signal_grant(27)(14)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "111111111111110000000000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "111111111111110000000000000" => Signal_priority <= "011111111111111000000000000";
+		       when "011111111111111000000000000" => Signal_priority <= "001111111111111100000000000";
+		       when "001111111111111100000000000" => Signal_priority <= "000111111111111110000000000";
+		       when "000111111111111110000000000" => Signal_priority <= "000011111111111111000000000";
+		       when "000011111111111111000000000" => Signal_priority <= "000001111111111111100000000";
+		       when "000001111111111111100000000" => Signal_priority <= "000000111111111111110000000";
+		       when "000000111111111111110000000" => Signal_priority <= "000000011111111111111000000";
+		       when "000000011111111111111000000" => Signal_priority <= "000000001111111111111100000";
+		       when "000000001111111111111100000" => Signal_priority <= "000000000111111111111110000";
+		       when "000000000111111111111110000" => Signal_priority <= "000000000011111111111111000";
+		       when "000000000011111111111111000" => Signal_priority <= "000000000001111111111111100";
+		       when "000000000001111111111111100" => Signal_priority <= "000000000000111111111111110";
+		       when "000000000000111111111111110" => Signal_priority <= "000000000000011111111111111";
+		       when "000000000000011111111111111" => Signal_priority <= "111111111111110000000000000";
+		       when others    => Signal_priority <= "111111111111110000000000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER15_15.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER15_15.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER15_15.VHD	(revision 20)
@@ -0,0 +1,2597 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler15_15 is
+    Port ( Request : in  STD_LOGIC_VECTOR (225 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (15 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (15 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (225 downto 1));
+end Scheduler15_15;
+
+architecture Behavioral of Scheduler15_15 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(29 downto 1) of STD_LOGIC_VECTOR(15 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (29 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(225 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(225 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 32767 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(16)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(17)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(18)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(19)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(20)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(21)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(22)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(23)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) or Signal_grant(24)(9); --  Grant(1,9)
+Grant(10)  <= Signal_grant(10)(10) or Signal_grant(25)(10); --  Grant(1,10)
+Grant(11)  <= Signal_grant(11)(11) or Signal_grant(26)(11); --  Grant(1,11)
+Grant(12)  <= Signal_grant(12)(12) or Signal_grant(27)(12); --  Grant(1,12)
+Grant(13)  <= Signal_grant(13)(13) or Signal_grant(28)(13); --  Grant(1,13)
+Grant(14)  <= Signal_grant(14)(14) or Signal_grant(29)(14); --  Grant(1,14)
+Grant(15)  <= Signal_grant(15)(15) ;                      --  Grant(1,15)
+Grant(16)  <= Signal_grant(2)(1) or Signal_grant(17)(1); --  Grant(2,1)
+Grant(17)  <= Signal_grant(3)(2) or Signal_grant(18)(2); --  Grant(2,2)
+Grant(18)  <= Signal_grant(4)(3) or Signal_grant(19)(3); --  Grant(2,3)
+Grant(19)  <= Signal_grant(5)(4) or Signal_grant(20)(4); --  Grant(2,4)
+Grant(20)  <= Signal_grant(6)(5) or Signal_grant(21)(5); --  Grant(2,5)
+Grant(21)  <= Signal_grant(7)(6) or Signal_grant(22)(6); --  Grant(2,6)
+Grant(22)  <= Signal_grant(8)(7) or Signal_grant(23)(7); --  Grant(2,7)
+Grant(23)  <= Signal_grant(9)(8) or Signal_grant(24)(8); --  Grant(2,8)
+Grant(24)  <= Signal_grant(10)(9) or Signal_grant(25)(9); --  Grant(2,9)
+Grant(25)  <= Signal_grant(11)(10) or Signal_grant(26)(10); --  Grant(2,10)
+Grant(26)  <= Signal_grant(12)(11) or Signal_grant(27)(11); --  Grant(2,11)
+Grant(27)  <= Signal_grant(13)(12) or Signal_grant(28)(12); --  Grant(2,12)
+Grant(28)  <= Signal_grant(14)(13) or Signal_grant(29)(13); --  Grant(2,13)
+Grant(29)  <= Signal_grant(15)(14) ;                      --  Grant(2,14)
+Grant(30)  <= Signal_grant(1)(15) or Signal_grant(16)(15); --  Grant(2,15)
+Grant(31)  <= Signal_grant(3)(1) or Signal_grant(18)(1); --  Grant(3,1)
+Grant(32)  <= Signal_grant(4)(2) or Signal_grant(19)(2); --  Grant(3,2)
+Grant(33)  <= Signal_grant(5)(3) or Signal_grant(20)(3); --  Grant(3,3)
+Grant(34)  <= Signal_grant(6)(4) or Signal_grant(21)(4); --  Grant(3,4)
+Grant(35)  <= Signal_grant(7)(5) or Signal_grant(22)(5); --  Grant(3,5)
+Grant(36)  <= Signal_grant(8)(6) or Signal_grant(23)(6); --  Grant(3,6)
+Grant(37)  <= Signal_grant(9)(7) or Signal_grant(24)(7); --  Grant(3,7)
+Grant(38)  <= Signal_grant(10)(8) or Signal_grant(25)(8); --  Grant(3,8)
+Grant(39)  <= Signal_grant(11)(9) or Signal_grant(26)(9); --  Grant(3,9)
+Grant(40)  <= Signal_grant(12)(10) or Signal_grant(27)(10); --  Grant(3,10)
+Grant(41)  <= Signal_grant(13)(11) or Signal_grant(28)(11); --  Grant(3,11)
+Grant(42)  <= Signal_grant(14)(12) or Signal_grant(29)(12); --  Grant(3,12)
+Grant(43)  <= Signal_grant(15)(13) ;                      --  Grant(3,13)
+Grant(44)  <= Signal_grant(1)(14) or Signal_grant(16)(14); --  Grant(3,14)
+Grant(45)  <= Signal_grant(2)(15) or Signal_grant(17)(15); --  Grant(3,15)
+Grant(46)  <= Signal_grant(4)(1) or Signal_grant(19)(1); --  Grant(4,1)
+Grant(47)  <= Signal_grant(5)(2) or Signal_grant(20)(2); --  Grant(4,2)
+Grant(48)  <= Signal_grant(6)(3) or Signal_grant(21)(3); --  Grant(4,3)
+Grant(49)  <= Signal_grant(7)(4) or Signal_grant(22)(4); --  Grant(4,4)
+Grant(50)  <= Signal_grant(8)(5) or Signal_grant(23)(5); --  Grant(4,5)
+Grant(51)  <= Signal_grant(9)(6) or Signal_grant(24)(6); --  Grant(4,6)
+Grant(52)  <= Signal_grant(10)(7) or Signal_grant(25)(7); --  Grant(4,7)
+Grant(53)  <= Signal_grant(11)(8) or Signal_grant(26)(8); --  Grant(4,8)
+Grant(54)  <= Signal_grant(12)(9) or Signal_grant(27)(9); --  Grant(4,9)
+Grant(55)  <= Signal_grant(13)(10) or Signal_grant(28)(10); --  Grant(4,10)
+Grant(56)  <= Signal_grant(14)(11) or Signal_grant(29)(11); --  Grant(4,11)
+Grant(57)  <= Signal_grant(15)(12) ;                      --  Grant(4,12)
+Grant(58)  <= Signal_grant(1)(13) or Signal_grant(16)(13); --  Grant(4,13)
+Grant(59)  <= Signal_grant(2)(14) or Signal_grant(17)(14); --  Grant(4,14)
+Grant(60)  <= Signal_grant(3)(15) or Signal_grant(18)(15); --  Grant(4,15)
+Grant(61)  <= Signal_grant(5)(1) or Signal_grant(20)(1); --  Grant(5,1)
+Grant(62)  <= Signal_grant(6)(2) or Signal_grant(21)(2); --  Grant(5,2)
+Grant(63)  <= Signal_grant(7)(3) or Signal_grant(22)(3); --  Grant(5,3)
+Grant(64)  <= Signal_grant(8)(4) or Signal_grant(23)(4); --  Grant(5,4)
+Grant(65)  <= Signal_grant(9)(5) or Signal_grant(24)(5); --  Grant(5,5)
+Grant(66)  <= Signal_grant(10)(6) or Signal_grant(25)(6); --  Grant(5,6)
+Grant(67)  <= Signal_grant(11)(7) or Signal_grant(26)(7); --  Grant(5,7)
+Grant(68)  <= Signal_grant(12)(8) or Signal_grant(27)(8); --  Grant(5,8)
+Grant(69)  <= Signal_grant(13)(9) or Signal_grant(28)(9); --  Grant(5,9)
+Grant(70)  <= Signal_grant(14)(10) or Signal_grant(29)(10); --  Grant(5,10)
+Grant(71)  <= Signal_grant(15)(11) ;                      --  Grant(5,11)
+Grant(72)  <= Signal_grant(1)(12) or Signal_grant(16)(12); --  Grant(5,12)
+Grant(73)  <= Signal_grant(2)(13) or Signal_grant(17)(13); --  Grant(5,13)
+Grant(74)  <= Signal_grant(3)(14) or Signal_grant(18)(14); --  Grant(5,14)
+Grant(75)  <= Signal_grant(4)(15) or Signal_grant(19)(15); --  Grant(5,15)
+Grant(76)  <= Signal_grant(6)(1) or Signal_grant(21)(1); --  Grant(6,1)
+Grant(77)  <= Signal_grant(7)(2) or Signal_grant(22)(2); --  Grant(6,2)
+Grant(78)  <= Signal_grant(8)(3) or Signal_grant(23)(3); --  Grant(6,3)
+Grant(79)  <= Signal_grant(9)(4) or Signal_grant(24)(4); --  Grant(6,4)
+Grant(80)  <= Signal_grant(10)(5) or Signal_grant(25)(5); --  Grant(6,5)
+Grant(81)  <= Signal_grant(11)(6) or Signal_grant(26)(6); --  Grant(6,6)
+Grant(82)  <= Signal_grant(12)(7) or Signal_grant(27)(7); --  Grant(6,7)
+Grant(83)  <= Signal_grant(13)(8) or Signal_grant(28)(8); --  Grant(6,8)
+Grant(84)  <= Signal_grant(14)(9) or Signal_grant(29)(9); --  Grant(6,9)
+Grant(85)  <= Signal_grant(15)(10) ;                      --  Grant(6,10)
+Grant(86)  <= Signal_grant(1)(11) or Signal_grant(16)(11); --  Grant(6,11)
+Grant(87)  <= Signal_grant(2)(12) or Signal_grant(17)(12); --  Grant(6,12)
+Grant(88)  <= Signal_grant(3)(13) or Signal_grant(18)(13); --  Grant(6,13)
+Grant(89)  <= Signal_grant(4)(14) or Signal_grant(19)(14); --  Grant(6,14)
+Grant(90)  <= Signal_grant(5)(15) or Signal_grant(20)(15); --  Grant(6,15)
+Grant(91)  <= Signal_grant(7)(1) or Signal_grant(22)(1); --  Grant(7,1)
+Grant(92)  <= Signal_grant(8)(2) or Signal_grant(23)(2); --  Grant(7,2)
+Grant(93)  <= Signal_grant(9)(3) or Signal_grant(24)(3); --  Grant(7,3)
+Grant(94)  <= Signal_grant(10)(4) or Signal_grant(25)(4); --  Grant(7,4)
+Grant(95)  <= Signal_grant(11)(5) or Signal_grant(26)(5); --  Grant(7,5)
+Grant(96)  <= Signal_grant(12)(6) or Signal_grant(27)(6); --  Grant(7,6)
+Grant(97)  <= Signal_grant(13)(7) or Signal_grant(28)(7); --  Grant(7,7)
+Grant(98)  <= Signal_grant(14)(8) or Signal_grant(29)(8); --  Grant(7,8)
+Grant(99)  <= Signal_grant(15)(9) ;                      --  Grant(7,9)
+Grant(100)  <= Signal_grant(1)(10) or Signal_grant(16)(10); --  Grant(7,10)
+Grant(101)  <= Signal_grant(2)(11) or Signal_grant(17)(11); --  Grant(7,11)
+Grant(102)  <= Signal_grant(3)(12) or Signal_grant(18)(12); --  Grant(7,12)
+Grant(103)  <= Signal_grant(4)(13) or Signal_grant(19)(13); --  Grant(7,13)
+Grant(104)  <= Signal_grant(5)(14) or Signal_grant(20)(14); --  Grant(7,14)
+Grant(105)  <= Signal_grant(6)(15) or Signal_grant(21)(15); --  Grant(7,15)
+Grant(106)  <= Signal_grant(8)(1) or Signal_grant(23)(1); --  Grant(8,1)
+Grant(107)  <= Signal_grant(9)(2) or Signal_grant(24)(2); --  Grant(8,2)
+Grant(108)  <= Signal_grant(10)(3) or Signal_grant(25)(3); --  Grant(8,3)
+Grant(109)  <= Signal_grant(11)(4) or Signal_grant(26)(4); --  Grant(8,4)
+Grant(110)  <= Signal_grant(12)(5) or Signal_grant(27)(5); --  Grant(8,5)
+Grant(111)  <= Signal_grant(13)(6) or Signal_grant(28)(6); --  Grant(8,6)
+Grant(112)  <= Signal_grant(14)(7) or Signal_grant(29)(7); --  Grant(8,7)
+Grant(113)  <= Signal_grant(15)(8) ;                      --  Grant(8,8)
+Grant(114)  <= Signal_grant(1)(9) or Signal_grant(16)(9); --  Grant(8,9)
+Grant(115)  <= Signal_grant(2)(10) or Signal_grant(17)(10); --  Grant(8,10)
+Grant(116)  <= Signal_grant(3)(11) or Signal_grant(18)(11); --  Grant(8,11)
+Grant(117)  <= Signal_grant(4)(12) or Signal_grant(19)(12); --  Grant(8,12)
+Grant(118)  <= Signal_grant(5)(13) or Signal_grant(20)(13); --  Grant(8,13)
+Grant(119)  <= Signal_grant(6)(14) or Signal_grant(21)(14); --  Grant(8,14)
+Grant(120)  <= Signal_grant(7)(15) or Signal_grant(22)(15); --  Grant(8,15)
+Grant(121)  <= Signal_grant(9)(1) or Signal_grant(24)(1); --  Grant(9,1)
+Grant(122)  <= Signal_grant(10)(2) or Signal_grant(25)(2); --  Grant(9,2)
+Grant(123)  <= Signal_grant(11)(3) or Signal_grant(26)(3); --  Grant(9,3)
+Grant(124)  <= Signal_grant(12)(4) or Signal_grant(27)(4); --  Grant(9,4)
+Grant(125)  <= Signal_grant(13)(5) or Signal_grant(28)(5); --  Grant(9,5)
+Grant(126)  <= Signal_grant(14)(6) or Signal_grant(29)(6); --  Grant(9,6)
+Grant(127)  <= Signal_grant(15)(7) ;                      --  Grant(9,7)
+Grant(128)  <= Signal_grant(1)(8) or Signal_grant(16)(8); --  Grant(9,8)
+Grant(129)  <= Signal_grant(2)(9) or Signal_grant(17)(9); --  Grant(9,9)
+Grant(130)  <= Signal_grant(3)(10) or Signal_grant(18)(10); --  Grant(9,10)
+Grant(131)  <= Signal_grant(4)(11) or Signal_grant(19)(11); --  Grant(9,11)
+Grant(132)  <= Signal_grant(5)(12) or Signal_grant(20)(12); --  Grant(9,12)
+Grant(133)  <= Signal_grant(6)(13) or Signal_grant(21)(13); --  Grant(9,13)
+Grant(134)  <= Signal_grant(7)(14) or Signal_grant(22)(14); --  Grant(9,14)
+Grant(135)  <= Signal_grant(8)(15) or Signal_grant(23)(15); --  Grant(9,15)
+Grant(136)  <= Signal_grant(10)(1) or Signal_grant(25)(1); --  Grant(10,1)
+Grant(137)  <= Signal_grant(11)(2) or Signal_grant(26)(2); --  Grant(10,2)
+Grant(138)  <= Signal_grant(12)(3) or Signal_grant(27)(3); --  Grant(10,3)
+Grant(139)  <= Signal_grant(13)(4) or Signal_grant(28)(4); --  Grant(10,4)
+Grant(140)  <= Signal_grant(14)(5) or Signal_grant(29)(5); --  Grant(10,5)
+Grant(141)  <= Signal_grant(15)(6) ;                      --  Grant(10,6)
+Grant(142)  <= Signal_grant(1)(7) or Signal_grant(16)(7); --  Grant(10,7)
+Grant(143)  <= Signal_grant(2)(8) or Signal_grant(17)(8); --  Grant(10,8)
+Grant(144)  <= Signal_grant(3)(9) or Signal_grant(18)(9); --  Grant(10,9)
+Grant(145)  <= Signal_grant(4)(10) or Signal_grant(19)(10); --  Grant(10,10)
+Grant(146)  <= Signal_grant(5)(11) or Signal_grant(20)(11); --  Grant(10,11)
+Grant(147)  <= Signal_grant(6)(12) or Signal_grant(21)(12); --  Grant(10,12)
+Grant(148)  <= Signal_grant(7)(13) or Signal_grant(22)(13); --  Grant(10,13)
+Grant(149)  <= Signal_grant(8)(14) or Signal_grant(23)(14); --  Grant(10,14)
+Grant(150)  <= Signal_grant(9)(15) or Signal_grant(24)(15); --  Grant(10,15)
+Grant(151)  <= Signal_grant(11)(1) or Signal_grant(26)(1); --  Grant(11,1)
+Grant(152)  <= Signal_grant(12)(2) or Signal_grant(27)(2); --  Grant(11,2)
+Grant(153)  <= Signal_grant(13)(3) or Signal_grant(28)(3); --  Grant(11,3)
+Grant(154)  <= Signal_grant(14)(4) or Signal_grant(29)(4); --  Grant(11,4)
+Grant(155)  <= Signal_grant(15)(5) ;                      --  Grant(11,5)
+Grant(156)  <= Signal_grant(1)(6) or Signal_grant(16)(6); --  Grant(11,6)
+Grant(157)  <= Signal_grant(2)(7) or Signal_grant(17)(7); --  Grant(11,7)
+Grant(158)  <= Signal_grant(3)(8) or Signal_grant(18)(8); --  Grant(11,8)
+Grant(159)  <= Signal_grant(4)(9) or Signal_grant(19)(9); --  Grant(11,9)
+Grant(160)  <= Signal_grant(5)(10) or Signal_grant(20)(10); --  Grant(11,10)
+Grant(161)  <= Signal_grant(6)(11) or Signal_grant(21)(11); --  Grant(11,11)
+Grant(162)  <= Signal_grant(7)(12) or Signal_grant(22)(12); --  Grant(11,12)
+Grant(163)  <= Signal_grant(8)(13) or Signal_grant(23)(13); --  Grant(11,13)
+Grant(164)  <= Signal_grant(9)(14) or Signal_grant(24)(14); --  Grant(11,14)
+Grant(165)  <= Signal_grant(10)(15) or Signal_grant(25)(15); --  Grant(11,15)
+Grant(166)  <= Signal_grant(12)(1) or Signal_grant(27)(1); --  Grant(12,1)
+Grant(167)  <= Signal_grant(13)(2) or Signal_grant(28)(2); --  Grant(12,2)
+Grant(168)  <= Signal_grant(14)(3) or Signal_grant(29)(3); --  Grant(12,3)
+Grant(169)  <= Signal_grant(15)(4) ;                      --  Grant(12,4)
+Grant(170)  <= Signal_grant(1)(5) or Signal_grant(16)(5); --  Grant(12,5)
+Grant(171)  <= Signal_grant(2)(6) or Signal_grant(17)(6); --  Grant(12,6)
+Grant(172)  <= Signal_grant(3)(7) or Signal_grant(18)(7); --  Grant(12,7)
+Grant(173)  <= Signal_grant(4)(8) or Signal_grant(19)(8); --  Grant(12,8)
+Grant(174)  <= Signal_grant(5)(9) or Signal_grant(20)(9); --  Grant(12,9)
+Grant(175)  <= Signal_grant(6)(10) or Signal_grant(21)(10); --  Grant(12,10)
+Grant(176)  <= Signal_grant(7)(11) or Signal_grant(22)(11); --  Grant(12,11)
+Grant(177)  <= Signal_grant(8)(12) or Signal_grant(23)(12); --  Grant(12,12)
+Grant(178)  <= Signal_grant(9)(13) or Signal_grant(24)(13); --  Grant(12,13)
+Grant(179)  <= Signal_grant(10)(14) or Signal_grant(25)(14); --  Grant(12,14)
+Grant(180)  <= Signal_grant(11)(15) or Signal_grant(26)(15); --  Grant(12,15)
+Grant(181)  <= Signal_grant(13)(1) or Signal_grant(28)(1); --  Grant(13,1)
+Grant(182)  <= Signal_grant(14)(2) or Signal_grant(29)(2); --  Grant(13,2)
+Grant(183)  <= Signal_grant(15)(3) ;                      --  Grant(13,3)
+Grant(184)  <= Signal_grant(1)(4) or Signal_grant(16)(4); --  Grant(13,4)
+Grant(185)  <= Signal_grant(2)(5) or Signal_grant(17)(5); --  Grant(13,5)
+Grant(186)  <= Signal_grant(3)(6) or Signal_grant(18)(6); --  Grant(13,6)
+Grant(187)  <= Signal_grant(4)(7) or Signal_grant(19)(7); --  Grant(13,7)
+Grant(188)  <= Signal_grant(5)(8) or Signal_grant(20)(8); --  Grant(13,8)
+Grant(189)  <= Signal_grant(6)(9) or Signal_grant(21)(9); --  Grant(13,9)
+Grant(190)  <= Signal_grant(7)(10) or Signal_grant(22)(10); --  Grant(13,10)
+Grant(191)  <= Signal_grant(8)(11) or Signal_grant(23)(11); --  Grant(13,11)
+Grant(192)  <= Signal_grant(9)(12) or Signal_grant(24)(12); --  Grant(13,12)
+Grant(193)  <= Signal_grant(10)(13) or Signal_grant(25)(13); --  Grant(13,13)
+Grant(194)  <= Signal_grant(11)(14) or Signal_grant(26)(14); --  Grant(13,14)
+Grant(195)  <= Signal_grant(12)(15) or Signal_grant(27)(15); --  Grant(13,15)
+Grant(196)  <= Signal_grant(14)(1) or Signal_grant(29)(1); --  Grant(14,1)
+Grant(197)  <= Signal_grant(15)(2) ;                      --  Grant(14,2)
+Grant(198)  <= Signal_grant(1)(3) or Signal_grant(16)(3); --  Grant(14,3)
+Grant(199)  <= Signal_grant(2)(4) or Signal_grant(17)(4); --  Grant(14,4)
+Grant(200)  <= Signal_grant(3)(5) or Signal_grant(18)(5); --  Grant(14,5)
+Grant(201)  <= Signal_grant(4)(6) or Signal_grant(19)(6); --  Grant(14,6)
+Grant(202)  <= Signal_grant(5)(7) or Signal_grant(20)(7); --  Grant(14,7)
+Grant(203)  <= Signal_grant(6)(8) or Signal_grant(21)(8); --  Grant(14,8)
+Grant(204)  <= Signal_grant(7)(9) or Signal_grant(22)(9); --  Grant(14,9)
+Grant(205)  <= Signal_grant(8)(10) or Signal_grant(23)(10); --  Grant(14,10)
+Grant(206)  <= Signal_grant(9)(11) or Signal_grant(24)(11); --  Grant(14,11)
+Grant(207)  <= Signal_grant(10)(12) or Signal_grant(25)(12); --  Grant(14,12)
+Grant(208)  <= Signal_grant(11)(13) or Signal_grant(26)(13); --  Grant(14,13)
+Grant(209)  <= Signal_grant(12)(14) or Signal_grant(27)(14); --  Grant(14,14)
+Grant(210)  <= Signal_grant(13)(15) or Signal_grant(28)(15); --  Grant(14,15)
+Grant(211)  <= Signal_grant(15)(1) ;                      --  Grant(15,1)
+Grant(212)  <= Signal_grant(1)(2) or Signal_grant(16)(2); --  Grant(15,2)
+Grant(213)  <= Signal_grant(2)(3) or Signal_grant(17)(3); --  Grant(15,3)
+Grant(214)  <= Signal_grant(3)(4) or Signal_grant(18)(4); --  Grant(15,4)
+Grant(215)  <= Signal_grant(4)(5) or Signal_grant(19)(5); --  Grant(15,5)
+Grant(216)  <= Signal_grant(5)(6) or Signal_grant(20)(6); --  Grant(15,6)
+Grant(217)  <= Signal_grant(6)(7) or Signal_grant(21)(7); --  Grant(15,7)
+Grant(218)  <= Signal_grant(7)(8) or Signal_grant(22)(8); --  Grant(15,8)
+Grant(219)  <= Signal_grant(8)(9) or Signal_grant(23)(9); --  Grant(15,9)
+Grant(220)  <= Signal_grant(9)(10) or Signal_grant(24)(10); --  Grant(15,10)
+Grant(221)  <= Signal_grant(10)(11) or Signal_grant(25)(11); --  Grant(15,11)
+Grant(222)  <= Signal_grant(11)(12) or Signal_grant(26)(12); --  Grant(15,12)
+Grant(223)  <= Signal_grant(12)(13) or Signal_grant(27)(13); --  Grant(15,13)
+Grant(224)  <= Signal_grant(13)(14) or Signal_grant(28)(14); --  Grant(15,14)
+Grant(225)  <= Signal_grant(14)(15) or Signal_grant(29)(15); --  Grant(15,15)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(212), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(198), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(184), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(170), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(156), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(142), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(128), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(114), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+Arbiter_1_10 : Arbiter
+
+PORT MAP (Request => Request(100), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(10),  
+South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); 
+
+Arbiter_1_11 : Arbiter
+
+PORT MAP (Request => Request(86), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(11),  
+South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); 
+
+Arbiter_1_12 : Arbiter
+
+PORT MAP (Request => Request(72), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(12),  
+South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); 
+
+Arbiter_1_13 : Arbiter
+
+PORT MAP (Request => Request(58), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(13),  
+South => south_2_north(1)(13), East => east_2_west(1)(13) , Grant => Signal_grant(1)(13)); 
+
+Arbiter_1_14 : Arbiter
+
+PORT MAP (Request => Request(44), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(14),  
+South => south_2_north(1)(14), East => east_2_west(1)(14) , Grant => Signal_grant(1)(14)); 
+
+Arbiter_1_15 : Arbiter
+
+PORT MAP (Request => Request(30), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(15),  
+South => south_2_north(1)(15), East => east_2_west(1)(15) , Grant => Signal_grant(1)(15)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(1)(1), West => east_2_west(1)(15), P => Signal_priority(28), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(28), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(213), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(28), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(199), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(28), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(185), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(28), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(171), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(28), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(157), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(28), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(28), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(28), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+Arbiter_2_10 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(28), Fifo_full => Fifo_full(10),  
+South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); 
+
+Arbiter_2_11 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(28), Fifo_full => Fifo_full(11),  
+South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); 
+
+Arbiter_2_12 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(28), Fifo_full => Fifo_full(12),  
+South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); 
+
+Arbiter_2_13 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(1)(13), West => east_2_west(1)(12), P => Signal_priority(28), Fifo_full => Fifo_full(13),  
+South => south_2_north(2)(13), East => east_2_west(2)(13) , Grant => Signal_grant(2)(13)); 
+
+Arbiter_2_14 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(1)(14), West => east_2_west(1)(13), P => Signal_priority(28), Fifo_full => Fifo_full(14),  
+South => south_2_north(2)(14), East => east_2_west(2)(14) , Grant => Signal_grant(2)(14)); 
+
+Arbiter_2_15 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(1)(15), West => east_2_west(1)(14), P => Signal_priority(28), Fifo_full => Fifo_full(15),  
+South => south_2_north(2)(15), East => east_2_west(2)(15) , Grant => Signal_grant(2)(15)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(2)(1), West => east_2_west(2)(15), P => Signal_priority(27), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(27), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(27), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(214), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(27), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(200), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(27), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(186), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(27), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(172), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(27), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(158), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(27), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(27), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+Arbiter_3_10 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(27), Fifo_full => Fifo_full(10),  
+South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); 
+
+Arbiter_3_11 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(27), Fifo_full => Fifo_full(11),  
+South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); 
+
+Arbiter_3_12 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(27), Fifo_full => Fifo_full(12),  
+South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); 
+
+Arbiter_3_13 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(2)(13), West => east_2_west(2)(12), P => Signal_priority(27), Fifo_full => Fifo_full(13),  
+South => south_2_north(3)(13), East => east_2_west(3)(13) , Grant => Signal_grant(3)(13)); 
+
+Arbiter_3_14 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(2)(14), West => east_2_west(2)(13), P => Signal_priority(27), Fifo_full => Fifo_full(14),  
+South => south_2_north(3)(14), East => east_2_west(3)(14) , Grant => Signal_grant(3)(14)); 
+
+Arbiter_3_15 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(2)(15), West => east_2_west(2)(14), P => Signal_priority(27), Fifo_full => Fifo_full(15),  
+South => south_2_north(3)(15), East => east_2_west(3)(15) , Grant => Signal_grant(3)(15)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(3)(1), West => east_2_west(3)(15), P => Signal_priority(26), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(26), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(26), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(26), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(215), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(26), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(201), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(26), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(187), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(26), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(173), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(26), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(26), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+Arbiter_4_10 : Arbiter
+
+PORT MAP (Request => Request(145), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(26), Fifo_full => Fifo_full(10),  
+South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); 
+
+Arbiter_4_11 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(26), Fifo_full => Fifo_full(11),  
+South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); 
+
+Arbiter_4_12 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(26), Fifo_full => Fifo_full(12),  
+South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); 
+
+Arbiter_4_13 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(3)(13), West => east_2_west(3)(12), P => Signal_priority(26), Fifo_full => Fifo_full(13),  
+South => south_2_north(4)(13), East => east_2_west(4)(13) , Grant => Signal_grant(4)(13)); 
+
+Arbiter_4_14 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(3)(14), West => east_2_west(3)(13), P => Signal_priority(26), Fifo_full => Fifo_full(14),  
+South => south_2_north(4)(14), East => east_2_west(4)(14) , Grant => Signal_grant(4)(14)); 
+
+Arbiter_4_15 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(3)(15), West => east_2_west(3)(14), P => Signal_priority(26), Fifo_full => Fifo_full(15),  
+South => south_2_north(4)(15), East => east_2_west(4)(15) , Grant => Signal_grant(4)(15)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(4)(1), West => east_2_west(4)(15), P => Signal_priority(25), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(25), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(25), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(25), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(25), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(216), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(25), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(202), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(25), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(188), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(25), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(174), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(25), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+Arbiter_5_10 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(25), Fifo_full => Fifo_full(10),  
+South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); 
+
+Arbiter_5_11 : Arbiter
+
+PORT MAP (Request => Request(146), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(25), Fifo_full => Fifo_full(11),  
+South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); 
+
+Arbiter_5_12 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(25), Fifo_full => Fifo_full(12),  
+South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); 
+
+Arbiter_5_13 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(4)(13), West => east_2_west(4)(12), P => Signal_priority(25), Fifo_full => Fifo_full(13),  
+South => south_2_north(5)(13), East => east_2_west(5)(13) , Grant => Signal_grant(5)(13)); 
+
+Arbiter_5_14 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(4)(14), West => east_2_west(4)(13), P => Signal_priority(25), Fifo_full => Fifo_full(14),  
+South => south_2_north(5)(14), East => east_2_west(5)(14) , Grant => Signal_grant(5)(14)); 
+
+Arbiter_5_15 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(4)(15), West => east_2_west(4)(14), P => Signal_priority(25), Fifo_full => Fifo_full(15),  
+South => south_2_north(5)(15), East => east_2_west(5)(15) , Grant => Signal_grant(5)(15)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(5)(1), West => east_2_west(5)(15), P => Signal_priority(24), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(24), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(24), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(24), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(24), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(24), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(217), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(24), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(203), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(24), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(189), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(24), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+Arbiter_6_10 : Arbiter
+
+PORT MAP (Request => Request(175), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(24), Fifo_full => Fifo_full(10),  
+South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); 
+
+Arbiter_6_11 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(24), Fifo_full => Fifo_full(11),  
+South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); 
+
+Arbiter_6_12 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(24), Fifo_full => Fifo_full(12),  
+South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); 
+
+Arbiter_6_13 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(5)(13), West => east_2_west(5)(12), P => Signal_priority(24), Fifo_full => Fifo_full(13),  
+South => south_2_north(6)(13), East => east_2_west(6)(13) , Grant => Signal_grant(6)(13)); 
+
+Arbiter_6_14 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(5)(14), West => east_2_west(5)(13), P => Signal_priority(24), Fifo_full => Fifo_full(14),  
+South => south_2_north(6)(14), East => east_2_west(6)(14) , Grant => Signal_grant(6)(14)); 
+
+Arbiter_6_15 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(5)(15), West => east_2_west(5)(14), P => Signal_priority(24), Fifo_full => Fifo_full(15),  
+South => south_2_north(6)(15), East => east_2_west(6)(15) , Grant => Signal_grant(6)(15)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(6)(1), West => east_2_west(6)(15), P => Signal_priority(23), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(23), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(23), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(23), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(23), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(23), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(23), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(218), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(23), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(204), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(23), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+Arbiter_7_10 : Arbiter
+
+PORT MAP (Request => Request(190), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(23), Fifo_full => Fifo_full(10),  
+South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); 
+
+Arbiter_7_11 : Arbiter
+
+PORT MAP (Request => Request(176), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(23), Fifo_full => Fifo_full(11),  
+South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); 
+
+Arbiter_7_12 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(23), Fifo_full => Fifo_full(12),  
+South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); 
+
+Arbiter_7_13 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(6)(13), West => east_2_west(6)(12), P => Signal_priority(23), Fifo_full => Fifo_full(13),  
+South => south_2_north(7)(13), East => east_2_west(7)(13) , Grant => Signal_grant(7)(13)); 
+
+Arbiter_7_14 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(6)(14), West => east_2_west(6)(13), P => Signal_priority(23), Fifo_full => Fifo_full(14),  
+South => south_2_north(7)(14), East => east_2_west(7)(14) , Grant => Signal_grant(7)(14)); 
+
+Arbiter_7_15 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(6)(15), West => east_2_west(6)(14), P => Signal_priority(23), Fifo_full => Fifo_full(15),  
+South => south_2_north(7)(15), East => east_2_west(7)(15) , Grant => Signal_grant(7)(15)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(7)(1), West => east_2_west(7)(15), P => Signal_priority(22), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(219), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+Arbiter_8_10 : Arbiter
+
+PORT MAP (Request => Request(205), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10),  
+South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); 
+
+Arbiter_8_11 : Arbiter
+
+PORT MAP (Request => Request(191), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11),  
+South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); 
+
+Arbiter_8_12 : Arbiter
+
+PORT MAP (Request => Request(177), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12),  
+South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); 
+
+Arbiter_8_13 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(7)(13), West => east_2_west(7)(12), P => Signal_priority(22), Fifo_full => Fifo_full(13),  
+South => south_2_north(8)(13), East => east_2_west(8)(13) , Grant => Signal_grant(8)(13)); 
+
+Arbiter_8_14 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(7)(14), West => east_2_west(7)(13), P => Signal_priority(22), Fifo_full => Fifo_full(14),  
+South => south_2_north(8)(14), East => east_2_west(8)(14) , Grant => Signal_grant(8)(14)); 
+
+Arbiter_8_15 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(7)(15), West => east_2_west(7)(14), P => Signal_priority(22), Fifo_full => Fifo_full(15),  
+South => south_2_north(8)(15), East => east_2_west(8)(15) , Grant => Signal_grant(8)(15)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(8)(1), West => east_2_west(8)(15), P => Signal_priority(21), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+Arbiter_9_10 : Arbiter
+
+PORT MAP (Request => Request(220), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10),  
+South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); 
+
+Arbiter_9_11 : Arbiter
+
+PORT MAP (Request => Request(206), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11),  
+South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); 
+
+Arbiter_9_12 : Arbiter
+
+PORT MAP (Request => Request(192), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12),  
+South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); 
+
+Arbiter_9_13 : Arbiter
+
+PORT MAP (Request => Request(178), North => south_2_north(8)(13), West => east_2_west(8)(12), P => Signal_priority(21), Fifo_full => Fifo_full(13),  
+South => south_2_north(9)(13), East => east_2_west(9)(13) , Grant => Signal_grant(9)(13)); 
+
+Arbiter_9_14 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(8)(14), West => east_2_west(8)(13), P => Signal_priority(21), Fifo_full => Fifo_full(14),  
+South => south_2_north(9)(14), East => east_2_west(9)(14) , Grant => Signal_grant(9)(14)); 
+
+Arbiter_9_15 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(8)(15), West => east_2_west(8)(14), P => Signal_priority(21), Fifo_full => Fifo_full(15),  
+South => south_2_north(9)(15), East => east_2_west(9)(15) , Grant => Signal_grant(9)(15)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(9)(1), West => east_2_west(9)(15), P => Signal_priority(20), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(122), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+Arbiter_10_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10),  
+South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); 
+
+Arbiter_10_11 : Arbiter
+
+PORT MAP (Request => Request(221), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11),  
+South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); 
+
+Arbiter_10_12 : Arbiter
+
+PORT MAP (Request => Request(207), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12),  
+South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); 
+
+Arbiter_10_13 : Arbiter
+
+PORT MAP (Request => Request(193), North => south_2_north(9)(13), West => east_2_west(9)(12), P => Signal_priority(20), Fifo_full => Fifo_full(13),  
+South => south_2_north(10)(13), East => east_2_west(10)(13) , Grant => Signal_grant(10)(13)); 
+
+Arbiter_10_14 : Arbiter
+
+PORT MAP (Request => Request(179), North => south_2_north(9)(14), West => east_2_west(9)(13), P => Signal_priority(20), Fifo_full => Fifo_full(14),  
+South => south_2_north(10)(14), East => east_2_west(10)(14) , Grant => Signal_grant(10)(14)); 
+
+Arbiter_10_15 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(9)(15), West => east_2_west(9)(14), P => Signal_priority(20), Fifo_full => Fifo_full(15),  
+South => south_2_north(10)(15), East => east_2_west(10)(15) , Grant => Signal_grant(10)(15)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(151), North => south_2_north(10)(1), West => east_2_west(10)(15), P => Signal_priority(19), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+Arbiter_11_10 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10),  
+South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); 
+
+Arbiter_11_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11),  
+South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); 
+
+Arbiter_11_12 : Arbiter
+
+PORT MAP (Request => Request(222), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12),  
+South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); 
+
+Arbiter_11_13 : Arbiter
+
+PORT MAP (Request => Request(208), North => south_2_north(10)(13), West => east_2_west(10)(12), P => Signal_priority(19), Fifo_full => Fifo_full(13),  
+South => south_2_north(11)(13), East => east_2_west(11)(13) , Grant => Signal_grant(11)(13)); 
+
+Arbiter_11_14 : Arbiter
+
+PORT MAP (Request => Request(194), North => south_2_north(10)(14), West => east_2_west(10)(13), P => Signal_priority(19), Fifo_full => Fifo_full(14),  
+South => south_2_north(11)(14), East => east_2_west(11)(14) , Grant => Signal_grant(11)(14)); 
+
+Arbiter_11_15 : Arbiter
+
+PORT MAP (Request => Request(180), North => south_2_north(10)(15), West => east_2_west(10)(14), P => Signal_priority(19), Fifo_full => Fifo_full(15),  
+South => south_2_north(11)(15), East => east_2_west(11)(15) , Grant => Signal_grant(11)(15)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(166), North => south_2_north(11)(1), West => east_2_west(11)(15), P => Signal_priority(18), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(152), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+Arbiter_12_10 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10),  
+South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); 
+
+Arbiter_12_11 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11),  
+South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); 
+
+Arbiter_12_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12),  
+South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); 
+
+Arbiter_12_13 : Arbiter
+
+PORT MAP (Request => Request(223), North => south_2_north(11)(13), West => east_2_west(11)(12), P => Signal_priority(18), Fifo_full => Fifo_full(13),  
+South => south_2_north(12)(13), East => east_2_west(12)(13) , Grant => Signal_grant(12)(13)); 
+
+Arbiter_12_14 : Arbiter
+
+PORT MAP (Request => Request(209), North => south_2_north(11)(14), West => east_2_west(11)(13), P => Signal_priority(18), Fifo_full => Fifo_full(14),  
+South => south_2_north(12)(14), East => east_2_west(12)(14) , Grant => Signal_grant(12)(14)); 
+
+Arbiter_12_15 : Arbiter
+
+PORT MAP (Request => Request(195), North => south_2_north(11)(15), West => east_2_west(11)(14), P => Signal_priority(18), Fifo_full => Fifo_full(15),  
+South => south_2_north(12)(15), East => east_2_west(12)(15) , Grant => Signal_grant(12)(15)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(181), North => south_2_north(12)(1), West => east_2_west(12)(15), P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(167), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+Arbiter_13_10 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10),  
+South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); 
+
+Arbiter_13_11 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11),  
+South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); 
+
+Arbiter_13_12 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12),  
+South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); 
+
+Arbiter_13_13 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(12)(13), West => east_2_west(12)(12), P => Signal_priority(17), Fifo_full => Fifo_full(13),  
+South => south_2_north(13)(13), East => east_2_west(13)(13) , Grant => Signal_grant(13)(13)); 
+
+Arbiter_13_14 : Arbiter
+
+PORT MAP (Request => Request(224), North => south_2_north(12)(14), West => east_2_west(12)(13), P => Signal_priority(17), Fifo_full => Fifo_full(14),  
+South => south_2_north(13)(14), East => east_2_west(13)(14) , Grant => Signal_grant(13)(14)); 
+
+Arbiter_13_15 : Arbiter
+
+PORT MAP (Request => Request(210), North => south_2_north(12)(15), West => east_2_west(12)(14), P => Signal_priority(17), Fifo_full => Fifo_full(15),  
+South => south_2_north(13)(15), East => east_2_west(13)(15) , Grant => Signal_grant(13)(15)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(196), North => south_2_north(13)(1), West => east_2_west(13)(15), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(182), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+Arbiter_14_10 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10),  
+South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); 
+
+Arbiter_14_11 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11),  
+South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); 
+
+Arbiter_14_12 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12),  
+South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); 
+
+Arbiter_14_13 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(13)(13), West => east_2_west(13)(12), P => Signal_priority(16), Fifo_full => Fifo_full(13),  
+South => south_2_north(14)(13), East => east_2_west(14)(13) , Grant => Signal_grant(14)(13)); 
+
+Arbiter_14_14 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(13)(14), West => east_2_west(13)(13), P => Signal_priority(16), Fifo_full => Fifo_full(14),  
+South => south_2_north(14)(14), East => east_2_west(14)(14) , Grant => Signal_grant(14)(14)); 
+
+Arbiter_14_15 : Arbiter
+
+PORT MAP (Request => Request(225), North => south_2_north(13)(15), West => east_2_west(13)(14), P => Signal_priority(16), Fifo_full => Fifo_full(15),  
+South => south_2_north(14)(15), East => east_2_west(14)(15) , Grant => Signal_grant(14)(15)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(211), North => south_2_north(14)(1), West => east_2_west(14)(15), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(197), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(183), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(169), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(155), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+Arbiter_15_10 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10),  
+South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); 
+
+Arbiter_15_11 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11),  
+South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); 
+
+Arbiter_15_12 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12),  
+South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); 
+
+Arbiter_15_13 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(14)(13), West => east_2_west(14)(12), P => Signal_priority(15), Fifo_full => Fifo_full(13),  
+South => south_2_north(15)(13), East => east_2_west(15)(13) , Grant => Signal_grant(15)(13)); 
+
+Arbiter_15_14 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(14)(14), West => east_2_west(14)(13), P => Signal_priority(15), Fifo_full => Fifo_full(14),  
+South => south_2_north(15)(14), East => east_2_west(15)(14) , Grant => Signal_grant(15)(14)); 
+
+Arbiter_15_15 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(14)(15), West => east_2_west(14)(14), P => Signal_priority(15), Fifo_full => Fifo_full(15),  
+South => south_2_north(15)(15), East => east_2_west(15)(15) , Grant => Signal_grant(15)(15)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(15)(1), West => east_2_west(15)(15), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(212), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(198), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(184), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(170), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(156), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+Arbiter_16_10 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10),  
+South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); 
+
+Arbiter_16_11 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11),  
+South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); 
+
+Arbiter_16_12 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12),  
+South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); 
+
+Arbiter_16_13 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(15)(13), West => east_2_west(15)(12), P => Signal_priority(14), Fifo_full => Fifo_full(13),  
+South => south_2_north(16)(13), East => east_2_west(16)(13) , Grant => Signal_grant(16)(13)); 
+
+Arbiter_16_14 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(15)(14), West => east_2_west(15)(13), P => Signal_priority(14), Fifo_full => Fifo_full(14),  
+South => south_2_north(16)(14), East => east_2_west(16)(14) , Grant => Signal_grant(16)(14)); 
+
+Arbiter_16_15 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(15)(15), West => east_2_west(15)(14), P => Signal_priority(14), Fifo_full => Fifo_full(15),  
+South => south_2_north(16)(15), East => east_2_west(16)(15) , Grant => Signal_grant(16)(15)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(16)(1), West => east_2_west(16)(15), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(213), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(199), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(185), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(171), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(157), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+Arbiter_17_10 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10),  
+South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); 
+
+Arbiter_17_11 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11),  
+South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); 
+
+Arbiter_17_12 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12),  
+South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); 
+
+Arbiter_17_13 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(16)(13), West => east_2_west(16)(12), P => Signal_priority(13), Fifo_full => Fifo_full(13),  
+South => south_2_north(17)(13), East => east_2_west(17)(13) , Grant => Signal_grant(17)(13)); 
+
+Arbiter_17_14 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(16)(14), West => east_2_west(16)(13), P => Signal_priority(13), Fifo_full => Fifo_full(14),  
+South => south_2_north(17)(14), East => east_2_west(17)(14) , Grant => Signal_grant(17)(14)); 
+
+Arbiter_17_15 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(16)(15), West => east_2_west(16)(14), P => Signal_priority(13), Fifo_full => Fifo_full(15),  
+South => south_2_north(17)(15), East => east_2_west(17)(15) , Grant => Signal_grant(17)(15)); 
+
+-------------------------- Diagonale n° 18 
+
+
+Arbiter_18_1 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(17)(1), West => east_2_west(17)(15), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); 
+
+Arbiter_18_2 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); 
+
+Arbiter_18_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); 
+
+Arbiter_18_4 : Arbiter
+
+PORT MAP (Request => Request(214), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); 
+
+Arbiter_18_5 : Arbiter
+
+PORT MAP (Request => Request(200), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); 
+
+Arbiter_18_6 : Arbiter
+
+PORT MAP (Request => Request(186), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); 
+
+Arbiter_18_7 : Arbiter
+
+PORT MAP (Request => Request(172), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); 
+
+Arbiter_18_8 : Arbiter
+
+PORT MAP (Request => Request(158), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); 
+
+Arbiter_18_9 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); 
+
+Arbiter_18_10 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10),  
+South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); 
+
+Arbiter_18_11 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11),  
+South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); 
+
+Arbiter_18_12 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12),  
+South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); 
+
+Arbiter_18_13 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(17)(13), West => east_2_west(17)(12), P => Signal_priority(12), Fifo_full => Fifo_full(13),  
+South => south_2_north(18)(13), East => east_2_west(18)(13) , Grant => Signal_grant(18)(13)); 
+
+Arbiter_18_14 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(17)(14), West => east_2_west(17)(13), P => Signal_priority(12), Fifo_full => Fifo_full(14),  
+South => south_2_north(18)(14), East => east_2_west(18)(14) , Grant => Signal_grant(18)(14)); 
+
+Arbiter_18_15 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(17)(15), West => east_2_west(17)(14), P => Signal_priority(12), Fifo_full => Fifo_full(15),  
+South => south_2_north(18)(15), East => east_2_west(18)(15) , Grant => Signal_grant(18)(15)); 
+
+-------------------------- Diagonale n° 19 
+
+
+Arbiter_19_1 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(18)(1), West => east_2_west(18)(15), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); 
+
+Arbiter_19_2 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); 
+
+Arbiter_19_3 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); 
+
+Arbiter_19_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); 
+
+Arbiter_19_5 : Arbiter
+
+PORT MAP (Request => Request(215), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); 
+
+Arbiter_19_6 : Arbiter
+
+PORT MAP (Request => Request(201), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); 
+
+Arbiter_19_7 : Arbiter
+
+PORT MAP (Request => Request(187), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); 
+
+Arbiter_19_8 : Arbiter
+
+PORT MAP (Request => Request(173), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); 
+
+Arbiter_19_9 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); 
+
+Arbiter_19_10 : Arbiter
+
+PORT MAP (Request => Request(145), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10),  
+South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); 
+
+Arbiter_19_11 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11),  
+South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); 
+
+Arbiter_19_12 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12),  
+South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); 
+
+Arbiter_19_13 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(18)(13), West => east_2_west(18)(12), P => Signal_priority(11), Fifo_full => Fifo_full(13),  
+South => south_2_north(19)(13), East => east_2_west(19)(13) , Grant => Signal_grant(19)(13)); 
+
+Arbiter_19_14 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(18)(14), West => east_2_west(18)(13), P => Signal_priority(11), Fifo_full => Fifo_full(14),  
+South => south_2_north(19)(14), East => east_2_west(19)(14) , Grant => Signal_grant(19)(14)); 
+
+Arbiter_19_15 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(18)(15), West => east_2_west(18)(14), P => Signal_priority(11), Fifo_full => Fifo_full(15),  
+South => south_2_north(19)(15), East => east_2_west(19)(15) , Grant => Signal_grant(19)(15)); 
+
+-------------------------- Diagonale n° 20 
+
+
+Arbiter_20_1 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(19)(1), West => east_2_west(19)(15), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); 
+
+Arbiter_20_2 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); 
+
+Arbiter_20_3 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); 
+
+Arbiter_20_4 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); 
+
+Arbiter_20_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); 
+
+Arbiter_20_6 : Arbiter
+
+PORT MAP (Request => Request(216), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); 
+
+Arbiter_20_7 : Arbiter
+
+PORT MAP (Request => Request(202), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); 
+
+Arbiter_20_8 : Arbiter
+
+PORT MAP (Request => Request(188), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); 
+
+Arbiter_20_9 : Arbiter
+
+PORT MAP (Request => Request(174), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); 
+
+Arbiter_20_10 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10),  
+South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); 
+
+Arbiter_20_11 : Arbiter
+
+PORT MAP (Request => Request(146), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11),  
+South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); 
+
+Arbiter_20_12 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12),  
+South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); 
+
+Arbiter_20_13 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(19)(13), West => east_2_west(19)(12), P => Signal_priority(10), Fifo_full => Fifo_full(13),  
+South => south_2_north(20)(13), East => east_2_west(20)(13) , Grant => Signal_grant(20)(13)); 
+
+Arbiter_20_14 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(19)(14), West => east_2_west(19)(13), P => Signal_priority(10), Fifo_full => Fifo_full(14),  
+South => south_2_north(20)(14), East => east_2_west(20)(14) , Grant => Signal_grant(20)(14)); 
+
+Arbiter_20_15 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(19)(15), West => east_2_west(19)(14), P => Signal_priority(10), Fifo_full => Fifo_full(15),  
+South => south_2_north(20)(15), East => east_2_west(20)(15) , Grant => Signal_grant(20)(15)); 
+
+-------------------------- Diagonale n° 21 
+
+
+Arbiter_21_1 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(20)(1), West => east_2_west(20)(15), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); 
+
+Arbiter_21_2 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); 
+
+Arbiter_21_3 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); 
+
+Arbiter_21_4 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); 
+
+Arbiter_21_5 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); 
+
+Arbiter_21_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); 
+
+Arbiter_21_7 : Arbiter
+
+PORT MAP (Request => Request(217), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); 
+
+Arbiter_21_8 : Arbiter
+
+PORT MAP (Request => Request(203), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); 
+
+Arbiter_21_9 : Arbiter
+
+PORT MAP (Request => Request(189), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); 
+
+Arbiter_21_10 : Arbiter
+
+PORT MAP (Request => Request(175), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10),  
+South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); 
+
+Arbiter_21_11 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11),  
+South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); 
+
+Arbiter_21_12 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12),  
+South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); 
+
+Arbiter_21_13 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(20)(13), West => east_2_west(20)(12), P => Signal_priority(9), Fifo_full => Fifo_full(13),  
+South => south_2_north(21)(13), East => east_2_west(21)(13) , Grant => Signal_grant(21)(13)); 
+
+Arbiter_21_14 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(20)(14), West => east_2_west(20)(13), P => Signal_priority(9), Fifo_full => Fifo_full(14),  
+South => south_2_north(21)(14), East => east_2_west(21)(14) , Grant => Signal_grant(21)(14)); 
+
+Arbiter_21_15 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(20)(15), West => east_2_west(20)(14), P => Signal_priority(9), Fifo_full => Fifo_full(15),  
+South => south_2_north(21)(15), East => east_2_west(21)(15) , Grant => Signal_grant(21)(15)); 
+
+-------------------------- Diagonale n° 22 
+
+
+Arbiter_22_1 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(21)(1), West => east_2_west(21)(15), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); 
+
+Arbiter_22_2 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); 
+
+Arbiter_22_3 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); 
+
+Arbiter_22_4 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); 
+
+Arbiter_22_5 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); 
+
+Arbiter_22_6 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); 
+
+Arbiter_22_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); 
+
+Arbiter_22_8 : Arbiter
+
+PORT MAP (Request => Request(218), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); 
+
+Arbiter_22_9 : Arbiter
+
+PORT MAP (Request => Request(204), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); 
+
+Arbiter_22_10 : Arbiter
+
+PORT MAP (Request => Request(190), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10),  
+South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); 
+
+Arbiter_22_11 : Arbiter
+
+PORT MAP (Request => Request(176), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11),  
+South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); 
+
+Arbiter_22_12 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12),  
+South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); 
+
+Arbiter_22_13 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(21)(13), West => east_2_west(21)(12), P => Signal_priority(8), Fifo_full => Fifo_full(13),  
+South => south_2_north(22)(13), East => east_2_west(22)(13) , Grant => Signal_grant(22)(13)); 
+
+Arbiter_22_14 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(21)(14), West => east_2_west(21)(13), P => Signal_priority(8), Fifo_full => Fifo_full(14),  
+South => south_2_north(22)(14), East => east_2_west(22)(14) , Grant => Signal_grant(22)(14)); 
+
+Arbiter_22_15 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(21)(15), West => east_2_west(21)(14), P => Signal_priority(8), Fifo_full => Fifo_full(15),  
+South => south_2_north(22)(15), East => east_2_west(22)(15) , Grant => Signal_grant(22)(15)); 
+
+-------------------------- Diagonale n° 23 
+
+
+Arbiter_23_1 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(22)(1), West => east_2_west(22)(15), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); 
+
+Arbiter_23_2 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); 
+
+Arbiter_23_3 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); 
+
+Arbiter_23_4 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); 
+
+Arbiter_23_5 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); 
+
+Arbiter_23_6 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); 
+
+Arbiter_23_7 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); 
+
+Arbiter_23_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); 
+
+Arbiter_23_9 : Arbiter
+
+PORT MAP (Request => Request(219), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); 
+
+Arbiter_23_10 : Arbiter
+
+PORT MAP (Request => Request(205), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10),  
+South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); 
+
+Arbiter_23_11 : Arbiter
+
+PORT MAP (Request => Request(191), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11),  
+South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); 
+
+Arbiter_23_12 : Arbiter
+
+PORT MAP (Request => Request(177), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12),  
+South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); 
+
+Arbiter_23_13 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(22)(13), West => east_2_west(22)(12), P => Signal_priority(7), Fifo_full => Fifo_full(13),  
+South => south_2_north(23)(13), East => east_2_west(23)(13) , Grant => Signal_grant(23)(13)); 
+
+Arbiter_23_14 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(22)(14), West => east_2_west(22)(13), P => Signal_priority(7), Fifo_full => Fifo_full(14),  
+South => south_2_north(23)(14), East => east_2_west(23)(14) , Grant => Signal_grant(23)(14)); 
+
+Arbiter_23_15 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(22)(15), West => east_2_west(22)(14), P => Signal_priority(7), Fifo_full => Fifo_full(15),  
+South => south_2_north(23)(15), East => east_2_west(23)(15) , Grant => Signal_grant(23)(15)); 
+
+-------------------------- Diagonale n° 24 
+
+
+Arbiter_24_1 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(23)(1), West => east_2_west(23)(15), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(24)(1), East => east_2_west(24)(1) , Grant => Signal_grant(24)(1)); 
+
+Arbiter_24_2 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(23)(2), West => east_2_west(23)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(24)(2), East => east_2_west(24)(2) , Grant => Signal_grant(24)(2)); 
+
+Arbiter_24_3 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(23)(3), West => east_2_west(23)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(24)(3), East => east_2_west(24)(3) , Grant => Signal_grant(24)(3)); 
+
+Arbiter_24_4 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(23)(4), West => east_2_west(23)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(24)(4), East => east_2_west(24)(4) , Grant => Signal_grant(24)(4)); 
+
+Arbiter_24_5 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(23)(5), West => east_2_west(23)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(24)(5), East => east_2_west(24)(5) , Grant => Signal_grant(24)(5)); 
+
+Arbiter_24_6 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(23)(6), West => east_2_west(23)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(24)(6), East => east_2_west(24)(6) , Grant => Signal_grant(24)(6)); 
+
+Arbiter_24_7 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(23)(7), West => east_2_west(23)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(24)(7), East => east_2_west(24)(7) , Grant => Signal_grant(24)(7)); 
+
+Arbiter_24_8 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(23)(8), West => east_2_west(23)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(24)(8), East => east_2_west(24)(8) , Grant => Signal_grant(24)(8)); 
+
+Arbiter_24_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(23)(9), West => east_2_west(23)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(24)(9), East => east_2_west(24)(9) , Grant => Signal_grant(24)(9)); 
+
+Arbiter_24_10 : Arbiter
+
+PORT MAP (Request => Request(220), North => south_2_north(23)(10), West => east_2_west(23)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10),  
+South => south_2_north(24)(10), East => east_2_west(24)(10) , Grant => Signal_grant(24)(10)); 
+
+Arbiter_24_11 : Arbiter
+
+PORT MAP (Request => Request(206), North => south_2_north(23)(11), West => east_2_west(23)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11),  
+South => south_2_north(24)(11), East => east_2_west(24)(11) , Grant => Signal_grant(24)(11)); 
+
+Arbiter_24_12 : Arbiter
+
+PORT MAP (Request => Request(192), North => south_2_north(23)(12), West => east_2_west(23)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12),  
+South => south_2_north(24)(12), East => east_2_west(24)(12) , Grant => Signal_grant(24)(12)); 
+
+Arbiter_24_13 : Arbiter
+
+PORT MAP (Request => Request(178), North => south_2_north(23)(13), West => east_2_west(23)(12), P => Signal_priority(6), Fifo_full => Fifo_full(13),  
+South => south_2_north(24)(13), East => east_2_west(24)(13) , Grant => Signal_grant(24)(13)); 
+
+Arbiter_24_14 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(23)(14), West => east_2_west(23)(13), P => Signal_priority(6), Fifo_full => Fifo_full(14),  
+South => south_2_north(24)(14), East => east_2_west(24)(14) , Grant => Signal_grant(24)(14)); 
+
+Arbiter_24_15 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(23)(15), West => east_2_west(23)(14), P => Signal_priority(6), Fifo_full => Fifo_full(15),  
+South => south_2_north(24)(15), East => east_2_west(24)(15) , Grant => Signal_grant(24)(15)); 
+
+-------------------------- Diagonale n° 25 
+
+
+Arbiter_25_1 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(24)(1), West => east_2_west(24)(15), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(25)(1), East => east_2_west(25)(1) , Grant => Signal_grant(25)(1)); 
+
+Arbiter_25_2 : Arbiter
+
+PORT MAP (Request => Request(122), North => south_2_north(24)(2), West => east_2_west(24)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(25)(2), East => east_2_west(25)(2) , Grant => Signal_grant(25)(2)); 
+
+Arbiter_25_3 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(24)(3), West => east_2_west(24)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(25)(3), East => east_2_west(25)(3) , Grant => Signal_grant(25)(3)); 
+
+Arbiter_25_4 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(24)(4), West => east_2_west(24)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(25)(4), East => east_2_west(25)(4) , Grant => Signal_grant(25)(4)); 
+
+Arbiter_25_5 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(24)(5), West => east_2_west(24)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(25)(5), East => east_2_west(25)(5) , Grant => Signal_grant(25)(5)); 
+
+Arbiter_25_6 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(24)(6), West => east_2_west(24)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(25)(6), East => east_2_west(25)(6) , Grant => Signal_grant(25)(6)); 
+
+Arbiter_25_7 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(24)(7), West => east_2_west(24)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(25)(7), East => east_2_west(25)(7) , Grant => Signal_grant(25)(7)); 
+
+Arbiter_25_8 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(24)(8), West => east_2_west(24)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(25)(8), East => east_2_west(25)(8) , Grant => Signal_grant(25)(8)); 
+
+Arbiter_25_9 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(24)(9), West => east_2_west(24)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(25)(9), East => east_2_west(25)(9) , Grant => Signal_grant(25)(9)); 
+
+Arbiter_25_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(24)(10), West => east_2_west(24)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10),  
+South => south_2_north(25)(10), East => east_2_west(25)(10) , Grant => Signal_grant(25)(10)); 
+
+Arbiter_25_11 : Arbiter
+
+PORT MAP (Request => Request(221), North => south_2_north(24)(11), West => east_2_west(24)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11),  
+South => south_2_north(25)(11), East => east_2_west(25)(11) , Grant => Signal_grant(25)(11)); 
+
+Arbiter_25_12 : Arbiter
+
+PORT MAP (Request => Request(207), North => south_2_north(24)(12), West => east_2_west(24)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12),  
+South => south_2_north(25)(12), East => east_2_west(25)(12) , Grant => Signal_grant(25)(12)); 
+
+Arbiter_25_13 : Arbiter
+
+PORT MAP (Request => Request(193), North => south_2_north(24)(13), West => east_2_west(24)(12), P => Signal_priority(5), Fifo_full => Fifo_full(13),  
+South => south_2_north(25)(13), East => east_2_west(25)(13) , Grant => Signal_grant(25)(13)); 
+
+Arbiter_25_14 : Arbiter
+
+PORT MAP (Request => Request(179), North => south_2_north(24)(14), West => east_2_west(24)(13), P => Signal_priority(5), Fifo_full => Fifo_full(14),  
+South => south_2_north(25)(14), East => east_2_west(25)(14) , Grant => Signal_grant(25)(14)); 
+
+Arbiter_25_15 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(24)(15), West => east_2_west(24)(14), P => Signal_priority(5), Fifo_full => Fifo_full(15),  
+South => south_2_north(25)(15), East => east_2_west(25)(15) , Grant => Signal_grant(25)(15)); 
+
+-------------------------- Diagonale n° 26 
+
+
+Arbiter_26_1 : Arbiter
+
+PORT MAP (Request => Request(151), North => south_2_north(25)(1), West => east_2_west(25)(15), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(26)(1), East => east_2_west(26)(1) , Grant => Signal_grant(26)(1)); 
+
+Arbiter_26_2 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(25)(2), West => east_2_west(25)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(26)(2), East => east_2_west(26)(2) , Grant => Signal_grant(26)(2)); 
+
+Arbiter_26_3 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(25)(3), West => east_2_west(25)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(26)(3), East => east_2_west(26)(3) , Grant => Signal_grant(26)(3)); 
+
+Arbiter_26_4 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(25)(4), West => east_2_west(25)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(26)(4), East => east_2_west(26)(4) , Grant => Signal_grant(26)(4)); 
+
+Arbiter_26_5 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(25)(5), West => east_2_west(25)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(26)(5), East => east_2_west(26)(5) , Grant => Signal_grant(26)(5)); 
+
+Arbiter_26_6 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(25)(6), West => east_2_west(25)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(26)(6), East => east_2_west(26)(6) , Grant => Signal_grant(26)(6)); 
+
+Arbiter_26_7 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(25)(7), West => east_2_west(25)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(26)(7), East => east_2_west(26)(7) , Grant => Signal_grant(26)(7)); 
+
+Arbiter_26_8 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(25)(8), West => east_2_west(25)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(26)(8), East => east_2_west(26)(8) , Grant => Signal_grant(26)(8)); 
+
+Arbiter_26_9 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(25)(9), West => east_2_west(25)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(26)(9), East => east_2_west(26)(9) , Grant => Signal_grant(26)(9)); 
+
+Arbiter_26_10 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(25)(10), West => east_2_west(25)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10),  
+South => south_2_north(26)(10), East => east_2_west(26)(10) , Grant => Signal_grant(26)(10)); 
+
+Arbiter_26_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(25)(11), West => east_2_west(25)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11),  
+South => south_2_north(26)(11), East => east_2_west(26)(11) , Grant => Signal_grant(26)(11)); 
+
+Arbiter_26_12 : Arbiter
+
+PORT MAP (Request => Request(222), North => south_2_north(25)(12), West => east_2_west(25)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12),  
+South => south_2_north(26)(12), East => east_2_west(26)(12) , Grant => Signal_grant(26)(12)); 
+
+Arbiter_26_13 : Arbiter
+
+PORT MAP (Request => Request(208), North => south_2_north(25)(13), West => east_2_west(25)(12), P => Signal_priority(4), Fifo_full => Fifo_full(13),  
+South => south_2_north(26)(13), East => east_2_west(26)(13) , Grant => Signal_grant(26)(13)); 
+
+Arbiter_26_14 : Arbiter
+
+PORT MAP (Request => Request(194), North => south_2_north(25)(14), West => east_2_west(25)(13), P => Signal_priority(4), Fifo_full => Fifo_full(14),  
+South => south_2_north(26)(14), East => east_2_west(26)(14) , Grant => Signal_grant(26)(14)); 
+
+Arbiter_26_15 : Arbiter
+
+PORT MAP (Request => Request(180), North => south_2_north(25)(15), West => east_2_west(25)(14), P => Signal_priority(4), Fifo_full => Fifo_full(15),  
+South => south_2_north(26)(15), East => east_2_west(26)(15) , Grant => Signal_grant(26)(15)); 
+
+-------------------------- Diagonale n° 27 
+
+
+Arbiter_27_1 : Arbiter
+
+PORT MAP (Request => Request(166), North => south_2_north(26)(1), West => east_2_west(26)(15), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(27)(1), East => east_2_west(27)(1) , Grant => Signal_grant(27)(1)); 
+
+Arbiter_27_2 : Arbiter
+
+PORT MAP (Request => Request(152), North => south_2_north(26)(2), West => east_2_west(26)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(27)(2), East => east_2_west(27)(2) , Grant => Signal_grant(27)(2)); 
+
+Arbiter_27_3 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(26)(3), West => east_2_west(26)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(27)(3), East => east_2_west(27)(3) , Grant => Signal_grant(27)(3)); 
+
+Arbiter_27_4 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(26)(4), West => east_2_west(26)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(27)(4), East => east_2_west(27)(4) , Grant => Signal_grant(27)(4)); 
+
+Arbiter_27_5 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(26)(5), West => east_2_west(26)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(27)(5), East => east_2_west(27)(5) , Grant => Signal_grant(27)(5)); 
+
+Arbiter_27_6 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(26)(6), West => east_2_west(26)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(27)(6), East => east_2_west(27)(6) , Grant => Signal_grant(27)(6)); 
+
+Arbiter_27_7 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(26)(7), West => east_2_west(26)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(27)(7), East => east_2_west(27)(7) , Grant => Signal_grant(27)(7)); 
+
+Arbiter_27_8 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(26)(8), West => east_2_west(26)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(27)(8), East => east_2_west(27)(8) , Grant => Signal_grant(27)(8)); 
+
+Arbiter_27_9 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(26)(9), West => east_2_west(26)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(27)(9), East => east_2_west(27)(9) , Grant => Signal_grant(27)(9)); 
+
+Arbiter_27_10 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(26)(10), West => east_2_west(26)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10),  
+South => south_2_north(27)(10), East => east_2_west(27)(10) , Grant => Signal_grant(27)(10)); 
+
+Arbiter_27_11 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(26)(11), West => east_2_west(26)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11),  
+South => south_2_north(27)(11), East => east_2_west(27)(11) , Grant => Signal_grant(27)(11)); 
+
+Arbiter_27_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(26)(12), West => east_2_west(26)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12),  
+South => south_2_north(27)(12), East => east_2_west(27)(12) , Grant => Signal_grant(27)(12)); 
+
+Arbiter_27_13 : Arbiter
+
+PORT MAP (Request => Request(223), North => south_2_north(26)(13), West => east_2_west(26)(12), P => Signal_priority(3), Fifo_full => Fifo_full(13),  
+South => south_2_north(27)(13), East => east_2_west(27)(13) , Grant => Signal_grant(27)(13)); 
+
+Arbiter_27_14 : Arbiter
+
+PORT MAP (Request => Request(209), North => south_2_north(26)(14), West => east_2_west(26)(13), P => Signal_priority(3), Fifo_full => Fifo_full(14),  
+South => south_2_north(27)(14), East => east_2_west(27)(14) , Grant => Signal_grant(27)(14)); 
+
+Arbiter_27_15 : Arbiter
+
+PORT MAP (Request => Request(195), North => south_2_north(26)(15), West => east_2_west(26)(14), P => Signal_priority(3), Fifo_full => Fifo_full(15),  
+South => south_2_north(27)(15), East => east_2_west(27)(15) , Grant => Signal_grant(27)(15)); 
+
+-------------------------- Diagonale n° 28 
+
+
+Arbiter_28_1 : Arbiter
+
+PORT MAP (Request => Request(181), North => south_2_north(27)(1), West => east_2_west(27)(15), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(28)(1), East => east_2_west(28)(1) , Grant => Signal_grant(28)(1)); 
+
+Arbiter_28_2 : Arbiter
+
+PORT MAP (Request => Request(167), North => south_2_north(27)(2), West => east_2_west(27)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(28)(2), East => east_2_west(28)(2) , Grant => Signal_grant(28)(2)); 
+
+Arbiter_28_3 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(27)(3), West => east_2_west(27)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(28)(3), East => east_2_west(28)(3) , Grant => Signal_grant(28)(3)); 
+
+Arbiter_28_4 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(27)(4), West => east_2_west(27)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(28)(4), East => east_2_west(28)(4) , Grant => Signal_grant(28)(4)); 
+
+Arbiter_28_5 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(27)(5), West => east_2_west(27)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(28)(5), East => east_2_west(28)(5) , Grant => Signal_grant(28)(5)); 
+
+Arbiter_28_6 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(27)(6), West => east_2_west(27)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(28)(6), East => east_2_west(28)(6) , Grant => Signal_grant(28)(6)); 
+
+Arbiter_28_7 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(27)(7), West => east_2_west(27)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(28)(7), East => east_2_west(28)(7) , Grant => Signal_grant(28)(7)); 
+
+Arbiter_28_8 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(27)(8), West => east_2_west(27)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(28)(8), East => east_2_west(28)(8) , Grant => Signal_grant(28)(8)); 
+
+Arbiter_28_9 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(27)(9), West => east_2_west(27)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(28)(9), East => east_2_west(28)(9) , Grant => Signal_grant(28)(9)); 
+
+Arbiter_28_10 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(27)(10), West => east_2_west(27)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10),  
+South => south_2_north(28)(10), East => east_2_west(28)(10) , Grant => Signal_grant(28)(10)); 
+
+Arbiter_28_11 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(27)(11), West => east_2_west(27)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11),  
+South => south_2_north(28)(11), East => east_2_west(28)(11) , Grant => Signal_grant(28)(11)); 
+
+Arbiter_28_12 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(27)(12), West => east_2_west(27)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12),  
+South => south_2_north(28)(12), East => east_2_west(28)(12) , Grant => Signal_grant(28)(12)); 
+
+Arbiter_28_13 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(27)(13), West => east_2_west(27)(12), P => Signal_priority(2), Fifo_full => Fifo_full(13),  
+South => south_2_north(28)(13), East => east_2_west(28)(13) , Grant => Signal_grant(28)(13)); 
+
+Arbiter_28_14 : Arbiter
+
+PORT MAP (Request => Request(224), North => south_2_north(27)(14), West => east_2_west(27)(13), P => Signal_priority(2), Fifo_full => Fifo_full(14),  
+South => south_2_north(28)(14), East => east_2_west(28)(14) , Grant => Signal_grant(28)(14)); 
+
+Arbiter_28_15 : Arbiter
+
+PORT MAP (Request => Request(210), North => south_2_north(27)(15), West => east_2_west(27)(14), P => Signal_priority(2), Fifo_full => Fifo_full(15),  
+South => south_2_north(28)(15), East => east_2_west(28)(15) , Grant => Signal_grant(28)(15)); 
+
+-------------------------- Diagonale n° 29 
+
+
+Arbiter_29_1 : Arbiter
+
+PORT MAP (Request => Request(196), North => south_2_north(28)(1), West => east_2_west(28)(15), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(29)(1), East => east_2_west(29)(1) , Grant => Signal_grant(29)(1)); 
+
+Arbiter_29_2 : Arbiter
+
+PORT MAP (Request => Request(182), North => south_2_north(28)(2), West => east_2_west(28)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(29)(2), East => east_2_west(29)(2) , Grant => Signal_grant(29)(2)); 
+
+Arbiter_29_3 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(28)(3), West => east_2_west(28)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(29)(3), East => east_2_west(29)(3) , Grant => Signal_grant(29)(3)); 
+
+Arbiter_29_4 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(28)(4), West => east_2_west(28)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(29)(4), East => east_2_west(29)(4) , Grant => Signal_grant(29)(4)); 
+
+Arbiter_29_5 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(28)(5), West => east_2_west(28)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(29)(5), East => east_2_west(29)(5) , Grant => Signal_grant(29)(5)); 
+
+Arbiter_29_6 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(28)(6), West => east_2_west(28)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(29)(6), East => east_2_west(29)(6) , Grant => Signal_grant(29)(6)); 
+
+Arbiter_29_7 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(28)(7), West => east_2_west(28)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(29)(7), East => east_2_west(29)(7) , Grant => Signal_grant(29)(7)); 
+
+Arbiter_29_8 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(28)(8), West => east_2_west(28)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(29)(8), East => east_2_west(29)(8) , Grant => Signal_grant(29)(8)); 
+
+Arbiter_29_9 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(28)(9), West => east_2_west(28)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(29)(9), East => east_2_west(29)(9) , Grant => Signal_grant(29)(9)); 
+
+Arbiter_29_10 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(28)(10), West => east_2_west(28)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10),  
+South => south_2_north(29)(10), East => east_2_west(29)(10) , Grant => Signal_grant(29)(10)); 
+
+Arbiter_29_11 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(28)(11), West => east_2_west(28)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11),  
+South => south_2_north(29)(11), East => east_2_west(29)(11) , Grant => Signal_grant(29)(11)); 
+
+Arbiter_29_12 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(28)(12), West => east_2_west(28)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12),  
+South => south_2_north(29)(12), East => east_2_west(29)(12) , Grant => Signal_grant(29)(12)); 
+
+Arbiter_29_13 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(28)(13), West => east_2_west(28)(12), P => Signal_priority(1), Fifo_full => Fifo_full(13),  
+South => south_2_north(29)(13), East => east_2_west(29)(13) , Grant => Signal_grant(29)(13)); 
+
+Arbiter_29_14 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(28)(14), West => east_2_west(28)(13), P => Signal_priority(1), Fifo_full => Fifo_full(14),  
+South => south_2_north(29)(14), East => east_2_west(29)(14) , Grant => Signal_grant(29)(14)); 
+
+Arbiter_29_15 : Arbiter
+
+PORT MAP (Request => Request(225), North => south_2_north(28)(15), West => east_2_west(28)(14), P => Signal_priority(1), Fifo_full => Fifo_full(15),  
+South => south_2_north(29)(15), East => east_2_west(29)(15) , Grant => Signal_grant(29)(15)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "11111111111111100000000000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "11111111111111100000000000000" => Signal_priority <= "01111111111111110000000000000";
+		       when "01111111111111110000000000000" => Signal_priority <= "00111111111111111000000000000";
+		       when "00111111111111111000000000000" => Signal_priority <= "00011111111111111100000000000";
+		       when "00011111111111111100000000000" => Signal_priority <= "00001111111111111110000000000";
+		       when "00001111111111111110000000000" => Signal_priority <= "00000111111111111111000000000";
+		       when "00000111111111111111000000000" => Signal_priority <= "00000011111111111111100000000";
+		       when "00000011111111111111100000000" => Signal_priority <= "00000001111111111111110000000";
+		       when "00000001111111111111110000000" => Signal_priority <= "00000000111111111111111000000";
+		       when "00000000111111111111111000000" => Signal_priority <= "00000000011111111111111100000";
+		       when "00000000011111111111111100000" => Signal_priority <= "00000000001111111111111110000";
+		       when "00000000001111111111111110000" => Signal_priority <= "00000000000111111111111111000";
+		       when "00000000000111111111111111000" => Signal_priority <= "00000000000011111111111111100";
+		       when "00000000000011111111111111100" => Signal_priority <= "00000000000001111111111111110";
+		       when "00000000000001111111111111110" => Signal_priority <= "00000000000000111111111111111";
+		       when "00000000000000111111111111111" => Signal_priority <= "11111111111111100000000000000";
+		       when others    => Signal_priority <= "11111111111111100000000000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER16_16.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER16_16.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER16_16.VHD	(revision 20)
@@ -0,0 +1,2940 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler16_16 is
+    Port ( Request : in  STD_LOGIC_VECTOR (256 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (16 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (16 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (256 downto 1));
+end Scheduler16_16;
+
+architecture Behavioral of Scheduler16_16 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(31 downto 1) of STD_LOGIC_VECTOR(16 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (31 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(256 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(256 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 65535 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(17)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(18)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(19)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(20)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(21)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(22)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(23)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(24)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) or Signal_grant(25)(9); --  Grant(1,9)
+Grant(10)  <= Signal_grant(10)(10) or Signal_grant(26)(10); --  Grant(1,10)
+Grant(11)  <= Signal_grant(11)(11) or Signal_grant(27)(11); --  Grant(1,11)
+Grant(12)  <= Signal_grant(12)(12) or Signal_grant(28)(12); --  Grant(1,12)
+Grant(13)  <= Signal_grant(13)(13) or Signal_grant(29)(13); --  Grant(1,13)
+Grant(14)  <= Signal_grant(14)(14) or Signal_grant(30)(14); --  Grant(1,14)
+Grant(15)  <= Signal_grant(15)(15) or Signal_grant(31)(15); --  Grant(1,15)
+Grant(16)  <= Signal_grant(16)(16) ;                      --  Grant(1,16)
+Grant(17)  <= Signal_grant(2)(1) or Signal_grant(18)(1); --  Grant(2,1)
+Grant(18)  <= Signal_grant(3)(2) or Signal_grant(19)(2); --  Grant(2,2)
+Grant(19)  <= Signal_grant(4)(3) or Signal_grant(20)(3); --  Grant(2,3)
+Grant(20)  <= Signal_grant(5)(4) or Signal_grant(21)(4); --  Grant(2,4)
+Grant(21)  <= Signal_grant(6)(5) or Signal_grant(22)(5); --  Grant(2,5)
+Grant(22)  <= Signal_grant(7)(6) or Signal_grant(23)(6); --  Grant(2,6)
+Grant(23)  <= Signal_grant(8)(7) or Signal_grant(24)(7); --  Grant(2,7)
+Grant(24)  <= Signal_grant(9)(8) or Signal_grant(25)(8); --  Grant(2,8)
+Grant(25)  <= Signal_grant(10)(9) or Signal_grant(26)(9); --  Grant(2,9)
+Grant(26)  <= Signal_grant(11)(10) or Signal_grant(27)(10); --  Grant(2,10)
+Grant(27)  <= Signal_grant(12)(11) or Signal_grant(28)(11); --  Grant(2,11)
+Grant(28)  <= Signal_grant(13)(12) or Signal_grant(29)(12); --  Grant(2,12)
+Grant(29)  <= Signal_grant(14)(13) or Signal_grant(30)(13); --  Grant(2,13)
+Grant(30)  <= Signal_grant(15)(14) or Signal_grant(31)(14); --  Grant(2,14)
+Grant(31)  <= Signal_grant(16)(15) ;                      --  Grant(2,15)
+Grant(32)  <= Signal_grant(1)(16) or Signal_grant(17)(16); --  Grant(2,16)
+Grant(33)  <= Signal_grant(3)(1) or Signal_grant(19)(1); --  Grant(3,1)
+Grant(34)  <= Signal_grant(4)(2) or Signal_grant(20)(2); --  Grant(3,2)
+Grant(35)  <= Signal_grant(5)(3) or Signal_grant(21)(3); --  Grant(3,3)
+Grant(36)  <= Signal_grant(6)(4) or Signal_grant(22)(4); --  Grant(3,4)
+Grant(37)  <= Signal_grant(7)(5) or Signal_grant(23)(5); --  Grant(3,5)
+Grant(38)  <= Signal_grant(8)(6) or Signal_grant(24)(6); --  Grant(3,6)
+Grant(39)  <= Signal_grant(9)(7) or Signal_grant(25)(7); --  Grant(3,7)
+Grant(40)  <= Signal_grant(10)(8) or Signal_grant(26)(8); --  Grant(3,8)
+Grant(41)  <= Signal_grant(11)(9) or Signal_grant(27)(9); --  Grant(3,9)
+Grant(42)  <= Signal_grant(12)(10) or Signal_grant(28)(10); --  Grant(3,10)
+Grant(43)  <= Signal_grant(13)(11) or Signal_grant(29)(11); --  Grant(3,11)
+Grant(44)  <= Signal_grant(14)(12) or Signal_grant(30)(12); --  Grant(3,12)
+Grant(45)  <= Signal_grant(15)(13) or Signal_grant(31)(13); --  Grant(3,13)
+Grant(46)  <= Signal_grant(16)(14) ;                      --  Grant(3,14)
+Grant(47)  <= Signal_grant(1)(15) or Signal_grant(17)(15); --  Grant(3,15)
+Grant(48)  <= Signal_grant(2)(16) or Signal_grant(18)(16); --  Grant(3,16)
+Grant(49)  <= Signal_grant(4)(1) or Signal_grant(20)(1); --  Grant(4,1)
+Grant(50)  <= Signal_grant(5)(2) or Signal_grant(21)(2); --  Grant(4,2)
+Grant(51)  <= Signal_grant(6)(3) or Signal_grant(22)(3); --  Grant(4,3)
+Grant(52)  <= Signal_grant(7)(4) or Signal_grant(23)(4); --  Grant(4,4)
+Grant(53)  <= Signal_grant(8)(5) or Signal_grant(24)(5); --  Grant(4,5)
+Grant(54)  <= Signal_grant(9)(6) or Signal_grant(25)(6); --  Grant(4,6)
+Grant(55)  <= Signal_grant(10)(7) or Signal_grant(26)(7); --  Grant(4,7)
+Grant(56)  <= Signal_grant(11)(8) or Signal_grant(27)(8); --  Grant(4,8)
+Grant(57)  <= Signal_grant(12)(9) or Signal_grant(28)(9); --  Grant(4,9)
+Grant(58)  <= Signal_grant(13)(10) or Signal_grant(29)(10); --  Grant(4,10)
+Grant(59)  <= Signal_grant(14)(11) or Signal_grant(30)(11); --  Grant(4,11)
+Grant(60)  <= Signal_grant(15)(12) or Signal_grant(31)(12); --  Grant(4,12)
+Grant(61)  <= Signal_grant(16)(13) ;                      --  Grant(4,13)
+Grant(62)  <= Signal_grant(1)(14) or Signal_grant(17)(14); --  Grant(4,14)
+Grant(63)  <= Signal_grant(2)(15) or Signal_grant(18)(15); --  Grant(4,15)
+Grant(64)  <= Signal_grant(3)(16) or Signal_grant(19)(16); --  Grant(4,16)
+Grant(65)  <= Signal_grant(5)(1) or Signal_grant(21)(1); --  Grant(5,1)
+Grant(66)  <= Signal_grant(6)(2) or Signal_grant(22)(2); --  Grant(5,2)
+Grant(67)  <= Signal_grant(7)(3) or Signal_grant(23)(3); --  Grant(5,3)
+Grant(68)  <= Signal_grant(8)(4) or Signal_grant(24)(4); --  Grant(5,4)
+Grant(69)  <= Signal_grant(9)(5) or Signal_grant(25)(5); --  Grant(5,5)
+Grant(70)  <= Signal_grant(10)(6) or Signal_grant(26)(6); --  Grant(5,6)
+Grant(71)  <= Signal_grant(11)(7) or Signal_grant(27)(7); --  Grant(5,7)
+Grant(72)  <= Signal_grant(12)(8) or Signal_grant(28)(8); --  Grant(5,8)
+Grant(73)  <= Signal_grant(13)(9) or Signal_grant(29)(9); --  Grant(5,9)
+Grant(74)  <= Signal_grant(14)(10) or Signal_grant(30)(10); --  Grant(5,10)
+Grant(75)  <= Signal_grant(15)(11) or Signal_grant(31)(11); --  Grant(5,11)
+Grant(76)  <= Signal_grant(16)(12) ;                      --  Grant(5,12)
+Grant(77)  <= Signal_grant(1)(13) or Signal_grant(17)(13); --  Grant(5,13)
+Grant(78)  <= Signal_grant(2)(14) or Signal_grant(18)(14); --  Grant(5,14)
+Grant(79)  <= Signal_grant(3)(15) or Signal_grant(19)(15); --  Grant(5,15)
+Grant(80)  <= Signal_grant(4)(16) or Signal_grant(20)(16); --  Grant(5,16)
+Grant(81)  <= Signal_grant(6)(1) or Signal_grant(22)(1); --  Grant(6,1)
+Grant(82)  <= Signal_grant(7)(2) or Signal_grant(23)(2); --  Grant(6,2)
+Grant(83)  <= Signal_grant(8)(3) or Signal_grant(24)(3); --  Grant(6,3)
+Grant(84)  <= Signal_grant(9)(4) or Signal_grant(25)(4); --  Grant(6,4)
+Grant(85)  <= Signal_grant(10)(5) or Signal_grant(26)(5); --  Grant(6,5)
+Grant(86)  <= Signal_grant(11)(6) or Signal_grant(27)(6); --  Grant(6,6)
+Grant(87)  <= Signal_grant(12)(7) or Signal_grant(28)(7); --  Grant(6,7)
+Grant(88)  <= Signal_grant(13)(8) or Signal_grant(29)(8); --  Grant(6,8)
+Grant(89)  <= Signal_grant(14)(9) or Signal_grant(30)(9); --  Grant(6,9)
+Grant(90)  <= Signal_grant(15)(10) or Signal_grant(31)(10); --  Grant(6,10)
+Grant(91)  <= Signal_grant(16)(11) ;                      --  Grant(6,11)
+Grant(92)  <= Signal_grant(1)(12) or Signal_grant(17)(12); --  Grant(6,12)
+Grant(93)  <= Signal_grant(2)(13) or Signal_grant(18)(13); --  Grant(6,13)
+Grant(94)  <= Signal_grant(3)(14) or Signal_grant(19)(14); --  Grant(6,14)
+Grant(95)  <= Signal_grant(4)(15) or Signal_grant(20)(15); --  Grant(6,15)
+Grant(96)  <= Signal_grant(5)(16) or Signal_grant(21)(16); --  Grant(6,16)
+Grant(97)  <= Signal_grant(7)(1) or Signal_grant(23)(1); --  Grant(7,1)
+Grant(98)  <= Signal_grant(8)(2) or Signal_grant(24)(2); --  Grant(7,2)
+Grant(99)  <= Signal_grant(9)(3) or Signal_grant(25)(3); --  Grant(7,3)
+Grant(100)  <= Signal_grant(10)(4) or Signal_grant(26)(4); --  Grant(7,4)
+Grant(101)  <= Signal_grant(11)(5) or Signal_grant(27)(5); --  Grant(7,5)
+Grant(102)  <= Signal_grant(12)(6) or Signal_grant(28)(6); --  Grant(7,6)
+Grant(103)  <= Signal_grant(13)(7) or Signal_grant(29)(7); --  Grant(7,7)
+Grant(104)  <= Signal_grant(14)(8) or Signal_grant(30)(8); --  Grant(7,8)
+Grant(105)  <= Signal_grant(15)(9) or Signal_grant(31)(9); --  Grant(7,9)
+Grant(106)  <= Signal_grant(16)(10) ;                      --  Grant(7,10)
+Grant(107)  <= Signal_grant(1)(11) or Signal_grant(17)(11); --  Grant(7,11)
+Grant(108)  <= Signal_grant(2)(12) or Signal_grant(18)(12); --  Grant(7,12)
+Grant(109)  <= Signal_grant(3)(13) or Signal_grant(19)(13); --  Grant(7,13)
+Grant(110)  <= Signal_grant(4)(14) or Signal_grant(20)(14); --  Grant(7,14)
+Grant(111)  <= Signal_grant(5)(15) or Signal_grant(21)(15); --  Grant(7,15)
+Grant(112)  <= Signal_grant(6)(16) or Signal_grant(22)(16); --  Grant(7,16)
+Grant(113)  <= Signal_grant(8)(1) or Signal_grant(24)(1); --  Grant(8,1)
+Grant(114)  <= Signal_grant(9)(2) or Signal_grant(25)(2); --  Grant(8,2)
+Grant(115)  <= Signal_grant(10)(3) or Signal_grant(26)(3); --  Grant(8,3)
+Grant(116)  <= Signal_grant(11)(4) or Signal_grant(27)(4); --  Grant(8,4)
+Grant(117)  <= Signal_grant(12)(5) or Signal_grant(28)(5); --  Grant(8,5)
+Grant(118)  <= Signal_grant(13)(6) or Signal_grant(29)(6); --  Grant(8,6)
+Grant(119)  <= Signal_grant(14)(7) or Signal_grant(30)(7); --  Grant(8,7)
+Grant(120)  <= Signal_grant(15)(8) or Signal_grant(31)(8); --  Grant(8,8)
+Grant(121)  <= Signal_grant(16)(9) ;                      --  Grant(8,9)
+Grant(122)  <= Signal_grant(1)(10) or Signal_grant(17)(10); --  Grant(8,10)
+Grant(123)  <= Signal_grant(2)(11) or Signal_grant(18)(11); --  Grant(8,11)
+Grant(124)  <= Signal_grant(3)(12) or Signal_grant(19)(12); --  Grant(8,12)
+Grant(125)  <= Signal_grant(4)(13) or Signal_grant(20)(13); --  Grant(8,13)
+Grant(126)  <= Signal_grant(5)(14) or Signal_grant(21)(14); --  Grant(8,14)
+Grant(127)  <= Signal_grant(6)(15) or Signal_grant(22)(15); --  Grant(8,15)
+Grant(128)  <= Signal_grant(7)(16) or Signal_grant(23)(16); --  Grant(8,16)
+Grant(129)  <= Signal_grant(9)(1) or Signal_grant(25)(1); --  Grant(9,1)
+Grant(130)  <= Signal_grant(10)(2) or Signal_grant(26)(2); --  Grant(9,2)
+Grant(131)  <= Signal_grant(11)(3) or Signal_grant(27)(3); --  Grant(9,3)
+Grant(132)  <= Signal_grant(12)(4) or Signal_grant(28)(4); --  Grant(9,4)
+Grant(133)  <= Signal_grant(13)(5) or Signal_grant(29)(5); --  Grant(9,5)
+Grant(134)  <= Signal_grant(14)(6) or Signal_grant(30)(6); --  Grant(9,6)
+Grant(135)  <= Signal_grant(15)(7) or Signal_grant(31)(7); --  Grant(9,7)
+Grant(136)  <= Signal_grant(16)(8) ;                      --  Grant(9,8)
+Grant(137)  <= Signal_grant(1)(9) or Signal_grant(17)(9); --  Grant(9,9)
+Grant(138)  <= Signal_grant(2)(10) or Signal_grant(18)(10); --  Grant(9,10)
+Grant(139)  <= Signal_grant(3)(11) or Signal_grant(19)(11); --  Grant(9,11)
+Grant(140)  <= Signal_grant(4)(12) or Signal_grant(20)(12); --  Grant(9,12)
+Grant(141)  <= Signal_grant(5)(13) or Signal_grant(21)(13); --  Grant(9,13)
+Grant(142)  <= Signal_grant(6)(14) or Signal_grant(22)(14); --  Grant(9,14)
+Grant(143)  <= Signal_grant(7)(15) or Signal_grant(23)(15); --  Grant(9,15)
+Grant(144)  <= Signal_grant(8)(16) or Signal_grant(24)(16); --  Grant(9,16)
+Grant(145)  <= Signal_grant(10)(1) or Signal_grant(26)(1); --  Grant(10,1)
+Grant(146)  <= Signal_grant(11)(2) or Signal_grant(27)(2); --  Grant(10,2)
+Grant(147)  <= Signal_grant(12)(3) or Signal_grant(28)(3); --  Grant(10,3)
+Grant(148)  <= Signal_grant(13)(4) or Signal_grant(29)(4); --  Grant(10,4)
+Grant(149)  <= Signal_grant(14)(5) or Signal_grant(30)(5); --  Grant(10,5)
+Grant(150)  <= Signal_grant(15)(6) or Signal_grant(31)(6); --  Grant(10,6)
+Grant(151)  <= Signal_grant(16)(7) ;                      --  Grant(10,7)
+Grant(152)  <= Signal_grant(1)(8) or Signal_grant(17)(8); --  Grant(10,8)
+Grant(153)  <= Signal_grant(2)(9) or Signal_grant(18)(9); --  Grant(10,9)
+Grant(154)  <= Signal_grant(3)(10) or Signal_grant(19)(10); --  Grant(10,10)
+Grant(155)  <= Signal_grant(4)(11) or Signal_grant(20)(11); --  Grant(10,11)
+Grant(156)  <= Signal_grant(5)(12) or Signal_grant(21)(12); --  Grant(10,12)
+Grant(157)  <= Signal_grant(6)(13) or Signal_grant(22)(13); --  Grant(10,13)
+Grant(158)  <= Signal_grant(7)(14) or Signal_grant(23)(14); --  Grant(10,14)
+Grant(159)  <= Signal_grant(8)(15) or Signal_grant(24)(15); --  Grant(10,15)
+Grant(160)  <= Signal_grant(9)(16) or Signal_grant(25)(16); --  Grant(10,16)
+Grant(161)  <= Signal_grant(11)(1) or Signal_grant(27)(1); --  Grant(11,1)
+Grant(162)  <= Signal_grant(12)(2) or Signal_grant(28)(2); --  Grant(11,2)
+Grant(163)  <= Signal_grant(13)(3) or Signal_grant(29)(3); --  Grant(11,3)
+Grant(164)  <= Signal_grant(14)(4) or Signal_grant(30)(4); --  Grant(11,4)
+Grant(165)  <= Signal_grant(15)(5) or Signal_grant(31)(5); --  Grant(11,5)
+Grant(166)  <= Signal_grant(16)(6) ;                      --  Grant(11,6)
+Grant(167)  <= Signal_grant(1)(7) or Signal_grant(17)(7); --  Grant(11,7)
+Grant(168)  <= Signal_grant(2)(8) or Signal_grant(18)(8); --  Grant(11,8)
+Grant(169)  <= Signal_grant(3)(9) or Signal_grant(19)(9); --  Grant(11,9)
+Grant(170)  <= Signal_grant(4)(10) or Signal_grant(20)(10); --  Grant(11,10)
+Grant(171)  <= Signal_grant(5)(11) or Signal_grant(21)(11); --  Grant(11,11)
+Grant(172)  <= Signal_grant(6)(12) or Signal_grant(22)(12); --  Grant(11,12)
+Grant(173)  <= Signal_grant(7)(13) or Signal_grant(23)(13); --  Grant(11,13)
+Grant(174)  <= Signal_grant(8)(14) or Signal_grant(24)(14); --  Grant(11,14)
+Grant(175)  <= Signal_grant(9)(15) or Signal_grant(25)(15); --  Grant(11,15)
+Grant(176)  <= Signal_grant(10)(16) or Signal_grant(26)(16); --  Grant(11,16)
+Grant(177)  <= Signal_grant(12)(1) or Signal_grant(28)(1); --  Grant(12,1)
+Grant(178)  <= Signal_grant(13)(2) or Signal_grant(29)(2); --  Grant(12,2)
+Grant(179)  <= Signal_grant(14)(3) or Signal_grant(30)(3); --  Grant(12,3)
+Grant(180)  <= Signal_grant(15)(4) or Signal_grant(31)(4); --  Grant(12,4)
+Grant(181)  <= Signal_grant(16)(5) ;                      --  Grant(12,5)
+Grant(182)  <= Signal_grant(1)(6) or Signal_grant(17)(6); --  Grant(12,6)
+Grant(183)  <= Signal_grant(2)(7) or Signal_grant(18)(7); --  Grant(12,7)
+Grant(184)  <= Signal_grant(3)(8) or Signal_grant(19)(8); --  Grant(12,8)
+Grant(185)  <= Signal_grant(4)(9) or Signal_grant(20)(9); --  Grant(12,9)
+Grant(186)  <= Signal_grant(5)(10) or Signal_grant(21)(10); --  Grant(12,10)
+Grant(187)  <= Signal_grant(6)(11) or Signal_grant(22)(11); --  Grant(12,11)
+Grant(188)  <= Signal_grant(7)(12) or Signal_grant(23)(12); --  Grant(12,12)
+Grant(189)  <= Signal_grant(8)(13) or Signal_grant(24)(13); --  Grant(12,13)
+Grant(190)  <= Signal_grant(9)(14) or Signal_grant(25)(14); --  Grant(12,14)
+Grant(191)  <= Signal_grant(10)(15) or Signal_grant(26)(15); --  Grant(12,15)
+Grant(192)  <= Signal_grant(11)(16) or Signal_grant(27)(16); --  Grant(12,16)
+Grant(193)  <= Signal_grant(13)(1) or Signal_grant(29)(1); --  Grant(13,1)
+Grant(194)  <= Signal_grant(14)(2) or Signal_grant(30)(2); --  Grant(13,2)
+Grant(195)  <= Signal_grant(15)(3) or Signal_grant(31)(3); --  Grant(13,3)
+Grant(196)  <= Signal_grant(16)(4) ;                      --  Grant(13,4)
+Grant(197)  <= Signal_grant(1)(5) or Signal_grant(17)(5); --  Grant(13,5)
+Grant(198)  <= Signal_grant(2)(6) or Signal_grant(18)(6); --  Grant(13,6)
+Grant(199)  <= Signal_grant(3)(7) or Signal_grant(19)(7); --  Grant(13,7)
+Grant(200)  <= Signal_grant(4)(8) or Signal_grant(20)(8); --  Grant(13,8)
+Grant(201)  <= Signal_grant(5)(9) or Signal_grant(21)(9); --  Grant(13,9)
+Grant(202)  <= Signal_grant(6)(10) or Signal_grant(22)(10); --  Grant(13,10)
+Grant(203)  <= Signal_grant(7)(11) or Signal_grant(23)(11); --  Grant(13,11)
+Grant(204)  <= Signal_grant(8)(12) or Signal_grant(24)(12); --  Grant(13,12)
+Grant(205)  <= Signal_grant(9)(13) or Signal_grant(25)(13); --  Grant(13,13)
+Grant(206)  <= Signal_grant(10)(14) or Signal_grant(26)(14); --  Grant(13,14)
+Grant(207)  <= Signal_grant(11)(15) or Signal_grant(27)(15); --  Grant(13,15)
+Grant(208)  <= Signal_grant(12)(16) or Signal_grant(28)(16); --  Grant(13,16)
+Grant(209)  <= Signal_grant(14)(1) or Signal_grant(30)(1); --  Grant(14,1)
+Grant(210)  <= Signal_grant(15)(2) or Signal_grant(31)(2); --  Grant(14,2)
+Grant(211)  <= Signal_grant(16)(3) ;                      --  Grant(14,3)
+Grant(212)  <= Signal_grant(1)(4) or Signal_grant(17)(4); --  Grant(14,4)
+Grant(213)  <= Signal_grant(2)(5) or Signal_grant(18)(5); --  Grant(14,5)
+Grant(214)  <= Signal_grant(3)(6) or Signal_grant(19)(6); --  Grant(14,6)
+Grant(215)  <= Signal_grant(4)(7) or Signal_grant(20)(7); --  Grant(14,7)
+Grant(216)  <= Signal_grant(5)(8) or Signal_grant(21)(8); --  Grant(14,8)
+Grant(217)  <= Signal_grant(6)(9) or Signal_grant(22)(9); --  Grant(14,9)
+Grant(218)  <= Signal_grant(7)(10) or Signal_grant(23)(10); --  Grant(14,10)
+Grant(219)  <= Signal_grant(8)(11) or Signal_grant(24)(11); --  Grant(14,11)
+Grant(220)  <= Signal_grant(9)(12) or Signal_grant(25)(12); --  Grant(14,12)
+Grant(221)  <= Signal_grant(10)(13) or Signal_grant(26)(13); --  Grant(14,13)
+Grant(222)  <= Signal_grant(11)(14) or Signal_grant(27)(14); --  Grant(14,14)
+Grant(223)  <= Signal_grant(12)(15) or Signal_grant(28)(15); --  Grant(14,15)
+Grant(224)  <= Signal_grant(13)(16) or Signal_grant(29)(16); --  Grant(14,16)
+Grant(225)  <= Signal_grant(15)(1) or Signal_grant(31)(1); --  Grant(15,1)
+Grant(226)  <= Signal_grant(16)(2) ;                      --  Grant(15,2)
+Grant(227)  <= Signal_grant(1)(3) or Signal_grant(17)(3); --  Grant(15,3)
+Grant(228)  <= Signal_grant(2)(4) or Signal_grant(18)(4); --  Grant(15,4)
+Grant(229)  <= Signal_grant(3)(5) or Signal_grant(19)(5); --  Grant(15,5)
+Grant(230)  <= Signal_grant(4)(6) or Signal_grant(20)(6); --  Grant(15,6)
+Grant(231)  <= Signal_grant(5)(7) or Signal_grant(21)(7); --  Grant(15,7)
+Grant(232)  <= Signal_grant(6)(8) or Signal_grant(22)(8); --  Grant(15,8)
+Grant(233)  <= Signal_grant(7)(9) or Signal_grant(23)(9); --  Grant(15,9)
+Grant(234)  <= Signal_grant(8)(10) or Signal_grant(24)(10); --  Grant(15,10)
+Grant(235)  <= Signal_grant(9)(11) or Signal_grant(25)(11); --  Grant(15,11)
+Grant(236)  <= Signal_grant(10)(12) or Signal_grant(26)(12); --  Grant(15,12)
+Grant(237)  <= Signal_grant(11)(13) or Signal_grant(27)(13); --  Grant(15,13)
+Grant(238)  <= Signal_grant(12)(14) or Signal_grant(28)(14); --  Grant(15,14)
+Grant(239)  <= Signal_grant(13)(15) or Signal_grant(29)(15); --  Grant(15,15)
+Grant(240)  <= Signal_grant(14)(16) or Signal_grant(30)(16); --  Grant(15,16)
+Grant(241)  <= Signal_grant(16)(1) ;                      --  Grant(16,1)
+Grant(242)  <= Signal_grant(1)(2) or Signal_grant(17)(2); --  Grant(16,2)
+Grant(243)  <= Signal_grant(2)(3) or Signal_grant(18)(3); --  Grant(16,3)
+Grant(244)  <= Signal_grant(3)(4) or Signal_grant(19)(4); --  Grant(16,4)
+Grant(245)  <= Signal_grant(4)(5) or Signal_grant(20)(5); --  Grant(16,5)
+Grant(246)  <= Signal_grant(5)(6) or Signal_grant(21)(6); --  Grant(16,6)
+Grant(247)  <= Signal_grant(6)(7) or Signal_grant(22)(7); --  Grant(16,7)
+Grant(248)  <= Signal_grant(7)(8) or Signal_grant(23)(8); --  Grant(16,8)
+Grant(249)  <= Signal_grant(8)(9) or Signal_grant(24)(9); --  Grant(16,9)
+Grant(250)  <= Signal_grant(9)(10) or Signal_grant(25)(10); --  Grant(16,10)
+Grant(251)  <= Signal_grant(10)(11) or Signal_grant(26)(11); --  Grant(16,11)
+Grant(252)  <= Signal_grant(11)(12) or Signal_grant(27)(12); --  Grant(16,12)
+Grant(253)  <= Signal_grant(12)(13) or Signal_grant(28)(13); --  Grant(16,13)
+Grant(254)  <= Signal_grant(13)(14) or Signal_grant(29)(14); --  Grant(16,14)
+Grant(255)  <= Signal_grant(14)(15) or Signal_grant(30)(15); --  Grant(16,15)
+Grant(256)  <= Signal_grant(15)(16) or Signal_grant(31)(16); --  Grant(16,16)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(242), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(227), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(212), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(197), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(182), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(167), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(152), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(137), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+Arbiter_1_10 : Arbiter
+
+PORT MAP (Request => Request(122), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(10),  
+South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); 
+
+Arbiter_1_11 : Arbiter
+
+PORT MAP (Request => Request(107), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(11),  
+South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); 
+
+Arbiter_1_12 : Arbiter
+
+PORT MAP (Request => Request(92), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(12),  
+South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); 
+
+Arbiter_1_13 : Arbiter
+
+PORT MAP (Request => Request(77), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(13),  
+South => south_2_north(1)(13), East => east_2_west(1)(13) , Grant => Signal_grant(1)(13)); 
+
+Arbiter_1_14 : Arbiter
+
+PORT MAP (Request => Request(62), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(14),  
+South => south_2_north(1)(14), East => east_2_west(1)(14) , Grant => Signal_grant(1)(14)); 
+
+Arbiter_1_15 : Arbiter
+
+PORT MAP (Request => Request(47), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(15),  
+South => south_2_north(1)(15), East => east_2_west(1)(15) , Grant => Signal_grant(1)(15)); 
+
+Arbiter_1_16 : Arbiter
+
+PORT MAP (Request => Request(32), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(16),  
+South => south_2_north(1)(16), East => east_2_west(1)(16) , Grant => Signal_grant(1)(16)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(1)(1), West => east_2_west(1)(16), P => Signal_priority(30), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(30), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(243), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(30), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(228), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(30), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(213), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(30), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(198), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(30), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(183), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(30), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(30), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(30), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+Arbiter_2_10 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(30), Fifo_full => Fifo_full(10),  
+South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); 
+
+Arbiter_2_11 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(30), Fifo_full => Fifo_full(11),  
+South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); 
+
+Arbiter_2_12 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(30), Fifo_full => Fifo_full(12),  
+South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); 
+
+Arbiter_2_13 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(1)(13), West => east_2_west(1)(12), P => Signal_priority(30), Fifo_full => Fifo_full(13),  
+South => south_2_north(2)(13), East => east_2_west(2)(13) , Grant => Signal_grant(2)(13)); 
+
+Arbiter_2_14 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(1)(14), West => east_2_west(1)(13), P => Signal_priority(30), Fifo_full => Fifo_full(14),  
+South => south_2_north(2)(14), East => east_2_west(2)(14) , Grant => Signal_grant(2)(14)); 
+
+Arbiter_2_15 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(1)(15), West => east_2_west(1)(14), P => Signal_priority(30), Fifo_full => Fifo_full(15),  
+South => south_2_north(2)(15), East => east_2_west(2)(15) , Grant => Signal_grant(2)(15)); 
+
+Arbiter_2_16 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(1)(16), West => east_2_west(1)(15), P => Signal_priority(30), Fifo_full => Fifo_full(16),  
+South => south_2_north(2)(16), East => east_2_west(2)(16) , Grant => Signal_grant(2)(16)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(2)(1), West => east_2_west(2)(16), P => Signal_priority(29), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(29), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(29), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(244), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(29), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(229), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(29), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(214), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(29), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(199), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(29), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(184), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(29), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(169), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(29), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+Arbiter_3_10 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(29), Fifo_full => Fifo_full(10),  
+South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); 
+
+Arbiter_3_11 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(29), Fifo_full => Fifo_full(11),  
+South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); 
+
+Arbiter_3_12 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(29), Fifo_full => Fifo_full(12),  
+South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); 
+
+Arbiter_3_13 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(2)(13), West => east_2_west(2)(12), P => Signal_priority(29), Fifo_full => Fifo_full(13),  
+South => south_2_north(3)(13), East => east_2_west(3)(13) , Grant => Signal_grant(3)(13)); 
+
+Arbiter_3_14 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(2)(14), West => east_2_west(2)(13), P => Signal_priority(29), Fifo_full => Fifo_full(14),  
+South => south_2_north(3)(14), East => east_2_west(3)(14) , Grant => Signal_grant(3)(14)); 
+
+Arbiter_3_15 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(2)(15), West => east_2_west(2)(14), P => Signal_priority(29), Fifo_full => Fifo_full(15),  
+South => south_2_north(3)(15), East => east_2_west(3)(15) , Grant => Signal_grant(3)(15)); 
+
+Arbiter_3_16 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(2)(16), West => east_2_west(2)(15), P => Signal_priority(29), Fifo_full => Fifo_full(16),  
+South => south_2_north(3)(16), East => east_2_west(3)(16) , Grant => Signal_grant(3)(16)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(3)(1), West => east_2_west(3)(16), P => Signal_priority(28), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(28), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(28), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(28), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(245), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(28), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(230), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(28), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(215), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(28), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(200), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(28), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(185), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(28), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+Arbiter_4_10 : Arbiter
+
+PORT MAP (Request => Request(170), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(28), Fifo_full => Fifo_full(10),  
+South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); 
+
+Arbiter_4_11 : Arbiter
+
+PORT MAP (Request => Request(155), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(28), Fifo_full => Fifo_full(11),  
+South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); 
+
+Arbiter_4_12 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(28), Fifo_full => Fifo_full(12),  
+South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); 
+
+Arbiter_4_13 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(3)(13), West => east_2_west(3)(12), P => Signal_priority(28), Fifo_full => Fifo_full(13),  
+South => south_2_north(4)(13), East => east_2_west(4)(13) , Grant => Signal_grant(4)(13)); 
+
+Arbiter_4_14 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(3)(14), West => east_2_west(3)(13), P => Signal_priority(28), Fifo_full => Fifo_full(14),  
+South => south_2_north(4)(14), East => east_2_west(4)(14) , Grant => Signal_grant(4)(14)); 
+
+Arbiter_4_15 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(3)(15), West => east_2_west(3)(14), P => Signal_priority(28), Fifo_full => Fifo_full(15),  
+South => south_2_north(4)(15), East => east_2_west(4)(15) , Grant => Signal_grant(4)(15)); 
+
+Arbiter_4_16 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(3)(16), West => east_2_west(3)(15), P => Signal_priority(28), Fifo_full => Fifo_full(16),  
+South => south_2_north(4)(16), East => east_2_west(4)(16) , Grant => Signal_grant(4)(16)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(4)(1), West => east_2_west(4)(16), P => Signal_priority(27), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(27), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(27), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(27), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(27), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(246), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(27), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(231), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(27), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(216), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(27), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(201), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(27), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+Arbiter_5_10 : Arbiter
+
+PORT MAP (Request => Request(186), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(27), Fifo_full => Fifo_full(10),  
+South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); 
+
+Arbiter_5_11 : Arbiter
+
+PORT MAP (Request => Request(171), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(27), Fifo_full => Fifo_full(11),  
+South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); 
+
+Arbiter_5_12 : Arbiter
+
+PORT MAP (Request => Request(156), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(27), Fifo_full => Fifo_full(12),  
+South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); 
+
+Arbiter_5_13 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(4)(13), West => east_2_west(4)(12), P => Signal_priority(27), Fifo_full => Fifo_full(13),  
+South => south_2_north(5)(13), East => east_2_west(5)(13) , Grant => Signal_grant(5)(13)); 
+
+Arbiter_5_14 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(4)(14), West => east_2_west(4)(13), P => Signal_priority(27), Fifo_full => Fifo_full(14),  
+South => south_2_north(5)(14), East => east_2_west(5)(14) , Grant => Signal_grant(5)(14)); 
+
+Arbiter_5_15 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(4)(15), West => east_2_west(4)(14), P => Signal_priority(27), Fifo_full => Fifo_full(15),  
+South => south_2_north(5)(15), East => east_2_west(5)(15) , Grant => Signal_grant(5)(15)); 
+
+Arbiter_5_16 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(4)(16), West => east_2_west(4)(15), P => Signal_priority(27), Fifo_full => Fifo_full(16),  
+South => south_2_north(5)(16), East => east_2_west(5)(16) , Grant => Signal_grant(5)(16)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(5)(1), West => east_2_west(5)(16), P => Signal_priority(26), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(26), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(26), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(26), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(26), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(26), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(247), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(26), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(232), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(26), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(217), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(26), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+Arbiter_6_10 : Arbiter
+
+PORT MAP (Request => Request(202), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(26), Fifo_full => Fifo_full(10),  
+South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); 
+
+Arbiter_6_11 : Arbiter
+
+PORT MAP (Request => Request(187), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(26), Fifo_full => Fifo_full(11),  
+South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); 
+
+Arbiter_6_12 : Arbiter
+
+PORT MAP (Request => Request(172), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(26), Fifo_full => Fifo_full(12),  
+South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); 
+
+Arbiter_6_13 : Arbiter
+
+PORT MAP (Request => Request(157), North => south_2_north(5)(13), West => east_2_west(5)(12), P => Signal_priority(26), Fifo_full => Fifo_full(13),  
+South => south_2_north(6)(13), East => east_2_west(6)(13) , Grant => Signal_grant(6)(13)); 
+
+Arbiter_6_14 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(5)(14), West => east_2_west(5)(13), P => Signal_priority(26), Fifo_full => Fifo_full(14),  
+South => south_2_north(6)(14), East => east_2_west(6)(14) , Grant => Signal_grant(6)(14)); 
+
+Arbiter_6_15 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(5)(15), West => east_2_west(5)(14), P => Signal_priority(26), Fifo_full => Fifo_full(15),  
+South => south_2_north(6)(15), East => east_2_west(6)(15) , Grant => Signal_grant(6)(15)); 
+
+Arbiter_6_16 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(5)(16), West => east_2_west(5)(15), P => Signal_priority(26), Fifo_full => Fifo_full(16),  
+South => south_2_north(6)(16), East => east_2_west(6)(16) , Grant => Signal_grant(6)(16)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(6)(1), West => east_2_west(6)(16), P => Signal_priority(25), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(25), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(25), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(25), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(25), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(25), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(25), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(248), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(25), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(233), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(25), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+Arbiter_7_10 : Arbiter
+
+PORT MAP (Request => Request(218), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(25), Fifo_full => Fifo_full(10),  
+South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); 
+
+Arbiter_7_11 : Arbiter
+
+PORT MAP (Request => Request(203), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(25), Fifo_full => Fifo_full(11),  
+South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); 
+
+Arbiter_7_12 : Arbiter
+
+PORT MAP (Request => Request(188), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(25), Fifo_full => Fifo_full(12),  
+South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); 
+
+Arbiter_7_13 : Arbiter
+
+PORT MAP (Request => Request(173), North => south_2_north(6)(13), West => east_2_west(6)(12), P => Signal_priority(25), Fifo_full => Fifo_full(13),  
+South => south_2_north(7)(13), East => east_2_west(7)(13) , Grant => Signal_grant(7)(13)); 
+
+Arbiter_7_14 : Arbiter
+
+PORT MAP (Request => Request(158), North => south_2_north(6)(14), West => east_2_west(6)(13), P => Signal_priority(25), Fifo_full => Fifo_full(14),  
+South => south_2_north(7)(14), East => east_2_west(7)(14) , Grant => Signal_grant(7)(14)); 
+
+Arbiter_7_15 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(6)(15), West => east_2_west(6)(14), P => Signal_priority(25), Fifo_full => Fifo_full(15),  
+South => south_2_north(7)(15), East => east_2_west(7)(15) , Grant => Signal_grant(7)(15)); 
+
+Arbiter_7_16 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(6)(16), West => east_2_west(6)(15), P => Signal_priority(25), Fifo_full => Fifo_full(16),  
+South => south_2_north(7)(16), East => east_2_west(7)(16) , Grant => Signal_grant(7)(16)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(7)(1), West => east_2_west(7)(16), P => Signal_priority(24), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(24), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(24), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(24), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(24), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(24), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(24), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(24), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(249), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(24), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+Arbiter_8_10 : Arbiter
+
+PORT MAP (Request => Request(234), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(24), Fifo_full => Fifo_full(10),  
+South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); 
+
+Arbiter_8_11 : Arbiter
+
+PORT MAP (Request => Request(219), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(24), Fifo_full => Fifo_full(11),  
+South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); 
+
+Arbiter_8_12 : Arbiter
+
+PORT MAP (Request => Request(204), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(24), Fifo_full => Fifo_full(12),  
+South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); 
+
+Arbiter_8_13 : Arbiter
+
+PORT MAP (Request => Request(189), North => south_2_north(7)(13), West => east_2_west(7)(12), P => Signal_priority(24), Fifo_full => Fifo_full(13),  
+South => south_2_north(8)(13), East => east_2_west(8)(13) , Grant => Signal_grant(8)(13)); 
+
+Arbiter_8_14 : Arbiter
+
+PORT MAP (Request => Request(174), North => south_2_north(7)(14), West => east_2_west(7)(13), P => Signal_priority(24), Fifo_full => Fifo_full(14),  
+South => south_2_north(8)(14), East => east_2_west(8)(14) , Grant => Signal_grant(8)(14)); 
+
+Arbiter_8_15 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(7)(15), West => east_2_west(7)(14), P => Signal_priority(24), Fifo_full => Fifo_full(15),  
+South => south_2_north(8)(15), East => east_2_west(8)(15) , Grant => Signal_grant(8)(15)); 
+
+Arbiter_8_16 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(7)(16), West => east_2_west(7)(15), P => Signal_priority(24), Fifo_full => Fifo_full(16),  
+South => south_2_north(8)(16), East => east_2_west(8)(16) , Grant => Signal_grant(8)(16)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(8)(1), West => east_2_west(8)(16), P => Signal_priority(23), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(23), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(23), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(23), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(23), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(23), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(23), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(23), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(23), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+Arbiter_9_10 : Arbiter
+
+PORT MAP (Request => Request(250), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(23), Fifo_full => Fifo_full(10),  
+South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); 
+
+Arbiter_9_11 : Arbiter
+
+PORT MAP (Request => Request(235), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(23), Fifo_full => Fifo_full(11),  
+South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); 
+
+Arbiter_9_12 : Arbiter
+
+PORT MAP (Request => Request(220), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(23), Fifo_full => Fifo_full(12),  
+South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); 
+
+Arbiter_9_13 : Arbiter
+
+PORT MAP (Request => Request(205), North => south_2_north(8)(13), West => east_2_west(8)(12), P => Signal_priority(23), Fifo_full => Fifo_full(13),  
+South => south_2_north(9)(13), East => east_2_west(9)(13) , Grant => Signal_grant(9)(13)); 
+
+Arbiter_9_14 : Arbiter
+
+PORT MAP (Request => Request(190), North => south_2_north(8)(14), West => east_2_west(8)(13), P => Signal_priority(23), Fifo_full => Fifo_full(14),  
+South => south_2_north(9)(14), East => east_2_west(9)(14) , Grant => Signal_grant(9)(14)); 
+
+Arbiter_9_15 : Arbiter
+
+PORT MAP (Request => Request(175), North => south_2_north(8)(15), West => east_2_west(8)(14), P => Signal_priority(23), Fifo_full => Fifo_full(15),  
+South => south_2_north(9)(15), East => east_2_west(9)(15) , Grant => Signal_grant(9)(15)); 
+
+Arbiter_9_16 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(8)(16), West => east_2_west(8)(15), P => Signal_priority(23), Fifo_full => Fifo_full(16),  
+South => south_2_north(9)(16), East => east_2_west(9)(16) , Grant => Signal_grant(9)(16)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(145), North => south_2_north(9)(1), West => east_2_west(9)(16), P => Signal_priority(22), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+Arbiter_10_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10),  
+South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); 
+
+Arbiter_10_11 : Arbiter
+
+PORT MAP (Request => Request(251), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11),  
+South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); 
+
+Arbiter_10_12 : Arbiter
+
+PORT MAP (Request => Request(236), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12),  
+South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); 
+
+Arbiter_10_13 : Arbiter
+
+PORT MAP (Request => Request(221), North => south_2_north(9)(13), West => east_2_west(9)(12), P => Signal_priority(22), Fifo_full => Fifo_full(13),  
+South => south_2_north(10)(13), East => east_2_west(10)(13) , Grant => Signal_grant(10)(13)); 
+
+Arbiter_10_14 : Arbiter
+
+PORT MAP (Request => Request(206), North => south_2_north(9)(14), West => east_2_west(9)(13), P => Signal_priority(22), Fifo_full => Fifo_full(14),  
+South => south_2_north(10)(14), East => east_2_west(10)(14) , Grant => Signal_grant(10)(14)); 
+
+Arbiter_10_15 : Arbiter
+
+PORT MAP (Request => Request(191), North => south_2_north(9)(15), West => east_2_west(9)(14), P => Signal_priority(22), Fifo_full => Fifo_full(15),  
+South => south_2_north(10)(15), East => east_2_west(10)(15) , Grant => Signal_grant(10)(15)); 
+
+Arbiter_10_16 : Arbiter
+
+PORT MAP (Request => Request(176), North => south_2_north(9)(16), West => east_2_west(9)(15), P => Signal_priority(22), Fifo_full => Fifo_full(16),  
+South => south_2_north(10)(16), East => east_2_west(10)(16) , Grant => Signal_grant(10)(16)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(10)(1), West => east_2_west(10)(16), P => Signal_priority(21), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(146), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+Arbiter_11_10 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10),  
+South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); 
+
+Arbiter_11_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11),  
+South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); 
+
+Arbiter_11_12 : Arbiter
+
+PORT MAP (Request => Request(252), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12),  
+South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); 
+
+Arbiter_11_13 : Arbiter
+
+PORT MAP (Request => Request(237), North => south_2_north(10)(13), West => east_2_west(10)(12), P => Signal_priority(21), Fifo_full => Fifo_full(13),  
+South => south_2_north(11)(13), East => east_2_west(11)(13) , Grant => Signal_grant(11)(13)); 
+
+Arbiter_11_14 : Arbiter
+
+PORT MAP (Request => Request(222), North => south_2_north(10)(14), West => east_2_west(10)(13), P => Signal_priority(21), Fifo_full => Fifo_full(14),  
+South => south_2_north(11)(14), East => east_2_west(11)(14) , Grant => Signal_grant(11)(14)); 
+
+Arbiter_11_15 : Arbiter
+
+PORT MAP (Request => Request(207), North => south_2_north(10)(15), West => east_2_west(10)(14), P => Signal_priority(21), Fifo_full => Fifo_full(15),  
+South => south_2_north(11)(15), East => east_2_west(11)(15) , Grant => Signal_grant(11)(15)); 
+
+Arbiter_11_16 : Arbiter
+
+PORT MAP (Request => Request(192), North => south_2_north(10)(16), West => east_2_west(10)(15), P => Signal_priority(21), Fifo_full => Fifo_full(16),  
+South => south_2_north(11)(16), East => east_2_west(11)(16) , Grant => Signal_grant(11)(16)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(177), North => south_2_north(11)(1), West => east_2_west(11)(16), P => Signal_priority(20), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+Arbiter_12_10 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10),  
+South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); 
+
+Arbiter_12_11 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11),  
+South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); 
+
+Arbiter_12_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12),  
+South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); 
+
+Arbiter_12_13 : Arbiter
+
+PORT MAP (Request => Request(253), North => south_2_north(11)(13), West => east_2_west(11)(12), P => Signal_priority(20), Fifo_full => Fifo_full(13),  
+South => south_2_north(12)(13), East => east_2_west(12)(13) , Grant => Signal_grant(12)(13)); 
+
+Arbiter_12_14 : Arbiter
+
+PORT MAP (Request => Request(238), North => south_2_north(11)(14), West => east_2_west(11)(13), P => Signal_priority(20), Fifo_full => Fifo_full(14),  
+South => south_2_north(12)(14), East => east_2_west(12)(14) , Grant => Signal_grant(12)(14)); 
+
+Arbiter_12_15 : Arbiter
+
+PORT MAP (Request => Request(223), North => south_2_north(11)(15), West => east_2_west(11)(14), P => Signal_priority(20), Fifo_full => Fifo_full(15),  
+South => south_2_north(12)(15), East => east_2_west(12)(15) , Grant => Signal_grant(12)(15)); 
+
+Arbiter_12_16 : Arbiter
+
+PORT MAP (Request => Request(208), North => south_2_north(11)(16), West => east_2_west(11)(15), P => Signal_priority(20), Fifo_full => Fifo_full(16),  
+South => south_2_north(12)(16), East => east_2_west(12)(16) , Grant => Signal_grant(12)(16)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(193), North => south_2_north(12)(1), West => east_2_west(12)(16), P => Signal_priority(19), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(178), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+Arbiter_13_10 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10),  
+South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); 
+
+Arbiter_13_11 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11),  
+South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); 
+
+Arbiter_13_12 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12),  
+South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); 
+
+Arbiter_13_13 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(12)(13), West => east_2_west(12)(12), P => Signal_priority(19), Fifo_full => Fifo_full(13),  
+South => south_2_north(13)(13), East => east_2_west(13)(13) , Grant => Signal_grant(13)(13)); 
+
+Arbiter_13_14 : Arbiter
+
+PORT MAP (Request => Request(254), North => south_2_north(12)(14), West => east_2_west(12)(13), P => Signal_priority(19), Fifo_full => Fifo_full(14),  
+South => south_2_north(13)(14), East => east_2_west(13)(14) , Grant => Signal_grant(13)(14)); 
+
+Arbiter_13_15 : Arbiter
+
+PORT MAP (Request => Request(239), North => south_2_north(12)(15), West => east_2_west(12)(14), P => Signal_priority(19), Fifo_full => Fifo_full(15),  
+South => south_2_north(13)(15), East => east_2_west(13)(15) , Grant => Signal_grant(13)(15)); 
+
+Arbiter_13_16 : Arbiter
+
+PORT MAP (Request => Request(224), North => south_2_north(12)(16), West => east_2_west(12)(15), P => Signal_priority(19), Fifo_full => Fifo_full(16),  
+South => south_2_north(13)(16), East => east_2_west(13)(16) , Grant => Signal_grant(13)(16)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(209), North => south_2_north(13)(1), West => east_2_west(13)(16), P => Signal_priority(18), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(194), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(179), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+Arbiter_14_10 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10),  
+South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); 
+
+Arbiter_14_11 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11),  
+South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); 
+
+Arbiter_14_12 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12),  
+South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); 
+
+Arbiter_14_13 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(13)(13), West => east_2_west(13)(12), P => Signal_priority(18), Fifo_full => Fifo_full(13),  
+South => south_2_north(14)(13), East => east_2_west(14)(13) , Grant => Signal_grant(14)(13)); 
+
+Arbiter_14_14 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(13)(14), West => east_2_west(13)(13), P => Signal_priority(18), Fifo_full => Fifo_full(14),  
+South => south_2_north(14)(14), East => east_2_west(14)(14) , Grant => Signal_grant(14)(14)); 
+
+Arbiter_14_15 : Arbiter
+
+PORT MAP (Request => Request(255), North => south_2_north(13)(15), West => east_2_west(13)(14), P => Signal_priority(18), Fifo_full => Fifo_full(15),  
+South => south_2_north(14)(15), East => east_2_west(14)(15) , Grant => Signal_grant(14)(15)); 
+
+Arbiter_14_16 : Arbiter
+
+PORT MAP (Request => Request(240), North => south_2_north(13)(16), West => east_2_west(13)(15), P => Signal_priority(18), Fifo_full => Fifo_full(16),  
+South => south_2_north(14)(16), East => east_2_west(14)(16) , Grant => Signal_grant(14)(16)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(225), North => south_2_north(14)(1), West => east_2_west(14)(16), P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(210), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(195), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(180), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+Arbiter_15_10 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10),  
+South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); 
+
+Arbiter_15_11 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11),  
+South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); 
+
+Arbiter_15_12 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12),  
+South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); 
+
+Arbiter_15_13 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(14)(13), West => east_2_west(14)(12), P => Signal_priority(17), Fifo_full => Fifo_full(13),  
+South => south_2_north(15)(13), East => east_2_west(15)(13) , Grant => Signal_grant(15)(13)); 
+
+Arbiter_15_14 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(14)(14), West => east_2_west(14)(13), P => Signal_priority(17), Fifo_full => Fifo_full(14),  
+South => south_2_north(15)(14), East => east_2_west(15)(14) , Grant => Signal_grant(15)(14)); 
+
+Arbiter_15_15 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(14)(15), West => east_2_west(14)(14), P => Signal_priority(17), Fifo_full => Fifo_full(15),  
+South => south_2_north(15)(15), East => east_2_west(15)(15) , Grant => Signal_grant(15)(15)); 
+
+Arbiter_15_16 : Arbiter
+
+PORT MAP (Request => Request(256), North => south_2_north(14)(16), West => east_2_west(14)(15), P => Signal_priority(17), Fifo_full => Fifo_full(16),  
+South => south_2_north(15)(16), East => east_2_west(15)(16) , Grant => Signal_grant(15)(16)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(241), North => south_2_north(15)(1), West => east_2_west(15)(16), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(226), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(211), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(196), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(181), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(166), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(151), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+Arbiter_16_10 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10),  
+South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); 
+
+Arbiter_16_11 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11),  
+South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); 
+
+Arbiter_16_12 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12),  
+South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); 
+
+Arbiter_16_13 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(15)(13), West => east_2_west(15)(12), P => Signal_priority(16), Fifo_full => Fifo_full(13),  
+South => south_2_north(16)(13), East => east_2_west(16)(13) , Grant => Signal_grant(16)(13)); 
+
+Arbiter_16_14 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(15)(14), West => east_2_west(15)(13), P => Signal_priority(16), Fifo_full => Fifo_full(14),  
+South => south_2_north(16)(14), East => east_2_west(16)(14) , Grant => Signal_grant(16)(14)); 
+
+Arbiter_16_15 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(15)(15), West => east_2_west(15)(14), P => Signal_priority(16), Fifo_full => Fifo_full(15),  
+South => south_2_north(16)(15), East => east_2_west(16)(15) , Grant => Signal_grant(16)(15)); 
+
+Arbiter_16_16 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(15)(16), West => east_2_west(15)(15), P => Signal_priority(16), Fifo_full => Fifo_full(16),  
+South => south_2_north(16)(16), East => east_2_west(16)(16) , Grant => Signal_grant(16)(16)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(16)(1), West => east_2_west(16)(16), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(242), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(227), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(212), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(197), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(182), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(167), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(152), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+Arbiter_17_10 : Arbiter
+
+PORT MAP (Request => Request(122), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10),  
+South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); 
+
+Arbiter_17_11 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11),  
+South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); 
+
+Arbiter_17_12 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12),  
+South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); 
+
+Arbiter_17_13 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(16)(13), West => east_2_west(16)(12), P => Signal_priority(15), Fifo_full => Fifo_full(13),  
+South => south_2_north(17)(13), East => east_2_west(17)(13) , Grant => Signal_grant(17)(13)); 
+
+Arbiter_17_14 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(16)(14), West => east_2_west(16)(13), P => Signal_priority(15), Fifo_full => Fifo_full(14),  
+South => south_2_north(17)(14), East => east_2_west(17)(14) , Grant => Signal_grant(17)(14)); 
+
+Arbiter_17_15 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(16)(15), West => east_2_west(16)(14), P => Signal_priority(15), Fifo_full => Fifo_full(15),  
+South => south_2_north(17)(15), East => east_2_west(17)(15) , Grant => Signal_grant(17)(15)); 
+
+Arbiter_17_16 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(16)(16), West => east_2_west(16)(15), P => Signal_priority(15), Fifo_full => Fifo_full(16),  
+South => south_2_north(17)(16), East => east_2_west(17)(16) , Grant => Signal_grant(17)(16)); 
+
+-------------------------- Diagonale n° 18 
+
+
+Arbiter_18_1 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(17)(1), West => east_2_west(17)(16), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); 
+
+Arbiter_18_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); 
+
+Arbiter_18_3 : Arbiter
+
+PORT MAP (Request => Request(243), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); 
+
+Arbiter_18_4 : Arbiter
+
+PORT MAP (Request => Request(228), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); 
+
+Arbiter_18_5 : Arbiter
+
+PORT MAP (Request => Request(213), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); 
+
+Arbiter_18_6 : Arbiter
+
+PORT MAP (Request => Request(198), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); 
+
+Arbiter_18_7 : Arbiter
+
+PORT MAP (Request => Request(183), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); 
+
+Arbiter_18_8 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); 
+
+Arbiter_18_9 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); 
+
+Arbiter_18_10 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10),  
+South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); 
+
+Arbiter_18_11 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11),  
+South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); 
+
+Arbiter_18_12 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12),  
+South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); 
+
+Arbiter_18_13 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(17)(13), West => east_2_west(17)(12), P => Signal_priority(14), Fifo_full => Fifo_full(13),  
+South => south_2_north(18)(13), East => east_2_west(18)(13) , Grant => Signal_grant(18)(13)); 
+
+Arbiter_18_14 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(17)(14), West => east_2_west(17)(13), P => Signal_priority(14), Fifo_full => Fifo_full(14),  
+South => south_2_north(18)(14), East => east_2_west(18)(14) , Grant => Signal_grant(18)(14)); 
+
+Arbiter_18_15 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(17)(15), West => east_2_west(17)(14), P => Signal_priority(14), Fifo_full => Fifo_full(15),  
+South => south_2_north(18)(15), East => east_2_west(18)(15) , Grant => Signal_grant(18)(15)); 
+
+Arbiter_18_16 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(17)(16), West => east_2_west(17)(15), P => Signal_priority(14), Fifo_full => Fifo_full(16),  
+South => south_2_north(18)(16), East => east_2_west(18)(16) , Grant => Signal_grant(18)(16)); 
+
+-------------------------- Diagonale n° 19 
+
+
+Arbiter_19_1 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(18)(1), West => east_2_west(18)(16), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); 
+
+Arbiter_19_2 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); 
+
+Arbiter_19_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); 
+
+Arbiter_19_4 : Arbiter
+
+PORT MAP (Request => Request(244), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); 
+
+Arbiter_19_5 : Arbiter
+
+PORT MAP (Request => Request(229), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); 
+
+Arbiter_19_6 : Arbiter
+
+PORT MAP (Request => Request(214), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); 
+
+Arbiter_19_7 : Arbiter
+
+PORT MAP (Request => Request(199), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); 
+
+Arbiter_19_8 : Arbiter
+
+PORT MAP (Request => Request(184), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); 
+
+Arbiter_19_9 : Arbiter
+
+PORT MAP (Request => Request(169), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); 
+
+Arbiter_19_10 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10),  
+South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); 
+
+Arbiter_19_11 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11),  
+South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); 
+
+Arbiter_19_12 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12),  
+South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); 
+
+Arbiter_19_13 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(18)(13), West => east_2_west(18)(12), P => Signal_priority(13), Fifo_full => Fifo_full(13),  
+South => south_2_north(19)(13), East => east_2_west(19)(13) , Grant => Signal_grant(19)(13)); 
+
+Arbiter_19_14 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(18)(14), West => east_2_west(18)(13), P => Signal_priority(13), Fifo_full => Fifo_full(14),  
+South => south_2_north(19)(14), East => east_2_west(19)(14) , Grant => Signal_grant(19)(14)); 
+
+Arbiter_19_15 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(18)(15), West => east_2_west(18)(14), P => Signal_priority(13), Fifo_full => Fifo_full(15),  
+South => south_2_north(19)(15), East => east_2_west(19)(15) , Grant => Signal_grant(19)(15)); 
+
+Arbiter_19_16 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(18)(16), West => east_2_west(18)(15), P => Signal_priority(13), Fifo_full => Fifo_full(16),  
+South => south_2_north(19)(16), East => east_2_west(19)(16) , Grant => Signal_grant(19)(16)); 
+
+-------------------------- Diagonale n° 20 
+
+
+Arbiter_20_1 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(19)(1), West => east_2_west(19)(16), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); 
+
+Arbiter_20_2 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); 
+
+Arbiter_20_3 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); 
+
+Arbiter_20_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); 
+
+Arbiter_20_5 : Arbiter
+
+PORT MAP (Request => Request(245), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); 
+
+Arbiter_20_6 : Arbiter
+
+PORT MAP (Request => Request(230), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); 
+
+Arbiter_20_7 : Arbiter
+
+PORT MAP (Request => Request(215), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); 
+
+Arbiter_20_8 : Arbiter
+
+PORT MAP (Request => Request(200), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); 
+
+Arbiter_20_9 : Arbiter
+
+PORT MAP (Request => Request(185), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); 
+
+Arbiter_20_10 : Arbiter
+
+PORT MAP (Request => Request(170), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10),  
+South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); 
+
+Arbiter_20_11 : Arbiter
+
+PORT MAP (Request => Request(155), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11),  
+South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); 
+
+Arbiter_20_12 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12),  
+South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); 
+
+Arbiter_20_13 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(19)(13), West => east_2_west(19)(12), P => Signal_priority(12), Fifo_full => Fifo_full(13),  
+South => south_2_north(20)(13), East => east_2_west(20)(13) , Grant => Signal_grant(20)(13)); 
+
+Arbiter_20_14 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(19)(14), West => east_2_west(19)(13), P => Signal_priority(12), Fifo_full => Fifo_full(14),  
+South => south_2_north(20)(14), East => east_2_west(20)(14) , Grant => Signal_grant(20)(14)); 
+
+Arbiter_20_15 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(19)(15), West => east_2_west(19)(14), P => Signal_priority(12), Fifo_full => Fifo_full(15),  
+South => south_2_north(20)(15), East => east_2_west(20)(15) , Grant => Signal_grant(20)(15)); 
+
+Arbiter_20_16 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(19)(16), West => east_2_west(19)(15), P => Signal_priority(12), Fifo_full => Fifo_full(16),  
+South => south_2_north(20)(16), East => east_2_west(20)(16) , Grant => Signal_grant(20)(16)); 
+
+-------------------------- Diagonale n° 21 
+
+
+Arbiter_21_1 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(20)(1), West => east_2_west(20)(16), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); 
+
+Arbiter_21_2 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); 
+
+Arbiter_21_3 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); 
+
+Arbiter_21_4 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); 
+
+Arbiter_21_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); 
+
+Arbiter_21_6 : Arbiter
+
+PORT MAP (Request => Request(246), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); 
+
+Arbiter_21_7 : Arbiter
+
+PORT MAP (Request => Request(231), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); 
+
+Arbiter_21_8 : Arbiter
+
+PORT MAP (Request => Request(216), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); 
+
+Arbiter_21_9 : Arbiter
+
+PORT MAP (Request => Request(201), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); 
+
+Arbiter_21_10 : Arbiter
+
+PORT MAP (Request => Request(186), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10),  
+South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); 
+
+Arbiter_21_11 : Arbiter
+
+PORT MAP (Request => Request(171), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11),  
+South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); 
+
+Arbiter_21_12 : Arbiter
+
+PORT MAP (Request => Request(156), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12),  
+South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); 
+
+Arbiter_21_13 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(20)(13), West => east_2_west(20)(12), P => Signal_priority(11), Fifo_full => Fifo_full(13),  
+South => south_2_north(21)(13), East => east_2_west(21)(13) , Grant => Signal_grant(21)(13)); 
+
+Arbiter_21_14 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(20)(14), West => east_2_west(20)(13), P => Signal_priority(11), Fifo_full => Fifo_full(14),  
+South => south_2_north(21)(14), East => east_2_west(21)(14) , Grant => Signal_grant(21)(14)); 
+
+Arbiter_21_15 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(20)(15), West => east_2_west(20)(14), P => Signal_priority(11), Fifo_full => Fifo_full(15),  
+South => south_2_north(21)(15), East => east_2_west(21)(15) , Grant => Signal_grant(21)(15)); 
+
+Arbiter_21_16 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(20)(16), West => east_2_west(20)(15), P => Signal_priority(11), Fifo_full => Fifo_full(16),  
+South => south_2_north(21)(16), East => east_2_west(21)(16) , Grant => Signal_grant(21)(16)); 
+
+-------------------------- Diagonale n° 22 
+
+
+Arbiter_22_1 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(21)(1), West => east_2_west(21)(16), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); 
+
+Arbiter_22_2 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); 
+
+Arbiter_22_3 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); 
+
+Arbiter_22_4 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); 
+
+Arbiter_22_5 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); 
+
+Arbiter_22_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); 
+
+Arbiter_22_7 : Arbiter
+
+PORT MAP (Request => Request(247), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); 
+
+Arbiter_22_8 : Arbiter
+
+PORT MAP (Request => Request(232), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); 
+
+Arbiter_22_9 : Arbiter
+
+PORT MAP (Request => Request(217), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); 
+
+Arbiter_22_10 : Arbiter
+
+PORT MAP (Request => Request(202), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10),  
+South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); 
+
+Arbiter_22_11 : Arbiter
+
+PORT MAP (Request => Request(187), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11),  
+South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); 
+
+Arbiter_22_12 : Arbiter
+
+PORT MAP (Request => Request(172), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12),  
+South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); 
+
+Arbiter_22_13 : Arbiter
+
+PORT MAP (Request => Request(157), North => south_2_north(21)(13), West => east_2_west(21)(12), P => Signal_priority(10), Fifo_full => Fifo_full(13),  
+South => south_2_north(22)(13), East => east_2_west(22)(13) , Grant => Signal_grant(22)(13)); 
+
+Arbiter_22_14 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(21)(14), West => east_2_west(21)(13), P => Signal_priority(10), Fifo_full => Fifo_full(14),  
+South => south_2_north(22)(14), East => east_2_west(22)(14) , Grant => Signal_grant(22)(14)); 
+
+Arbiter_22_15 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(21)(15), West => east_2_west(21)(14), P => Signal_priority(10), Fifo_full => Fifo_full(15),  
+South => south_2_north(22)(15), East => east_2_west(22)(15) , Grant => Signal_grant(22)(15)); 
+
+Arbiter_22_16 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(21)(16), West => east_2_west(21)(15), P => Signal_priority(10), Fifo_full => Fifo_full(16),  
+South => south_2_north(22)(16), East => east_2_west(22)(16) , Grant => Signal_grant(22)(16)); 
+
+-------------------------- Diagonale n° 23 
+
+
+Arbiter_23_1 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(22)(1), West => east_2_west(22)(16), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); 
+
+Arbiter_23_2 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); 
+
+Arbiter_23_3 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); 
+
+Arbiter_23_4 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); 
+
+Arbiter_23_5 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); 
+
+Arbiter_23_6 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); 
+
+Arbiter_23_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); 
+
+Arbiter_23_8 : Arbiter
+
+PORT MAP (Request => Request(248), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); 
+
+Arbiter_23_9 : Arbiter
+
+PORT MAP (Request => Request(233), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); 
+
+Arbiter_23_10 : Arbiter
+
+PORT MAP (Request => Request(218), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10),  
+South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); 
+
+Arbiter_23_11 : Arbiter
+
+PORT MAP (Request => Request(203), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11),  
+South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); 
+
+Arbiter_23_12 : Arbiter
+
+PORT MAP (Request => Request(188), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12),  
+South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); 
+
+Arbiter_23_13 : Arbiter
+
+PORT MAP (Request => Request(173), North => south_2_north(22)(13), West => east_2_west(22)(12), P => Signal_priority(9), Fifo_full => Fifo_full(13),  
+South => south_2_north(23)(13), East => east_2_west(23)(13) , Grant => Signal_grant(23)(13)); 
+
+Arbiter_23_14 : Arbiter
+
+PORT MAP (Request => Request(158), North => south_2_north(22)(14), West => east_2_west(22)(13), P => Signal_priority(9), Fifo_full => Fifo_full(14),  
+South => south_2_north(23)(14), East => east_2_west(23)(14) , Grant => Signal_grant(23)(14)); 
+
+Arbiter_23_15 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(22)(15), West => east_2_west(22)(14), P => Signal_priority(9), Fifo_full => Fifo_full(15),  
+South => south_2_north(23)(15), East => east_2_west(23)(15) , Grant => Signal_grant(23)(15)); 
+
+Arbiter_23_16 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(22)(16), West => east_2_west(22)(15), P => Signal_priority(9), Fifo_full => Fifo_full(16),  
+South => south_2_north(23)(16), East => east_2_west(23)(16) , Grant => Signal_grant(23)(16)); 
+
+-------------------------- Diagonale n° 24 
+
+
+Arbiter_24_1 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(23)(1), West => east_2_west(23)(16), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(24)(1), East => east_2_west(24)(1) , Grant => Signal_grant(24)(1)); 
+
+Arbiter_24_2 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(23)(2), West => east_2_west(23)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(24)(2), East => east_2_west(24)(2) , Grant => Signal_grant(24)(2)); 
+
+Arbiter_24_3 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(23)(3), West => east_2_west(23)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(24)(3), East => east_2_west(24)(3) , Grant => Signal_grant(24)(3)); 
+
+Arbiter_24_4 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(23)(4), West => east_2_west(23)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(24)(4), East => east_2_west(24)(4) , Grant => Signal_grant(24)(4)); 
+
+Arbiter_24_5 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(23)(5), West => east_2_west(23)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(24)(5), East => east_2_west(24)(5) , Grant => Signal_grant(24)(5)); 
+
+Arbiter_24_6 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(23)(6), West => east_2_west(23)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(24)(6), East => east_2_west(24)(6) , Grant => Signal_grant(24)(6)); 
+
+Arbiter_24_7 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(23)(7), West => east_2_west(23)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(24)(7), East => east_2_west(24)(7) , Grant => Signal_grant(24)(7)); 
+
+Arbiter_24_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(23)(8), West => east_2_west(23)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(24)(8), East => east_2_west(24)(8) , Grant => Signal_grant(24)(8)); 
+
+Arbiter_24_9 : Arbiter
+
+PORT MAP (Request => Request(249), North => south_2_north(23)(9), West => east_2_west(23)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(24)(9), East => east_2_west(24)(9) , Grant => Signal_grant(24)(9)); 
+
+Arbiter_24_10 : Arbiter
+
+PORT MAP (Request => Request(234), North => south_2_north(23)(10), West => east_2_west(23)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10),  
+South => south_2_north(24)(10), East => east_2_west(24)(10) , Grant => Signal_grant(24)(10)); 
+
+Arbiter_24_11 : Arbiter
+
+PORT MAP (Request => Request(219), North => south_2_north(23)(11), West => east_2_west(23)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11),  
+South => south_2_north(24)(11), East => east_2_west(24)(11) , Grant => Signal_grant(24)(11)); 
+
+Arbiter_24_12 : Arbiter
+
+PORT MAP (Request => Request(204), North => south_2_north(23)(12), West => east_2_west(23)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12),  
+South => south_2_north(24)(12), East => east_2_west(24)(12) , Grant => Signal_grant(24)(12)); 
+
+Arbiter_24_13 : Arbiter
+
+PORT MAP (Request => Request(189), North => south_2_north(23)(13), West => east_2_west(23)(12), P => Signal_priority(8), Fifo_full => Fifo_full(13),  
+South => south_2_north(24)(13), East => east_2_west(24)(13) , Grant => Signal_grant(24)(13)); 
+
+Arbiter_24_14 : Arbiter
+
+PORT MAP (Request => Request(174), North => south_2_north(23)(14), West => east_2_west(23)(13), P => Signal_priority(8), Fifo_full => Fifo_full(14),  
+South => south_2_north(24)(14), East => east_2_west(24)(14) , Grant => Signal_grant(24)(14)); 
+
+Arbiter_24_15 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(23)(15), West => east_2_west(23)(14), P => Signal_priority(8), Fifo_full => Fifo_full(15),  
+South => south_2_north(24)(15), East => east_2_west(24)(15) , Grant => Signal_grant(24)(15)); 
+
+Arbiter_24_16 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(23)(16), West => east_2_west(23)(15), P => Signal_priority(8), Fifo_full => Fifo_full(16),  
+South => south_2_north(24)(16), East => east_2_west(24)(16) , Grant => Signal_grant(24)(16)); 
+
+-------------------------- Diagonale n° 25 
+
+
+Arbiter_25_1 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(24)(1), West => east_2_west(24)(16), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(25)(1), East => east_2_west(25)(1) , Grant => Signal_grant(25)(1)); 
+
+Arbiter_25_2 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(24)(2), West => east_2_west(24)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(25)(2), East => east_2_west(25)(2) , Grant => Signal_grant(25)(2)); 
+
+Arbiter_25_3 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(24)(3), West => east_2_west(24)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(25)(3), East => east_2_west(25)(3) , Grant => Signal_grant(25)(3)); 
+
+Arbiter_25_4 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(24)(4), West => east_2_west(24)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(25)(4), East => east_2_west(25)(4) , Grant => Signal_grant(25)(4)); 
+
+Arbiter_25_5 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(24)(5), West => east_2_west(24)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(25)(5), East => east_2_west(25)(5) , Grant => Signal_grant(25)(5)); 
+
+Arbiter_25_6 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(24)(6), West => east_2_west(24)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(25)(6), East => east_2_west(25)(6) , Grant => Signal_grant(25)(6)); 
+
+Arbiter_25_7 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(24)(7), West => east_2_west(24)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(25)(7), East => east_2_west(25)(7) , Grant => Signal_grant(25)(7)); 
+
+Arbiter_25_8 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(24)(8), West => east_2_west(24)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(25)(8), East => east_2_west(25)(8) , Grant => Signal_grant(25)(8)); 
+
+Arbiter_25_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(24)(9), West => east_2_west(24)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(25)(9), East => east_2_west(25)(9) , Grant => Signal_grant(25)(9)); 
+
+Arbiter_25_10 : Arbiter
+
+PORT MAP (Request => Request(250), North => south_2_north(24)(10), West => east_2_west(24)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10),  
+South => south_2_north(25)(10), East => east_2_west(25)(10) , Grant => Signal_grant(25)(10)); 
+
+Arbiter_25_11 : Arbiter
+
+PORT MAP (Request => Request(235), North => south_2_north(24)(11), West => east_2_west(24)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11),  
+South => south_2_north(25)(11), East => east_2_west(25)(11) , Grant => Signal_grant(25)(11)); 
+
+Arbiter_25_12 : Arbiter
+
+PORT MAP (Request => Request(220), North => south_2_north(24)(12), West => east_2_west(24)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12),  
+South => south_2_north(25)(12), East => east_2_west(25)(12) , Grant => Signal_grant(25)(12)); 
+
+Arbiter_25_13 : Arbiter
+
+PORT MAP (Request => Request(205), North => south_2_north(24)(13), West => east_2_west(24)(12), P => Signal_priority(7), Fifo_full => Fifo_full(13),  
+South => south_2_north(25)(13), East => east_2_west(25)(13) , Grant => Signal_grant(25)(13)); 
+
+Arbiter_25_14 : Arbiter
+
+PORT MAP (Request => Request(190), North => south_2_north(24)(14), West => east_2_west(24)(13), P => Signal_priority(7), Fifo_full => Fifo_full(14),  
+South => south_2_north(25)(14), East => east_2_west(25)(14) , Grant => Signal_grant(25)(14)); 
+
+Arbiter_25_15 : Arbiter
+
+PORT MAP (Request => Request(175), North => south_2_north(24)(15), West => east_2_west(24)(14), P => Signal_priority(7), Fifo_full => Fifo_full(15),  
+South => south_2_north(25)(15), East => east_2_west(25)(15) , Grant => Signal_grant(25)(15)); 
+
+Arbiter_25_16 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(24)(16), West => east_2_west(24)(15), P => Signal_priority(7), Fifo_full => Fifo_full(16),  
+South => south_2_north(25)(16), East => east_2_west(25)(16) , Grant => Signal_grant(25)(16)); 
+
+-------------------------- Diagonale n° 26 
+
+
+Arbiter_26_1 : Arbiter
+
+PORT MAP (Request => Request(145), North => south_2_north(25)(1), West => east_2_west(25)(16), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(26)(1), East => east_2_west(26)(1) , Grant => Signal_grant(26)(1)); 
+
+Arbiter_26_2 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(25)(2), West => east_2_west(25)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(26)(2), East => east_2_west(26)(2) , Grant => Signal_grant(26)(2)); 
+
+Arbiter_26_3 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(25)(3), West => east_2_west(25)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(26)(3), East => east_2_west(26)(3) , Grant => Signal_grant(26)(3)); 
+
+Arbiter_26_4 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(25)(4), West => east_2_west(25)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(26)(4), East => east_2_west(26)(4) , Grant => Signal_grant(26)(4)); 
+
+Arbiter_26_5 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(25)(5), West => east_2_west(25)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(26)(5), East => east_2_west(26)(5) , Grant => Signal_grant(26)(5)); 
+
+Arbiter_26_6 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(25)(6), West => east_2_west(25)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(26)(6), East => east_2_west(26)(6) , Grant => Signal_grant(26)(6)); 
+
+Arbiter_26_7 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(25)(7), West => east_2_west(25)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(26)(7), East => east_2_west(26)(7) , Grant => Signal_grant(26)(7)); 
+
+Arbiter_26_8 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(25)(8), West => east_2_west(25)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(26)(8), East => east_2_west(26)(8) , Grant => Signal_grant(26)(8)); 
+
+Arbiter_26_9 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(25)(9), West => east_2_west(25)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(26)(9), East => east_2_west(26)(9) , Grant => Signal_grant(26)(9)); 
+
+Arbiter_26_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(25)(10), West => east_2_west(25)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10),  
+South => south_2_north(26)(10), East => east_2_west(26)(10) , Grant => Signal_grant(26)(10)); 
+
+Arbiter_26_11 : Arbiter
+
+PORT MAP (Request => Request(251), North => south_2_north(25)(11), West => east_2_west(25)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11),  
+South => south_2_north(26)(11), East => east_2_west(26)(11) , Grant => Signal_grant(26)(11)); 
+
+Arbiter_26_12 : Arbiter
+
+PORT MAP (Request => Request(236), North => south_2_north(25)(12), West => east_2_west(25)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12),  
+South => south_2_north(26)(12), East => east_2_west(26)(12) , Grant => Signal_grant(26)(12)); 
+
+Arbiter_26_13 : Arbiter
+
+PORT MAP (Request => Request(221), North => south_2_north(25)(13), West => east_2_west(25)(12), P => Signal_priority(6), Fifo_full => Fifo_full(13),  
+South => south_2_north(26)(13), East => east_2_west(26)(13) , Grant => Signal_grant(26)(13)); 
+
+Arbiter_26_14 : Arbiter
+
+PORT MAP (Request => Request(206), North => south_2_north(25)(14), West => east_2_west(25)(13), P => Signal_priority(6), Fifo_full => Fifo_full(14),  
+South => south_2_north(26)(14), East => east_2_west(26)(14) , Grant => Signal_grant(26)(14)); 
+
+Arbiter_26_15 : Arbiter
+
+PORT MAP (Request => Request(191), North => south_2_north(25)(15), West => east_2_west(25)(14), P => Signal_priority(6), Fifo_full => Fifo_full(15),  
+South => south_2_north(26)(15), East => east_2_west(26)(15) , Grant => Signal_grant(26)(15)); 
+
+Arbiter_26_16 : Arbiter
+
+PORT MAP (Request => Request(176), North => south_2_north(25)(16), West => east_2_west(25)(15), P => Signal_priority(6), Fifo_full => Fifo_full(16),  
+South => south_2_north(26)(16), East => east_2_west(26)(16) , Grant => Signal_grant(26)(16)); 
+
+-------------------------- Diagonale n° 27 
+
+
+Arbiter_27_1 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(26)(1), West => east_2_west(26)(16), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(27)(1), East => east_2_west(27)(1) , Grant => Signal_grant(27)(1)); 
+
+Arbiter_27_2 : Arbiter
+
+PORT MAP (Request => Request(146), North => south_2_north(26)(2), West => east_2_west(26)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(27)(2), East => east_2_west(27)(2) , Grant => Signal_grant(27)(2)); 
+
+Arbiter_27_3 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(26)(3), West => east_2_west(26)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(27)(3), East => east_2_west(27)(3) , Grant => Signal_grant(27)(3)); 
+
+Arbiter_27_4 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(26)(4), West => east_2_west(26)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(27)(4), East => east_2_west(27)(4) , Grant => Signal_grant(27)(4)); 
+
+Arbiter_27_5 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(26)(5), West => east_2_west(26)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(27)(5), East => east_2_west(27)(5) , Grant => Signal_grant(27)(5)); 
+
+Arbiter_27_6 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(26)(6), West => east_2_west(26)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(27)(6), East => east_2_west(27)(6) , Grant => Signal_grant(27)(6)); 
+
+Arbiter_27_7 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(26)(7), West => east_2_west(26)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(27)(7), East => east_2_west(27)(7) , Grant => Signal_grant(27)(7)); 
+
+Arbiter_27_8 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(26)(8), West => east_2_west(26)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(27)(8), East => east_2_west(27)(8) , Grant => Signal_grant(27)(8)); 
+
+Arbiter_27_9 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(26)(9), West => east_2_west(26)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(27)(9), East => east_2_west(27)(9) , Grant => Signal_grant(27)(9)); 
+
+Arbiter_27_10 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(26)(10), West => east_2_west(26)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10),  
+South => south_2_north(27)(10), East => east_2_west(27)(10) , Grant => Signal_grant(27)(10)); 
+
+Arbiter_27_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(26)(11), West => east_2_west(26)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11),  
+South => south_2_north(27)(11), East => east_2_west(27)(11) , Grant => Signal_grant(27)(11)); 
+
+Arbiter_27_12 : Arbiter
+
+PORT MAP (Request => Request(252), North => south_2_north(26)(12), West => east_2_west(26)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12),  
+South => south_2_north(27)(12), East => east_2_west(27)(12) , Grant => Signal_grant(27)(12)); 
+
+Arbiter_27_13 : Arbiter
+
+PORT MAP (Request => Request(237), North => south_2_north(26)(13), West => east_2_west(26)(12), P => Signal_priority(5), Fifo_full => Fifo_full(13),  
+South => south_2_north(27)(13), East => east_2_west(27)(13) , Grant => Signal_grant(27)(13)); 
+
+Arbiter_27_14 : Arbiter
+
+PORT MAP (Request => Request(222), North => south_2_north(26)(14), West => east_2_west(26)(13), P => Signal_priority(5), Fifo_full => Fifo_full(14),  
+South => south_2_north(27)(14), East => east_2_west(27)(14) , Grant => Signal_grant(27)(14)); 
+
+Arbiter_27_15 : Arbiter
+
+PORT MAP (Request => Request(207), North => south_2_north(26)(15), West => east_2_west(26)(14), P => Signal_priority(5), Fifo_full => Fifo_full(15),  
+South => south_2_north(27)(15), East => east_2_west(27)(15) , Grant => Signal_grant(27)(15)); 
+
+Arbiter_27_16 : Arbiter
+
+PORT MAP (Request => Request(192), North => south_2_north(26)(16), West => east_2_west(26)(15), P => Signal_priority(5), Fifo_full => Fifo_full(16),  
+South => south_2_north(27)(16), East => east_2_west(27)(16) , Grant => Signal_grant(27)(16)); 
+
+-------------------------- Diagonale n° 28 
+
+
+Arbiter_28_1 : Arbiter
+
+PORT MAP (Request => Request(177), North => south_2_north(27)(1), West => east_2_west(27)(16), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(28)(1), East => east_2_west(28)(1) , Grant => Signal_grant(28)(1)); 
+
+Arbiter_28_2 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(27)(2), West => east_2_west(27)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(28)(2), East => east_2_west(28)(2) , Grant => Signal_grant(28)(2)); 
+
+Arbiter_28_3 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(27)(3), West => east_2_west(27)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(28)(3), East => east_2_west(28)(3) , Grant => Signal_grant(28)(3)); 
+
+Arbiter_28_4 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(27)(4), West => east_2_west(27)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(28)(4), East => east_2_west(28)(4) , Grant => Signal_grant(28)(4)); 
+
+Arbiter_28_5 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(27)(5), West => east_2_west(27)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(28)(5), East => east_2_west(28)(5) , Grant => Signal_grant(28)(5)); 
+
+Arbiter_28_6 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(27)(6), West => east_2_west(27)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(28)(6), East => east_2_west(28)(6) , Grant => Signal_grant(28)(6)); 
+
+Arbiter_28_7 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(27)(7), West => east_2_west(27)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(28)(7), East => east_2_west(28)(7) , Grant => Signal_grant(28)(7)); 
+
+Arbiter_28_8 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(27)(8), West => east_2_west(27)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(28)(8), East => east_2_west(28)(8) , Grant => Signal_grant(28)(8)); 
+
+Arbiter_28_9 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(27)(9), West => east_2_west(27)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(28)(9), East => east_2_west(28)(9) , Grant => Signal_grant(28)(9)); 
+
+Arbiter_28_10 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(27)(10), West => east_2_west(27)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10),  
+South => south_2_north(28)(10), East => east_2_west(28)(10) , Grant => Signal_grant(28)(10)); 
+
+Arbiter_28_11 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(27)(11), West => east_2_west(27)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11),  
+South => south_2_north(28)(11), East => east_2_west(28)(11) , Grant => Signal_grant(28)(11)); 
+
+Arbiter_28_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(27)(12), West => east_2_west(27)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12),  
+South => south_2_north(28)(12), East => east_2_west(28)(12) , Grant => Signal_grant(28)(12)); 
+
+Arbiter_28_13 : Arbiter
+
+PORT MAP (Request => Request(253), North => south_2_north(27)(13), West => east_2_west(27)(12), P => Signal_priority(4), Fifo_full => Fifo_full(13),  
+South => south_2_north(28)(13), East => east_2_west(28)(13) , Grant => Signal_grant(28)(13)); 
+
+Arbiter_28_14 : Arbiter
+
+PORT MAP (Request => Request(238), North => south_2_north(27)(14), West => east_2_west(27)(13), P => Signal_priority(4), Fifo_full => Fifo_full(14),  
+South => south_2_north(28)(14), East => east_2_west(28)(14) , Grant => Signal_grant(28)(14)); 
+
+Arbiter_28_15 : Arbiter
+
+PORT MAP (Request => Request(223), North => south_2_north(27)(15), West => east_2_west(27)(14), P => Signal_priority(4), Fifo_full => Fifo_full(15),  
+South => south_2_north(28)(15), East => east_2_west(28)(15) , Grant => Signal_grant(28)(15)); 
+
+Arbiter_28_16 : Arbiter
+
+PORT MAP (Request => Request(208), North => south_2_north(27)(16), West => east_2_west(27)(15), P => Signal_priority(4), Fifo_full => Fifo_full(16),  
+South => south_2_north(28)(16), East => east_2_west(28)(16) , Grant => Signal_grant(28)(16)); 
+
+-------------------------- Diagonale n° 29 
+
+
+Arbiter_29_1 : Arbiter
+
+PORT MAP (Request => Request(193), North => south_2_north(28)(1), West => east_2_west(28)(16), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(29)(1), East => east_2_west(29)(1) , Grant => Signal_grant(29)(1)); 
+
+Arbiter_29_2 : Arbiter
+
+PORT MAP (Request => Request(178), North => south_2_north(28)(2), West => east_2_west(28)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(29)(2), East => east_2_west(29)(2) , Grant => Signal_grant(29)(2)); 
+
+Arbiter_29_3 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(28)(3), West => east_2_west(28)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(29)(3), East => east_2_west(29)(3) , Grant => Signal_grant(29)(3)); 
+
+Arbiter_29_4 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(28)(4), West => east_2_west(28)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(29)(4), East => east_2_west(29)(4) , Grant => Signal_grant(29)(4)); 
+
+Arbiter_29_5 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(28)(5), West => east_2_west(28)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(29)(5), East => east_2_west(29)(5) , Grant => Signal_grant(29)(5)); 
+
+Arbiter_29_6 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(28)(6), West => east_2_west(28)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(29)(6), East => east_2_west(29)(6) , Grant => Signal_grant(29)(6)); 
+
+Arbiter_29_7 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(28)(7), West => east_2_west(28)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(29)(7), East => east_2_west(29)(7) , Grant => Signal_grant(29)(7)); 
+
+Arbiter_29_8 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(28)(8), West => east_2_west(28)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(29)(8), East => east_2_west(29)(8) , Grant => Signal_grant(29)(8)); 
+
+Arbiter_29_9 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(28)(9), West => east_2_west(28)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(29)(9), East => east_2_west(29)(9) , Grant => Signal_grant(29)(9)); 
+
+Arbiter_29_10 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(28)(10), West => east_2_west(28)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10),  
+South => south_2_north(29)(10), East => east_2_west(29)(10) , Grant => Signal_grant(29)(10)); 
+
+Arbiter_29_11 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(28)(11), West => east_2_west(28)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11),  
+South => south_2_north(29)(11), East => east_2_west(29)(11) , Grant => Signal_grant(29)(11)); 
+
+Arbiter_29_12 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(28)(12), West => east_2_west(28)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12),  
+South => south_2_north(29)(12), East => east_2_west(29)(12) , Grant => Signal_grant(29)(12)); 
+
+Arbiter_29_13 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(28)(13), West => east_2_west(28)(12), P => Signal_priority(3), Fifo_full => Fifo_full(13),  
+South => south_2_north(29)(13), East => east_2_west(29)(13) , Grant => Signal_grant(29)(13)); 
+
+Arbiter_29_14 : Arbiter
+
+PORT MAP (Request => Request(254), North => south_2_north(28)(14), West => east_2_west(28)(13), P => Signal_priority(3), Fifo_full => Fifo_full(14),  
+South => south_2_north(29)(14), East => east_2_west(29)(14) , Grant => Signal_grant(29)(14)); 
+
+Arbiter_29_15 : Arbiter
+
+PORT MAP (Request => Request(239), North => south_2_north(28)(15), West => east_2_west(28)(14), P => Signal_priority(3), Fifo_full => Fifo_full(15),  
+South => south_2_north(29)(15), East => east_2_west(29)(15) , Grant => Signal_grant(29)(15)); 
+
+Arbiter_29_16 : Arbiter
+
+PORT MAP (Request => Request(224), North => south_2_north(28)(16), West => east_2_west(28)(15), P => Signal_priority(3), Fifo_full => Fifo_full(16),  
+South => south_2_north(29)(16), East => east_2_west(29)(16) , Grant => Signal_grant(29)(16)); 
+
+-------------------------- Diagonale n° 30 
+
+
+Arbiter_30_1 : Arbiter
+
+PORT MAP (Request => Request(209), North => south_2_north(29)(1), West => east_2_west(29)(16), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(30)(1), East => east_2_west(30)(1) , Grant => Signal_grant(30)(1)); 
+
+Arbiter_30_2 : Arbiter
+
+PORT MAP (Request => Request(194), North => south_2_north(29)(2), West => east_2_west(29)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(30)(2), East => east_2_west(30)(2) , Grant => Signal_grant(30)(2)); 
+
+Arbiter_30_3 : Arbiter
+
+PORT MAP (Request => Request(179), North => south_2_north(29)(3), West => east_2_west(29)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(30)(3), East => east_2_west(30)(3) , Grant => Signal_grant(30)(3)); 
+
+Arbiter_30_4 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(29)(4), West => east_2_west(29)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(30)(4), East => east_2_west(30)(4) , Grant => Signal_grant(30)(4)); 
+
+Arbiter_30_5 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(29)(5), West => east_2_west(29)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(30)(5), East => east_2_west(30)(5) , Grant => Signal_grant(30)(5)); 
+
+Arbiter_30_6 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(29)(6), West => east_2_west(29)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(30)(6), East => east_2_west(30)(6) , Grant => Signal_grant(30)(6)); 
+
+Arbiter_30_7 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(29)(7), West => east_2_west(29)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(30)(7), East => east_2_west(30)(7) , Grant => Signal_grant(30)(7)); 
+
+Arbiter_30_8 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(29)(8), West => east_2_west(29)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(30)(8), East => east_2_west(30)(8) , Grant => Signal_grant(30)(8)); 
+
+Arbiter_30_9 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(29)(9), West => east_2_west(29)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(30)(9), East => east_2_west(30)(9) , Grant => Signal_grant(30)(9)); 
+
+Arbiter_30_10 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(29)(10), West => east_2_west(29)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10),  
+South => south_2_north(30)(10), East => east_2_west(30)(10) , Grant => Signal_grant(30)(10)); 
+
+Arbiter_30_11 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(29)(11), West => east_2_west(29)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11),  
+South => south_2_north(30)(11), East => east_2_west(30)(11) , Grant => Signal_grant(30)(11)); 
+
+Arbiter_30_12 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(29)(12), West => east_2_west(29)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12),  
+South => south_2_north(30)(12), East => east_2_west(30)(12) , Grant => Signal_grant(30)(12)); 
+
+Arbiter_30_13 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(29)(13), West => east_2_west(29)(12), P => Signal_priority(2), Fifo_full => Fifo_full(13),  
+South => south_2_north(30)(13), East => east_2_west(30)(13) , Grant => Signal_grant(30)(13)); 
+
+Arbiter_30_14 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(29)(14), West => east_2_west(29)(13), P => Signal_priority(2), Fifo_full => Fifo_full(14),  
+South => south_2_north(30)(14), East => east_2_west(30)(14) , Grant => Signal_grant(30)(14)); 
+
+Arbiter_30_15 : Arbiter
+
+PORT MAP (Request => Request(255), North => south_2_north(29)(15), West => east_2_west(29)(14), P => Signal_priority(2), Fifo_full => Fifo_full(15),  
+South => south_2_north(30)(15), East => east_2_west(30)(15) , Grant => Signal_grant(30)(15)); 
+
+Arbiter_30_16 : Arbiter
+
+PORT MAP (Request => Request(240), North => south_2_north(29)(16), West => east_2_west(29)(15), P => Signal_priority(2), Fifo_full => Fifo_full(16),  
+South => south_2_north(30)(16), East => east_2_west(30)(16) , Grant => Signal_grant(30)(16)); 
+
+-------------------------- Diagonale n° 31 
+
+
+Arbiter_31_1 : Arbiter
+
+PORT MAP (Request => Request(225), North => south_2_north(30)(1), West => east_2_west(30)(16), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(31)(1), East => east_2_west(31)(1) , Grant => Signal_grant(31)(1)); 
+
+Arbiter_31_2 : Arbiter
+
+PORT MAP (Request => Request(210), North => south_2_north(30)(2), West => east_2_west(30)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(31)(2), East => east_2_west(31)(2) , Grant => Signal_grant(31)(2)); 
+
+Arbiter_31_3 : Arbiter
+
+PORT MAP (Request => Request(195), North => south_2_north(30)(3), West => east_2_west(30)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(31)(3), East => east_2_west(31)(3) , Grant => Signal_grant(31)(3)); 
+
+Arbiter_31_4 : Arbiter
+
+PORT MAP (Request => Request(180), North => south_2_north(30)(4), West => east_2_west(30)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(31)(4), East => east_2_west(31)(4) , Grant => Signal_grant(31)(4)); 
+
+Arbiter_31_5 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(30)(5), West => east_2_west(30)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(31)(5), East => east_2_west(31)(5) , Grant => Signal_grant(31)(5)); 
+
+Arbiter_31_6 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(30)(6), West => east_2_west(30)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(31)(6), East => east_2_west(31)(6) , Grant => Signal_grant(31)(6)); 
+
+Arbiter_31_7 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(30)(7), West => east_2_west(30)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(31)(7), East => east_2_west(31)(7) , Grant => Signal_grant(31)(7)); 
+
+Arbiter_31_8 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(30)(8), West => east_2_west(30)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(31)(8), East => east_2_west(31)(8) , Grant => Signal_grant(31)(8)); 
+
+Arbiter_31_9 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(30)(9), West => east_2_west(30)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(31)(9), East => east_2_west(31)(9) , Grant => Signal_grant(31)(9)); 
+
+Arbiter_31_10 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(30)(10), West => east_2_west(30)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10),  
+South => south_2_north(31)(10), East => east_2_west(31)(10) , Grant => Signal_grant(31)(10)); 
+
+Arbiter_31_11 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(30)(11), West => east_2_west(30)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11),  
+South => south_2_north(31)(11), East => east_2_west(31)(11) , Grant => Signal_grant(31)(11)); 
+
+Arbiter_31_12 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(30)(12), West => east_2_west(30)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12),  
+South => south_2_north(31)(12), East => east_2_west(31)(12) , Grant => Signal_grant(31)(12)); 
+
+Arbiter_31_13 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(30)(13), West => east_2_west(30)(12), P => Signal_priority(1), Fifo_full => Fifo_full(13),  
+South => south_2_north(31)(13), East => east_2_west(31)(13) , Grant => Signal_grant(31)(13)); 
+
+Arbiter_31_14 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(30)(14), West => east_2_west(30)(13), P => Signal_priority(1), Fifo_full => Fifo_full(14),  
+South => south_2_north(31)(14), East => east_2_west(31)(14) , Grant => Signal_grant(31)(14)); 
+
+Arbiter_31_15 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(30)(15), West => east_2_west(30)(14), P => Signal_priority(1), Fifo_full => Fifo_full(15),  
+South => south_2_north(31)(15), East => east_2_west(31)(15) , Grant => Signal_grant(31)(15)); 
+
+Arbiter_31_16 : Arbiter
+
+PORT MAP (Request => Request(256), North => south_2_north(30)(16), West => east_2_west(30)(15), P => Signal_priority(1), Fifo_full => Fifo_full(16),  
+South => south_2_north(31)(16), East => east_2_west(31)(16) , Grant => Signal_grant(31)(16)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "1111111111111111000000000000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "1111111111111111000000000000000" => Signal_priority <= "0111111111111111100000000000000";
+		       when "0111111111111111100000000000000" => Signal_priority <= "0011111111111111110000000000000";
+		       when "0011111111111111110000000000000" => Signal_priority <= "0001111111111111111000000000000";
+		       when "0001111111111111111000000000000" => Signal_priority <= "0000111111111111111100000000000";
+		       when "0000111111111111111100000000000" => Signal_priority <= "0000011111111111111110000000000";
+		       when "0000011111111111111110000000000" => Signal_priority <= "0000001111111111111111000000000";
+		       when "0000001111111111111111000000000" => Signal_priority <= "0000000111111111111111100000000";
+		       when "0000000111111111111111100000000" => Signal_priority <= "0000000011111111111111110000000";
+		       when "0000000011111111111111110000000" => Signal_priority <= "0000000001111111111111111000000";
+		       when "0000000001111111111111111000000" => Signal_priority <= "0000000000111111111111111100000";
+		       when "0000000000111111111111111100000" => Signal_priority <= "0000000000011111111111111110000";
+		       when "0000000000011111111111111110000" => Signal_priority <= "0000000000001111111111111111000";
+		       when "0000000000001111111111111111000" => Signal_priority <= "0000000000000111111111111111100";
+		       when "0000000000000111111111111111100" => Signal_priority <= "0000000000000011111111111111110";
+		       when "0000000000000011111111111111110" => Signal_priority <= "0000000000000001111111111111111";
+		       when "0000000000000001111111111111111" => Signal_priority <= "1111111111111111000000000000000";
+		       when others    => Signal_priority <= "1111111111111111000000000000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER2_2.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER2_2.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER2_2.VHD	(revision 20)
@@ -0,0 +1,141 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler2_2 is
+    Port ( Request : in  STD_LOGIC_VECTOR (4 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (2 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (2 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (4 downto 1));
+end Scheduler2_2;
+
+architecture Behavioral of Scheduler2_2 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(3 downto 1) of STD_LOGIC_VECTOR(2 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (3 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(4 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant ,req_grant :  std_logic_vector(4 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 3 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(3)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) ;                      --  Grant(1,2)
+Grant(3)  <= Signal_grant(2)(1) ;                      --  Grant(2,1)
+Grant(4)  <= Signal_grant(1)(2) or Signal_grant(3)(2); --  Grant(2,2)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(4), North => High, West => High, P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(1)(1), West => east_2_west(1)(2), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(2)(1), West => east_2_west(2)(2), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "110";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "110" => Signal_priority <= "011";
+		       when "011" => Signal_priority <= "110";
+		       when others    => Signal_priority <= "110";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER3_3.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER3_3.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER3_3.VHD	(revision 20)
@@ -0,0 +1,198 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler3_3 is
+    Port ( Request : in  STD_LOGIC_VECTOR (9 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (3 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (3 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (9 downto 1));
+end Scheduler3_3;
+
+architecture Behavioral of Scheduler3_3 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(5 downto 1) of STD_LOGIC_VECTOR(3 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (5 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(9 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant,req_grant :  std_logic_vector(9 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 7 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(4)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(5)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) ;                      --  Grant(1,3)
+Grant(4)  <= Signal_grant(2)(1) or Signal_grant(5)(1); --  Grant(2,1)
+Grant(5)  <= Signal_grant(3)(2) ;                      --  Grant(2,2)
+Grant(6)  <= Signal_grant(1)(3) or Signal_grant(4)(3); --  Grant(2,3)
+Grant(7)  <= Signal_grant(3)(1) ;                      --  Grant(3,1)
+Grant(8)  <= Signal_grant(1)(2) or Signal_grant(4)(2); --  Grant(3,2)
+Grant(9)  <= Signal_grant(2)(3) or Signal_grant(5)(3); --  Grant(3,3)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(8), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(6), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(1)(1), West => east_2_west(1)(3), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(2)(1), West => east_2_west(2)(3), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(3)(1), West => east_2_west(3)(3), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(4)(1), West => east_2_west(4)(3), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "11100";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "11100" => Signal_priority <= "01110";
+		       when "01110" => Signal_priority <= "00111";
+		       when "00111" => Signal_priority <= "11100";
+		       when others    => Signal_priority <= "11100";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER3_3.stx
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER3_3.stx	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER3_3.stx	(revision 20)
@@ -0,0 +1,35 @@
+Release 11.1 - xst L.33 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
+--> Parameter TMPDIR set to C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 1.00 secs
+Total CPU time to Xst completion: 0.17 secs
+ 
+--> Parameter xsthdpdir set to C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst
+
+
+Total REAL time to Xst completion: 1.00 secs
+Total CPU time to Xst completion: 0.17 secs
+ 
+--> 
+=========================================================================
+*                          HDL Compilation                              *
+=========================================================================
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/Arbiter.vhd" in Library work.
+Architecture behavioral of Entity arbiter is up to date.
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/SCHEDULER3_3.VHD" in Library work.
+Architecture behavioral of Entity scheduler3_3 is up to date.
+
+
+Total REAL time to Xst completion: 1.00 secs
+Total CPU time to Xst completion: 0.35 secs
+ 
+--> 
+
+Total memory usage is 119772 kilobytes
+
+Number of errors   :    0 (   0 filtered)
+Number of warnings :    0 (   0 filtered)
+Number of infos    :    0 (   0 filtered)
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER3_3.xst
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER3_3.xst	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER3_3.xst	(revision 20)
@@ -0,0 +1,5 @@
+set -tmpdir "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst/projnav.tmp"
+set -xsthdpdir "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst"
+elaborate
+-ifn SCHEDULER3_3.prj
+-ifmt mixed
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER4_4.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER4_4.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER4_4.VHD	(revision 20)
@@ -0,0 +1,278 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler4_4 is
+    Port ( Request : in  STD_LOGIC_VECTOR (16 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (4 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (4 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (16 downto 1));
+end Scheduler4_4;
+
+architecture Behavioral of Scheduler4_4 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(7 downto 1) of STD_LOGIC_VECTOR(4 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (7 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch,req_grant: std_logic_vector(16 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(16 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 15 else 	'0'; 
+
+--latch  qui memorise le signal grant pendant la transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <=  grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(5)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(6)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(7)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) ;                      --  Grant(1,4)
+Grant(5)  <= Signal_grant(2)(1) or Signal_grant(6)(1); --  Grant(2,1)
+Grant(6)  <= Signal_grant(3)(2) or Signal_grant(7)(2); --  Grant(2,2)
+Grant(7)  <= Signal_grant(4)(3) ;                      --  Grant(2,3)
+Grant(8)  <= Signal_grant(1)(4) or Signal_grant(5)(4); --  Grant(2,4)
+Grant(9)  <= Signal_grant(3)(1) or Signal_grant(7)(1); --  Grant(3,1)
+Grant(10)  <= Signal_grant(4)(2) ;                      --  Grant(3,2)
+Grant(11)  <= Signal_grant(1)(3) or Signal_grant(5)(3); --  Grant(3,3)
+Grant(12)  <= Signal_grant(2)(4) or Signal_grant(6)(4); --  Grant(3,4)
+Grant(13)  <= Signal_grant(4)(1) ;                      --  Grant(4,1)
+Grant(14)  <= Signal_grant(1)(2) or Signal_grant(5)(2); --  Grant(4,2)
+Grant(15)  <= Signal_grant(2)(3) or Signal_grant(6)(3); --  Grant(4,3)
+Grant(16)  <= Signal_grant(3)(4) or Signal_grant(7)(4); --  Grant(4,4)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(14), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(11), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(8), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(1)(1), West => east_2_west(1)(4), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(2)(1), West => east_2_west(2)(4), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(3)(1), West => east_2_west(3)(4), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(4)(1), West => east_2_west(4)(4), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(5)(1), West => east_2_west(5)(4), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(6)(1), West => east_2_west(6)(4), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "1111000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "1111000" => Signal_priority <= "0111100";
+		       when "0111100" => Signal_priority <= "0011110";
+		       when "0011110" => Signal_priority <= "0001111";
+		       when "0001111" => Signal_priority <= "1111000";
+		       when others    => Signal_priority <= "1111000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER5_5.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER5_5.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER5_5.VHD	(revision 20)
@@ -0,0 +1,378 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler5_5 is
+    Port ( Request : in  STD_LOGIC_VECTOR (25 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (5 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (5 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (25 downto 1));
+end Scheduler5_5;
+
+architecture Behavioral of Scheduler5_5 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(9 downto 1) of STD_LOGIC_VECTOR(5 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (9 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(25 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant ,req_grant:  std_logic_vector(25 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+  req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when   unsigned(req_grant) = 0 or unsigned(priority_rotation) = 31 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(6)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(7)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(8)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(9)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) ;                      --  Grant(1,5)
+Grant(6)  <= Signal_grant(2)(1) or Signal_grant(7)(1); --  Grant(2,1)
+Grant(7)  <= Signal_grant(3)(2) or Signal_grant(8)(2); --  Grant(2,2)
+Grant(8)  <= Signal_grant(4)(3) or Signal_grant(9)(3); --  Grant(2,3)
+Grant(9)  <= Signal_grant(5)(4) ;                      --  Grant(2,4)
+Grant(10)  <= Signal_grant(1)(5) or Signal_grant(6)(5); --  Grant(2,5)
+Grant(11)  <= Signal_grant(3)(1) or Signal_grant(8)(1); --  Grant(3,1)
+Grant(12)  <= Signal_grant(4)(2) or Signal_grant(9)(2); --  Grant(3,2)
+Grant(13)  <= Signal_grant(5)(3) ;                      --  Grant(3,3)
+Grant(14)  <= Signal_grant(1)(4) or Signal_grant(6)(4); --  Grant(3,4)
+Grant(15)  <= Signal_grant(2)(5) or Signal_grant(7)(5); --  Grant(3,5)
+Grant(16)  <= Signal_grant(4)(1) or Signal_grant(9)(1); --  Grant(4,1)
+Grant(17)  <= Signal_grant(5)(2) ;                      --  Grant(4,2)
+Grant(18)  <= Signal_grant(1)(3) or Signal_grant(6)(3); --  Grant(4,3)
+Grant(19)  <= Signal_grant(2)(4) or Signal_grant(7)(4); --  Grant(4,4)
+Grant(20)  <= Signal_grant(3)(5) or Signal_grant(8)(5); --  Grant(4,5)
+Grant(21)  <= Signal_grant(5)(1) ;                      --  Grant(5,1)
+Grant(22)  <= Signal_grant(1)(2) or Signal_grant(6)(2); --  Grant(5,2)
+Grant(23)  <= Signal_grant(2)(3) or Signal_grant(7)(3); --  Grant(5,3)
+Grant(24)  <= Signal_grant(3)(4) or Signal_grant(8)(4); --  Grant(5,4)
+Grant(25)  <= Signal_grant(4)(5) or Signal_grant(9)(5); --  Grant(5,5)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(22), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(18), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(14), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(10), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(1)(1), West => east_2_west(1)(5), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(2)(1), West => east_2_west(2)(5), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(3)(1), West => east_2_west(3)(5), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(4)(1), West => east_2_west(4)(5), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(5)(1), West => east_2_west(5)(5), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(6)(1), West => east_2_west(6)(5), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(7)(1), West => east_2_west(7)(5), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(8)(1), West => east_2_west(8)(5), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "111110000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "111110000" => Signal_priority <= "011111000";
+		       when "011111000" => Signal_priority <= "001111100";
+		       when "001111100" => Signal_priority <= "000111110";
+		       when "000111110" => Signal_priority <= "000011111";
+		       when "000011111" => Signal_priority <= "111110000";
+		       when others    => Signal_priority <= "111110000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER6_6.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER6_6.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER6_6.VHD	(revision 20)
@@ -0,0 +1,501 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler6_6 is
+    Port ( Request : in  STD_LOGIC_VECTOR (36 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (6 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (6 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (36 downto 1));
+end Scheduler6_6;
+
+architecture Behavioral of Scheduler6_6 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(11 downto 1) of STD_LOGIC_VECTOR(6 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (11 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(36 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant,req_grant :  std_logic_vector(36 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when   unsigned(req_grant) = 0 or unsigned(priority_rotation) = 63 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(7)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(8)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(9)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(10)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(11)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) ;                      --  Grant(1,6)
+Grant(7)  <= Signal_grant(2)(1) or Signal_grant(8)(1); --  Grant(2,1)
+Grant(8)  <= Signal_grant(3)(2) or Signal_grant(9)(2); --  Grant(2,2)
+Grant(9)  <= Signal_grant(4)(3) or Signal_grant(10)(3); --  Grant(2,3)
+Grant(10)  <= Signal_grant(5)(4) or Signal_grant(11)(4); --  Grant(2,4)
+Grant(11)  <= Signal_grant(6)(5) ;                      --  Grant(2,5)
+Grant(12)  <= Signal_grant(1)(6) or Signal_grant(7)(6); --  Grant(2,6)
+Grant(13)  <= Signal_grant(3)(1) or Signal_grant(9)(1); --  Grant(3,1)
+Grant(14)  <= Signal_grant(4)(2) or Signal_grant(10)(2); --  Grant(3,2)
+Grant(15)  <= Signal_grant(5)(3) or Signal_grant(11)(3); --  Grant(3,3)
+Grant(16)  <= Signal_grant(6)(4) ;                      --  Grant(3,4)
+Grant(17)  <= Signal_grant(1)(5) or Signal_grant(7)(5); --  Grant(3,5)
+Grant(18)  <= Signal_grant(2)(6) or Signal_grant(8)(6); --  Grant(3,6)
+Grant(19)  <= Signal_grant(4)(1) or Signal_grant(10)(1); --  Grant(4,1)
+Grant(20)  <= Signal_grant(5)(2) or Signal_grant(11)(2); --  Grant(4,2)
+Grant(21)  <= Signal_grant(6)(3) ;                      --  Grant(4,3)
+Grant(22)  <= Signal_grant(1)(4) or Signal_grant(7)(4); --  Grant(4,4)
+Grant(23)  <= Signal_grant(2)(5) or Signal_grant(8)(5); --  Grant(4,5)
+Grant(24)  <= Signal_grant(3)(6) or Signal_grant(9)(6); --  Grant(4,6)
+Grant(25)  <= Signal_grant(5)(1) or Signal_grant(11)(1); --  Grant(5,1)
+Grant(26)  <= Signal_grant(6)(2) ;                      --  Grant(5,2)
+Grant(27)  <= Signal_grant(1)(3) or Signal_grant(7)(3); --  Grant(5,3)
+Grant(28)  <= Signal_grant(2)(4) or Signal_grant(8)(4); --  Grant(5,4)
+Grant(29)  <= Signal_grant(3)(5) or Signal_grant(9)(5); --  Grant(5,5)
+Grant(30)  <= Signal_grant(4)(6) or Signal_grant(10)(6); --  Grant(5,6)
+Grant(31)  <= Signal_grant(6)(1) ;                      --  Grant(6,1)
+Grant(32)  <= Signal_grant(1)(2) or Signal_grant(7)(2); --  Grant(6,2)
+Grant(33)  <= Signal_grant(2)(3) or Signal_grant(8)(3); --  Grant(6,3)
+Grant(34)  <= Signal_grant(3)(4) or Signal_grant(9)(4); --  Grant(6,4)
+Grant(35)  <= Signal_grant(4)(5) or Signal_grant(10)(5); --  Grant(6,5)
+Grant(36)  <= Signal_grant(5)(6) or Signal_grant(11)(6); --  Grant(6,6)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(32), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(27), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(22), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(17), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(12), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(1)(1), West => east_2_west(1)(6), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(2)(1), West => east_2_west(2)(6), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(3)(1), West => east_2_west(3)(6), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(4)(1), West => east_2_west(4)(6), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(5)(1), West => east_2_west(5)(6), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(6)(1), West => east_2_west(6)(6), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(7)(1), West => east_2_west(7)(6), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(8)(1), West => east_2_west(8)(6), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(9)(1), West => east_2_west(9)(6), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(10)(1), West => east_2_west(10)(6), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "11111100000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "11111100000" => Signal_priority <= "01111110000";
+		       when "01111110000" => Signal_priority <= "00111111000";
+		       when "00111111000" => Signal_priority <= "00011111100";
+		       when "00011111100" => Signal_priority <= "00001111110";
+		       when "00001111110" => Signal_priority <= "00000111111";
+		       when "00000111111" => Signal_priority <= "11111100000";
+		       when others    => Signal_priority <= "11111100000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER7_7.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER7_7.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER7_7.VHD	(revision 20)
@@ -0,0 +1,646 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler7_7 is
+    Port ( Request : in  STD_LOGIC_VECTOR (49 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (7 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (7 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (49 downto 1));
+end Scheduler7_7;
+
+architecture Behavioral of Scheduler7_7 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(13 downto 1) of STD_LOGIC_VECTOR(7 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (13 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(49 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant,req_grant :  std_logic_vector(49 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when   unsigned(req_grant) = 0 or unsigned(priority_rotation) = 127 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(8)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(9)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(10)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(11)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(12)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(13)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) ;                      --  Grant(1,7)
+Grant(8)  <= Signal_grant(2)(1) or Signal_grant(9)(1); --  Grant(2,1)
+Grant(9)  <= Signal_grant(3)(2) or Signal_grant(10)(2); --  Grant(2,2)
+Grant(10)  <= Signal_grant(4)(3) or Signal_grant(11)(3); --  Grant(2,3)
+Grant(11)  <= Signal_grant(5)(4) or Signal_grant(12)(4); --  Grant(2,4)
+Grant(12)  <= Signal_grant(6)(5) or Signal_grant(13)(5); --  Grant(2,5)
+Grant(13)  <= Signal_grant(7)(6) ;                      --  Grant(2,6)
+Grant(14)  <= Signal_grant(1)(7) or Signal_grant(8)(7); --  Grant(2,7)
+Grant(15)  <= Signal_grant(3)(1) or Signal_grant(10)(1); --  Grant(3,1)
+Grant(16)  <= Signal_grant(4)(2) or Signal_grant(11)(2); --  Grant(3,2)
+Grant(17)  <= Signal_grant(5)(3) or Signal_grant(12)(3); --  Grant(3,3)
+Grant(18)  <= Signal_grant(6)(4) or Signal_grant(13)(4); --  Grant(3,4)
+Grant(19)  <= Signal_grant(7)(5) ;                      --  Grant(3,5)
+Grant(20)  <= Signal_grant(1)(6) or Signal_grant(8)(6); --  Grant(3,6)
+Grant(21)  <= Signal_grant(2)(7) or Signal_grant(9)(7); --  Grant(3,7)
+Grant(22)  <= Signal_grant(4)(1) or Signal_grant(11)(1); --  Grant(4,1)
+Grant(23)  <= Signal_grant(5)(2) or Signal_grant(12)(2); --  Grant(4,2)
+Grant(24)  <= Signal_grant(6)(3) or Signal_grant(13)(3); --  Grant(4,3)
+Grant(25)  <= Signal_grant(7)(4) ;                      --  Grant(4,4)
+Grant(26)  <= Signal_grant(1)(5) or Signal_grant(8)(5); --  Grant(4,5)
+Grant(27)  <= Signal_grant(2)(6) or Signal_grant(9)(6); --  Grant(4,6)
+Grant(28)  <= Signal_grant(3)(7) or Signal_grant(10)(7); --  Grant(4,7)
+Grant(29)  <= Signal_grant(5)(1) or Signal_grant(12)(1); --  Grant(5,1)
+Grant(30)  <= Signal_grant(6)(2) or Signal_grant(13)(2); --  Grant(5,2)
+Grant(31)  <= Signal_grant(7)(3) ;                      --  Grant(5,3)
+Grant(32)  <= Signal_grant(1)(4) or Signal_grant(8)(4); --  Grant(5,4)
+Grant(33)  <= Signal_grant(2)(5) or Signal_grant(9)(5); --  Grant(5,5)
+Grant(34)  <= Signal_grant(3)(6) or Signal_grant(10)(6); --  Grant(5,6)
+Grant(35)  <= Signal_grant(4)(7) or Signal_grant(11)(7); --  Grant(5,7)
+Grant(36)  <= Signal_grant(6)(1) or Signal_grant(13)(1); --  Grant(6,1)
+Grant(37)  <= Signal_grant(7)(2) ;                      --  Grant(6,2)
+Grant(38)  <= Signal_grant(1)(3) or Signal_grant(8)(3); --  Grant(6,3)
+Grant(39)  <= Signal_grant(2)(4) or Signal_grant(9)(4); --  Grant(6,4)
+Grant(40)  <= Signal_grant(3)(5) or Signal_grant(10)(5); --  Grant(6,5)
+Grant(41)  <= Signal_grant(4)(6) or Signal_grant(11)(6); --  Grant(6,6)
+Grant(42)  <= Signal_grant(5)(7) or Signal_grant(12)(7); --  Grant(6,7)
+Grant(43)  <= Signal_grant(7)(1) ;                      --  Grant(7,1)
+Grant(44)  <= Signal_grant(1)(2) or Signal_grant(8)(2); --  Grant(7,2)
+Grant(45)  <= Signal_grant(2)(3) or Signal_grant(9)(3); --  Grant(7,3)
+Grant(46)  <= Signal_grant(3)(4) or Signal_grant(10)(4); --  Grant(7,4)
+Grant(47)  <= Signal_grant(4)(5) or Signal_grant(11)(5); --  Grant(7,5)
+Grant(48)  <= Signal_grant(5)(6) or Signal_grant(12)(6); --  Grant(7,6)
+Grant(49)  <= Signal_grant(6)(7) or Signal_grant(13)(7); --  Grant(7,7)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(44), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(38), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(32), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(26), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(20), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(14), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(1)(1), West => east_2_west(1)(7), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(2)(1), West => east_2_west(2)(7), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(3)(1), West => east_2_west(3)(7), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(4)(1), West => east_2_west(4)(7), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(5)(1), West => east_2_west(5)(7), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(6)(1), West => east_2_west(6)(7), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(7)(1), West => east_2_west(7)(7), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(8)(1), West => east_2_west(8)(7), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(9)(1), West => east_2_west(9)(7), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(10)(1), West => east_2_west(10)(7), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(11)(1), West => east_2_west(11)(7), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(12)(1), West => east_2_west(12)(7), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "1111111000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "1111111000000" => Signal_priority <= "0111111100000";
+		       when "0111111100000" => Signal_priority <= "0011111110000";
+		       when "0011111110000" => Signal_priority <= "0001111111000";
+		       when "0001111111000" => Signal_priority <= "0000111111100";
+		       when "0000111111100" => Signal_priority <= "0000011111110";
+		       when "0000011111110" => Signal_priority <= "0000001111111";
+		       when "0000001111111" => Signal_priority <= "1111111000000";
+		       when others    => Signal_priority <= "1111111000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER8_8.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER8_8.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER8_8.VHD	(revision 20)
@@ -0,0 +1,813 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler8_8 is
+    Port ( Request : in  STD_LOGIC_VECTOR (64 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (8 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (8 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (64 downto 1));
+end Scheduler8_8;
+
+architecture Behavioral of Scheduler8_8 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(15 downto 1) of STD_LOGIC_VECTOR(8 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (15 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(64 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant,req_grant :  std_logic_vector(64 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when  unsigned(req_grant) = 0 or unsigned(priority_rotation) = 255 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' or unsigned(Grant_latch)=0 then 
+	   grant_latch <= Grant;
+   end if; 
+   end if; 
+ end process; 
+ port_grant <=  grant_latch ; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(9)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(10)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(11)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(12)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(13)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(14)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(15)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) ;                      --  Grant(1,8)
+Grant(9)  <= Signal_grant(2)(1) or Signal_grant(10)(1); --  Grant(2,1)
+Grant(10)  <= Signal_grant(3)(2) or Signal_grant(11)(2); --  Grant(2,2)
+Grant(11)  <= Signal_grant(4)(3) or Signal_grant(12)(3); --  Grant(2,3)
+Grant(12)  <= Signal_grant(5)(4) or Signal_grant(13)(4); --  Grant(2,4)
+Grant(13)  <= Signal_grant(6)(5) or Signal_grant(14)(5); --  Grant(2,5)
+Grant(14)  <= Signal_grant(7)(6) or Signal_grant(15)(6); --  Grant(2,6)
+Grant(15)  <= Signal_grant(8)(7) ;                      --  Grant(2,7)
+Grant(16)  <= Signal_grant(1)(8) or Signal_grant(9)(8); --  Grant(2,8)
+Grant(17)  <= Signal_grant(3)(1) or Signal_grant(11)(1); --  Grant(3,1)
+Grant(18)  <= Signal_grant(4)(2) or Signal_grant(12)(2); --  Grant(3,2)
+Grant(19)  <= Signal_grant(5)(3) or Signal_grant(13)(3); --  Grant(3,3)
+Grant(20)  <= Signal_grant(6)(4) or Signal_grant(14)(4); --  Grant(3,4)
+Grant(21)  <= Signal_grant(7)(5) or Signal_grant(15)(5); --  Grant(3,5)
+Grant(22)  <= Signal_grant(8)(6) ;                      --  Grant(3,6)
+Grant(23)  <= Signal_grant(1)(7) or Signal_grant(9)(7); --  Grant(3,7)
+Grant(24)  <= Signal_grant(2)(8) or Signal_grant(10)(8); --  Grant(3,8)
+Grant(25)  <= Signal_grant(4)(1) or Signal_grant(12)(1); --  Grant(4,1)
+Grant(26)  <= Signal_grant(5)(2) or Signal_grant(13)(2); --  Grant(4,2)
+Grant(27)  <= Signal_grant(6)(3) or Signal_grant(14)(3); --  Grant(4,3)
+Grant(28)  <= Signal_grant(7)(4) or Signal_grant(15)(4); --  Grant(4,4)
+Grant(29)  <= Signal_grant(8)(5) ;                      --  Grant(4,5)
+Grant(30)  <= Signal_grant(1)(6) or Signal_grant(9)(6); --  Grant(4,6)
+Grant(31)  <= Signal_grant(2)(7) or Signal_grant(10)(7); --  Grant(4,7)
+Grant(32)  <= Signal_grant(3)(8) or Signal_grant(11)(8); --  Grant(4,8)
+Grant(33)  <= Signal_grant(5)(1) or Signal_grant(13)(1); --  Grant(5,1)
+Grant(34)  <= Signal_grant(6)(2) or Signal_grant(14)(2); --  Grant(5,2)
+Grant(35)  <= Signal_grant(7)(3) or Signal_grant(15)(3); --  Grant(5,3)
+Grant(36)  <= Signal_grant(8)(4) ;                      --  Grant(5,4)
+Grant(37)  <= Signal_grant(1)(5) or Signal_grant(9)(5); --  Grant(5,5)
+Grant(38)  <= Signal_grant(2)(6) or Signal_grant(10)(6); --  Grant(5,6)
+Grant(39)  <= Signal_grant(3)(7) or Signal_grant(11)(7); --  Grant(5,7)
+Grant(40)  <= Signal_grant(4)(8) or Signal_grant(12)(8); --  Grant(5,8)
+Grant(41)  <= Signal_grant(6)(1) or Signal_grant(14)(1); --  Grant(6,1)
+Grant(42)  <= Signal_grant(7)(2) or Signal_grant(15)(2); --  Grant(6,2)
+Grant(43)  <= Signal_grant(8)(3) ;                      --  Grant(6,3)
+Grant(44)  <= Signal_grant(1)(4) or Signal_grant(9)(4); --  Grant(6,4)
+Grant(45)  <= Signal_grant(2)(5) or Signal_grant(10)(5); --  Grant(6,5)
+Grant(46)  <= Signal_grant(3)(6) or Signal_grant(11)(6); --  Grant(6,6)
+Grant(47)  <= Signal_grant(4)(7) or Signal_grant(12)(7); --  Grant(6,7)
+Grant(48)  <= Signal_grant(5)(8) or Signal_grant(13)(8); --  Grant(6,8)
+Grant(49)  <= Signal_grant(7)(1) or Signal_grant(15)(1); --  Grant(7,1)
+Grant(50)  <= Signal_grant(8)(2) ;                      --  Grant(7,2)
+Grant(51)  <= Signal_grant(1)(3) or Signal_grant(9)(3); --  Grant(7,3)
+Grant(52)  <= Signal_grant(2)(4) or Signal_grant(10)(4); --  Grant(7,4)
+Grant(53)  <= Signal_grant(3)(5) or Signal_grant(11)(5); --  Grant(7,5)
+Grant(54)  <= Signal_grant(4)(6) or Signal_grant(12)(6); --  Grant(7,6)
+Grant(55)  <= Signal_grant(5)(7) or Signal_grant(13)(7); --  Grant(7,7)
+Grant(56)  <= Signal_grant(6)(8) or Signal_grant(14)(8); --  Grant(7,8)
+Grant(57)  <= Signal_grant(8)(1) ;                      --  Grant(8,1)
+Grant(58)  <= Signal_grant(1)(2) or Signal_grant(9)(2); --  Grant(8,2)
+Grant(59)  <= Signal_grant(2)(3) or Signal_grant(10)(3); --  Grant(8,3)
+Grant(60)  <= Signal_grant(3)(4) or Signal_grant(11)(4); --  Grant(8,4)
+Grant(61)  <= Signal_grant(4)(5) or Signal_grant(12)(5); --  Grant(8,5)
+Grant(62)  <= Signal_grant(5)(6) or Signal_grant(13)(6); --  Grant(8,6)
+Grant(63)  <= Signal_grant(6)(7) or Signal_grant(14)(7); --  Grant(8,7)
+Grant(64)  <= Signal_grant(7)(8) or Signal_grant(15)(8); --  Grant(8,8)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(58), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(51), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(44), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(37), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(30), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(23), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(16), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(1)(1), West => east_2_west(1)(8), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(2)(1), West => east_2_west(2)(8), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(3)(1), West => east_2_west(3)(8), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(4)(1), West => east_2_west(4)(8), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(5)(1), West => east_2_west(5)(8), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(6)(1), West => east_2_west(6)(8), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(7)(1), West => east_2_west(7)(8), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(8)(1), West => east_2_west(8)(8), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(9)(1), West => east_2_west(9)(8), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(10)(1), West => east_2_west(10)(8), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(11)(1), West => east_2_west(11)(8), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(12)(1), West => east_2_west(12)(8), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(13)(1), West => east_2_west(13)(8), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(14)(1), West => east_2_west(14)(8), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "111111110000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "111111110000000" => Signal_priority <= "011111111000000";
+		       when "011111111000000" => Signal_priority <= "001111111100000";
+		       when "001111111100000" => Signal_priority <= "000111111110000";
+		       when "000111111110000" => Signal_priority <= "000011111111000";
+		       when "000011111111000" => Signal_priority <= "000001111111100";
+		       when "000001111111100" => Signal_priority <= "000000111111110";
+		       when "000000111111110" => Signal_priority <= "000000011111111";
+		       when "000000011111111" => Signal_priority <= "111111110000000";
+		       when others    => Signal_priority <= "111111110000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER9_9.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER9_9.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SCHEDULER9_9.VHD	(revision 20)
@@ -0,0 +1,1001 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler9_9 is
+    Port ( Request : in  STD_LOGIC_VECTOR (81 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (9 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (9 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (81 downto 1));
+end Scheduler9_9;
+
+architecture Behavioral of Scheduler9_9 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(17 downto 1) of STD_LOGIC_VECTOR(9 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (17 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(81 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(81 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 511 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(10)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(11)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(12)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(13)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(14)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(15)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(16)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(17)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) ;                      --  Grant(1,9)
+Grant(10)  <= Signal_grant(2)(1) or Signal_grant(11)(1); --  Grant(2,1)
+Grant(11)  <= Signal_grant(3)(2) or Signal_grant(12)(2); --  Grant(2,2)
+Grant(12)  <= Signal_grant(4)(3) or Signal_grant(13)(3); --  Grant(2,3)
+Grant(13)  <= Signal_grant(5)(4) or Signal_grant(14)(4); --  Grant(2,4)
+Grant(14)  <= Signal_grant(6)(5) or Signal_grant(15)(5); --  Grant(2,5)
+Grant(15)  <= Signal_grant(7)(6) or Signal_grant(16)(6); --  Grant(2,6)
+Grant(16)  <= Signal_grant(8)(7) or Signal_grant(17)(7); --  Grant(2,7)
+Grant(17)  <= Signal_grant(9)(8) ;                      --  Grant(2,8)
+Grant(18)  <= Signal_grant(1)(9) or Signal_grant(10)(9); --  Grant(2,9)
+Grant(19)  <= Signal_grant(3)(1) or Signal_grant(12)(1); --  Grant(3,1)
+Grant(20)  <= Signal_grant(4)(2) or Signal_grant(13)(2); --  Grant(3,2)
+Grant(21)  <= Signal_grant(5)(3) or Signal_grant(14)(3); --  Grant(3,3)
+Grant(22)  <= Signal_grant(6)(4) or Signal_grant(15)(4); --  Grant(3,4)
+Grant(23)  <= Signal_grant(7)(5) or Signal_grant(16)(5); --  Grant(3,5)
+Grant(24)  <= Signal_grant(8)(6) or Signal_grant(17)(6); --  Grant(3,6)
+Grant(25)  <= Signal_grant(9)(7) ;                      --  Grant(3,7)
+Grant(26)  <= Signal_grant(1)(8) or Signal_grant(10)(8); --  Grant(3,8)
+Grant(27)  <= Signal_grant(2)(9) or Signal_grant(11)(9); --  Grant(3,9)
+Grant(28)  <= Signal_grant(4)(1) or Signal_grant(13)(1); --  Grant(4,1)
+Grant(29)  <= Signal_grant(5)(2) or Signal_grant(14)(2); --  Grant(4,2)
+Grant(30)  <= Signal_grant(6)(3) or Signal_grant(15)(3); --  Grant(4,3)
+Grant(31)  <= Signal_grant(7)(4) or Signal_grant(16)(4); --  Grant(4,4)
+Grant(32)  <= Signal_grant(8)(5) or Signal_grant(17)(5); --  Grant(4,5)
+Grant(33)  <= Signal_grant(9)(6) ;                      --  Grant(4,6)
+Grant(34)  <= Signal_grant(1)(7) or Signal_grant(10)(7); --  Grant(4,7)
+Grant(35)  <= Signal_grant(2)(8) or Signal_grant(11)(8); --  Grant(4,8)
+Grant(36)  <= Signal_grant(3)(9) or Signal_grant(12)(9); --  Grant(4,9)
+Grant(37)  <= Signal_grant(5)(1) or Signal_grant(14)(1); --  Grant(5,1)
+Grant(38)  <= Signal_grant(6)(2) or Signal_grant(15)(2); --  Grant(5,2)
+Grant(39)  <= Signal_grant(7)(3) or Signal_grant(16)(3); --  Grant(5,3)
+Grant(40)  <= Signal_grant(8)(4) or Signal_grant(17)(4); --  Grant(5,4)
+Grant(41)  <= Signal_grant(9)(5) ;                      --  Grant(5,5)
+Grant(42)  <= Signal_grant(1)(6) or Signal_grant(10)(6); --  Grant(5,6)
+Grant(43)  <= Signal_grant(2)(7) or Signal_grant(11)(7); --  Grant(5,7)
+Grant(44)  <= Signal_grant(3)(8) or Signal_grant(12)(8); --  Grant(5,8)
+Grant(45)  <= Signal_grant(4)(9) or Signal_grant(13)(9); --  Grant(5,9)
+Grant(46)  <= Signal_grant(6)(1) or Signal_grant(15)(1); --  Grant(6,1)
+Grant(47)  <= Signal_grant(7)(2) or Signal_grant(16)(2); --  Grant(6,2)
+Grant(48)  <= Signal_grant(8)(3) or Signal_grant(17)(3); --  Grant(6,3)
+Grant(49)  <= Signal_grant(9)(4) ;                      --  Grant(6,4)
+Grant(50)  <= Signal_grant(1)(5) or Signal_grant(10)(5); --  Grant(6,5)
+Grant(51)  <= Signal_grant(2)(6) or Signal_grant(11)(6); --  Grant(6,6)
+Grant(52)  <= Signal_grant(3)(7) or Signal_grant(12)(7); --  Grant(6,7)
+Grant(53)  <= Signal_grant(4)(8) or Signal_grant(13)(8); --  Grant(6,8)
+Grant(54)  <= Signal_grant(5)(9) or Signal_grant(14)(9); --  Grant(6,9)
+Grant(55)  <= Signal_grant(7)(1) or Signal_grant(16)(1); --  Grant(7,1)
+Grant(56)  <= Signal_grant(8)(2) or Signal_grant(17)(2); --  Grant(7,2)
+Grant(57)  <= Signal_grant(9)(3) ;                      --  Grant(7,3)
+Grant(58)  <= Signal_grant(1)(4) or Signal_grant(10)(4); --  Grant(7,4)
+Grant(59)  <= Signal_grant(2)(5) or Signal_grant(11)(5); --  Grant(7,5)
+Grant(60)  <= Signal_grant(3)(6) or Signal_grant(12)(6); --  Grant(7,6)
+Grant(61)  <= Signal_grant(4)(7) or Signal_grant(13)(7); --  Grant(7,7)
+Grant(62)  <= Signal_grant(5)(8) or Signal_grant(14)(8); --  Grant(7,8)
+Grant(63)  <= Signal_grant(6)(9) or Signal_grant(15)(9); --  Grant(7,9)
+Grant(64)  <= Signal_grant(8)(1) or Signal_grant(17)(1); --  Grant(8,1)
+Grant(65)  <= Signal_grant(9)(2) ;                      --  Grant(8,2)
+Grant(66)  <= Signal_grant(1)(3) or Signal_grant(10)(3); --  Grant(8,3)
+Grant(67)  <= Signal_grant(2)(4) or Signal_grant(11)(4); --  Grant(8,4)
+Grant(68)  <= Signal_grant(3)(5) or Signal_grant(12)(5); --  Grant(8,5)
+Grant(69)  <= Signal_grant(4)(6) or Signal_grant(13)(6); --  Grant(8,6)
+Grant(70)  <= Signal_grant(5)(7) or Signal_grant(14)(7); --  Grant(8,7)
+Grant(71)  <= Signal_grant(6)(8) or Signal_grant(15)(8); --  Grant(8,8)
+Grant(72)  <= Signal_grant(7)(9) or Signal_grant(16)(9); --  Grant(8,9)
+Grant(73)  <= Signal_grant(9)(1) ;                      --  Grant(9,1)
+Grant(74)  <= Signal_grant(1)(2) or Signal_grant(10)(2); --  Grant(9,2)
+Grant(75)  <= Signal_grant(2)(3) or Signal_grant(11)(3); --  Grant(9,3)
+Grant(76)  <= Signal_grant(3)(4) or Signal_grant(12)(4); --  Grant(9,4)
+Grant(77)  <= Signal_grant(4)(5) or Signal_grant(13)(5); --  Grant(9,5)
+Grant(78)  <= Signal_grant(5)(6) or Signal_grant(14)(6); --  Grant(9,6)
+Grant(79)  <= Signal_grant(6)(7) or Signal_grant(15)(7); --  Grant(9,7)
+Grant(80)  <= Signal_grant(7)(8) or Signal_grant(16)(8); --  Grant(9,8)
+Grant(81)  <= Signal_grant(8)(9) or Signal_grant(17)(9); --  Grant(9,9)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(74), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(66), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(58), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(50), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(42), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(34), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(26), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(18), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(1)(1), West => east_2_west(1)(9), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(2)(1), West => east_2_west(2)(9), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(3)(1), West => east_2_west(3)(9), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(4)(1), West => east_2_west(4)(9), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(5)(1), West => east_2_west(5)(9), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(6)(1), West => east_2_west(6)(9), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(7)(1), West => east_2_west(7)(9), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(8)(1), West => east_2_west(8)(9), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(9)(1), West => east_2_west(9)(9), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(10)(1), West => east_2_west(10)(9), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(11)(1), West => east_2_west(11)(9), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(12)(1), West => east_2_west(12)(9), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(13)(1), West => east_2_west(13)(9), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(14)(1), West => east_2_west(14)(9), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(15)(1), West => east_2_west(15)(9), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(16)(1), West => east_2_west(16)(9), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "11111111100000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "11111111100000000" => Signal_priority <= "01111111110000000";
+		       when "01111111110000000" => Signal_priority <= "00111111111000000";
+		       when "00111111111000000" => Signal_priority <= "00011111111100000";
+		       when "00011111111100000" => Signal_priority <= "00001111111110000";
+		       when "00001111111110000" => Signal_priority <= "00000111111111000";
+		       when "00000111111111000" => Signal_priority <= "00000011111111100";
+		       when "00000011111111100" => Signal_priority <= "00000001111111110";
+		       when "00000001111111110" => Signal_priority <= "00000000111111111";
+		       when "00000000111111111" => Signal_priority <= "11111111100000000";
+		       when others    => Signal_priority <= "11111111100000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN.vhd	(revision 20)
@@ -0,0 +1,7432 @@
+----------------------------------------------------------------------------------
+-- Company: ENSET 2011
+-- Engineer: GAMOM NGOUNOU
+-- 
+-- Create Date:    03:40:47 11/19/2011 
+-- Design Name: 
+-- Module Name:    SWITCH_GEN - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+-- fichier principal du switch générique; en fonction du parametre generique le 
+-- les directive de generation conditionnelle permettent de ne générer et synthétiser uniquement  la logique 
+-- nécessaire à l'implémentation  du switch de la dimension voulue
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.Coretypes.all ;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity SWITCH_GEN is 
+ --type portio is array(positive range) of std_logic_vector (7 downto 0);    
+ generic(number_of_ports : positive := 8);
+     port(
+	        -- ports d'entree
+           Port_in : in typ_portIO(1 to number_of_ports) ;
+--			  Port1_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--           Port2_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--           Port3_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--           Port4_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--			  Port5_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--           Port6_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--           Port7_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--           Port8_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--			  Port9_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--           Port10_in : in  STD_LOGIC_VECTOR (7 downto 0);
+--           Port11_in : in  STD_LOGIC_VECTOR (7 downto 0);
+--           Port12_in : in  STD_LOGIC_VECTOR (7 downto 0);
+--			  Port13_in : in  STD_LOGIC_VECTOR (7 downto 0);
+--           Port14_in : in  STD_LOGIC_VECTOR (7 downto 0);
+--           Port15_in : in  STD_LOGIC_VECTOR (7 downto 0);
+--           Port16_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			 
+			  -- port de sortie
+			  Port_out : out  typ_portIO(1 to number_of_ports);
+--			  Port1_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port2_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port3_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port4_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--			  Port5_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port6_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port7_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port8_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--			  Port9_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port10_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port11_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port12_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--			  Port13_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port14_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port15_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port16_out : out  STD_LOGIC_VECTOR (7 downto 0);
+			  -- signaux de controle
+			  data_in_en : in std_logic_vector(number_of_ports downto 1);
+			  cmd_in_en :  in std_logic_vector(number_of_ports downto 1);
+			  data_out_en : in std_logic_vector(number_of_ports downto 1);
+			  fifo_in_full : out std_logic_vector(number_of_ports downto 1);
+			  fifo_in_empty : out std_logic_vector(number_of_ports downto 1);
+			  data_available : out std_logic_vector(number_of_ports downto 1);
+			  clk       : in   STD_LOGIC;
+			  reset     : in   STD_LOGIC);
+end SWITCH_GEN;
+
+architecture Behavioral of SWITCH_GEN is
+-- declaration des modules du switch generique
+-- le module de gestion des ports d'entrée
+
+COMPONENT INPUT_PORT_MODULE
+  generic(number_of_ports : positive := 4;
+			Port_num: natural);
+    Port ( data_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           data_in_en : in  STD_LOGIC;
+			  cmd_in_en : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+			  clk   : in  STD_LOGIC;
+			  request : out  STD_LOGIC_VECTOR (number_of_ports downto 1);
+           grant : in  STD_LOGIC_VECTOR (number_of_ports  downto 1);			  
+           fifo_full : out  STD_LOGIC;
+			  fifo_empty : out  STD_LOGIC;
+			  priority_rotation : out std_logic;
+           data_out : out  STD_LOGIC_VECTOR (7 downto 0);
+			  data_out_pulse : out std_logic);
+END COMPONENT;
+
+-- le module des ports de sortie
+
+COMPONENT OUTPUT_PORT_MODULE
+	PORT(
+		data_in : IN std_logic_vector(7 downto 0);
+		reset : IN std_logic;
+		clk : IN std_logic;
+		wr_en : IN std_logic;
+		rd_out_en : IN std_logic;          
+		data_out : OUT std_logic_vector(7 downto 0);
+		fifo_full : OUT std_logic;
+		data_avalaible : OUT std_logic
+		);
+END COMPONENT;
+	
+-- le module du crossbar
+COMPONENT Crossbar
+ generic
+	      (
+			  number_of_crossbar_ports: positive := 4
+			);
+    Port ( 
+	        --Port_in : in Typ_PortIO(1 to number_of_crossbar_ports);
+			  Port1_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port2_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port3_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port4_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port5_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port6_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port7_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port8_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port9_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port10_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port13_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  
+			  --Port_pulse_in : in std_logic_vector(1 to number_of_ports);
+			  Port1_pulse_in : in std_logic;
+			  Port2_pulse_in : in std_logic;
+			  Port3_pulse_in : in std_logic;
+			  Port4_pulse_in : in std_logic;
+			  Port5_pulse_in : in std_logic;
+			  Port6_pulse_in : in std_logic;
+			  Port7_pulse_in : in std_logic;
+			  Port8_pulse_in : in std_logic;
+			  Port9_pulse_in : in std_logic;
+			  Port10_pulse_in : in std_logic;
+			  Port11_pulse_in : in std_logic;
+			  Port12_pulse_in : in std_logic;
+			  Port13_pulse_in : in std_logic;
+			  Port14_pulse_in : in std_logic;
+			  Port15_pulse_in : in std_logic;
+			  Port16_pulse_in : in std_logic;
+			  
+			  --Port_pulse_out : in std_logic_vector(1 to number_of_ports);
+			  Port1_pulse_out : out std_logic;
+			  Port2_pulse_out : out std_logic;
+			  Port3_pulse_out : out std_logic;
+			  Port4_pulse_out : out std_logic;
+			  Port5_pulse_out : out std_logic;
+			  Port6_pulse_out : out std_logic;
+			  Port7_pulse_out : out std_logic;
+			  Port8_pulse_out : out std_logic;
+			  Port9_pulse_out : out std_logic;
+			  Port10_pulse_out : out std_logic;
+			  Port11_pulse_out : out std_logic;
+			  Port12_pulse_out : out std_logic;
+			  Port13_pulse_out : out std_logic;
+			  Port14_pulse_out : out std_logic;
+			  Port15_pulse_out : out std_logic;
+			  Port16_pulse_out : out std_logic;
+			  
+			  --Port_out : out Typ_PortIO(1 to number_of_crossbar_ports);
+			  Port1_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port2_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port3_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port4_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port5_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port6_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port7_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port8_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port9_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port10_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port13_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  
+           Ctrl : in  STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1)
+       ); 
+ END COMPONENT;
+
+-- déclaration du  scheduler
+COMPONENT Scheduler
+	generic(number_of_ports : positive := 4);
+    Port ( Request : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
+			  Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1);
+           clk : in  STD_LOGIC;
+	        reset : in  STD_LOGIC;
+			  priority_rotation : in  STD_LOGIC_VECTOR (number_of_ports downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1));
+END COMPONENT;
+
+--declaration des signaux de connection entre les modules du switch
+--type port_connection_type is array(16 downto 1) of std_logic_vector(7 downto 1);
+--signal crossbar_port_in_connetion : port_connection_type;
+--signal crossbar_port_out_connetion :port_connection_type;
+--signal request_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
+--signal grant_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
+--signal priority_rotation_connection : std_logic_vector(number_of_ports downto 1);
+--signal fifo_out_full_connection : std_logic_vector(1 to number_of_ports);
+--signal crossbar_in_pulse(_connection : std_logic_vector(number_of_ports downto 1);
+--signal crossbar_out_pulse_connection : std_logic_vector(number_of_ports downto 1);
+--variable i,j : integer;
+
+Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
+Signal grant_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
+Signal priority_rotation_signal : STD_LOGIC_VECTOR(number_of_ports downto 1);
+signal fifo_out_full_signal : std_logic_vector(number_of_ports downto 1);
+
+signal crossbar_in_port :  Typ_PortIO(1 to number_of_ports);
+
+--signal crossbar_in_port1 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port2 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port3 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port4 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port5 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port6 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port7 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port8 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port9 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port10 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port11 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port12 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port13 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port14 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port15 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port16 : std_logic_vector(7 downto 0);
+
+signal crossbar_out_port  :  Typ_PortIO(1 to number_of_ports);
+--signal crossbar_out_port1 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port2 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port3 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port4 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port5 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port6 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port7 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port8 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port9 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port10 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port11 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port12 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port13 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port14 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port15 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port16 : std_logic_vector(7 downto 0);
+
+signal crossbar_in_pulse  : std_logic_vector(number_of_ports downto 1);
+--signal crossbar_in_pulse1 : std_logic;
+--signal crossbar_in_pulse2 : std_logic;
+--signal crossbar_in_pulse3 : std_logic;
+--signal crossbar_in_pulse4 : std_logic;
+--signal crossbar_in_pulse5 : std_logic;
+--signal crossbar_in_pulse6 : std_logic;
+--signal crossbar_in_pulse7 : std_logic;
+--signal crossbar_in_pulse8 : std_logic;
+--signal crossbar_in_pulse9 : std_logic;
+--signal crossbar_in_pulse10 : std_logic;
+--signal crossbar_in_pulse11 : std_logic;
+--signal crossbar_in_pulse12 : std_logic;
+--signal crossbar_in_pulse13 : std_logic;
+--signal crossbar_in_pulse14 : std_logic;
+--signal crossbar_in_pulse15 : std_logic;
+--signal crossbar_in_pulse16 : std_logic;
+
+signal crossbar_out_pulse  : std_logic_vector(number_of_ports downto 1);
+--signal crossbar_out_pulse1 : std_logic;
+--signal crossbar_out_pulse2 : std_logic;
+--signal crossbar_out_pulse3 : std_logic;
+--signal crossbar_out_pulse4 : std_logic;
+--signal crossbar_out_pulse5 : std_logic;
+--signal crossbar_out_pulse6 : std_logic;
+--signal crossbar_out_pulse7 : std_logic;
+--signal crossbar_out_pulse8 : std_logic;
+--signal crossbar_out_pulse9 : std_logic;
+--signal crossbar_out_pulse10 : std_logic;
+--signal crossbar_out_pulse11 : std_logic;
+--signal crossbar_out_pulse12 : std_logic;
+--signal crossbar_out_pulse13 : std_logic;
+--signal crossbar_out_pulse14 : std_logic;
+--signal crossbar_out_pulse15 : std_logic;
+--signal crossbar_out_pulse16 : std_logic;
+
+
+begin
+-- intstanciation et connexion des modules du switch en fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+switch2x2 : if number_of_ports = 2 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>2,Port_num=>1)
+PORT MAP(
+   data_in => Port_in(1),
+   data_in_en => data_in_en(1),
+	cmd_in_en => cmd_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port(1),
+   data_out_pulse =>crossbar_in_pulse(1),
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>2,Port_num=>2)
+PORT MAP(
+   data_in => Port_in(2),
+   data_in_en => data_in_en(2),
+	cmd_in_en => cmd_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(3),
+   grant(2) => grant_signal(4),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port(2),
+   data_out_pulse =>crossbar_in_pulse(2),
+   request(1) =>request_signal(3),
+   request(2) =>request_signal(4)
+);
+
+end generate switch2x2;
+
+
+-- switch 3 ports
+switch3x3 : if number_of_ports = 3 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>3,Port_num=>1)
+PORT MAP(
+   data_in => Port_in(1),
+   data_in_en => data_in_en(1),
+	cmd_in_en => cmd_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port(1),
+   data_out_pulse =>crossbar_in_pulse(1),
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>3,Port_num=>2)
+PORT MAP(
+   data_in => Port_in(2),
+   data_in_en => data_in_en(2),
+	cmd_in_en => cmd_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port(2),
+   data_out_pulse =>crossbar_in_pulse(2),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>3,Port_num=>3)
+PORT MAP(
+   data_in => Port_in(3),
+   data_in_en => data_in_en(3),
+	cmd_in_en => cmd_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port(3),
+   data_out_pulse =>crossbar_in_pulse(3),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9)
+);
+
+end generate switch3x3;
+
+
+-- switch 4 à 7 ports
+switch4x4_7x7 : if number_of_ports >= 4 and number_of_ports <=7 generate
+
+switch_4x4_7x7:for i in 1 to number_of_ports generate
+
+constant j: natural:=number_of_ports*(i-1);
+begin
+--j=number_of_ports*(i-1);
+PORTx4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>4,Port_num=>i)
+PORT MAP(
+   data_in => Port_in(i),
+   data_in_en => data_in_en(i),
+	cmd_in_en => cmd_in_en(i),
+   reset => reset,
+   clk =>clk,
+	grant =>grant_signal(j+NUMBER_OF_PORTS downto j+1),
+ 
+   fifo_full =>fifo_in_full(i),
+   priority_rotation =>  priority_rotation_signal(i),
+   fifo_empty => fifo_in_empty(i),
+   data_out =>crossbar_in_port(i),
+   data_out_pulse =>crossbar_in_pulse(i),
+	request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
+   
+);
+end generate switch_4x4_7x7;
+end generate switch4x4_7x7;
+
+
+---- switch 5 ports
+--switch5x5 : if number_of_ports = 5 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>5)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>5)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(6),
+--   grant(2) => grant_signal(7),
+--   grant(3) => grant_signal(8),
+--   grant(4) => grant_signal(9),
+--   grant(5) => grant_signal(10),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>5)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(11) => grant_signal(11),
+--   grant(12) => grant_signal(12),
+--   grant(13) => grant_signal(13),
+--   grant(14) => grant_signal(14),
+--   grant(15) => grant_signal(15),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(11) =>request_signal(11),
+--   request(12) =>request_signal(12),
+--   request(13) =>request_signal(13),
+--   request(14) =>request_signal(14),
+--   request(15) =>request_signal(15)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>5)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(16) => grant_signal(16),
+--   grant(17) => grant_signal(17),
+--   grant(18) => grant_signal(18),
+--   grant(19) => grant_signal(19),
+--   grant(20) => grant_signal(20),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(16) =>request_signal(16),
+--   request(17) =>request_signal(17),
+--   request(18) =>request_signal(18),
+--   request(19) =>request_signal(19),
+--   request(20) =>request_signal(20)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>5)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(21) => grant_signal(21),
+--   grant(22) => grant_signal(22),
+--   grant(23) => grant_signal(23),
+--   grant(24) => grant_signal(24),
+--   grant(25) => grant_signal(25),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(21) =>request_signal(21),
+--   request(22) =>request_signal(22),
+--   request(23) =>request_signal(23),
+--   request(24) =>request_signal(24),
+--   request(25) =>request_signal(25)
+--);
+--
+--end generate switch5x5;
+--
+--
+---- switch 6 ports
+--switch6x6 : if number_of_ports = 6 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>6)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--	cmd_in_en => cmd_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>6)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(7),
+--   grant(2) => grant_signal(8),
+--   grant(3) => grant_signal(9),
+--   grant(4) => grant_signal(10),
+--   grant(5) => grant_signal(11),
+--   grant(6) => grant_signal(12),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(1) =>request_signal(7),
+--   request(2) =>request_signal(8),
+--   request(3) =>request_signal(9),
+--   request(4) =>request_signal(10),
+--   request(5) =>request_signal(11),
+--   request(6) =>request_signal(12)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>6)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(13) => grant_signal(13),
+--   grant(14) => grant_signal(14),
+--   grant(15) => grant_signal(15),
+--   grant(16) => grant_signal(16),
+--   grant(17) => grant_signal(17),
+--   grant(18) => grant_signal(18),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(13) =>request_signal(13),
+--   request(14) =>request_signal(14),
+--   request(15) =>request_signal(15),
+--   request(16) =>request_signal(16),
+--   request(17) =>request_signal(17),
+--   request(18) =>request_signal(18)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>6)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--	cmd_in_en => cmd_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(19) => grant_signal(19),
+--   grant(20) => grant_signal(20),
+--   grant(21) => grant_signal(21),
+--   grant(22) => grant_signal(22),
+--   grant(23) => grant_signal(23),
+--   grant(24) => grant_signal(24),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(19) =>request_signal(19),
+--   request(20) =>request_signal(20),
+--   request(21) =>request_signal(21),
+--   request(22) =>request_signal(22),
+--   request(23) =>request_signal(23),
+--   request(24) =>request_signal(24)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>6)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--	cmd_in_en => cmd_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(25) => grant_signal(25),
+--   grant(26) => grant_signal(26),
+--   grant(27) => grant_signal(27),
+--   grant(28) => grant_signal(28),
+--   grant(29) => grant_signal(29),
+--   grant(30) => grant_signal(30),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(25) =>request_signal(25),
+--   request(26) =>request_signal(26),
+--   request(27) =>request_signal(27),
+--   request(28) =>request_signal(28),
+--   request(29) =>request_signal(29),
+--   request(30) =>request_signal(30)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>6)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(31) => grant_signal(31),
+--   grant(32) => grant_signal(32),
+--   grant(33) => grant_signal(33),
+--   grant(34) => grant_signal(34),
+--   grant(35) => grant_signal(35),
+--   grant(36) => grant_signal(36),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(31) =>request_signal(31),
+--   request(32) =>request_signal(32),
+--   request(33) =>request_signal(33),
+--   request(34) =>request_signal(34),
+--   request(35) =>request_signal(35),
+--   request(36) =>request_signal(36)
+--);
+--
+--end generate switch6x6;
+--
+--
+---- switch 7 ports
+--switch7x7 : if number_of_ports = 7 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>7)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--	cmd_in_en => cmd_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   grant(7) => grant_signal(7),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>7)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(8),
+--   grant(2) => grant_signal(9),
+--   grant(3) => grant_signal(10),
+--   grant(4) => grant_signal(11),
+--   grant(5) => grant_signal(12),
+--   grant(6) => grant_signal(13),
+--   grant(7) => grant_signal(14),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10),
+--   request(11) =>request_signal(11),
+--   request(12) =>request_signal(12),
+--   request(13) =>request_signal(13),
+--   request(14) =>request_signal(14)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>7)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(15) => grant_signal(15),
+--   grant(16) => grant_signal(16),
+--   grant(17) => grant_signal(17),
+--   grant(18) => grant_signal(18),
+--   grant(19) => grant_signal(19),
+--   grant(20) => grant_signal(20),
+--   grant(21) => grant_signal(21),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(15) =>request_signal(15),
+--   request(16) =>request_signal(16),
+--   request(17) =>request_signal(17),
+--   request(18) =>request_signal(18),
+--   request(19) =>request_signal(19),
+--   request(20) =>request_signal(20),
+--   request(21) =>request_signal(21)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>7)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(22) => grant_signal(22),
+--   grant(23) => grant_signal(23),
+--   grant(24) => grant_signal(24),
+--   grant(25) => grant_signal(25),
+--   grant(26) => grant_signal(26),
+--   grant(27) => grant_signal(27),
+--   grant(28) => grant_signal(28),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(22) =>request_signal(22),
+--   request(23) =>request_signal(23),
+--   request(24) =>request_signal(24),
+--   request(25) =>request_signal(25),
+--   request(26) =>request_signal(26),
+--   request(27) =>request_signal(27),
+--   request(28) =>request_signal(28)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>7)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(29) => grant_signal(29),
+--   grant(30) => grant_signal(30),
+--   grant(31) => grant_signal(31),
+--   grant(32) => grant_signal(32),
+--   grant(33) => grant_signal(33),
+--   grant(34) => grant_signal(34),
+--   grant(35) => grant_signal(35),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(29) =>request_signal(29),
+--   request(30) =>request_signal(30),
+--   request(31) =>request_signal(31),
+--   request(32) =>request_signal(32),
+--   request(33) =>request_signal(33),
+--   request(34) =>request_signal(34),
+--   request(35) =>request_signal(35)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>7)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(36) => grant_signal(36),
+--   grant(37) => grant_signal(37),
+--   grant(38) => grant_signal(38),
+--   grant(39) => grant_signal(39),
+--   grant(40) => grant_signal(40),
+--   grant(41) => grant_signal(41),
+--   grant(42) => grant_signal(42),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(36) =>request_signal(36),
+--   request(37) =>request_signal(37),
+--   request(38) =>request_signal(38),
+--   request(39) =>request_signal(39),
+--   request(40) =>request_signal(40),
+--   request(41) =>request_signal(41),
+--   request(42) =>request_signal(42)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>7)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(43) => grant_signal(43),
+--   grant(44) => grant_signal(44),
+--   grant(45) => grant_signal(45),
+--   grant(46) => grant_signal(46),
+--   grant(47) => grant_signal(47),
+--   grant(48) => grant_signal(48),
+--   grant(49) => grant_signal(49),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(7),
+--   request(43) =>request_signal(43),
+--   request(44) =>request_signal(44),
+--   request(45) =>request_signal(45),
+--   request(46) =>request_signal(46),
+--   request(47) =>request_signal(47),
+--   request(48) =>request_signal(48),
+--   request(49) =>request_signal(49)
+--);
+--
+--end generate switch7x7;
+
+
+-- switch 8 ports
+switch8x8 : if number_of_ports = 8 generate
+switch_8x8:for i in 1 to number_of_ports generate
+constant j: natural:=number_of_ports*(i-1);
+begin
+--j<=number_of_ports*(i-1);
+PORTx8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8,Port_num=>i)
+PORT MAP(
+   data_in => Port_in(i),
+   data_in_en => data_in_en(i),
+	cmd_in_en => cmd_in_en(i),
+   reset => reset,
+   clk =>clk,
+	grant =>grant_signal(j+NUMBER_OF_PORTS downto j+1),
+   fifo_full =>fifo_in_full(i),
+   priority_rotation =>  priority_rotation_signal(i),
+   fifo_empty => fifo_in_empty(i),
+   data_out =>crossbar_in_port(i),
+   data_out_pulse =>crossbar_in_pulse(i),
+
+	request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
+);
+end generate switch_8x8;
+end generate switch8x8;
+
+-- switch 9 ports
+switch9x9_to_15 : if (number_of_ports >= 9)and (number_of_ports <= 15) generate
+
+switch_9x9_to_15:for i in 1 to number_of_ports generate
+
+constant j: natural:=number_of_ports*(i-1);
+begin
+
+PORTx9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>NUMBER_OF_PORTS,Port_num=>i)
+PORT MAP(
+   data_in => Port_in(i),
+   data_in_en => data_in_en(i),
+	cmd_in_en => cmd_in_en(i),
+   reset => reset,
+   clk =>clk,
+   grant => grant_signal(j+NUMBER_OF_PORTS downto j+1),
+   fifo_full =>fifo_in_full(i),
+   priority_rotation =>  priority_rotation_signal(i),
+   fifo_empty => fifo_in_empty(i),
+   data_out =>crossbar_in_port(i),
+   data_out_pulse =>crossbar_in_pulse(i),
+
+	request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
+);
+end generate switch_9x9_to_15;
+end generate switch9x9_to_15;
+
+
+
+-- switch 10 ports
+--switch10x10 : if number_of_ports = 10 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   grant(7) => grant_signal(7),
+--   grant(8) => grant_signal(8),
+--   grant(9) => grant_signal(9),
+--   grant(10) => grant_signal(10),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(11),
+--   grant(2) => grant_signal(12),
+--   grant(3) => grant_signal(13),
+--   grant(4) => grant_signal(14),
+--   grant(5) => grant_signal(15),
+--   grant(6) => grant_signal(16),
+--   grant(7) => grant_signal(17),
+--   grant(8) => grant_signal(18),
+--   grant(9) => grant_signal(19),
+--   grant(10) => grant_signal(20),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(1) =>request_signal(11),
+--   request(2) =>request_signal(12),
+--   request(3) =>request_signal(13),
+--   request(4) =>request_signal(14),
+--   request(5) =>request_signal(15),
+--   request(6) =>request_signal(16),
+--   request(7) =>request_signal(17),
+--   request(8) =>request_signal(18),
+--   request(9) =>request_signal(19),
+--   request(10) =>request_signal(20)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(21),
+--   grant(2) => grant_signal(22),
+--   grant(3) => grant_signal(23),
+--   grant(4) => grant_signal(24),
+--   grant(5) => grant_signal(25),
+--   grant(6) => grant_signal(26),
+--   grant(7) => grant_signal(27),
+--   grant(8) => grant_signal(28),
+--   grant(9) => grant_signal(29),
+--   grant(10) => grant_signal(30),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(1) =>request_signal(21),
+--   request(2) =>request_signal(22),
+--   request(3) =>request_signal(23),
+--   request(4) =>request_signal(24),
+--   request(5) =>request_signal(25),
+--   request(6) =>request_signal(26),
+--   request(7) =>request_signal(27),
+--   request(8) =>request_signal(28),
+--   request(9) =>request_signal(29),
+--   request(10) =>request_signal(30)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(31),
+--   grant(2) => grant_signal(32),
+--   grant(3) => grant_signal(33),
+--   grant(4) => grant_signal(34),
+--   grant(5) => grant_signal(35),
+--   grant(6) => grant_signal(36),
+--   grant(7) => grant_signal(37),
+--   grant(8) => grant_signal(38),
+--   grant(9) => grant_signal(39),
+--   grant(10) => grant_signal(40),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(1) =>request_signal(31),
+--   request(2) =>request_signal(32),
+--   request(3) =>request_signal(33),
+--   request(4) =>request_signal(34),
+--   request(5) =>request_signal(35),
+--   request(6) =>request_signal(36),
+--   request(7) =>request_signal(37),
+--   request(8) =>request_signal(38),
+--   request(9) =>request_signal(39),
+--   request(10) =>request_signal(40)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(41),
+--   grant(2) => grant_signal(42),
+--   grant(3) => grant_signal(43),
+--   grant(4) => grant_signal(44),
+--   grant(5) => grant_signal(45),
+--   grant(6) => grant_signal(46),
+--   grant(7) => grant_signal(47),
+--   grant(8) => grant_signal(48),
+--   grant(9) => grant_signal(49),
+--   grant(10) => grant_signal(50),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(1) =>request_signal(41),
+--   request(2) =>request_signal(42),
+--   request(3) =>request_signal(43),
+--   request(4) =>request_signal(44),
+--   request(5) =>request_signal(45),
+--   request(6) =>request_signal(46),
+--   request(7) =>request_signal(47),
+--   request(8) =>request_signal(48),
+--   request(9) =>request_signal(49),
+--   request(10) =>request_signal(50)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(51),
+--   grant(2) => grant_signal(52),
+--   grant(3) => grant_signal(53),
+--   grant(4) => grant_signal(54),
+--   grant(5) => grant_signal(55),
+--   grant(6) => grant_signal(56),
+--   grant(7) => grant_signal(57),
+--   grant(8) => grant_signal(58),
+--   grant(9) => grant_signal(59),
+--   grant(10) => grant_signal(60),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(1) =>request_signal(51),
+--   request(2) =>request_signal(52),
+--   request(3) =>request_signal(53),
+--   request(4) =>request_signal(54),
+--   request(5) =>request_signal(55),
+--   request(6) =>request_signal(56),
+--   request(7) =>request_signal(57),
+--   request(8) =>request_signal(58),
+--   request(9) =>request_signal(59),
+--   request(10) =>request_signal(60)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(61),
+--   grant(2) => grant_signal(62),
+--   grant(3) => grant_signal(63),
+--   grant(4) => grant_signal(64),
+--   grant(5) => grant_signal(65),
+--   grant(6) => grant_signal(66),
+--   grant(7) => grant_signal(67),
+--   grant(8) => grant_signal(68),
+--   grant(9) => grant_signal(69),
+--   grant(10) => grant_signal(70),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(7),
+--   data_out_pulse =>crossbar_in_pulse(7),
+--   request(1) =>request_signal(61),
+--   request(2) =>request_signal(62),
+--   request(3) =>request_signal(63),
+--   request(4) =>request_signal(64),
+--   request(5) =>request_signal(65),
+--   request(6) =>request_signal(66),
+--   request(7) =>request_signal(67),
+--   request(8) =>request_signal(68),
+--   request(9) =>request_signal(69),
+--   request(10) =>request_signal(70)
+--);
+--
+--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(8),
+--   data_in_en => data_in_en(8),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(71),
+--   grant(2) => grant_signal(72),
+--   grant(3) => grant_signal(73),
+--   grant(4) => grant_signal(74),
+--   grant(5) => grant_signal(75),
+--   grant(6) => grant_signal(76),
+--   grant(7) => grant_signal(77),
+--   grant(8) => grant_signal(78),
+--   grant(9) => grant_signal(79),
+--   grant(10) => grant_signal(80),
+--   fifo_full =>fifo_in_full(8),
+--   priority_rotation =>  priority_rotation_signal(8),
+--   fifo_empty => fifo_in_empty(8),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(8),
+--   request(1) =>request_signal(71),
+--   request(2) =>request_signal(72),
+--   request(3) =>request_signal(73),
+--   request(4) =>request_signal(74),
+--   request(5) =>request_signal(75),
+--   request(6) =>request_signal(76),
+--   request(7) =>request_signal(77),
+--   request(8) =>request_signal(78),
+--   request(9) =>request_signal(79),
+--   request(10) =>request_signal(80)
+--);
+--
+--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(9),
+--   data_in_en => data_in_en(9),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(81),
+--   grant(2) => grant_signal(82),
+--   grant(3) => grant_signal(83),
+--   grant(4) => grant_signal(84),
+--   grant(5) => grant_signal(85),
+--   grant(6) => grant_signal(86),
+--   grant(7) => grant_signal(87),
+--   grant(8) => grant_signal(88),
+--   grant(9) => grant_signal(89),
+--   grant(10) => grant_signal(90),
+--   fifo_full =>fifo_in_full(9),
+--   priority_rotation =>  priority_rotation_signal(9),
+--   fifo_empty => fifo_in_empty(9),
+--   data_out =>crossbar_in_port(9),
+--   data_out_pulse =>crossbar_in_pulse(9),
+--   request(1) =>request_signal(81),
+--   request(2) =>request_signal(82),
+--   request(3) =>request_signal(83),
+--   request(4) =>request_signal(84),
+--   request(5) =>request_signal(85),
+--   request(6) =>request_signal(86),
+--   request(7) =>request_signal(87),
+--   request(8) =>request_signal(88),
+--   request(9) =>request_signal(89),
+--   request(10) =>request_signal(90)
+--);
+--
+--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(10),
+--   data_in_en => data_in_en(10),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(91),
+--   grant(2) => grant_signal(92),
+--   grant(3) => grant_signal(93),
+--   grant(4) => grant_signal(94),
+--   grant(5) => grant_signal(95),
+--   grant(6) => grant_signal(96),
+--   grant(7) => grant_signal(97),
+--   grant(8) => grant_signal(98),
+--   grant(9) => grant_signal(99),
+--   grant(10) => grant_signal(100),
+--   fifo_full =>fifo_in_full(10),
+--   priority_rotation =>  priority_rotation_signal(10),
+--   fifo_empty => fifo_in_empty(10),
+--   data_out =>crossbar_in_port(10),
+--   data_out_pulse =>crossbar_in_pulse(10),
+--   request(1) =>request_signal(91),
+--   request(2) =>request_signal(92),
+--   request(3) =>request_signal(93),
+--   request(4) =>request_signal(94),
+--   request(5) =>request_signal(95),
+--   request(6) =>request_signal(96),
+--   request(7) =>request_signal(97),
+--   request(8) =>request_signal(98),
+--   request(9) =>request_signal(99),
+--   request(10) =>request_signal(100)
+--);
+--
+--end generate switch10x10;
+--
+--
+---- switch 11 ports
+--switch11x11 : if number_of_ports = 11 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   grant(7) => grant_signal(7),
+--   grant(8) => grant_signal(8),
+--   grant(9) => grant_signal(9),
+--   grant(10) => grant_signal(10),
+--   grant(11) => grant_signal(11),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10),
+--   request(11) =>request_signal(11)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(12),
+--   grant(02) => grant_signal(13),
+--   grant(03) => grant_signal(14),
+--   grant(04) => grant_signal(15),
+--   grant(05) => grant_signal(16),
+--   grant(06) => grant_signal(17),
+--   grant(07) => grant_signal(18),
+--   grant(08) => grant_signal(19),
+--   grant(09) => grant_signal(20),
+--   grant(10) => grant_signal(21),
+--   grant(11) => grant_signal(22),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(01) =>request_signal(12),
+--   request(02) =>request_signal(13),
+--   request(03) =>request_signal(14),
+--   request(04) =>request_signal(15),
+--   request(05) =>request_signal(16),
+--   request(06) =>request_signal(17),
+--   request(07) =>request_signal(18),
+--   request(08) =>request_signal(19),
+--   request(09) =>request_signal(20),
+--   request(10) =>request_signal(21),
+--   request(11) =>request_signal(22)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(01) => grant_signal(23),
+--   grant(02) => grant_signal(24),
+--   grant(03) => grant_signal(25),
+--   grant(04) => grant_signal(26),
+--   grant(05) => grant_signal(27),
+--   grant(06) => grant_signal(28),
+--   grant(07) => grant_signal(29),
+--   grant(08) => grant_signal(30),
+--   grant(09) => grant_signal(31),
+--   grant(10) => grant_signal(32),
+--   grant(11) => grant_signal(33),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(01) =>request_signal(23),
+--   request(02) =>request_signal(24),
+--   request(03) =>request_signal(25),
+--   request(04) =>request_signal(26),
+--   request(05) =>request_signal(27),
+--   request(06) =>request_signal(28),
+--   request(07) =>request_signal(29),
+--   request(08) =>request_signal(30),
+--   request(09) =>request_signal(31),
+--   request(10) =>request_signal(32),
+--   request(11) =>request_signal(33)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(01) => grant_signal(34),
+--   grant(02) => grant_signal(35),
+--   grant(03) => grant_signal(36),
+--   grant(04) => grant_signal(37),
+--   grant(05) => grant_signal(38),
+--   grant(06) => grant_signal(39),
+--   grant(07) => grant_signal(40),
+--   grant(08) => grant_signal(41),
+--   grant(09) => grant_signal(42),
+--   grant(10) => grant_signal(43),
+--   grant(11) => grant_signal(44),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(01) =>request_signal(34),
+--   request(02) =>request_signal(35),
+--   request(03) =>request_signal(36),
+--   request(04) =>request_signal(37),
+--   request(05) =>request_signal(38),
+--   request(06) =>request_signal(39),
+--   request(07) =>request_signal(40),
+--   request(08) =>request_signal(41),
+--   request(09) =>request_signal(42),
+--   request(10) =>request_signal(43),
+--   request(11) =>request_signal(44)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(45) => grant_signal(45),
+--   grant(46) => grant_signal(46),
+--   grant(47) => grant_signal(47),
+--   grant(48) => grant_signal(48),
+--   grant(49) => grant_signal(49),
+--   grant(50) => grant_signal(50),
+--   grant(51) => grant_signal(51),
+--   grant(52) => grant_signal(52),
+--   grant(53) => grant_signal(53),
+--   grant(54) => grant_signal(54),
+--   grant(55) => grant_signal(55),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(45) =>request_signal(45),
+--   request(46) =>request_signal(46),
+--   request(47) =>request_signal(47),
+--   request(48) =>request_signal(48),
+--   request(49) =>request_signal(49),
+--   request(50) =>request_signal(50),
+--   request(51) =>request_signal(51),
+--   request(52) =>request_signal(52),
+--   request(53) =>request_signal(53),
+--   request(54) =>request_signal(54),
+--   request(55) =>request_signal(55)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(56) => grant_signal(56),
+--   grant(57) => grant_signal(57),
+--   grant(58) => grant_signal(58),
+--   grant(59) => grant_signal(59),
+--   grant(60) => grant_signal(60),
+--   grant(61) => grant_signal(61),
+--   grant(62) => grant_signal(62),
+--   grant(63) => grant_signal(63),
+--   grant(64) => grant_signal(64),
+--   grant(65) => grant_signal(65),
+--   grant(66) => grant_signal(66),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(56) =>request_signal(56),
+--   request(57) =>request_signal(57),
+--   request(58) =>request_signal(58),
+--   request(59) =>request_signal(59),
+--   request(60) =>request_signal(60),
+--   request(61) =>request_signal(61),
+--   request(62) =>request_signal(62),
+--   request(63) =>request_signal(63),
+--   request(64) =>request_signal(64),
+--   request(65) =>request_signal(65),
+--   request(66) =>request_signal(66)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(67) => grant_signal(67),
+--   grant(68) => grant_signal(68),
+--   grant(69) => grant_signal(69),
+--   grant(70) => grant_signal(70),
+--   grant(71) => grant_signal(71),
+--   grant(72) => grant_signal(72),
+--   grant(73) => grant_signal(73),
+--   grant(74) => grant_signal(74),
+--   grant(75) => grant_signal(75),
+--   grant(76) => grant_signal(76),
+--   grant(77) => grant_signal(77),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(7),
+--   request(67) =>request_signal(67),
+--   request(68) =>request_signal(68),
+--   request(69) =>request_signal(69),
+--   request(70) =>request_signal(70),
+--   request(71) =>request_signal(71),
+--   request(72) =>request_signal(72),
+--   request(73) =>request_signal(73),
+--   request(74) =>request_signal(74),
+--   request(75) =>request_signal(75),
+--   request(76) =>request_signal(76),
+--   request(77) =>request_signal(77)
+--);
+--
+--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(8),
+--   data_in_en => data_in_en(8),
+--   reset => reset,
+--   clk =>clk,
+--   grant(78) => grant_signal(78),
+--   grant(79) => grant_signal(79),
+--   grant(80) => grant_signal(80),
+--   grant(81) => grant_signal(81),
+--   grant(82) => grant_signal(82),
+--   grant(83) => grant_signal(83),
+--   grant(84) => grant_signal(84),
+--   grant(85) => grant_signal(85),
+--   grant(86) => grant_signal(86),
+--   grant(87) => grant_signal(87),
+--   grant(88) => grant_signal(88),
+--   fifo_full =>fifo_in_full(8),
+--   priority_rotation =>  priority_rotation_signal(8),
+--   fifo_empty => fifo_in_empty(8),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(8),
+--   request(78) =>request_signal(78),
+--   request(79) =>request_signal(79),
+--   request(80) =>request_signal(80),
+--   request(81) =>request_signal(81),
+--   request(82) =>request_signal(82),
+--   request(83) =>request_signal(83),
+--   request(84) =>request_signal(84),
+--   request(85) =>request_signal(85),
+--   request(86) =>request_signal(86),
+--   request(87) =>request_signal(87),
+--   request(88) =>request_signal(88)
+--);
+--
+--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(9),
+--   data_in_en => data_in_en(9),
+--   reset => reset,
+--   clk =>clk,
+--   grant(89) => grant_signal(89),
+--   grant(90) => grant_signal(90),
+--   grant(91) => grant_signal(91),
+--   grant(92) => grant_signal(92),
+--   grant(93) => grant_signal(93),
+--   grant(94) => grant_signal(94),
+--   grant(95) => grant_signal(95),
+--   grant(96) => grant_signal(96),
+--   grant(97) => grant_signal(97),
+--   grant(98) => grant_signal(98),
+--   grant(99) => grant_signal(99),
+--   fifo_full =>fifo_in_full(9),
+--   priority_rotation =>  priority_rotation_signal(9),
+--   fifo_empty => fifo_in_empty(9),
+--   data_out =>crossbar_in_port(9),
+--   data_out_pulse =>crossbar_in_pulse(9),
+--   request(89) =>request_signal(89),
+--   request(90) =>request_signal(90),
+--   request(91) =>request_signal(91),
+--   request(92) =>request_signal(92),
+--   request(93) =>request_signal(93),
+--   request(94) =>request_signal(94),
+--   request(95) =>request_signal(95),
+--   request(96) =>request_signal(96),
+--   request(97) =>request_signal(97),
+--   request(98) =>request_signal(98),
+--   request(99) =>request_signal(99)
+--);
+--
+--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(10),
+--   data_in_en => data_in_en(10),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(100),
+--   grant(2) => grant_signal(101),
+--   grant(3) => grant_signal(102),
+--   grant(4) => grant_signal(103),
+--   grant(5) => grant_signal(104),
+--   grant(6) => grant_signal(105),
+--   grant(7) => grant_signal(106),
+--   grant(8) => grant_signal(107),
+--   grant(9) => grant_signal(108),
+--   grant(10) => grant_signal(109),
+--   grant(11) => grant_signal(110),
+--   fifo_full =>fifo_in_full(10),
+--   priority_rotation =>  priority_rotation_signal(10),
+--   fifo_empty => fifo_in_empty(10),
+--   data_out =>crossbar_in_port(10),
+--   data_out_pulse =>crossbar_in_pulse(10),
+--   request(1) =>request_signal(100),
+--   request(2) =>request_signal(101),
+--   request(3) =>request_signal(102),
+--   request(4) =>request_signal(103),
+--   request(5) =>request_signal(104),
+--   request(6) =>request_signal(105),
+--   request(7) =>request_signal(106),
+--   request(8) =>request_signal(107),
+--   request(9) =>request_signal(108),
+--   request(10) =>request_signal(109),
+--   request(11) =>request_signal(110)
+--);
+--
+--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(11),
+--   data_in_en => data_in_en(11),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(111),
+--   grant(2) => grant_signal(112),
+--   grant(3) => grant_signal(113),
+--   grant(4) => grant_signal(114),
+--   grant(5) => grant_signal(115),
+--   grant(6) => grant_signal(116),
+--   grant(7) => grant_signal(117),
+--   grant(8) => grant_signal(118),
+--   grant(9) => grant_signal(119),
+--   grant(10) => grant_signal(120),
+--   grant(11) => grant_signal(121),
+--   fifo_full =>fifo_in_full(11),
+--   priority_rotation =>  priority_rotation_signal(11),
+--   fifo_empty => fifo_in_empty(11),
+--   data_out =>crossbar_in_port(11),
+--   data_out_pulse =>crossbar_in_pulse(11),
+--   request(1) =>request_signal(111),
+--   request(2) =>request_signal(112),
+--   request(3) =>request_signal(113),
+--   request(4) =>request_signal(114),
+--   request(5) =>request_signal(115),
+--   request(6) =>request_signal(116),
+--   request(7) =>request_signal(117),
+--   request(8) =>request_signal(118),
+--   request(9) =>request_signal(119),
+--   request(10) =>request_signal(120),
+--   request(11) =>request_signal(121)
+--);
+--
+--end generate switch11x11;
+--
+--
+---- switch 12 ports
+--switch12x12 : if number_of_ports = 12 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   grant(7) => grant_signal(7),
+--   grant(8) => grant_signal(8),
+--   grant(9) => grant_signal(9),
+--   grant(10) => grant_signal(10),
+--   grant(11) => grant_signal(11),
+--   grant(12) => grant_signal(12),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10),
+--   request(11) =>request_signal(11),
+--   request(12) =>request_signal(12)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(13) => grant_signal(13),
+--   grant(14) => grant_signal(14),
+--   grant(15) => grant_signal(15),
+--   grant(16) => grant_signal(16),
+--   grant(17) => grant_signal(17),
+--   grant(18) => grant_signal(18),
+--   grant(19) => grant_signal(19),
+--   grant(20) => grant_signal(20),
+--   grant(21) => grant_signal(21),
+--   grant(22) => grant_signal(22),
+--   grant(23) => grant_signal(23),
+--   grant(24) => grant_signal(24),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(13) =>request_signal(13),
+--   request(14) =>request_signal(14),
+--   request(15) =>request_signal(15),
+--   request(16) =>request_signal(16),
+--   request(17) =>request_signal(17),
+--   request(18) =>request_signal(18),
+--   request(19) =>request_signal(19),
+--   request(20) =>request_signal(20),
+--   request(21) =>request_signal(21),
+--   request(22) =>request_signal(22),
+--   request(23) =>request_signal(23),
+--   request(24) =>request_signal(24)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(25) => grant_signal(25),
+--   grant(26) => grant_signal(26),
+--   grant(27) => grant_signal(27),
+--   grant(28) => grant_signal(28),
+--   grant(29) => grant_signal(29),
+--   grant(30) => grant_signal(30),
+--   grant(31) => grant_signal(31),
+--   grant(32) => grant_signal(32),
+--   grant(33) => grant_signal(33),
+--   grant(34) => grant_signal(34),
+--   grant(35) => grant_signal(35),
+--   grant(36) => grant_signal(36),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(25) =>request_signal(25),
+--   request(26) =>request_signal(26),
+--   request(27) =>request_signal(27),
+--   request(28) =>request_signal(28),
+--   request(29) =>request_signal(29),
+--   request(30) =>request_signal(30),
+--   request(31) =>request_signal(31),
+--   request(32) =>request_signal(32),
+--   request(33) =>request_signal(33),
+--   request(34) =>request_signal(34),
+--   request(35) =>request_signal(35),
+--   request(36) =>request_signal(36)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(37) => grant_signal(37),
+--   grant(38) => grant_signal(38),
+--   grant(39) => grant_signal(39),
+--   grant(40) => grant_signal(40),
+--   grant(41) => grant_signal(41),
+--   grant(42) => grant_signal(42),
+--   grant(43) => grant_signal(43),
+--   grant(44) => grant_signal(44),
+--   grant(45) => grant_signal(45),
+--   grant(46) => grant_signal(46),
+--   grant(47) => grant_signal(47),
+--   grant(48) => grant_signal(48),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(37) =>request_signal(37),
+--   request(38) =>request_signal(38),
+--   request(39) =>request_signal(39),
+--   request(40) =>request_signal(40),
+--   request(41) =>request_signal(41),
+--   request(42) =>request_signal(42),
+--   request(43) =>request_signal(43),
+--   request(44) =>request_signal(44),
+--   request(45) =>request_signal(45),
+--   request(46) =>request_signal(46),
+--   request(47) =>request_signal(47),
+--   request(48) =>request_signal(48)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(49) => grant_signal(49),
+--   grant(50) => grant_signal(50),
+--   grant(51) => grant_signal(51),
+--   grant(52) => grant_signal(52),
+--   grant(53) => grant_signal(53),
+--   grant(54) => grant_signal(54),
+--   grant(55) => grant_signal(55),
+--   grant(56) => grant_signal(56),
+--   grant(57) => grant_signal(57),
+--   grant(58) => grant_signal(58),
+--   grant(59) => grant_signal(59),
+--   grant(60) => grant_signal(60),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(49) =>request_signal(49),
+--   request(50) =>request_signal(50),
+--   request(51) =>request_signal(51),
+--   request(52) =>request_signal(52),
+--   request(53) =>request_signal(53),
+--   request(54) =>request_signal(54),
+--   request(55) =>request_signal(55),
+--   request(56) =>request_signal(56),
+--   request(57) =>request_signal(57),
+--   request(58) =>request_signal(58),
+--   request(59) =>request_signal(59),
+--   request(60) =>request_signal(60)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(61) => grant_signal(61),
+--   grant(62) => grant_signal(62),
+--   grant(63) => grant_signal(63),
+--   grant(64) => grant_signal(64),
+--   grant(65) => grant_signal(65),
+--   grant(66) => grant_signal(66),
+--   grant(67) => grant_signal(67),
+--   grant(68) => grant_signal(68),
+--   grant(69) => grant_signal(69),
+--   grant(70) => grant_signal(70),
+--   grant(71) => grant_signal(71),
+--   grant(72) => grant_signal(72),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(61) =>request_signal(61),
+--   request(62) =>request_signal(62),
+--   request(63) =>request_signal(63),
+--   request(64) =>request_signal(64),
+--   request(65) =>request_signal(65),
+--   request(66) =>request_signal(66),
+--   request(67) =>request_signal(67),
+--   request(68) =>request_signal(68),
+--   request(69) =>request_signal(69),
+--   request(70) =>request_signal(70),
+--   request(71) =>request_signal(71),
+--   request(72) =>request_signal(72)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(73) => grant_signal(73),
+--   grant(74) => grant_signal(74),
+--   grant(75) => grant_signal(75),
+--   grant(76) => grant_signal(76),
+--   grant(77) => grant_signal(77),
+--   grant(78) => grant_signal(78),
+--   grant(79) => grant_signal(79),
+--   grant(80) => grant_signal(80),
+--   grant(81) => grant_signal(81),
+--   grant(82) => grant_signal(82),
+--   grant(83) => grant_signal(83),
+--   grant(84) => grant_signal(84),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(7),
+--   data_out_pulse =>crossbar_in_pulse(7),
+--   request(73) =>request_signal(73),
+--   request(74) =>request_signal(74),
+--   request(75) =>request_signal(75),
+--   request(76) =>request_signal(76),
+--   request(77) =>request_signal(77),
+--   request(78) =>request_signal(78),
+--   request(79) =>request_signal(79),
+--   request(80) =>request_signal(80),
+--   request(81) =>request_signal(81),
+--   request(82) =>request_signal(82),
+--   request(83) =>request_signal(83),
+--   request(84) =>request_signal(84)
+--);
+--
+--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(8),
+--   data_in_en => data_in_en(8),
+--   reset => reset,
+--   clk =>clk,
+--   grant(85) => grant_signal(85),
+--   grant(86) => grant_signal(86),
+--   grant(87) => grant_signal(87),
+--   grant(88) => grant_signal(88),
+--   grant(89) => grant_signal(89),
+--   grant(90) => grant_signal(90),
+--   grant(91) => grant_signal(91),
+--   grant(92) => grant_signal(92),
+--   grant(93) => grant_signal(93),
+--   grant(94) => grant_signal(94),
+--   grant(95) => grant_signal(95),
+--   grant(96) => grant_signal(96),
+--   fifo_full =>fifo_in_full(8),
+--   priority_rotation =>  priority_rotation_signal(8),
+--   fifo_empty => fifo_in_empty(8),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(8),
+--   request(85) =>request_signal(85),
+--   request(86) =>request_signal(86),
+--   request(87) =>request_signal(87),
+--   request(88) =>request_signal(88),
+--   request(89) =>request_signal(89),
+--   request(90) =>request_signal(90),
+--   request(91) =>request_signal(91),
+--   request(92) =>request_signal(92),
+--   request(93) =>request_signal(93),
+--   request(94) =>request_signal(94),
+--   request(95) =>request_signal(95),
+--   request(96) =>request_signal(96)
+--);
+--
+--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(9),
+--   data_in_en => data_in_en(9),
+--   reset => reset,
+--   clk =>clk,
+--   grant(97) => grant_signal(97),
+--   grant(98) => grant_signal(98),
+--   grant(99) => grant_signal(99),
+--   grant(100) => grant_signal(100),
+--   grant(101) => grant_signal(101),
+--   grant(102) => grant_signal(102),
+--   grant(103) => grant_signal(103),
+--   grant(104) => grant_signal(104),
+--   grant(105) => grant_signal(105),
+--   grant(106) => grant_signal(106),
+--   grant(107) => grant_signal(107),
+--   grant(108) => grant_signal(108),
+--   fifo_full =>fifo_in_full(9),
+--   priority_rotation =>  priority_rotation_signal(9),
+--   fifo_empty => fifo_in_empty(9),
+--   data_out =>crossbar_in_port(9),
+--   data_out_pulse =>crossbar_in_pulse(9),
+--   request(97) =>request_signal(97),
+--   request(98) =>request_signal(98),
+--   request(99) =>request_signal(99),
+--   request(100) =>request_signal(100),
+--   request(101) =>request_signal(101),
+--   request(102) =>request_signal(102),
+--   request(103) =>request_signal(103),
+--   request(104) =>request_signal(104),
+--   request(105) =>request_signal(105),
+--   request(106) =>request_signal(106),
+--   request(107) =>request_signal(107),
+--   request(108) =>request_signal(108)
+--);
+--
+--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(10),
+--   data_in_en => data_in_en(10),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(109),
+--   grant(2) => grant_signal(110),
+--   grant(3) => grant_signal(111),
+--   grant(4) => grant_signal(112),
+--   grant(5) => grant_signal(113),
+--   grant(6) => grant_signal(114),
+--   grant(7) => grant_signal(115),
+--   grant(8) => grant_signal(116),
+--   grant(9) => grant_signal(117),
+--   grant(10) => grant_signal(118),
+--   grant(11) => grant_signal(119),
+--   grant(12) => grant_signal(120),
+--   fifo_full =>fifo_in_full(10),
+--   priority_rotation =>  priority_rotation_signal(10),
+--   fifo_empty => fifo_in_empty(10),
+--   data_out =>crossbar_in_port(10),
+--   data_out_pulse =>crossbar_in_pulse(10),
+--   request(109) =>request_signal(109),
+--   request(110) =>request_signal(110),
+--   request(111) =>request_signal(111),
+--   request(112) =>request_signal(112),
+--   request(113) =>request_signal(113),
+--   request(114) =>request_signal(114),
+--   request(115) =>request_signal(115),
+--   request(116) =>request_signal(116),
+--   request(117) =>request_signal(117),
+--   request(118) =>request_signal(118),
+--   request(119) =>request_signal(119),
+--   request(120) =>request_signal(120)
+--);
+--
+--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(11),
+--   data_in_en => data_in_en(11),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(121),
+--   grant(2) => grant_signal(122),
+--   grant(3) => grant_signal(123),
+--   grant(4) => grant_signal(124),
+--   grant(5) => grant_signal(125),
+--   grant(6) => grant_signal(126),
+--   grant(7) => grant_signal(127),
+--   grant(8) => grant_signal(128),
+--   grant(9) => grant_signal(129),
+--   grant(10) => grant_signal(130),
+--   grant(11) => grant_signal(131),
+--   grant(12) => grant_signal(132),
+--   fifo_full =>fifo_in_full(11),
+--   priority_rotation =>  priority_rotation_signal(11),
+--   fifo_empty => fifo_in_empty(11),
+--   data_out =>crossbar_in_port(11),
+--   data_out_pulse =>crossbar_in_pulse(11),
+--   request(121) =>request_signal(121),
+--   request(122) =>request_signal(122),
+--   request(123) =>request_signal(123),
+--   request(124) =>request_signal(124),
+--   request(125) =>request_signal(125),
+--   request(126) =>request_signal(126),
+--   request(127) =>request_signal(127),
+--   request(128) =>request_signal(128),
+--   request(129) =>request_signal(129),
+--   request(130) =>request_signal(130),
+--   request(131) =>request_signal(131),
+--   request(132) =>request_signal(132)
+--);
+--
+--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(12),
+--   data_in_en => data_in_en(12),
+--   reset => reset,
+--   clk =>clk,
+--   grant(133) => grant_signal(133),
+--   grant(134) => grant_signal(134),
+--   grant(135) => grant_signal(135),
+--   grant(136) => grant_signal(136),
+--   grant(137) => grant_signal(137),
+--   grant(138) => grant_signal(138),
+--   grant(139) => grant_signal(139),
+--   grant(140) => grant_signal(140),
+--   grant(141) => grant_signal(141),
+--   grant(142) => grant_signal(142),
+--   grant(143) => grant_signal(143),
+--   grant(144) => grant_signal(144),
+--   fifo_full =>fifo_in_full(12),
+--   priority_rotation =>  priority_rotation_signal(12),
+--   fifo_empty => fifo_in_empty(12),
+--   data_out =>crossbar_in_port(12),
+--   data_out_pulse =>crossbar_in_pulse(12),
+--   request(133) =>request_signal(133),
+--   request(134) =>request_signal(134),
+--   request(135) =>request_signal(135),
+--   request(136) =>request_signal(136),
+--   request(137) =>request_signal(137),
+--   request(138) =>request_signal(138),
+--   request(139) =>request_signal(139),
+--   request(140) =>request_signal(140),
+--   request(141) =>request_signal(141),
+--   request(142) =>request_signal(142),
+--   request(143) =>request_signal(143),
+--   request(144) =>request_signal(144)
+--);
+--
+--end generate switch12x12;
+--
+--
+---- switch 13 ports
+--switch13x13 : if number_of_ports = 13 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   grant(7) => grant_signal(7),
+--   grant(8) => grant_signal(8),
+--   grant(9) => grant_signal(9),
+--   grant(10) => grant_signal(10),
+--   grant(11) => grant_signal(11),
+--   grant(12) => grant_signal(12),
+--   grant(13) => grant_signal(13),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10),
+--   request(11) =>request_signal(11),
+--   request(12) =>request_signal(12),
+--   request(13) =>request_signal(13)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(14) => grant_signal(14),
+--   grant(15) => grant_signal(15),
+--   grant(16) => grant_signal(16),
+--   grant(17) => grant_signal(17),
+--   grant(18) => grant_signal(18),
+--   grant(19) => grant_signal(19),
+--   grant(20) => grant_signal(20),
+--   grant(21) => grant_signal(21),
+--   grant(22) => grant_signal(22),
+--   grant(23) => grant_signal(23),
+--   grant(24) => grant_signal(24),
+--   grant(25) => grant_signal(25),
+--   grant(26) => grant_signal(26),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(14) =>request_signal(14),
+--   request(15) =>request_signal(15),
+--   request(16) =>request_signal(16),
+--   request(17) =>request_signal(17),
+--   request(18) =>request_signal(18),
+--   request(19) =>request_signal(19),
+--   request(20) =>request_signal(20),
+--   request(21) =>request_signal(21),
+--   request(22) =>request_signal(22),
+--   request(23) =>request_signal(23),
+--   request(24) =>request_signal(24),
+--   request(25) =>request_signal(25),
+--   request(26) =>request_signal(26)
+--);
+
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(27) => grant_signal(27),
+--   grant(28) => grant_signal(28),
+--   grant(29) => grant_signal(29),
+--   grant(30) => grant_signal(30),
+--   grant(31) => grant_signal(31),
+--   grant(32) => grant_signal(32),
+--   grant(33) => grant_signal(33),
+--   grant(34) => grant_signal(34),
+--   grant(35) => grant_signal(35),
+--   grant(36) => grant_signal(36),
+--   grant(37) => grant_signal(37),
+--   grant(38) => grant_signal(38),
+--   grant(39) => grant_signal(39),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(27) =>request_signal(27),
+--   request(28) =>request_signal(28),
+--   request(29) =>request_signal(29),
+--   request(30) =>request_signal(30),
+--   request(31) =>request_signal(31),
+--   request(32) =>request_signal(32),
+--   request(33) =>request_signal(33),
+--   request(34) =>request_signal(34),
+--   request(35) =>request_signal(35),
+--   request(36) =>request_signal(36),
+--   request(37) =>request_signal(37),
+--   request(38) =>request_signal(38),
+--   request(39) =>request_signal(39)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(40) => grant_signal(40),
+--   grant(41) => grant_signal(41),
+--   grant(42) => grant_signal(42),
+--   grant(43) => grant_signal(43),
+--   grant(44) => grant_signal(44),
+--   grant(45) => grant_signal(45),
+--   grant(46) => grant_signal(46),
+--   grant(47) => grant_signal(47),
+--   grant(48) => grant_signal(48),
+--   grant(49) => grant_signal(49),
+--   grant(50) => grant_signal(50),
+--   grant(51) => grant_signal(51),
+--   grant(52) => grant_signal(52),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(40) =>request_signal(40),
+--   request(41) =>request_signal(41),
+--   request(42) =>request_signal(42),
+--   request(43) =>request_signal(43),
+--   request(44) =>request_signal(44),
+--   request(45) =>request_signal(45),
+--   request(46) =>request_signal(46),
+--   request(47) =>request_signal(47),
+--   request(48) =>request_signal(48),
+--   request(49) =>request_signal(49),
+--   request(50) =>request_signal(50),
+--   request(51) =>request_signal(51),
+--   request(52) =>request_signal(52)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(53) => grant_signal(53),
+--   grant(54) => grant_signal(54),
+--   grant(55) => grant_signal(55),
+--   grant(56) => grant_signal(56),
+--   grant(57) => grant_signal(57),
+--   grant(58) => grant_signal(58),
+--   grant(59) => grant_signal(59),
+--   grant(60) => grant_signal(60),
+--   grant(61) => grant_signal(61),
+--   grant(62) => grant_signal(62),
+--   grant(63) => grant_signal(63),
+--   grant(64) => grant_signal(64),
+--   grant(65) => grant_signal(65),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(53) =>request_signal(53),
+--   request(54) =>request_signal(54),
+--   request(55) =>request_signal(55),
+--   request(56) =>request_signal(56),
+--   request(57) =>request_signal(57),
+--   request(58) =>request_signal(58),
+--   request(59) =>request_signal(59),
+--   request(60) =>request_signal(60),
+--   request(61) =>request_signal(61),
+--   request(62) =>request_signal(62),
+--   request(63) =>request_signal(63),
+--   request(64) =>request_signal(64),
+--   request(65) =>request_signal(65)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(66) => grant_signal(66),
+--   grant(67) => grant_signal(67),
+--   grant(68) => grant_signal(68),
+--   grant(69) => grant_signal(69),
+--   grant(70) => grant_signal(70),
+--   grant(71) => grant_signal(71),
+--   grant(72) => grant_signal(72),
+--   grant(73) => grant_signal(73),
+--   grant(74) => grant_signal(74),
+--   grant(75) => grant_signal(75),
+--   grant(76) => grant_signal(76),
+--   grant(77) => grant_signal(77),
+--   grant(78) => grant_signal(78),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(66) =>request_signal(66),
+--   request(67) =>request_signal(67),
+--   request(68) =>request_signal(68),
+--   request(69) =>request_signal(69),
+--   request(70) =>request_signal(70),
+--   request(71) =>request_signal(71),
+--   request(72) =>request_signal(72),
+--   request(73) =>request_signal(73),
+--   request(74) =>request_signal(74),
+--   request(75) =>request_signal(75),
+--   request(76) =>request_signal(76),
+--   request(77) =>request_signal(77),
+--   request(78) =>request_signal(78)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(79) => grant_signal(79),
+--   grant(80) => grant_signal(80),
+--   grant(81) => grant_signal(81),
+--   grant(82) => grant_signal(82),
+--   grant(83) => grant_signal(83),
+--   grant(84) => grant_signal(84),
+--   grant(85) => grant_signal(85),
+--   grant(86) => grant_signal(86),
+--   grant(87) => grant_signal(87),
+--   grant(88) => grant_signal(88),
+--   grant(89) => grant_signal(89),
+--   grant(90) => grant_signal(90),
+--   grant(91) => grant_signal(91),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(7),
+--   data_out_pulse =>crossbar_in_pulse(7),
+--   request(79) =>request_signal(79),
+--   request(80) =>request_signal(80),
+--   request(81) =>request_signal(81),
+--   request(82) =>request_signal(82),
+--   request(83) =>request_signal(83),
+--   request(84) =>request_signal(84),
+--   request(85) =>request_signal(85),
+--   request(86) =>request_signal(86),
+--   request(87) =>request_signal(87),
+--   request(88) =>request_signal(88),
+--   request(89) =>request_signal(89),
+--   request(90) =>request_signal(90),
+--   request(91) =>request_signal(91)
+--);
+--
+--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(8),
+--   data_in_en => data_in_en(8),
+--   reset => reset,
+--   clk =>clk,
+--   grant(92) => grant_signal(92),
+--   grant(93) => grant_signal(93),
+--   grant(94) => grant_signal(94),
+--   grant(95) => grant_signal(95),
+--   grant(96) => grant_signal(96),
+--   grant(97) => grant_signal(97),
+--   grant(98) => grant_signal(98),
+--   grant(99) => grant_signal(99),
+--   grant(100) => grant_signal(100),
+--   grant(101) => grant_signal(101),
+--   grant(102) => grant_signal(102),
+--   grant(103) => grant_signal(103),
+--   grant(104) => grant_signal(104),
+--   fifo_full =>fifo_in_full(8),
+--   priority_rotation =>  priority_rotation_signal(8),
+--   fifo_empty => fifo_in_empty(8),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(8),
+--   request(92) =>request_signal(92),
+--   request(93) =>request_signal(93),
+--   request(94) =>request_signal(94),
+--   request(95) =>request_signal(95),
+--   request(96) =>request_signal(96),
+--   request(97) =>request_signal(97),
+--   request(98) =>request_signal(98),
+--   request(99) =>request_signal(99),
+--   request(100) =>request_signal(100),
+--   request(101) =>request_signal(101),
+--   request(102) =>request_signal(102),
+--   request(103) =>request_signal(103),
+--   request(104) =>request_signal(104)
+--);
+--
+--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(9),
+--   data_in_en => data_in_en(9),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(105),
+--   grant(2) => grant_signal(106),
+--   grant(3) => grant_signal(107),
+--   grant(4) => grant_signal(108),
+--   grant(5) => grant_signal(109),
+--   grant(6) => grant_signal(110),
+--   grant(7) => grant_signal(111),
+--   grant(8) => grant_signal(112),
+--   grant(9) => grant_signal(113),
+--   grant(10) => grant_signal(114),
+--   grant(11) => grant_signal(115),
+--   grant(12) => grant_signal(116),
+--   grant(13) => grant_signal(117),
+--   fifo_full =>fifo_in_full(9),
+--   priority_rotation =>  priority_rotation_signal(9),
+--   fifo_empty => fifo_in_empty(9),
+--   data_out =>crossbar_in_port(9),
+--   data_out_pulse =>crossbar_in_pulse(9),
+--   request(105) =>request_signal(105),
+--   request(106) =>request_signal(106),
+--   request(107) =>request_signal(107),
+--   request(108) =>request_signal(108),
+--   request(109) =>request_signal(109),
+--   request(110) =>request_signal(110),
+--   request(111) =>request_signal(111),
+--   request(112) =>request_signal(112),
+--   request(113) =>request_signal(113),
+--   request(114) =>request_signal(114),
+--   request(115) =>request_signal(115),
+--   request(116) =>request_signal(116),
+--   request(117) =>request_signal(117)
+--);
+--
+--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(10),
+--   data_in_en => data_in_en(10),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(118),
+--   grant(2) => grant_signal(119),
+--   grant(3) => grant_signal(120),
+--   grant(4) => grant_signal(121),
+--   grant(5) => grant_signal(122),
+--   grant(6) => grant_signal(123),
+--   grant(7) => grant_signal(124),
+--   grant(8) => grant_signal(125),
+--   grant(9) => grant_signal(126),
+--   grant(10) => grant_signal(127),
+--   grant(11) => grant_signal(128),
+--   grant(12) => grant_signal(129),
+--   grant(13) => grant_signal(130),
+--   fifo_full =>fifo_in_full(10),
+--   priority_rotation =>  priority_rotation_signal(10),
+--   fifo_empty => fifo_in_empty(10),
+--   data_out =>crossbar_in_port(10),
+--   data_out_pulse =>crossbar_in_pulse(10),
+--   request(1) =>request_signal(118),
+--   request(2) =>request_signal(119),
+--   request(3) =>request_signal(120),
+--   request(4) =>request_signal(121),
+--   request(5) =>request_signal(122),
+--   request(6) =>request_signal(123),
+--   request(7) =>request_signal(124),
+--   request(8) =>request_signal(125),
+--   request(9) =>request_signal(126),
+--   request(10) =>request_signal(127),
+--   request(11) =>request_signal(128),
+--   request(12) =>request_signal(129),
+--   request(13) =>request_signal(130)
+--);
+--
+--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(11),
+--   data_in_en => data_in_en(11),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(131),
+--   grant(2) => grant_signal(132),
+--   grant(3) => grant_signal(133),
+--   grant(4) => grant_signal(134),
+--   grant(5) => grant_signal(135),
+--   grant(6) => grant_signal(136),
+--   grant(7) => grant_signal(137),
+--   grant(8) => grant_signal(138),
+--   grant(9) => grant_signal(139),
+--   grant(10) => grant_signal(140),
+--   grant(11) => grant_signal(141),
+--   grant(12) => grant_signal(142),
+--   grant(13) => grant_signal(143),
+--   fifo_full =>fifo_in_full(11),
+--   priority_rotation =>  priority_rotation_signal(11),
+--   fifo_empty => fifo_in_empty(11),
+--   data_out =>crossbar_in_port(11),
+--   data_out_pulse =>crossbar_in_pulse(11),
+--   request(1) =>request_signal(131),
+--   request(2) =>request_signal(132),
+--   request(3) =>request_signal(133),
+--   request(4) =>request_signal(134),
+--   request(5) =>request_signal(135),
+--   request(6) =>request_signal(136),
+--   request(7) =>request_signal(137),
+--   request(8) =>request_signal(138),
+--   request(9) =>request_signal(139),
+--   request(10) =>request_signal(140),
+--   request(11) =>request_signal(141),
+--   request(12) =>request_signal(142),
+--   request(13) =>request_signal(143)
+--);
+--
+--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(12),
+--   data_in_en => data_in_en(12),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(144),
+--   grant(2) => grant_signal(145),
+--   grant(3) => grant_signal(146),
+--   grant(4) => grant_signal(147),
+--   grant(5) => grant_signal(148),
+--   grant(6) => grant_signal(149),
+--   grant(7) => grant_signal(150),
+--   grant(8) => grant_signal(151),
+--   grant(9) => grant_signal(152),
+--   grant(10) => grant_signal(153),
+--   grant(11) => grant_signal(154),
+--   grant(12) => grant_signal(155),
+--   grant(13) => grant_signal(156),
+--   fifo_full =>fifo_in_full(12),
+--   priority_rotation =>  priority_rotation_signal(12),
+--   fifo_empty => fifo_in_empty(12),
+--   data_out =>crossbar_in_port(12),
+--   data_out_pulse =>crossbar_in_pulse(12),
+--   request(1) =>request_signal(144),
+--   request(2) =>request_signal(145),
+--   request(3) =>request_signal(146),
+--   request(4) =>request_signal(147),
+--   request(5) =>request_signal(148),
+--   request(6) =>request_signal(149),
+--   request(7) =>request_signal(150),
+--   request(8) =>request_signal(151),
+--   request(9) =>request_signal(152),
+--   request(10) =>request_signal(153),
+--   request(11) =>request_signal(154),
+--   request(12) =>request_signal(155),
+--   request(13) =>request_signal(156)
+--);
+--
+--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(13),
+--   data_in_en => data_in_en(13),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(157),
+--   grant(2) => grant_signal(158),
+--   grant(3) => grant_signal(159),
+--   grant(4) => grant_signal(160),
+--   grant(5) => grant_signal(161),
+--   grant(6) => grant_signal(162),
+--   grant(7) => grant_signal(163),
+--   grant(8) => grant_signal(164),
+--   grant(9) => grant_signal(165),
+--   grant(10) => grant_signal(166),
+--   grant(11) => grant_signal(167),
+--   grant(12) => grant_signal(168),
+--   grant(13) => grant_signal(169),
+--   fifo_full =>fifo_in_full(13),
+--   priority_rotation =>  priority_rotation_signal(13),
+--   fifo_empty => fifo_in_empty(13),
+--   data_out =>crossbar_in_port(13),
+--   data_out_pulse =>crossbar_in_pulse(13),
+--   request(1) =>request_signal(157),
+--   request(2) =>request_signal(158),
+--   request(3) =>request_signal(159),
+--   request(4) =>request_signal(160),
+--   request(5) =>request_signal(161),
+--   request(6) =>request_signal(162),
+--   request(7) =>request_signal(163),
+--   request(8) =>request_signal(164),
+--   request(9) =>request_signal(165),
+--   request(10) =>request_signal(166),
+--   request(11) =>request_signal(167),
+--   request(12) =>request_signal(168),
+--   request(13) =>request_signal(169)
+--);
+--
+--end generate switch13x13;
+--
+--
+---- switch 14 ports
+--switch14x14 : if number_of_ports = 14 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   grant(7) => grant_signal(7),
+--   grant(8) => grant_signal(8),
+--   grant(9) => grant_signal(9),
+--   grant(10) => grant_signal(10),
+--   grant(11) => grant_signal(11),
+--   grant(12) => grant_signal(12),
+--   grant(13) => grant_signal(13),
+--   grant(14) => grant_signal(14),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10),
+--   request(11) =>request_signal(11),
+--   request(12) =>request_signal(12),
+--   request(13) =>request_signal(13),
+--   request(14) =>request_signal(14)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(15),
+--   grant(2) => grant_signal(16),
+--   grant(3) => grant_signal(17),
+--   grant(4) => grant_signal(18),
+--   grant(5) => grant_signal(19),
+--   grant(6) => grant_signal(20),
+--   grant(7) => grant_signal(21),
+--   grant(8) => grant_signal(22),
+--   grant(9) => grant_signal(23),
+--   grant(10) => grant_signal(24),
+--   grant(11) => grant_signal(25),
+--   grant(12) => grant_signal(26),
+--   grant(13) => grant_signal(27),
+--   grant(14) => grant_signal(28),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(1) =>request_signal(15),
+--   request(2) =>request_signal(16),
+--   request(3) =>request_signal(17),
+--   request(4) =>request_signal(18),
+--   request(5) =>request_signal(19),
+--   request(6) =>request_signal(20),
+--   request(7) =>request_signal(21),
+--   request(8) =>request_signal(22),
+--   request(9) =>request_signal(23),
+--   request(10) =>request_signal(24),
+--   request(11) =>request_signal(25),
+--   request(12) =>request_signal(26),
+--   request(13) =>request_signal(27),
+--   request(14) =>request_signal(28)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(29),
+--   grant(2) => grant_signal(30),
+--   grant(3) => grant_signal(31),
+--   grant(4) => grant_signal(32),
+--   grant(5) => grant_signal(33),
+--   grant(6) => grant_signal(34),
+--   grant(7) => grant_signal(35),
+--   grant(8) => grant_signal(36),
+--   grant(9) => grant_signal(37),
+--   grant(10)=> grant_signal(38),
+--   grant(11) => grant_signal(39),
+--   grant(12) => grant_signal(40),
+--   grant(13) => grant_signal(41),
+--   grant(14) => grant_signal(42),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(01) =>request_signal(29),
+--   request(02) =>request_signal(30),
+--   request(03) =>request_signal(31),
+--   request(04) =>request_signal(32),
+--   request(05) =>request_signal(33),
+--   request(06) =>request_signal(34),
+--   request(07) =>request_signal(35),
+--   request(08) =>request_signal(36),
+--   request(09) =>request_signal(37),
+--   request(10) =>request_signal(38),
+--   request(11) =>request_signal(39),
+--   request(12) =>request_signal(40),
+--   request(13) =>request_signal(41),
+--   request(14) =>request_signal(42)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(01) => grant_signal(43),
+--   grant(02) => grant_signal(44),
+--   grant(03) => grant_signal(45),
+--   grant(04) => grant_signal(46),
+--   grant(05) => grant_signal(47),
+--   grant(06) => grant_signal(48),
+--   grant(07) => grant_signal(49),
+--   grant(08) => grant_signal(50),
+--   grant(09) => grant_signal(51),
+--   grant(10) => grant_signal(52),
+--   grant(11) => grant_signal(53),
+--   grant(12) => grant_signal(54),
+--   grant(13) => grant_signal(55),
+--   grant(14) => grant_signal(56),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(01) =>request_signal(43),
+--   request(02) =>request_signal(44),
+--   request(03) =>request_signal(45),
+--   request(04) =>request_signal(46),
+--   request(05) =>request_signal(47),
+--   request(06) =>request_signal(48),
+--   request(07) =>request_signal(49),
+--   request(08) =>request_signal(50),
+--   request(09) =>request_signal(51),
+--   request(10) =>request_signal(52),
+--   request(11) =>request_signal(53),
+--   request(12) =>request_signal(54),
+--   request(13) =>request_signal(55),
+--   request(14) =>request_signal(56)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(01) => grant_signal(57),
+--   grant(02) => grant_signal(58),
+--   grant(03) => grant_signal(59),
+--   grant(04) => grant_signal(60),
+--   grant(05) => grant_signal(61),
+--   grant(06) => grant_signal(62),
+--   grant(07) => grant_signal(63),
+--   grant(08) => grant_signal(64),
+--   grant(09) => grant_signal(65),
+--   grant(10) => grant_signal(66),
+--   grant(11) => grant_signal(67),
+--   grant(12) => grant_signal(68),
+--   grant(13) => grant_signal(69),
+--   grant(14) => grant_signal(70),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(01) =>request_signal(57),
+--   request(02) =>request_signal(58),
+--   request(03) =>request_signal(59),
+--   request(04) =>request_signal(60),
+--   request(05) =>request_signal(61),
+--   request(06) =>request_signal(62),
+--   request(07) =>request_signal(63),
+--   request(08) =>request_signal(64),
+--   request(09) =>request_signal(65),
+--   request(10) =>request_signal(66),
+--   request(11) =>request_signal(67),
+--   request(12) =>request_signal(68),
+--   request(13) =>request_signal(69),
+--   request(14) =>request_signal(70)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(01) => grant_signal(71),
+--   grant(02) => grant_signal(72),
+--   grant(03) => grant_signal(73),
+--   grant(04) => grant_signal(74),
+--   grant(05) => grant_signal(75),
+--   grant(06) => grant_signal(76),
+--   grant(07) => grant_signal(77),
+--   grant(08) => grant_signal(78),
+--   grant(09) => grant_signal(79),
+--   grant(10) => grant_signal(80),
+--   grant(11) => grant_signal(81),
+--   grant(12) => grant_signal(82),
+--   grant(13) => grant_signal(83),
+--   grant(14) => grant_signal(84),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(01) =>request_signal(71),
+--   request(02) =>request_signal(72),
+--   request(03) =>request_signal(73),
+--   request(04) =>request_signal(74),
+--   request(05) =>request_signal(75),
+--   request(06) =>request_signal(76),
+--   request(07) =>request_signal(77),
+--   request(08) =>request_signal(78),
+--   request(09) =>request_signal(79),
+--   request(10) =>request_signal(80),
+--   request(11) =>request_signal(81),
+--   request(12) =>request_signal(82),
+--   request(13) =>request_signal(83),
+--   request(14) =>request_signal(84)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(01) => grant_signal(85),
+--   grant(02) => grant_signal(86),
+--   grant(03) => grant_signal(87),
+--   grant(04) => grant_signal(88),
+--   grant(05) => grant_signal(89),
+--   grant(06) => grant_signal(90),
+--   grant(07) => grant_signal(91),
+--   grant(08) => grant_signal(92),
+--   grant(09) => grant_signal(93),
+--   grant(10) => grant_signal(94),
+--   grant(11) => grant_signal(95),
+--   grant(12) => grant_signal(96),
+--   grant(13) => grant_signal(97),
+--   grant(14) => grant_signal(98),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(7),
+--   data_out_pulse =>crossbar_in_pulse(7),
+--   request(01) =>request_signal(85),
+--   request(02) =>request_signal(86),
+--   request(03) =>request_signal(87),
+--   request(04) =>request_signal(88),
+--   request(05) =>request_signal(89),
+--   request(06) =>request_signal(90),
+--   request(07) =>request_signal(91),
+--   request(08) =>request_signal(92),
+--   request(09) =>request_signal(93),
+--   request(10) =>request_signal(94),
+--   request(11) =>request_signal(95),
+--   request(12) =>request_signal(96),
+--   request(13) =>request_signal(97),
+--   request(14) =>request_signal(98)
+--);
+--
+--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(8),
+--   data_in_en => data_in_en(8),
+--   reset => reset,
+--   clk =>clk,
+--   grant(01) => grant_signal(99),
+--   grant(02) => grant_signal(100),
+--   grant(03) => grant_signal(101),
+--   grant(04) => grant_signal(102),
+--   grant(05) => grant_signal(103),
+--   grant(06) => grant_signal(104),
+--   grant(07) => grant_signal(105),
+--   grant(08) => grant_signal(106),
+--   grant(09) => grant_signal(107),
+--   grant(10) => grant_signal(108),
+--   grant(11) => grant_signal(109),
+--   grant(12) => grant_signal(110),
+--   grant(13) => grant_signal(111),
+--   grant(14) => grant_signal(112),
+--   fifo_full =>fifo_in_full(8),
+--   priority_rotation =>  priority_rotation_signal(8),
+--   fifo_empty => fifo_in_empty(8),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(8),
+--   request(1) =>request_signal(99),
+--   request(2) =>request_signal(100),
+--   request(3) =>request_signal(101),
+--   request(4) =>request_signal(102),
+--   request(5) =>request_signal(103),
+--   request(6) =>request_signal(104),
+--   request(7) =>request_signal(105),
+--   request(8) =>request_signal(106),
+--   request(9) =>request_signal(107),
+--   request(10) =>request_signal(108),
+--   request(11) =>request_signal(109),
+--   request(12) =>request_signal(110),
+--   request(13) =>request_signal(111),
+--   request(14) =>request_signal(112)
+--);
+--
+--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(9),
+--   data_in_en => data_in_en(9),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(113),
+--   grant(2) => grant_signal(114),
+--   grant(3) => grant_signal(115),
+--   grant(4) => grant_signal(116),
+--   grant(5) => grant_signal(117),
+--   grant(6) => grant_signal(118),
+--   grant(7) => grant_signal(119),
+--   grant(8) => grant_signal(120),
+--   grant(9) => grant_signal(121),
+--   grant(10) => grant_signal(122),
+--   grant(11) => grant_signal(123),
+--   grant(12) => grant_signal(124),
+--   grant(13) => grant_signal(125),
+--   grant(14) => grant_signal(126),
+--   fifo_full =>fifo_in_full(9),
+--   priority_rotation =>  priority_rotation_signal(9),
+--   fifo_empty => fifo_in_empty(9),
+--   data_out =>crossbar_in_port(9),
+--   data_out_pulse =>crossbar_in_pulse(9),
+--   request(1) =>request_signal(113),
+--   request(2) =>request_signal(114),
+--   request(3) =>request_signal(115),
+--   request(4) =>request_signal(116),
+--   request(5) =>request_signal(117),
+--   request(6) =>request_signal(118),
+--   request(7) =>request_signal(119),
+--   request(8) =>request_signal(120),
+--   request(9) =>request_signal(121),
+--   request(10) =>request_signal(122),
+--   request(11) =>request_signal(123),
+--   request(12) =>request_signal(124),
+--   request(13) =>request_signal(125),
+--   request(14) =>request_signal(126)
+--);
+--
+--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(10),
+--   data_in_en => data_in_en(10),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(127),
+--   grant(2) => grant_signal(128),
+--   grant(3) => grant_signal(129),
+--   grant(4) => grant_signal(130),
+--   grant(5) => grant_signal(131),
+--   grant(6) => grant_signal(132),
+--   grant(7) => grant_signal(133),
+--   grant(8) => grant_signal(134),
+--   grant(9) => grant_signal(135),
+--   grant(10) => grant_signal(136),
+--   grant(11) => grant_signal(137),
+--   grant(12) => grant_signal(138),
+--   grant(13) => grant_signal(139),
+--   grant(14) => grant_signal(140),
+--   fifo_full =>fifo_in_full(10),
+--   priority_rotation =>  priority_rotation_signal(10),
+--   fifo_empty => fifo_in_empty(10),
+--   data_out =>crossbar_in_port(10),
+--   data_out_pulse =>crossbar_in_pulse(10),
+--   request(1) =>request_signal(127),
+--   request(2) =>request_signal(128),
+--   request(3) =>request_signal(129),
+--   request(4) =>request_signal(130),
+--   request(5) =>request_signal(131),
+--   request(6) =>request_signal(132),
+--   request(7) =>request_signal(133),
+--   request(8) =>request_signal(134),
+--   request(9) =>request_signal(135),
+--   request(10) =>request_signal(136),
+--   request(11) =>request_signal(137),
+--   request(12) =>request_signal(138),
+--   request(13) =>request_signal(139),
+--   request(14) =>request_signal(140)
+--);
+--
+--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(11),
+--   data_in_en => data_in_en(11),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(141),
+--   grant(2) => grant_signal(142),
+--   grant(3) => grant_signal(143),
+--   grant(4) => grant_signal(144),
+--   grant(5) => grant_signal(145),
+--   grant(6) => grant_signal(146),
+--   grant(7) => grant_signal(147),
+--   grant(8) => grant_signal(148),
+--   grant(9) => grant_signal(149),
+--   grant(10) => grant_signal(150),
+--   grant(11) => grant_signal(151),
+--   grant(12) => grant_signal(152),
+--   grant(13) => grant_signal(153),
+--   grant(14) => grant_signal(154),
+--   fifo_full =>fifo_in_full(11),
+--   priority_rotation =>  priority_rotation_signal(11),
+--   fifo_empty => fifo_in_empty(11),
+--   data_out =>crossbar_in_port(11),
+--   data_out_pulse =>crossbar_in_pulse(11),
+--   request(1) =>request_signal(141),
+--   request(2) =>request_signal(142),
+--   request(3) =>request_signal(143),
+--   request(4) =>request_signal(144),
+--   request(5) =>request_signal(145),
+--   request(6) =>request_signal(146),
+--   request(7) =>request_signal(147),
+--   request(8) =>request_signal(148),
+--   request(9) =>request_signal(149),
+--   request(10) =>request_signal(150),
+--   request(11) =>request_signal(151),
+--   request(12) =>request_signal(152),
+--   request(13) =>request_signal(153),
+--   request(14) =>request_signal(154)
+--);
+--
+--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(12),
+--   data_in_en => data_in_en(12),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(155),
+--   grant(2) => grant_signal(156),
+--   grant(3) => grant_signal(157),
+--   grant(4) => grant_signal(158),
+--   grant(5) => grant_signal(159),
+--   grant(6) => grant_signal(160),
+--   grant(7) => grant_signal(161),
+--   grant(8) => grant_signal(162),
+--   grant(9) => grant_signal(163),
+--   grant(10) => grant_signal(164),
+--   grant(11) => grant_signal(165),
+--   grant(12) => grant_signal(166),
+--   grant(13) => grant_signal(167),
+--   grant(14) => grant_signal(168),
+--   fifo_full =>fifo_in_full(12),
+--   priority_rotation =>  priority_rotation_signal(12),
+--   fifo_empty => fifo_in_empty(12),
+--   data_out =>crossbar_in_port(12),
+--   data_out_pulse =>crossbar_in_pulse(12),
+--   request(1) =>request_signal(155),
+--   request(2) =>request_signal(156),
+--   request(3) =>request_signal(157),
+--   request(4) =>request_signal(158),
+--   request(5) =>request_signal(159),
+--   request(6) =>request_signal(160),
+--   request(7) =>request_signal(161),
+--   request(8) =>request_signal(162),
+--   request(9) =>request_signal(163),
+--   request(10) =>request_signal(164),
+--   request(11) =>request_signal(165),
+--   request(12) =>request_signal(166),
+--   request(13) =>request_signal(167),
+--   request(14) =>request_signal(168)
+--);
+--
+--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(13),
+--   data_in_en => data_in_en(13),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(169),
+--   grant(2) => grant_signal(170),
+--   grant(3) => grant_signal(171),
+--   grant(4) => grant_signal(172),
+--   grant(5) => grant_signal(173),
+--   grant(6) => grant_signal(174),
+--   grant(7) => grant_signal(175),
+--   grant(8) => grant_signal(176),
+--   grant(9) => grant_signal(177),
+--   grant(10) => grant_signal(178),
+--   grant(11) => grant_signal(179),
+--   grant(12) => grant_signal(180),
+--   grant(13) => grant_signal(181),
+--   grant(14) => grant_signal(182),
+--   fifo_full =>fifo_in_full(13),
+--   priority_rotation =>  priority_rotation_signal(13),
+--   fifo_empty => fifo_in_empty(13),
+--   data_out =>crossbar_in_port(13),
+--   data_out_pulse =>crossbar_in_pulse(13),
+--   request(1) =>request_signal(169),
+--   request(2) =>request_signal(170),
+--   request(3) =>request_signal(171),
+--   request(4) =>request_signal(172),
+--   request(5) =>request_signal(173),
+--   request(6) =>request_signal(174),
+--   request(7) =>request_signal(175),
+--   request(8) =>request_signal(176),
+--   request(9) =>request_signal(177),
+--   request(10) =>request_signal(178),
+--   request(11) =>request_signal(179),
+--   request(12) =>request_signal(180),
+--   request(13) =>request_signal(181),
+--   request(14) =>request_signal(182)
+--);
+--
+--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(14),
+--   data_in_en => data_in_en(14),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(183),
+--   grant(2) => grant_signal(184),
+--   grant(3) => grant_signal(185),
+--   grant(4) => grant_signal(186),
+--   grant(5) => grant_signal(187),
+--   grant(6) => grant_signal(188),
+--   grant(7) => grant_signal(189),
+--   grant(8) => grant_signal(190),
+--   grant(9) => grant_signal(191),
+--   grant(10) => grant_signal(192),
+--   grant(11) => grant_signal(193),
+--   grant(12) => grant_signal(194),
+--   grant(13) => grant_signal(195),
+--   grant(14) => grant_signal(196),
+--   fifo_full =>fifo_in_full(14),
+--   priority_rotation =>  priority_rotation_signal(14),
+--   fifo_empty => fifo_in_empty(14),
+--   data_out =>crossbar_in_port(14),
+--   data_out_pulse =>crossbar_in_pulse(14),
+--   request(1) =>request_signal(183),
+--   request(2) =>request_signal(184),
+--   request(3) =>request_signal(185),
+--   request(4) =>request_signal(186),
+--   request(5) =>request_signal(187),
+--   request(6) =>request_signal(188),
+--   request(7) =>request_signal(189),
+--   request(8) =>request_signal(190),
+--   request(9) =>request_signal(191),
+--   request(10) =>request_signal(192),
+--   request(11) =>request_signal(193),
+--   request(12) =>request_signal(194),
+--   request(13) =>request_signal(195),
+--   request(14) =>request_signal(196)
+--);
+--
+--end generate switch14x14;
+--
+--
+---- switch 15 ports
+--switch15x15 : if number_of_ports = 15 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   grant(7) => grant_signal(7),
+--   grant(8) => grant_signal(8),
+--   grant(9) => grant_signal(9),
+--   grant(10) => grant_signal(10),
+--   grant(11) => grant_signal(11),
+--   grant(12) => grant_signal(12),
+--   grant(13) => grant_signal(13),
+--   grant(14) => grant_signal(14),
+--   grant(15) => grant_signal(15),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10),
+--   request(11) =>request_signal(11),
+--   request(12) =>request_signal(12),
+--   request(13) =>request_signal(13),
+--   request(14) =>request_signal(14),
+--   request(15) =>request_signal(15)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(16) => grant_signal(16),
+--   grant(17) => grant_signal(17),
+--   grant(18) => grant_signal(18),
+--   grant(19) => grant_signal(19),
+--   grant(20) => grant_signal(20),
+--   grant(21) => grant_signal(21),
+--   grant(22) => grant_signal(22),
+--   grant(23) => grant_signal(23),
+--   grant(24) => grant_signal(24),
+--   grant(25) => grant_signal(25),
+--   grant(26) => grant_signal(26),
+--   grant(27) => grant_signal(27),
+--   grant(28) => grant_signal(28),
+--   grant(29) => grant_signal(29),
+--   grant(30) => grant_signal(30),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(16) =>request_signal(16),
+--   request(17) =>request_signal(17),
+--   request(18) =>request_signal(18),
+--   request(19) =>request_signal(19),
+--   request(20) =>request_signal(20),
+--   request(21) =>request_signal(21),
+--   request(22) =>request_signal(22),
+--   request(23) =>request_signal(23),
+--   request(24) =>request_signal(24),
+--   request(25) =>request_signal(25),
+--   request(26) =>request_signal(26),
+--   request(27) =>request_signal(27),
+--   request(28) =>request_signal(28),
+--   request(29) =>request_signal(29),
+--   request(30) =>request_signal(30)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(31) => grant_signal(31),
+--   grant(32) => grant_signal(32),
+--   grant(33) => grant_signal(33),
+--   grant(34) => grant_signal(34),
+--   grant(35) => grant_signal(35),
+--   grant(36) => grant_signal(36),
+--   grant(37) => grant_signal(37),
+--   grant(38) => grant_signal(38),
+--   grant(39) => grant_signal(39),
+--   grant(40) => grant_signal(40),
+--   grant(41) => grant_signal(41),
+--   grant(42) => grant_signal(42),
+--   grant(43) => grant_signal(43),
+--   grant(44) => grant_signal(44),
+--   grant(45) => grant_signal(45),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(31) =>request_signal(31),
+--   request(32) =>request_signal(32),
+--   request(33) =>request_signal(33),
+--   request(34) =>request_signal(34),
+--   request(35) =>request_signal(35),
+--   request(36) =>request_signal(36),
+--   request(37) =>request_signal(37),
+--   request(38) =>request_signal(38),
+--   request(39) =>request_signal(39),
+--   request(40) =>request_signal(40),
+--   request(41) =>request_signal(41),
+--   request(42) =>request_signal(42),
+--   request(43) =>request_signal(43),
+--   request(44) =>request_signal(44),
+--   request(45) =>request_signal(45)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(46) => grant_signal(46),
+--   grant(47) => grant_signal(47),
+--   grant(48) => grant_signal(48),
+--   grant(49) => grant_signal(49),
+--   grant(50) => grant_signal(50),
+--   grant(51) => grant_signal(51),
+--   grant(52) => grant_signal(52),
+--   grant(53) => grant_signal(53),
+--   grant(54) => grant_signal(54),
+--   grant(55) => grant_signal(55),
+--   grant(56) => grant_signal(56),
+--   grant(57) => grant_signal(57),
+--   grant(58) => grant_signal(58),
+--   grant(59) => grant_signal(59),
+--   grant(60) => grant_signal(60),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(46) =>request_signal(46),
+--   request(47) =>request_signal(47),
+--   request(48) =>request_signal(48),
+--   request(49) =>request_signal(49),
+--   request(50) =>request_signal(50),
+--   request(51) =>request_signal(51),
+--   request(52) =>request_signal(52),
+--   request(53) =>request_signal(53),
+--   request(54) =>request_signal(54),
+--   request(55) =>request_signal(55),
+--   request(56) =>request_signal(56),
+--   request(57) =>request_signal(57),
+--   request(58) =>request_signal(58),
+--   request(59) =>request_signal(59),
+--   request(60) =>request_signal(60)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(61) => grant_signal(61),
+--   grant(62) => grant_signal(62),
+--   grant(63) => grant_signal(63),
+--   grant(64) => grant_signal(64),
+--   grant(65) => grant_signal(65),
+--   grant(66) => grant_signal(66),
+--   grant(67) => grant_signal(67),
+--   grant(68) => grant_signal(68),
+--   grant(69) => grant_signal(69),
+--   grant(70) => grant_signal(70),
+--   grant(71) => grant_signal(71),
+--   grant(72) => grant_signal(72),
+--   grant(73) => grant_signal(73),
+--   grant(74) => grant_signal(74),
+--   grant(75) => grant_signal(75),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(61) =>request_signal(61),
+--   request(62) =>request_signal(62),
+--   request(63) =>request_signal(63),
+--   request(64) =>request_signal(64),
+--   request(65) =>request_signal(65),
+--   request(66) =>request_signal(66),
+--   request(67) =>request_signal(67),
+--   request(68) =>request_signal(68),
+--   request(69) =>request_signal(69),
+--   request(70) =>request_signal(70),
+--   request(71) =>request_signal(71),
+--   request(72) =>request_signal(72),
+--   request(73) =>request_signal(73),
+--   request(74) =>request_signal(74),
+--   request(75) =>request_signal(75)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(76) => grant_signal(76),
+--   grant(77) => grant_signal(77),
+--   grant(78) => grant_signal(78),
+--   grant(79) => grant_signal(79),
+--   grant(80) => grant_signal(80),
+--   grant(81) => grant_signal(81),
+--   grant(82) => grant_signal(82),
+--   grant(83) => grant_signal(83),
+--   grant(84) => grant_signal(84),
+--   grant(85) => grant_signal(85),
+--   grant(86) => grant_signal(86),
+--   grant(87) => grant_signal(87),
+--   grant(88) => grant_signal(88),
+--   grant(89) => grant_signal(89),
+--   grant(90) => grant_signal(90),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(76) =>request_signal(76),
+--   request(77) =>request_signal(77),
+--   request(78) =>request_signal(78),
+--   request(79) =>request_signal(79),
+--   request(80) =>request_signal(80),
+--   request(81) =>request_signal(81),
+--   request(82) =>request_signal(82),
+--   request(83) =>request_signal(83),
+--   request(84) =>request_signal(84),
+--   request(85) =>request_signal(85),
+--   request(86) =>request_signal(86),
+--   request(87) =>request_signal(87),
+--   request(88) =>request_signal(88),
+--   request(89) =>request_signal(89),
+--   request(90) =>request_signal(90)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(91) => grant_signal(91),
+--   grant(92) => grant_signal(92),
+--   grant(93) => grant_signal(93),
+--   grant(94) => grant_signal(94),
+--   grant(95) => grant_signal(95),
+--   grant(96) => grant_signal(96),
+--   grant(97) => grant_signal(97),
+--   grant(98) => grant_signal(98),
+--   grant(99) => grant_signal(99),
+--   grant(100) => grant_signal(100),
+--   grant(101) => grant_signal(101),
+--   grant(102) => grant_signal(102),
+--   grant(103) => grant_signal(103),
+--   grant(104) => grant_signal(104),
+--   grant(105) => grant_signal(105),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(7),
+--   data_out_pulse =>crossbar_in_pulse(7),
+--   request(91) =>request_signal(91),
+--   request(92) =>request_signal(92),
+--   request(93) =>request_signal(93),
+--   request(94) =>request_signal(94),
+--   request(95) =>request_signal(95),
+--   request(96) =>request_signal(96),
+--   request(97) =>request_signal(97),
+--   request(98) =>request_signal(98),
+--   request(99) =>request_signal(99),
+--   request(100) =>request_signal(100),
+--   request(101) =>request_signal(101),
+--   request(102) =>request_signal(102),
+--   request(103) =>request_signal(103),
+--   request(104) =>request_signal(104),
+--   request(105) =>request_signal(105)
+--);
+--
+--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(8),
+--   data_in_en => data_in_en(8),
+--   reset => reset,
+--   clk =>clk,
+--   grant(106) => grant_signal(106),
+--   grant(107) => grant_signal(107),
+--   grant(108) => grant_signal(108),
+--   grant(109) => grant_signal(109),
+--   grant(110) => grant_signal(110),
+--   grant(111) => grant_signal(111),
+--   grant(112) => grant_signal(112),
+--   grant(113) => grant_signal(113),
+--   grant(114) => grant_signal(114),
+--   grant(115) => grant_signal(115),
+--   grant(116) => grant_signal(116),
+--   grant(117) => grant_signal(117),
+--   grant(118) => grant_signal(118),
+--   grant(119) => grant_signal(119),
+--   grant(120) => grant_signal(120),
+--   fifo_full =>fifo_in_full(8),
+--   priority_rotation =>  priority_rotation_signal(8),
+--   fifo_empty => fifo_in_empty(8),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(8),
+--   request(106) =>request_signal(106),
+--   request(107) =>request_signal(107),
+--   request(108) =>request_signal(108),
+--   request(109) =>request_signal(109),
+--   request(110) =>request_signal(110),
+--   request(111) =>request_signal(111),
+--   request(112) =>request_signal(112),
+--   request(113) =>request_signal(113),
+--   request(114) =>request_signal(114),
+--   request(115) =>request_signal(115),
+--   request(116) =>request_signal(116),
+--   request(117) =>request_signal(117),
+--   request(118) =>request_signal(118),
+--   request(119) =>request_signal(119),
+--   request(120) =>request_signal(120)
+--);
+--
+--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(9),
+--   data_in_en => data_in_en(9),
+--   reset => reset,
+--   clk =>clk,
+--   grant(121) => grant_signal(121),
+--   grant(122) => grant_signal(122),
+--   grant(123) => grant_signal(123),
+--   grant(124) => grant_signal(124),
+--   grant(125) => grant_signal(125),
+--   grant(126) => grant_signal(126),
+--   grant(127) => grant_signal(127),
+--   grant(128) => grant_signal(128),
+--   grant(129) => grant_signal(129),
+--   grant(130) => grant_signal(130),
+--   grant(131) => grant_signal(131),
+--   grant(132) => grant_signal(132),
+--   grant(133) => grant_signal(133),
+--   grant(134) => grant_signal(134),
+--   grant(135) => grant_signal(135),
+--   fifo_full =>fifo_in_full(9),
+--   priority_rotation =>  priority_rotation_signal(9),
+--   fifo_empty => fifo_in_empty(9),
+--   data_out =>crossbar_in_port(9),
+--   data_out_pulse =>crossbar_in_pulse(9),
+--   request(121) =>request_signal(121),
+--   request(122) =>request_signal(122),
+--   request(123) =>request_signal(123),
+--   request(124) =>request_signal(124),
+--   request(125) =>request_signal(125),
+--   request(126) =>request_signal(126),
+--   request(127) =>request_signal(127),
+--   request(128) =>request_signal(128),
+--   request(129) =>request_signal(129),
+--   request(130) =>request_signal(130),
+--   request(131) =>request_signal(131),
+--   request(132) =>request_signal(132),
+--   request(133) =>request_signal(133),
+--   request(134) =>request_signal(134),
+--   request(135) =>request_signal(135)
+--);
+--
+--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(10),
+--   data_in_en => data_in_en(10),
+--   reset => reset,
+--   clk =>clk,
+--   grant(136) => grant_signal(136),
+--   grant(137) => grant_signal(137),
+--   grant(138) => grant_signal(138),
+--   grant(139) => grant_signal(139),
+--   grant(140) => grant_signal(140),
+--   grant(141) => grant_signal(141),
+--   grant(142) => grant_signal(142),
+--   grant(143) => grant_signal(143),
+--   grant(144) => grant_signal(144),
+--   grant(145) => grant_signal(145),
+--   grant(146) => grant_signal(146),
+--   grant(147) => grant_signal(147),
+--   grant(148) => grant_signal(148),
+--   grant(149) => grant_signal(149),
+--   grant(150) => grant_signal(150),
+--   fifo_full =>fifo_in_full(10),
+--   priority_rotation =>  priority_rotation_signal(10),
+--   fifo_empty => fifo_in_empty(10),
+--   data_out =>crossbar_in_port(10),
+--   data_out_pulse =>crossbar_in_pulse(10),
+--   request(136) =>request_signal(136),
+--   request(137) =>request_signal(137),
+--   request(138) =>request_signal(138),
+--   request(139) =>request_signal(139),
+--   request(140) =>request_signal(140),
+--   request(141) =>request_signal(141),
+--   request(142) =>request_signal(142),
+--   request(143) =>request_signal(143),
+--   request(144) =>request_signal(144),
+--   request(145) =>request_signal(145),
+--   request(146) =>request_signal(146),
+--   request(147) =>request_signal(147),
+--   request(148) =>request_signal(148),
+--   request(149) =>request_signal(149),
+--   request(150) =>request_signal(150)
+--);
+--
+--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(11),
+--   data_in_en => data_in_en(11),
+--   reset => reset,
+--   clk =>clk,
+--   grant(151) => grant_signal(151),
+--   grant(152) => grant_signal(152),
+--   grant(153) => grant_signal(153),
+--   grant(154) => grant_signal(154),
+--   grant(155) => grant_signal(155),
+--   grant(156) => grant_signal(156),
+--   grant(157) => grant_signal(157),
+--   grant(158) => grant_signal(158),
+--   grant(159) => grant_signal(159),
+--   grant(160) => grant_signal(160),
+--   grant(161) => grant_signal(161),
+--   grant(162) => grant_signal(162),
+--   grant(163) => grant_signal(163),
+--   grant(164) => grant_signal(164),
+--   grant(165) => grant_signal(165),
+--   fifo_full =>fifo_in_full(11),
+--   priority_rotation =>  priority_rotation_signal(11),
+--   fifo_empty => fifo_in_empty(11),
+--   data_out =>crossbar_in_port(11),
+--   data_out_pulse =>crossbar_in_pulse(11),
+--   request(151) =>request_signal(151),
+--   request(152) =>request_signal(152),
+--   request(153) =>request_signal(153),
+--   request(154) =>request_signal(154),
+--   request(155) =>request_signal(155),
+--   request(156) =>request_signal(156),
+--   request(157) =>request_signal(157),
+--   request(158) =>request_signal(158),
+--   request(159) =>request_signal(159),
+--   request(160) =>request_signal(160),
+--   request(161) =>request_signal(161),
+--   request(162) =>request_signal(162),
+--   request(163) =>request_signal(163),
+--   request(164) =>request_signal(164),
+--   request(165) =>request_signal(165)
+--);
+--
+--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(12),
+--   data_in_en => data_in_en(12),
+--   reset => reset,
+--   clk =>clk,
+--   grant(166) => grant_signal(166),
+--   grant(167) => grant_signal(167),
+--   grant(168) => grant_signal(168),
+--   grant(169) => grant_signal(169),
+--   grant(170) => grant_signal(170),
+--   grant(171) => grant_signal(171),
+--   grant(172) => grant_signal(172),
+--   grant(173) => grant_signal(173),
+--   grant(174) => grant_signal(174),
+--   grant(175) => grant_signal(175),
+--   grant(176) => grant_signal(176),
+--   grant(177) => grant_signal(177),
+--   grant(178) => grant_signal(178),
+--   grant(179) => grant_signal(179),
+--   grant(180) => grant_signal(180),
+--   fifo_full =>fifo_in_full(12),
+--   priority_rotation =>  priority_rotation_signal(12),
+--   fifo_empty => fifo_in_empty(12),
+--   data_out =>crossbar_in_port(12),
+--   data_out_pulse =>crossbar_in_pulse(12),
+--   request(166) =>request_signal(166),
+--   request(167) =>request_signal(167),
+--   request(168) =>request_signal(168),
+--   request(169) =>request_signal(169),
+--   request(170) =>request_signal(170),
+--   request(171) =>request_signal(171),
+--   request(172) =>request_signal(172),
+--   request(173) =>request_signal(173),
+--   request(174) =>request_signal(174),
+--   request(175) =>request_signal(175),
+--   request(176) =>request_signal(176),
+--   request(177) =>request_signal(177),
+--   request(178) =>request_signal(178),
+--   request(179) =>request_signal(179),
+--   request(180) =>request_signal(180)
+--);
+--
+--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(13),
+--   data_in_en => data_in_en(13),
+--   reset => reset,
+--   clk =>clk,
+--   grant(181) => grant_signal(181),
+--   grant(182) => grant_signal(182),
+--   grant(183) => grant_signal(183),
+--   grant(184) => grant_signal(184),
+--   grant(185) => grant_signal(185),
+--   grant(186) => grant_signal(186),
+--   grant(187) => grant_signal(187),
+--   grant(188) => grant_signal(188),
+--   grant(189) => grant_signal(189),
+--   grant(190) => grant_signal(190),
+--   grant(191) => grant_signal(191),
+--   grant(192) => grant_signal(192),
+--   grant(193) => grant_signal(193),
+--   grant(194) => grant_signal(194),
+--   grant(195) => grant_signal(195),
+--   fifo_full =>fifo_in_full(13),
+--   priority_rotation =>  priority_rotation_signal(13),
+--   fifo_empty => fifo_in_empty(13),
+--   data_out =>crossbar_in_port(13),
+--   data_out_pulse =>crossbar_in_pulse(13),
+--   request(181) =>request_signal(181),
+--   request(182) =>request_signal(182),
+--   request(183) =>request_signal(183),
+--   request(184) =>request_signal(184),
+--   request(185) =>request_signal(185),
+--   request(186) =>request_signal(186),
+--   request(187) =>request_signal(187),
+--   request(188) =>request_signal(188),
+--   request(189) =>request_signal(189),
+--   request(190) =>request_signal(190),
+--   request(191) =>request_signal(191),
+--   request(192) =>request_signal(192),
+--   request(193) =>request_signal(193),
+--   request(194) =>request_signal(194),
+--   request(195) =>request_signal(195)
+--);
+--
+--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(14),
+--   data_in_en => data_in_en(14),
+--   reset => reset,
+--   clk =>clk,
+--   grant(196) => grant_signal(196),
+--   grant(197) => grant_signal(197),
+--   grant(198) => grant_signal(198),
+--   grant(199) => grant_signal(199),
+--   grant(200) => grant_signal(200),
+--   grant(201) => grant_signal(201),
+--   grant(202) => grant_signal(202),
+--   grant(203) => grant_signal(203),
+--   grant(204) => grant_signal(204),
+--   grant(205) => grant_signal(205),
+--   grant(206) => grant_signal(206),
+--   grant(207) => grant_signal(207),
+--   grant(208) => grant_signal(208),
+--   grant(209) => grant_signal(209),
+--   grant(210) => grant_signal(210),
+--   fifo_full =>fifo_in_full(14),
+--   priority_rotation =>  priority_rotation_signal(14),
+--   fifo_empty => fifo_in_empty(14),
+--   data_out =>crossbar_in_port(14),
+--   data_out_pulse =>crossbar_in_pulse(14),
+--   request(196) =>request_signal(196),
+--   request(197) =>request_signal(197),
+--   request(198) =>request_signal(198),
+--   request(199) =>request_signal(199),
+--   request(200) =>request_signal(200),
+--   request(201) =>request_signal(201),
+--   request(202) =>request_signal(202),
+--   request(203) =>request_signal(203),
+--   request(204) =>request_signal(204),
+--   request(205) =>request_signal(205),
+--   request(206) =>request_signal(206),
+--   request(207) =>request_signal(207),
+--   request(208) =>request_signal(208),
+--   request(209) =>request_signal(209),
+--   request(210) =>request_signal(210)
+--);
+--
+--PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(15),
+--   data_in_en => data_in_en(15),
+--   reset => reset,
+--   clk =>clk,
+--   grant(211) => grant_signal(211),
+--   grant(212) => grant_signal(212),
+--   grant(213) => grant_signal(213),
+--   grant(214) => grant_signal(214),
+--   grant(215) => grant_signal(215),
+--   grant(216) => grant_signal(216),
+--   grant(217) => grant_signal(217),
+--   grant(218) => grant_signal(218),
+--   grant(219) => grant_signal(219),
+--   grant(220) => grant_signal(220),
+--   grant(221) => grant_signal(221),
+--   grant(222) => grant_signal(222),
+--   grant(223) => grant_signal(223),
+--   grant(224) => grant_signal(224),
+--   grant(225) => grant_signal(225),
+--   fifo_full =>fifo_in_full(15),
+--   priority_rotation =>  priority_rotation_signal(15),
+--   fifo_empty => fifo_in_empty(15),
+--   data_out =>crossbar_in_port(15),
+--   data_out_pulse =>crossbar_in_pulse(15),
+--   request(211) =>request_signal(211),
+--   request(212) =>request_signal(212),
+--   request(213) =>request_signal(213),
+--   request(214) =>request_signal(214),
+--   request(215) =>request_signal(215),
+--   request(216) =>request_signal(216),
+--   request(217) =>request_signal(217),
+--   request(218) =>request_signal(218),
+--   request(219) =>request_signal(219),
+--   request(220) =>request_signal(220),
+--   request(221) =>request_signal(221),
+--   request(222) =>request_signal(222),
+--   request(223) =>request_signal(223),
+--   request(224) =>request_signal(224),
+--   request(225) =>request_signal(225)
+--);
+--
+--end generate switch15x15;
+
+
+-- switch 16 ports
+switch16x16 : if number_of_ports = 16 generate
+switch_16x16 :for i in 1 to number_of_ports generate
+Constant j : natural:=number_of_ports*(i-1);
+begin
+--j<=number_of_ports*(i-1);
+PORTx16_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16,port_num=>i)
+PORT MAP(
+   data_in => Port_in(i),
+   data_in_en => data_in_en(i),
+	cmd_in_en => cmd_in_en(i),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(j+1),
+   grant(2) => grant_signal(j+2),
+   grant(3) => grant_signal(j+3),
+   grant(4) => grant_signal(j+4),
+   grant(5) => grant_signal(j+5),
+   grant(6) => grant_signal(j+6),
+   grant(7) => grant_signal(j+7),
+   grant(8) => grant_signal(j+8),
+   grant(9) => grant_signal(j+9),
+   grant(10) => grant_signal(j+10),
+   grant(11) => grant_signal(j+11),
+   grant(12) => grant_signal(j+12),
+   grant(13) => grant_signal(j+13),
+   grant(14) => grant_signal(j+14),
+   grant(15) => grant_signal(j+15),
+   grant(16) => grant_signal(j+16),
+   fifo_full =>fifo_in_full(i),
+   priority_rotation => priority_rotation_signal(i),
+   fifo_empty => fifo_in_empty(i),
+   data_out =>crossbar_in_port(i),
+   data_out_pulse =>crossbar_in_pulse(i),
+   request(1) =>request_signal(j+1),
+   request(2) =>request_signal(j+2),
+   request(3) =>request_signal(j+3),
+   request(4) =>request_signal(j+4),
+   request(5) =>request_signal(j+5),
+   request(6) =>request_signal(j+6),
+   request(7) =>request_signal(j+7),
+   request(8) =>request_signal(j+8),
+   request(9) =>request_signal(j+9),
+   request(10) =>request_signal(j+10),
+   request(11) =>request_signal(j+11),
+   request(12) =>request_signal(j+12),
+   request(13) =>request_signal(j+13),
+   request(14) =>request_signal(j+14),
+   request(15) =>request_signal(j+15),
+   request(16) =>request_signal(j+16)
+);
+end generate switch_16x16;
+end generate switch16x16;
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(17) => grant_signal(17),
+--   grant(18) => grant_signal(18),
+--   grant(19) => grant_signal(19),
+--   grant(20) => grant_signal(20),
+--   grant(21) => grant_signal(21),
+--   grant(22) => grant_signal(22),
+--   grant(23) => grant_signal(23),
+--   grant(24) => grant_signal(24),
+--   grant(25) => grant_signal(25),
+--   grant(26) => grant_signal(26),
+--   grant(27) => grant_signal(27),
+--   grant(28) => grant_signal(28),
+--   grant(29) => grant_signal(29),
+--   grant(30) => grant_signal(30),
+--   grant(31) => grant_signal(31),
+--   grant(32) => grant_signal(32),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port2,
+--   data_out_pulse =>crossbar_in_pulse(2,
+--   request(17) =>request_signal(17),
+--   request(18) =>request_signal(18),
+--   request(19) =>request_signal(19),
+--   request(20) =>request_signal(20),
+--   request(21) =>request_signal(21),
+--   request(22) =>request_signal(22),
+--   request(23) =>request_signal(23),
+--   request(24) =>request_signal(24),
+--   request(25) =>request_signal(25),
+--   request(26) =>request_signal(26),
+--   request(27) =>request_signal(27),
+--   request(28) =>request_signal(28),
+--   request(29) =>request_signal(29),
+--   request(30) =>request_signal(30),
+--   request(31) =>request_signal(31),
+--   request(32) =>request_signal(32)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(33) => grant_signal(33),
+--   grant(34) => grant_signal(34),
+--   grant(35) => grant_signal(35),
+--   grant(36) => grant_signal(36),
+--   grant(37) => grant_signal(37),
+--   grant(38) => grant_signal(38),
+--   grant(39) => grant_signal(39),
+--   grant(40) => grant_signal(40),
+--   grant(41) => grant_signal(41),
+--   grant(42) => grant_signal(42),
+--   grant(43) => grant_signal(43),
+--   grant(44) => grant_signal(44),
+--   grant(45) => grant_signal(45),
+--   grant(46) => grant_signal(46),
+--   grant(47) => grant_signal(47),
+--   grant(48) => grant_signal(48),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port3,
+--   data_out_pulse =>crossbar_in_pulse(3,
+--   request(33) =>request_signal(33),
+--   request(34) =>request_signal(34),
+--   request(35) =>request_signal(35),
+--   request(36) =>request_signal(36),
+--   request(37) =>request_signal(37),
+--   request(38) =>request_signal(38),
+--   request(39) =>request_signal(39),
+--   request(40) =>request_signal(40),
+--   request(41) =>request_signal(41),
+--   request(42) =>request_signal(42),
+--   request(43) =>request_signal(43),
+--   request(44) =>request_signal(44),
+--   request(45) =>request_signal(45),
+--   request(46) =>request_signal(46),
+--   request(47) =>request_signal(47),
+--   request(48) =>request_signal(48)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(49) => grant_signal(49),
+--   grant(50) => grant_signal(50),
+--   grant(51) => grant_signal(51),
+--   grant(52) => grant_signal(52),
+--   grant(53) => grant_signal(53),
+--   grant(54) => grant_signal(54),
+--   grant(55) => grant_signal(55),
+--   grant(56) => grant_signal(56),
+--   grant(57) => grant_signal(57),
+--   grant(58) => grant_signal(58),
+--   grant(59) => grant_signal(59),
+--   grant(60) => grant_signal(60),
+--   grant(61) => grant_signal(61),
+--   grant(62) => grant_signal(62),
+--   grant(63) => grant_signal(63),
+--   grant(64) => grant_signal(64),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4,
+--   request(49) =>request_signal(49),
+--   request(50) =>request_signal(50),
+--   request(51) =>request_signal(51),
+--   request(52) =>request_signal(52),
+--   request(53) =>request_signal(53),
+--   request(54) =>request_signal(54),
+--   request(55) =>request_signal(55),
+--   request(56) =>request_signal(56),
+--   request(57) =>request_signal(57),
+--   request(58) =>request_signal(58),
+--   request(59) =>request_signal(59),
+--   request(60) =>request_signal(60),
+--   request(61) =>request_signal(61),
+--   request(62) =>request_signal(62),
+--   request(63) =>request_signal(63),
+--   request(64) =>request_signal(64)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(65) => grant_signal(65),
+--   grant(66) => grant_signal(66),
+--   grant(67) => grant_signal(67),
+--   grant(68) => grant_signal(68),
+--   grant(69) => grant_signal(69),
+--   grant(70) => grant_signal(70),
+--   grant(71) => grant_signal(71),
+--   grant(72) => grant_signal(72),
+--   grant(73) => grant_signal(73),
+--   grant(74) => grant_signal(74),
+--   grant(75) => grant_signal(75),
+--   grant(76) => grant_signal(76),
+--   grant(77) => grant_signal(77),
+--   grant(78) => grant_signal(78),
+--   grant(79) => grant_signal(79),
+--   grant(80) => grant_signal(80),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5,
+--   request(65) =>request_signal(65),
+--   request(66) =>request_signal(66),
+--   request(67) =>request_signal(67),
+--   request(68) =>request_signal(68),
+--   request(69) =>request_signal(69),
+--   request(70) =>request_signal(70),
+--   request(71) =>request_signal(71),
+--   request(72) =>request_signal(72),
+--   request(73) =>request_signal(73),
+--   request(74) =>request_signal(74),
+--   request(75) =>request_signal(75),
+--   request(76) =>request_signal(76),
+--   request(77) =>request_signal(77),
+--   request(78) =>request_signal(78),
+--   request(79) =>request_signal(79),
+--   request(80) =>request_signal(80)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(81) => grant_signal(81),
+--   grant(82) => grant_signal(82),
+--   grant(83) => grant_signal(83),
+--   grant(84) => grant_signal(84),
+--   grant(85) => grant_signal(85),
+--   grant(86) => grant_signal(86),
+--   grant(87) => grant_signal(87),
+--   grant(88) => grant_signal(88),
+--   grant(89) => grant_signal(89),
+--   grant(90) => grant_signal(90),
+--   grant(91) => grant_signal(91),
+--   grant(92) => grant_signal(92),
+--   grant(93) => grant_signal(93),
+--   grant(94) => grant_signal(94),
+--   grant(95) => grant_signal(95),
+--   grant(96) => grant_signal(96),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6,
+--   request(81) =>request_signal(81),
+--   request(82) =>request_signal(82),
+--   request(83) =>request_signal(83),
+--   request(84) =>request_signal(84),
+--   request(85) =>request_signal(85),
+--   request(86) =>request_signal(86),
+--   request(87) =>request_signal(87),
+--   request(88) =>request_signal(88),
+--   request(89) =>request_signal(89),
+--   request(90) =>request_signal(90),
+--   request(91) =>request_signal(91),
+--   request(92) =>request_signal(92),
+--   request(93) =>request_signal(93),
+--   request(94) =>request_signal(94),
+--   request(95) =>request_signal(95),
+--   request(96) =>request_signal(96)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(97) => grant_signal(97),
+--   grant(98) => grant_signal(98),
+--   grant(99) => grant_signal(99),
+--   grant(0) => grant_signal(100),
+--   grant(1) => grant_signal(101),
+--   grant(2) => grant_signal(102),
+--   grant(3) => grant_signal(103),
+--   grant(4) => grant_signal(104),
+--   grant(5) => grant_signal(105),
+--   grant(6) => grant_signal(106),
+--   grant(7) => grant_signal(107),
+--   grant(8) => grant_signal(108),
+--   grant(9) => grant_signal(109),
+--   grant(110) => grant_signal(110),
+--   grant(111) => grant_signal(111),
+--   grant(112) => grant_signal(112),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(7,
+--   request(97) =>request_signal(97),
+--   request(98) =>request_signal(98),
+--   request(99) =>request_signal(99),
+--   request(100) =>request_signal(100),
+--   request(101) =>request_signal(101),
+--   request(102) =>request_signal(102),
+--   request(103) =>request_signal(103),
+--   request(104) =>request_signal(104),
+--   request(105) =>request_signal(105),
+--   request(106) =>request_signal(106),
+--   request(107) =>request_signal(107),
+--   request(108) =>request_signal(108),
+--   request(109) =>request_signal(109),
+--   request(110) =>request_signal(110),
+--   request(111) =>request_signal(111),
+--   request(112) =>request_signal(112)
+--);
+--
+--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(8),
+--   data_in_en => data_in_en(8),
+--   reset => reset,
+--   clk =>clk,
+--   grant(113) => grant_signal(113),
+--   grant(114) => grant_signal(114),
+--   grant(115) => grant_signal(115),
+--   grant(116) => grant_signal(116),
+--   grant(117) => grant_signal(117),
+--   grant(118) => grant_signal(118),
+--   grant(119) => grant_signal(119),
+--   grant(120) => grant_signal(120),
+--   grant(121) => grant_signal(121),
+--   grant(122) => grant_signal(122),
+--   grant(123) => grant_signal(123),
+--   grant(124) => grant_signal(124),
+--   grant(125) => grant_signal(125),
+--   grant(126) => grant_signal(126),
+--   grant(127) => grant_signal(127),
+--   grant(128) => grant_signal(128),
+--   fifo_full =>fifo_in_full(8),
+--   priority_rotation =>  priority_rotation_signal(8),
+--   fifo_empty => fifo_in_empty(8),
+--   data_out =>crossbar_in_port8,
+--   data_out_pulse =>crossbar_in_pulse(8,
+--   request(113) =>request_signal(113),
+--   request(114) =>request_signal(114),
+--   request(115) =>request_signal(115),
+--   request(116) =>request_signal(116),
+--   request(117) =>request_signal(117),
+--   request(118) =>request_signal(118),
+--   request(119) =>request_signal(119),
+--   request(120) =>request_signal(120),
+--   request(121) =>request_signal(121),
+--   request(122) =>request_signal(122),
+--   request(123) =>request_signal(123),
+--   request(124) =>request_signal(124),
+--   request(125) =>request_signal(125),
+--   request(126) =>request_signal(126),
+--   request(127) =>request_signal(127),
+--   request(128) =>request_signal(128)
+--);
+--
+--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(9),
+--   data_in_en => data_in_en(9),
+--   reset => reset,
+--   clk =>clk,
+--   grant(129) => grant_signal(129),
+--   grant(130) => grant_signal(130),
+--   grant(131) => grant_signal(131),
+--   grant(132) => grant_signal(132),
+--   grant(133) => grant_signal(133),
+--   grant(134) => grant_signal(134),
+--   grant(135) => grant_signal(135),
+--   grant(136) => grant_signal(136),
+--   grant(137) => grant_signal(137),
+--   grant(138) => grant_signal(138),
+--   grant(139) => grant_signal(139),
+--   grant(140) => grant_signal(140),
+--   grant(141) => grant_signal(141),
+--   grant(142) => grant_signal(142),
+--   grant(143) => grant_signal(143),
+--   grant(144) => grant_signal(144),
+--   fifo_full =>fifo_in_full(9),
+--   priority_rotation =>  priority_rotation_signal(9),
+--   fifo_empty => fifo_in_empty(9),
+--   data_out =>crossbar_in_port9,
+--   data_out_pulse =>crossbar_in_pulse(9),
+--   request(129) =>request_signal(129),
+--   request(130) =>request_signal(130),
+--   request(131) =>request_signal(131),
+--   request(132) =>request_signal(132),
+--   request(133) =>request_signal(133),
+--   request(134) =>request_signal(134),
+--   request(135) =>request_signal(135),
+--   request(136) =>request_signal(136),
+--   request(137) =>request_signal(137),
+--   request(138) =>request_signal(138),
+--   request(139) =>request_signal(139),
+--   request(140) =>request_signal(140),
+--   request(141) =>request_signal(141),
+--   request(142) =>request_signal(142),
+--   request(143) =>request_signal(143),
+--   request(144) =>request_signal(144)
+--);
+--
+--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(10),
+--   data_in_en => data_in_en(10),
+--   reset => reset,
+--   clk =>clk,
+--   grant(145) => grant_signal(145),
+--   grant(146) => grant_signal(146),
+--   grant(147) => grant_signal(147),
+--   grant(148) => grant_signal(148),
+--   grant(149) => grant_signal(149),
+--   grant(150) => grant_signal(150),
+--   grant(151) => grant_signal(151),
+--   grant(152) => grant_signal(152),
+--   grant(153) => grant_signal(153),
+--   grant(154) => grant_signal(154),
+--   grant(155) => grant_signal(155),
+--   grant(156) => grant_signal(156),
+--   grant(157) => grant_signal(157),
+--   grant(158) => grant_signal(158),
+--   grant(159) => grant_signal(159),
+--   grant(160) => grant_signal(160),
+--   fifo_full =>fifo_in_full(10),
+--   priority_rotation =>  priority_rotation_signal(10),
+--   fifo_empty => fifo_in_empty(10),
+--   data_out =>crossbar_in_port(10),
+--   data_out_pulse =>crossbar_in_pulse(10),
+--   request(145) =>request_signal(145),
+--   request(146) =>request_signal(146),
+--   request(147) =>request_signal(147),
+--   request(148) =>request_signal(148),
+--   request(149) =>request_signal(149),
+--   request(150) =>request_signal(150),
+--   request(151) =>request_signal(151),
+--   request(152) =>request_signal(152),
+--   request(153) =>request_signal(153),
+--   request(154) =>request_signal(154),
+--   request(155) =>request_signal(155),
+--   request(156) =>request_signal(156),
+--   request(157) =>request_signal(157),
+--   request(158) =>request_signal(158),
+--   request(159) =>request_signal(159),
+--   request(160) =>request_signal(160)
+--);
+--
+--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(11),
+--   data_in_en => data_in_en(11),
+--   reset => reset,
+--   clk =>clk,
+--   grant(161) => grant_signal(161),
+--   grant(162) => grant_signal(162),
+--   grant(163) => grant_signal(163),
+--   grant(164) => grant_signal(164),
+--   grant(165) => grant_signal(165),
+--   grant(166) => grant_signal(166),
+--   grant(167) => grant_signal(167),
+--   grant(168) => grant_signal(168),
+--   grant(169) => grant_signal(169),
+--   grant(170) => grant_signal(170),
+--   grant(171) => grant_signal(171),
+--   grant(172) => grant_signal(172),
+--   grant(173) => grant_signal(173),
+--   grant(174) => grant_signal(174),
+--   grant(175) => grant_signal(175),
+--   grant(176) => grant_signal(176),
+--   fifo_full =>fifo_in_full(11),
+--   priority_rotation =>  priority_rotation_signal(11),
+--   fifo_empty => fifo_in_empty(11),
+--   data_out =>crossbar_in_port(11),
+--   data_out_pulse =>crossbar_in_pulse(11),
+--   request(161) =>request_signal(161),
+--   request(162) =>request_signal(162),
+--   request(163) =>request_signal(163),
+--   request(164) =>request_signal(164),
+--   request(165) =>request_signal(165),
+--   request(166) =>request_signal(166),
+--   request(167) =>request_signal(167),
+--   request(168) =>request_signal(168),
+--   request(169) =>request_signal(169),
+--   request(170) =>request_signal(170),
+--   request(171) =>request_signal(171),
+--   request(172) =>request_signal(172),
+--   request(173) =>request_signal(173),
+--   request(174) =>request_signal(174),
+--   request(175) =>request_signal(175),
+--   request(176) =>request_signal(176)
+--);
+--
+--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(12),
+--   data_in_en => data_in_en(12),
+--   reset => reset,
+--   clk =>clk,
+--   grant(177) => grant_signal(177),
+--   grant(178) => grant_signal(178),
+--   grant(179) => grant_signal(179),
+--   grant(180) => grant_signal(180),
+--   grant(181) => grant_signal(181),
+--   grant(182) => grant_signal(182),
+--   grant(183) => grant_signal(183),
+--   grant(184) => grant_signal(184),
+--   grant(185) => grant_signal(185),
+--   grant(186) => grant_signal(186),
+--   grant(187) => grant_signal(187),
+--   grant(188) => grant_signal(188),
+--   grant(189) => grant_signal(189),
+--   grant(190) => grant_signal(190),
+--   grant(191) => grant_signal(191),
+--   grant(192) => grant_signal(192),
+--   fifo_full =>fifo_in_full(12),
+--   priority_rotation =>  priority_rotation_signal(12),
+--   fifo_empty => fifo_in_empty(12),
+--   data_out =>crossbar_in_port(12),
+--   data_out_pulse =>crossbar_in_pulse(12),
+--   request(177) =>request_signal(177),
+--   request(178) =>request_signal(178),
+--   request(179) =>request_signal(179),
+--   request(180) =>request_signal(180),
+--   request(181) =>request_signal(181),
+--   request(182) =>request_signal(182),
+--   request(183) =>request_signal(183),
+--   request(184) =>request_signal(184),
+--   request(185) =>request_signal(185),
+--   request(186) =>request_signal(186),
+--   request(187) =>request_signal(187),
+--   request(188) =>request_signal(188),
+--   request(189) =>request_signal(189),
+--   request(190) =>request_signal(190),
+--   request(191) =>request_signal(191),
+--   request(192) =>request_signal(192)
+--);
+--
+--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(13),
+--   data_in_en => data_in_en(13),
+--   reset => reset,
+--   clk =>clk,
+--   grant(193) => grant_signal(193),
+--   grant(194) => grant_signal(194),
+--   grant(195) => grant_signal(195),
+--   grant(196) => grant_signal(196),
+--   grant(197) => grant_signal(197),
+--   grant(198) => grant_signal(198),
+--   grant(199) => grant_signal(199),
+--   grant(200) => grant_signal(200),
+--   grant(201) => grant_signal(201),
+--   grant(202) => grant_signal(202),
+--   grant(203) => grant_signal(203),
+--   grant(204) => grant_signal(204),
+--   grant(205) => grant_signal(205),
+--   grant(206) => grant_signal(206),
+--   grant(207) => grant_signal(207),
+--   grant(208) => grant_signal(208),
+--   fifo_full =>fifo_in_full(13),
+--   priority_rotation =>  priority_rotation_signal(13),
+--   fifo_empty => fifo_in_empty(13),
+--   data_out =>crossbar_in_port13,
+--   data_out_pulse =>crossbar_in_pulse(13,
+--   request(193) =>request_signal(193),
+--   request(194) =>request_signal(194),
+--   request(195) =>request_signal(195),
+--   request(196) =>request_signal(196),
+--   request(197) =>request_signal(197),
+--   request(198) =>request_signal(198),
+--   request(199) =>request_signal(199),
+--   request(200) =>request_signal(200),
+--   request(201) =>request_signal(201),
+--   request(202) =>request_signal(202),
+--   request(203) =>request_signal(203),
+--   request(204) =>request_signal(204),
+--   request(205) =>request_signal(205),
+--   request(206) =>request_signal(206),
+--   request(207) =>request_signal(207),
+--   request(208) =>request_signal(208)
+--);
+--
+--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(14),
+--   data_in_en => data_in_en(14),
+--   reset => reset,
+--   clk =>clk,
+--   grant(209) => grant_signal(209),
+--   grant(210) => grant_signal(210),
+--   grant(211) => grant_signal(211),
+--   grant(212) => grant_signal(212),
+--   grant(213) => grant_signal(213),
+--   grant(214) => grant_signal(214),
+--   grant(215) => grant_signal(215),
+--   grant(216) => grant_signal(216),
+--   grant(217) => grant_signal(217),
+--   grant(218) => grant_signal(218),
+--   grant(219) => grant_signal(219),
+--   grant(220) => grant_signal(220),
+--   grant(221) => grant_signal(221),
+--   grant(222) => grant_signal(222),
+--   grant(223) => grant_signal(223),
+--   grant(224) => grant_signal(224),
+--   fifo_full =>fifo_in_full(14),
+--   priority_rotation =>  priority_rotation_signal(14),
+--   fifo_empty => fifo_in_empty(14),
+--   data_out =>crossbar_in_port(14),
+--   data_out_pulse =>crossbar_in_pulse(14),
+--   request(209) =>request_signal(209),
+--   request(210) =>request_signal(210),
+--   request(211) =>request_signal(211),
+--   request(212) =>request_signal(212),
+--   request(213) =>request_signal(213),
+--   request(214) =>request_signal(214),
+--   request(215) =>request_signal(215),
+--   request(216) =>request_signal(216),
+--   request(217) =>request_signal(217),
+--   request(218) =>request_signal(218),
+--   request(219) =>request_signal(219),
+--   request(220) =>request_signal(220),
+--   request(221) =>request_signal(221),
+--   request(222) =>request_signal(222),
+--   request(223) =>request_signal(223),
+--   request(224) =>request_signal(224)
+--);
+--
+--PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(15),
+--   data_in_en => data_in_en(15),
+--   reset => reset,
+--   clk =>clk,
+--   grant(225) => grant_signal(225),
+--   grant(226) => grant_signal(226),
+--   grant(227) => grant_signal(227),
+--   grant(228) => grant_signal(228),
+--   grant(229) => grant_signal(229),
+--   grant(230) => grant_signal(230),
+--   grant(231) => grant_signal(231),
+--   grant(232) => grant_signal(232),
+--   grant(233) => grant_signal(233),
+--   grant(234) => grant_signal(234),
+--   grant(235) => grant_signal(235),
+--   grant(236) => grant_signal(236),
+--   grant(237) => grant_signal(237),
+--   grant(238) => grant_signal(238),
+--   grant(239) => grant_signal(239),
+--   grant(240) => grant_signal(240),
+--   fifo_full =>fifo_in_full(15),
+--   priority_rotation =>  priority_rotation_signal(15),
+--   fifo_empty => fifo_in_empty(15),
+--   data_out =>crossbar_in_port(15),
+--   data_out_pulse =>crossbar_in_pulse(15),
+--   request(225) =>request_signal(225),
+--   request(226) =>request_signal(226),
+--   request(227) =>request_signal(227),
+--   request(228) =>request_signal(228),
+--   request(229) =>request_signal(229),
+--   request(230) =>request_signal(230),
+--   request(231) =>request_signal(231),
+--   request(232) =>request_signal(232),
+--   request(233) =>request_signal(233),
+--   request(234) =>request_signal(234),
+--   request(235) =>request_signal(235),
+--   request(236) =>request_signal(236),
+--   request(237) =>request_signal(237),
+--   request(238) =>request_signal(238),
+--   request(239) =>request_signal(239),
+--   request(240) =>request_signal(240)
+--);
+--
+--PORT16_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(16),
+--   data_in_en => data_in_en(16),
+--   reset => reset,
+--   clk =>clk,
+--   grant(241) => grant_signal(241),
+--   grant(242) => grant_signal(242),
+--   grant(243) => grant_signal(243),
+--   grant(244) => grant_signal(244),
+--   grant(245) => grant_signal(245),
+--   grant(246) => grant_signal(246),
+--   grant(247) => grant_signal(247),
+--   grant(248) => grant_signal(248),
+--   grant(249) => grant_signal(249),
+--   grant(250) => grant_signal(250),
+--   grant(251) => grant_signal(251),
+--   grant(252) => grant_signal(252),
+--   grant(253) => grant_signal(253),
+--   grant(254) => grant_signal(254),
+--   grant(255) => grant_signal(255),
+--   grant(256) => grant_signal(256),
+--   fifo_full =>fifo_in_full(16),
+--   priority_rotation =>  priority_rotation_signal(16),
+--   fifo_empty => fifo_in_empty(16),
+--   data_out =>crossbar_in_port(16),
+--   data_out_pulse =>crossbar_in_pulse(16),
+--   request(241) =>request_signal(241),
+--   request(242) =>request_signal(242),
+--   request(243) =>request_signal(243),
+--   request(244) =>request_signal(244),
+--   request(245) =>request_signal(245),
+--   request(246) =>request_signal(246),
+--   request(247) =>request_signal(247),
+--   request(248) =>request_signal(248),
+--   request(249) =>request_signal(249),
+--   request(250) =>request_signal(250),
+--   request(251) =>request_signal(251),
+--   request(252) =>request_signal(252),
+--   request(253) =>request_signal(253),
+--   request(254) =>request_signal(254),
+--   request(255) =>request_signal(255),
+--   request(256) =>request_signal(256)
+--);
+--
+--end generate switch16x16;
+-- intstanciation et connexion des modules des ports de sorties fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+port_out_switch2x2 : if number_of_ports = 2 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+end generate port_out_switch2x2;
+
+
+-- switch 3 ports
+port_out_switch3x3 : if number_of_ports = 3 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+end generate port_out_switch3x3;
+
+
+-- switch 4 ports
+port_out_switch4x4 : if number_of_ports = 4 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+end generate port_out_switch4x4;
+
+
+-- switch 5 ports
+port_out_switch5x5 : if number_of_ports = 5 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+end generate port_out_switch5x5;
+
+
+-- switch 6 ports
+port_out_switch6x6 : if number_of_ports = 6 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+end generate port_out_switch6x6;
+
+
+-- switch 7 ports
+port_out_switch7x7 : if number_of_ports = 7 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+end generate port_out_switch7x7;
+
+
+-- switch 8 ports
+port_out_switch8x8 : if number_of_ports = 8 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+end generate port_out_switch8x8;
+
+
+-- switch 9 ports
+port_out_switch9x9 : if number_of_ports = 9 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(9),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(9),
+     data_out =>Port_out(9),
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+end generate port_out_switch9x9;
+
+
+-- switch 10 ports
+port_out_switch10x10 : if number_of_ports = 10 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(9),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(9),
+     data_out =>Port_out(9),
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(10),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(10),
+     data_out =>Port_out(10),
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+end generate port_out_switch10x10;
+
+
+-- switch 11 ports
+port_out_switch11x11 : if number_of_ports = 11 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(9),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(9),
+     data_out =>Port_out(9),
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(10),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(10),
+     data_out =>Port_out(10),
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(11),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(11),
+     data_out =>Port_out(11),
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+end generate port_out_switch11x11;
+
+
+-- switch 12 ports
+port_out_switch12x12 : if number_of_ports = 12 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(9),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(9),
+     data_out =>Port_out(9),
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(10),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(10),
+     data_out =>Port_out(10),
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(11),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(11),
+     data_out =>Port_out(11),
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(12),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(12),
+     data_out =>Port_out(12),
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+end generate port_out_switch12x12;
+
+
+-- switch 13 ports
+port_out_switch13x13 : if number_of_ports = 13 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(9),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(9),
+     data_out =>Port_out(9),
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(10),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(10),
+     data_out =>Port_out(10),
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(11),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(11),
+     data_out =>Port_out(11),
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(12),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(12),
+     data_out =>Port_out(12),
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(13),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(13),
+     data_out =>Port_out(13),
+     fifo_full =>fifo_out_full_signal(13),
+     data_avalaible => data_available(13),
+     rd_out_en => data_out_en(13)
+    );
+
+end generate port_out_switch13x13;
+
+
+-- switch 14 ports
+port_out_switch14x14 : if number_of_ports = 14 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(9),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(9),
+     data_out =>Port_out(9),
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(10),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(10),
+     data_out =>Port_out(10),
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(11),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(11),
+     data_out =>Port_out(11),
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(12),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(12),
+     data_out =>Port_out(12),
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(13),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(13),
+     data_out =>Port_out(13),
+     fifo_full =>fifo_out_full_signal(13),
+     data_avalaible => data_available(13),
+     rd_out_en => data_out_en(13)
+    );
+
+PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(14),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(14),
+     data_out =>Port_out(14),
+     fifo_full =>fifo_out_full_signal(14),
+     data_avalaible => data_available(14),
+     rd_out_en => data_out_en(14)
+    );
+
+end generate port_out_switch14x14;
+
+
+-- switch 15 ports
+port_out_switch15x15 : if number_of_ports = 15 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(9),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(9),
+     data_out =>Port_out(9),
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(10),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(10),
+     data_out =>Port_out(10),
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(11),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(11),
+     data_out =>Port_out(11),
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(12),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(12),
+     data_out =>Port_out(12),
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(13),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(13),
+     data_out =>Port_out(13),
+     fifo_full =>fifo_out_full_signal(13),
+     data_avalaible => data_available(13),
+     rd_out_en => data_out_en(13)
+    );
+
+PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(14),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(14),
+     data_out =>Port_out(14),
+     fifo_full =>fifo_out_full_signal(14),
+     data_avalaible => data_available(14),
+     rd_out_en => data_out_en(14)
+    );
+
+PORT15_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(15),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(15),
+     data_out =>Port_out(15),
+     fifo_full =>fifo_out_full_signal(15),
+     data_avalaible => data_available(15),
+     rd_out_en => data_out_en(15)
+    );
+
+end generate port_out_switch15x15;
+
+
+-- switch 16 ports
+port_out_switch16x16 : if number_of_ports = 16 generate
+port_out_switch_16x16:for i in 1 to number_of_ports generate
+  begin
+  PORTx16_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(i),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(i),
+     data_out =>Port_out(i),
+     fifo_full =>fifo_out_full_signal(i),
+     data_avalaible => data_available(i),
+     rd_out_en => data_out_en(i)
+    );
+end generate port_out_switch_16x16;
+
+end generate port_out_switch16x16;
+
+-- intstanciation et connexion des crossbars du  switch en fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+crossbar_switch2x2 : if number_of_ports = 2 generate
+
+Switch_Crossbar2_2: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>2)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => "00000000",
+   Port4_in => "00000000",
+   Port5_in => "00000000",
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in =>'0' ,
+   Port4_pulse_in =>'0' ,
+   Port5_pulse_in =>'0' ,
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+   Ctrl => Grant_signal);
+end generate crossbar_switch2x2;
+
+
+-- switch 3 ports
+crossbar_switch3x3 : if number_of_ports = 3 generate
+
+Switch_Crossbar3_3: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>3)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => "00000000",
+   Port5_in => "00000000",
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in =>'0' ,
+   Port5_pulse_in =>'0' ,
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+   Ctrl => Grant_signal);
+end generate crossbar_switch3x3;
+
+
+-- switch 4 ports
+crossbar_switch4x4 : if number_of_ports = 4 generate
+
+Switch_Crossbar4_4: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>4)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => "00000000",
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in =>'0' ,
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+   Ctrl => Grant_signal);
+end generate crossbar_switch4x4;
+
+
+-- switch 5 ports
+crossbar_switch5x5 : if number_of_ports = 5 generate
+
+Switch_Crossbar5_5: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>5)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+   Ctrl => Grant_signal);
+end generate crossbar_switch5x5;
+
+
+-- switch 6 ports
+crossbar_switch6x6 : if number_of_ports = 6 generate
+
+Switch_Crossbar6_6: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>6)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+   Ctrl => Grant_signal);
+end generate crossbar_switch6x6;
+
+
+-- switch 7 ports
+crossbar_switch7x7 : if number_of_ports = 7 generate
+
+Switch_Crossbar7_7: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>7)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+   Ctrl => Grant_signal);
+end generate crossbar_switch7x7;
+
+
+-- switch 8 ports
+crossbar_switch8x8 : if number_of_ports = 8 generate
+
+Switch_Crossbar8_8: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>8)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+   Ctrl => Grant_signal);
+end generate crossbar_switch8x8;
+
+
+-- switch 9 ports
+crossbar_switch9x9 : if number_of_ports = 9 generate
+
+Switch_Crossbar9_9: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>9)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+   Ctrl => Grant_signal);
+end generate crossbar_switch9x9;
+
+
+-- switch 10 ports
+crossbar_switch10x10 : if number_of_ports = 10 generate
+
+Switch_Crossbar10_10: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>10)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => crossbar_in_port(10),
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in => crossbar_in_pulse(10),
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+   Port10_pulse_out => crossbar_out_pulse(10),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+  Port10_out => crossbar_out_port(10),
+   Ctrl => Grant_signal);
+end generate crossbar_switch10x10;
+
+
+-- switch 11 ports
+crossbar_switch11x11 : if number_of_ports = 11 generate
+
+Switch_Crossbar11_11: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>11)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => crossbar_in_port(10),
+   Port11_in => crossbar_in_port(11),
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in => crossbar_in_pulse(10),
+   Port11_pulse_in => crossbar_in_pulse(11),
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+   Port10_pulse_out => crossbar_out_pulse(10),
+   Port11_pulse_out => crossbar_out_pulse(11),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+  Port10_out => crossbar_out_port(10),
+  Port11_out => crossbar_out_port(11),
+   Ctrl => Grant_signal);
+end generate crossbar_switch11x11;
+
+
+-- switch 12 ports
+crossbar_switch12x12 : if number_of_ports = 12 generate
+
+Switch_Crossbar12_12: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>12)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => crossbar_in_port(10),
+   Port11_in => crossbar_in_port(11),
+   Port12_in => crossbar_in_port(12),
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in => crossbar_in_pulse(10),
+   Port11_pulse_in => crossbar_in_pulse(11),
+   Port12_pulse_in => crossbar_in_pulse(12),
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+   Port10_pulse_out => crossbar_out_pulse(10),
+   Port11_pulse_out => crossbar_out_pulse(11),
+   Port12_pulse_out => crossbar_out_pulse(12),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+  Port10_out => crossbar_out_port(10),
+  Port11_out => crossbar_out_port(11),
+  Port12_out => crossbar_out_port(12),
+   Ctrl => Grant_signal);
+end generate crossbar_switch12x12;
+
+
+-- switch 13 ports
+crossbar_switch13x13 : if number_of_ports = 13 generate
+
+Switch_Crossbar13_13: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>13)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => crossbar_in_port(10),
+   Port11_in => crossbar_in_port(11),
+   Port12_in => crossbar_in_port(12),
+   Port13_in => crossbar_in_port(13),
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in => crossbar_in_pulse(10),
+   Port11_pulse_in => crossbar_in_pulse(11),
+   Port12_pulse_in => crossbar_in_pulse(12),
+   Port13_pulse_in => crossbar_in_pulse(13),
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+   Port10_pulse_out => crossbar_out_pulse(10),
+   Port11_pulse_out => crossbar_out_pulse(11),
+   Port12_pulse_out => crossbar_out_pulse(12),
+   Port13_pulse_out => crossbar_out_pulse(13),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+  Port10_out => crossbar_out_port(10),
+  Port11_out => crossbar_out_port(11),
+  Port12_out => crossbar_out_port(12),
+  Port13_out => crossbar_out_port(13),
+   Ctrl => Grant_signal);
+end generate crossbar_switch13x13;
+
+
+-- switch 14 ports
+crossbar_switch14x14 : if number_of_ports = 14 generate
+
+Switch_Crossbar14_14: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>14)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => crossbar_in_port(10),
+   Port11_in => crossbar_in_port(11),
+   Port12_in => crossbar_in_port(12),
+   Port13_in => crossbar_in_port(13),
+   Port14_in => crossbar_in_port(14),
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in => crossbar_in_pulse(10),
+   Port11_pulse_in => crossbar_in_pulse(11),
+   Port12_pulse_in => crossbar_in_pulse(12),
+   Port13_pulse_in => crossbar_in_pulse(13),
+   Port14_pulse_in => crossbar_in_pulse(14),
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+   Port10_pulse_out => crossbar_out_pulse(10),
+   Port11_pulse_out => crossbar_out_pulse(11),
+   Port12_pulse_out => crossbar_out_pulse(12),
+   Port13_pulse_out => crossbar_out_pulse(13),
+   Port14_pulse_out => crossbar_out_pulse(14),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+  Port10_out => crossbar_out_port(10),
+  Port11_out => crossbar_out_port(11),
+  Port12_out => crossbar_out_port(12),
+  Port13_out => crossbar_out_port(13),
+  Port14_out => crossbar_out_port(14),
+   Ctrl => Grant_signal);
+end generate crossbar_switch14x14;
+
+
+-- switch 15 ports
+crossbar_switch15x15 : if number_of_ports = 15 generate
+
+Switch_Crossbar15_15: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>15)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => crossbar_in_port(10),
+   Port11_in => crossbar_in_port(11),
+   Port12_in => crossbar_in_port(12),
+   Port13_in => crossbar_in_port(13),
+   Port14_in => crossbar_in_port(14),
+   Port15_in => crossbar_in_port(15),
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in => crossbar_in_pulse(10),
+   Port11_pulse_in => crossbar_in_pulse(11),
+   Port12_pulse_in => crossbar_in_pulse(12),
+   Port13_pulse_in => crossbar_in_pulse(13),
+   Port14_pulse_in => crossbar_in_pulse(14),
+   Port15_pulse_in => crossbar_in_pulse(15),
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+   Port10_pulse_out => crossbar_out_pulse(10),
+   Port11_pulse_out => crossbar_out_pulse(11),
+   Port12_pulse_out => crossbar_out_pulse(12),
+   Port13_pulse_out => crossbar_out_pulse(13),
+   Port14_pulse_out => crossbar_out_pulse(14),
+   Port15_pulse_out => crossbar_out_pulse(15),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+  Port10_out => crossbar_out_port(10),
+  Port11_out => crossbar_out_port(11),
+  Port12_out => crossbar_out_port(12),
+  Port13_out => crossbar_out_port(13),
+  Port14_out => crossbar_out_port(14),
+  Port15_out => crossbar_out_port(15),
+   Ctrl => Grant_signal);
+end generate crossbar_switch15x15;
+
+
+-- switch 16 ports
+crossbar_switch16x16 : if number_of_ports = 16 generate
+
+Switch_Crossbar16_16: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>16)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => crossbar_in_port(10),
+   Port11_in => crossbar_in_port(11),
+   Port12_in => crossbar_in_port(12),
+   Port13_in => crossbar_in_port(13),
+   Port14_in => crossbar_in_port(14),
+   Port15_in => crossbar_in_port(15),
+   Port16_in => crossbar_in_port(16),
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in => crossbar_in_pulse(10),
+   Port11_pulse_in => crossbar_in_pulse(11),
+   Port12_pulse_in => crossbar_in_pulse(12),
+   Port13_pulse_in => crossbar_in_pulse(13),
+   Port14_pulse_in => crossbar_in_pulse(14),
+   Port15_pulse_in => crossbar_in_pulse(15),
+   Port16_pulse_in => crossbar_in_pulse(16),
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+   Port10_pulse_out => crossbar_out_pulse(10),
+   Port11_pulse_out => crossbar_out_pulse(11),
+   Port12_pulse_out => crossbar_out_pulse(12),
+   Port13_pulse_out => crossbar_out_pulse(13),
+   Port14_pulse_out => crossbar_out_pulse(14),
+   Port15_pulse_out => crossbar_out_pulse(15),
+   Port16_pulse_out => crossbar_out_pulse(16),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+  Port10_out => crossbar_out_port(10),
+  Port11_out => crossbar_out_port(11),
+  Port12_out => crossbar_out_port(12),
+  Port13_out => crossbar_out_port(13),
+  Port14_out => crossbar_out_port(14),
+  Port15_out => crossbar_out_port(15),
+  Port16_out => crossbar_out_port(16),
+   Ctrl => Grant_signal);
+end generate crossbar_switch16x16;
+-- intstanciation et connexion du scheduler en fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+scheduler_switch2x2 : if number_of_ports = 2 generate
+
+Scheduler2_2: Scheduler 
+   GENERIC MAP(number_of_ports => 2 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch2x2;
+
+
+-- switch 3 ports
+scheduler_switch3x3 : if number_of_ports = 3 generate
+
+Scheduler3_3: Scheduler 
+   GENERIC MAP(number_of_ports => 3 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch3x3;
+
+
+-- switch 4 ports
+scheduler_switch4x4 : if number_of_ports = 4 generate
+
+Scheduler4_4: Scheduler 
+   GENERIC MAP(number_of_ports => 4 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch4x4;
+
+
+-- switch 5 ports
+scheduler_switch5x5 : if number_of_ports = 5 generate
+
+Scheduler5_5: Scheduler 
+   GENERIC MAP(number_of_ports => 5 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch5x5;
+
+
+-- switch 6 ports
+scheduler_switch6x6 : if number_of_ports = 6 generate
+
+Scheduler6_6: Scheduler 
+   GENERIC MAP(number_of_ports => 6 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch6x6;
+
+
+-- switch 7 ports
+scheduler_switch7x7 : if number_of_ports = 7 generate
+
+Scheduler7_7: Scheduler 
+   GENERIC MAP(number_of_ports => 7 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch7x7;
+
+
+-- switch 8 ports
+scheduler_switch8x8 : if number_of_ports = 8 generate
+
+Scheduler8_8: Scheduler 
+   GENERIC MAP(number_of_ports => 8 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch8x8;
+
+
+-- switch 9 ports
+scheduler_switch9x9 : if number_of_ports = 9 generate
+
+Scheduler9_9: Scheduler 
+   GENERIC MAP(number_of_ports => 9 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch9x9;
+
+
+-- switch 10 ports
+scheduler_switch10x10 : if number_of_ports = 10 generate
+
+Scheduler10_10: Scheduler 
+   GENERIC MAP(number_of_ports => 10 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch10x10;
+
+
+-- switch 11 ports
+scheduler_switch11x11 : if number_of_ports = 11 generate
+
+Scheduler11_11: Scheduler 
+   GENERIC MAP(number_of_ports => 11 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch11x11;
+
+
+-- switch 12 ports
+scheduler_switch12x12 : if number_of_ports = 12 generate
+
+Scheduler12_12: Scheduler 
+   GENERIC MAP(number_of_ports => 12 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch12x12;
+
+
+-- switch 13 ports
+scheduler_switch13x13 : if number_of_ports = 13 generate
+
+Scheduler13_13: Scheduler 
+   GENERIC MAP(number_of_ports => 13 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch13x13;
+
+
+-- switch 14 ports
+scheduler_switch14x14 : if number_of_ports = 14 generate
+
+Scheduler14_14: Scheduler 
+   GENERIC MAP(number_of_ports => 14 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch14x14;
+
+
+-- switch 15 ports
+scheduler_switch15x15 : if number_of_ports = 15 generate
+
+Scheduler15_15: Scheduler 
+   GENERIC MAP(number_of_ports => 15 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch15x15;
+
+
+-- switch 16 ports
+scheduler_switch16x16 : if number_of_ports = 16 generate
+
+Scheduler16_16: Scheduler 
+   GENERIC MAP(number_of_ports => 16 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch16x16;
+
+
+end Behavioral;
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Arbiter.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Arbiter.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Arbiter.vhd	(revision 20)
@@ -0,0 +1,83 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: Kiegaing Emmanuel GEL EN5
+-- 
+-- Create Date:    18:18:09 03/19/2011 
+-- Design Name: 
+-- Module Name:    Arbiter - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+-- cellule d'arbitrage de l'ordonnanceur du crossbar
+-- Dependencies: 
+--
+-- Revision: 1.0
+-- a été ajouté le signal fifo_full pour inclure la codition buffer pas plein dans
+-- la cellules d'arbitrage
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Arbiter is
+    Port ( P: in  STD_LOGIC;--vecteur de priorité
+			  Fifo_full : in STD_LOGIC;
+           Request : in  STD_LOGIC;-- demande de permission
+           West : in  STD_LOGIC;-- verouillage ouest
+           North : in  STD_LOGIC;--etc
+           Grant : out  STD_LOGIC;-- validation de la transition
+           East : out  STD_LOGIC;
+           South : out  STD_LOGIC);
+end Arbiter;
+
+architecture Behavioral of Arbiter is
+-- modelisation comportementale 3 LUT après synthèse
+-- ce module peut aussi facilement s'implémenter en flot de données
+signal grant_signal : STD_LOGIC; 
+--signal not_fifo_full : STD_LOGIC;
+signal Mask : STD_LOGIC;
+begin
+--Grant<=grant_signal; -- Grant n'a pas été déclarée InOut
+Mask <= P AND (not Fifo_full);
+process(Mask, Request, North, West)-- genere de la logique purement combinatoire
+begin
+if Mask ='0' then --cellule inactive
+Grant <= '0';-- pas d'autorisation
+South <= '1';
+East <= '1';
+   else
+	Grant <= Request And North And West;
+	South <= (North) And (Not (Request And North And West));	
+	East  <= (West)  And (Not (Request And North And West));
+end if;
+end process;
+
+end Behavioral;
+--modélidation flot de données elle semble plus efficace 3 LUT
+--architecture Behavioral of Arbiter is
+--signal x, x1, x2, x3, x4, x5: STD_LOGIC; 
+--begin
+----equations logiques de la cellule
+--x  <= Mask And Request;
+--x1 <= North;
+--x2 <= West;
+--x3 <= x And x1 And x2;
+--x4 <= x1 And (Not x3);
+--x5 <= x2 And (Not x3);
+--South <= x4 Or (Not Mask);
+--East  <= x5 Or (Not Mask);
+--Grant <= x3;
+--
+--end Behavioral;
+
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Backup_prj.bat
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Backup_prj.bat	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Backup_prj.bat	(revision 20)
@@ -0,0 +1,34 @@
+@Echo off
+rem Fichier permettant de copier l'ensemble des
+rem sources du projet vers une autre destination
+rem
+Echo donner le chemin de destination des fichiers à copier svp (defaut=D:\Core_MPI\NOC)
+set Dest=
+set /P Dest="Defaut D:\SCORE_MPI\NOC"
+
+if "%Dest%" == "" goto defaut
+if "%Dest%" == " " goto defaut
+ goto normal
+:defaut
+set dest=D:\SCORE_MPI\NOC
+:normal
+echo la destination est
+echo "%Dest%"
+
+If exist %Dest% goto lancecopie
+Echo Attention la destination n'existe pas
+Echo nous tentons de la créer
+MD %Dest%
+If exist %Dest%\nul goto lancecopie
+Echo Création impossible du dossier. 
+Echo le dossier parent n'existe pas ou le chemin est invalide
+Echo vous devez le faire vous-même ou donner un chemin valide.
+goto fin
+:lancecopie
+copy *.vhd %Dest%\
+copy *.wcfg %Dest%\
+copy *.prj %Dest%\
+copy *.ucf %Dest%\
+:fin
+pause
+Echo fin de la copie
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/CoreTypes.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/CoreTypes.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/CoreTypes.vhd	(revision 20)
@@ -0,0 +1,232 @@
+  --	Package File Template
+--
+--	Purpose: This package defines supplemental types, subtypes, 
+--		 constants, and components 
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package CoreTypes is
+CONSTANT Word :POSITIVE:= 8;
+CONSTANT ADRLEN:POSITIVE:=16;
+CONSTANT LZFILL :std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0');--indique le nombre de zero à utiliser pour completer le bus de données lorsque la longueur restante du bus d'adresse est inférueure à la largeur du bus de données
+CONSTANT IADR0 : NATURAL :=2; --Adresse basse de l'instruction
+CONSTANT IADR1 : natural :=3;
+CONSTANT CORE_BASE_ADR :natural range 0 to 65535:=4096;
+CONSTANT CORE_UPPER_ADR : natural range 0 to 255:=16;
+CONSTANT CORE_GET_ADR:natural:=CORE_BASE_ADR+526;
+CONSTANT CORE_PUT_ADR :natural:=CORE_BASE_ADR+516;
+CONSTANT core_INIT_ADR : natural:=CORE_BASE_ADR+512;
+CONSTANT CORE_WCREATE_ADR : natural := CORE_BASE_ADR+536;
+CONSTANT CORE_WCOMPL_ADR : natural := CORE_BASE_ADR+546;
+CONSTANT CORE_WPOST_ADR : natural := CORE_BASE_ADR+556;
+CONSTANT CORE_WWAIT_ADR : natural := CORE_BASE_ADR+566;
+CONSTANT CORE_Rank2port_BASE :NATURAL:=32;
+CONSTANT WIN0_ADR :natural :=4;
+CONSTANT WIN1_ADR :natural :=14;
+CONSTANT WIN2_ADR :natural :=24;
+CONSTANT WIN3_ADR :natural :=34;
+CONSTANT GETPORTID : std_logic_vector(3 downto 0):="0001";
+  
+  type Typ_PortIO is
+   array(natural range <>) of std_logic_vector( Word-1 downto 0);
+	
+	type memory is 
+	array (natural range <>) of std_logic_vector(word-1 downto 0);
+	
+type Core_io is
+	record
+		Instr_en :std_logic;  -- active une instruction MPI
+		Instr_ack :std_logic;-- signal la prise en compte de l'instruction
+		Ready   :std_logic;-- indique que la dernière fonction est terminée
+		InitOk :std_logic; -- l'initialisation est terminée
+		Hold_Req :std_logic;--Demande DMA 
+		Hold_Ack :std_logic;-- Autorisation DMA
+		MemBusy :std_logic;-- active le refus de DMA (1 -> ignoré la requête DMA) 
+		RamSel :std_logic;-- indique le statut de la RAM (0 ->dispo 1->occupé par Core_MPI)
+		IntState1 : natural range 0 to 255; --permet de stocker l'état des MAE interne dans les procédures
+		IntState2 : natural range 0 to 255;
+		Instruction :std_logic_vector (word-1 downto 0);
+		WinId :natural range  0 to 255; --stocke le dernier Id utilisé par WinCreate
+		IsMain : std_logic; -- indique si la librairie est principal
+		Rank : natural range 0 to 16; --donne le rang du processus courant
+end record;
+
+type typ_dpram is
+record
+			  
+           
+	    clk_wr :  STD_LOGIC;
+	    clk_rd :  STD_LOGIC;
+		we     :  STD_LOGIC;
+		ena    :  STD_LOGIC;
+		enb    :  STD_LOGIC;
+		addr_wr:  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
+		addr_rd :  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
+		data_in  :  STD_LOGIC_VECTOR (Word-1 downto 0);
+		data_out :  STD_LOGIC_VECTOR (Word-1 downto 0); 
+			  
+           		  
+end record;        
+type Typ_MPIPort_in is
+record
+			  instruction :   STD_LOGIC_VECTOR (Word -1 downto 0);
+           instruction_en :  STD_LOGIC;
+           		  
+
+			  packet_ack : std_logic;
+           ram_data_out :  STD_LOGIC_VECTOR (Word-1 downto 0);
+			  
+			  hold_ack       :  STD_Logic;  --autorisation par l'application
+			  clk :  STD_LOGIC;
+           reset :  STD_LOGIC;
+           		  
+end record;
+type Typ_MPIPort_out is
+record		  
+          
+			  
+           ram_we :  STD_LOGIC;
+			  ram_en :  STD_LOGIC;
+			  ram_data_in : STD_LOGIC_VECTOR (WORD-1 downto 0);
+           ram_address_rd :  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
+			  ram_address_wr :  STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
+			  packet_received : STD_LOGIC;
+			  barrier_completed : STD_LOGIC;
+           instruction_fifo_full : STD_LOGIC;
+			  PushOut :  STD_LOGIC_VECTOR (WORD-1 downto 0);
+			   
+           hold_req       : STD_Logic;  --requete vers application
+end record;
+
+Type Ar_MPIPort_In is array (positive range <>) of Typ_MPIPort_in;
+Type Ar_MPIPort_out is array (positive range <>) of Typ_MPIPort_out;
+
+-- Declare constants
+
+--  constant <constant_name>		: time := <time_unit> ns;
+--  constant <constant_name>		: integer := <value>;
+-- 
+-- Declare functions and procedure
+Component  SWITCH_GEN is     
+ generic(number_of_ports : positive := 8);
+     port(
+	        -- ports d'entree
+           Port_in : in typ_portIO(1 to number_of_ports) ;
+--			  
+			 
+			  -- port de sortie
+			  Port_out : out  typ_portIO(1 to number_of_ports);
+--			  
+			  -- signaux de controle
+			  cmd_in_en : in std_logic_vector(number_of_ports downto 1);
+			  data_in_en : in std_logic_vector(number_of_ports downto 1);
+			  data_out_en : in std_logic_vector(number_of_ports downto 1);
+			  fifo_in_full : out std_logic_vector(number_of_ports downto 1);
+			  fifo_in_empty : out std_logic_vector(number_of_ports downto 1);
+			  data_available : out std_logic_vector(number_of_ports downto 1);
+			  clk       : in   STD_LOGIC;
+			  reset     : in   STD_LOGIC);
+end component SWITCH_GEN;
+-- déclaration des fonctions utilisées
+ 
+ FUNCTION all_ones(s1:std_logic_vector) return std_logic; 
+  --This function returns if the input vector has all ones and no zeros
+ FUNCTION all_zeros(s1:std_logic_vector) return std_logic; 
+  --This function returns if the input vector has all zeros and no ones
+ FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector; 
+  --This function increments an std_logic_vector type by '1', without 
+  --using any arithmatic
+
+  FUNCTION dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector; 
+  --This function decrements an std_logic_vector type by '1', without 
+  --using any arithmatic
+  FUNCTION Rol_Vec(s1:std_logic_vector) return std_logic_vector;
+  --renvoie un std_logic_vector de taille ADRLEN
+  Function Stdlv (s1 : natural ) return std_logic_vector;
+end CoreTypes;
+
+
+Package body CoreTypes is
+
+
+FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is 
+                  --this function increments a std_logic_vector type by '1' 
+        VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
+        VARIABLE tb : std_logic_vector(s1'high downto s1'low); 
+        BEGIN 
+        tb(s1'low) := en; 
+        V := s1; 
+        for i in (V'low + 1) to V'high loop 
+            tb(i) := V(i - 1) and tb(i -1); 
+        end loop; 
+        for i in V'low to V'high loop 
+            if(tb(i) = '1') then 
+                V(i) := not(V(i)); 
+            end if; 
+        end loop; 
+        return V; 
+        end incr_vec; -- end function
+
+FUNCTION  dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is 
+                  --this function decrements a std_logic_vector type by '1' 
+        VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
+        VARIABLE tb : std_logic_vector(s1'high downto s1'low); 
+        BEGIN 
+        tb(s1'low) := not(en); 
+        V := s1; 
+        for i in (V'low + 1) to V'high loop 
+            tb(i) := V(i - 1) or tb(i -1); 
+        end loop; 
+        for i in V'low to V'high loop 
+            if(tb(i) = '0') then 
+                V(i) := not(V(i)); 
+            end if; 
+        end loop; 
+        return V; 
+        end dcr_vec; -- end function
+FUNCTION all_ones(s1:std_logic_vector) return std_logic is 
+                  --this function tells if all bits of a vector are '1' 
+                  --return value Z is '1', then vector has all 1 bits 
+        --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
+        VARIABLE Z : std_logic; 
+        BEGIN 
+        Z := s1(s1'low); 
+        FOR i IN (s1'low+1) to s1'high LOOP 
+            Z := Z AND s1(i); 
+        END LOOP; 
+        RETURN Z; 
+        END all_ones; -- end function
+FUNCTION all_zeros(s1:std_logic_vector) return std_logic is 
+                  --this function tells if all bits of a vector are '0' 
+                  --return value Z if '1', then vector has all 0 bits 
+        --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
+        VARIABLE Z : std_logic; 
+        BEGIN 
+        Z := '0'; 
+        FOR i IN (s1'low) to s1'high LOOP 
+            Z := Z OR s1(i); 
+        END LOOP; 
+        RETURN not(Z); 
+        END all_zeros; -- end function
+		  
+FUNCTION Rol_Vec(s1:std_logic_vector) return std_logic_vector is
+--cette fonction fait roter un STD_logic d'un pas vers la gauche
+VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
+        VARIABLE lb : std_logic :=s1(s1'left);
+        BEGIN 
+     
+        for i in V'left  downto (V'right+1) loop 
+            V(i) := s1(i - 1) ; 
+        end loop; 
+        V(V'right):=lb;
+        return V; 
+        end Rol_vec;
+ Function Stdlv (s1 : natural ) return std_logic_vector is
+VARIABLE V : std_logic_vector(ADRLEN-1 downto 0)
+ begin
+	V:=std_logic_vector(to_unsigned(s1,ADRLEN));
+	return V;
+ end stdlv;
+end CoreTypes;
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Crossbar.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Crossbar.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Crossbar.vhd	(revision 20)
@@ -0,0 +1,3876 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL
+-- 
+-- Create Date:    11:48:18 06/19/2011 
+-- Design Name: 
+-- Module Name:    Crossbar - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: module implémentant les crossbar
+-- ce module instacie les crossbar 1 bit du fichier crossbit.vhd
+--  
+-- CROSSBAR GENERIQUE
+-- Revision: 1.0
+-- a été retiré les signaux inutilisées comme fp, port_source, etc...
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library NocLib ;
+use NocLib.CoreTypes.all;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Crossbar is
+    generic
+	      (
+			  number_of_crossbar_ports: positive := 4
+			);
+    Port ( Port1_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port2_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port3_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port4_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+			  Port5_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port6_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port7_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port8_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+			  Port9_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port10_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port11_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port12_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+			  Port13_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port14_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port15_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port16_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+			  
+			  Port1_pulse_in : in std_logic;
+			  Port2_pulse_in : in std_logic;
+			  Port3_pulse_in : in std_logic;
+			  Port4_pulse_in : in std_logic;
+			  Port5_pulse_in : in std_logic;
+			  Port6_pulse_in : in std_logic;
+			  Port7_pulse_in : in std_logic;
+			  Port8_pulse_in : in std_logic;
+			  Port9_pulse_in : in std_logic;
+			  Port10_pulse_in : in std_logic;
+			  Port11_pulse_in : in std_logic;
+			  Port12_pulse_in : in std_logic;
+			  Port13_pulse_in : in std_logic;
+			  Port14_pulse_in : in std_logic;
+			  Port15_pulse_in : in std_logic;
+			  Port16_pulse_in : in std_logic;
+			  
+			  Port1_pulse_out : out std_logic;
+			  Port2_pulse_out : out std_logic;
+			  Port3_pulse_out : out std_logic;
+			  Port4_pulse_out : out std_logic;
+			  Port5_pulse_out : out std_logic;
+			  Port6_pulse_out : out std_logic;
+			  Port7_pulse_out : out std_logic;
+			  Port8_pulse_out : out std_logic;
+			  Port9_pulse_out : out std_logic;
+			  Port10_pulse_out : out std_logic;
+			  Port11_pulse_out : out std_logic;
+			  Port12_pulse_out : out std_logic;
+			  Port13_pulse_out : out std_logic;
+			  Port14_pulse_out : out std_logic;
+			  Port15_pulse_out : out std_logic;
+			  Port16_pulse_out : out std_logic;
+			  
+			  Port1_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port2_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port3_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port4_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
+			  Port5_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port6_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port7_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port8_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
+			  Port9_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port10_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port11_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port12_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
+			  Port13_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port14_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port15_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           Port16_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); 
+			  
+           Ctrl : in  STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1)
+            );        
+end Crossbar;
+
+architecture Behavioral of Crossbar is
+
+-- declaration du crossbar un bit instanciés pour former les crossbars
+COMPONENT Crossbit
+	generic
+	      (
+			  number_of_ports : positive := 4
+			);
+    Port ( Control : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
+           Data_In : in  STD_LOGIC_VECTOR (number_of_ports downto 1);
+           Data_out : out  STD_LOGIC_VECTOR (number_of_ports downto 1));
+	END COMPONENT;	
+	
+begin
+-- La matrice interconnectee
+-- le circuit genere depend du parametre generique nombre de ports
+
+--======================crossbar 2 ports=======================
+
+crossbar2x2 : if number_of_crossbar_ports = 2 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7)
+
+           );
+-- crossbit du pulse_out 2 ports 
+
+   Pulse_out_Crossbit2: Crossbit 
+      GENERIC MAP(number_of_ports => 2)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out 
+
+           );
+end generate crossbar2x2;
+
+
+--======================crossbar 3 ports=======================
+
+crossbar3x3 : if number_of_crossbar_ports = 3 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7)
+
+           );
+-- crossbit du pulse_out 3 ports 
+
+   Pulse_out_Crossbit3: Crossbit 
+      GENERIC MAP(number_of_ports => 3)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out 
+
+           );
+end generate crossbar3x3;
+
+
+--======================crossbar 4 ports=======================
+
+crossbar4x4 : if number_of_crossbar_ports = 4 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7)
+
+           );
+-- crossbit du pulse_out 4 ports 
+
+   Pulse_out_Crossbit4: Crossbit 
+      GENERIC MAP(number_of_ports => 4)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out 
+
+           );
+end generate crossbar4x4;
+
+
+--======================crossbar 5 ports=======================
+
+crossbar5x5 : if number_of_crossbar_ports = 5 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7)
+
+           );
+-- crossbit du pulse_out 5 ports 
+
+   Pulse_out_Crossbit5: Crossbit 
+      GENERIC MAP(number_of_ports => 5)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out 
+
+           );
+end generate crossbar5x5;
+
+
+--======================crossbar 6 ports=======================
+
+crossbar6x6 : if number_of_crossbar_ports = 6 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7)
+
+           );
+-- crossbit du pulse_out 6 ports 
+
+   Pulse_out_Crossbit6: Crossbit 
+      GENERIC MAP(number_of_ports => 6)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out 
+
+           );
+end generate crossbar6x6;
+
+
+--======================crossbar 7 ports=======================
+
+crossbar7x7 : if number_of_crossbar_ports = 7 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7)
+
+           );
+-- crossbit du pulse_out 7 ports 
+
+   Pulse_out_Crossbit7: Crossbit 
+      GENERIC MAP(number_of_ports => 7)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out 
+
+           );
+end generate crossbar7x7;
+
+
+--======================crossbar 8 ports=======================
+
+crossbar8x8 : if number_of_crossbar_ports = 8 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7)
+
+           );
+-- crossbit du pulse_out 8 ports 
+
+   Pulse_out_Crossbit8: Crossbit 
+      GENERIC MAP(number_of_ports => 8)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out 
+
+           );
+end generate crossbar8x8;
+
+
+--======================crossbar 9 ports=======================
+
+crossbar9x9 : if number_of_crossbar_ports = 9 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7)
+
+           );
+-- crossbit du pulse_out 9 ports 
+
+   Pulse_out_Crossbit9: Crossbit 
+      GENERIC MAP(number_of_ports => 9)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out 
+
+           );
+end generate crossbar9x9;
+
+
+--======================crossbar 10 ports=======================
+
+crossbar10x10 : if number_of_crossbar_ports = 10 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_In(10) => Port10_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0),
+       Data_out(10)=> Port10_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_In(10) => Port10_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1),
+       Data_out(10)=> Port10_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_In(10) => Port10_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2),
+       Data_out(10)=> Port10_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_In(10) => Port10_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3),
+       Data_out(10)=> Port10_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_In(10) => Port10_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4),
+       Data_out(10)=> Port10_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_In(10) => Port10_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5),
+       Data_out(10)=> Port10_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_In(10) => Port10_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6),
+       Data_out(10)=> Port10_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_In(10) => Port10_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7),
+       Data_out(10)=> Port10_out(7)
+
+           );
+-- crossbit du pulse_out 10 ports 
+
+   Pulse_out_Crossbit10: Crossbit 
+      GENERIC MAP(number_of_ports => 10)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_In(10) => Port10_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out,
+       Data_out(10) => Port10_pulse_out 
+
+           );
+end generate crossbar10x10;
+
+
+--======================crossbar 11 ports=======================
+
+crossbar11x11 : if number_of_crossbar_ports = 11 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_In(10) => Port10_in(0),
+       Data_In(11) => Port11_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0),
+       Data_out(10)=> Port10_out(0),
+       Data_out(11)=> Port11_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_In(10) => Port10_in(1),
+       Data_In(11) => Port11_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1),
+       Data_out(10)=> Port10_out(1),
+       Data_out(11)=> Port11_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_In(10) => Port10_in(2),
+       Data_In(11) => Port11_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2),
+       Data_out(10)=> Port10_out(2),
+       Data_out(11)=> Port11_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_In(10) => Port10_in(3),
+       Data_In(11) => Port11_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3),
+       Data_out(10)=> Port10_out(3),
+       Data_out(11)=> Port11_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_In(10) => Port10_in(4),
+       Data_In(11) => Port11_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4),
+       Data_out(10)=> Port10_out(4),
+       Data_out(11)=> Port11_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_In(10) => Port10_in(5),
+       Data_In(11) => Port11_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5),
+       Data_out(10)=> Port10_out(5),
+       Data_out(11)=> Port11_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_In(10) => Port10_in(6),
+       Data_In(11) => Port11_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6),
+       Data_out(10)=> Port10_out(6),
+       Data_out(11)=> Port11_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_In(10) => Port10_in(7),
+       Data_In(11) => Port11_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7),
+       Data_out(10)=> Port10_out(7),
+       Data_out(11)=> Port11_out(7)
+
+           );
+-- crossbit du pulse_out 11 ports 
+
+   Pulse_out_Crossbit11: Crossbit 
+      GENERIC MAP(number_of_ports => 11)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_In(10) => Port10_pulse_in,
+       Data_In(11) => Port11_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out,
+       Data_out(10) => Port10_pulse_out,
+       Data_out(11) => Port11_pulse_out 
+
+           );
+end generate crossbar11x11;
+
+
+--======================crossbar 12 ports=======================
+
+crossbar12x12 : if number_of_crossbar_ports = 12 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_In(10) => Port10_in(0),
+       Data_In(11) => Port11_in(0),
+       Data_In(12) => Port12_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0),
+       Data_out(10)=> Port10_out(0),
+       Data_out(11)=> Port11_out(0),
+       Data_out(12)=> Port12_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_In(10) => Port10_in(1),
+       Data_In(11) => Port11_in(1),
+       Data_In(12) => Port12_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1),
+       Data_out(10)=> Port10_out(1),
+       Data_out(11)=> Port11_out(1),
+       Data_out(12)=> Port12_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_In(10) => Port10_in(2),
+       Data_In(11) => Port11_in(2),
+       Data_In(12) => Port12_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2),
+       Data_out(10)=> Port10_out(2),
+       Data_out(11)=> Port11_out(2),
+       Data_out(12)=> Port12_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_In(10) => Port10_in(3),
+       Data_In(11) => Port11_in(3),
+       Data_In(12) => Port12_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3),
+       Data_out(10)=> Port10_out(3),
+       Data_out(11)=> Port11_out(3),
+       Data_out(12)=> Port12_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_In(10) => Port10_in(4),
+       Data_In(11) => Port11_in(4),
+       Data_In(12) => Port12_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4),
+       Data_out(10)=> Port10_out(4),
+       Data_out(11)=> Port11_out(4),
+       Data_out(12)=> Port12_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_In(10) => Port10_in(5),
+       Data_In(11) => Port11_in(5),
+       Data_In(12) => Port12_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5),
+       Data_out(10)=> Port10_out(5),
+       Data_out(11)=> Port11_out(5),
+       Data_out(12)=> Port12_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_In(10) => Port10_in(6),
+       Data_In(11) => Port11_in(6),
+       Data_In(12) => Port12_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6),
+       Data_out(10)=> Port10_out(6),
+       Data_out(11)=> Port11_out(6),
+       Data_out(12)=> Port12_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_In(10) => Port10_in(7),
+       Data_In(11) => Port11_in(7),
+       Data_In(12) => Port12_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7),
+       Data_out(10)=> Port10_out(7),
+       Data_out(11)=> Port11_out(7),
+       Data_out(12)=> Port12_out(7)
+
+           );
+-- crossbit du pulse_out 12 ports 
+
+   Pulse_out_Crossbit12: Crossbit 
+      GENERIC MAP(number_of_ports => 12)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_In(10) => Port10_pulse_in,
+       Data_In(11) => Port11_pulse_in,
+       Data_In(12) => Port12_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out,
+       Data_out(10) => Port10_pulse_out,
+       Data_out(11) => Port11_pulse_out,
+       Data_out(12) => Port12_pulse_out 
+
+           );
+end generate crossbar12x12;
+
+
+--======================crossbar 13 ports=======================
+
+crossbar13x13 : if number_of_crossbar_ports = 13 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_In(10) => Port10_in(0),
+       Data_In(11) => Port11_in(0),
+       Data_In(12) => Port12_in(0),
+       Data_In(13) => Port13_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0),
+       Data_out(10)=> Port10_out(0),
+       Data_out(11)=> Port11_out(0),
+       Data_out(12)=> Port12_out(0),
+       Data_out(13)=> Port13_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_In(10) => Port10_in(1),
+       Data_In(11) => Port11_in(1),
+       Data_In(12) => Port12_in(1),
+       Data_In(13) => Port13_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1),
+       Data_out(10)=> Port10_out(1),
+       Data_out(11)=> Port11_out(1),
+       Data_out(12)=> Port12_out(1),
+       Data_out(13)=> Port13_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_In(10) => Port10_in(2),
+       Data_In(11) => Port11_in(2),
+       Data_In(12) => Port12_in(2),
+       Data_In(13) => Port13_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2),
+       Data_out(10)=> Port10_out(2),
+       Data_out(11)=> Port11_out(2),
+       Data_out(12)=> Port12_out(2),
+       Data_out(13)=> Port13_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_In(10) => Port10_in(3),
+       Data_In(11) => Port11_in(3),
+       Data_In(12) => Port12_in(3),
+       Data_In(13) => Port13_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3),
+       Data_out(10)=> Port10_out(3),
+       Data_out(11)=> Port11_out(3),
+       Data_out(12)=> Port12_out(3),
+       Data_out(13)=> Port13_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_In(10) => Port10_in(4),
+       Data_In(11) => Port11_in(4),
+       Data_In(12) => Port12_in(4),
+       Data_In(13) => Port13_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4),
+       Data_out(10)=> Port10_out(4),
+       Data_out(11)=> Port11_out(4),
+       Data_out(12)=> Port12_out(4),
+       Data_out(13)=> Port13_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_In(10) => Port10_in(5),
+       Data_In(11) => Port11_in(5),
+       Data_In(12) => Port12_in(5),
+       Data_In(13) => Port13_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5),
+       Data_out(10)=> Port10_out(5),
+       Data_out(11)=> Port11_out(5),
+       Data_out(12)=> Port12_out(5),
+       Data_out(13)=> Port13_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_In(10) => Port10_in(6),
+       Data_In(11) => Port11_in(6),
+       Data_In(12) => Port12_in(6),
+       Data_In(13) => Port13_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6),
+       Data_out(10)=> Port10_out(6),
+       Data_out(11)=> Port11_out(6),
+       Data_out(12)=> Port12_out(6),
+       Data_out(13)=> Port13_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_In(10) => Port10_in(7),
+       Data_In(11) => Port11_in(7),
+       Data_In(12) => Port12_in(7),
+       Data_In(13) => Port13_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7),
+       Data_out(10)=> Port10_out(7),
+       Data_out(11)=> Port11_out(7),
+       Data_out(12)=> Port12_out(7),
+       Data_out(13)=> Port13_out(7)
+
+           );
+-- crossbit du pulse_out 13 ports 
+
+   Pulse_out_Crossbit13: Crossbit 
+      GENERIC MAP(number_of_ports => 13)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_In(10) => Port10_pulse_in,
+       Data_In(11) => Port11_pulse_in,
+       Data_In(12) => Port12_pulse_in,
+       Data_In(13) => Port13_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out,
+       Data_out(10) => Port10_pulse_out,
+       Data_out(11) => Port11_pulse_out,
+       Data_out(12) => Port12_pulse_out,
+       Data_out(13) => Port13_pulse_out 
+
+           );
+end generate crossbar13x13;
+
+
+--======================crossbar 14 ports=======================
+
+crossbar14x14 : if number_of_crossbar_ports = 14 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_In(10) => Port10_in(0),
+       Data_In(11) => Port11_in(0),
+       Data_In(12) => Port12_in(0),
+       Data_In(13) => Port13_in(0),
+       Data_In(14) => Port14_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0),
+       Data_out(10)=> Port10_out(0),
+       Data_out(11)=> Port11_out(0),
+       Data_out(12)=> Port12_out(0),
+       Data_out(13)=> Port13_out(0),
+       Data_out(14)=> Port14_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_In(10) => Port10_in(1),
+       Data_In(11) => Port11_in(1),
+       Data_In(12) => Port12_in(1),
+       Data_In(13) => Port13_in(1),
+       Data_In(14) => Port14_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1),
+       Data_out(10)=> Port10_out(1),
+       Data_out(11)=> Port11_out(1),
+       Data_out(12)=> Port12_out(1),
+       Data_out(13)=> Port13_out(1),
+       Data_out(14)=> Port14_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_In(10) => Port10_in(2),
+       Data_In(11) => Port11_in(2),
+       Data_In(12) => Port12_in(2),
+       Data_In(13) => Port13_in(2),
+       Data_In(14) => Port14_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2),
+       Data_out(10)=> Port10_out(2),
+       Data_out(11)=> Port11_out(2),
+       Data_out(12)=> Port12_out(2),
+       Data_out(13)=> Port13_out(2),
+       Data_out(14)=> Port14_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_In(10) => Port10_in(3),
+       Data_In(11) => Port11_in(3),
+       Data_In(12) => Port12_in(3),
+       Data_In(13) => Port13_in(3),
+       Data_In(14) => Port14_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3),
+       Data_out(10)=> Port10_out(3),
+       Data_out(11)=> Port11_out(3),
+       Data_out(12)=> Port12_out(3),
+       Data_out(13)=> Port13_out(3),
+       Data_out(14)=> Port14_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_In(10) => Port10_in(4),
+       Data_In(11) => Port11_in(4),
+       Data_In(12) => Port12_in(4),
+       Data_In(13) => Port13_in(4),
+       Data_In(14) => Port14_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4),
+       Data_out(10)=> Port10_out(4),
+       Data_out(11)=> Port11_out(4),
+       Data_out(12)=> Port12_out(4),
+       Data_out(13)=> Port13_out(4),
+       Data_out(14)=> Port14_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_In(10) => Port10_in(5),
+       Data_In(11) => Port11_in(5),
+       Data_In(12) => Port12_in(5),
+       Data_In(13) => Port13_in(5),
+       Data_In(14) => Port14_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5),
+       Data_out(10)=> Port10_out(5),
+       Data_out(11)=> Port11_out(5),
+       Data_out(12)=> Port12_out(5),
+       Data_out(13)=> Port13_out(5),
+       Data_out(14)=> Port14_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_In(10) => Port10_in(6),
+       Data_In(11) => Port11_in(6),
+       Data_In(12) => Port12_in(6),
+       Data_In(13) => Port13_in(6),
+       Data_In(14) => Port14_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6),
+       Data_out(10)=> Port10_out(6),
+       Data_out(11)=> Port11_out(6),
+       Data_out(12)=> Port12_out(6),
+       Data_out(13)=> Port13_out(6),
+       Data_out(14)=> Port14_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_In(10) => Port10_in(7),
+       Data_In(11) => Port11_in(7),
+       Data_In(12) => Port12_in(7),
+       Data_In(13) => Port13_in(7),
+       Data_In(14) => Port14_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7),
+       Data_out(10)=> Port10_out(7),
+       Data_out(11)=> Port11_out(7),
+       Data_out(12)=> Port12_out(7),
+       Data_out(13)=> Port13_out(7),
+       Data_out(14)=> Port14_out(7)
+
+           );
+-- crossbit du pulse_out 14 ports 
+
+   Pulse_out_Crossbit14: Crossbit 
+      GENERIC MAP(number_of_ports => 14)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_In(10) => Port10_pulse_in,
+       Data_In(11) => Port11_pulse_in,
+       Data_In(12) => Port12_pulse_in,
+       Data_In(13) => Port13_pulse_in,
+       Data_In(14) => Port14_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out,
+       Data_out(10) => Port10_pulse_out,
+       Data_out(11) => Port11_pulse_out,
+       Data_out(12) => Port12_pulse_out,
+       Data_out(13) => Port13_pulse_out,
+       Data_out(14) => Port14_pulse_out 
+
+           );
+end generate crossbar14x14;
+
+
+--======================crossbar 15 ports=======================
+
+crossbar15x15 : if number_of_crossbar_ports = 15 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_In(10) => Port10_in(0),
+       Data_In(11) => Port11_in(0),
+       Data_In(12) => Port12_in(0),
+       Data_In(13) => Port13_in(0),
+       Data_In(14) => Port14_in(0),
+       Data_In(15) => Port15_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0),
+       Data_out(10)=> Port10_out(0),
+       Data_out(11)=> Port11_out(0),
+       Data_out(12)=> Port12_out(0),
+       Data_out(13)=> Port13_out(0),
+       Data_out(14)=> Port14_out(0),
+       Data_out(15)=> Port15_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_In(10) => Port10_in(1),
+       Data_In(11) => Port11_in(1),
+       Data_In(12) => Port12_in(1),
+       Data_In(13) => Port13_in(1),
+       Data_In(14) => Port14_in(1),
+       Data_In(15) => Port15_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1),
+       Data_out(10)=> Port10_out(1),
+       Data_out(11)=> Port11_out(1),
+       Data_out(12)=> Port12_out(1),
+       Data_out(13)=> Port13_out(1),
+       Data_out(14)=> Port14_out(1),
+       Data_out(15)=> Port15_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_In(10) => Port10_in(2),
+       Data_In(11) => Port11_in(2),
+       Data_In(12) => Port12_in(2),
+       Data_In(13) => Port13_in(2),
+       Data_In(14) => Port14_in(2),
+       Data_In(15) => Port15_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2),
+       Data_out(10)=> Port10_out(2),
+       Data_out(11)=> Port11_out(2),
+       Data_out(12)=> Port12_out(2),
+       Data_out(13)=> Port13_out(2),
+       Data_out(14)=> Port14_out(2),
+       Data_out(15)=> Port15_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_In(10) => Port10_in(3),
+       Data_In(11) => Port11_in(3),
+       Data_In(12) => Port12_in(3),
+       Data_In(13) => Port13_in(3),
+       Data_In(14) => Port14_in(3),
+       Data_In(15) => Port15_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3),
+       Data_out(10)=> Port10_out(3),
+       Data_out(11)=> Port11_out(3),
+       Data_out(12)=> Port12_out(3),
+       Data_out(13)=> Port13_out(3),
+       Data_out(14)=> Port14_out(3),
+       Data_out(15)=> Port15_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_In(10) => Port10_in(4),
+       Data_In(11) => Port11_in(4),
+       Data_In(12) => Port12_in(4),
+       Data_In(13) => Port13_in(4),
+       Data_In(14) => Port14_in(4),
+       Data_In(15) => Port15_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4),
+       Data_out(10)=> Port10_out(4),
+       Data_out(11)=> Port11_out(4),
+       Data_out(12)=> Port12_out(4),
+       Data_out(13)=> Port13_out(4),
+       Data_out(14)=> Port14_out(4),
+       Data_out(15)=> Port15_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_In(10) => Port10_in(5),
+       Data_In(11) => Port11_in(5),
+       Data_In(12) => Port12_in(5),
+       Data_In(13) => Port13_in(5),
+       Data_In(14) => Port14_in(5),
+       Data_In(15) => Port15_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5),
+       Data_out(10)=> Port10_out(5),
+       Data_out(11)=> Port11_out(5),
+       Data_out(12)=> Port12_out(5),
+       Data_out(13)=> Port13_out(5),
+       Data_out(14)=> Port14_out(5),
+       Data_out(15)=> Port15_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_In(10) => Port10_in(6),
+       Data_In(11) => Port11_in(6),
+       Data_In(12) => Port12_in(6),
+       Data_In(13) => Port13_in(6),
+       Data_In(14) => Port14_in(6),
+       Data_In(15) => Port15_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6),
+       Data_out(10)=> Port10_out(6),
+       Data_out(11)=> Port11_out(6),
+       Data_out(12)=> Port12_out(6),
+       Data_out(13)=> Port13_out(6),
+       Data_out(14)=> Port14_out(6),
+       Data_out(15)=> Port15_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_In(10) => Port10_in(7),
+       Data_In(11) => Port11_in(7),
+       Data_In(12) => Port12_in(7),
+       Data_In(13) => Port13_in(7),
+       Data_In(14) => Port14_in(7),
+       Data_In(15) => Port15_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7),
+       Data_out(10)=> Port10_out(7),
+       Data_out(11)=> Port11_out(7),
+       Data_out(12)=> Port12_out(7),
+       Data_out(13)=> Port13_out(7),
+       Data_out(14)=> Port14_out(7),
+       Data_out(15)=> Port15_out(7)
+
+           );
+-- crossbit du pulse_out 15 ports 
+
+   Pulse_out_Crossbit15: Crossbit 
+      GENERIC MAP(number_of_ports => 15)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_In(10) => Port10_pulse_in,
+       Data_In(11) => Port11_pulse_in,
+       Data_In(12) => Port12_pulse_in,
+       Data_In(13) => Port13_pulse_in,
+       Data_In(14) => Port14_pulse_in,
+       Data_In(15) => Port15_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out,
+       Data_out(10) => Port10_pulse_out,
+       Data_out(11) => Port11_pulse_out,
+       Data_out(12) => Port12_pulse_out,
+       Data_out(13) => Port13_pulse_out,
+       Data_out(14) => Port14_pulse_out,
+       Data_out(15) => Port15_pulse_out 
+
+           );
+end generate crossbar15x15;
+
+
+--======================crossbar 16 ports=======================
+
+crossbar16x16 : if number_of_crossbar_ports = 16 generate
+
+-- crossbit du bit 0 de donnée
+
+   Data0_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(0),
+       Data_In(2) => Port2_in(0),
+       Data_In(3) => Port3_in(0),
+       Data_In(4) => Port4_in(0),
+       Data_In(5) => Port5_in(0),
+       Data_In(6) => Port6_in(0),
+       Data_In(7) => Port7_in(0),
+       Data_In(8) => Port8_in(0),
+       Data_In(9) => Port9_in(0),
+       Data_In(10) => Port10_in(0),
+       Data_In(11) => Port11_in(0),
+       Data_In(12) => Port12_in(0),
+       Data_In(13) => Port13_in(0),
+       Data_In(14) => Port14_in(0),
+       Data_In(15) => Port15_in(0),
+       Data_In(16) => Port16_in(0),
+       Data_out(1)=> Port1_out(0),
+       Data_out(2)=> Port2_out(0),
+       Data_out(3)=> Port3_out(0),
+       Data_out(4)=> Port4_out(0),
+       Data_out(5)=> Port5_out(0),
+       Data_out(6)=> Port6_out(0),
+       Data_out(7)=> Port7_out(0),
+       Data_out(8)=> Port8_out(0),
+       Data_out(9)=> Port9_out(0),
+       Data_out(10)=> Port10_out(0),
+       Data_out(11)=> Port11_out(0),
+       Data_out(12)=> Port12_out(0),
+       Data_out(13)=> Port13_out(0),
+       Data_out(14)=> Port14_out(0),
+       Data_out(15)=> Port15_out(0),
+       Data_out(16)=> Port16_out(0)
+
+           );
+-- crossbit du bit 1 de donnée
+
+   Data1_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(1),
+       Data_In(2) => Port2_in(1),
+       Data_In(3) => Port3_in(1),
+       Data_In(4) => Port4_in(1),
+       Data_In(5) => Port5_in(1),
+       Data_In(6) => Port6_in(1),
+       Data_In(7) => Port7_in(1),
+       Data_In(8) => Port8_in(1),
+       Data_In(9) => Port9_in(1),
+       Data_In(10) => Port10_in(1),
+       Data_In(11) => Port11_in(1),
+       Data_In(12) => Port12_in(1),
+       Data_In(13) => Port13_in(1),
+       Data_In(14) => Port14_in(1),
+       Data_In(15) => Port15_in(1),
+       Data_In(16) => Port16_in(1),
+       Data_out(1)=> Port1_out(1),
+       Data_out(2)=> Port2_out(1),
+       Data_out(3)=> Port3_out(1),
+       Data_out(4)=> Port4_out(1),
+       Data_out(5)=> Port5_out(1),
+       Data_out(6)=> Port6_out(1),
+       Data_out(7)=> Port7_out(1),
+       Data_out(8)=> Port8_out(1),
+       Data_out(9)=> Port9_out(1),
+       Data_out(10)=> Port10_out(1),
+       Data_out(11)=> Port11_out(1),
+       Data_out(12)=> Port12_out(1),
+       Data_out(13)=> Port13_out(1),
+       Data_out(14)=> Port14_out(1),
+       Data_out(15)=> Port15_out(1),
+       Data_out(16)=> Port16_out(1)
+
+           );
+-- crossbit du bit 2 de donnée
+
+   Data2_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(2),
+       Data_In(2) => Port2_in(2),
+       Data_In(3) => Port3_in(2),
+       Data_In(4) => Port4_in(2),
+       Data_In(5) => Port5_in(2),
+       Data_In(6) => Port6_in(2),
+       Data_In(7) => Port7_in(2),
+       Data_In(8) => Port8_in(2),
+       Data_In(9) => Port9_in(2),
+       Data_In(10) => Port10_in(2),
+       Data_In(11) => Port11_in(2),
+       Data_In(12) => Port12_in(2),
+       Data_In(13) => Port13_in(2),
+       Data_In(14) => Port14_in(2),
+       Data_In(15) => Port15_in(2),
+       Data_In(16) => Port16_in(2),
+       Data_out(1)=> Port1_out(2),
+       Data_out(2)=> Port2_out(2),
+       Data_out(3)=> Port3_out(2),
+       Data_out(4)=> Port4_out(2),
+       Data_out(5)=> Port5_out(2),
+       Data_out(6)=> Port6_out(2),
+       Data_out(7)=> Port7_out(2),
+       Data_out(8)=> Port8_out(2),
+       Data_out(9)=> Port9_out(2),
+       Data_out(10)=> Port10_out(2),
+       Data_out(11)=> Port11_out(2),
+       Data_out(12)=> Port12_out(2),
+       Data_out(13)=> Port13_out(2),
+       Data_out(14)=> Port14_out(2),
+       Data_out(15)=> Port15_out(2),
+       Data_out(16)=> Port16_out(2)
+
+           );
+-- crossbit du bit 3 de donnée
+
+   Data3_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(3),
+       Data_In(2) => Port2_in(3),
+       Data_In(3) => Port3_in(3),
+       Data_In(4) => Port4_in(3),
+       Data_In(5) => Port5_in(3),
+       Data_In(6) => Port6_in(3),
+       Data_In(7) => Port7_in(3),
+       Data_In(8) => Port8_in(3),
+       Data_In(9) => Port9_in(3),
+       Data_In(10) => Port10_in(3),
+       Data_In(11) => Port11_in(3),
+       Data_In(12) => Port12_in(3),
+       Data_In(13) => Port13_in(3),
+       Data_In(14) => Port14_in(3),
+       Data_In(15) => Port15_in(3),
+       Data_In(16) => Port16_in(3),
+       Data_out(1)=> Port1_out(3),
+       Data_out(2)=> Port2_out(3),
+       Data_out(3)=> Port3_out(3),
+       Data_out(4)=> Port4_out(3),
+       Data_out(5)=> Port5_out(3),
+       Data_out(6)=> Port6_out(3),
+       Data_out(7)=> Port7_out(3),
+       Data_out(8)=> Port8_out(3),
+       Data_out(9)=> Port9_out(3),
+       Data_out(10)=> Port10_out(3),
+       Data_out(11)=> Port11_out(3),
+       Data_out(12)=> Port12_out(3),
+       Data_out(13)=> Port13_out(3),
+       Data_out(14)=> Port14_out(3),
+       Data_out(15)=> Port15_out(3),
+       Data_out(16)=> Port16_out(3)
+
+           );
+-- crossbit du bit 4 de donnée
+
+   Data4_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(4),
+       Data_In(2) => Port2_in(4),
+       Data_In(3) => Port3_in(4),
+       Data_In(4) => Port4_in(4),
+       Data_In(5) => Port5_in(4),
+       Data_In(6) => Port6_in(4),
+       Data_In(7) => Port7_in(4),
+       Data_In(8) => Port8_in(4),
+       Data_In(9) => Port9_in(4),
+       Data_In(10) => Port10_in(4),
+       Data_In(11) => Port11_in(4),
+       Data_In(12) => Port12_in(4),
+       Data_In(13) => Port13_in(4),
+       Data_In(14) => Port14_in(4),
+       Data_In(15) => Port15_in(4),
+       Data_In(16) => Port16_in(4),
+       Data_out(1)=> Port1_out(4),
+       Data_out(2)=> Port2_out(4),
+       Data_out(3)=> Port3_out(4),
+       Data_out(4)=> Port4_out(4),
+       Data_out(5)=> Port5_out(4),
+       Data_out(6)=> Port6_out(4),
+       Data_out(7)=> Port7_out(4),
+       Data_out(8)=> Port8_out(4),
+       Data_out(9)=> Port9_out(4),
+       Data_out(10)=> Port10_out(4),
+       Data_out(11)=> Port11_out(4),
+       Data_out(12)=> Port12_out(4),
+       Data_out(13)=> Port13_out(4),
+       Data_out(14)=> Port14_out(4),
+       Data_out(15)=> Port15_out(4),
+       Data_out(16)=> Port16_out(4)
+
+           );
+-- crossbit du bit 5 de donnée
+
+   Data5_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(5),
+       Data_In(2) => Port2_in(5),
+       Data_In(3) => Port3_in(5),
+       Data_In(4) => Port4_in(5),
+       Data_In(5) => Port5_in(5),
+       Data_In(6) => Port6_in(5),
+       Data_In(7) => Port7_in(5),
+       Data_In(8) => Port8_in(5),
+       Data_In(9) => Port9_in(5),
+       Data_In(10) => Port10_in(5),
+       Data_In(11) => Port11_in(5),
+       Data_In(12) => Port12_in(5),
+       Data_In(13) => Port13_in(5),
+       Data_In(14) => Port14_in(5),
+       Data_In(15) => Port15_in(5),
+       Data_In(16) => Port16_in(5),
+       Data_out(1)=> Port1_out(5),
+       Data_out(2)=> Port2_out(5),
+       Data_out(3)=> Port3_out(5),
+       Data_out(4)=> Port4_out(5),
+       Data_out(5)=> Port5_out(5),
+       Data_out(6)=> Port6_out(5),
+       Data_out(7)=> Port7_out(5),
+       Data_out(8)=> Port8_out(5),
+       Data_out(9)=> Port9_out(5),
+       Data_out(10)=> Port10_out(5),
+       Data_out(11)=> Port11_out(5),
+       Data_out(12)=> Port12_out(5),
+       Data_out(13)=> Port13_out(5),
+       Data_out(14)=> Port14_out(5),
+       Data_out(15)=> Port15_out(5),
+       Data_out(16)=> Port16_out(5)
+
+           );
+-- crossbit du bit 6 de donnée
+
+   Data6_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(6),
+       Data_In(2) => Port2_in(6),
+       Data_In(3) => Port3_in(6),
+       Data_In(4) => Port4_in(6),
+       Data_In(5) => Port5_in(6),
+       Data_In(6) => Port6_in(6),
+       Data_In(7) => Port7_in(6),
+       Data_In(8) => Port8_in(6),
+       Data_In(9) => Port9_in(6),
+       Data_In(10) => Port10_in(6),
+       Data_In(11) => Port11_in(6),
+       Data_In(12) => Port12_in(6),
+       Data_In(13) => Port13_in(6),
+       Data_In(14) => Port14_in(6),
+       Data_In(15) => Port15_in(6),
+       Data_In(16) => Port16_in(6),
+       Data_out(1)=> Port1_out(6),
+       Data_out(2)=> Port2_out(6),
+       Data_out(3)=> Port3_out(6),
+       Data_out(4)=> Port4_out(6),
+       Data_out(5)=> Port5_out(6),
+       Data_out(6)=> Port6_out(6),
+       Data_out(7)=> Port7_out(6),
+       Data_out(8)=> Port8_out(6),
+       Data_out(9)=> Port9_out(6),
+       Data_out(10)=> Port10_out(6),
+       Data_out(11)=> Port11_out(6),
+       Data_out(12)=> Port12_out(6),
+       Data_out(13)=> Port13_out(6),
+       Data_out(14)=> Port14_out(6),
+       Data_out(15)=> Port15_out(6),
+       Data_out(16)=> Port16_out(6)
+
+           );
+-- crossbit du bit 7 de donnée
+
+   Data7_Crossbit: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_in(7),
+       Data_In(2) => Port2_in(7),
+       Data_In(3) => Port3_in(7),
+       Data_In(4) => Port4_in(7),
+       Data_In(5) => Port5_in(7),
+       Data_In(6) => Port6_in(7),
+       Data_In(7) => Port7_in(7),
+       Data_In(8) => Port8_in(7),
+       Data_In(9) => Port9_in(7),
+       Data_In(10) => Port10_in(7),
+       Data_In(11) => Port11_in(7),
+       Data_In(12) => Port12_in(7),
+       Data_In(13) => Port13_in(7),
+       Data_In(14) => Port14_in(7),
+       Data_In(15) => Port15_in(7),
+       Data_In(16) => Port16_in(7),
+       Data_out(1)=> Port1_out(7),
+       Data_out(2)=> Port2_out(7),
+       Data_out(3)=> Port3_out(7),
+       Data_out(4)=> Port4_out(7),
+       Data_out(5)=> Port5_out(7),
+       Data_out(6)=> Port6_out(7),
+       Data_out(7)=> Port7_out(7),
+       Data_out(8)=> Port8_out(7),
+       Data_out(9)=> Port9_out(7),
+       Data_out(10)=> Port10_out(7),
+       Data_out(11)=> Port11_out(7),
+       Data_out(12)=> Port12_out(7),
+       Data_out(13)=> Port13_out(7),
+       Data_out(14)=> Port14_out(7),
+       Data_out(15)=> Port15_out(7),
+       Data_out(16)=> Port16_out(7)
+
+           );
+-- crossbit du pulse_out 16 ports 
+
+   Pulse_out_Crossbit16: Crossbit 
+      GENERIC MAP(number_of_ports => 16)
+      PORT MAP(
+
+      Control => Ctrl,
+       Data_In(1) => Port1_pulse_in,
+       Data_In(2) => Port2_pulse_in,
+       Data_In(3) => Port3_pulse_in,
+       Data_In(4) => Port4_pulse_in,
+       Data_In(5) => Port5_pulse_in,
+       Data_In(6) => Port6_pulse_in,
+       Data_In(7) => Port7_pulse_in,
+       Data_In(8) => Port8_pulse_in,
+       Data_In(9) => Port9_pulse_in,
+       Data_In(10) => Port10_pulse_in,
+       Data_In(11) => Port11_pulse_in,
+       Data_In(12) => Port12_pulse_in,
+       Data_In(13) => Port13_pulse_in,
+       Data_In(14) => Port14_pulse_in,
+       Data_In(15) => Port15_pulse_in,
+       Data_In(16) => Port16_pulse_in,
+       Data_out(1) => Port1_pulse_out,
+       Data_out(2) => Port2_pulse_out,
+       Data_out(3) => Port3_pulse_out,
+       Data_out(4) => Port4_pulse_out,
+       Data_out(5) => Port5_pulse_out,
+       Data_out(6) => Port6_pulse_out,
+       Data_out(7) => Port7_pulse_out,
+       Data_out(8) => Port8_pulse_out,
+       Data_out(9) => Port9_pulse_out,
+       Data_out(10) => Port10_pulse_out,
+       Data_out(11) => Port11_pulse_out,
+       Data_out(12) => Port12_pulse_out,
+       Data_out(13) => Port13_pulse_out,
+       Data_out(14) => Port14_pulse_out,
+       Data_out(15) => Port15_pulse_out,
+       Data_out(16) => Port16_pulse_out 
+
+           );
+end generate crossbar16x16;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Crossbar_summary.html
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Crossbar_summary.html	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Crossbar_summary.html	(revision 20)
@@ -0,0 +1,73 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>GENERIC_16_16 Project Status</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>GENERIC_16_16.ise</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>New</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>Crossbar</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc3s1200e-4fg320</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 11.1</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD>Xilinx Default (unlocked)</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 06/19/2011 - 14:29:40</center>
+</BODY></HTML>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Crossbit.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Crossbit.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Crossbit.vhd	(revision 20)
@@ -0,0 +1,288 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: Kiegaing Emmanuel GEL EN 5
+-- 
+-- Create Date:    01:47 05/06/2011
+-- Design Name: 
+-- Module Name:    Crossbar - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: module implémentant un crosbar d'un bit
+-- ces modules seront instanciés pour faire le switch
+-- module generique
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Crossbit is
+    generic
+	      (
+			  number_of_ports: positive := 4
+			);
+    Port ( Control : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
+			  Data_In : in  STD_LOGIC_VECTOR (number_of_ports downto 1);
+           Data_out : out  STD_LOGIC_VECTOR (number_of_ports downto 1)
+			  );
+end Crossbit;
+
+architecture Behavioral of Crossbit is
+
+begin
+-- element de commutation utilisee dans la matrice interconnecte
+-- le circuit genere depend du parametre generique nombre de ports
+--======================crossbit 2 ports=======================
+
+crossbit2x2 : if number_of_ports = 2 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(3)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(4)));
+end generate crossbit2x2;
+
+
+--======================crossbit 3 ports=======================
+
+crossbit3x3 : if number_of_ports = 3 generate
+
+ 
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(4)) OR (Data_in(3) And Control(7)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(5)) OR (Data_in(3) And Control(8)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(9)));
+end generate crossbit3x3;
+
+
+--======================crossbit 4 ports=======================
+
+crossbit4x4 : if number_of_ports = 4 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(5)) OR (Data_in(3) And Control(9)) OR (Data_in(4) And Control(13)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(10)) OR (Data_in(4) And Control(14)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(11)) OR (Data_in(4) And Control(15)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(12)) OR (Data_in(4) And Control(16)));
+end generate crossbit4x4;
+
+
+--======================crossbit 5 ports=======================
+
+crossbit5x5 : if number_of_ports = 5 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(11)) OR (Data_in(4) And Control(16)) OR (Data_in(5) And Control(21)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(12)) OR (Data_in(4) And Control(17)) OR (Data_in(5) And Control(22)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(13)) OR (Data_in(4) And Control(18)) OR (Data_in(5) And Control(23)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(14)) OR (Data_in(4) And Control(19)) OR (Data_in(5) And Control(24)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(20)) OR (Data_in(5) And Control(25)));
+end generate crossbit5x5;
+
+
+--======================crossbit 6 ports=======================
+
+crossbit6x6 : if number_of_ports = 6 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(13)) OR (Data_in(4) And Control(19)) OR (Data_in(5) And Control(25)) OR (Data_in(6) And Control(31)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(14)) OR (Data_in(4) And Control(20)) OR (Data_in(5) And Control(26)) OR (Data_in(6) And Control(32)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(21)) OR (Data_in(5) And Control(27)) OR (Data_in(6) And Control(33)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(16)) OR (Data_in(4) And Control(22)) OR (Data_in(5) And Control(28)) OR (Data_in(6) And Control(34)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(23)) OR (Data_in(5) And Control(29)) OR (Data_in(6) And Control(35)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(24)) OR (Data_in(5) And Control(30)) OR (Data_in(6) And Control(36)));
+end generate crossbit6x6;
+
+
+--======================crossbit 7 ports=======================
+
+crossbit7x7 : if number_of_ports = 7 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(22)) OR (Data_in(5) And Control(29)) OR (Data_in(6) And Control(36)) OR (Data_in(7) And Control(43)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(16)) OR (Data_in(4) And Control(23)) OR (Data_in(5) And Control(30)) OR (Data_in(6) And Control(37)) OR (Data_in(7) And Control(44)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(24)) OR (Data_in(5) And Control(31)) OR (Data_in(6) And Control(38)) OR (Data_in(7) And Control(45)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(25)) OR (Data_in(5) And Control(32)) OR (Data_in(6) And Control(39)) OR (Data_in(7) And Control(46)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(26)) OR (Data_in(5) And Control(33)) OR (Data_in(6) And Control(40)) OR (Data_in(7) And Control(47)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(27)) OR (Data_in(5) And Control(34)) OR (Data_in(6) And Control(41)) OR (Data_in(7) And Control(48)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(35)) OR (Data_in(6) And Control(42)) OR (Data_in(7) And Control(49)));
+end generate crossbit7x7;
+
+
+--======================crossbit 8 ports=======================
+
+crossbit8x8 : if number_of_ports = 8 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(25)) OR (Data_in(5) And Control(33)) OR (Data_in(6) And Control(41)) OR (Data_in(7) And Control(49)) OR (Data_in(8) And Control(57)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(26)) OR (Data_in(5) And Control(34)) OR (Data_in(6) And Control(42)) OR (Data_in(7) And Control(50)) OR (Data_in(8) And Control(58)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(27)) OR (Data_in(5) And Control(35)) OR (Data_in(6) And Control(43)) OR (Data_in(7) And Control(51)) OR (Data_in(8) And Control(59)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(36)) OR (Data_in(6) And Control(44)) OR (Data_in(7) And Control(52)) OR (Data_in(8) And Control(60)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(29)) OR (Data_in(5) And Control(37)) OR (Data_in(6) And Control(45)) OR (Data_in(7) And Control(53)) OR (Data_in(8) And Control(61)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(30)) OR (Data_in(5) And Control(38)) OR (Data_in(6) And Control(46)) OR (Data_in(7) And Control(54)) OR (Data_in(8) And Control(62)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(39)) OR (Data_in(6) And Control(47)) OR (Data_in(7) And Control(55)) OR (Data_in(8) And Control(63)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(40)) OR (Data_in(6) And Control(48)) OR (Data_in(7) And Control(56)) OR (Data_in(8) And Control(64)));
+end generate crossbit8x8;
+
+
+--======================crossbit 9 ports=======================
+
+crossbit9x9 : if number_of_ports = 9 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(37)) OR (Data_in(6) And Control(46)) OR (Data_in(7) And Control(55)) OR (Data_in(8) And Control(64)) OR (Data_in(9) And Control(73)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(29)) OR (Data_in(5) And Control(38)) OR (Data_in(6) And Control(47)) OR (Data_in(7) And Control(56)) OR (Data_in(8) And Control(65)) OR (Data_in(9) And Control(74)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(30)) OR (Data_in(5) And Control(39)) OR (Data_in(6) And Control(48)) OR (Data_in(7) And Control(57)) OR (Data_in(8) And Control(66)) OR (Data_in(9) And Control(75)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(40)) OR (Data_in(6) And Control(49)) OR (Data_in(7) And Control(58)) OR (Data_in(8) And Control(67)) OR (Data_in(9) And Control(76)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(41)) OR (Data_in(6) And Control(50)) OR (Data_in(7) And Control(59)) OR (Data_in(8) And Control(68)) OR (Data_in(9) And Control(77)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(33)) OR (Data_in(5) And Control(42)) OR (Data_in(6) And Control(51)) OR (Data_in(7) And Control(60)) OR (Data_in(8) And Control(69)) OR (Data_in(9) And Control(78)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(43)) OR (Data_in(6) And Control(52)) OR (Data_in(7) And Control(61)) OR (Data_in(8) And Control(70)) OR (Data_in(9) And Control(79)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(44)) OR (Data_in(6) And Control(53)) OR (Data_in(7) And Control(62)) OR (Data_in(8) And Control(71)) OR (Data_in(9) And Control(80)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(54)) OR (Data_in(7) And Control(63)) OR (Data_in(8) And Control(72)) OR (Data_in(9) And Control(81)));
+end generate crossbit9x9;
+
+
+--======================crossbit 10 ports=======================
+
+crossbit10x10 : if number_of_ports = 10 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(41)) OR (Data_in(6) And Control(51)) OR (Data_in(7) And Control(61)) OR (Data_in(8) And Control(71)) OR (Data_in(9) And Control(81)) OR (Data_in(10) And Control(91)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(42)) OR (Data_in(6) And Control(52)) OR (Data_in(7) And Control(62)) OR (Data_in(8) And Control(72)) OR (Data_in(9) And Control(82)) OR (Data_in(10) And Control(92)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(33)) OR (Data_in(5) And Control(43)) OR (Data_in(6) And Control(53)) OR (Data_in(7) And Control(63)) OR (Data_in(8) And Control(73)) OR (Data_in(9) And Control(83)) OR (Data_in(10) And Control(93)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(44)) OR (Data_in(6) And Control(54)) OR (Data_in(7) And Control(64)) OR (Data_in(8) And Control(74)) OR (Data_in(9) And Control(84)) OR (Data_in(10) And Control(94)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(55)) OR (Data_in(7) And Control(65)) OR (Data_in(8) And Control(75)) OR (Data_in(9) And Control(85)) OR (Data_in(10) And Control(95)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(46)) OR (Data_in(6) And Control(56)) OR (Data_in(7) And Control(66)) OR (Data_in(8) And Control(76)) OR (Data_in(9) And Control(86)) OR (Data_in(10) And Control(96)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(47)) OR (Data_in(6) And Control(57)) OR (Data_in(7) And Control(67)) OR (Data_in(8) And Control(77)) OR (Data_in(9) And Control(87)) OR (Data_in(10) And Control(97)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(48)) OR (Data_in(6) And Control(58)) OR (Data_in(7) And Control(68)) OR (Data_in(8) And Control(78)) OR (Data_in(9) And Control(88)) OR (Data_in(10) And Control(98)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(59)) OR (Data_in(7) And Control(69)) OR (Data_in(8) And Control(79)) OR (Data_in(9) And Control(89)) OR (Data_in(10) And Control(99)));
+  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(60)) OR (Data_in(7) And Control(70)) OR (Data_in(8) And Control(80)) OR (Data_in(9) And Control(90)) OR (Data_in(10) And Control(100)));
+end generate crossbit10x10;
+
+
+--======================crossbit 11 ports=======================
+
+crossbit11x11 : if number_of_ports = 11 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(56)) OR (Data_in(7) And Control(67)) OR (Data_in(8) And Control(78)) OR (Data_in(9) And Control(89)) OR (Data_in(10) And Control(100)) OR (Data_in(11) And Control(111)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(46)) OR (Data_in(6) And Control(57)) OR (Data_in(7) And Control(68)) OR (Data_in(8) And Control(79)) OR (Data_in(9) And Control(90)) OR (Data_in(10) And Control(101)) OR (Data_in(11) And Control(112)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(47)) OR (Data_in(6) And Control(58)) OR (Data_in(7) And Control(69)) OR (Data_in(8) And Control(80)) OR (Data_in(9) And Control(91)) OR (Data_in(10) And Control(102)) OR (Data_in(11) And Control(113)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(48)) OR (Data_in(6) And Control(59)) OR (Data_in(7) And Control(70)) OR (Data_in(8) And Control(81)) OR (Data_in(9) And Control(92)) OR (Data_in(10) And Control(103)) OR (Data_in(11) And Control(114)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(60)) OR (Data_in(7) And Control(71)) OR (Data_in(8) And Control(82)) OR (Data_in(9) And Control(93)) OR (Data_in(10) And Control(104)) OR (Data_in(11) And Control(115)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(61)) OR (Data_in(7) And Control(72)) OR (Data_in(8) And Control(83)) OR (Data_in(9) And Control(94)) OR (Data_in(10) And Control(105)) OR (Data_in(11) And Control(116)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(51)) OR (Data_in(6) And Control(62)) OR (Data_in(7) And Control(73)) OR (Data_in(8) And Control(84)) OR (Data_in(9) And Control(95)) OR (Data_in(10) And Control(106)) OR (Data_in(11) And Control(117)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(52)) OR (Data_in(6) And Control(63)) OR (Data_in(7) And Control(74)) OR (Data_in(8) And Control(85)) OR (Data_in(9) And Control(96)) OR (Data_in(10) And Control(107)) OR (Data_in(11) And Control(118)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(64)) OR (Data_in(7) And Control(75)) OR (Data_in(8) And Control(86)) OR (Data_in(9) And Control(97)) OR (Data_in(10) And Control(108)) OR (Data_in(11) And Control(119)));
+  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(65)) OR (Data_in(7) And Control(76)) OR (Data_in(8) And Control(87)) OR (Data_in(9) And Control(98)) OR (Data_in(10) And Control(109)) OR (Data_in(11) And Control(120)));
+  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(77)) OR (Data_in(8) And Control(88)) OR (Data_in(9) And Control(99)) OR (Data_in(10) And Control(110)) OR (Data_in(11) And Control(121)));
+end generate crossbit11x11;
+
+
+--======================crossbit 12 ports=======================
+
+crossbit12x12 : if number_of_ports = 12 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(61)) OR (Data_in(7) And Control(73)) OR (Data_in(8) And Control(85)) OR (Data_in(9) And Control(97)) OR (Data_in(10) And Control(109)) OR (Data_in(11) And Control(121)) OR (Data_in(12) And Control(133)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(62)) OR (Data_in(7) And Control(74)) OR (Data_in(8) And Control(86)) OR (Data_in(9) And Control(98)) OR (Data_in(10) And Control(110)) OR (Data_in(11) And Control(122)) OR (Data_in(12) And Control(134)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(51)) OR (Data_in(6) And Control(63)) OR (Data_in(7) And Control(75)) OR (Data_in(8) And Control(87)) OR (Data_in(9) And Control(99)) OR (Data_in(10) And Control(111)) OR (Data_in(11) And Control(123)) OR (Data_in(12) And Control(135)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(52)) OR (Data_in(6) And Control(64)) OR (Data_in(7) And Control(76)) OR (Data_in(8) And Control(88)) OR (Data_in(9) And Control(100)) OR (Data_in(10) And Control(112)) OR (Data_in(11) And Control(124)) OR (Data_in(12) And Control(136)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(65)) OR (Data_in(7) And Control(77)) OR (Data_in(8) And Control(89)) OR (Data_in(9) And Control(101)) OR (Data_in(10) And Control(113)) OR (Data_in(11) And Control(125)) OR (Data_in(12) And Control(137)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(78)) OR (Data_in(8) And Control(90)) OR (Data_in(9) And Control(102)) OR (Data_in(10) And Control(114)) OR (Data_in(11) And Control(126)) OR (Data_in(12) And Control(138)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(67)) OR (Data_in(7) And Control(79)) OR (Data_in(8) And Control(91)) OR (Data_in(9) And Control(103)) OR (Data_in(10) And Control(115)) OR (Data_in(11) And Control(127)) OR (Data_in(12) And Control(139)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(56)) OR (Data_in(6) And Control(68)) OR (Data_in(7) And Control(80)) OR (Data_in(8) And Control(92)) OR (Data_in(9) And Control(104)) OR (Data_in(10) And Control(116)) OR (Data_in(11) And Control(128)) OR (Data_in(12) And Control(140)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(69)) OR (Data_in(7) And Control(81)) OR (Data_in(8) And Control(93)) OR (Data_in(9) And Control(105)) OR (Data_in(10) And Control(117)) OR (Data_in(11) And Control(129)) OR (Data_in(12) And Control(141)));
+  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(70)) OR (Data_in(7) And Control(82)) OR (Data_in(8) And Control(94)) OR (Data_in(9) And Control(106)) OR (Data_in(10) And Control(118)) OR (Data_in(11) And Control(130)) OR (Data_in(12) And Control(142)));
+  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(83)) OR (Data_in(8) And Control(95)) OR (Data_in(9) And Control(107)) OR (Data_in(10) And Control(119)) OR (Data_in(11) And Control(131)) OR (Data_in(12) And Control(143)));
+  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(84)) OR (Data_in(8) And Control(96)) OR (Data_in(9) And Control(108)) OR (Data_in(10) And Control(120)) OR (Data_in(11) And Control(132)) OR (Data_in(12) And Control(144)));
+end generate crossbit12x12;
+
+
+--======================crossbit 13 ports=======================
+
+crossbit13x13 : if number_of_ports = 13 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(79)) OR (Data_in(8) And Control(92)) OR (Data_in(9) And Control(105)) OR (Data_in(10) And Control(118)) OR (Data_in(11) And Control(131)) OR (Data_in(12) And Control(144)) OR (Data_in(13) And Control(157)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(67)) OR (Data_in(7) And Control(80)) OR (Data_in(8) And Control(93)) OR (Data_in(9) And Control(106)) OR (Data_in(10) And Control(119)) OR (Data_in(11) And Control(132)) OR (Data_in(12) And Control(145)) OR (Data_in(13) And Control(158)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(68)) OR (Data_in(7) And Control(81)) OR (Data_in(8) And Control(94)) OR (Data_in(9) And Control(107)) OR (Data_in(10) And Control(120)) OR (Data_in(11) And Control(133)) OR (Data_in(12) And Control(146)) OR (Data_in(13) And Control(159)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(56)) OR (Data_in(6) And Control(69)) OR (Data_in(7) And Control(82)) OR (Data_in(8) And Control(95)) OR (Data_in(9) And Control(108)) OR (Data_in(10) And Control(121)) OR (Data_in(11) And Control(134)) OR (Data_in(12) And Control(147)) OR (Data_in(13) And Control(160)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(70)) OR (Data_in(7) And Control(83)) OR (Data_in(8) And Control(96)) OR (Data_in(9) And Control(109)) OR (Data_in(10) And Control(122)) OR (Data_in(11) And Control(135)) OR (Data_in(12) And Control(148)) OR (Data_in(13) And Control(161)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(84)) OR (Data_in(8) And Control(97)) OR (Data_in(9) And Control(110)) OR (Data_in(10) And Control(123)) OR (Data_in(11) And Control(136)) OR (Data_in(12) And Control(149)) OR (Data_in(13) And Control(162)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(85)) OR (Data_in(8) And Control(98)) OR (Data_in(9) And Control(111)) OR (Data_in(10) And Control(124)) OR (Data_in(11) And Control(137)) OR (Data_in(12) And Control(150)) OR (Data_in(13) And Control(163)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(73)) OR (Data_in(7) And Control(86)) OR (Data_in(8) And Control(99)) OR (Data_in(9) And Control(112)) OR (Data_in(10) And Control(125)) OR (Data_in(11) And Control(138)) OR (Data_in(12) And Control(151)) OR (Data_in(13) And Control(164)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(74)) OR (Data_in(7) And Control(87)) OR (Data_in(8) And Control(100)) OR (Data_in(9) And Control(113)) OR (Data_in(10) And Control(126)) OR (Data_in(11) And Control(139)) OR (Data_in(12) And Control(152)) OR (Data_in(13) And Control(165)));
+  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(75)) OR (Data_in(7) And Control(88)) OR (Data_in(8) And Control(101)) OR (Data_in(9) And Control(114)) OR (Data_in(10) And Control(127)) OR (Data_in(11) And Control(140)) OR (Data_in(12) And Control(153)) OR (Data_in(13) And Control(166)));
+  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(89)) OR (Data_in(8) And Control(102)) OR (Data_in(9) And Control(115)) OR (Data_in(10) And Control(128)) OR (Data_in(11) And Control(141)) OR (Data_in(12) And Control(154)) OR (Data_in(13) And Control(167)));
+  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(90)) OR (Data_in(8) And Control(103)) OR (Data_in(9) And Control(116)) OR (Data_in(10) And Control(129)) OR (Data_in(11) And Control(142)) OR (Data_in(12) And Control(155)) OR (Data_in(13) And Control(168)));
+  Data_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(104)) OR (Data_in(9) And Control(117)) OR (Data_in(10) And Control(130)) OR (Data_in(11) And Control(143)) OR (Data_in(12) And Control(156)) OR (Data_in(13) And Control(169)));
+end generate crossbit13x13;
+
+
+--======================crossbit 14 ports=======================
+
+crossbit14x14 : if number_of_ports = 14 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(85)) OR (Data_in(8) And Control(99)) OR (Data_in(9) And Control(113)) OR (Data_in(10) And Control(127)) OR (Data_in(11) And Control(141)) OR (Data_in(12) And Control(155)) OR (Data_in(13) And Control(169)) OR (Data_in(14) And Control(183)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(86)) OR (Data_in(8) And Control(100)) OR (Data_in(9) And Control(114)) OR (Data_in(10) And Control(128)) OR (Data_in(11) And Control(142)) OR (Data_in(12) And Control(156)) OR (Data_in(13) And Control(170)) OR (Data_in(14) And Control(184)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(73)) OR (Data_in(7) And Control(87)) OR (Data_in(8) And Control(101)) OR (Data_in(9) And Control(115)) OR (Data_in(10) And Control(129)) OR (Data_in(11) And Control(143)) OR (Data_in(12) And Control(157)) OR (Data_in(13) And Control(171)) OR (Data_in(14) And Control(185)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(74)) OR (Data_in(7) And Control(88)) OR (Data_in(8) And Control(102)) OR (Data_in(9) And Control(116)) OR (Data_in(10) And Control(130)) OR (Data_in(11) And Control(144)) OR (Data_in(12) And Control(158)) OR (Data_in(13) And Control(172)) OR (Data_in(14) And Control(186)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(75)) OR (Data_in(7) And Control(89)) OR (Data_in(8) And Control(103)) OR (Data_in(9) And Control(117)) OR (Data_in(10) And Control(131)) OR (Data_in(11) And Control(145)) OR (Data_in(12) And Control(159)) OR (Data_in(13) And Control(173)) OR (Data_in(14) And Control(187)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(90)) OR (Data_in(8) And Control(104)) OR (Data_in(9) And Control(118)) OR (Data_in(10) And Control(132)) OR (Data_in(11) And Control(146)) OR (Data_in(12) And Control(160)) OR (Data_in(13) And Control(174)) OR (Data_in(14) And Control(188)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(105)) OR (Data_in(9) And Control(119)) OR (Data_in(10) And Control(133)) OR (Data_in(11) And Control(147)) OR (Data_in(12) And Control(161)) OR (Data_in(13) And Control(175)) OR (Data_in(14) And Control(189)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(92)) OR (Data_in(8) And Control(106)) OR (Data_in(9) And Control(120)) OR (Data_in(10) And Control(134)) OR (Data_in(11) And Control(148)) OR (Data_in(12) And Control(162)) OR (Data_in(13) And Control(176)) OR (Data_in(14) And Control(190)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(79)) OR (Data_in(7) And Control(93)) OR (Data_in(8) And Control(107)) OR (Data_in(9) And Control(121)) OR (Data_in(10) And Control(135)) OR (Data_in(11) And Control(149)) OR (Data_in(12) And Control(163)) OR (Data_in(13) And Control(177)) OR (Data_in(14) And Control(191)));
+  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(80)) OR (Data_in(7) And Control(94)) OR (Data_in(8) And Control(108)) OR (Data_in(9) And Control(122)) OR (Data_in(10) And Control(136)) OR (Data_in(11) And Control(150)) OR (Data_in(12) And Control(164)) OR (Data_in(13) And Control(178)) OR (Data_in(14) And Control(192)));
+  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(95)) OR (Data_in(8) And Control(109)) OR (Data_in(9) And Control(123)) OR (Data_in(10) And Control(137)) OR (Data_in(11) And Control(151)) OR (Data_in(12) And Control(165)) OR (Data_in(13) And Control(179)) OR (Data_in(14) And Control(193)));
+  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(96)) OR (Data_in(8) And Control(110)) OR (Data_in(9) And Control(124)) OR (Data_in(10) And Control(138)) OR (Data_in(11) And Control(152)) OR (Data_in(12) And Control(166)) OR (Data_in(13) And Control(180)) OR (Data_in(14) And Control(194)));
+  Data_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(111)) OR (Data_in(9) And Control(125)) OR (Data_in(10) And Control(139)) OR (Data_in(11) And Control(153)) OR (Data_in(12) And Control(167)) OR (Data_in(13) And Control(181)) OR (Data_in(14) And Control(195)));
+  Data_out(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(112)) OR (Data_in(9) And Control(126)) OR (Data_in(10) And Control(140)) OR (Data_in(11) And Control(154)) OR (Data_in(12) And Control(168)) OR (Data_in(13) And Control(182)) OR (Data_in(14) And Control(196)));
+end generate crossbit14x14;
+
+
+--======================crossbit 15 ports=======================
+
+crossbit15x15 : if number_of_ports = 15 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(106)) OR (Data_in(9) And Control(121)) OR (Data_in(10) And Control(136)) OR (Data_in(11) And Control(151)) OR (Data_in(12) And Control(166)) OR (Data_in(13) And Control(181)) OR (Data_in(14) And Control(196)) OR (Data_in(15) And Control(211)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(92)) OR (Data_in(8) And Control(107)) OR (Data_in(9) And Control(122)) OR (Data_in(10) And Control(137)) OR (Data_in(11) And Control(152)) OR (Data_in(12) And Control(167)) OR (Data_in(13) And Control(182)) OR (Data_in(14) And Control(197)) OR (Data_in(15) And Control(212)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(93)) OR (Data_in(8) And Control(108)) OR (Data_in(9) And Control(123)) OR (Data_in(10) And Control(138)) OR (Data_in(11) And Control(153)) OR (Data_in(12) And Control(168)) OR (Data_in(13) And Control(183)) OR (Data_in(14) And Control(198)) OR (Data_in(15) And Control(213)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(79)) OR (Data_in(7) And Control(94)) OR (Data_in(8) And Control(109)) OR (Data_in(9) And Control(124)) OR (Data_in(10) And Control(139)) OR (Data_in(11) And Control(154)) OR (Data_in(12) And Control(169)) OR (Data_in(13) And Control(184)) OR (Data_in(14) And Control(199)) OR (Data_in(15) And Control(214)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(80)) OR (Data_in(7) And Control(95)) OR (Data_in(8) And Control(110)) OR (Data_in(9) And Control(125)) OR (Data_in(10) And Control(140)) OR (Data_in(11) And Control(155)) OR (Data_in(12) And Control(170)) OR (Data_in(13) And Control(185)) OR (Data_in(14) And Control(200)) OR (Data_in(15) And Control(215)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(96)) OR (Data_in(8) And Control(111)) OR (Data_in(9) And Control(126)) OR (Data_in(10) And Control(141)) OR (Data_in(11) And Control(156)) OR (Data_in(12) And Control(171)) OR (Data_in(13) And Control(186)) OR (Data_in(14) And Control(201)) OR (Data_in(15) And Control(216)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(112)) OR (Data_in(9) And Control(127)) OR (Data_in(10) And Control(142)) OR (Data_in(11) And Control(157)) OR (Data_in(12) And Control(172)) OR (Data_in(13) And Control(187)) OR (Data_in(14) And Control(202)) OR (Data_in(15) And Control(217)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(113)) OR (Data_in(9) And Control(128)) OR (Data_in(10) And Control(143)) OR (Data_in(11) And Control(158)) OR (Data_in(12) And Control(173)) OR (Data_in(13) And Control(188)) OR (Data_in(14) And Control(203)) OR (Data_in(15) And Control(218)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(99)) OR (Data_in(8) And Control(114)) OR (Data_in(9) And Control(129)) OR (Data_in(10) And Control(144)) OR (Data_in(11) And Control(159)) OR (Data_in(12) And Control(174)) OR (Data_in(13) And Control(189)) OR (Data_in(14) And Control(204)) OR (Data_in(15) And Control(219)));
+  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(85)) OR (Data_in(7) And Control(100)) OR (Data_in(8) And Control(115)) OR (Data_in(9) And Control(130)) OR (Data_in(10) And Control(145)) OR (Data_in(11) And Control(160)) OR (Data_in(12) And Control(175)) OR (Data_in(13) And Control(190)) OR (Data_in(14) And Control(205)) OR (Data_in(15) And Control(220)));
+  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(71)) OR (Data_in(6) And Control(86)) OR (Data_in(7) And Control(101)) OR (Data_in(8) And Control(116)) OR (Data_in(9) And Control(131)) OR (Data_in(10) And Control(146)) OR (Data_in(11) And Control(161)) OR (Data_in(12) And Control(176)) OR (Data_in(13) And Control(191)) OR (Data_in(14) And Control(206)) OR (Data_in(15) And Control(221)));
+  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(57)) OR (Data_in(5) And Control(72)) OR (Data_in(6) And Control(87)) OR (Data_in(7) And Control(102)) OR (Data_in(8) And Control(117)) OR (Data_in(9) And Control(132)) OR (Data_in(10) And Control(147)) OR (Data_in(11) And Control(162)) OR (Data_in(12) And Control(177)) OR (Data_in(13) And Control(192)) OR (Data_in(14) And Control(207)) OR (Data_in(15) And Control(222)));
+  Data_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(43)) OR (Data_in(4) And Control(58)) OR (Data_in(5) And Control(73)) OR (Data_in(6) And Control(88)) OR (Data_in(7) And Control(103)) OR (Data_in(8) And Control(118)) OR (Data_in(9) And Control(133)) OR (Data_in(10) And Control(148)) OR (Data_in(11) And Control(163)) OR (Data_in(12) And Control(178)) OR (Data_in(13) And Control(193)) OR (Data_in(14) And Control(208)) OR (Data_in(15) And Control(223)));
+  Data_out(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(29)) OR (Data_in(3) And Control(44)) OR (Data_in(4) And Control(59)) OR (Data_in(5) And Control(74)) OR (Data_in(6) And Control(89)) OR (Data_in(7) And Control(104)) OR (Data_in(8) And Control(119)) OR (Data_in(9) And Control(134)) OR (Data_in(10) And Control(149)) OR (Data_in(11) And Control(164)) OR (Data_in(12) And Control(179)) OR (Data_in(13) And Control(194)) OR (Data_in(14) And Control(209)) OR (Data_in(15) And Control(224)));
+  Data_out(15) <= ((Data_in(1) And Control(15)) OR (Data_in(2) And Control(30)) OR (Data_in(3) And Control(45)) OR (Data_in(4) And Control(60)) OR (Data_in(5) And Control(75)) OR (Data_in(6) And Control(90)) OR (Data_in(7) And Control(105)) OR (Data_in(8) And Control(120)) OR (Data_in(9) And Control(135)) OR (Data_in(10) And Control(150)) OR (Data_in(11) And Control(165)) OR (Data_in(12) And Control(180)) OR (Data_in(13) And Control(195)) OR (Data_in(14) And Control(210)) OR (Data_in(15) And Control(225)));
+end generate crossbit15x15;
+
+
+--======================crossbit 16 ports=======================
+
+crossbit16x16 : if number_of_ports = 16 generate
+
+  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(113)) OR (Data_in(9) And Control(129)) OR (Data_in(10) And Control(145)) OR (Data_in(11) And Control(161)) OR (Data_in(12) And Control(177)) OR (Data_in(13) And Control(193)) OR (Data_in(14) And Control(209)) OR (Data_in(15) And Control(225)) OR (Data_in(16) And Control(241)));
+  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(114)) OR (Data_in(9) And Control(130)) OR (Data_in(10) And Control(146)) OR (Data_in(11) And Control(162)) OR (Data_in(12) And Control(178)) OR (Data_in(13) And Control(194)) OR (Data_in(14) And Control(210)) OR (Data_in(15) And Control(226)) OR (Data_in(16) And Control(242)));
+  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(99)) OR (Data_in(8) And Control(115)) OR (Data_in(9) And Control(131)) OR (Data_in(10) And Control(147)) OR (Data_in(11) And Control(163)) OR (Data_in(12) And Control(179)) OR (Data_in(13) And Control(195)) OR (Data_in(14) And Control(211)) OR (Data_in(15) And Control(227)) OR (Data_in(16) And Control(243)));
+  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(100)) OR (Data_in(8) And Control(116)) OR (Data_in(9) And Control(132)) OR (Data_in(10) And Control(148)) OR (Data_in(11) And Control(164)) OR (Data_in(12) And Control(180)) OR (Data_in(13) And Control(196)) OR (Data_in(14) And Control(212)) OR (Data_in(15) And Control(228)) OR (Data_in(16) And Control(244)));
+  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(85)) OR (Data_in(7) And Control(101)) OR (Data_in(8) And Control(117)) OR (Data_in(9) And Control(133)) OR (Data_in(10) And Control(149)) OR (Data_in(11) And Control(165)) OR (Data_in(12) And Control(181)) OR (Data_in(13) And Control(197)) OR (Data_in(14) And Control(213)) OR (Data_in(15) And Control(229)) OR (Data_in(16) And Control(245)));
+  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(86)) OR (Data_in(7) And Control(102)) OR (Data_in(8) And Control(118)) OR (Data_in(9) And Control(134)) OR (Data_in(10) And Control(150)) OR (Data_in(11) And Control(166)) OR (Data_in(12) And Control(182)) OR (Data_in(13) And Control(198)) OR (Data_in(14) And Control(214)) OR (Data_in(15) And Control(230)) OR (Data_in(16) And Control(246)));
+  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(71)) OR (Data_in(6) And Control(87)) OR (Data_in(7) And Control(103)) OR (Data_in(8) And Control(119)) OR (Data_in(9) And Control(135)) OR (Data_in(10) And Control(151)) OR (Data_in(11) And Control(167)) OR (Data_in(12) And Control(183)) OR (Data_in(13) And Control(199)) OR (Data_in(14) And Control(215)) OR (Data_in(15) And Control(231)) OR (Data_in(16) And Control(247)));
+  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(72)) OR (Data_in(6) And Control(88)) OR (Data_in(7) And Control(104)) OR (Data_in(8) And Control(120)) OR (Data_in(9) And Control(136)) OR (Data_in(10) And Control(152)) OR (Data_in(11) And Control(168)) OR (Data_in(12) And Control(184)) OR (Data_in(13) And Control(200)) OR (Data_in(14) And Control(216)) OR (Data_in(15) And Control(232)) OR (Data_in(16) And Control(248)));
+  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(57)) OR (Data_in(5) And Control(73)) OR (Data_in(6) And Control(89)) OR (Data_in(7) And Control(105)) OR (Data_in(8) And Control(121)) OR (Data_in(9) And Control(137)) OR (Data_in(10) And Control(153)) OR (Data_in(11) And Control(169)) OR (Data_in(12) And Control(185)) OR (Data_in(13) And Control(201)) OR (Data_in(14) And Control(217)) OR (Data_in(15) And Control(233)) OR (Data_in(16) And Control(249)));
+  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(58)) OR (Data_in(5) And Control(74)) OR (Data_in(6) And Control(90)) OR (Data_in(7) And Control(106)) OR (Data_in(8) And Control(122)) OR (Data_in(9) And Control(138)) OR (Data_in(10) And Control(154)) OR (Data_in(11) And Control(170)) OR (Data_in(12) And Control(186)) OR (Data_in(13) And Control(202)) OR (Data_in(14) And Control(218)) OR (Data_in(15) And Control(234)) OR (Data_in(16) And Control(250)));
+  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(43)) OR (Data_in(4) And Control(59)) OR (Data_in(5) And Control(75)) OR (Data_in(6) And Control(91)) OR (Data_in(7) And Control(107)) OR (Data_in(8) And Control(123)) OR (Data_in(9) And Control(139)) OR (Data_in(10) And Control(155)) OR (Data_in(11) And Control(171)) OR (Data_in(12) And Control(187)) OR (Data_in(13) And Control(203)) OR (Data_in(14) And Control(219)) OR (Data_in(15) And Control(235)) OR (Data_in(16) And Control(251)));
+  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(44)) OR (Data_in(4) And Control(60)) OR (Data_in(5) And Control(76)) OR (Data_in(6) And Control(92)) OR (Data_in(7) And Control(108)) OR (Data_in(8) And Control(124)) OR (Data_in(9) And Control(140)) OR (Data_in(10) And Control(156)) OR (Data_in(11) And Control(172)) OR (Data_in(12) And Control(188)) OR (Data_in(13) And Control(204)) OR (Data_in(14) And Control(220)) OR (Data_in(15) And Control(236)) OR (Data_in(16) And Control(252)));
+  Data_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(29)) OR (Data_in(3) And Control(45)) OR (Data_in(4) And Control(61)) OR (Data_in(5) And Control(77)) OR (Data_in(6) And Control(93)) OR (Data_in(7) And Control(109)) OR (Data_in(8) And Control(125)) OR (Data_in(9) And Control(141)) OR (Data_in(10) And Control(157)) OR (Data_in(11) And Control(173)) OR (Data_in(12) And Control(189)) OR (Data_in(13) And Control(205)) OR (Data_in(14) And Control(221)) OR (Data_in(15) And Control(237)) OR (Data_in(16) And Control(253)));
+  Data_out(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(30)) OR (Data_in(3) And Control(46)) OR (Data_in(4) And Control(62)) OR (Data_in(5) And Control(78)) OR (Data_in(6) And Control(94)) OR (Data_in(7) And Control(110)) OR (Data_in(8) And Control(126)) OR (Data_in(9) And Control(142)) OR (Data_in(10) And Control(158)) OR (Data_in(11) And Control(174)) OR (Data_in(12) And Control(190)) OR (Data_in(13) And Control(206)) OR (Data_in(14) And Control(222)) OR (Data_in(15) And Control(238)) OR (Data_in(16) And Control(254)));
+  Data_out(15) <= ((Data_in(1) And Control(15)) OR (Data_in(2) And Control(31)) OR (Data_in(3) And Control(47)) OR (Data_in(4) And Control(63)) OR (Data_in(5) And Control(79)) OR (Data_in(6) And Control(95)) OR (Data_in(7) And Control(111)) OR (Data_in(8) And Control(127)) OR (Data_in(9) And Control(143)) OR (Data_in(10) And Control(159)) OR (Data_in(11) And Control(175)) OR (Data_in(12) And Control(191)) OR (Data_in(13) And Control(207)) OR (Data_in(14) And Control(223)) OR (Data_in(15) And Control(239)) OR (Data_in(16) And Control(255)));
+  Data_out(16) <= ((Data_in(1) And Control(16)) OR (Data_in(2) And Control(32)) OR (Data_in(3) And Control(48)) OR (Data_in(4) And Control(64)) OR (Data_in(5) And Control(80)) OR (Data_in(6) And Control(96)) OR (Data_in(7) And Control(112)) OR (Data_in(8) And Control(128)) OR (Data_in(9) And Control(144)) OR (Data_in(10) And Control(160)) OR (Data_in(11) And Control(176)) OR (Data_in(12) And Control(192)) OR (Data_in(13) And Control(208)) OR (Data_in(14) And Control(224)) OR (Data_in(15) And Control(240)) OR (Data_in(16) And Control(256)));
+end generate crossbit16x16;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/FIFO_256_FWFT.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/FIFO_256_FWFT.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/FIFO_256_FWFT.vhd	(revision 20)
@@ -0,0 +1,232 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL/GAMOM 
+-- 
+-- Create Date:    19:51:54 04/19/2011 
+-- Design Name: 
+-- Module Name:    FIFO_64 - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--FIFO 64 Octets utisé pour les modules d'entrée 
+-- ce fifo est de type fwft first word falls throught ce qui 
+-- signifie que l'on a toujours la donnée au sommet de la pile en 
+-- sortie du fifo. 
+-- Dependencies:  RAM_64.vhd
+-- 
+-- Revision: 30-07-2012
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+-- le signal counter_en a été supprimé
+----------------------------------------------------------------------------------
+library IEEE;
+
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--Library NocLib;
+--use NocLib.CoreTypes.all;
+use work.CoreTypes.all;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity FIFO_256_FWFT is
+    Port ( clk : in  STD_LOGIC;
+           din : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           rd_en : in  STD_LOGIC;
+           srst : in  STD_LOGIC;
+           wr_en : in  STD_LOGIC;
+           dout : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+           empty : out  STD_LOGIC;
+           full : out  STD_LOGIC);
+end FIFO_256_FWFT;
+
+architecture Behavioral of FIFO_256_FWFT is
+-- declaration de la ram 256 octets
+COMPONENT RAM_256
+	PORT(
+		clka : IN std_logic;
+		clkb : IN std_logic;
+		wea : IN std_logic;
+		ena : IN std_logic;
+		enb : IN std_logic;
+		addra : IN std_logic_vector(Word-1 downto 0);
+		addrb : IN std_logic_vector(Word-1 downto 0);
+		dia : IN std_logic_vector(Word-1 downto 0);          
+		dob : OUT std_logic_vector(Word-1 downto 0)
+		);
+END COMPONENT;
+type fsm_states is (state0, state1, state2, state3);-- definition du type etat pour le codage des etats des fsm
+signal fwft_fsm_state : fsm_states;
+type ram_type is array (255 downto 0) of std_logic_vector (Word-1 downto 0);
+	signal RAM: ram_type;
+-- declaration des signeaux des compteurs
+signal push_address_counter: std_logic_vector(Word-1 downto 0);
+signal pop_address_counter : std_logic_vector(Word-1 downto 0);
+signal fifo_counter : std_logic_vector(Word-1 downto 0);
+--autre signaux
+signal empty_signal: std_logic:='1';
+signal rd_ready : std_logic:='0';
+signal full_signal  : std_logic;
+signal wr_en_signal : std_logic;--_vector(0 downto 0);
+signal rd_en_signal : std_logic;
+signal clk_signal :  std_logic;
+signal dob_signal : std_logic_vector(Word-1 downto 0);
+signal dout_signal : std_logic_vector(Word-1 downto 0);
+signal doa_signal : std_logic_vector(Word-1 downto 0);
+signal counter_en : std_logic; 
+
+begin
+
+-- ram instantiation de la bloc ram 256 octets du FIFO
+fifo_RAM_256: RAM_256 PORT MAP(
+		clka => clk_signal,
+		clkb => clk_signal,
+		wea => wr_en_signal,
+		ena => '1',
+		enb => '1',
+		addra => push_address_counter,
+		addrb => pop_address_counter,
+		dia => din,
+		dob => doa_signal
+	);
+		
+-- circuiterie des signaux de validation et d'etat du fifo
+wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein
+rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide
+full_signal <= '1' when fifo_counter = "11111111" else
+				   '0';
+--empty_signal <= '1' when fifo_counter = "000000"  else
+--					 '0';
+empty_signal <= '1' when rd_ready='0' or unsigned(fifo_counter) = 0  else
+					 '0';
+clk_signal <= clk;
+full <= full_signal;
+empty <= empty_signal ;
+
+-- sortie du fifo fwft
+dout <= dout_signal;
+
+-- le processus des transistion
+fwft_fsm_nsl : process(clk_signal)
+ begin
+    if rising_edge(clk_signal) then
+	   if srst = '1' then
+		   fwft_fsm_state  <= state0;
+		else
+		   case fwft_fsm_state  is
+					when state0 => if wr_en_signal = '1' then  --tampon vide seule l'écriture est possible
+											fwft_fsm_state  <= state1;
+										end if;
+										
+										
+					when state1 => --if rd_en_signal = '1' and wr_en_signal='1'  then  --écriture seule dans le tampon
+											
+											fwft_fsm_state  <= state2;
+										--end if;
+										
+					when state2 => if rd_en_signal = '1' and wr_en_signal='1'  then
+											fwft_fsm_state  <= state2;
+										elsif rd_en_signal='1' and wr_en_signal='0' and unsigned(fifo_counter) = 1 then --lecture avec écriture
+											fwft_fsm_state  <= state0;
+										elsif unsigned(fifo_counter) = 0 then
+											fwft_fsm_state  <= state0;
+										end if;
+										
+					when state3 => if rd_en_signal = '1' then  --écriture seule dans le tampon
+											fwft_fsm_state  <= state0;
+										elsif wr_en_signal='1' then
+											fwft_fsm_state  <= state2;
+										end if;
+
+					when others => fwft_fsm_state <= state0;
+										
+										
+			end case;
+	   end if;
+	end if;
+ end process;
+ -- actions associées à la fsm
+ -- mux qui oriente les sortie doa et dob vers out
+ with fwft_fsm_state select
+    dout_signal <= dob_signal when state0, 
+	                dob_signal when state1, --la sortie est la donnée en entrée
+	                dob_signal when state2, -- la sortie vient de la RAM
+						 dob_signal when state3,
+						 doa_signal when others;
+ -- counter_en
+ with fwft_fsm_state select
+    counter_en   <= '0' when state0, 
+	                 '1' when state1,
+	                 '1' when state2,
+						  '1' when state3,	
+						  '0' when others;
+						  
+with fwft_fsm_state select
+    rd_ready   <= '0' when state0, 
+	                 '0' when state1,
+	                 '1' when state2,
+						  '1' when state3,	
+						  '0' when others;
+doa_latch_process : process(clk_signal)
+begin
+  if rising_edge(clk_signal) then
+		if wr_en_signal ='1'  then
+			doa_signal <= din;
+		end if;
+  end if;
+end process;
+	               
+-- processus de comptage des adresses d'empilement
+push_process : process(clk_signal)
+ begin
+ if rising_edge(clk_signal) then
+   if srst = '1' then
+	 push_address_counter <= (others =>'0');
+	elsif wr_en_signal ='1'   then
+			RAM(conv_integer(push_address_counter)) <=din;
+	   	push_address_counter <= push_address_counter +1;
+	 end if;
+ end if;
+end process;
+ 
+ -- processus de comptage des adresses depilement du fifo
+pop_process : process(clk_signal)
+ begin
+ if rising_edge(clk_signal) then
+   if srst = '1' then
+	  pop_address_counter <= (others =>'0'); --pour avoir un décalage entre la valeur lue et celle qui est écrite
+	elsif rd_en_signal ='1'  then
+		pop_address_counter <= pop_address_counter+1;
+	end if;
+	
+ end if;
+ end process;
+ dob_signal<=RAM(conv_integer(pop_address_counter));
+ -- processus de comptage des octets dans le fifo
+ fifo_counter_process : process(clk_signal)
+variable count : std_logic_vector(word-1 downto 0):= (others=>'0');
+begin
+ if rising_edge(clk_signal) then
+   if srst = '1' then
+	 fifo_counter <= (others =>'0');
+	 count:=(others =>'0');
+	else
+	 if wr_en_signal ='1'  and rd_en_signal ='0' then 
+		--fifo_counter <= fifo_counter +1;
+		count:=count+1;
+	  end if;
+	 if rd_en_signal ='1' and wr_en_signal ='0' and counter_en='1' then
+		--fifo_counter <= fifo_counter - 1;
+		count:=count-1;		
+	 end if;
+	 fifo_counter<=count;
+  end if;
+ end if;
+end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/FIFO_256_FWFT_guide.ncd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/FIFO_256_FWFT_guide.ncd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/FIFO_256_FWFT_guide.ncd	(revision 20)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
+###4376:XlxV32DM    315f    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   188d     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Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/FIFO_DP.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/FIFO_DP.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/FIFO_DP.vhd	(revision 20)
@@ -0,0 +1,102 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    16:32:59 10/23/2012 
+-- Design Name: 
+-- Module Name:    FIFO_DP - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity fifo_dp is
+GENERIC
+(
+ADDRESS_WIDTH : integer:=8;---8 bit
+DATA_WIDTH : integer:=8 ---8 bit
+);
+
+port ( clk : in std_logic;
+reset : in std_logic;
+enr : in std_logic; --enable read,should be '0' when not in use.
+enw : in std_logic; --enable write,should be '0' when not in use.
+dataout : out std_logic_vector(DATA_WIDTH-1 downto 0); --output data
+datain : in std_logic_vector (DATA_WIDTH-1 downto 0); --input data
+empty : out std_logic; --set as '1' when the queue is empty
+err : out std_logic;
+full : out std_logic --set as '1' when the queue is full
+);
+end fifo;
+
+architecture Behavioral of fifo_dp is
+
+type memory_type is array (0 to ((2**ADDRESS_WIDTH)-1)) of std_logic_vector(DATA_WIDTH-1 downto 0);
+
+
+-----distributed-------
+signal memory : memory_type ;-- :=(others => (others => '0')); --memory for queue.----- 
+signal readptr,writeptr : std_logic_vector(ADDRESS_WIDTH-1 downto 0); --read and write pointers.
+signal full0 : std_logic;
+signal empty0 : std_logic;
+
+begin
+full <= full0;
+empty <= empty0; 
+
+fifo0: process(clk,reset)
+begin
+if reset='1' then
+
+readptr <= (others => '0');
+writeptr <= (others => '0');
+empty0 <='1';
+full0<='0';
+err<='0';
+
+
+elsif rising_edge(clk) then 
+
+if (writeptr + '1' = readptr) then 
+full0<='1';
+else
+full0<='0';
+end if ;
+
+if (readptr = writeptr ) then 
+empty0<='1';
+else
+empty0<='0';
+end if ; 
+
+if (empty0='0' and enr='1') or (full0='0' and enw='1') then 
+err<='1';
+end if ; 
+
+if enw='1' and full0='0' then 
+memory (conv_integer(writeptr)) <= datain ;
+writeptr <= writeptr + '1' ;
+end if ; 
+
+if enr='1' and empty0='0' then 
+dataout <= memory (conv_integer(readptr));
+readptr <= readptr + '1' ;
+end if ; 
+
+end if; 
+
+end process;
+end Behavioral;
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16.gise
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16.gise	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16.gise	(revision 20)
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="GENERIC_16_16.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_NCD" xil_pn:name="FIFO_256_FWFT_guide.ncd" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="OUTPUT_PORT_MODULE.sym" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GENERIQUE_guide.ncd" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GEN_guide.ncd" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16.xise
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16.xise	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16.xise	(revision 20)
@@ -0,0 +1,515 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="Crossbit.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="Crossbar.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="Scheduler.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="Arbiter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER2_2.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER3_3.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER4_4.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER5_5.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER6_6.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER7_7.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER8_8.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER9_9.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER10_10.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER11_11.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER12_12.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER13_13.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER14_14.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER15_15.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SCHEDULER16_16.VHD" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="RAM_256.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="FIFO_256_FWFT.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="INPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="OUTPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SWITCH_GENERIQUE.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="test_xbar_8x8.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="PostMapSimulation"/>
+      <association xil_pn:name="PostRouteSimulation"/>
+      <association xil_pn:name="PostTranslateSimulation"/>
+    </file>
+    <file xil_pn:name="conv.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="stimuli1.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="C:/RomSwitch/testport5.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="CoreTypes.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="../CORE_MPI/sim_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="Proto_receiv.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="FIFO_DP.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="proto_send.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="AES Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="Test_fifo.wcfg" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Custom Waveform Configuration File Translate" xil_pn:value="test_xbar_8x8.wcfg" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc3s1200e" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../CORE_MPI/sim_fifo.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
+    <property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="testbench" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="ft256" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="testbench_map.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="testbench_timesim.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="testbench_synthesis.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="testbench_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="testbench" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.test_xbar_8x8" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.test_xbar_16x16" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="180 ns" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.test_xbar_8x8" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.test_xbar_16x16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="d:/Xilinx/12.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Waveform Database Filename Post-Translate" xil_pn:value="test_xbar_8x8_isim_beh.wdb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="GENERIC_16_16" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="Architecture|test_xbar_16x16|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Architecture|test_xbar_16x16|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-07-11T16:58:22" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6E6D9310BD824CB7AA37132338EEB7D5" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries>
+    <library xil_pn:name="NoClib"/>
+    <library xil_pn:name="typesconv"/>
+  </libraries>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys	(revision 20)
@@ -0,0 +1,24 @@
+CommandLine-Map
+
+s
+CommandLine-Ngdbuild
+
+s
+CommandLine-Par
+
+s
+CommandLine-Xst
+
+s
+Previous-NGD
+
+s
+Previous-NGM
+
+s
+Previous-Packed-NCD
+
+s
+Previous-Routed-NCD
+
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ISE_VERSION_LAST_SAVED_WITH
+11.1
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys	(revision 20)
@@ -0,0 +1,6 @@
+ISE_VERSION_LAST_SAVED_WITH
+11.1
+s
+XISE_FILE
+GENERIC_16_16.xise
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/XSLTProcess.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys	(revision 20)
@@ -0,0 +1,21 @@
+ISE_VERSION_CREATED_WITH
+11.1
+s
+ISE_VERSION_LAST_SAVED_WITH
+11.1
+s
+LastRepoDir
+C:\Documents and Settings\GENERAL\Bureau\GENERIC_16_16\
+s
+OBJSTORE_VERSION
+1.3
+s
+PROJECT_CREATION_TIMESTAMP
+2011-06-19T11:17:23
+s
+REGISTRY_VERSION
+1.1
+s
+REPOSITORY_VERSION
+1.1
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/bitgen.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/bitinit.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/common/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/common/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/common/regkeys	(revision 20)
@@ -0,0 +1,15 @@
+IncrementalMessagingEnabled
+false
+s
+MessageCaptureEnabled
+true
+s
+MessageFilterFile
+filter.filter
+s
+MessageFilteringEnabled
+false
+s
+RunOnce
+#/PnAutoRun/Scripts/RunOnce_tcl
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/cpldfit.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/dumpngdio.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/fuse/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/fuse/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/fuse/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/fuse.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/hprep6.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/idem/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/idem/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/idem/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/idem.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/libgen/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/libgen/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/libgen/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/libgen.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/map/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/map/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/map/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/map.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/netgen/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/netgen/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/netgen/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/netgen.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/ngc2edif.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/ngcbuild.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/ngdbuild.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/par/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/par/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/par/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/par.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/platgen/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/platgen/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/platgen/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/platgen.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/runner/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/runner/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/runner/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/runner.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/simgen/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/simgen/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/simgen/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/simgen.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/taengine/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/taengine/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/taengine/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/taengine.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/trce/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/trce/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/trce/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/trce.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/tsim/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/tsim/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/tsim/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/tsim.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/vhpcomp.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/vlogcomp.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/xpwr.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/xst/regkeys
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/xst/regkeys	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/__REGISTRY__/xst/regkeys	(revision 20)
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/xst.xmsgs
+s
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/version
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/version	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/GENERIC_16_16_xdb/tmp/ise/version	(revision 20)
@@ -0,0 +1,10 @@
+REPOSITORY_VERSION
+1.1
+REGISTRY_VERSION
+1.1
+OBJSTORE_VERSION
+1.3
+ISE_VERSION_CREATED_WITH
+11.1
+ISE_VERSION_LAST_SAVED_WITH
+11.1
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.cmd_log
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.cmd_log	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.cmd_log	(revision 20)
@@ -0,0 +1,2 @@
+xst -ise "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/GENERIC_16_16.ise" -intstyle ise -ifn "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.xst" -ofn "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.syr" 
+xst -ise "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/GENERIC_16_16.ise" -intstyle ise -ifn "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.xst" -ofn "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.syr" 
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.ngc
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.ngc	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.ngc	(revision 20)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.5e
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Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.prj
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.prj	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.prj	(revision 20)
@@ -0,0 +1,3 @@
+vhdl work "RAM_256.vhd"
+vhdl work "FIFO_256_FWFT.vhd"
+vhdl work "INPUT_PORT_MODULE.vhd"
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.stx
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.stx	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.stx	(revision 20)
@@ -0,0 +1,38 @@
+Release 11.1 - xst L.33 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
+--> Parameter TMPDIR set to C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.17 secs
+ 
+--> Parameter xsthdpdir set to C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.17 secs
+ 
+--> 
+=========================================================================
+*                          HDL Compilation                              *
+=========================================================================
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/RAM_256.vhd" in Library work.
+Architecture behavioral of Entity ram_256 is up to date.
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/FIFO_256_FWFT.vhd" in Library work.
+Architecture behavioral of Entity fifo_256_fwft is up to date.
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.vhd" in Library work.
+Entity <input_port_module> compiled.
+Entity <INPUT_PORT_MODULE> (Architecture <Behavioral>) compiled.
+
+
+Total REAL time to Xst completion: 1.00 secs
+Total CPU time to Xst completion: 0.83 secs
+ 
+--> 
+
+Total memory usage is 120796 kilobytes
+
+Number of errors   :    0 (   0 filtered)
+Number of warnings :    0 (   0 filtered)
+Number of infos    :    0 (   0 filtered)
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.syr
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.syr	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.syr	(revision 20)
@@ -0,0 +1,552 @@
+Release 11.1 - xst L.33 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
+--> Parameter TMPDIR set to xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.18 secs
+ 
+--> Parameter xsthdpdir set to xst
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.18 secs
+ 
+--> Reading design: INPUT_PORT_MODULE.prj
+
+TABLE OF CONTENTS
+  1) Synthesis Options Summary
+  2) HDL Compilation
+  3) Design Hierarchy Analysis
+  4) HDL Analysis
+  5) HDL Synthesis
+     5.1) HDL Synthesis Report
+  6) Advanced HDL Synthesis
+     6.1) Advanced HDL Synthesis Report
+  7) Low Level Synthesis
+  8) Partition Report
+  9) Final Report
+	9.1) Device utilization summary
+	9.2) Partition Resource Summary
+	9.3) TIMING REPORT
+
+
+=========================================================================
+*                      Synthesis Options Summary                        *
+=========================================================================
+---- Source Parameters
+Input File Name                    : "INPUT_PORT_MODULE.prj"
+Input Format                       : mixed
+Ignore Synthesis Constraint File   : NO
+
+---- Target Parameters
+Output File Name                   : "INPUT_PORT_MODULE"
+Output Format                      : NGC
+Target Device                      : xc3s1200e-4-fg320
+
+---- Source Options
+Top Module Name                    : INPUT_PORT_MODULE
+Automatic FSM Extraction           : YES
+FSM Encoding Algorithm             : Auto
+Safe Implementation                : No
+FSM Style                          : lut
+RAM Extraction                     : Yes
+RAM Style                          : Auto
+ROM Extraction                     : Yes
+Mux Style                          : Auto
+Decoder Extraction                 : YES
+Priority Encoder Extraction        : YES
+Shift Register Extraction          : YES
+Logical Shifter Extraction         : YES
+XOR Collapsing                     : YES
+ROM Style                          : Auto
+Mux Extraction                     : YES
+Resource Sharing                   : YES
+Asynchronous To Synchronous        : NO
+Automatic Register Balancing       : No
+
+---- Target Options
+Add IO Buffers                     : YES
+Add Generic Clock Buffer(BUFG)     : 24
+Register Duplication               : YES
+Slice Packing                      : YES
+Optimize Instantiated Primitives   : NO
+Use Clock Enable                   : Yes
+Use Synchronous Set                : Yes
+Use Synchronous Reset              : Yes
+Pack IO Registers into IOBs        : auto
+Equivalent register Removal        : YES
+
+---- General Options
+Optimization Goal                  : Speed
+Optimization Effort                : 1
+Library Search Order               : INPUT_PORT_MODULE.lso
+Keep Hierarchy                     : NO
+Netlist Hierarchy                  : as_optimized
+RTL Output                         : Yes
+Global Optimization                : AllClockNets
+Read Cores                         : YES
+Write Timing Constraints           : NO
+Cross Clock Analysis               : NO
+Hierarchy Separator                : /
+Bus Delimiter                      : <>
+Case Specifier                     : maintain
+Slice Utilization Ratio            : 100
+BRAM Utilization Ratio             : 100
+Verilog 2001                       : YES
+Auto BRAM Packing                  : NO
+Slice Utilization Ratio Delta      : 5
+
+=========================================================================
+
+
+=========================================================================
+*                          HDL Compilation                              *
+=========================================================================
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/RAM_256.vhd" in Library work.
+Architecture behavioral of Entity ram_256 is up to date.
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/FIFO_256_FWFT.vhd" in Library work.
+Architecture behavioral of Entity fifo_256_fwft is up to date.
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.vhd" in Library work.
+Entity <input_port_module> compiled.
+Entity <input_port_module> (Architecture <behavioral>) compiled.
+
+=========================================================================
+*                     Design Hierarchy Analysis                         *
+=========================================================================
+Analyzing hierarchy for entity <INPUT_PORT_MODULE> in library <work> (architecture <behavioral>) with generics.
+	number_of_ports = 4
+
+Analyzing hierarchy for entity <FIFO_256_FWFT> in library <work> (architecture <behavioral>).
+
+Analyzing hierarchy for entity <RAM_256> in library <work> (architecture <behavioral>).
+
+
+=========================================================================
+*                            HDL Analysis                               *
+=========================================================================
+Analyzing generic Entity <INPUT_PORT_MODULE> in library <work> (Architecture <behavioral>).
+	number_of_ports = 4
+Entity <INPUT_PORT_MODULE> analyzed. Unit <INPUT_PORT_MODULE> generated.
+
+Analyzing Entity <FIFO_256_FWFT> in library <work> (Architecture <behavioral>).
+Entity <FIFO_256_FWFT> analyzed. Unit <FIFO_256_FWFT> generated.
+
+Analyzing Entity <RAM_256> in library <work> (Architecture <behavioral>).
+Entity <RAM_256> analyzed. Unit <RAM_256> generated.
+
+
+=========================================================================
+*                           HDL Synthesis                               *
+=========================================================================
+
+Performing bidirectional port resolution...
+
+Synthesizing Unit <RAM_256>.
+    Related source file is "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/RAM_256.vhd".
+    Found 256x8-bit dual-port RAM <Mram_RAM> for signal <RAM>.
+    Found 8-bit register for signal <dob>.
+    Summary:
+	inferred   1 RAM(s).
+	inferred   8 D-type flip-flop(s).
+Unit <RAM_256> synthesized.
+
+
+Synthesizing Unit <FIFO_256_FWFT>.
+    Related source file is "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/FIFO_256_FWFT.vhd".
+    Found finite state machine <FSM_0> for signal <fwft_fsm_state>.
+    -----------------------------------------------------------------------
+    | States             | 3                                              |
+    | Transitions        | 8                                              |
+    | Inputs             | 3                                              |
+    | Outputs            | 4                                              |
+    | Clock              | clk (rising_edge)                              |
+    | Reset              | srst (positive)                                |
+    | Reset type         | synchronous                                    |
+    | Reset State        | state0                                         |
+    | Power Up State     | state0                                         |
+    | Encoding           | automatic                                      |
+    | Implementation     | LUT                                            |
+    -----------------------------------------------------------------------
+    Found 8-bit register for signal <doa_signal>.
+    Found 8-bit updown counter for signal <fifo_counter>.
+    Found 8-bit up counter for signal <pop_address_counter>.
+    Found 8-bit up counter for signal <push_address_counter>.
+    Summary:
+	inferred   1 Finite State Machine(s).
+	inferred   3 Counter(s).
+	inferred   8 D-type flip-flop(s).
+Unit <FIFO_256_FWFT> synthesized.
+
+
+Synthesizing Unit <INPUT_PORT_MODULE>.
+    Related source file is "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.vhd".
+    Found finite state machine <FSM_1> for signal <pop_state>.
+    -----------------------------------------------------------------------
+    | States             | 4                                              |
+    | Transitions        | 9                                              |
+    | Inputs             | 4                                              |
+    | Outputs            | 5                                              |
+    | Clock              | clk (rising_edge)                              |
+    | Reset              | reset_signal (positive)                        |
+    | Reset type         | synchronous                                    |
+    | Reset State        | state0                                         |
+    | Power Up State     | state0                                         |
+    | Encoding           | automatic                                      |
+    | Implementation     | LUT                                            |
+    -----------------------------------------------------------------------
+    Found 8-bit register for signal <data_counter>.
+    Found 8-bit subtractor for signal <data_counter$share0000> created at line 434.
+    Found 1-bit register for signal <empty_latch>.
+    Found 8-bit register for signal <pipeline_latch>.
+    Found 5-bit comparator greater for signal <port_granted$cmp_gt0000> created at line 110.
+    Found 4-bit register for signal <request_latch>.
+    Summary:
+	inferred   1 Finite State Machine(s).
+	inferred  21 D-type flip-flop(s).
+	inferred   1 Adder/Subtractor(s).
+	inferred   1 Comparator(s).
+Unit <INPUT_PORT_MODULE> synthesized.
+
+INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
+
+=========================================================================
+HDL Synthesis Report
+
+Macro Statistics
+# RAMs                                                 : 1
+ 256x8-bit dual-port RAM                               : 1
+# Adders/Subtractors                                   : 1
+ 8-bit subtractor                                      : 1
+# Counters                                             : 3
+ 8-bit up counter                                      : 2
+ 8-bit updown counter                                  : 1
+# Registers                                            : 6
+ 1-bit register                                        : 1
+ 4-bit register                                        : 1
+ 8-bit register                                        : 4
+# Comparators                                          : 1
+ 5-bit comparator greater                              : 1
+
+=========================================================================
+
+=========================================================================
+*                       Advanced HDL Synthesis                          *
+=========================================================================
+
+Analyzing FSM <FSM_1> for best encoding.
+Choose code 2 with characteristics nb_luts=8,nb_literals=21,nb_ffs=2,depth=2 ...
+Optimizing FSM <pop_state/FSM> on signal <pop_state[1:2]> with gray encoding.
+--------------------
+ State  | Encoding
+--------------------
+ state0 | 00
+ state1 | 01
+ state2 | 11
+ state3 | 10
+--------------------
+Analyzing FSM <FSM_0> for best encoding.
+Choose code 7 with characteristics nb_luts=5,nb_literals=16,nb_ffs=2,depth=2 ...
+Optimizing FSM <INPUT_PORT_FIFO/fwft_fsm_state/FSM> on signal <fwft_fsm_state[1:2]> with user encoding.
+--------------------
+ State  | Encoding
+--------------------
+ state0 | 00
+ state1 | 01
+ state2 | 10
+--------------------
+
+Synthesizing (advanced) Unit <RAM_256>.
+INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dob>
+    -----------------------------------------------------------------------
+    | ram_type           | Block                               |          |
+    -----------------------------------------------------------------------
+    | Port A                                                              |
+    |     aspect ratio   | 256-word x 8-bit                    |          |
+    |     mode           | read-first                          |          |
+    |     clkA           | connected to signal <clka>          | rise     |
+    |     weA            | connected to signal <wea>           | high     |
+    |     addrA          | connected to signal <addra>         |          |
+    |     diA            | connected to signal <dia>           |          |
+    -----------------------------------------------------------------------
+    | optimization       | speed                               |          |
+    -----------------------------------------------------------------------
+    | Port B                                                              |
+    |     aspect ratio   | 256-word x 8-bit                    |          |
+    |     mode           | write-first                         |          |
+    |     clkB           | connected to signal <clkb>          | rise     |
+    |     addrB          | connected to signal <addrb>         |          |
+    |     doB            | connected to signal <dob>           |          |
+    -----------------------------------------------------------------------
+    | optimization       | speed                               |          |
+    -----------------------------------------------------------------------
+Unit <RAM_256> synthesized (advanced).
+
+=========================================================================
+Advanced HDL Synthesis Report
+
+Macro Statistics
+# FSMs                                                 : 2
+# RAMs                                                 : 1
+ 256x8-bit dual-port block RAM                         : 1
+# Adders/Subtractors                                   : 1
+ 8-bit subtractor                                      : 1
+# Counters                                             : 3
+ 8-bit up counter                                      : 2
+ 8-bit updown counter                                  : 1
+# Registers                                            : 29
+ Flip-Flops                                            : 29
+# Comparators                                          : 1
+ 5-bit comparator greater                              : 1
+
+=========================================================================
+
+=========================================================================
+*                         Low Level Synthesis                           *
+=========================================================================
+
+Optimizing unit <INPUT_PORT_MODULE> ...
+
+Optimizing unit <FIFO_256_FWFT> ...
+
+Mapping all equations...
+Building and optimizing final netlist ...
+Found area constraint ratio of 100 (+ 5) on block INPUT_PORT_MODULE, actual ratio is 0.
+
+Final Macro Processing ...
+
+=========================================================================
+Final Register Report
+
+Macro Statistics
+# Registers                                            : 57
+ Flip-Flops                                            : 57
+
+=========================================================================
+
+=========================================================================
+*                           Partition Report                             *
+=========================================================================
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+=========================================================================
+*                            Final Report                               *
+=========================================================================
+Final Results
+RTL Top Level Output File Name     : INPUT_PORT_MODULE.ngr
+Top Level Output File Name         : INPUT_PORT_MODULE
+Output Format                      : NGC
+Optimization Goal                  : Speed
+Keep Hierarchy                     : NO
+
+Design Statistics
+# IOs                              : 31
+
+Cell Usage :
+# BELS                             : 142
+#      GND                         : 1
+#      INV                         : 2
+#      LUT1                        : 14
+#      LUT2                        : 4
+#      LUT3                        : 20
+#      LUT3_D                      : 1
+#      LUT3_L                      : 2
+#      LUT4                        : 44
+#      LUT4_D                      : 5
+#      LUT4_L                      : 2
+#      MUXCY                       : 21
+#      MUXF5                       : 1
+#      VCC                         : 1
+#      XORCY                       : 24
+# FlipFlops/Latches                : 57
+#      FDE                         : 8
+#      FDR                         : 3
+#      FDRE                        : 37
+#      FDRS                        : 9
+# RAMS                             : 1
+#      RAMB16_S9_S9                : 1
+# Clock Buffers                    : 1
+#      BUFGP                       : 1
+# IO Buffers                       : 30
+#      IBUF                        : 14
+#      OBUF                        : 16
+=========================================================================
+
+Device utilization summary:
+---------------------------
+
+Selected Device : 3s1200efg320-4 
+
+ Number of Slices:                       49  out of   8672     0%  
+ Number of Slice Flip Flops:             57  out of  17344     0%  
+ Number of 4 input LUTs:                 94  out of  17344     0%  
+ Number of IOs:                          31
+ Number of bonded IOBs:                  31  out of    250    12%  
+ Number of BRAMs:                         1  out of     28     3%  
+ Number of GCLKs:                         1  out of     24     4%  
+
+---------------------------
+Partition Resource Summary:
+---------------------------
+
+  No Partitions were found in this design.
+
+---------------------------
+
+
+=========================================================================
+TIMING REPORT
+
+NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
+      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
+      GENERATED AFTER PLACE-and-ROUTE.
+
+Clock Information:
+------------------
+-----------------------------------+------------------------+-------+
+Clock Signal                       | Clock buffer(FF name)  | Load  |
+-----------------------------------+------------------------+-------+
+clk                                | BUFGP                  | 58    |
+-----------------------------------+------------------------+-------+
+
+Asynchronous Control Signals Information:
+----------------------------------------
+No asynchronous control signals found in this design
+
+Timing Summary:
+---------------
+Speed Grade: -4
+
+   Minimum period: 7.226ns (Maximum Frequency: 138.389MHz)
+   Minimum input arrival time before clock: 9.258ns
+   Maximum output required time after clock: 7.556ns
+   Maximum combinational path delay: 8.635ns
+
+Timing Detail:
+--------------
+All values displayed in nanoseconds (ns)
+
+=========================================================================
+Timing constraint: Default period analysis for Clock 'clk'
+  Clock period: 7.226ns (frequency: 138.389MHz)
+  Total number of paths / destination ports: 1824 / 119
+-------------------------------------------------------------------------
+Delay:               7.226ns (Levels of Logic = 11)
+  Source:            pop_state_FSM_FFd1 (FF)
+  Destination:       INPUT_PORT_FIFO/fifo_counter_7 (FF)
+  Source Clock:      clk rising
+  Destination Clock: clk rising
+
+  Data Path: pop_state_FSM_FFd1 to INPUT_PORT_FIFO/fifo_counter_7
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FDRE:C->Q            18   0.591   1.103  pop_state_FSM_FFd1 (pop_state_FSM_FFd1)
+     LUT4_D:I2->O          1   0.704   0.455  INPUT_PORT_FIFO/rd_en_signal1_SW5 (N14)
+     LUT3:I2->O           14   0.704   1.035  INPUT_PORT_FIFO/rd_en_signal1 (INPUT_PORT_FIFO/rd_en_signal)
+     LUT3:I2->O            1   0.704   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0>)
+     MUXCY:S->O            1   0.464   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5>)
+     MUXCY:CI->O           0   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6>)
+     XORCY:CI->O           1   0.804   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_xor<7> (INPUT_PORT_FIFO/Result<7>)
+     FDRE:D                    0.308          INPUT_PORT_FIFO/fifo_counter_7
+    ----------------------------------------
+    Total                      7.226ns (4.633ns logic, 2.593ns route)
+                                       (64.1% logic, 35.9% route)
+
+=========================================================================
+Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
+  Total number of paths / destination ports: 528 / 134
+-------------------------------------------------------------------------
+Offset:              9.258ns (Levels of Logic = 13)
+  Source:            grant<1> (PAD)
+  Destination:       INPUT_PORT_FIFO/fifo_counter_7 (FF)
+  Destination Clock: clk rising
+
+  Data Path: grant<1> to INPUT_PORT_FIFO/fifo_counter_7
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     IBUF:I->O             1   1.218   0.595  grant_1_IBUF (grant_1_IBUF)
+     LUT4:I0->O           16   0.704   1.209  port_granted1 (port_granted)
+     LUT4_D:I0->O          1   0.704   0.455  INPUT_PORT_FIFO/rd_en_signal1_SW5 (N14)
+     LUT3:I2->O           14   0.704   1.035  INPUT_PORT_FIFO/rd_en_signal1 (INPUT_PORT_FIFO/rd_en_signal)
+     LUT3:I2->O            1   0.704   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0>)
+     MUXCY:S->O            1   0.464   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4>)
+     MUXCY:CI->O           1   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5>)
+     MUXCY:CI->O           0   0.059   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6>)
+     XORCY:CI->O           1   0.804   0.000  INPUT_PORT_FIFO/Mcount_fifo_counter_xor<7> (INPUT_PORT_FIFO/Result<7>)
+     FDRE:D                    0.308          INPUT_PORT_FIFO/fifo_counter_7
+    ----------------------------------------
+    Total                      9.258ns (5.964ns logic, 3.294ns route)
+                                       (64.4% logic, 35.6% route)
+
+=========================================================================
+Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
+  Total number of paths / destination ports: 53 / 16
+-------------------------------------------------------------------------
+Offset:              7.556ns (Levels of Logic = 3)
+  Source:            pop_state_FSM_FFd1 (FF)
+  Destination:       request<4> (PAD)
+  Source Clock:      clk rising
+
+  Data Path: pop_state_FSM_FFd1 to request<4>
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FDRE:C->Q            18   0.591   1.243  pop_state_FSM_FFd1 (pop_state_FSM_FFd1)
+     LUT4:I0->O            4   0.704   0.622  request_decoder_and00001 (request_decoder_and0000)
+     LUT3:I2->O            1   0.704   0.420  request_decoder<4>1 (request_4_OBUF)
+     OBUF:I->O                 3.272          request_4_OBUF (request<4>)
+    ----------------------------------------
+    Total                      7.556ns (5.271ns logic, 2.285ns route)
+                                       (69.8% logic, 30.2% route)
+
+=========================================================================
+Timing constraint: Default path analysis
+  Total number of paths / destination ports: 8 / 2
+-------------------------------------------------------------------------
+Delay:               8.635ns (Levels of Logic = 4)
+  Source:            grant<1> (PAD)
+  Destination:       data_out_pulse (PAD)
+
+  Data Path: grant<1> to data_out_pulse
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     IBUF:I->O             1   1.218   0.595  grant_1_IBUF (grant_1_IBUF)
+     LUT4:I0->O           16   0.704   1.209  port_granted1 (port_granted)
+     LUT4:I0->O           11   0.704   0.933  data_out_pulse1 (data_out_pulse_OBUF)
+     OBUF:I->O                 3.272          data_out_pulse_OBUF (data_out_pulse)
+    ----------------------------------------
+    Total                      8.635ns (5.898ns logic, 2.737ns route)
+                                       (68.3% logic, 31.7% route)
+
+=========================================================================
+
+
+Total REAL time to Xst completion: 10.00 secs
+Total CPU time to Xst completion: 9.84 secs
+ 
+--> 
+
+Total memory usage is 137348 kilobytes
+
+Number of errors   :    0 (   0 filtered)
+Number of warnings :    0 (   0 filtered)
+Number of infos    :    2 (   0 filtered)
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.vhd	(revision 20)
@@ -0,0 +1,796 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL/GAMOM Roland CHristian
+-- 
+-- Create Date:    03:47:50 04/24/2011 
+-- Design Name: 
+-- Module Name:    INPUT_PORT_MODULE - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+-- Module de gestion des entrées des ports du switch crossbar
+-- il supose qu'une donnée est empilée à chaque cycle d'horloge
+-- Dependencies: 
+-- FIFO_64_FWFT.vhd
+-- RAM_64.vhd
+-- Revision: 1
+-- remplacement du fifo ordinaire par un fifo fwft
+-- Revision 1.01 - File Created
+-- Additional Comments: 
+-- modifié le 14/05/20011  pour eviter une écriture multiple dans le FIFO de sortie
+-- si le FIFO d'entrée vient a se vider pendant le transfert d'un packet
+-- le machine a état on été re modeliser et sont maintenant du type FSMD
+-- remodéliation pour plus de vitesse
+--inclusion du signal priority rotation pour eviter la perte du grant pendant une transmission
+--02-08-2012 :Prise en compte du signal Port_Granted dans un process
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE ieee.numeric_std.ALL;
+use work.Coretypes.all;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+
+entity INPUT_PORT_MODULE is
+    generic(number_of_ports : positive := 4;
+	 
+	 Port_num: natural:=1);  -- port_num est l'id du port
+    Port ( data_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           data_in_en : in  STD_LOGIC; -- signaler la présence des données en entrée
+			  cmd_in_en : STD_LOGIC;    --permet d'identifier les données qui sont dans le tampon
+           reset : in  STD_LOGIC;
+			  clk   : in  STD_LOGIC;
+			  request : out  STD_LOGIC_VECTOR (number_of_ports downto 1); --demande de canal de transmission
+           grant : in  STD_LOGIC_VECTOR (number_of_ports  downto 1);	 -- autorisation de transmission		  
+           fifo_full : out  STD_LOGIC; -- signaler que les données ne peuvent plus être acceptées en entrée
+			  fifo_empty : out  STD_LOGIC; -- le tampon d'entrée est vide
+			  priority_rotation : out std_logic;  -- reserver le canal de transmission
+           data_out : out  STD_LOGIC_VECTOR (Word-1 downto 0); --données vers le réseau crossbar
+			  data_out_pulse : out std_logic); -- permet de ...
+       
+end INPUT_PORT_MODULE;
+
+architecture Behavioral of INPUT_PORT_MODULE is
+
+-- declaration du fifo 64 octet utilisé pour chaque port
+component FIFO_256_FWFT
+	port (
+	clk: IN std_logic;
+	din: IN std_logic_VECTOR(Word-1 downto 0);
+	rd_en: IN std_logic;
+	srst: IN std_logic;
+	wr_en: IN std_logic;
+	dout: OUT std_logic_VECTOR(Word-1 downto 0);
+	empty: OUT std_logic;
+	full: OUT std_logic);
+end component;
+
+--definition du type etat pour les fsm
+type fsm_states is (state0, CmdOn, WaitGrant, ReqPort, state1, state2,stpulse, state3);-- definition du type etat pour le codage des etats des fsm
+type fsm_states2 is(cmdstart,cmdwait,cmdread,cmdSetDest,cmdSetCount,cmdSetId,cmdpulse,CmdEnd);
+signal pop_state : fsm_states;
+signal cmdstate : fsm_states2;
+signal cmd_exec : std_logic:='0';  --indique que le port est en train d'exécuter une commande
+signal dat_exec :std_logic:='0'; -- indique le port est en train de transférer des données
+signal readOk : std_logic:='0'; --indique s'il est possible de lire les données
+-- signaux utilisés dans les fsm
+signal request_decoder : STD_LOGIC_VECTOR(number_of_ports  downto 1);
+signal request_decoder_en : std_logic;
+signal request_latch : STD_LOGIC_VECTOR(4 downto 1);   -- pourquoi pas 3 downto 0 ?
+signal request_latch_en : std_logic;
+signal pipeline_latch : std_logic_vector(Word-1 downto 0);
+signal pipeline_latch_en : std_logic;
+signal request_word :  std_logic_vector(5 downto 1);
+signal port_granted : std_logic;
+signal rd_en_signal : std_logic;
+--signaux utilisés dans la MAE de gestion des commandes
+signal cmd_request_latch_en :std_logic;
+signal cmd_pipeline_latch_en :std_logic;
+signal cmd_fifo_read_signal :std_logic;
+signal cmd_request_decoder_en :std_logic;
+signal cmd_data_out_pulse :std_logic;
+signal cmd_priority_rotation :std_logic;
+--signaux utilisés dans la MAE de transfert des données
+signal dat_request_latch_en :std_logic;
+signal dat_pipeline_latch_en :std_logic;
+signal dat_fifo_read_signal :std_logic;
+signal dat_request_decoder_en :std_logic;
+signal dat_data_out_pulse :std_logic;
+signal dat_priority_rotation :std_logic;
+-- signaux utilisés pour les connections entre composants
+signal clk_signal : std_logic;
+signal reset_signal : std_logic;
+signal fifo_empty_signal : std_logic;
+signal fifo_read_signal : std_logic;
+signal fifo_out_signal,cmd_data_signal : std_logic_vector(Word-1 downto 0);
+signal push_dout : std_logic_vector(Word-1 downto 0);
+signal empty_latch : std_logic ;
+signal PORT_ID :std_logic_vector(Word-1 downto 0):=STD_LOGIC_VECTOR(to_unsigned(number_of_ports-1,4))& STD_LOGIC_VECTOR(to_unsigned(port_num-1,4));
+-- signaux du compteur de données
+signal data_counter : std_logic_vector(Word-1 downto 0);
+
+begin
+-- instantiation du FIFO_256
+ INPUT_PORT_FIFO : FIFO_256_FWFT
+		port map (
+			clk => clk_signal,
+			din => data_in,
+			rd_en => fifo_read_signal,
+			srst => reset_signal,
+			wr_en => data_in_en,
+			dout => fifo_out_signal,
+			empty => fifo_empty_signal,
+			full => fifo_full);
+-- connections avec les ports de l'entité
+
+data_out <= pipeline_latch ;--when cmd_exec='0' else cmd_data_signal;
+fifo_empty <= fifo_empty_signal;
+reset_signal <= reset;
+grant_proc:process(clk)
+begin
+if rising_edge(clk) then
+	if unsigned(grant)> 0 then
+		port_granted <= '1';   		--il faut veiller à ce que ce port soit vraiment autorisé
+	else 
+		Port_granted<='0'; 	 		--ceci présuppose que la valeur qu'il reçoit est forcément la sienne
+	end if;
+end if;		
+end process;			 
+rd_en_signal <= not(empty_latch) ;
+request <= request_decoder;
+request_word <=  request_latch & request_decoder_en;
+clk_signal <= clk;
+
+
+
+WITH cmd_exec SELECT
+    request_latch_en <=  dat_request_latch_en   WHEN '0',
+								  cmd_request_latch_en  WHEN others;
+								  
+WITH cmd_exec SELECT
+		pipeline_latch_en  <=  dat_pipeline_latch_en   WHEN '0',
+								    cmd_pipeline_latch_en  WHEN others;
+								      
+WITH cmd_exec SELECT    
+		fifo_read_signal <=dat_fifo_read_signal WHEN '0', 
+		
+								cmd_fifo_read_signal WHEN others;
+WITH cmd_exec SELECT
+		request_decoder_en <=dat_request_decoder_en WHEN '0',
+									cmd_request_decoder_en WHEN others; 
+WITH cmd_exec SELECT
+		data_out_pulse <=dat_data_out_pulse WHEN '0',
+							  cmd_data_out_pulse WHEN others;
+WITH cmd_exec SELECT
+		priority_rotation<=dat_priority_rotation WHEN '0',
+								 cmd_priority_rotation WHEN others;
+
+
+--processus permettant de latcher le signal empty
+-- evite une perte de données en cas d'arret au cours d'une transmission
+empty_latch_process : process(clk)
+begin
+ if rising_edge(clk) then
+	if reset_signal = '1' then
+	    empty_latch <= '1';
+	else
+	 empty_latch <= fifo_empty_signal;
+   end if;
+ end if;	
+
+end process;
+-- decodeur de requete en fonction de l'adresse destination
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+switch2x2 : if number_of_ports = 2 generate
+
+with request_word select
+      request_decoder <="01" when "00001",
+                        "10" when "00011",
+                        "00" when others;
+
+end generate switch2x2;
+
+
+-- switch 3 ports
+switch3x3 : if number_of_ports = 3 generate
+
+with request_word select
+      request_decoder <="001" when "00001",
+                        "010" when "00011",
+                        "100" when "00101",
+                        "000" when others;
+
+end generate switch3x3;
+
+
+-- switch 4 ports
+switch4x4 : if number_of_ports = 4 generate
+
+with request_word select
+      request_decoder <="0001" when "00001",
+                        "0010" when "00011",
+                        "0100" when "00101",
+                        "1000" when "00111",
+                        "0000" when others;
+
+end generate switch4x4;
+
+
+-- switch 5 ports
+switch5x5 : if number_of_ports = 5 generate
+
+with request_word select
+      request_decoder <="00001" when "00001",
+                        "00010" when "00011",
+                        "00100" when "00101",
+                        "01000" when "00111",
+                        "10000" when "01001",
+                        "00000" when others;
+
+end generate switch5x5;
+
+
+-- switch 6 ports
+switch6x6 : if number_of_ports = 6 generate
+
+with request_word select
+      request_decoder <="000001" when "00001",
+                        "000010" when "00011",
+                        "000100" when "00101",
+                        "001000" when "00111",
+                        "010000" when "01001",
+                        "100000" when "01011",
+                        "000000" when others;
+
+end generate switch6x6;
+
+
+-- switch 7 ports
+switch7x7 : if number_of_ports = 7 generate
+
+with request_word select
+      request_decoder <="0000001" when "00001",
+                        "0000010" when "00011",
+                        "0000100" when "00101",
+                        "0001000" when "00111",
+                        "0010000" when "01001",
+                        "0100000" when "01011",
+                        "1000000" when "01101",
+                        "0000000" when others;
+
+end generate switch7x7;
+
+
+-- switch 8 ports
+switch8x8 : if number_of_ports = 8 generate
+
+with request_word select
+      request_decoder <="00000001" when "00001",
+                        "00000010" when "00011",
+                        "00000100" when "00101",
+                        "00001000" when "00111",
+                        "00010000" when "01001",
+                        "00100000" when "01011",
+                        "01000000" when "01101",
+                        "10000000" when "01111",
+                        "00000000" when others;
+
+end generate switch8x8;
+
+
+-- switch 9 ports
+switch9x9 : if number_of_ports = 9 generate
+
+with request_word select
+      request_decoder <="000000001" when "00001",
+                        "000000010" when "00011",
+                        "000000100" when "00101",
+                        "000001000" when "00111",
+                        "000010000" when "01001",
+                        "000100000" when "01011",
+                        "001000000" when "01101",
+                        "010000000" when "01111",
+                        "100000000" when "10001",
+                        "000000000" when others;
+
+end generate switch9x9;
+
+
+-- switch 10 ports
+switch10x10 : if number_of_ports = 10 generate
+
+with request_word select
+      request_decoder <="0000000001" when "00001",
+                        "0000000010" when "00011",
+                        "0000000100" when "00101",
+                        "0000001000" when "00111",
+                        "0000010000" when "01001",
+                        "0000100000" when "01011",
+                        "0001000000" when "01101",
+                        "0010000000" when "01111",
+                        "0100000000" when "10001",
+                        "1000000000" when "10011",
+                        "0000000000" when others;
+
+end generate switch10x10;
+
+
+-- switch 11 ports
+switch11x11 : if number_of_ports = 11 generate
+
+with request_word select
+      request_decoder <="00000000001" when "00001",
+                        "00000000010" when "00011",
+                        "00000000100" when "00101",
+                        "00000001000" when "00111",
+                        "00000010000" when "01001",
+                        "00000100000" when "01011",
+                        "00001000000" when "01101",
+                        "00010000000" when "01111",
+                        "00100000000" when "10001",
+                        "01000000000" when "10011",
+                        "10000000000" when "10101",
+                        "00000000000" when others;
+
+end generate switch11x11;
+
+
+-- switch 12 ports
+switch12x12 : if number_of_ports = 12 generate
+
+with request_word select
+      request_decoder <="000000000001" when "00001",
+                        "000000000010" when "00011",
+                        "000000000100" when "00101",
+                        "000000001000" when "00111",
+                        "000000010000" when "01001",
+                        "000000100000" when "01011",
+                        "000001000000" when "01101",
+                        "000010000000" when "01111",
+                        "000100000000" when "10001",
+                        "001000000000" when "10011",
+                        "010000000000" when "10101",
+                        "100000000000" when "10111",
+                        "000000000000" when others;
+
+end generate switch12x12;
+
+
+-- switch 13 ports
+switch13x13 : if number_of_ports = 13 generate
+
+with request_word select
+      request_decoder <="0000000000001" when "00001",
+                        "0000000000010" when "00011",
+                        "0000000000100" when "00101",
+                        "0000000001000" when "00111",
+                        "0000000010000" when "01001",
+                        "0000000100000" when "01011",
+                        "0000001000000" when "01101",
+                        "0000010000000" when "01111",
+                        "0000100000000" when "10001",
+                        "0001000000000" when "10011",
+                        "0010000000000" when "10101",
+                        "0100000000000" when "10111",
+                        "1000000000000" when "11001",
+                        "0000000000000" when others;
+
+end generate switch13x13;
+
+
+-- switch 14 ports
+switch14x14 : if number_of_ports = 14 generate
+
+with request_word select
+      request_decoder <="00000000000001" when "00001",
+                        "00000000000010" when "00011",
+                        "00000000000100" when "00101",
+                        "00000000001000" when "00111",
+                        "00000000010000" when "01001",
+                        "00000000100000" when "01011",
+                        "00000001000000" when "01101",
+                        "00000010000000" when "01111",
+                        "00000100000000" when "10001",
+                        "00001000000000" when "10011",
+                        "00010000000000" when "10101",
+                        "00100000000000" when "10111",
+                        "01000000000000" when "11001",
+                        "10000000000000" when "11011",
+                        "00000000000000" when others;
+
+end generate switch14x14;
+
+
+-- switch 15 ports
+switch15x15 : if number_of_ports = 15 generate
+
+with request_word select
+      request_decoder <="000000000000001" when "00001",
+                        "000000000000010" when "00011",
+                        "000000000000100" when "00101",
+                        "000000000001000" when "00111",
+                        "000000000010000" when "01001",
+                        "000000000100000" when "01011",
+                        "000000001000000" when "01101",
+                        "000000010000000" when "01111",
+                        "000000100000000" when "10001",
+                        "000001000000000" when "10011",
+                        "000010000000000" when "10101",
+                        "000100000000000" when "10111",
+                        "001000000000000" when "11001",
+                        "010000000000000" when "11011",
+                        "100000000000000" when "11101",
+                        "000000000000000" when others;
+
+end generate switch15x15;
+
+
+-- switch 16 ports
+switch16x16 : if number_of_ports = 16 generate
+
+with request_word select
+      request_decoder <="0000000000000001" when "00001",
+                        "0000000000000010" when "00011",
+                        "0000000000000100" when "00101",
+                        "0000000000001000" when "00111",
+                        "0000000000010000" when "01001",
+                        "0000000000100000" when "01011",
+                        "0000000001000000" when "01101",
+                        "0000000010000000" when "01111",
+                        "0000000100000000" when "10001",
+                        "0000001000000000" when "10011",
+                        "0000010000000000" when "10101",
+                        "0000100000000000" when "10111",
+                        "0001000000000000" when "11001",
+                        "0010000000000000" when "11011",
+                        "0100000000000000" when "11101",
+                        "1000000000000000" when "11111",
+                        "0000000000000000" when others;
+
+end generate switch16x16;									
+--latch du fifo de sortie ??
+pipeline_latch_process : process(clk)
+begin
+	if rising_edge(clk) then 
+	  if reset_signal = '1' then 
+	   pipeline_latch <= (others => '0');
+		 elsif pipeline_latch_en = '1' and cmd_exec='0' then
+		  pipeline_latch <= push_dout;
+		  elsif pipeline_latch_en = '1' and cmd_exec='1' then
+		  pipeline_latch <= cmd_data_signal;
+	  end if;
+	end if;
+end process;
+
+--latch qui memorise l'adresse de destination du packet
+
+request_latch_process : process(clk)
+begin
+	if rising_edge(clk) then
+		if reset_signal = '1' then
+		  request_latch <= (others => '0');
+		  elsif request_latch_en = '1' and cmd_in_en='0' then  --si la lecture de la destination est autorisée
+		  request_latch <=fifo_out_signal(3 downto 0); --fifo_out_signal(3) & fifo_out_signal(2) & fifo_out_signal(1) & fifo_out_signal(0);
+		  elsif cmd_in_en='1' and request_latch_en='1' then  --c'est une commande le port de dest est le même que le port d'entrée
+		   request_latch<=Port_ID(3 downto 0);  --car les ports commencent à 0
+		end if;
+	end if;
+end process;
+
+-- machine à etat de mealy qui depile les donnees dans le fifo
+--
+-- processus determinant l'etat futur
+pop_fsm_nsl : process(clk)
+begin 
+	if rising_edge(clk) then 
+	 if reset_signal = '1' then
+		pop_state <= state0;
+		data_counter <= (others => '0');
+	  elsif cmd_exec='0' then  --il ne faut pas exécuter cette MAE
+										-- lorsque l'autre est en cours 
+	  
+		  case pop_state is
+			when state0 => if cmd_in_en='0'  then --il ne faut pas exécuter les deux MAE ...
+									if fifo_empty_signal  ='0' then -- pile pas vide on doit dépiler									
+										pop_state <= WaitGrant;
+									end if;
+								else
+									pop_state <= CmdOn;
+								end if;
+			when CmdOn => if fifo_empty_signal='1' then
+								pop_state <= state0;
+								end if;
+			when WaitGrant => if port_granted = '1' then
+										--
+										pop_state <= ReqPort;
+								end if;					
+			when ReqPort => --if port_granted = '1' then
+										--
+										pop_state <= state1;
+								--end if;
+		
+			when state1 => if port_granted ='1' then --lecture de la longueur des données
+										data_counter <= fifo_out_signal;
+										if unsigned(fifo_out_signal)<=3 then 
+												ReadOk<='1';
+										else
+												readOk<='1';
+										end if;
+										pop_state <= state2;
+							      end if;
+										
+			when state2 => if port_granted='1' then 
+										if rd_en_signal ='1' and unsigned(data_counter)<= 3 then
+											data_counter <= data_counter - 1;
+											pop_state <= stpulse;
+											ReadOk<='1';
+										elsif rd_en_signal ='1' then
+										  data_counter <= data_counter - 1;
+										  pop_state <= state2;
+										  ReadOk<='1';
+										end if;
+									else
+										ReadOk<='0';
+									end if;
+			
+			when stpulse =>	if port_granted='1' then 
+											pop_state <= state3;		--pousser la dernière donnée dehors		
+											data_counter <= data_counter - 1;
+									end if;
+			
+			when state3 => 	
+										data_counter <= data_counter - 1;
+										pop_state <= state0;
+																						
+			when others => pop_state <= state0;
+		   end case;
+	 end if;
+	end if;
+end process;
+
+-- actions associées à chaque etat de la fsm de mealy
+pop_fsm_action : process(pop_state, fifo_out_signal,fifo_empty_signal, rd_en_signal,readok, port_granted )
+  begin   
+-- code fonctionnel	
+	case pop_state is
+		when state0 =>    dat_request_latch_en <= '0';  
+								dat_pipeline_latch_en <= rd_en_signal;
+								dat_fifo_read_signal <='0';
+								dat_request_decoder_en <= '0';
+								dat_data_out_pulse <= '0';
+								dat_priority_rotation <= '1';
+								dat_exec<='0';
+								push_dout<=fifo_out_signal;
+		when CmdOn =>		dat_request_latch_en <= '0';  
+								dat_pipeline_latch_en <= rd_en_signal;
+								dat_fifo_read_signal <='0';
+								dat_request_decoder_en <= '0';
+								dat_data_out_pulse <= '0';
+								dat_priority_rotation <= '1';
+								dat_exec<='0';
+								push_dout<=fifo_out_signal;
+		when WaitGrant =>	
+								dat_request_latch_en <='1'; --autoriser l'identification du port de destination
+								dat_pipeline_latch_en <= Port_granted; --pour le transmettre à travers le réseau
+								dat_fifo_read_signal <= '0';
+								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+								dat_data_out_pulse <= '0';     --transmettre le signal pour le dernier mot
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0);
+		when ReqPort =>	
+								dat_request_latch_en <='1'; --autoriser l'identification du port de destination
+								dat_pipeline_latch_en <= Port_granted; --pour le transmettre à travers le réseau
+								dat_fifo_read_signal <= Port_granted;
+								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+								dat_data_out_pulse <= '0';     --transmettre le signal pour le dernier mot
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0);
+							
+		when state1 =>    dat_request_latch_en <= '0';
+								dat_pipeline_latch_en <= rd_en_signal and port_granted;   
+								dat_fifo_read_signal <= rd_en_signal and port_granted;
+								dat_request_decoder_en <= '1';
+								dat_data_out_pulse <= '1';
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								push_dout<=fifo_out_signal;
+								
+	  when state2 =>    dat_request_latch_en <= '0';
+								dat_pipeline_latch_en <= rd_en_signal;  --autoriser la lecture du fifo en sortie
+								dat_fifo_read_signal <= readok;   
+								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+								dat_data_out_pulse <= readOk;
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								push_dout<=fifo_out_signal;
+								
+	  when stpulse =>    dat_request_latch_en <= '0'; --pousser la dernière donnée 
+								dat_pipeline_latch_en <= '0';  --autoriser la lecture du fifo en sortie
+								dat_fifo_read_signal <='0';   
+								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+								dat_data_out_pulse <= '1';  -- pousser le dernier mot
+								dat_priority_rotation <= '0';
+								dat_exec<='1';
+								push_dout<=fifo_out_signal;
+								
+		when state3 =>    dat_request_latch_en <= '0';
+								dat_pipeline_latch_en <= '0';
+								dat_priority_rotation <= '1';    -- libérer la priorité
+								dat_fifo_read_signal <= '0';
+								dat_request_decoder_en <= '0';   --libérer le décodeur
+								dat_data_out_pulse <= '0';
+								dat_exec<='0';
+								push_dout<=fifo_out_signal;
+		
+		when others =>    dat_request_latch_en <= '0';
+								dat_pipeline_latch_en <= '0';
+								dat_priority_rotation <= '1';
+								dat_fifo_read_signal <= '0';
+								dat_request_decoder_en <= '0';
+								dat_data_out_pulse <= '0';
+								dat_exec<='0';
+								push_dout<=fifo_out_signal;
+										
+		end case;
+ end process; 
+ -- traitement des commandes reçues par le switch
+fsm_cmd:process(clk,cmd_in_en)
+variable timeout : natural:=0;
+variable cmdcode : natural range 0 to 255;
+begin
+if rising_edge(clk) then
+   if reset_signal = '1' then
+	   cmdstate<=cmdstart;
+	else -- il ne faut pas traiter les cmdes et les données en même temps 
+	case cmdstate is
+	
+	   when cmdstart  =>
+				if cmd_in_en='1' and dat_exec='0' and fifo_empty_signal='0' then 
+				cmdstate<=cmdwait;
+				end if;
+		when cmdwait => if fifo_empty_signal='0' and port_granted ='1' then
+								
+									cmdstate<=cmdread;
+							else 
+								cmdstate<=cmdstart;
+							end if;
+		when cmdread =>
+				if port_granted ='1'then -- ne pas modifier l'état des priorités si on ne l'avait pas
+					cmdcode:= to_integer(unsigned(fifo_out_signal));
+					if cmdcode=1 then --code de getportid
+							cmdstate<=cmdsetdest;
+					else
+						if port_granted='1' then
+							cmdstate<=cmdend;
+						end if;
+					end if;
+				end if;
+		when cmdsetdest =>
+				if port_granted='1' then
+					cmdstate<=cmdsetcount;
+				end if;
+		when cmdsetcount =>
+				if port_granted='1' then
+					cmdstate<=cmdsetID;
+				end if;
+		when cmdsetID=>
+			if port_granted='1' then
+			cmdstate <=cmdpulse;
+			end if;
+		when cmdpulse =>
+			if port_granted='1' then
+			cmdstate <=cmdEnd;
+			end if;
+		when cmdend  =>
+			
+				cmdstate<=cmdstart; 
+			
+				
+	  
+	end case;
+  	end if;		
+end if;
+end process fsm_cmd;
+
+cmdaffect:process (cmdstate,fifo_empty_signal, port_granted, PORT_ID)
+begin
+case cmdstate is
+
+	when cmdstart =>
+						cmd_exec<='0';
+						cmd_pipeline_latch_en <='0';
+						cmd_priority_rotation <= '1';
+						cmd_request_latch_en<='0';
+						cmd_fifo_read_signal <= '0';
+						cmd_request_decoder_en <= '0';
+						cmd_data_signal<=(others=>'0');
+						cmd_data_out_pulse <= '0';
+	when cmdwait =>
+						cmd_exec<='1';
+						cmd_pipeline_latch_en <='0';
+						cmd_fifo_read_signal <= '0';
+						cmd_priority_rotation <= '1';    --sans priorité
+						cmd_request_latch_en<='0';
+						cmd_request_decoder_en <= not(fifo_empty_signal);   --demande d'émission
+						cmd_data_signal<=(others=>'0');
+						cmd_data_out_pulse <= '0';
+	when cmdread =>
+						cmd_exec<='1';
+						cmd_pipeline_latch_en <= '1';
+						cmd_fifo_read_signal <= '0';
+						cmd_request_latch_en<='1';    --mémoriser l'adresse de destination
+						cmd_request_decoder_en <= '1';                   --demande d'émission
+						cmd_data_out_pulse <= '0';
+						cmd_priority_rotation <= '0';                    --avec priorité
+						--cmd_data_signal<=(others=>'0');
+						cmd_data_signal<=Port_ID;  
+	when cmdsetdest  =>
+						--cmd_request_decoder_en <= '1';
+						cmd_exec<='1';
+						cmd_pipeline_latch_en <='1';
+						cmd_fifo_read_signal <='0';
+						cmd_request_latch_en<='0';
+						cmd_request_decoder_en <= '1';          --autoriser le decodeur à activer le dernier bit de request
+						cmd_data_out_pulse <= '0';
+						cmd_priority_rotation <= '0';
+						cmd_data_signal<=Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
+						
+	when cmdSetId =>
+						--cmd_request_decoder_en <= '1';
+						cmd_exec<='1';
+						cmd_pipeline_latch_en <='1';
+						cmd_fifo_read_signal <='0';
+						cmd_request_latch_en<='0';
+						cmd_request_decoder_en <= '1';          --autoriser le decodeur à activer le dernier bit de request
+						cmd_data_out_pulse <= '1';
+						cmd_priority_rotation <= '0';
+						cmd_data_signal<=Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
+											
+	when cmdsetcount =>
+								 
+						cmd_exec<='1';   
+						cmd_pipeline_latch_en <='1';
+						cmd_fifo_read_signal <='1';
+						cmd_request_latch_en<='0';
+						cmd_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+						cmd_data_out_pulse <= port_granted;
+						cmd_priority_rotation <= '0';
+						cmd_data_signal<=STD_LOGIC_VECTOR(to_unsigned(3,8));
+	
+	when cmdpulse =>	cmd_exec<='1';
+						cmd_pipeline_latch_en <='0';
+						cmd_fifo_read_signal <='0';
+						cmd_request_latch_en<='0';
+						cmd_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+						cmd_data_out_pulse <= port_granted;     --s'assurer que la dernière donnée est bien lue
+						cmd_priority_rotation <= '0';
+								--cmd_data_signal<=Port_ID ;
+						cmd_data_signal<=Port_ID; 
+						
+	when cmdend =>
+								cmd_exec<='0';
+								cmd_request_latch_en <= '0';
+								cmd_pipeline_latch_en <= '0';
+								cmd_fifo_read_signal <= '0';
+								cmd_request_latch_en<='0';
+								cmd_request_decoder_en <= '0';
+								cmd_data_out_pulse <= '0';
+								cmd_priority_rotation <= '1';
+								cmd_data_signal<=(others=>'0');
+								
+								
+end case ;
+end process cmdaffect;
+
+end Behavioral;
+
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.vhi
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.vhi	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.vhi	(revision 20)
@@ -0,0 +1,39 @@
+
+-- VHDL Instantiation Created from source file INPUT_PORT_MODULE.vhd -- 15:22:33 06/19/2011
+--
+-- Notes: 
+-- 1) This instantiation template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the instantiated module
+-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
+
+	COMPONENT INPUT_PORT_MODULE
+	PORT(
+		data_in : IN std_logic_vector(7 downto 0);
+		data_in_en : IN std_logic;
+		reset : IN std_logic;
+		clk : IN std_logic;
+		grant : IN std_logic_vector(4 downto 1);          
+		request : OUT std_logic_vector(4 downto 1);
+		fifo_full : OUT std_logic;
+		fifo_empty : OUT std_logic;
+		priority_rotation : OUT std_logic;
+		data_out : OUT std_logic_vector(7 downto 0);
+		data_out_pulse : OUT std_logic
+		);
+	END COMPONENT;
+
+	Inst_INPUT_PORT_MODULE: INPUT_PORT_MODULE PORT MAP(
+		data_in => ,
+		data_in_en => ,
+		reset => ,
+		clk => ,
+		request => ,
+		grant => ,
+		fifo_full => ,
+		fifo_empty => ,
+		priority_rotation => ,
+		data_out => ,
+		data_out_pulse => 
+	);
+
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.xst
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.xst	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE.xst	(revision 20)
@@ -0,0 +1,55 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn INPUT_PORT_MODULE.prj
+-ifmt mixed
+-ofn INPUT_PORT_MODULE
+-ofmt NGC
+-p xc3s1200e-4-fg320
+-top INPUT_PORT_MODULE
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso INPUT_PORT_MODULE.lso
+-keep_hierarchy NO
+-netlist_hierarchy as_optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract YES
+-resource_sharing YES
+-async_to_sync NO
+-iobuf YES
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE_summary.html
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE_summary.html	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE_summary.html	(revision 20)
@@ -0,0 +1,107 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>GENERIC_16_16 Project Status (06/19/2011 - 19:25:38)</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>GENERIC_16_16.ise</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>Synthesized</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>INPUT_PORT_MODULE</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc3s1200e-4fg320</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 11.1</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD>Xilinx Default (unlocked)</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>
+<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
+<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slices</TD>
+<TD ALIGN=RIGHT>49</TD>
+<TD ALIGN=RIGHT>8672</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
+<TD ALIGN=RIGHT>57</TD>
+<TD ALIGN=RIGHT>17344</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
+<TD ALIGN=RIGHT>94</TD>
+<TD ALIGN=RIGHT>17344</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
+<TD ALIGN=RIGHT>31</TD>
+<TD ALIGN=RIGHT>250</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>12%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BRAMs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>28</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>3%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of GCLKs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>24</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>4%</TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16\INPUT_PORT_MODULE.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>dim. 19. juin 14:27:18 2011</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 06/19/2011 - 19:26:32</center>
+</BODY></HTML>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE_vhdl.prj
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE_vhdl.prj	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE_vhdl.prj	(revision 20)
@@ -0,0 +1,3 @@
+vhdl work "C:\Documents and Settings\GENERAL\Bureau\GENERIC_16_16\RAM_256.vhd"
+vhdl work "C:\Documents and Settings\GENERAL\Bureau\GENERIC_16_16\FIFO_256_FWFT.vhd"
+vhdl work "C:\Documents and Settings\GENERAL\Bureau\GENERIC_16_16\INPUT_PORT_MODULE.vhd"
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE_xst.xrpt
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE_xst.xrpt	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/INPUT_PORT_MODULE_xst.xrpt	(revision 20)
@@ -0,0 +1,133 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="nt" product="ISE" version="11.1">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="Xst" timeStamp="Sun Jun 19 14:27:08 2011">
+    <section stringID="User_Env">
+      <table stringID="User_EnvVar">
+        <column stringID="variable"/>
+        <column stringID="value"/>
+        <row stringID="row" value="0">
+          <item stringID="variable" value="XILINX"/>
+          <item stringID="value" value="C:\Xilinx\11.1\ISE"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="variable" value="XILINX_PLANAHEAD"/>
+          <item stringID="value" value="C:\Xilinx\11.1\PlanAhead"/>
+        </row>
+      </table>
+      <item stringID="User_EnvOs" value="OS Information">
+        <item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
+        <item stringID="User_EnvOsrelease" value="Service Pack 2  (build 2600)"/>
+      </item>
+      <item stringID="User_EnvHost" value="get-1c498a90fcb"/>
+      <table stringID="User_EnvCpu">
+        <column stringID="arch"/>
+        <column stringID="speed"/>
+        <row stringID="row" value="0">
+          <item stringID="arch" value="        Intel(R) Pentium(R) M processor 1400MHz"/>
+          <item stringID="speed" value="1398 MHz"/>
+        </row>
+      </table>
+    </section>
+    <section stringID="XST_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_RAMS" value="1"></item>
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="1"></item>
+      <item dataType="int" stringID="XST_COUNTERS" value="3"></item>
+      <item dataType="int" stringID="XST_REGISTERS" value="6">
+        <item dataType="int" stringID="XST_1BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_4BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_8BIT_REGISTER" value="4"/>
+      </item>
+      <item dataType="int" stringID="XST_COMPARATORS" value="1"></item>
+    </section>
+    <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_FSMS" value="2"/>
+      <item dataType="int" stringID="XST_RAMS" value="1"></item>
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="1"></item>
+      <item dataType="int" stringID="XST_COUNTERS" value="3"></item>
+      <item dataType="int" stringID="XST_REGISTERS" value="29">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="29"/>
+      </item>
+      <item dataType="int" stringID="XST_COMPARATORS" value="1"></item>
+    </section>
+    <section stringID="XST_FINAL_REGISTER_REPORT">
+      <item dataType="int" stringID="XST_REGISTERS" value="57">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="57"/>
+      </item>
+    </section>
+    <section stringID="XST_PARTITION_REPORT">
+      <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
+        <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+      </section>
+    </section>
+    <section stringID="XST_FINAL_REPORT">
+      <section stringID="XST_FINAL_RESULTS">
+        <item stringID="XST_RTL_TOP_LEVEL_OUTPUT_FILE_NAME" value="INPUT_PORT_MODULE.ngr"/>
+        <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="INPUT_PORT_MODULE"/>
+        <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
+        <item stringID="XST_OPTIMIZATION_GOAL" value="Speed"/>
+        <item stringID="XST_KEEP_HIERARCHY" value="NO"/>
+      </section>
+      <section stringID="XST_DESIGN_STATISTICS">
+        <item stringID="XST_IOS" value="31"/>
+      </section>
+      <section stringID="XST_CELL_USAGE">
+        <item dataType="int" stringID="XST_BELS" value="142">
+          <item dataType="int" stringID="XST_GND" value="1"/>
+          <item dataType="int" stringID="XST_INV" value="2"/>
+          <item dataType="int" stringID="XST_LUT1" value="14"/>
+          <item dataType="int" stringID="XST_LUT2" value="4"/>
+          <item dataType="int" stringID="XST_LUT3" value="20"/>
+          <item dataType="int" stringID="XST_LUT3D" value="1"/>
+          <item dataType="int" stringID="XST_LUT3L" value="2"/>
+          <item dataType="int" stringID="XST_LUT4" value="44"/>
+          <item dataType="int" stringID="XST_LUT4D" value="5"/>
+          <item dataType="int" stringID="XST_LUT4L" value="2"/>
+          <item dataType="int" stringID="XST_MUXCY" value="21"/>
+          <item dataType="int" stringID="XST_MUXF5" value="1"/>
+          <item dataType="int" stringID="XST_VCC" value="1"/>
+          <item dataType="int" stringID="XST_XORCY" value="24"/>
+        </item>
+        <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="57">
+          <item dataType="int" stringID="XST_FDE" value="8"/>
+          <item dataType="int" stringID="XST_FDR" value="3"/>
+          <item dataType="int" stringID="XST_FDRE" value="37"/>
+          <item dataType="int" stringID="XST_FDRS" value="9"/>
+        </item>
+        <item dataType="int" stringID="XST_RAMS" value="1">
+          <item dataType="int" stringID="XST_RAMB16S9S9" value="1"/>
+        </item>
+        <item dataType="int" stringID="XST_CLOCK_BUFFERS" value="1">
+          <item dataType="int" stringID="XST_BUFGP" value="1"/>
+        </item>
+        <item dataType="int" stringID="XST_IO_BUFFERS" value="30">
+          <item dataType="int" stringID="XST_IBUF" value="14"/>
+          <item dataType="int" stringID="XST_OBUF" value="16"/>
+        </item>
+      </section>
+    </section>
+    <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
+      <item stringID="XST_SELECTED_DEVICE" value="3s1200efg320-4"/>
+      <item AVAILABLE="8672" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="49"/>
+      <item AVAILABLE="17344" dataType="int" label="Number of Slice Flip Flops" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="57"/>
+      <item AVAILABLE="17344" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="94"/>
+      <item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="31"/>
+      <item AVAILABLE="250" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="31"/>
+      <item AVAILABLE="28" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="1"/>
+      <item AVAILABLE="24" dataType="int" label="Number of GCLKs" stringID="XST_NUMBER_OF_GCLKS" value="1"/>
+    </section>
+    <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
+      <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+    </section>
+    <section stringID="XST_ERRORS_STATISTICS">
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="2"/>
+    </section>
+  </application>
+
+</document>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/OUTPUT_PORT_MODULE.cmd_log
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/OUTPUT_PORT_MODULE.cmd_log	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/OUTPUT_PORT_MODULE.cmd_log	(revision 20)
@@ -0,0 +1,3 @@
+vhdtdtfi -lib work RAM_256.vhd -lib work FIFO_256_FWFT.vhd -lib work OUTPUT_PORT_MODULE.vhd -prj GENERIC_16_16 -o OUTPUT_PORT_MODULE.spl -module OUTPUT_PORT_MODULE -template d:/Xilinx/12.3/ISE_DS/ISE//data/splfile.tft -deleteonerror 
+spl2sym -intstyle ise -family virtex5 OUTPUT_PORT_MODULE.spl {C:/Core MPI/SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.sym} 
+vhdtdtfi -prj GENERIC_16_16 -o "C:/Core MPI/SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhi" -lib work "C:/Core MPI/SWITCH_GENERIC_16_16//OUTPUT_PORT_MODULE.vhd" -module OUTPUT_PORT_MODULE -template d:/Xilinx/12.3/ISE_DS/ISE//data/vhdlinst.tft -deleteonerror 
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/OUTPUT_PORT_MODULE.sym
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/OUTPUT_PORT_MODULE.sym	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/OUTPUT_PORT_MODULE.sym	(revision 20)
@@ -0,0 +1,35 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="OUTPUT_PORT_MODULE">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2012-2-10T16:50:49</timestamp>
+    <pin polarity="Input" x="0" y="-288" name="reset" />
+    <pin polarity="Input" x="0" y="-224" name="clk" />
+    <pin polarity="Input" x="0" y="-160" name="wr_en" />
+    <pin polarity="Input" x="0" y="-96" name="rd_out_en" />
+    <pin polarity="Input" x="0" y="-32" name="data_in(7:0)" />
+    <pin polarity="Output" x="432" y="-288" name="fifo_full" />
+    <pin polarity="Output" x="432" y="-160" name="data_avalaible" />
+    <pin polarity="Output" x="432" y="-32" name="data_out(7:0)" />
+    <graph>
+        <rect width="304" x="64" y="-320" height="320" />
+        <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="216" y="-328" type="symbol" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin reset" />
+        <line x2="0" y1="-288" y2="-288" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin clk" />
+        <line x2="0" y1="-224" y2="-224" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin wr_en" />
+        <line x2="0" y1="-160" y2="-160" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin rd_out_en" />
+        <line x2="0" y1="-96" y2="-96" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin data_in(7:0)" />
+        <rect width="64" x="0" y="-44" height="24" />
+        <line x2="0" y1="-32" y2="-32" x1="64" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-288" type="pin fifo_full" />
+        <line x2="432" y1="-288" y2="-288" x1="368" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-160" type="pin data_avalaible" />
+        <line x2="432" y1="-160" y2="-160" x1="368" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-32" type="pin data_out(7:0)" />
+        <rect width="64" x="368" y="-44" height="24" />
+        <line x2="432" y1="-32" y2="-32" x1="368" />
+    </graph>
+</symbol>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/OUTPUT_PORT_MODULE.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/OUTPUT_PORT_MODULE.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/OUTPUT_PORT_MODULE.vhd	(revision 20)
@@ -0,0 +1,75 @@
+
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    09:29:48 04/18/2011 
+-- Design Name: 
+-- Module Name:    OUTPUT_PORT_MODULE - Behavioral_description 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description:
+-- cette version du module de sortie se limite à une instance du fifo ordinaire 
+-- les données son emise en sortie à chaque cycle d'horloge
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+Library NocLib;
+use NocLib.CoreTypes.all;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity OUTPUT_PORT_MODULE is
+    Port ( data_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+           reset : in  STD_LOGIC;
+           clk : in  STD_LOGIC;
+           wr_en : in  STD_LOGIC;
+           data_out : out  STD_LOGIC_VECTOR (Word-1 downto 0);
+			  fifo_full : out std_logic;
+			  data_avalaible : out std_logic;
+			  rd_out_en : in  STD_LOGIC);
+end OUTPUT_PORT_MODULE;
+
+architecture Behavioral_description of OUTPUT_PORT_MODULE is
+-- declaration du FIFO 64 octets
+component FIFO_256_FWFT
+	port (
+	clk: IN std_logic;
+	din: IN std_logic_VECTOR(Word-1 downto 0);
+	rd_en: IN std_logic;
+	srst: IN std_logic;
+	wr_en: IN std_logic;
+	dout: OUT std_logic_VECTOR(Word-1 downto 0);
+	empty: OUT std_logic;
+	full: OUT std_logic);
+end component;
+--definition du type etat pour les fsm
+signal empty_signal : std_logic;	
+begin
+-- instantiation du FIFO_64
+ OUTPUT_PORT_FIFO : FIFO_256_FWFT
+		port map (
+			clk => clk,
+			din => data_in,
+			rd_en => rd_out_en,
+			srst => reset,
+			wr_en => wr_en,
+			dout => data_out,
+			empty => empty_signal,
+			full => fifo_full);
+			
+data_avalaible <= not empty_signal;
+
+end Behavioral_description;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/PortRam.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/PortRam.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/PortRam.vhd	(revision 20)
@@ -0,0 +1,74 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: GAMOM NGOUNOU ROland Christian
+-- 
+-- Create Date:    12:49:02 02/02/2012 
+-- Design Name: 
+-- Module Name:    Portdata - arch_portdata 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use ieee.numeric_std.all;
+--USE ieee.std_logic_arith.all;
+
+
+entity Portdata is
+generic (N:Natural:=8);
+    Port ( clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+           wr_en : in  STD_LOGIC;
+           rd_en : in  STD_LOGIC;
+           datain : in  STD_LOGIC_VECTOR (N-1 downto 0);
+           dataout : out  STD_LOGIC_VECTOR (N-1 downto 0);
+           address : in  STD_LOGIC_VECTOR (3 downto 0));
+end Portdata;
+
+architecture arch_portdata of Portdata is
+
+Type Ram_type is array (0 to 3) of std_logic_vector (N-1 downto 0);
+constant zero : integer :=0;
+constant Zero_log:STD_LOGIC_VECTOR:=STD_LOGIC_VECTOR(to_unsigned(zero,N));
+constant portid:STD_LOGIC_VECTOR:="00000001";
+signal RAM : Ram_type;
+
+constant max_address : natural:=15;
+signal address_counter : natural := 0;
+begin
+
+dataout <= RAM(address_counter);
+process (clk)
+  begin
+     if rising_edge(clk) then
+        if reset = '1' then
+            address_counter <= 0;
+				for address_counter in 1 to max_address 			--la mémoire d'adresse 0 contient 
+				loop															-- l'ID du port
+					RAM(address_counter)<=(others=>'0');
+				end loop;
+				RAM(0)<=portid;                                -- portid est une valeur fixé par le générateur de port
+        elsif rd_en='1' and wr_en='0' then 
+		     
+			  RAM(to_integer(unsigned(address)))<=datain;
+		  
+		  elsif rd_en='0' and wr_en='1' then
+			 dataout <= RAM(to_integer(unsigned(address)));
+			  
+		  end if;
+    end if;
+  end process;
+end arch_portdata;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Proto_receiv.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Proto_receiv.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Proto_receiv.vhd	(revision 20)
@@ -0,0 +1,149 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    17:03:41 10/22/2012 
+-- Design Name: 
+-- Module Name:    Proto_receiv - ReceiveProto 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use work.CoreTypes.all;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Proto_receiv is
+ generic (sizemem : natural := 64);
+ port (
+ clk,reset : in std_logic;
+ fifo_empty,fifo_full : in std_logic;
+ rcv_start : in std_logic; --début de la réception
+ rcv_ack :in std_logic;   -- acquittement de la réception
+ rcv_comp : out std_logic; -- fin de la réception
+  pop : out std_logic:='0';
+ fifo_out : in std_logic_vector(Word-1 downto 0);
+ mem :out memory(0 to sizemem-1));
+end Proto_receiv;
+
+architecture ReceiveProto of Proto_receiv is
+type typ_receiv is (r_wait,r_head,r_len,r_glen,r_data,r_pulse,r_end);
+
+			 signal spush,spop :  std_logic:='0';
+          SIGNAL data_in:  std_logic_vector(7 downto 0);
+			 signal etrec :typ_receiv;
+begin
+
+proc_receiv : process (clk,reset)
+variable dlen,i: natural range 0 to 255 :=0;
+
+	begin
+	if reset='1' then 
+				 etrec<=r_wait;
+				 
+				else  
+						if rising_edge(clk) then -- le process s'exécute sur chaque front 
+															-- montant de l'horloge
+						case etrec is
+						when r_wait  =>
+							
+							i:=0;
+							if fifo_empty='0' and rcv_start='1' then
+							
+							etrec<=r_head;
+							mem(0)<=fifo_out;
+							
+							end if;
+						when r_head  =>
+							mem(0)<=fifo_out;  --l'en-tête
+							
+							etrec<=r_len;
+							
+						
+						when r_len =>
+								dlen:=to_integer(unsigned(fifo_out));
+								mem(1)<=fifo_out; -- la longueur
+								etrec<=r_data;
+								
+								i:=1;
+								
+						when r_data  =>
+								if fifo_empty='0' then
+									if i<dlen-3 then
+										i:=i+1;
+										mem(i)<=fifo_out;
+										
+										
+									else
+										etrec<=r_pulse;
+										
+										mem(i+1)<=fifo_out;
+									end if;
+									-- time out à prévoir ici
+								end if;
+						when r_pulse =>
+								etrec<=r_end;
+								
+						when r_end  =>
+								if rcv_ack='1' then
+									etrec<=r_wait;
+								end if;
+								
+						when others =>
+								
+								
+								etrec<=r_wait;
+						end case;
+						end if;
+				end if;
+	end process;
+	
+	pop<=spop;
+	
+rec_value : process (etrec)
+begin
+case etrec is
+					when r_wait  =>
+						spop<='0';
+						rcv_comp<='0';
+					when r_head  =>
+							
+							spop<='1';
+							rcv_comp<='0';
+--					when r_sync =>
+--							spop<='1';
+--							rcv_comp<='0';
+					when r_len =>
+							spop<='1';
+					when r_data =>
+							spop<='1';
+					when r_pulse =>
+								spop<='0';
+								rcv_comp<='1';
+					when r_end =>
+							spop<='0';
+							rcv_comp<='1';
+					when others =>
+							spop<='0';
+							rcv_comp<='0';
+				end case;
+	end process;
+end ReceiveProto;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/RAM_256.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/RAM_256.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/RAM_256.vhd	(revision 20)
@@ -0,0 +1,68 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    18:54:08 04/19/2011 
+-- Design Name: 
+-- Module Name:    RAM_64 - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: SYNTHESE d'une RAM 256 octet par inferation
+-- la ram possède un port d'écriture et un port de lecture
+-- le port primaire est à lecture et ecrite et le port secondaire à lecture seule
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--Library NocLib;
+--use NocLib.CoreTypes.all;
+use work.CoreTypes.all;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity RAM_256 is
+    Port ( clka, clkb : in std_logic;
+			  wea : in std_logic;
+			  ena, enb : in std_logic;
+			  addra, addrb : in std_logic_vector(Word-1 downto 0);
+			  dia : in std_logic_vector(Word-1 downto 0);
+			  dob : out std_logic_vector(Word-1 downto 0));
+end RAM_256;
+
+architecture Behavioral of RAM_256 is
+	type ram_type is array (255 downto 0) of std_logic_vector (Word-1 downto 0);
+	signal RAM: ram_type;
+begin
+ process (clka)
+	begin
+		if clka'event and clka = '1' then
+			if ena = '1' then
+				if wea = '1' then
+					RAM(conv_integer(addra)) <= dia;
+				end if;
+			end if;
+		 end if;
+ end process;
+ 
+ process (clkb)
+	begin
+		if clkb'event and clkb = '1' then
+			if enb = '1' then
+				dob <= RAM(conv_integer(addrb)) ;
+			end if;
+		end if;
+ end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER10_10.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER10_10.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER10_10.VHD	(revision 20)
@@ -0,0 +1,1212 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler10_10 is
+    Port ( Request : in  STD_LOGIC_VECTOR (100 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (10 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (10 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (100 downto 1));
+end Scheduler10_10;
+
+architecture Behavioral of Scheduler10_10 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(19 downto 1) of STD_LOGIC_VECTOR(10 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (19 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(100 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(100 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 1023 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(11)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(12)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(13)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(14)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(15)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(16)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(17)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(18)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) or Signal_grant(19)(9); --  Grant(1,9)
+Grant(10)  <= Signal_grant(10)(10) ;                      --  Grant(1,10)
+Grant(11)  <= Signal_grant(2)(1) or Signal_grant(12)(1); --  Grant(2,1)
+Grant(12)  <= Signal_grant(3)(2) or Signal_grant(13)(2); --  Grant(2,2)
+Grant(13)  <= Signal_grant(4)(3) or Signal_grant(14)(3); --  Grant(2,3)
+Grant(14)  <= Signal_grant(5)(4) or Signal_grant(15)(4); --  Grant(2,4)
+Grant(15)  <= Signal_grant(6)(5) or Signal_grant(16)(5); --  Grant(2,5)
+Grant(16)  <= Signal_grant(7)(6) or Signal_grant(17)(6); --  Grant(2,6)
+Grant(17)  <= Signal_grant(8)(7) or Signal_grant(18)(7); --  Grant(2,7)
+Grant(18)  <= Signal_grant(9)(8) or Signal_grant(19)(8); --  Grant(2,8)
+Grant(19)  <= Signal_grant(10)(9) ;                      --  Grant(2,9)
+Grant(20)  <= Signal_grant(1)(10) or Signal_grant(11)(10); --  Grant(2,10)
+Grant(21)  <= Signal_grant(3)(1) or Signal_grant(13)(1); --  Grant(3,1)
+Grant(22)  <= Signal_grant(4)(2) or Signal_grant(14)(2); --  Grant(3,2)
+Grant(23)  <= Signal_grant(5)(3) or Signal_grant(15)(3); --  Grant(3,3)
+Grant(24)  <= Signal_grant(6)(4) or Signal_grant(16)(4); --  Grant(3,4)
+Grant(25)  <= Signal_grant(7)(5) or Signal_grant(17)(5); --  Grant(3,5)
+Grant(26)  <= Signal_grant(8)(6) or Signal_grant(18)(6); --  Grant(3,6)
+Grant(27)  <= Signal_grant(9)(7) or Signal_grant(19)(7); --  Grant(3,7)
+Grant(28)  <= Signal_grant(10)(8) ;                      --  Grant(3,8)
+Grant(29)  <= Signal_grant(1)(9) or Signal_grant(11)(9); --  Grant(3,9)
+Grant(30)  <= Signal_grant(2)(10) or Signal_grant(12)(10); --  Grant(3,10)
+Grant(31)  <= Signal_grant(4)(1) or Signal_grant(14)(1); --  Grant(4,1)
+Grant(32)  <= Signal_grant(5)(2) or Signal_grant(15)(2); --  Grant(4,2)
+Grant(33)  <= Signal_grant(6)(3) or Signal_grant(16)(3); --  Grant(4,3)
+Grant(34)  <= Signal_grant(7)(4) or Signal_grant(17)(4); --  Grant(4,4)
+Grant(35)  <= Signal_grant(8)(5) or Signal_grant(18)(5); --  Grant(4,5)
+Grant(36)  <= Signal_grant(9)(6) or Signal_grant(19)(6); --  Grant(4,6)
+Grant(37)  <= Signal_grant(10)(7) ;                      --  Grant(4,7)
+Grant(38)  <= Signal_grant(1)(8) or Signal_grant(11)(8); --  Grant(4,8)
+Grant(39)  <= Signal_grant(2)(9) or Signal_grant(12)(9); --  Grant(4,9)
+Grant(40)  <= Signal_grant(3)(10) or Signal_grant(13)(10); --  Grant(4,10)
+Grant(41)  <= Signal_grant(5)(1) or Signal_grant(15)(1); --  Grant(5,1)
+Grant(42)  <= Signal_grant(6)(2) or Signal_grant(16)(2); --  Grant(5,2)
+Grant(43)  <= Signal_grant(7)(3) or Signal_grant(17)(3); --  Grant(5,3)
+Grant(44)  <= Signal_grant(8)(4) or Signal_grant(18)(4); --  Grant(5,4)
+Grant(45)  <= Signal_grant(9)(5) or Signal_grant(19)(5); --  Grant(5,5)
+Grant(46)  <= Signal_grant(10)(6) ;                      --  Grant(5,6)
+Grant(47)  <= Signal_grant(1)(7) or Signal_grant(11)(7); --  Grant(5,7)
+Grant(48)  <= Signal_grant(2)(8) or Signal_grant(12)(8); --  Grant(5,8)
+Grant(49)  <= Signal_grant(3)(9) or Signal_grant(13)(9); --  Grant(5,9)
+Grant(50)  <= Signal_grant(4)(10) or Signal_grant(14)(10); --  Grant(5,10)
+Grant(51)  <= Signal_grant(6)(1) or Signal_grant(16)(1); --  Grant(6,1)
+Grant(52)  <= Signal_grant(7)(2) or Signal_grant(17)(2); --  Grant(6,2)
+Grant(53)  <= Signal_grant(8)(3) or Signal_grant(18)(3); --  Grant(6,3)
+Grant(54)  <= Signal_grant(9)(4) or Signal_grant(19)(4); --  Grant(6,4)
+Grant(55)  <= Signal_grant(10)(5) ;                      --  Grant(6,5)
+Grant(56)  <= Signal_grant(1)(6) or Signal_grant(11)(6); --  Grant(6,6)
+Grant(57)  <= Signal_grant(2)(7) or Signal_grant(12)(7); --  Grant(6,7)
+Grant(58)  <= Signal_grant(3)(8) or Signal_grant(13)(8); --  Grant(6,8)
+Grant(59)  <= Signal_grant(4)(9) or Signal_grant(14)(9); --  Grant(6,9)
+Grant(60)  <= Signal_grant(5)(10) or Signal_grant(15)(10); --  Grant(6,10)
+Grant(61)  <= Signal_grant(7)(1) or Signal_grant(17)(1); --  Grant(7,1)
+Grant(62)  <= Signal_grant(8)(2) or Signal_grant(18)(2); --  Grant(7,2)
+Grant(63)  <= Signal_grant(9)(3) or Signal_grant(19)(3); --  Grant(7,3)
+Grant(64)  <= Signal_grant(10)(4) ;                      --  Grant(7,4)
+Grant(65)  <= Signal_grant(1)(5) or Signal_grant(11)(5); --  Grant(7,5)
+Grant(66)  <= Signal_grant(2)(6) or Signal_grant(12)(6); --  Grant(7,6)
+Grant(67)  <= Signal_grant(3)(7) or Signal_grant(13)(7); --  Grant(7,7)
+Grant(68)  <= Signal_grant(4)(8) or Signal_grant(14)(8); --  Grant(7,8)
+Grant(69)  <= Signal_grant(5)(9) or Signal_grant(15)(9); --  Grant(7,9)
+Grant(70)  <= Signal_grant(6)(10) or Signal_grant(16)(10); --  Grant(7,10)
+Grant(71)  <= Signal_grant(8)(1) or Signal_grant(18)(1); --  Grant(8,1)
+Grant(72)  <= Signal_grant(9)(2) or Signal_grant(19)(2); --  Grant(8,2)
+Grant(73)  <= Signal_grant(10)(3) ;                      --  Grant(8,3)
+Grant(74)  <= Signal_grant(1)(4) or Signal_grant(11)(4); --  Grant(8,4)
+Grant(75)  <= Signal_grant(2)(5) or Signal_grant(12)(5); --  Grant(8,5)
+Grant(76)  <= Signal_grant(3)(6) or Signal_grant(13)(6); --  Grant(8,6)
+Grant(77)  <= Signal_grant(4)(7) or Signal_grant(14)(7); --  Grant(8,7)
+Grant(78)  <= Signal_grant(5)(8) or Signal_grant(15)(8); --  Grant(8,8)
+Grant(79)  <= Signal_grant(6)(9) or Signal_grant(16)(9); --  Grant(8,9)
+Grant(80)  <= Signal_grant(7)(10) or Signal_grant(17)(10); --  Grant(8,10)
+Grant(81)  <= Signal_grant(9)(1) or Signal_grant(19)(1); --  Grant(9,1)
+Grant(82)  <= Signal_grant(10)(2) ;                      --  Grant(9,2)
+Grant(83)  <= Signal_grant(1)(3) or Signal_grant(11)(3); --  Grant(9,3)
+Grant(84)  <= Signal_grant(2)(4) or Signal_grant(12)(4); --  Grant(9,4)
+Grant(85)  <= Signal_grant(3)(5) or Signal_grant(13)(5); --  Grant(9,5)
+Grant(86)  <= Signal_grant(4)(6) or Signal_grant(14)(6); --  Grant(9,6)
+Grant(87)  <= Signal_grant(5)(7) or Signal_grant(15)(7); --  Grant(9,7)
+Grant(88)  <= Signal_grant(6)(8) or Signal_grant(16)(8); --  Grant(9,8)
+Grant(89)  <= Signal_grant(7)(9) or Signal_grant(17)(9); --  Grant(9,9)
+Grant(90)  <= Signal_grant(8)(10) or Signal_grant(18)(10); --  Grant(9,10)
+Grant(91)  <= Signal_grant(10)(1) ;                      --  Grant(10,1)
+Grant(92)  <= Signal_grant(1)(2) or Signal_grant(11)(2); --  Grant(10,2)
+Grant(93)  <= Signal_grant(2)(3) or Signal_grant(12)(3); --  Grant(10,3)
+Grant(94)  <= Signal_grant(3)(4) or Signal_grant(13)(4); --  Grant(10,4)
+Grant(95)  <= Signal_grant(4)(5) or Signal_grant(14)(5); --  Grant(10,5)
+Grant(96)  <= Signal_grant(5)(6) or Signal_grant(15)(6); --  Grant(10,6)
+Grant(97)  <= Signal_grant(6)(7) or Signal_grant(16)(7); --  Grant(10,7)
+Grant(98)  <= Signal_grant(7)(8) or Signal_grant(17)(8); --  Grant(10,8)
+Grant(99)  <= Signal_grant(8)(9) or Signal_grant(18)(9); --  Grant(10,9)
+Grant(100)  <= Signal_grant(9)(10) or Signal_grant(19)(10); --  Grant(10,10)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(92), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(83), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(74), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(65), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(56), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(47), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(38), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(29), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+Arbiter_1_10 : Arbiter
+
+PORT MAP (Request => Request(20), North => High, West => High, P => Signal_priority(19), Fifo_full => Fifo_full(10),  
+South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(1)(1), West => east_2_west(1)(10), P => Signal_priority(18), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+Arbiter_2_10 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10),  
+South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(2)(1), West => east_2_west(2)(10), P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+Arbiter_3_10 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10),  
+South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(3)(1), West => east_2_west(3)(10), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+Arbiter_4_10 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10),  
+South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(4)(1), West => east_2_west(4)(10), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+Arbiter_5_10 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10),  
+South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(5)(1), West => east_2_west(5)(10), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+Arbiter_6_10 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10),  
+South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(6)(1), West => east_2_west(6)(10), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+Arbiter_7_10 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10),  
+South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(7)(1), West => east_2_west(7)(10), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+Arbiter_8_10 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10),  
+South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(8)(1), West => east_2_west(8)(10), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+Arbiter_9_10 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10),  
+South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(9)(1), West => east_2_west(9)(10), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+Arbiter_10_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10),  
+South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(10)(1), West => east_2_west(10)(10), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+Arbiter_11_10 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10),  
+South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(11)(1), West => east_2_west(11)(10), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+Arbiter_12_10 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10),  
+South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(12)(1), West => east_2_west(12)(10), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+Arbiter_13_10 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10),  
+South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(13)(1), West => east_2_west(13)(10), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+Arbiter_14_10 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10),  
+South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(14)(1), West => east_2_west(14)(10), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+Arbiter_15_10 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10),  
+South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(15)(1), West => east_2_west(15)(10), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+Arbiter_16_10 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10),  
+South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(16)(1), West => east_2_west(16)(10), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+Arbiter_17_10 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10),  
+South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); 
+
+-------------------------- Diagonale n° 18 
+
+
+Arbiter_18_1 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(17)(1), West => east_2_west(17)(10), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); 
+
+Arbiter_18_2 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); 
+
+Arbiter_18_3 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); 
+
+Arbiter_18_4 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); 
+
+Arbiter_18_5 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); 
+
+Arbiter_18_6 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); 
+
+Arbiter_18_7 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); 
+
+Arbiter_18_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); 
+
+Arbiter_18_9 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); 
+
+Arbiter_18_10 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10),  
+South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); 
+
+-------------------------- Diagonale n° 19 
+
+
+Arbiter_19_1 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(18)(1), West => east_2_west(18)(10), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); 
+
+Arbiter_19_2 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); 
+
+Arbiter_19_3 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); 
+
+Arbiter_19_4 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); 
+
+Arbiter_19_5 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); 
+
+Arbiter_19_6 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); 
+
+Arbiter_19_7 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); 
+
+Arbiter_19_8 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); 
+
+Arbiter_19_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); 
+
+Arbiter_19_10 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10),  
+South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "1111111111000000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "1111111111000000000" => Signal_priority <= "0111111111100000000";
+		       when "0111111111100000000" => Signal_priority <= "0011111111110000000";
+		       when "0011111111110000000" => Signal_priority <= "0001111111111000000";
+		       when "0001111111111000000" => Signal_priority <= "0000111111111100000";
+		       when "0000111111111100000" => Signal_priority <= "0000011111111110000";
+		       when "0000011111111110000" => Signal_priority <= "0000001111111111000";
+		       when "0000001111111111000" => Signal_priority <= "0000000111111111100";
+		       when "0000000111111111100" => Signal_priority <= "0000000011111111110";
+		       when "0000000011111111110" => Signal_priority <= "0000000001111111111";
+		       when "0000000001111111111" => Signal_priority <= "1111111111000000000";
+		       when others    => Signal_priority <= "1111111111000000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER11_11.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER11_11.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER11_11.VHD	(revision 20)
@@ -0,0 +1,1445 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler11_11 is
+    Port ( Request : in  STD_LOGIC_VECTOR (121 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (11 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (11 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (121 downto 1));
+end Scheduler11_11;
+
+architecture Behavioral of Scheduler11_11 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(21 downto 1) of STD_LOGIC_VECTOR(11 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (21 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(121 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(121 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 2047 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(12)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(13)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(14)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(15)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(16)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(17)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(18)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(19)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) or Signal_grant(20)(9); --  Grant(1,9)
+Grant(10)  <= Signal_grant(10)(10) or Signal_grant(21)(10); --  Grant(1,10)
+Grant(11)  <= Signal_grant(11)(11) ;                      --  Grant(1,11)
+Grant(12)  <= Signal_grant(2)(1) or Signal_grant(13)(1); --  Grant(2,1)
+Grant(13)  <= Signal_grant(3)(2) or Signal_grant(14)(2); --  Grant(2,2)
+Grant(14)  <= Signal_grant(4)(3) or Signal_grant(15)(3); --  Grant(2,3)
+Grant(15)  <= Signal_grant(5)(4) or Signal_grant(16)(4); --  Grant(2,4)
+Grant(16)  <= Signal_grant(6)(5) or Signal_grant(17)(5); --  Grant(2,5)
+Grant(17)  <= Signal_grant(7)(6) or Signal_grant(18)(6); --  Grant(2,6)
+Grant(18)  <= Signal_grant(8)(7) or Signal_grant(19)(7); --  Grant(2,7)
+Grant(19)  <= Signal_grant(9)(8) or Signal_grant(20)(8); --  Grant(2,8)
+Grant(20)  <= Signal_grant(10)(9) or Signal_grant(21)(9); --  Grant(2,9)
+Grant(21)  <= Signal_grant(11)(10) ;                      --  Grant(2,10)
+Grant(22)  <= Signal_grant(1)(11) or Signal_grant(12)(11); --  Grant(2,11)
+Grant(23)  <= Signal_grant(3)(1) or Signal_grant(14)(1); --  Grant(3,1)
+Grant(24)  <= Signal_grant(4)(2) or Signal_grant(15)(2); --  Grant(3,2)
+Grant(25)  <= Signal_grant(5)(3) or Signal_grant(16)(3); --  Grant(3,3)
+Grant(26)  <= Signal_grant(6)(4) or Signal_grant(17)(4); --  Grant(3,4)
+Grant(27)  <= Signal_grant(7)(5) or Signal_grant(18)(5); --  Grant(3,5)
+Grant(28)  <= Signal_grant(8)(6) or Signal_grant(19)(6); --  Grant(3,6)
+Grant(29)  <= Signal_grant(9)(7) or Signal_grant(20)(7); --  Grant(3,7)
+Grant(30)  <= Signal_grant(10)(8) or Signal_grant(21)(8); --  Grant(3,8)
+Grant(31)  <= Signal_grant(11)(9) ;                      --  Grant(3,9)
+Grant(32)  <= Signal_grant(1)(10) or Signal_grant(12)(10); --  Grant(3,10)
+Grant(33)  <= Signal_grant(2)(11) or Signal_grant(13)(11); --  Grant(3,11)
+Grant(34)  <= Signal_grant(4)(1) or Signal_grant(15)(1); --  Grant(4,1)
+Grant(35)  <= Signal_grant(5)(2) or Signal_grant(16)(2); --  Grant(4,2)
+Grant(36)  <= Signal_grant(6)(3) or Signal_grant(17)(3); --  Grant(4,3)
+Grant(37)  <= Signal_grant(7)(4) or Signal_grant(18)(4); --  Grant(4,4)
+Grant(38)  <= Signal_grant(8)(5) or Signal_grant(19)(5); --  Grant(4,5)
+Grant(39)  <= Signal_grant(9)(6) or Signal_grant(20)(6); --  Grant(4,6)
+Grant(40)  <= Signal_grant(10)(7) or Signal_grant(21)(7); --  Grant(4,7)
+Grant(41)  <= Signal_grant(11)(8) ;                      --  Grant(4,8)
+Grant(42)  <= Signal_grant(1)(9) or Signal_grant(12)(9); --  Grant(4,9)
+Grant(43)  <= Signal_grant(2)(10) or Signal_grant(13)(10); --  Grant(4,10)
+Grant(44)  <= Signal_grant(3)(11) or Signal_grant(14)(11); --  Grant(4,11)
+Grant(45)  <= Signal_grant(5)(1) or Signal_grant(16)(1); --  Grant(5,1)
+Grant(46)  <= Signal_grant(6)(2) or Signal_grant(17)(2); --  Grant(5,2)
+Grant(47)  <= Signal_grant(7)(3) or Signal_grant(18)(3); --  Grant(5,3)
+Grant(48)  <= Signal_grant(8)(4) or Signal_grant(19)(4); --  Grant(5,4)
+Grant(49)  <= Signal_grant(9)(5) or Signal_grant(20)(5); --  Grant(5,5)
+Grant(50)  <= Signal_grant(10)(6) or Signal_grant(21)(6); --  Grant(5,6)
+Grant(51)  <= Signal_grant(11)(7) ;                      --  Grant(5,7)
+Grant(52)  <= Signal_grant(1)(8) or Signal_grant(12)(8); --  Grant(5,8)
+Grant(53)  <= Signal_grant(2)(9) or Signal_grant(13)(9); --  Grant(5,9)
+Grant(54)  <= Signal_grant(3)(10) or Signal_grant(14)(10); --  Grant(5,10)
+Grant(55)  <= Signal_grant(4)(11) or Signal_grant(15)(11); --  Grant(5,11)
+Grant(56)  <= Signal_grant(6)(1) or Signal_grant(17)(1); --  Grant(6,1)
+Grant(57)  <= Signal_grant(7)(2) or Signal_grant(18)(2); --  Grant(6,2)
+Grant(58)  <= Signal_grant(8)(3) or Signal_grant(19)(3); --  Grant(6,3)
+Grant(59)  <= Signal_grant(9)(4) or Signal_grant(20)(4); --  Grant(6,4)
+Grant(60)  <= Signal_grant(10)(5) or Signal_grant(21)(5); --  Grant(6,5)
+Grant(61)  <= Signal_grant(11)(6) ;                      --  Grant(6,6)
+Grant(62)  <= Signal_grant(1)(7) or Signal_grant(12)(7); --  Grant(6,7)
+Grant(63)  <= Signal_grant(2)(8) or Signal_grant(13)(8); --  Grant(6,8)
+Grant(64)  <= Signal_grant(3)(9) or Signal_grant(14)(9); --  Grant(6,9)
+Grant(65)  <= Signal_grant(4)(10) or Signal_grant(15)(10); --  Grant(6,10)
+Grant(66)  <= Signal_grant(5)(11) or Signal_grant(16)(11); --  Grant(6,11)
+Grant(67)  <= Signal_grant(7)(1) or Signal_grant(18)(1); --  Grant(7,1)
+Grant(68)  <= Signal_grant(8)(2) or Signal_grant(19)(2); --  Grant(7,2)
+Grant(69)  <= Signal_grant(9)(3) or Signal_grant(20)(3); --  Grant(7,3)
+Grant(70)  <= Signal_grant(10)(4) or Signal_grant(21)(4); --  Grant(7,4)
+Grant(71)  <= Signal_grant(11)(5) ;                      --  Grant(7,5)
+Grant(72)  <= Signal_grant(1)(6) or Signal_grant(12)(6); --  Grant(7,6)
+Grant(73)  <= Signal_grant(2)(7) or Signal_grant(13)(7); --  Grant(7,7)
+Grant(74)  <= Signal_grant(3)(8) or Signal_grant(14)(8); --  Grant(7,8)
+Grant(75)  <= Signal_grant(4)(9) or Signal_grant(15)(9); --  Grant(7,9)
+Grant(76)  <= Signal_grant(5)(10) or Signal_grant(16)(10); --  Grant(7,10)
+Grant(77)  <= Signal_grant(6)(11) or Signal_grant(17)(11); --  Grant(7,11)
+Grant(78)  <= Signal_grant(8)(1) or Signal_grant(19)(1); --  Grant(8,1)
+Grant(79)  <= Signal_grant(9)(2) or Signal_grant(20)(2); --  Grant(8,2)
+Grant(80)  <= Signal_grant(10)(3) or Signal_grant(21)(3); --  Grant(8,3)
+Grant(81)  <= Signal_grant(11)(4) ;                      --  Grant(8,4)
+Grant(82)  <= Signal_grant(1)(5) or Signal_grant(12)(5); --  Grant(8,5)
+Grant(83)  <= Signal_grant(2)(6) or Signal_grant(13)(6); --  Grant(8,6)
+Grant(84)  <= Signal_grant(3)(7) or Signal_grant(14)(7); --  Grant(8,7)
+Grant(85)  <= Signal_grant(4)(8) or Signal_grant(15)(8); --  Grant(8,8)
+Grant(86)  <= Signal_grant(5)(9) or Signal_grant(16)(9); --  Grant(8,9)
+Grant(87)  <= Signal_grant(6)(10) or Signal_grant(17)(10); --  Grant(8,10)
+Grant(88)  <= Signal_grant(7)(11) or Signal_grant(18)(11); --  Grant(8,11)
+Grant(89)  <= Signal_grant(9)(1) or Signal_grant(20)(1); --  Grant(9,1)
+Grant(90)  <= Signal_grant(10)(2) or Signal_grant(21)(2); --  Grant(9,2)
+Grant(91)  <= Signal_grant(11)(3) ;                      --  Grant(9,3)
+Grant(92)  <= Signal_grant(1)(4) or Signal_grant(12)(4); --  Grant(9,4)
+Grant(93)  <= Signal_grant(2)(5) or Signal_grant(13)(5); --  Grant(9,5)
+Grant(94)  <= Signal_grant(3)(6) or Signal_grant(14)(6); --  Grant(9,6)
+Grant(95)  <= Signal_grant(4)(7) or Signal_grant(15)(7); --  Grant(9,7)
+Grant(96)  <= Signal_grant(5)(8) or Signal_grant(16)(8); --  Grant(9,8)
+Grant(97)  <= Signal_grant(6)(9) or Signal_grant(17)(9); --  Grant(9,9)
+Grant(98)  <= Signal_grant(7)(10) or Signal_grant(18)(10); --  Grant(9,10)
+Grant(99)  <= Signal_grant(8)(11) or Signal_grant(19)(11); --  Grant(9,11)
+Grant(100)  <= Signal_grant(10)(1) or Signal_grant(21)(1); --  Grant(10,1)
+Grant(101)  <= Signal_grant(11)(2) ;                      --  Grant(10,2)
+Grant(102)  <= Signal_grant(1)(3) or Signal_grant(12)(3); --  Grant(10,3)
+Grant(103)  <= Signal_grant(2)(4) or Signal_grant(13)(4); --  Grant(10,4)
+Grant(104)  <= Signal_grant(3)(5) or Signal_grant(14)(5); --  Grant(10,5)
+Grant(105)  <= Signal_grant(4)(6) or Signal_grant(15)(6); --  Grant(10,6)
+Grant(106)  <= Signal_grant(5)(7) or Signal_grant(16)(7); --  Grant(10,7)
+Grant(107)  <= Signal_grant(6)(8) or Signal_grant(17)(8); --  Grant(10,8)
+Grant(108)  <= Signal_grant(7)(9) or Signal_grant(18)(9); --  Grant(10,9)
+Grant(109)  <= Signal_grant(8)(10) or Signal_grant(19)(10); --  Grant(10,10)
+Grant(110)  <= Signal_grant(9)(11) or Signal_grant(20)(11); --  Grant(10,11)
+Grant(111)  <= Signal_grant(11)(1) ;                      --  Grant(11,1)
+Grant(112)  <= Signal_grant(1)(2) or Signal_grant(12)(2); --  Grant(11,2)
+Grant(113)  <= Signal_grant(2)(3) or Signal_grant(13)(3); --  Grant(11,3)
+Grant(114)  <= Signal_grant(3)(4) or Signal_grant(14)(4); --  Grant(11,4)
+Grant(115)  <= Signal_grant(4)(5) or Signal_grant(15)(5); --  Grant(11,5)
+Grant(116)  <= Signal_grant(5)(6) or Signal_grant(16)(6); --  Grant(11,6)
+Grant(117)  <= Signal_grant(6)(7) or Signal_grant(17)(7); --  Grant(11,7)
+Grant(118)  <= Signal_grant(7)(8) or Signal_grant(18)(8); --  Grant(11,8)
+Grant(119)  <= Signal_grant(8)(9) or Signal_grant(19)(9); --  Grant(11,9)
+Grant(120)  <= Signal_grant(9)(10) or Signal_grant(20)(10); --  Grant(11,10)
+Grant(121)  <= Signal_grant(10)(11) or Signal_grant(21)(11); --  Grant(11,11)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(112), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(102), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(92), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(82), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(72), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(62), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(52), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(42), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+Arbiter_1_10 : Arbiter
+
+PORT MAP (Request => Request(32), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(10),  
+South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); 
+
+Arbiter_1_11 : Arbiter
+
+PORT MAP (Request => Request(22), North => High, West => High, P => Signal_priority(21), Fifo_full => Fifo_full(11),  
+South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(1)(1), West => east_2_west(1)(11), P => Signal_priority(20), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+Arbiter_2_10 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10),  
+South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); 
+
+Arbiter_2_11 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11),  
+South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(2)(1), West => east_2_west(2)(11), P => Signal_priority(19), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+Arbiter_3_10 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10),  
+South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); 
+
+Arbiter_3_11 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11),  
+South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(3)(1), West => east_2_west(3)(11), P => Signal_priority(18), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+Arbiter_4_10 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10),  
+South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); 
+
+Arbiter_4_11 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11),  
+South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(4)(1), West => east_2_west(4)(11), P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+Arbiter_5_10 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10),  
+South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); 
+
+Arbiter_5_11 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11),  
+South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(5)(1), West => east_2_west(5)(11), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+Arbiter_6_10 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10),  
+South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); 
+
+Arbiter_6_11 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11),  
+South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(6)(1), West => east_2_west(6)(11), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+Arbiter_7_10 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10),  
+South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); 
+
+Arbiter_7_11 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11),  
+South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(7)(1), West => east_2_west(7)(11), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+Arbiter_8_10 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10),  
+South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); 
+
+Arbiter_8_11 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11),  
+South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(8)(1), West => east_2_west(8)(11), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+Arbiter_9_10 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10),  
+South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); 
+
+Arbiter_9_11 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11),  
+South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(9)(1), West => east_2_west(9)(11), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+Arbiter_10_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10),  
+South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); 
+
+Arbiter_10_11 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11),  
+South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(10)(1), West => east_2_west(10)(11), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+Arbiter_11_10 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10),  
+South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); 
+
+Arbiter_11_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11),  
+South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(11)(1), West => east_2_west(11)(11), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+Arbiter_12_10 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10),  
+South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); 
+
+Arbiter_12_11 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11),  
+South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(12)(1), West => east_2_west(12)(11), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+Arbiter_13_10 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10),  
+South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); 
+
+Arbiter_13_11 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11),  
+South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(13)(1), West => east_2_west(13)(11), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+Arbiter_14_10 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10),  
+South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); 
+
+Arbiter_14_11 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11),  
+South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(14)(1), West => east_2_west(14)(11), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+Arbiter_15_10 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10),  
+South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); 
+
+Arbiter_15_11 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11),  
+South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(15)(1), West => east_2_west(15)(11), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+Arbiter_16_10 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10),  
+South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); 
+
+Arbiter_16_11 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11),  
+South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(16)(1), West => east_2_west(16)(11), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+Arbiter_17_10 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10),  
+South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); 
+
+Arbiter_17_11 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11),  
+South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); 
+
+-------------------------- Diagonale n° 18 
+
+
+Arbiter_18_1 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(17)(1), West => east_2_west(17)(11), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); 
+
+Arbiter_18_2 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); 
+
+Arbiter_18_3 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); 
+
+Arbiter_18_4 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); 
+
+Arbiter_18_5 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); 
+
+Arbiter_18_6 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); 
+
+Arbiter_18_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); 
+
+Arbiter_18_8 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); 
+
+Arbiter_18_9 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); 
+
+Arbiter_18_10 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10),  
+South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); 
+
+Arbiter_18_11 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11),  
+South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); 
+
+-------------------------- Diagonale n° 19 
+
+
+Arbiter_19_1 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(18)(1), West => east_2_west(18)(11), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); 
+
+Arbiter_19_2 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); 
+
+Arbiter_19_3 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); 
+
+Arbiter_19_4 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); 
+
+Arbiter_19_5 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); 
+
+Arbiter_19_6 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); 
+
+Arbiter_19_7 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); 
+
+Arbiter_19_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); 
+
+Arbiter_19_9 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); 
+
+Arbiter_19_10 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10),  
+South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); 
+
+Arbiter_19_11 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11),  
+South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); 
+
+-------------------------- Diagonale n° 20 
+
+
+Arbiter_20_1 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(19)(1), West => east_2_west(19)(11), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); 
+
+Arbiter_20_2 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); 
+
+Arbiter_20_3 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); 
+
+Arbiter_20_4 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); 
+
+Arbiter_20_5 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); 
+
+Arbiter_20_6 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); 
+
+Arbiter_20_7 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); 
+
+Arbiter_20_8 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); 
+
+Arbiter_20_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); 
+
+Arbiter_20_10 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10),  
+South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); 
+
+Arbiter_20_11 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11),  
+South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); 
+
+-------------------------- Diagonale n° 21 
+
+
+Arbiter_21_1 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(20)(1), West => east_2_west(20)(11), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); 
+
+Arbiter_21_2 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); 
+
+Arbiter_21_3 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); 
+
+Arbiter_21_4 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); 
+
+Arbiter_21_5 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); 
+
+Arbiter_21_6 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); 
+
+Arbiter_21_7 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); 
+
+Arbiter_21_8 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); 
+
+Arbiter_21_9 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); 
+
+Arbiter_21_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10),  
+South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); 
+
+Arbiter_21_11 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11),  
+South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "111111111110000000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "111111111110000000000" => Signal_priority <= "011111111111000000000";
+		       when "011111111111000000000" => Signal_priority <= "001111111111100000000";
+		       when "001111111111100000000" => Signal_priority <= "000111111111110000000";
+		       when "000111111111110000000" => Signal_priority <= "000011111111111000000";
+		       when "000011111111111000000" => Signal_priority <= "000001111111111100000";
+		       when "000001111111111100000" => Signal_priority <= "000000111111111110000";
+		       when "000000111111111110000" => Signal_priority <= "000000011111111111000";
+		       when "000000011111111111000" => Signal_priority <= "000000001111111111100";
+		       when "000000001111111111100" => Signal_priority <= "000000000111111111110";
+		       when "000000000111111111110" => Signal_priority <= "000000000011111111111";
+		       when "000000000011111111111" => Signal_priority <= "111111111110000000000";
+		       when others    => Signal_priority <= "111111111110000000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER12_12.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER12_12.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER12_12.VHD	(revision 20)
@@ -0,0 +1,1700 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler12_12 is
+    Port ( Request : in  STD_LOGIC_VECTOR (144 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (12 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (12 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (144 downto 1));
+end Scheduler12_12;
+
+architecture Behavioral of Scheduler12_12 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(23 downto 1) of STD_LOGIC_VECTOR(12 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (23 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(144 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(144 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 4095 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(13)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(14)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(15)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(16)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(17)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(18)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(19)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(20)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) or Signal_grant(21)(9); --  Grant(1,9)
+Grant(10)  <= Signal_grant(10)(10) or Signal_grant(22)(10); --  Grant(1,10)
+Grant(11)  <= Signal_grant(11)(11) or Signal_grant(23)(11); --  Grant(1,11)
+Grant(12)  <= Signal_grant(12)(12) ;                      --  Grant(1,12)
+Grant(13)  <= Signal_grant(2)(1) or Signal_grant(14)(1); --  Grant(2,1)
+Grant(14)  <= Signal_grant(3)(2) or Signal_grant(15)(2); --  Grant(2,2)
+Grant(15)  <= Signal_grant(4)(3) or Signal_grant(16)(3); --  Grant(2,3)
+Grant(16)  <= Signal_grant(5)(4) or Signal_grant(17)(4); --  Grant(2,4)
+Grant(17)  <= Signal_grant(6)(5) or Signal_grant(18)(5); --  Grant(2,5)
+Grant(18)  <= Signal_grant(7)(6) or Signal_grant(19)(6); --  Grant(2,6)
+Grant(19)  <= Signal_grant(8)(7) or Signal_grant(20)(7); --  Grant(2,7)
+Grant(20)  <= Signal_grant(9)(8) or Signal_grant(21)(8); --  Grant(2,8)
+Grant(21)  <= Signal_grant(10)(9) or Signal_grant(22)(9); --  Grant(2,9)
+Grant(22)  <= Signal_grant(11)(10) or Signal_grant(23)(10); --  Grant(2,10)
+Grant(23)  <= Signal_grant(12)(11) ;                      --  Grant(2,11)
+Grant(24)  <= Signal_grant(1)(12) or Signal_grant(13)(12); --  Grant(2,12)
+Grant(25)  <= Signal_grant(3)(1) or Signal_grant(15)(1); --  Grant(3,1)
+Grant(26)  <= Signal_grant(4)(2) or Signal_grant(16)(2); --  Grant(3,2)
+Grant(27)  <= Signal_grant(5)(3) or Signal_grant(17)(3); --  Grant(3,3)
+Grant(28)  <= Signal_grant(6)(4) or Signal_grant(18)(4); --  Grant(3,4)
+Grant(29)  <= Signal_grant(7)(5) or Signal_grant(19)(5); --  Grant(3,5)
+Grant(30)  <= Signal_grant(8)(6) or Signal_grant(20)(6); --  Grant(3,6)
+Grant(31)  <= Signal_grant(9)(7) or Signal_grant(21)(7); --  Grant(3,7)
+Grant(32)  <= Signal_grant(10)(8) or Signal_grant(22)(8); --  Grant(3,8)
+Grant(33)  <= Signal_grant(11)(9) or Signal_grant(23)(9); --  Grant(3,9)
+Grant(34)  <= Signal_grant(12)(10) ;                      --  Grant(3,10)
+Grant(35)  <= Signal_grant(1)(11) or Signal_grant(13)(11); --  Grant(3,11)
+Grant(36)  <= Signal_grant(2)(12) or Signal_grant(14)(12); --  Grant(3,12)
+Grant(37)  <= Signal_grant(4)(1) or Signal_grant(16)(1); --  Grant(4,1)
+Grant(38)  <= Signal_grant(5)(2) or Signal_grant(17)(2); --  Grant(4,2)
+Grant(39)  <= Signal_grant(6)(3) or Signal_grant(18)(3); --  Grant(4,3)
+Grant(40)  <= Signal_grant(7)(4) or Signal_grant(19)(4); --  Grant(4,4)
+Grant(41)  <= Signal_grant(8)(5) or Signal_grant(20)(5); --  Grant(4,5)
+Grant(42)  <= Signal_grant(9)(6) or Signal_grant(21)(6); --  Grant(4,6)
+Grant(43)  <= Signal_grant(10)(7) or Signal_grant(22)(7); --  Grant(4,7)
+Grant(44)  <= Signal_grant(11)(8) or Signal_grant(23)(8); --  Grant(4,8)
+Grant(45)  <= Signal_grant(12)(9) ;                      --  Grant(4,9)
+Grant(46)  <= Signal_grant(1)(10) or Signal_grant(13)(10); --  Grant(4,10)
+Grant(47)  <= Signal_grant(2)(11) or Signal_grant(14)(11); --  Grant(4,11)
+Grant(48)  <= Signal_grant(3)(12) or Signal_grant(15)(12); --  Grant(4,12)
+Grant(49)  <= Signal_grant(5)(1) or Signal_grant(17)(1); --  Grant(5,1)
+Grant(50)  <= Signal_grant(6)(2) or Signal_grant(18)(2); --  Grant(5,2)
+Grant(51)  <= Signal_grant(7)(3) or Signal_grant(19)(3); --  Grant(5,3)
+Grant(52)  <= Signal_grant(8)(4) or Signal_grant(20)(4); --  Grant(5,4)
+Grant(53)  <= Signal_grant(9)(5) or Signal_grant(21)(5); --  Grant(5,5)
+Grant(54)  <= Signal_grant(10)(6) or Signal_grant(22)(6); --  Grant(5,6)
+Grant(55)  <= Signal_grant(11)(7) or Signal_grant(23)(7); --  Grant(5,7)
+Grant(56)  <= Signal_grant(12)(8) ;                      --  Grant(5,8)
+Grant(57)  <= Signal_grant(1)(9) or Signal_grant(13)(9); --  Grant(5,9)
+Grant(58)  <= Signal_grant(2)(10) or Signal_grant(14)(10); --  Grant(5,10)
+Grant(59)  <= Signal_grant(3)(11) or Signal_grant(15)(11); --  Grant(5,11)
+Grant(60)  <= Signal_grant(4)(12) or Signal_grant(16)(12); --  Grant(5,12)
+Grant(61)  <= Signal_grant(6)(1) or Signal_grant(18)(1); --  Grant(6,1)
+Grant(62)  <= Signal_grant(7)(2) or Signal_grant(19)(2); --  Grant(6,2)
+Grant(63)  <= Signal_grant(8)(3) or Signal_grant(20)(3); --  Grant(6,3)
+Grant(64)  <= Signal_grant(9)(4) or Signal_grant(21)(4); --  Grant(6,4)
+Grant(65)  <= Signal_grant(10)(5) or Signal_grant(22)(5); --  Grant(6,5)
+Grant(66)  <= Signal_grant(11)(6) or Signal_grant(23)(6); --  Grant(6,6)
+Grant(67)  <= Signal_grant(12)(7) ;                      --  Grant(6,7)
+Grant(68)  <= Signal_grant(1)(8) or Signal_grant(13)(8); --  Grant(6,8)
+Grant(69)  <= Signal_grant(2)(9) or Signal_grant(14)(9); --  Grant(6,9)
+Grant(70)  <= Signal_grant(3)(10) or Signal_grant(15)(10); --  Grant(6,10)
+Grant(71)  <= Signal_grant(4)(11) or Signal_grant(16)(11); --  Grant(6,11)
+Grant(72)  <= Signal_grant(5)(12) or Signal_grant(17)(12); --  Grant(6,12)
+Grant(73)  <= Signal_grant(7)(1) or Signal_grant(19)(1); --  Grant(7,1)
+Grant(74)  <= Signal_grant(8)(2) or Signal_grant(20)(2); --  Grant(7,2)
+Grant(75)  <= Signal_grant(9)(3) or Signal_grant(21)(3); --  Grant(7,3)
+Grant(76)  <= Signal_grant(10)(4) or Signal_grant(22)(4); --  Grant(7,4)
+Grant(77)  <= Signal_grant(11)(5) or Signal_grant(23)(5); --  Grant(7,5)
+Grant(78)  <= Signal_grant(12)(6) ;                      --  Grant(7,6)
+Grant(79)  <= Signal_grant(1)(7) or Signal_grant(13)(7); --  Grant(7,7)
+Grant(80)  <= Signal_grant(2)(8) or Signal_grant(14)(8); --  Grant(7,8)
+Grant(81)  <= Signal_grant(3)(9) or Signal_grant(15)(9); --  Grant(7,9)
+Grant(82)  <= Signal_grant(4)(10) or Signal_grant(16)(10); --  Grant(7,10)
+Grant(83)  <= Signal_grant(5)(11) or Signal_grant(17)(11); --  Grant(7,11)
+Grant(84)  <= Signal_grant(6)(12) or Signal_grant(18)(12); --  Grant(7,12)
+Grant(85)  <= Signal_grant(8)(1) or Signal_grant(20)(1); --  Grant(8,1)
+Grant(86)  <= Signal_grant(9)(2) or Signal_grant(21)(2); --  Grant(8,2)
+Grant(87)  <= Signal_grant(10)(3) or Signal_grant(22)(3); --  Grant(8,3)
+Grant(88)  <= Signal_grant(11)(4) or Signal_grant(23)(4); --  Grant(8,4)
+Grant(89)  <= Signal_grant(12)(5) ;                      --  Grant(8,5)
+Grant(90)  <= Signal_grant(1)(6) or Signal_grant(13)(6); --  Grant(8,6)
+Grant(91)  <= Signal_grant(2)(7) or Signal_grant(14)(7); --  Grant(8,7)
+Grant(92)  <= Signal_grant(3)(8) or Signal_grant(15)(8); --  Grant(8,8)
+Grant(93)  <= Signal_grant(4)(9) or Signal_grant(16)(9); --  Grant(8,9)
+Grant(94)  <= Signal_grant(5)(10) or Signal_grant(17)(10); --  Grant(8,10)
+Grant(95)  <= Signal_grant(6)(11) or Signal_grant(18)(11); --  Grant(8,11)
+Grant(96)  <= Signal_grant(7)(12) or Signal_grant(19)(12); --  Grant(8,12)
+Grant(97)  <= Signal_grant(9)(1) or Signal_grant(21)(1); --  Grant(9,1)
+Grant(98)  <= Signal_grant(10)(2) or Signal_grant(22)(2); --  Grant(9,2)
+Grant(99)  <= Signal_grant(11)(3) or Signal_grant(23)(3); --  Grant(9,3)
+Grant(100)  <= Signal_grant(12)(4) ;                      --  Grant(9,4)
+Grant(101)  <= Signal_grant(1)(5) or Signal_grant(13)(5); --  Grant(9,5)
+Grant(102)  <= Signal_grant(2)(6) or Signal_grant(14)(6); --  Grant(9,6)
+Grant(103)  <= Signal_grant(3)(7) or Signal_grant(15)(7); --  Grant(9,7)
+Grant(104)  <= Signal_grant(4)(8) or Signal_grant(16)(8); --  Grant(9,8)
+Grant(105)  <= Signal_grant(5)(9) or Signal_grant(17)(9); --  Grant(9,9)
+Grant(106)  <= Signal_grant(6)(10) or Signal_grant(18)(10); --  Grant(9,10)
+Grant(107)  <= Signal_grant(7)(11) or Signal_grant(19)(11); --  Grant(9,11)
+Grant(108)  <= Signal_grant(8)(12) or Signal_grant(20)(12); --  Grant(9,12)
+Grant(109)  <= Signal_grant(10)(1) or Signal_grant(22)(1); --  Grant(10,1)
+Grant(110)  <= Signal_grant(11)(2) or Signal_grant(23)(2); --  Grant(10,2)
+Grant(111)  <= Signal_grant(12)(3) ;                      --  Grant(10,3)
+Grant(112)  <= Signal_grant(1)(4) or Signal_grant(13)(4); --  Grant(10,4)
+Grant(113)  <= Signal_grant(2)(5) or Signal_grant(14)(5); --  Grant(10,5)
+Grant(114)  <= Signal_grant(3)(6) or Signal_grant(15)(6); --  Grant(10,6)
+Grant(115)  <= Signal_grant(4)(7) or Signal_grant(16)(7); --  Grant(10,7)
+Grant(116)  <= Signal_grant(5)(8) or Signal_grant(17)(8); --  Grant(10,8)
+Grant(117)  <= Signal_grant(6)(9) or Signal_grant(18)(9); --  Grant(10,9)
+Grant(118)  <= Signal_grant(7)(10) or Signal_grant(19)(10); --  Grant(10,10)
+Grant(119)  <= Signal_grant(8)(11) or Signal_grant(20)(11); --  Grant(10,11)
+Grant(120)  <= Signal_grant(9)(12) or Signal_grant(21)(12); --  Grant(10,12)
+Grant(121)  <= Signal_grant(11)(1) or Signal_grant(23)(1); --  Grant(11,1)
+Grant(122)  <= Signal_grant(12)(2) ;                      --  Grant(11,2)
+Grant(123)  <= Signal_grant(1)(3) or Signal_grant(13)(3); --  Grant(11,3)
+Grant(124)  <= Signal_grant(2)(4) or Signal_grant(14)(4); --  Grant(11,4)
+Grant(125)  <= Signal_grant(3)(5) or Signal_grant(15)(5); --  Grant(11,5)
+Grant(126)  <= Signal_grant(4)(6) or Signal_grant(16)(6); --  Grant(11,6)
+Grant(127)  <= Signal_grant(5)(7) or Signal_grant(17)(7); --  Grant(11,7)
+Grant(128)  <= Signal_grant(6)(8) or Signal_grant(18)(8); --  Grant(11,8)
+Grant(129)  <= Signal_grant(7)(9) or Signal_grant(19)(9); --  Grant(11,9)
+Grant(130)  <= Signal_grant(8)(10) or Signal_grant(20)(10); --  Grant(11,10)
+Grant(131)  <= Signal_grant(9)(11) or Signal_grant(21)(11); --  Grant(11,11)
+Grant(132)  <= Signal_grant(10)(12) or Signal_grant(22)(12); --  Grant(11,12)
+Grant(133)  <= Signal_grant(12)(1) ;                      --  Grant(12,1)
+Grant(134)  <= Signal_grant(1)(2) or Signal_grant(13)(2); --  Grant(12,2)
+Grant(135)  <= Signal_grant(2)(3) or Signal_grant(14)(3); --  Grant(12,3)
+Grant(136)  <= Signal_grant(3)(4) or Signal_grant(15)(4); --  Grant(12,4)
+Grant(137)  <= Signal_grant(4)(5) or Signal_grant(16)(5); --  Grant(12,5)
+Grant(138)  <= Signal_grant(5)(6) or Signal_grant(17)(6); --  Grant(12,6)
+Grant(139)  <= Signal_grant(6)(7) or Signal_grant(18)(7); --  Grant(12,7)
+Grant(140)  <= Signal_grant(7)(8) or Signal_grant(19)(8); --  Grant(12,8)
+Grant(141)  <= Signal_grant(8)(9) or Signal_grant(20)(9); --  Grant(12,9)
+Grant(142)  <= Signal_grant(9)(10) or Signal_grant(21)(10); --  Grant(12,10)
+Grant(143)  <= Signal_grant(10)(11) or Signal_grant(22)(11); --  Grant(12,11)
+Grant(144)  <= Signal_grant(11)(12) or Signal_grant(23)(12); --  Grant(12,12)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(134), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(123), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(112), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(101), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(90), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(79), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(68), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(57), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+Arbiter_1_10 : Arbiter
+
+PORT MAP (Request => Request(46), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(10),  
+South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); 
+
+Arbiter_1_11 : Arbiter
+
+PORT MAP (Request => Request(35), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(11),  
+South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); 
+
+Arbiter_1_12 : Arbiter
+
+PORT MAP (Request => Request(24), North => High, West => High, P => Signal_priority(23), Fifo_full => Fifo_full(12),  
+South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(1)(1), West => east_2_west(1)(12), P => Signal_priority(22), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+Arbiter_2_10 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10),  
+South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); 
+
+Arbiter_2_11 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11),  
+South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); 
+
+Arbiter_2_12 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12),  
+South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(2)(1), West => east_2_west(2)(12), P => Signal_priority(21), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+Arbiter_3_10 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10),  
+South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); 
+
+Arbiter_3_11 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11),  
+South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); 
+
+Arbiter_3_12 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12),  
+South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(3)(1), West => east_2_west(3)(12), P => Signal_priority(20), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+Arbiter_4_10 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10),  
+South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); 
+
+Arbiter_4_11 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11),  
+South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); 
+
+Arbiter_4_12 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12),  
+South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(4)(1), West => east_2_west(4)(12), P => Signal_priority(19), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+Arbiter_5_10 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10),  
+South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); 
+
+Arbiter_5_11 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11),  
+South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); 
+
+Arbiter_5_12 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12),  
+South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(5)(1), West => east_2_west(5)(12), P => Signal_priority(18), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+Arbiter_6_10 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10),  
+South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); 
+
+Arbiter_6_11 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11),  
+South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); 
+
+Arbiter_6_12 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12),  
+South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(6)(1), West => east_2_west(6)(12), P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+Arbiter_7_10 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10),  
+South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); 
+
+Arbiter_7_11 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11),  
+South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); 
+
+Arbiter_7_12 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12),  
+South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(7)(1), West => east_2_west(7)(12), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+Arbiter_8_10 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10),  
+South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); 
+
+Arbiter_8_11 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11),  
+South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); 
+
+Arbiter_8_12 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12),  
+South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(8)(1), West => east_2_west(8)(12), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+Arbiter_9_10 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10),  
+South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); 
+
+Arbiter_9_11 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11),  
+South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); 
+
+Arbiter_9_12 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12),  
+South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(9)(1), West => east_2_west(9)(12), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+Arbiter_10_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10),  
+South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); 
+
+Arbiter_10_11 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11),  
+South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); 
+
+Arbiter_10_12 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12),  
+South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(10)(1), West => east_2_west(10)(12), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+Arbiter_11_10 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10),  
+South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); 
+
+Arbiter_11_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11),  
+South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); 
+
+Arbiter_11_12 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12),  
+South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(11)(1), West => east_2_west(11)(12), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(122), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+Arbiter_12_10 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10),  
+South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); 
+
+Arbiter_12_11 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11),  
+South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); 
+
+Arbiter_12_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12),  
+South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(12)(1), West => east_2_west(12)(12), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+Arbiter_13_10 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10),  
+South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); 
+
+Arbiter_13_11 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11),  
+South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); 
+
+Arbiter_13_12 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12),  
+South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(13)(1), West => east_2_west(13)(12), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+Arbiter_14_10 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10),  
+South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); 
+
+Arbiter_14_11 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11),  
+South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); 
+
+Arbiter_14_12 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12),  
+South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(14)(1), West => east_2_west(14)(12), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+Arbiter_15_10 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10),  
+South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); 
+
+Arbiter_15_11 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11),  
+South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); 
+
+Arbiter_15_12 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12),  
+South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(15)(1), West => east_2_west(15)(12), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+Arbiter_16_10 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10),  
+South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); 
+
+Arbiter_16_11 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11),  
+South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); 
+
+Arbiter_16_12 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12),  
+South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(16)(1), West => east_2_west(16)(12), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+Arbiter_17_10 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10),  
+South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); 
+
+Arbiter_17_11 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11),  
+South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); 
+
+Arbiter_17_12 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12),  
+South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); 
+
+-------------------------- Diagonale n° 18 
+
+
+Arbiter_18_1 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(17)(1), West => east_2_west(17)(12), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); 
+
+Arbiter_18_2 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); 
+
+Arbiter_18_3 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); 
+
+Arbiter_18_4 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); 
+
+Arbiter_18_5 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); 
+
+Arbiter_18_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); 
+
+Arbiter_18_7 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); 
+
+Arbiter_18_8 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); 
+
+Arbiter_18_9 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); 
+
+Arbiter_18_10 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10),  
+South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); 
+
+Arbiter_18_11 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11),  
+South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); 
+
+Arbiter_18_12 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12),  
+South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); 
+
+-------------------------- Diagonale n° 19 
+
+
+Arbiter_19_1 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(18)(1), West => east_2_west(18)(12), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); 
+
+Arbiter_19_2 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); 
+
+Arbiter_19_3 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); 
+
+Arbiter_19_4 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); 
+
+Arbiter_19_5 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); 
+
+Arbiter_19_6 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); 
+
+Arbiter_19_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); 
+
+Arbiter_19_8 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); 
+
+Arbiter_19_9 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); 
+
+Arbiter_19_10 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10),  
+South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); 
+
+Arbiter_19_11 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11),  
+South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); 
+
+Arbiter_19_12 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12),  
+South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); 
+
+-------------------------- Diagonale n° 20 
+
+
+Arbiter_20_1 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(19)(1), West => east_2_west(19)(12), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); 
+
+Arbiter_20_2 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); 
+
+Arbiter_20_3 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); 
+
+Arbiter_20_4 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); 
+
+Arbiter_20_5 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); 
+
+Arbiter_20_6 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); 
+
+Arbiter_20_7 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); 
+
+Arbiter_20_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); 
+
+Arbiter_20_9 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); 
+
+Arbiter_20_10 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10),  
+South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); 
+
+Arbiter_20_11 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11),  
+South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); 
+
+Arbiter_20_12 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12),  
+South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); 
+
+-------------------------- Diagonale n° 21 
+
+
+Arbiter_21_1 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(20)(1), West => east_2_west(20)(12), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); 
+
+Arbiter_21_2 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); 
+
+Arbiter_21_3 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); 
+
+Arbiter_21_4 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); 
+
+Arbiter_21_5 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); 
+
+Arbiter_21_6 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); 
+
+Arbiter_21_7 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); 
+
+Arbiter_21_8 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); 
+
+Arbiter_21_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); 
+
+Arbiter_21_10 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10),  
+South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); 
+
+Arbiter_21_11 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11),  
+South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); 
+
+Arbiter_21_12 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12),  
+South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); 
+
+-------------------------- Diagonale n° 22 
+
+
+Arbiter_22_1 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(21)(1), West => east_2_west(21)(12), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); 
+
+Arbiter_22_2 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); 
+
+Arbiter_22_3 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); 
+
+Arbiter_22_4 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); 
+
+Arbiter_22_5 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); 
+
+Arbiter_22_6 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); 
+
+Arbiter_22_7 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); 
+
+Arbiter_22_8 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); 
+
+Arbiter_22_9 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); 
+
+Arbiter_22_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10),  
+South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); 
+
+Arbiter_22_11 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11),  
+South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); 
+
+Arbiter_22_12 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12),  
+South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); 
+
+-------------------------- Diagonale n° 23 
+
+
+Arbiter_23_1 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(22)(1), West => east_2_west(22)(12), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); 
+
+Arbiter_23_2 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); 
+
+Arbiter_23_3 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); 
+
+Arbiter_23_4 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); 
+
+Arbiter_23_5 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); 
+
+Arbiter_23_6 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); 
+
+Arbiter_23_7 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); 
+
+Arbiter_23_8 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); 
+
+Arbiter_23_9 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); 
+
+Arbiter_23_10 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10),  
+South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); 
+
+Arbiter_23_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11),  
+South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); 
+
+Arbiter_23_12 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12),  
+South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "11111111111100000000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "11111111111100000000000" => Signal_priority <= "01111111111110000000000";
+		       when "01111111111110000000000" => Signal_priority <= "00111111111111000000000";
+		       when "00111111111111000000000" => Signal_priority <= "00011111111111100000000";
+		       when "00011111111111100000000" => Signal_priority <= "00001111111111110000000";
+		       when "00001111111111110000000" => Signal_priority <= "00000111111111111000000";
+		       when "00000111111111111000000" => Signal_priority <= "00000011111111111100000";
+		       when "00000011111111111100000" => Signal_priority <= "00000001111111111110000";
+		       when "00000001111111111110000" => Signal_priority <= "00000000111111111111000";
+		       when "00000000111111111111000" => Signal_priority <= "00000000011111111111100";
+		       when "00000000011111111111100" => Signal_priority <= "00000000001111111111110";
+		       when "00000000001111111111110" => Signal_priority <= "00000000000111111111111";
+		       when "00000000000111111111111" => Signal_priority <= "11111111111100000000000";
+		       when others    => Signal_priority <= "11111111111100000000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER13_13.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER13_13.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER13_13.VHD	(revision 20)
@@ -0,0 +1,1977 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler13_13 is
+    Port ( Request : in  STD_LOGIC_VECTOR (169 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (13 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (13 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (169 downto 1));
+end Scheduler13_13;
+
+architecture Behavioral of Scheduler13_13 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(25 downto 1) of STD_LOGIC_VECTOR(13 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (25 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(169 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(169 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 8191 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(14)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(15)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(16)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(17)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(18)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(19)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(20)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(21)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) or Signal_grant(22)(9); --  Grant(1,9)
+Grant(10)  <= Signal_grant(10)(10) or Signal_grant(23)(10); --  Grant(1,10)
+Grant(11)  <= Signal_grant(11)(11) or Signal_grant(24)(11); --  Grant(1,11)
+Grant(12)  <= Signal_grant(12)(12) or Signal_grant(25)(12); --  Grant(1,12)
+Grant(13)  <= Signal_grant(13)(13) ;                      --  Grant(1,13)
+Grant(14)  <= Signal_grant(2)(1) or Signal_grant(15)(1); --  Grant(2,1)
+Grant(15)  <= Signal_grant(3)(2) or Signal_grant(16)(2); --  Grant(2,2)
+Grant(16)  <= Signal_grant(4)(3) or Signal_grant(17)(3); --  Grant(2,3)
+Grant(17)  <= Signal_grant(5)(4) or Signal_grant(18)(4); --  Grant(2,4)
+Grant(18)  <= Signal_grant(6)(5) or Signal_grant(19)(5); --  Grant(2,5)
+Grant(19)  <= Signal_grant(7)(6) or Signal_grant(20)(6); --  Grant(2,6)
+Grant(20)  <= Signal_grant(8)(7) or Signal_grant(21)(7); --  Grant(2,7)
+Grant(21)  <= Signal_grant(9)(8) or Signal_grant(22)(8); --  Grant(2,8)
+Grant(22)  <= Signal_grant(10)(9) or Signal_grant(23)(9); --  Grant(2,9)
+Grant(23)  <= Signal_grant(11)(10) or Signal_grant(24)(10); --  Grant(2,10)
+Grant(24)  <= Signal_grant(12)(11) or Signal_grant(25)(11); --  Grant(2,11)
+Grant(25)  <= Signal_grant(13)(12) ;                      --  Grant(2,12)
+Grant(26)  <= Signal_grant(1)(13) or Signal_grant(14)(13); --  Grant(2,13)
+Grant(27)  <= Signal_grant(3)(1) or Signal_grant(16)(1); --  Grant(3,1)
+Grant(28)  <= Signal_grant(4)(2) or Signal_grant(17)(2); --  Grant(3,2)
+Grant(29)  <= Signal_grant(5)(3) or Signal_grant(18)(3); --  Grant(3,3)
+Grant(30)  <= Signal_grant(6)(4) or Signal_grant(19)(4); --  Grant(3,4)
+Grant(31)  <= Signal_grant(7)(5) or Signal_grant(20)(5); --  Grant(3,5)
+Grant(32)  <= Signal_grant(8)(6) or Signal_grant(21)(6); --  Grant(3,6)
+Grant(33)  <= Signal_grant(9)(7) or Signal_grant(22)(7); --  Grant(3,7)
+Grant(34)  <= Signal_grant(10)(8) or Signal_grant(23)(8); --  Grant(3,8)
+Grant(35)  <= Signal_grant(11)(9) or Signal_grant(24)(9); --  Grant(3,9)
+Grant(36)  <= Signal_grant(12)(10) or Signal_grant(25)(10); --  Grant(3,10)
+Grant(37)  <= Signal_grant(13)(11) ;                      --  Grant(3,11)
+Grant(38)  <= Signal_grant(1)(12) or Signal_grant(14)(12); --  Grant(3,12)
+Grant(39)  <= Signal_grant(2)(13) or Signal_grant(15)(13); --  Grant(3,13)
+Grant(40)  <= Signal_grant(4)(1) or Signal_grant(17)(1); --  Grant(4,1)
+Grant(41)  <= Signal_grant(5)(2) or Signal_grant(18)(2); --  Grant(4,2)
+Grant(42)  <= Signal_grant(6)(3) or Signal_grant(19)(3); --  Grant(4,3)
+Grant(43)  <= Signal_grant(7)(4) or Signal_grant(20)(4); --  Grant(4,4)
+Grant(44)  <= Signal_grant(8)(5) or Signal_grant(21)(5); --  Grant(4,5)
+Grant(45)  <= Signal_grant(9)(6) or Signal_grant(22)(6); --  Grant(4,6)
+Grant(46)  <= Signal_grant(10)(7) or Signal_grant(23)(7); --  Grant(4,7)
+Grant(47)  <= Signal_grant(11)(8) or Signal_grant(24)(8); --  Grant(4,8)
+Grant(48)  <= Signal_grant(12)(9) or Signal_grant(25)(9); --  Grant(4,9)
+Grant(49)  <= Signal_grant(13)(10) ;                      --  Grant(4,10)
+Grant(50)  <= Signal_grant(1)(11) or Signal_grant(14)(11); --  Grant(4,11)
+Grant(51)  <= Signal_grant(2)(12) or Signal_grant(15)(12); --  Grant(4,12)
+Grant(52)  <= Signal_grant(3)(13) or Signal_grant(16)(13); --  Grant(4,13)
+Grant(53)  <= Signal_grant(5)(1) or Signal_grant(18)(1); --  Grant(5,1)
+Grant(54)  <= Signal_grant(6)(2) or Signal_grant(19)(2); --  Grant(5,2)
+Grant(55)  <= Signal_grant(7)(3) or Signal_grant(20)(3); --  Grant(5,3)
+Grant(56)  <= Signal_grant(8)(4) or Signal_grant(21)(4); --  Grant(5,4)
+Grant(57)  <= Signal_grant(9)(5) or Signal_grant(22)(5); --  Grant(5,5)
+Grant(58)  <= Signal_grant(10)(6) or Signal_grant(23)(6); --  Grant(5,6)
+Grant(59)  <= Signal_grant(11)(7) or Signal_grant(24)(7); --  Grant(5,7)
+Grant(60)  <= Signal_grant(12)(8) or Signal_grant(25)(8); --  Grant(5,8)
+Grant(61)  <= Signal_grant(13)(9) ;                      --  Grant(5,9)
+Grant(62)  <= Signal_grant(1)(10) or Signal_grant(14)(10); --  Grant(5,10)
+Grant(63)  <= Signal_grant(2)(11) or Signal_grant(15)(11); --  Grant(5,11)
+Grant(64)  <= Signal_grant(3)(12) or Signal_grant(16)(12); --  Grant(5,12)
+Grant(65)  <= Signal_grant(4)(13) or Signal_grant(17)(13); --  Grant(5,13)
+Grant(66)  <= Signal_grant(6)(1) or Signal_grant(19)(1); --  Grant(6,1)
+Grant(67)  <= Signal_grant(7)(2) or Signal_grant(20)(2); --  Grant(6,2)
+Grant(68)  <= Signal_grant(8)(3) or Signal_grant(21)(3); --  Grant(6,3)
+Grant(69)  <= Signal_grant(9)(4) or Signal_grant(22)(4); --  Grant(6,4)
+Grant(70)  <= Signal_grant(10)(5) or Signal_grant(23)(5); --  Grant(6,5)
+Grant(71)  <= Signal_grant(11)(6) or Signal_grant(24)(6); --  Grant(6,6)
+Grant(72)  <= Signal_grant(12)(7) or Signal_grant(25)(7); --  Grant(6,7)
+Grant(73)  <= Signal_grant(13)(8) ;                      --  Grant(6,8)
+Grant(74)  <= Signal_grant(1)(9) or Signal_grant(14)(9); --  Grant(6,9)
+Grant(75)  <= Signal_grant(2)(10) or Signal_grant(15)(10); --  Grant(6,10)
+Grant(76)  <= Signal_grant(3)(11) or Signal_grant(16)(11); --  Grant(6,11)
+Grant(77)  <= Signal_grant(4)(12) or Signal_grant(17)(12); --  Grant(6,12)
+Grant(78)  <= Signal_grant(5)(13) or Signal_grant(18)(13); --  Grant(6,13)
+Grant(79)  <= Signal_grant(7)(1) or Signal_grant(20)(1); --  Grant(7,1)
+Grant(80)  <= Signal_grant(8)(2) or Signal_grant(21)(2); --  Grant(7,2)
+Grant(81)  <= Signal_grant(9)(3) or Signal_grant(22)(3); --  Grant(7,3)
+Grant(82)  <= Signal_grant(10)(4) or Signal_grant(23)(4); --  Grant(7,4)
+Grant(83)  <= Signal_grant(11)(5) or Signal_grant(24)(5); --  Grant(7,5)
+Grant(84)  <= Signal_grant(12)(6) or Signal_grant(25)(6); --  Grant(7,6)
+Grant(85)  <= Signal_grant(13)(7) ;                      --  Grant(7,7)
+Grant(86)  <= Signal_grant(1)(8) or Signal_grant(14)(8); --  Grant(7,8)
+Grant(87)  <= Signal_grant(2)(9) or Signal_grant(15)(9); --  Grant(7,9)
+Grant(88)  <= Signal_grant(3)(10) or Signal_grant(16)(10); --  Grant(7,10)
+Grant(89)  <= Signal_grant(4)(11) or Signal_grant(17)(11); --  Grant(7,11)
+Grant(90)  <= Signal_grant(5)(12) or Signal_grant(18)(12); --  Grant(7,12)
+Grant(91)  <= Signal_grant(6)(13) or Signal_grant(19)(13); --  Grant(7,13)
+Grant(92)  <= Signal_grant(8)(1) or Signal_grant(21)(1); --  Grant(8,1)
+Grant(93)  <= Signal_grant(9)(2) or Signal_grant(22)(2); --  Grant(8,2)
+Grant(94)  <= Signal_grant(10)(3) or Signal_grant(23)(3); --  Grant(8,3)
+Grant(95)  <= Signal_grant(11)(4) or Signal_grant(24)(4); --  Grant(8,4)
+Grant(96)  <= Signal_grant(12)(5) or Signal_grant(25)(5); --  Grant(8,5)
+Grant(97)  <= Signal_grant(13)(6) ;                      --  Grant(8,6)
+Grant(98)  <= Signal_grant(1)(7) or Signal_grant(14)(7); --  Grant(8,7)
+Grant(99)  <= Signal_grant(2)(8) or Signal_grant(15)(8); --  Grant(8,8)
+Grant(100)  <= Signal_grant(3)(9) or Signal_grant(16)(9); --  Grant(8,9)
+Grant(101)  <= Signal_grant(4)(10) or Signal_grant(17)(10); --  Grant(8,10)
+Grant(102)  <= Signal_grant(5)(11) or Signal_grant(18)(11); --  Grant(8,11)
+Grant(103)  <= Signal_grant(6)(12) or Signal_grant(19)(12); --  Grant(8,12)
+Grant(104)  <= Signal_grant(7)(13) or Signal_grant(20)(13); --  Grant(8,13)
+Grant(105)  <= Signal_grant(9)(1) or Signal_grant(22)(1); --  Grant(9,1)
+Grant(106)  <= Signal_grant(10)(2) or Signal_grant(23)(2); --  Grant(9,2)
+Grant(107)  <= Signal_grant(11)(3) or Signal_grant(24)(3); --  Grant(9,3)
+Grant(108)  <= Signal_grant(12)(4) or Signal_grant(25)(4); --  Grant(9,4)
+Grant(109)  <= Signal_grant(13)(5) ;                      --  Grant(9,5)
+Grant(110)  <= Signal_grant(1)(6) or Signal_grant(14)(6); --  Grant(9,6)
+Grant(111)  <= Signal_grant(2)(7) or Signal_grant(15)(7); --  Grant(9,7)
+Grant(112)  <= Signal_grant(3)(8) or Signal_grant(16)(8); --  Grant(9,8)
+Grant(113)  <= Signal_grant(4)(9) or Signal_grant(17)(9); --  Grant(9,9)
+Grant(114)  <= Signal_grant(5)(10) or Signal_grant(18)(10); --  Grant(9,10)
+Grant(115)  <= Signal_grant(6)(11) or Signal_grant(19)(11); --  Grant(9,11)
+Grant(116)  <= Signal_grant(7)(12) or Signal_grant(20)(12); --  Grant(9,12)
+Grant(117)  <= Signal_grant(8)(13) or Signal_grant(21)(13); --  Grant(9,13)
+Grant(118)  <= Signal_grant(10)(1) or Signal_grant(23)(1); --  Grant(10,1)
+Grant(119)  <= Signal_grant(11)(2) or Signal_grant(24)(2); --  Grant(10,2)
+Grant(120)  <= Signal_grant(12)(3) or Signal_grant(25)(3); --  Grant(10,3)
+Grant(121)  <= Signal_grant(13)(4) ;                      --  Grant(10,4)
+Grant(122)  <= Signal_grant(1)(5) or Signal_grant(14)(5); --  Grant(10,5)
+Grant(123)  <= Signal_grant(2)(6) or Signal_grant(15)(6); --  Grant(10,6)
+Grant(124)  <= Signal_grant(3)(7) or Signal_grant(16)(7); --  Grant(10,7)
+Grant(125)  <= Signal_grant(4)(8) or Signal_grant(17)(8); --  Grant(10,8)
+Grant(126)  <= Signal_grant(5)(9) or Signal_grant(18)(9); --  Grant(10,9)
+Grant(127)  <= Signal_grant(6)(10) or Signal_grant(19)(10); --  Grant(10,10)
+Grant(128)  <= Signal_grant(7)(11) or Signal_grant(20)(11); --  Grant(10,11)
+Grant(129)  <= Signal_grant(8)(12) or Signal_grant(21)(12); --  Grant(10,12)
+Grant(130)  <= Signal_grant(9)(13) or Signal_grant(22)(13); --  Grant(10,13)
+Grant(131)  <= Signal_grant(11)(1) or Signal_grant(24)(1); --  Grant(11,1)
+Grant(132)  <= Signal_grant(12)(2) or Signal_grant(25)(2); --  Grant(11,2)
+Grant(133)  <= Signal_grant(13)(3) ;                      --  Grant(11,3)
+Grant(134)  <= Signal_grant(1)(4) or Signal_grant(14)(4); --  Grant(11,4)
+Grant(135)  <= Signal_grant(2)(5) or Signal_grant(15)(5); --  Grant(11,5)
+Grant(136)  <= Signal_grant(3)(6) or Signal_grant(16)(6); --  Grant(11,6)
+Grant(137)  <= Signal_grant(4)(7) or Signal_grant(17)(7); --  Grant(11,7)
+Grant(138)  <= Signal_grant(5)(8) or Signal_grant(18)(8); --  Grant(11,8)
+Grant(139)  <= Signal_grant(6)(9) or Signal_grant(19)(9); --  Grant(11,9)
+Grant(140)  <= Signal_grant(7)(10) or Signal_grant(20)(10); --  Grant(11,10)
+Grant(141)  <= Signal_grant(8)(11) or Signal_grant(21)(11); --  Grant(11,11)
+Grant(142)  <= Signal_grant(9)(12) or Signal_grant(22)(12); --  Grant(11,12)
+Grant(143)  <= Signal_grant(10)(13) or Signal_grant(23)(13); --  Grant(11,13)
+Grant(144)  <= Signal_grant(12)(1) or Signal_grant(25)(1); --  Grant(12,1)
+Grant(145)  <= Signal_grant(13)(2) ;                      --  Grant(12,2)
+Grant(146)  <= Signal_grant(1)(3) or Signal_grant(14)(3); --  Grant(12,3)
+Grant(147)  <= Signal_grant(2)(4) or Signal_grant(15)(4); --  Grant(12,4)
+Grant(148)  <= Signal_grant(3)(5) or Signal_grant(16)(5); --  Grant(12,5)
+Grant(149)  <= Signal_grant(4)(6) or Signal_grant(17)(6); --  Grant(12,6)
+Grant(150)  <= Signal_grant(5)(7) or Signal_grant(18)(7); --  Grant(12,7)
+Grant(151)  <= Signal_grant(6)(8) or Signal_grant(19)(8); --  Grant(12,8)
+Grant(152)  <= Signal_grant(7)(9) or Signal_grant(20)(9); --  Grant(12,9)
+Grant(153)  <= Signal_grant(8)(10) or Signal_grant(21)(10); --  Grant(12,10)
+Grant(154)  <= Signal_grant(9)(11) or Signal_grant(22)(11); --  Grant(12,11)
+Grant(155)  <= Signal_grant(10)(12) or Signal_grant(23)(12); --  Grant(12,12)
+Grant(156)  <= Signal_grant(11)(13) or Signal_grant(24)(13); --  Grant(12,13)
+Grant(157)  <= Signal_grant(13)(1) ;                      --  Grant(13,1)
+Grant(158)  <= Signal_grant(1)(2) or Signal_grant(14)(2); --  Grant(13,2)
+Grant(159)  <= Signal_grant(2)(3) or Signal_grant(15)(3); --  Grant(13,3)
+Grant(160)  <= Signal_grant(3)(4) or Signal_grant(16)(4); --  Grant(13,4)
+Grant(161)  <= Signal_grant(4)(5) or Signal_grant(17)(5); --  Grant(13,5)
+Grant(162)  <= Signal_grant(5)(6) or Signal_grant(18)(6); --  Grant(13,6)
+Grant(163)  <= Signal_grant(6)(7) or Signal_grant(19)(7); --  Grant(13,7)
+Grant(164)  <= Signal_grant(7)(8) or Signal_grant(20)(8); --  Grant(13,8)
+Grant(165)  <= Signal_grant(8)(9) or Signal_grant(21)(9); --  Grant(13,9)
+Grant(166)  <= Signal_grant(9)(10) or Signal_grant(22)(10); --  Grant(13,10)
+Grant(167)  <= Signal_grant(10)(11) or Signal_grant(23)(11); --  Grant(13,11)
+Grant(168)  <= Signal_grant(11)(12) or Signal_grant(24)(12); --  Grant(13,12)
+Grant(169)  <= Signal_grant(12)(13) or Signal_grant(25)(13); --  Grant(13,13)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(158), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(146), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(134), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(122), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(110), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(98), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(86), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(74), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+Arbiter_1_10 : Arbiter
+
+PORT MAP (Request => Request(62), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(10),  
+South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); 
+
+Arbiter_1_11 : Arbiter
+
+PORT MAP (Request => Request(50), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(11),  
+South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); 
+
+Arbiter_1_12 : Arbiter
+
+PORT MAP (Request => Request(38), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(12),  
+South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); 
+
+Arbiter_1_13 : Arbiter
+
+PORT MAP (Request => Request(26), North => High, West => High, P => Signal_priority(25), Fifo_full => Fifo_full(13),  
+South => south_2_north(1)(13), East => east_2_west(1)(13) , Grant => Signal_grant(1)(13)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(1)(1), West => east_2_west(1)(13), P => Signal_priority(24), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(24), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(24), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(24), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(24), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(24), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(24), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(24), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(24), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+Arbiter_2_10 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(24), Fifo_full => Fifo_full(10),  
+South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); 
+
+Arbiter_2_11 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(24), Fifo_full => Fifo_full(11),  
+South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); 
+
+Arbiter_2_12 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(24), Fifo_full => Fifo_full(12),  
+South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); 
+
+Arbiter_2_13 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(1)(13), West => east_2_west(1)(12), P => Signal_priority(24), Fifo_full => Fifo_full(13),  
+South => south_2_north(2)(13), East => east_2_west(2)(13) , Grant => Signal_grant(2)(13)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(2)(1), West => east_2_west(2)(13), P => Signal_priority(23), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(23), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(23), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(23), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(23), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(23), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(23), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(23), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(23), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+Arbiter_3_10 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(23), Fifo_full => Fifo_full(10),  
+South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); 
+
+Arbiter_3_11 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(23), Fifo_full => Fifo_full(11),  
+South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); 
+
+Arbiter_3_12 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(23), Fifo_full => Fifo_full(12),  
+South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); 
+
+Arbiter_3_13 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(2)(13), West => east_2_west(2)(12), P => Signal_priority(23), Fifo_full => Fifo_full(13),  
+South => south_2_north(3)(13), East => east_2_west(3)(13) , Grant => Signal_grant(3)(13)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(3)(1), West => east_2_west(3)(13), P => Signal_priority(22), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+Arbiter_4_10 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10),  
+South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); 
+
+Arbiter_4_11 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11),  
+South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); 
+
+Arbiter_4_12 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12),  
+South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); 
+
+Arbiter_4_13 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(3)(13), West => east_2_west(3)(12), P => Signal_priority(22), Fifo_full => Fifo_full(13),  
+South => south_2_north(4)(13), East => east_2_west(4)(13) , Grant => Signal_grant(4)(13)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(4)(1), West => east_2_west(4)(13), P => Signal_priority(21), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+Arbiter_5_10 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10),  
+South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); 
+
+Arbiter_5_11 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11),  
+South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); 
+
+Arbiter_5_12 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12),  
+South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); 
+
+Arbiter_5_13 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(4)(13), West => east_2_west(4)(12), P => Signal_priority(21), Fifo_full => Fifo_full(13),  
+South => south_2_north(5)(13), East => east_2_west(5)(13) , Grant => Signal_grant(5)(13)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(5)(1), West => east_2_west(5)(13), P => Signal_priority(20), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(151), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+Arbiter_6_10 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10),  
+South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); 
+
+Arbiter_6_11 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11),  
+South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); 
+
+Arbiter_6_12 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12),  
+South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); 
+
+Arbiter_6_13 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(5)(13), West => east_2_west(5)(12), P => Signal_priority(20), Fifo_full => Fifo_full(13),  
+South => south_2_north(6)(13), East => east_2_west(6)(13) , Grant => Signal_grant(6)(13)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(6)(1), West => east_2_west(6)(13), P => Signal_priority(19), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(152), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+Arbiter_7_10 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10),  
+South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); 
+
+Arbiter_7_11 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11),  
+South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); 
+
+Arbiter_7_12 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12),  
+South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); 
+
+Arbiter_7_13 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(6)(13), West => east_2_west(6)(12), P => Signal_priority(19), Fifo_full => Fifo_full(13),  
+South => south_2_north(7)(13), East => east_2_west(7)(13) , Grant => Signal_grant(7)(13)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(7)(1), West => east_2_west(7)(13), P => Signal_priority(18), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+Arbiter_8_10 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10),  
+South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); 
+
+Arbiter_8_11 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11),  
+South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); 
+
+Arbiter_8_12 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12),  
+South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); 
+
+Arbiter_8_13 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(7)(13), West => east_2_west(7)(12), P => Signal_priority(18), Fifo_full => Fifo_full(13),  
+South => south_2_north(8)(13), East => east_2_west(8)(13) , Grant => Signal_grant(8)(13)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(8)(1), West => east_2_west(8)(13), P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+Arbiter_9_10 : Arbiter
+
+PORT MAP (Request => Request(166), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10),  
+South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); 
+
+Arbiter_9_11 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11),  
+South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); 
+
+Arbiter_9_12 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12),  
+South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); 
+
+Arbiter_9_13 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(8)(13), West => east_2_west(8)(12), P => Signal_priority(17), Fifo_full => Fifo_full(13),  
+South => south_2_north(9)(13), East => east_2_west(9)(13) , Grant => Signal_grant(9)(13)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(9)(1), West => east_2_west(9)(13), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+Arbiter_10_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10),  
+South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); 
+
+Arbiter_10_11 : Arbiter
+
+PORT MAP (Request => Request(167), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11),  
+South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); 
+
+Arbiter_10_12 : Arbiter
+
+PORT MAP (Request => Request(155), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12),  
+South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); 
+
+Arbiter_10_13 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(9)(13), West => east_2_west(9)(12), P => Signal_priority(16), Fifo_full => Fifo_full(13),  
+South => south_2_north(10)(13), East => east_2_west(10)(13) , Grant => Signal_grant(10)(13)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(10)(1), West => east_2_west(10)(13), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+Arbiter_11_10 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10),  
+South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); 
+
+Arbiter_11_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11),  
+South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); 
+
+Arbiter_11_12 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12),  
+South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); 
+
+Arbiter_11_13 : Arbiter
+
+PORT MAP (Request => Request(156), North => south_2_north(10)(13), West => east_2_west(10)(12), P => Signal_priority(15), Fifo_full => Fifo_full(13),  
+South => south_2_north(11)(13), East => east_2_west(11)(13) , Grant => Signal_grant(11)(13)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(11)(1), West => east_2_west(11)(13), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+Arbiter_12_10 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10),  
+South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); 
+
+Arbiter_12_11 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11),  
+South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); 
+
+Arbiter_12_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12),  
+South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); 
+
+Arbiter_12_13 : Arbiter
+
+PORT MAP (Request => Request(169), North => south_2_north(11)(13), West => east_2_west(11)(12), P => Signal_priority(14), Fifo_full => Fifo_full(13),  
+South => south_2_north(12)(13), East => east_2_west(12)(13) , Grant => Signal_grant(12)(13)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(157), North => south_2_north(12)(1), West => east_2_west(12)(13), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(145), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+Arbiter_13_10 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10),  
+South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); 
+
+Arbiter_13_11 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11),  
+South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); 
+
+Arbiter_13_12 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12),  
+South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); 
+
+Arbiter_13_13 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(12)(13), West => east_2_west(12)(12), P => Signal_priority(13), Fifo_full => Fifo_full(13),  
+South => south_2_north(13)(13), East => east_2_west(13)(13) , Grant => Signal_grant(13)(13)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(13)(1), West => east_2_west(13)(13), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(158), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(146), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(122), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+Arbiter_14_10 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10),  
+South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); 
+
+Arbiter_14_11 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11),  
+South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); 
+
+Arbiter_14_12 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12),  
+South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); 
+
+Arbiter_14_13 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(13)(13), West => east_2_west(13)(12), P => Signal_priority(12), Fifo_full => Fifo_full(13),  
+South => south_2_north(14)(13), East => east_2_west(14)(13) , Grant => Signal_grant(14)(13)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(14)(1), West => east_2_west(14)(13), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+Arbiter_15_10 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10),  
+South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); 
+
+Arbiter_15_11 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11),  
+South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); 
+
+Arbiter_15_12 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12),  
+South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); 
+
+Arbiter_15_13 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(14)(13), West => east_2_west(14)(12), P => Signal_priority(11), Fifo_full => Fifo_full(13),  
+South => south_2_north(15)(13), East => east_2_west(15)(13) , Grant => Signal_grant(15)(13)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(15)(1), West => east_2_west(15)(13), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+Arbiter_16_10 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10),  
+South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); 
+
+Arbiter_16_11 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11),  
+South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); 
+
+Arbiter_16_12 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12),  
+South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); 
+
+Arbiter_16_13 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(15)(13), West => east_2_west(15)(12), P => Signal_priority(10), Fifo_full => Fifo_full(13),  
+South => south_2_north(16)(13), East => east_2_west(16)(13) , Grant => Signal_grant(16)(13)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(16)(1), West => east_2_west(16)(13), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+Arbiter_17_10 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10),  
+South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); 
+
+Arbiter_17_11 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11),  
+South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); 
+
+Arbiter_17_12 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12),  
+South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); 
+
+Arbiter_17_13 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(16)(13), West => east_2_west(16)(12), P => Signal_priority(9), Fifo_full => Fifo_full(13),  
+South => south_2_north(17)(13), East => east_2_west(17)(13) , Grant => Signal_grant(17)(13)); 
+
+-------------------------- Diagonale n° 18 
+
+
+Arbiter_18_1 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(17)(1), West => east_2_west(17)(13), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); 
+
+Arbiter_18_2 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); 
+
+Arbiter_18_3 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); 
+
+Arbiter_18_4 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); 
+
+Arbiter_18_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); 
+
+Arbiter_18_6 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); 
+
+Arbiter_18_7 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); 
+
+Arbiter_18_8 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); 
+
+Arbiter_18_9 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); 
+
+Arbiter_18_10 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10),  
+South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); 
+
+Arbiter_18_11 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11),  
+South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); 
+
+Arbiter_18_12 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12),  
+South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); 
+
+Arbiter_18_13 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(17)(13), West => east_2_west(17)(12), P => Signal_priority(8), Fifo_full => Fifo_full(13),  
+South => south_2_north(18)(13), East => east_2_west(18)(13) , Grant => Signal_grant(18)(13)); 
+
+-------------------------- Diagonale n° 19 
+
+
+Arbiter_19_1 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(18)(1), West => east_2_west(18)(13), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); 
+
+Arbiter_19_2 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); 
+
+Arbiter_19_3 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); 
+
+Arbiter_19_4 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); 
+
+Arbiter_19_5 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); 
+
+Arbiter_19_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); 
+
+Arbiter_19_7 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); 
+
+Arbiter_19_8 : Arbiter
+
+PORT MAP (Request => Request(151), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); 
+
+Arbiter_19_9 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); 
+
+Arbiter_19_10 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10),  
+South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); 
+
+Arbiter_19_11 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11),  
+South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); 
+
+Arbiter_19_12 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12),  
+South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); 
+
+Arbiter_19_13 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(18)(13), West => east_2_west(18)(12), P => Signal_priority(7), Fifo_full => Fifo_full(13),  
+South => south_2_north(19)(13), East => east_2_west(19)(13) , Grant => Signal_grant(19)(13)); 
+
+-------------------------- Diagonale n° 20 
+
+
+Arbiter_20_1 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(19)(1), West => east_2_west(19)(13), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); 
+
+Arbiter_20_2 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); 
+
+Arbiter_20_3 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); 
+
+Arbiter_20_4 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); 
+
+Arbiter_20_5 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); 
+
+Arbiter_20_6 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); 
+
+Arbiter_20_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); 
+
+Arbiter_20_8 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); 
+
+Arbiter_20_9 : Arbiter
+
+PORT MAP (Request => Request(152), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); 
+
+Arbiter_20_10 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10),  
+South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); 
+
+Arbiter_20_11 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11),  
+South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); 
+
+Arbiter_20_12 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12),  
+South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); 
+
+Arbiter_20_13 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(19)(13), West => east_2_west(19)(12), P => Signal_priority(6), Fifo_full => Fifo_full(13),  
+South => south_2_north(20)(13), East => east_2_west(20)(13) , Grant => Signal_grant(20)(13)); 
+
+-------------------------- Diagonale n° 21 
+
+
+Arbiter_21_1 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(20)(1), West => east_2_west(20)(13), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); 
+
+Arbiter_21_2 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); 
+
+Arbiter_21_3 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); 
+
+Arbiter_21_4 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); 
+
+Arbiter_21_5 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); 
+
+Arbiter_21_6 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); 
+
+Arbiter_21_7 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); 
+
+Arbiter_21_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); 
+
+Arbiter_21_9 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); 
+
+Arbiter_21_10 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10),  
+South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); 
+
+Arbiter_21_11 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11),  
+South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); 
+
+Arbiter_21_12 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12),  
+South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); 
+
+Arbiter_21_13 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(20)(13), West => east_2_west(20)(12), P => Signal_priority(5), Fifo_full => Fifo_full(13),  
+South => south_2_north(21)(13), East => east_2_west(21)(13) , Grant => Signal_grant(21)(13)); 
+
+-------------------------- Diagonale n° 22 
+
+
+Arbiter_22_1 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(21)(1), West => east_2_west(21)(13), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); 
+
+Arbiter_22_2 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); 
+
+Arbiter_22_3 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); 
+
+Arbiter_22_4 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); 
+
+Arbiter_22_5 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); 
+
+Arbiter_22_6 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); 
+
+Arbiter_22_7 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); 
+
+Arbiter_22_8 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); 
+
+Arbiter_22_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); 
+
+Arbiter_22_10 : Arbiter
+
+PORT MAP (Request => Request(166), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10),  
+South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); 
+
+Arbiter_22_11 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11),  
+South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); 
+
+Arbiter_22_12 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12),  
+South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); 
+
+Arbiter_22_13 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(21)(13), West => east_2_west(21)(12), P => Signal_priority(4), Fifo_full => Fifo_full(13),  
+South => south_2_north(22)(13), East => east_2_west(22)(13) , Grant => Signal_grant(22)(13)); 
+
+-------------------------- Diagonale n° 23 
+
+
+Arbiter_23_1 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(22)(1), West => east_2_west(22)(13), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); 
+
+Arbiter_23_2 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); 
+
+Arbiter_23_3 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); 
+
+Arbiter_23_4 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); 
+
+Arbiter_23_5 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); 
+
+Arbiter_23_6 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); 
+
+Arbiter_23_7 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); 
+
+Arbiter_23_8 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); 
+
+Arbiter_23_9 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); 
+
+Arbiter_23_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10),  
+South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); 
+
+Arbiter_23_11 : Arbiter
+
+PORT MAP (Request => Request(167), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11),  
+South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); 
+
+Arbiter_23_12 : Arbiter
+
+PORT MAP (Request => Request(155), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12),  
+South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); 
+
+Arbiter_23_13 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(22)(13), West => east_2_west(22)(12), P => Signal_priority(3), Fifo_full => Fifo_full(13),  
+South => south_2_north(23)(13), East => east_2_west(23)(13) , Grant => Signal_grant(23)(13)); 
+
+-------------------------- Diagonale n° 24 
+
+
+Arbiter_24_1 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(23)(1), West => east_2_west(23)(13), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(24)(1), East => east_2_west(24)(1) , Grant => Signal_grant(24)(1)); 
+
+Arbiter_24_2 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(23)(2), West => east_2_west(23)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(24)(2), East => east_2_west(24)(2) , Grant => Signal_grant(24)(2)); 
+
+Arbiter_24_3 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(23)(3), West => east_2_west(23)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(24)(3), East => east_2_west(24)(3) , Grant => Signal_grant(24)(3)); 
+
+Arbiter_24_4 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(23)(4), West => east_2_west(23)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(24)(4), East => east_2_west(24)(4) , Grant => Signal_grant(24)(4)); 
+
+Arbiter_24_5 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(23)(5), West => east_2_west(23)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(24)(5), East => east_2_west(24)(5) , Grant => Signal_grant(24)(5)); 
+
+Arbiter_24_6 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(23)(6), West => east_2_west(23)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(24)(6), East => east_2_west(24)(6) , Grant => Signal_grant(24)(6)); 
+
+Arbiter_24_7 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(23)(7), West => east_2_west(23)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(24)(7), East => east_2_west(24)(7) , Grant => Signal_grant(24)(7)); 
+
+Arbiter_24_8 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(23)(8), West => east_2_west(23)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(24)(8), East => east_2_west(24)(8) , Grant => Signal_grant(24)(8)); 
+
+Arbiter_24_9 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(23)(9), West => east_2_west(23)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(24)(9), East => east_2_west(24)(9) , Grant => Signal_grant(24)(9)); 
+
+Arbiter_24_10 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(23)(10), West => east_2_west(23)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10),  
+South => south_2_north(24)(10), East => east_2_west(24)(10) , Grant => Signal_grant(24)(10)); 
+
+Arbiter_24_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(23)(11), West => east_2_west(23)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11),  
+South => south_2_north(24)(11), East => east_2_west(24)(11) , Grant => Signal_grant(24)(11)); 
+
+Arbiter_24_12 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(23)(12), West => east_2_west(23)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12),  
+South => south_2_north(24)(12), East => east_2_west(24)(12) , Grant => Signal_grant(24)(12)); 
+
+Arbiter_24_13 : Arbiter
+
+PORT MAP (Request => Request(156), North => south_2_north(23)(13), West => east_2_west(23)(12), P => Signal_priority(2), Fifo_full => Fifo_full(13),  
+South => south_2_north(24)(13), East => east_2_west(24)(13) , Grant => Signal_grant(24)(13)); 
+
+-------------------------- Diagonale n° 25 
+
+
+Arbiter_25_1 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(24)(1), West => east_2_west(24)(13), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(25)(1), East => east_2_west(25)(1) , Grant => Signal_grant(25)(1)); 
+
+Arbiter_25_2 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(24)(2), West => east_2_west(24)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(25)(2), East => east_2_west(25)(2) , Grant => Signal_grant(25)(2)); 
+
+Arbiter_25_3 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(24)(3), West => east_2_west(24)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(25)(3), East => east_2_west(25)(3) , Grant => Signal_grant(25)(3)); 
+
+Arbiter_25_4 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(24)(4), West => east_2_west(24)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(25)(4), East => east_2_west(25)(4) , Grant => Signal_grant(25)(4)); 
+
+Arbiter_25_5 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(24)(5), West => east_2_west(24)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(25)(5), East => east_2_west(25)(5) , Grant => Signal_grant(25)(5)); 
+
+Arbiter_25_6 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(24)(6), West => east_2_west(24)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(25)(6), East => east_2_west(25)(6) , Grant => Signal_grant(25)(6)); 
+
+Arbiter_25_7 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(24)(7), West => east_2_west(24)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(25)(7), East => east_2_west(25)(7) , Grant => Signal_grant(25)(7)); 
+
+Arbiter_25_8 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(24)(8), West => east_2_west(24)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(25)(8), East => east_2_west(25)(8) , Grant => Signal_grant(25)(8)); 
+
+Arbiter_25_9 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(24)(9), West => east_2_west(24)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(25)(9), East => east_2_west(25)(9) , Grant => Signal_grant(25)(9)); 
+
+Arbiter_25_10 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(24)(10), West => east_2_west(24)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10),  
+South => south_2_north(25)(10), East => east_2_west(25)(10) , Grant => Signal_grant(25)(10)); 
+
+Arbiter_25_11 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(24)(11), West => east_2_west(24)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11),  
+South => south_2_north(25)(11), East => east_2_west(25)(11) , Grant => Signal_grant(25)(11)); 
+
+Arbiter_25_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(24)(12), West => east_2_west(24)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12),  
+South => south_2_north(25)(12), East => east_2_west(25)(12) , Grant => Signal_grant(25)(12)); 
+
+Arbiter_25_13 : Arbiter
+
+PORT MAP (Request => Request(169), North => south_2_north(24)(13), West => east_2_west(24)(12), P => Signal_priority(1), Fifo_full => Fifo_full(13),  
+South => south_2_north(25)(13), East => east_2_west(25)(13) , Grant => Signal_grant(25)(13)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "1111111111111000000000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "1111111111111000000000000" => Signal_priority <= "0111111111111100000000000";
+		       when "0111111111111100000000000" => Signal_priority <= "0011111111111110000000000";
+		       when "0011111111111110000000000" => Signal_priority <= "0001111111111111000000000";
+		       when "0001111111111111000000000" => Signal_priority <= "0000111111111111100000000";
+		       when "0000111111111111100000000" => Signal_priority <= "0000011111111111110000000";
+		       when "0000011111111111110000000" => Signal_priority <= "0000001111111111111000000";
+		       when "0000001111111111111000000" => Signal_priority <= "0000000111111111111100000";
+		       when "0000000111111111111100000" => Signal_priority <= "0000000011111111111110000";
+		       when "0000000011111111111110000" => Signal_priority <= "0000000001111111111111000";
+		       when "0000000001111111111111000" => Signal_priority <= "0000000000111111111111100";
+		       when "0000000000111111111111100" => Signal_priority <= "0000000000011111111111110";
+		       when "0000000000011111111111110" => Signal_priority <= "0000000000001111111111111";
+		       when "0000000000001111111111111" => Signal_priority <= "1111111111111000000000000";
+		       when others    => Signal_priority <= "1111111111111000000000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER14_14.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER14_14.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER14_14.VHD	(revision 20)
@@ -0,0 +1,2276 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler14_14 is
+    Port ( Request : in  STD_LOGIC_VECTOR (196 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (14 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (14 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (196 downto 1));
+end Scheduler14_14;
+
+architecture Behavioral of Scheduler14_14 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(27 downto 1) of STD_LOGIC_VECTOR(14 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (27 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(196 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(196 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 16383 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(15)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(16)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(17)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(18)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(19)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(20)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(21)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(22)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) or Signal_grant(23)(9); --  Grant(1,9)
+Grant(10)  <= Signal_grant(10)(10) or Signal_grant(24)(10); --  Grant(1,10)
+Grant(11)  <= Signal_grant(11)(11) or Signal_grant(25)(11); --  Grant(1,11)
+Grant(12)  <= Signal_grant(12)(12) or Signal_grant(26)(12); --  Grant(1,12)
+Grant(13)  <= Signal_grant(13)(13) or Signal_grant(27)(13); --  Grant(1,13)
+Grant(14)  <= Signal_grant(14)(14) ;                      --  Grant(1,14)
+Grant(15)  <= Signal_grant(2)(1) or Signal_grant(16)(1); --  Grant(2,1)
+Grant(16)  <= Signal_grant(3)(2) or Signal_grant(17)(2); --  Grant(2,2)
+Grant(17)  <= Signal_grant(4)(3) or Signal_grant(18)(3); --  Grant(2,3)
+Grant(18)  <= Signal_grant(5)(4) or Signal_grant(19)(4); --  Grant(2,4)
+Grant(19)  <= Signal_grant(6)(5) or Signal_grant(20)(5); --  Grant(2,5)
+Grant(20)  <= Signal_grant(7)(6) or Signal_grant(21)(6); --  Grant(2,6)
+Grant(21)  <= Signal_grant(8)(7) or Signal_grant(22)(7); --  Grant(2,7)
+Grant(22)  <= Signal_grant(9)(8) or Signal_grant(23)(8); --  Grant(2,8)
+Grant(23)  <= Signal_grant(10)(9) or Signal_grant(24)(9); --  Grant(2,9)
+Grant(24)  <= Signal_grant(11)(10) or Signal_grant(25)(10); --  Grant(2,10)
+Grant(25)  <= Signal_grant(12)(11) or Signal_grant(26)(11); --  Grant(2,11)
+Grant(26)  <= Signal_grant(13)(12) or Signal_grant(27)(12); --  Grant(2,12)
+Grant(27)  <= Signal_grant(14)(13) ;                      --  Grant(2,13)
+Grant(28)  <= Signal_grant(1)(14) or Signal_grant(15)(14); --  Grant(2,14)
+Grant(29)  <= Signal_grant(3)(1) or Signal_grant(17)(1); --  Grant(3,1)
+Grant(30)  <= Signal_grant(4)(2) or Signal_grant(18)(2); --  Grant(3,2)
+Grant(31)  <= Signal_grant(5)(3) or Signal_grant(19)(3); --  Grant(3,3)
+Grant(32)  <= Signal_grant(6)(4) or Signal_grant(20)(4); --  Grant(3,4)
+Grant(33)  <= Signal_grant(7)(5) or Signal_grant(21)(5); --  Grant(3,5)
+Grant(34)  <= Signal_grant(8)(6) or Signal_grant(22)(6); --  Grant(3,6)
+Grant(35)  <= Signal_grant(9)(7) or Signal_grant(23)(7); --  Grant(3,7)
+Grant(36)  <= Signal_grant(10)(8) or Signal_grant(24)(8); --  Grant(3,8)
+Grant(37)  <= Signal_grant(11)(9) or Signal_grant(25)(9); --  Grant(3,9)
+Grant(38)  <= Signal_grant(12)(10) or Signal_grant(26)(10); --  Grant(3,10)
+Grant(39)  <= Signal_grant(13)(11) or Signal_grant(27)(11); --  Grant(3,11)
+Grant(40)  <= Signal_grant(14)(12) ;                      --  Grant(3,12)
+Grant(41)  <= Signal_grant(1)(13) or Signal_grant(15)(13); --  Grant(3,13)
+Grant(42)  <= Signal_grant(2)(14) or Signal_grant(16)(14); --  Grant(3,14)
+Grant(43)  <= Signal_grant(4)(1) or Signal_grant(18)(1); --  Grant(4,1)
+Grant(44)  <= Signal_grant(5)(2) or Signal_grant(19)(2); --  Grant(4,2)
+Grant(45)  <= Signal_grant(6)(3) or Signal_grant(20)(3); --  Grant(4,3)
+Grant(46)  <= Signal_grant(7)(4) or Signal_grant(21)(4); --  Grant(4,4)
+Grant(47)  <= Signal_grant(8)(5) or Signal_grant(22)(5); --  Grant(4,5)
+Grant(48)  <= Signal_grant(9)(6) or Signal_grant(23)(6); --  Grant(4,6)
+Grant(49)  <= Signal_grant(10)(7) or Signal_grant(24)(7); --  Grant(4,7)
+Grant(50)  <= Signal_grant(11)(8) or Signal_grant(25)(8); --  Grant(4,8)
+Grant(51)  <= Signal_grant(12)(9) or Signal_grant(26)(9); --  Grant(4,9)
+Grant(52)  <= Signal_grant(13)(10) or Signal_grant(27)(10); --  Grant(4,10)
+Grant(53)  <= Signal_grant(14)(11) ;                      --  Grant(4,11)
+Grant(54)  <= Signal_grant(1)(12) or Signal_grant(15)(12); --  Grant(4,12)
+Grant(55)  <= Signal_grant(2)(13) or Signal_grant(16)(13); --  Grant(4,13)
+Grant(56)  <= Signal_grant(3)(14) or Signal_grant(17)(14); --  Grant(4,14)
+Grant(57)  <= Signal_grant(5)(1) or Signal_grant(19)(1); --  Grant(5,1)
+Grant(58)  <= Signal_grant(6)(2) or Signal_grant(20)(2); --  Grant(5,2)
+Grant(59)  <= Signal_grant(7)(3) or Signal_grant(21)(3); --  Grant(5,3)
+Grant(60)  <= Signal_grant(8)(4) or Signal_grant(22)(4); --  Grant(5,4)
+Grant(61)  <= Signal_grant(9)(5) or Signal_grant(23)(5); --  Grant(5,5)
+Grant(62)  <= Signal_grant(10)(6) or Signal_grant(24)(6); --  Grant(5,6)
+Grant(63)  <= Signal_grant(11)(7) or Signal_grant(25)(7); --  Grant(5,7)
+Grant(64)  <= Signal_grant(12)(8) or Signal_grant(26)(8); --  Grant(5,8)
+Grant(65)  <= Signal_grant(13)(9) or Signal_grant(27)(9); --  Grant(5,9)
+Grant(66)  <= Signal_grant(14)(10) ;                      --  Grant(5,10)
+Grant(67)  <= Signal_grant(1)(11) or Signal_grant(15)(11); --  Grant(5,11)
+Grant(68)  <= Signal_grant(2)(12) or Signal_grant(16)(12); --  Grant(5,12)
+Grant(69)  <= Signal_grant(3)(13) or Signal_grant(17)(13); --  Grant(5,13)
+Grant(70)  <= Signal_grant(4)(14) or Signal_grant(18)(14); --  Grant(5,14)
+Grant(71)  <= Signal_grant(6)(1) or Signal_grant(20)(1); --  Grant(6,1)
+Grant(72)  <= Signal_grant(7)(2) or Signal_grant(21)(2); --  Grant(6,2)
+Grant(73)  <= Signal_grant(8)(3) or Signal_grant(22)(3); --  Grant(6,3)
+Grant(74)  <= Signal_grant(9)(4) or Signal_grant(23)(4); --  Grant(6,4)
+Grant(75)  <= Signal_grant(10)(5) or Signal_grant(24)(5); --  Grant(6,5)
+Grant(76)  <= Signal_grant(11)(6) or Signal_grant(25)(6); --  Grant(6,6)
+Grant(77)  <= Signal_grant(12)(7) or Signal_grant(26)(7); --  Grant(6,7)
+Grant(78)  <= Signal_grant(13)(8) or Signal_grant(27)(8); --  Grant(6,8)
+Grant(79)  <= Signal_grant(14)(9) ;                      --  Grant(6,9)
+Grant(80)  <= Signal_grant(1)(10) or Signal_grant(15)(10); --  Grant(6,10)
+Grant(81)  <= Signal_grant(2)(11) or Signal_grant(16)(11); --  Grant(6,11)
+Grant(82)  <= Signal_grant(3)(12) or Signal_grant(17)(12); --  Grant(6,12)
+Grant(83)  <= Signal_grant(4)(13) or Signal_grant(18)(13); --  Grant(6,13)
+Grant(84)  <= Signal_grant(5)(14) or Signal_grant(19)(14); --  Grant(6,14)
+Grant(85)  <= Signal_grant(7)(1) or Signal_grant(21)(1); --  Grant(7,1)
+Grant(86)  <= Signal_grant(8)(2) or Signal_grant(22)(2); --  Grant(7,2)
+Grant(87)  <= Signal_grant(9)(3) or Signal_grant(23)(3); --  Grant(7,3)
+Grant(88)  <= Signal_grant(10)(4) or Signal_grant(24)(4); --  Grant(7,4)
+Grant(89)  <= Signal_grant(11)(5) or Signal_grant(25)(5); --  Grant(7,5)
+Grant(90)  <= Signal_grant(12)(6) or Signal_grant(26)(6); --  Grant(7,6)
+Grant(91)  <= Signal_grant(13)(7) or Signal_grant(27)(7); --  Grant(7,7)
+Grant(92)  <= Signal_grant(14)(8) ;                      --  Grant(7,8)
+Grant(93)  <= Signal_grant(1)(9) or Signal_grant(15)(9); --  Grant(7,9)
+Grant(94)  <= Signal_grant(2)(10) or Signal_grant(16)(10); --  Grant(7,10)
+Grant(95)  <= Signal_grant(3)(11) or Signal_grant(17)(11); --  Grant(7,11)
+Grant(96)  <= Signal_grant(4)(12) or Signal_grant(18)(12); --  Grant(7,12)
+Grant(97)  <= Signal_grant(5)(13) or Signal_grant(19)(13); --  Grant(7,13)
+Grant(98)  <= Signal_grant(6)(14) or Signal_grant(20)(14); --  Grant(7,14)
+Grant(99)  <= Signal_grant(8)(1) or Signal_grant(22)(1); --  Grant(8,1)
+Grant(100)  <= Signal_grant(9)(2) or Signal_grant(23)(2); --  Grant(8,2)
+Grant(101)  <= Signal_grant(10)(3) or Signal_grant(24)(3); --  Grant(8,3)
+Grant(102)  <= Signal_grant(11)(4) or Signal_grant(25)(4); --  Grant(8,4)
+Grant(103)  <= Signal_grant(12)(5) or Signal_grant(26)(5); --  Grant(8,5)
+Grant(104)  <= Signal_grant(13)(6) or Signal_grant(27)(6); --  Grant(8,6)
+Grant(105)  <= Signal_grant(14)(7) ;                      --  Grant(8,7)
+Grant(106)  <= Signal_grant(1)(8) or Signal_grant(15)(8); --  Grant(8,8)
+Grant(107)  <= Signal_grant(2)(9) or Signal_grant(16)(9); --  Grant(8,9)
+Grant(108)  <= Signal_grant(3)(10) or Signal_grant(17)(10); --  Grant(8,10)
+Grant(109)  <= Signal_grant(4)(11) or Signal_grant(18)(11); --  Grant(8,11)
+Grant(110)  <= Signal_grant(5)(12) or Signal_grant(19)(12); --  Grant(8,12)
+Grant(111)  <= Signal_grant(6)(13) or Signal_grant(20)(13); --  Grant(8,13)
+Grant(112)  <= Signal_grant(7)(14) or Signal_grant(21)(14); --  Grant(8,14)
+Grant(113)  <= Signal_grant(9)(1) or Signal_grant(23)(1); --  Grant(9,1)
+Grant(114)  <= Signal_grant(10)(2) or Signal_grant(24)(2); --  Grant(9,2)
+Grant(115)  <= Signal_grant(11)(3) or Signal_grant(25)(3); --  Grant(9,3)
+Grant(116)  <= Signal_grant(12)(4) or Signal_grant(26)(4); --  Grant(9,4)
+Grant(117)  <= Signal_grant(13)(5) or Signal_grant(27)(5); --  Grant(9,5)
+Grant(118)  <= Signal_grant(14)(6) ;                      --  Grant(9,6)
+Grant(119)  <= Signal_grant(1)(7) or Signal_grant(15)(7); --  Grant(9,7)
+Grant(120)  <= Signal_grant(2)(8) or Signal_grant(16)(8); --  Grant(9,8)
+Grant(121)  <= Signal_grant(3)(9) or Signal_grant(17)(9); --  Grant(9,9)
+Grant(122)  <= Signal_grant(4)(10) or Signal_grant(18)(10); --  Grant(9,10)
+Grant(123)  <= Signal_grant(5)(11) or Signal_grant(19)(11); --  Grant(9,11)
+Grant(124)  <= Signal_grant(6)(12) or Signal_grant(20)(12); --  Grant(9,12)
+Grant(125)  <= Signal_grant(7)(13) or Signal_grant(21)(13); --  Grant(9,13)
+Grant(126)  <= Signal_grant(8)(14) or Signal_grant(22)(14); --  Grant(9,14)
+Grant(127)  <= Signal_grant(10)(1) or Signal_grant(24)(1); --  Grant(10,1)
+Grant(128)  <= Signal_grant(11)(2) or Signal_grant(25)(2); --  Grant(10,2)
+Grant(129)  <= Signal_grant(12)(3) or Signal_grant(26)(3); --  Grant(10,3)
+Grant(130)  <= Signal_grant(13)(4) or Signal_grant(27)(4); --  Grant(10,4)
+Grant(131)  <= Signal_grant(14)(5) ;                      --  Grant(10,5)
+Grant(132)  <= Signal_grant(1)(6) or Signal_grant(15)(6); --  Grant(10,6)
+Grant(133)  <= Signal_grant(2)(7) or Signal_grant(16)(7); --  Grant(10,7)
+Grant(134)  <= Signal_grant(3)(8) or Signal_grant(17)(8); --  Grant(10,8)
+Grant(135)  <= Signal_grant(4)(9) or Signal_grant(18)(9); --  Grant(10,9)
+Grant(136)  <= Signal_grant(5)(10) or Signal_grant(19)(10); --  Grant(10,10)
+Grant(137)  <= Signal_grant(6)(11) or Signal_grant(20)(11); --  Grant(10,11)
+Grant(138)  <= Signal_grant(7)(12) or Signal_grant(21)(12); --  Grant(10,12)
+Grant(139)  <= Signal_grant(8)(13) or Signal_grant(22)(13); --  Grant(10,13)
+Grant(140)  <= Signal_grant(9)(14) or Signal_grant(23)(14); --  Grant(10,14)
+Grant(141)  <= Signal_grant(11)(1) or Signal_grant(25)(1); --  Grant(11,1)
+Grant(142)  <= Signal_grant(12)(2) or Signal_grant(26)(2); --  Grant(11,2)
+Grant(143)  <= Signal_grant(13)(3) or Signal_grant(27)(3); --  Grant(11,3)
+Grant(144)  <= Signal_grant(14)(4) ;                      --  Grant(11,4)
+Grant(145)  <= Signal_grant(1)(5) or Signal_grant(15)(5); --  Grant(11,5)
+Grant(146)  <= Signal_grant(2)(6) or Signal_grant(16)(6); --  Grant(11,6)
+Grant(147)  <= Signal_grant(3)(7) or Signal_grant(17)(7); --  Grant(11,7)
+Grant(148)  <= Signal_grant(4)(8) or Signal_grant(18)(8); --  Grant(11,8)
+Grant(149)  <= Signal_grant(5)(9) or Signal_grant(19)(9); --  Grant(11,9)
+Grant(150)  <= Signal_grant(6)(10) or Signal_grant(20)(10); --  Grant(11,10)
+Grant(151)  <= Signal_grant(7)(11) or Signal_grant(21)(11); --  Grant(11,11)
+Grant(152)  <= Signal_grant(8)(12) or Signal_grant(22)(12); --  Grant(11,12)
+Grant(153)  <= Signal_grant(9)(13) or Signal_grant(23)(13); --  Grant(11,13)
+Grant(154)  <= Signal_grant(10)(14) or Signal_grant(24)(14); --  Grant(11,14)
+Grant(155)  <= Signal_grant(12)(1) or Signal_grant(26)(1); --  Grant(12,1)
+Grant(156)  <= Signal_grant(13)(2) or Signal_grant(27)(2); --  Grant(12,2)
+Grant(157)  <= Signal_grant(14)(3) ;                      --  Grant(12,3)
+Grant(158)  <= Signal_grant(1)(4) or Signal_grant(15)(4); --  Grant(12,4)
+Grant(159)  <= Signal_grant(2)(5) or Signal_grant(16)(5); --  Grant(12,5)
+Grant(160)  <= Signal_grant(3)(6) or Signal_grant(17)(6); --  Grant(12,6)
+Grant(161)  <= Signal_grant(4)(7) or Signal_grant(18)(7); --  Grant(12,7)
+Grant(162)  <= Signal_grant(5)(8) or Signal_grant(19)(8); --  Grant(12,8)
+Grant(163)  <= Signal_grant(6)(9) or Signal_grant(20)(9); --  Grant(12,9)
+Grant(164)  <= Signal_grant(7)(10) or Signal_grant(21)(10); --  Grant(12,10)
+Grant(165)  <= Signal_grant(8)(11) or Signal_grant(22)(11); --  Grant(12,11)
+Grant(166)  <= Signal_grant(9)(12) or Signal_grant(23)(12); --  Grant(12,12)
+Grant(167)  <= Signal_grant(10)(13) or Signal_grant(24)(13); --  Grant(12,13)
+Grant(168)  <= Signal_grant(11)(14) or Signal_grant(25)(14); --  Grant(12,14)
+Grant(169)  <= Signal_grant(13)(1) or Signal_grant(27)(1); --  Grant(13,1)
+Grant(170)  <= Signal_grant(14)(2) ;                      --  Grant(13,2)
+Grant(171)  <= Signal_grant(1)(3) or Signal_grant(15)(3); --  Grant(13,3)
+Grant(172)  <= Signal_grant(2)(4) or Signal_grant(16)(4); --  Grant(13,4)
+Grant(173)  <= Signal_grant(3)(5) or Signal_grant(17)(5); --  Grant(13,5)
+Grant(174)  <= Signal_grant(4)(6) or Signal_grant(18)(6); --  Grant(13,6)
+Grant(175)  <= Signal_grant(5)(7) or Signal_grant(19)(7); --  Grant(13,7)
+Grant(176)  <= Signal_grant(6)(8) or Signal_grant(20)(8); --  Grant(13,8)
+Grant(177)  <= Signal_grant(7)(9) or Signal_grant(21)(9); --  Grant(13,9)
+Grant(178)  <= Signal_grant(8)(10) or Signal_grant(22)(10); --  Grant(13,10)
+Grant(179)  <= Signal_grant(9)(11) or Signal_grant(23)(11); --  Grant(13,11)
+Grant(180)  <= Signal_grant(10)(12) or Signal_grant(24)(12); --  Grant(13,12)
+Grant(181)  <= Signal_grant(11)(13) or Signal_grant(25)(13); --  Grant(13,13)
+Grant(182)  <= Signal_grant(12)(14) or Signal_grant(26)(14); --  Grant(13,14)
+Grant(183)  <= Signal_grant(14)(1) ;                      --  Grant(14,1)
+Grant(184)  <= Signal_grant(1)(2) or Signal_grant(15)(2); --  Grant(14,2)
+Grant(185)  <= Signal_grant(2)(3) or Signal_grant(16)(3); --  Grant(14,3)
+Grant(186)  <= Signal_grant(3)(4) or Signal_grant(17)(4); --  Grant(14,4)
+Grant(187)  <= Signal_grant(4)(5) or Signal_grant(18)(5); --  Grant(14,5)
+Grant(188)  <= Signal_grant(5)(6) or Signal_grant(19)(6); --  Grant(14,6)
+Grant(189)  <= Signal_grant(6)(7) or Signal_grant(20)(7); --  Grant(14,7)
+Grant(190)  <= Signal_grant(7)(8) or Signal_grant(21)(8); --  Grant(14,8)
+Grant(191)  <= Signal_grant(8)(9) or Signal_grant(22)(9); --  Grant(14,9)
+Grant(192)  <= Signal_grant(9)(10) or Signal_grant(23)(10); --  Grant(14,10)
+Grant(193)  <= Signal_grant(10)(11) or Signal_grant(24)(11); --  Grant(14,11)
+Grant(194)  <= Signal_grant(11)(12) or Signal_grant(25)(12); --  Grant(14,12)
+Grant(195)  <= Signal_grant(12)(13) or Signal_grant(26)(13); --  Grant(14,13)
+Grant(196)  <= Signal_grant(13)(14) or Signal_grant(27)(14); --  Grant(14,14)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(184), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(171), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(158), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(145), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(132), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(119), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(106), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(93), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+Arbiter_1_10 : Arbiter
+
+PORT MAP (Request => Request(80), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(10),  
+South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); 
+
+Arbiter_1_11 : Arbiter
+
+PORT MAP (Request => Request(67), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(11),  
+South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); 
+
+Arbiter_1_12 : Arbiter
+
+PORT MAP (Request => Request(54), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(12),  
+South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); 
+
+Arbiter_1_13 : Arbiter
+
+PORT MAP (Request => Request(41), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(13),  
+South => south_2_north(1)(13), East => east_2_west(1)(13) , Grant => Signal_grant(1)(13)); 
+
+Arbiter_1_14 : Arbiter
+
+PORT MAP (Request => Request(28), North => High, West => High, P => Signal_priority(27), Fifo_full => Fifo_full(14),  
+South => south_2_north(1)(14), East => east_2_west(1)(14) , Grant => Signal_grant(1)(14)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(1)(1), West => east_2_west(1)(14), P => Signal_priority(26), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(26), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(185), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(26), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(172), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(26), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(26), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(146), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(26), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(26), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(26), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(26), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+Arbiter_2_10 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(26), Fifo_full => Fifo_full(10),  
+South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); 
+
+Arbiter_2_11 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(26), Fifo_full => Fifo_full(11),  
+South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); 
+
+Arbiter_2_12 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(26), Fifo_full => Fifo_full(12),  
+South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); 
+
+Arbiter_2_13 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(1)(13), West => east_2_west(1)(12), P => Signal_priority(26), Fifo_full => Fifo_full(13),  
+South => south_2_north(2)(13), East => east_2_west(2)(13) , Grant => Signal_grant(2)(13)); 
+
+Arbiter_2_14 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(1)(14), West => east_2_west(1)(13), P => Signal_priority(26), Fifo_full => Fifo_full(14),  
+South => south_2_north(2)(14), East => east_2_west(2)(14) , Grant => Signal_grant(2)(14)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(2)(1), West => east_2_west(2)(14), P => Signal_priority(25), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(25), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(25), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(186), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(25), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(173), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(25), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(25), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(25), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(25), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(25), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+Arbiter_3_10 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(25), Fifo_full => Fifo_full(10),  
+South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); 
+
+Arbiter_3_11 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(25), Fifo_full => Fifo_full(11),  
+South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); 
+
+Arbiter_3_12 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(25), Fifo_full => Fifo_full(12),  
+South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); 
+
+Arbiter_3_13 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(2)(13), West => east_2_west(2)(12), P => Signal_priority(25), Fifo_full => Fifo_full(13),  
+South => south_2_north(3)(13), East => east_2_west(3)(13) , Grant => Signal_grant(3)(13)); 
+
+Arbiter_3_14 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(2)(14), West => east_2_west(2)(13), P => Signal_priority(25), Fifo_full => Fifo_full(14),  
+South => south_2_north(3)(14), East => east_2_west(3)(14) , Grant => Signal_grant(3)(14)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(3)(1), West => east_2_west(3)(14), P => Signal_priority(24), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(24), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(24), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(24), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(187), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(24), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(174), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(24), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(24), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(24), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(24), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+Arbiter_4_10 : Arbiter
+
+PORT MAP (Request => Request(122), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(24), Fifo_full => Fifo_full(10),  
+South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); 
+
+Arbiter_4_11 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(24), Fifo_full => Fifo_full(11),  
+South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); 
+
+Arbiter_4_12 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(24), Fifo_full => Fifo_full(12),  
+South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); 
+
+Arbiter_4_13 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(3)(13), West => east_2_west(3)(12), P => Signal_priority(24), Fifo_full => Fifo_full(13),  
+South => south_2_north(4)(13), East => east_2_west(4)(13) , Grant => Signal_grant(4)(13)); 
+
+Arbiter_4_14 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(3)(14), West => east_2_west(3)(13), P => Signal_priority(24), Fifo_full => Fifo_full(14),  
+South => south_2_north(4)(14), East => east_2_west(4)(14) , Grant => Signal_grant(4)(14)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(4)(1), West => east_2_west(4)(14), P => Signal_priority(23), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(23), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(23), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(23), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(23), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(188), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(23), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(175), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(23), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(23), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(23), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+Arbiter_5_10 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(23), Fifo_full => Fifo_full(10),  
+South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); 
+
+Arbiter_5_11 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(23), Fifo_full => Fifo_full(11),  
+South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); 
+
+Arbiter_5_12 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(23), Fifo_full => Fifo_full(12),  
+South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); 
+
+Arbiter_5_13 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(4)(13), West => east_2_west(4)(12), P => Signal_priority(23), Fifo_full => Fifo_full(13),  
+South => south_2_north(5)(13), East => east_2_west(5)(13) , Grant => Signal_grant(5)(13)); 
+
+Arbiter_5_14 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(4)(14), West => east_2_west(4)(13), P => Signal_priority(23), Fifo_full => Fifo_full(14),  
+South => south_2_north(5)(14), East => east_2_west(5)(14) , Grant => Signal_grant(5)(14)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(5)(1), West => east_2_west(5)(14), P => Signal_priority(22), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(189), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(176), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+Arbiter_6_10 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10),  
+South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); 
+
+Arbiter_6_11 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11),  
+South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); 
+
+Arbiter_6_12 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12),  
+South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); 
+
+Arbiter_6_13 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(5)(13), West => east_2_west(5)(12), P => Signal_priority(22), Fifo_full => Fifo_full(13),  
+South => south_2_north(6)(13), East => east_2_west(6)(13) , Grant => Signal_grant(6)(13)); 
+
+Arbiter_6_14 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(5)(14), West => east_2_west(5)(13), P => Signal_priority(22), Fifo_full => Fifo_full(14),  
+South => south_2_north(6)(14), East => east_2_west(6)(14) , Grant => Signal_grant(6)(14)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(6)(1), West => east_2_west(6)(14), P => Signal_priority(21), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(190), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(177), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+Arbiter_7_10 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10),  
+South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); 
+
+Arbiter_7_11 : Arbiter
+
+PORT MAP (Request => Request(151), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11),  
+South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); 
+
+Arbiter_7_12 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12),  
+South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); 
+
+Arbiter_7_13 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(6)(13), West => east_2_west(6)(12), P => Signal_priority(21), Fifo_full => Fifo_full(13),  
+South => south_2_north(7)(13), East => east_2_west(7)(13) , Grant => Signal_grant(7)(13)); 
+
+Arbiter_7_14 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(6)(14), West => east_2_west(6)(13), P => Signal_priority(21), Fifo_full => Fifo_full(14),  
+South => south_2_north(7)(14), East => east_2_west(7)(14) , Grant => Signal_grant(7)(14)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(7)(1), West => east_2_west(7)(14), P => Signal_priority(20), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(191), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+Arbiter_8_10 : Arbiter
+
+PORT MAP (Request => Request(178), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10),  
+South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); 
+
+Arbiter_8_11 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11),  
+South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); 
+
+Arbiter_8_12 : Arbiter
+
+PORT MAP (Request => Request(152), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12),  
+South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); 
+
+Arbiter_8_13 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(7)(13), West => east_2_west(7)(12), P => Signal_priority(20), Fifo_full => Fifo_full(13),  
+South => south_2_north(8)(13), East => east_2_west(8)(13) , Grant => Signal_grant(8)(13)); 
+
+Arbiter_8_14 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(7)(14), West => east_2_west(7)(13), P => Signal_priority(20), Fifo_full => Fifo_full(14),  
+South => south_2_north(8)(14), East => east_2_west(8)(14) , Grant => Signal_grant(8)(14)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(8)(1), West => east_2_west(8)(14), P => Signal_priority(19), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+Arbiter_9_10 : Arbiter
+
+PORT MAP (Request => Request(192), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10),  
+South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); 
+
+Arbiter_9_11 : Arbiter
+
+PORT MAP (Request => Request(179), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11),  
+South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); 
+
+Arbiter_9_12 : Arbiter
+
+PORT MAP (Request => Request(166), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12),  
+South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); 
+
+Arbiter_9_13 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(8)(13), West => east_2_west(8)(12), P => Signal_priority(19), Fifo_full => Fifo_full(13),  
+South => south_2_north(9)(13), East => east_2_west(9)(13) , Grant => Signal_grant(9)(13)); 
+
+Arbiter_9_14 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(8)(14), West => east_2_west(8)(13), P => Signal_priority(19), Fifo_full => Fifo_full(14),  
+South => south_2_north(9)(14), East => east_2_west(9)(14) , Grant => Signal_grant(9)(14)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(9)(1), West => east_2_west(9)(14), P => Signal_priority(18), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+Arbiter_10_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10),  
+South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); 
+
+Arbiter_10_11 : Arbiter
+
+PORT MAP (Request => Request(193), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11),  
+South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); 
+
+Arbiter_10_12 : Arbiter
+
+PORT MAP (Request => Request(180), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12),  
+South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); 
+
+Arbiter_10_13 : Arbiter
+
+PORT MAP (Request => Request(167), North => south_2_north(9)(13), West => east_2_west(9)(12), P => Signal_priority(18), Fifo_full => Fifo_full(13),  
+South => south_2_north(10)(13), East => east_2_west(10)(13) , Grant => Signal_grant(10)(13)); 
+
+Arbiter_10_14 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(9)(14), West => east_2_west(9)(13), P => Signal_priority(18), Fifo_full => Fifo_full(14),  
+South => south_2_north(10)(14), East => east_2_west(10)(14) , Grant => Signal_grant(10)(14)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(10)(1), West => east_2_west(10)(14), P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+Arbiter_11_10 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10),  
+South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); 
+
+Arbiter_11_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11),  
+South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); 
+
+Arbiter_11_12 : Arbiter
+
+PORT MAP (Request => Request(194), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12),  
+South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); 
+
+Arbiter_11_13 : Arbiter
+
+PORT MAP (Request => Request(181), North => south_2_north(10)(13), West => east_2_west(10)(12), P => Signal_priority(17), Fifo_full => Fifo_full(13),  
+South => south_2_north(11)(13), East => east_2_west(11)(13) , Grant => Signal_grant(11)(13)); 
+
+Arbiter_11_14 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(10)(14), West => east_2_west(10)(13), P => Signal_priority(17), Fifo_full => Fifo_full(14),  
+South => south_2_north(11)(14), East => east_2_west(11)(14) , Grant => Signal_grant(11)(14)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(155), North => south_2_north(11)(1), West => east_2_west(11)(14), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+Arbiter_12_10 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10),  
+South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); 
+
+Arbiter_12_11 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11),  
+South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); 
+
+Arbiter_12_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12),  
+South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); 
+
+Arbiter_12_13 : Arbiter
+
+PORT MAP (Request => Request(195), North => south_2_north(11)(13), West => east_2_west(11)(12), P => Signal_priority(16), Fifo_full => Fifo_full(13),  
+South => south_2_north(12)(13), East => east_2_west(12)(13) , Grant => Signal_grant(12)(13)); 
+
+Arbiter_12_14 : Arbiter
+
+PORT MAP (Request => Request(182), North => south_2_north(11)(14), West => east_2_west(11)(13), P => Signal_priority(16), Fifo_full => Fifo_full(14),  
+South => south_2_north(12)(14), East => east_2_west(12)(14) , Grant => Signal_grant(12)(14)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(169), North => south_2_north(12)(1), West => east_2_west(12)(14), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(156), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+Arbiter_13_10 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10),  
+South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); 
+
+Arbiter_13_11 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11),  
+South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); 
+
+Arbiter_13_12 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12),  
+South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); 
+
+Arbiter_13_13 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(12)(13), West => east_2_west(12)(12), P => Signal_priority(15), Fifo_full => Fifo_full(13),  
+South => south_2_north(13)(13), East => east_2_west(13)(13) , Grant => Signal_grant(13)(13)); 
+
+Arbiter_13_14 : Arbiter
+
+PORT MAP (Request => Request(196), North => south_2_north(12)(14), West => east_2_west(12)(13), P => Signal_priority(15), Fifo_full => Fifo_full(14),  
+South => south_2_north(13)(14), East => east_2_west(13)(14) , Grant => Signal_grant(13)(14)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(183), North => south_2_north(13)(1), West => east_2_west(13)(14), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(170), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(157), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+Arbiter_14_10 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10),  
+South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); 
+
+Arbiter_14_11 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11),  
+South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); 
+
+Arbiter_14_12 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12),  
+South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); 
+
+Arbiter_14_13 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(13)(13), West => east_2_west(13)(12), P => Signal_priority(14), Fifo_full => Fifo_full(13),  
+South => south_2_north(14)(13), East => east_2_west(14)(13) , Grant => Signal_grant(14)(13)); 
+
+Arbiter_14_14 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(13)(14), West => east_2_west(13)(13), P => Signal_priority(14), Fifo_full => Fifo_full(14),  
+South => south_2_north(14)(14), East => east_2_west(14)(14) , Grant => Signal_grant(14)(14)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(14)(1), West => east_2_west(14)(14), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(184), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(171), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(158), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(145), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+Arbiter_15_10 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10),  
+South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); 
+
+Arbiter_15_11 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11),  
+South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); 
+
+Arbiter_15_12 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12),  
+South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); 
+
+Arbiter_15_13 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(14)(13), West => east_2_west(14)(12), P => Signal_priority(13), Fifo_full => Fifo_full(13),  
+South => south_2_north(15)(13), East => east_2_west(15)(13) , Grant => Signal_grant(15)(13)); 
+
+Arbiter_15_14 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(14)(14), West => east_2_west(14)(13), P => Signal_priority(13), Fifo_full => Fifo_full(14),  
+South => south_2_north(15)(14), East => east_2_west(15)(14) , Grant => Signal_grant(15)(14)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(15)(1), West => east_2_west(15)(14), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(185), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(172), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(146), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+Arbiter_16_10 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10),  
+South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); 
+
+Arbiter_16_11 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11),  
+South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); 
+
+Arbiter_16_12 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12),  
+South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); 
+
+Arbiter_16_13 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(15)(13), West => east_2_west(15)(12), P => Signal_priority(12), Fifo_full => Fifo_full(13),  
+South => south_2_north(16)(13), East => east_2_west(16)(13) , Grant => Signal_grant(16)(13)); 
+
+Arbiter_16_14 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(15)(14), West => east_2_west(15)(13), P => Signal_priority(12), Fifo_full => Fifo_full(14),  
+South => south_2_north(16)(14), East => east_2_west(16)(14) , Grant => Signal_grant(16)(14)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(16)(1), West => east_2_west(16)(14), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(186), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(173), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+Arbiter_17_10 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10),  
+South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); 
+
+Arbiter_17_11 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11),  
+South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); 
+
+Arbiter_17_12 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12),  
+South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); 
+
+Arbiter_17_13 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(16)(13), West => east_2_west(16)(12), P => Signal_priority(11), Fifo_full => Fifo_full(13),  
+South => south_2_north(17)(13), East => east_2_west(17)(13) , Grant => Signal_grant(17)(13)); 
+
+Arbiter_17_14 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(16)(14), West => east_2_west(16)(13), P => Signal_priority(11), Fifo_full => Fifo_full(14),  
+South => south_2_north(17)(14), East => east_2_west(17)(14) , Grant => Signal_grant(17)(14)); 
+
+-------------------------- Diagonale n° 18 
+
+
+Arbiter_18_1 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(17)(1), West => east_2_west(17)(14), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); 
+
+Arbiter_18_2 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); 
+
+Arbiter_18_3 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); 
+
+Arbiter_18_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); 
+
+Arbiter_18_5 : Arbiter
+
+PORT MAP (Request => Request(187), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); 
+
+Arbiter_18_6 : Arbiter
+
+PORT MAP (Request => Request(174), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); 
+
+Arbiter_18_7 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); 
+
+Arbiter_18_8 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); 
+
+Arbiter_18_9 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); 
+
+Arbiter_18_10 : Arbiter
+
+PORT MAP (Request => Request(122), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10),  
+South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); 
+
+Arbiter_18_11 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11),  
+South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); 
+
+Arbiter_18_12 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12),  
+South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); 
+
+Arbiter_18_13 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(17)(13), West => east_2_west(17)(12), P => Signal_priority(10), Fifo_full => Fifo_full(13),  
+South => south_2_north(18)(13), East => east_2_west(18)(13) , Grant => Signal_grant(18)(13)); 
+
+Arbiter_18_14 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(17)(14), West => east_2_west(17)(13), P => Signal_priority(10), Fifo_full => Fifo_full(14),  
+South => south_2_north(18)(14), East => east_2_west(18)(14) , Grant => Signal_grant(18)(14)); 
+
+-------------------------- Diagonale n° 19 
+
+
+Arbiter_19_1 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(18)(1), West => east_2_west(18)(14), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); 
+
+Arbiter_19_2 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); 
+
+Arbiter_19_3 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); 
+
+Arbiter_19_4 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); 
+
+Arbiter_19_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); 
+
+Arbiter_19_6 : Arbiter
+
+PORT MAP (Request => Request(188), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); 
+
+Arbiter_19_7 : Arbiter
+
+PORT MAP (Request => Request(175), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); 
+
+Arbiter_19_8 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); 
+
+Arbiter_19_9 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); 
+
+Arbiter_19_10 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10),  
+South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); 
+
+Arbiter_19_11 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11),  
+South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); 
+
+Arbiter_19_12 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12),  
+South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); 
+
+Arbiter_19_13 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(18)(13), West => east_2_west(18)(12), P => Signal_priority(9), Fifo_full => Fifo_full(13),  
+South => south_2_north(19)(13), East => east_2_west(19)(13) , Grant => Signal_grant(19)(13)); 
+
+Arbiter_19_14 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(18)(14), West => east_2_west(18)(13), P => Signal_priority(9), Fifo_full => Fifo_full(14),  
+South => south_2_north(19)(14), East => east_2_west(19)(14) , Grant => Signal_grant(19)(14)); 
+
+-------------------------- Diagonale n° 20 
+
+
+Arbiter_20_1 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(19)(1), West => east_2_west(19)(14), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); 
+
+Arbiter_20_2 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); 
+
+Arbiter_20_3 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); 
+
+Arbiter_20_4 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); 
+
+Arbiter_20_5 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); 
+
+Arbiter_20_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); 
+
+Arbiter_20_7 : Arbiter
+
+PORT MAP (Request => Request(189), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); 
+
+Arbiter_20_8 : Arbiter
+
+PORT MAP (Request => Request(176), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); 
+
+Arbiter_20_9 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); 
+
+Arbiter_20_10 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10),  
+South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); 
+
+Arbiter_20_11 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11),  
+South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); 
+
+Arbiter_20_12 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12),  
+South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); 
+
+Arbiter_20_13 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(19)(13), West => east_2_west(19)(12), P => Signal_priority(8), Fifo_full => Fifo_full(13),  
+South => south_2_north(20)(13), East => east_2_west(20)(13) , Grant => Signal_grant(20)(13)); 
+
+Arbiter_20_14 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(19)(14), West => east_2_west(19)(13), P => Signal_priority(8), Fifo_full => Fifo_full(14),  
+South => south_2_north(20)(14), East => east_2_west(20)(14) , Grant => Signal_grant(20)(14)); 
+
+-------------------------- Diagonale n° 21 
+
+
+Arbiter_21_1 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(20)(1), West => east_2_west(20)(14), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); 
+
+Arbiter_21_2 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); 
+
+Arbiter_21_3 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); 
+
+Arbiter_21_4 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); 
+
+Arbiter_21_5 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); 
+
+Arbiter_21_6 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); 
+
+Arbiter_21_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); 
+
+Arbiter_21_8 : Arbiter
+
+PORT MAP (Request => Request(190), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); 
+
+Arbiter_21_9 : Arbiter
+
+PORT MAP (Request => Request(177), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); 
+
+Arbiter_21_10 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10),  
+South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); 
+
+Arbiter_21_11 : Arbiter
+
+PORT MAP (Request => Request(151), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11),  
+South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); 
+
+Arbiter_21_12 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12),  
+South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); 
+
+Arbiter_21_13 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(20)(13), West => east_2_west(20)(12), P => Signal_priority(7), Fifo_full => Fifo_full(13),  
+South => south_2_north(21)(13), East => east_2_west(21)(13) , Grant => Signal_grant(21)(13)); 
+
+Arbiter_21_14 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(20)(14), West => east_2_west(20)(13), P => Signal_priority(7), Fifo_full => Fifo_full(14),  
+South => south_2_north(21)(14), East => east_2_west(21)(14) , Grant => Signal_grant(21)(14)); 
+
+-------------------------- Diagonale n° 22 
+
+
+Arbiter_22_1 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(21)(1), West => east_2_west(21)(14), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); 
+
+Arbiter_22_2 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); 
+
+Arbiter_22_3 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); 
+
+Arbiter_22_4 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); 
+
+Arbiter_22_5 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); 
+
+Arbiter_22_6 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); 
+
+Arbiter_22_7 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); 
+
+Arbiter_22_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); 
+
+Arbiter_22_9 : Arbiter
+
+PORT MAP (Request => Request(191), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); 
+
+Arbiter_22_10 : Arbiter
+
+PORT MAP (Request => Request(178), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10),  
+South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); 
+
+Arbiter_22_11 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11),  
+South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); 
+
+Arbiter_22_12 : Arbiter
+
+PORT MAP (Request => Request(152), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12),  
+South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); 
+
+Arbiter_22_13 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(21)(13), West => east_2_west(21)(12), P => Signal_priority(6), Fifo_full => Fifo_full(13),  
+South => south_2_north(22)(13), East => east_2_west(22)(13) , Grant => Signal_grant(22)(13)); 
+
+Arbiter_22_14 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(21)(14), West => east_2_west(21)(13), P => Signal_priority(6), Fifo_full => Fifo_full(14),  
+South => south_2_north(22)(14), East => east_2_west(22)(14) , Grant => Signal_grant(22)(14)); 
+
+-------------------------- Diagonale n° 23 
+
+
+Arbiter_23_1 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(22)(1), West => east_2_west(22)(14), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); 
+
+Arbiter_23_2 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); 
+
+Arbiter_23_3 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); 
+
+Arbiter_23_4 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); 
+
+Arbiter_23_5 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); 
+
+Arbiter_23_6 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); 
+
+Arbiter_23_7 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); 
+
+Arbiter_23_8 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); 
+
+Arbiter_23_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); 
+
+Arbiter_23_10 : Arbiter
+
+PORT MAP (Request => Request(192), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10),  
+South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); 
+
+Arbiter_23_11 : Arbiter
+
+PORT MAP (Request => Request(179), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11),  
+South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); 
+
+Arbiter_23_12 : Arbiter
+
+PORT MAP (Request => Request(166), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12),  
+South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); 
+
+Arbiter_23_13 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(22)(13), West => east_2_west(22)(12), P => Signal_priority(5), Fifo_full => Fifo_full(13),  
+South => south_2_north(23)(13), East => east_2_west(23)(13) , Grant => Signal_grant(23)(13)); 
+
+Arbiter_23_14 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(22)(14), West => east_2_west(22)(13), P => Signal_priority(5), Fifo_full => Fifo_full(14),  
+South => south_2_north(23)(14), East => east_2_west(23)(14) , Grant => Signal_grant(23)(14)); 
+
+-------------------------- Diagonale n° 24 
+
+
+Arbiter_24_1 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(23)(1), West => east_2_west(23)(14), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(24)(1), East => east_2_west(24)(1) , Grant => Signal_grant(24)(1)); 
+
+Arbiter_24_2 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(23)(2), West => east_2_west(23)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(24)(2), East => east_2_west(24)(2) , Grant => Signal_grant(24)(2)); 
+
+Arbiter_24_3 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(23)(3), West => east_2_west(23)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(24)(3), East => east_2_west(24)(3) , Grant => Signal_grant(24)(3)); 
+
+Arbiter_24_4 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(23)(4), West => east_2_west(23)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(24)(4), East => east_2_west(24)(4) , Grant => Signal_grant(24)(4)); 
+
+Arbiter_24_5 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(23)(5), West => east_2_west(23)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(24)(5), East => east_2_west(24)(5) , Grant => Signal_grant(24)(5)); 
+
+Arbiter_24_6 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(23)(6), West => east_2_west(23)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(24)(6), East => east_2_west(24)(6) , Grant => Signal_grant(24)(6)); 
+
+Arbiter_24_7 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(23)(7), West => east_2_west(23)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(24)(7), East => east_2_west(24)(7) , Grant => Signal_grant(24)(7)); 
+
+Arbiter_24_8 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(23)(8), West => east_2_west(23)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(24)(8), East => east_2_west(24)(8) , Grant => Signal_grant(24)(8)); 
+
+Arbiter_24_9 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(23)(9), West => east_2_west(23)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(24)(9), East => east_2_west(24)(9) , Grant => Signal_grant(24)(9)); 
+
+Arbiter_24_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(23)(10), West => east_2_west(23)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10),  
+South => south_2_north(24)(10), East => east_2_west(24)(10) , Grant => Signal_grant(24)(10)); 
+
+Arbiter_24_11 : Arbiter
+
+PORT MAP (Request => Request(193), North => south_2_north(23)(11), West => east_2_west(23)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11),  
+South => south_2_north(24)(11), East => east_2_west(24)(11) , Grant => Signal_grant(24)(11)); 
+
+Arbiter_24_12 : Arbiter
+
+PORT MAP (Request => Request(180), North => south_2_north(23)(12), West => east_2_west(23)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12),  
+South => south_2_north(24)(12), East => east_2_west(24)(12) , Grant => Signal_grant(24)(12)); 
+
+Arbiter_24_13 : Arbiter
+
+PORT MAP (Request => Request(167), North => south_2_north(23)(13), West => east_2_west(23)(12), P => Signal_priority(4), Fifo_full => Fifo_full(13),  
+South => south_2_north(24)(13), East => east_2_west(24)(13) , Grant => Signal_grant(24)(13)); 
+
+Arbiter_24_14 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(23)(14), West => east_2_west(23)(13), P => Signal_priority(4), Fifo_full => Fifo_full(14),  
+South => south_2_north(24)(14), East => east_2_west(24)(14) , Grant => Signal_grant(24)(14)); 
+
+-------------------------- Diagonale n° 25 
+
+
+Arbiter_25_1 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(24)(1), West => east_2_west(24)(14), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(25)(1), East => east_2_west(25)(1) , Grant => Signal_grant(25)(1)); 
+
+Arbiter_25_2 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(24)(2), West => east_2_west(24)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(25)(2), East => east_2_west(25)(2) , Grant => Signal_grant(25)(2)); 
+
+Arbiter_25_3 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(24)(3), West => east_2_west(24)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(25)(3), East => east_2_west(25)(3) , Grant => Signal_grant(25)(3)); 
+
+Arbiter_25_4 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(24)(4), West => east_2_west(24)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(25)(4), East => east_2_west(25)(4) , Grant => Signal_grant(25)(4)); 
+
+Arbiter_25_5 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(24)(5), West => east_2_west(24)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(25)(5), East => east_2_west(25)(5) , Grant => Signal_grant(25)(5)); 
+
+Arbiter_25_6 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(24)(6), West => east_2_west(24)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(25)(6), East => east_2_west(25)(6) , Grant => Signal_grant(25)(6)); 
+
+Arbiter_25_7 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(24)(7), West => east_2_west(24)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(25)(7), East => east_2_west(25)(7) , Grant => Signal_grant(25)(7)); 
+
+Arbiter_25_8 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(24)(8), West => east_2_west(24)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(25)(8), East => east_2_west(25)(8) , Grant => Signal_grant(25)(8)); 
+
+Arbiter_25_9 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(24)(9), West => east_2_west(24)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(25)(9), East => east_2_west(25)(9) , Grant => Signal_grant(25)(9)); 
+
+Arbiter_25_10 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(24)(10), West => east_2_west(24)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10),  
+South => south_2_north(25)(10), East => east_2_west(25)(10) , Grant => Signal_grant(25)(10)); 
+
+Arbiter_25_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(24)(11), West => east_2_west(24)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11),  
+South => south_2_north(25)(11), East => east_2_west(25)(11) , Grant => Signal_grant(25)(11)); 
+
+Arbiter_25_12 : Arbiter
+
+PORT MAP (Request => Request(194), North => south_2_north(24)(12), West => east_2_west(24)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12),  
+South => south_2_north(25)(12), East => east_2_west(25)(12) , Grant => Signal_grant(25)(12)); 
+
+Arbiter_25_13 : Arbiter
+
+PORT MAP (Request => Request(181), North => south_2_north(24)(13), West => east_2_west(24)(12), P => Signal_priority(3), Fifo_full => Fifo_full(13),  
+South => south_2_north(25)(13), East => east_2_west(25)(13) , Grant => Signal_grant(25)(13)); 
+
+Arbiter_25_14 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(24)(14), West => east_2_west(24)(13), P => Signal_priority(3), Fifo_full => Fifo_full(14),  
+South => south_2_north(25)(14), East => east_2_west(25)(14) , Grant => Signal_grant(25)(14)); 
+
+-------------------------- Diagonale n° 26 
+
+
+Arbiter_26_1 : Arbiter
+
+PORT MAP (Request => Request(155), North => south_2_north(25)(1), West => east_2_west(25)(14), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(26)(1), East => east_2_west(26)(1) , Grant => Signal_grant(26)(1)); 
+
+Arbiter_26_2 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(25)(2), West => east_2_west(25)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(26)(2), East => east_2_west(26)(2) , Grant => Signal_grant(26)(2)); 
+
+Arbiter_26_3 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(25)(3), West => east_2_west(25)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(26)(3), East => east_2_west(26)(3) , Grant => Signal_grant(26)(3)); 
+
+Arbiter_26_4 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(25)(4), West => east_2_west(25)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(26)(4), East => east_2_west(26)(4) , Grant => Signal_grant(26)(4)); 
+
+Arbiter_26_5 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(25)(5), West => east_2_west(25)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(26)(5), East => east_2_west(26)(5) , Grant => Signal_grant(26)(5)); 
+
+Arbiter_26_6 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(25)(6), West => east_2_west(25)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(26)(6), East => east_2_west(26)(6) , Grant => Signal_grant(26)(6)); 
+
+Arbiter_26_7 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(25)(7), West => east_2_west(25)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(26)(7), East => east_2_west(26)(7) , Grant => Signal_grant(26)(7)); 
+
+Arbiter_26_8 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(25)(8), West => east_2_west(25)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(26)(8), East => east_2_west(26)(8) , Grant => Signal_grant(26)(8)); 
+
+Arbiter_26_9 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(25)(9), West => east_2_west(25)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(26)(9), East => east_2_west(26)(9) , Grant => Signal_grant(26)(9)); 
+
+Arbiter_26_10 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(25)(10), West => east_2_west(25)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10),  
+South => south_2_north(26)(10), East => east_2_west(26)(10) , Grant => Signal_grant(26)(10)); 
+
+Arbiter_26_11 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(25)(11), West => east_2_west(25)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11),  
+South => south_2_north(26)(11), East => east_2_west(26)(11) , Grant => Signal_grant(26)(11)); 
+
+Arbiter_26_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(25)(12), West => east_2_west(25)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12),  
+South => south_2_north(26)(12), East => east_2_west(26)(12) , Grant => Signal_grant(26)(12)); 
+
+Arbiter_26_13 : Arbiter
+
+PORT MAP (Request => Request(195), North => south_2_north(25)(13), West => east_2_west(25)(12), P => Signal_priority(2), Fifo_full => Fifo_full(13),  
+South => south_2_north(26)(13), East => east_2_west(26)(13) , Grant => Signal_grant(26)(13)); 
+
+Arbiter_26_14 : Arbiter
+
+PORT MAP (Request => Request(182), North => south_2_north(25)(14), West => east_2_west(25)(13), P => Signal_priority(2), Fifo_full => Fifo_full(14),  
+South => south_2_north(26)(14), East => east_2_west(26)(14) , Grant => Signal_grant(26)(14)); 
+
+-------------------------- Diagonale n° 27 
+
+
+Arbiter_27_1 : Arbiter
+
+PORT MAP (Request => Request(169), North => south_2_north(26)(1), West => east_2_west(26)(14), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(27)(1), East => east_2_west(27)(1) , Grant => Signal_grant(27)(1)); 
+
+Arbiter_27_2 : Arbiter
+
+PORT MAP (Request => Request(156), North => south_2_north(26)(2), West => east_2_west(26)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(27)(2), East => east_2_west(27)(2) , Grant => Signal_grant(27)(2)); 
+
+Arbiter_27_3 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(26)(3), West => east_2_west(26)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(27)(3), East => east_2_west(27)(3) , Grant => Signal_grant(27)(3)); 
+
+Arbiter_27_4 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(26)(4), West => east_2_west(26)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(27)(4), East => east_2_west(27)(4) , Grant => Signal_grant(27)(4)); 
+
+Arbiter_27_5 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(26)(5), West => east_2_west(26)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(27)(5), East => east_2_west(27)(5) , Grant => Signal_grant(27)(5)); 
+
+Arbiter_27_6 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(26)(6), West => east_2_west(26)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(27)(6), East => east_2_west(27)(6) , Grant => Signal_grant(27)(6)); 
+
+Arbiter_27_7 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(26)(7), West => east_2_west(26)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(27)(7), East => east_2_west(27)(7) , Grant => Signal_grant(27)(7)); 
+
+Arbiter_27_8 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(26)(8), West => east_2_west(26)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(27)(8), East => east_2_west(27)(8) , Grant => Signal_grant(27)(8)); 
+
+Arbiter_27_9 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(26)(9), West => east_2_west(26)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(27)(9), East => east_2_west(27)(9) , Grant => Signal_grant(27)(9)); 
+
+Arbiter_27_10 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(26)(10), West => east_2_west(26)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10),  
+South => south_2_north(27)(10), East => east_2_west(27)(10) , Grant => Signal_grant(27)(10)); 
+
+Arbiter_27_11 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(26)(11), West => east_2_west(26)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11),  
+South => south_2_north(27)(11), East => east_2_west(27)(11) , Grant => Signal_grant(27)(11)); 
+
+Arbiter_27_12 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(26)(12), West => east_2_west(26)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12),  
+South => south_2_north(27)(12), East => east_2_west(27)(12) , Grant => Signal_grant(27)(12)); 
+
+Arbiter_27_13 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(26)(13), West => east_2_west(26)(12), P => Signal_priority(1), Fifo_full => Fifo_full(13),  
+South => south_2_north(27)(13), East => east_2_west(27)(13) , Grant => Signal_grant(27)(13)); 
+
+Arbiter_27_14 : Arbiter
+
+PORT MAP (Request => Request(196), North => south_2_north(26)(14), West => east_2_west(26)(13), P => Signal_priority(1), Fifo_full => Fifo_full(14),  
+South => south_2_north(27)(14), East => east_2_west(27)(14) , Grant => Signal_grant(27)(14)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "111111111111110000000000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "111111111111110000000000000" => Signal_priority <= "011111111111111000000000000";
+		       when "011111111111111000000000000" => Signal_priority <= "001111111111111100000000000";
+		       when "001111111111111100000000000" => Signal_priority <= "000111111111111110000000000";
+		       when "000111111111111110000000000" => Signal_priority <= "000011111111111111000000000";
+		       when "000011111111111111000000000" => Signal_priority <= "000001111111111111100000000";
+		       when "000001111111111111100000000" => Signal_priority <= "000000111111111111110000000";
+		       when "000000111111111111110000000" => Signal_priority <= "000000011111111111111000000";
+		       when "000000011111111111111000000" => Signal_priority <= "000000001111111111111100000";
+		       when "000000001111111111111100000" => Signal_priority <= "000000000111111111111110000";
+		       when "000000000111111111111110000" => Signal_priority <= "000000000011111111111111000";
+		       when "000000000011111111111111000" => Signal_priority <= "000000000001111111111111100";
+		       when "000000000001111111111111100" => Signal_priority <= "000000000000111111111111110";
+		       when "000000000000111111111111110" => Signal_priority <= "000000000000011111111111111";
+		       when "000000000000011111111111111" => Signal_priority <= "111111111111110000000000000";
+		       when others    => Signal_priority <= "111111111111110000000000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER15_15.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER15_15.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER15_15.VHD	(revision 20)
@@ -0,0 +1,2597 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler15_15 is
+    Port ( Request : in  STD_LOGIC_VECTOR (225 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (15 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (15 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (225 downto 1));
+end Scheduler15_15;
+
+architecture Behavioral of Scheduler15_15 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(29 downto 1) of STD_LOGIC_VECTOR(15 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (29 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(225 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(225 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 32767 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(16)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(17)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(18)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(19)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(20)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(21)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(22)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(23)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) or Signal_grant(24)(9); --  Grant(1,9)
+Grant(10)  <= Signal_grant(10)(10) or Signal_grant(25)(10); --  Grant(1,10)
+Grant(11)  <= Signal_grant(11)(11) or Signal_grant(26)(11); --  Grant(1,11)
+Grant(12)  <= Signal_grant(12)(12) or Signal_grant(27)(12); --  Grant(1,12)
+Grant(13)  <= Signal_grant(13)(13) or Signal_grant(28)(13); --  Grant(1,13)
+Grant(14)  <= Signal_grant(14)(14) or Signal_grant(29)(14); --  Grant(1,14)
+Grant(15)  <= Signal_grant(15)(15) ;                      --  Grant(1,15)
+Grant(16)  <= Signal_grant(2)(1) or Signal_grant(17)(1); --  Grant(2,1)
+Grant(17)  <= Signal_grant(3)(2) or Signal_grant(18)(2); --  Grant(2,2)
+Grant(18)  <= Signal_grant(4)(3) or Signal_grant(19)(3); --  Grant(2,3)
+Grant(19)  <= Signal_grant(5)(4) or Signal_grant(20)(4); --  Grant(2,4)
+Grant(20)  <= Signal_grant(6)(5) or Signal_grant(21)(5); --  Grant(2,5)
+Grant(21)  <= Signal_grant(7)(6) or Signal_grant(22)(6); --  Grant(2,6)
+Grant(22)  <= Signal_grant(8)(7) or Signal_grant(23)(7); --  Grant(2,7)
+Grant(23)  <= Signal_grant(9)(8) or Signal_grant(24)(8); --  Grant(2,8)
+Grant(24)  <= Signal_grant(10)(9) or Signal_grant(25)(9); --  Grant(2,9)
+Grant(25)  <= Signal_grant(11)(10) or Signal_grant(26)(10); --  Grant(2,10)
+Grant(26)  <= Signal_grant(12)(11) or Signal_grant(27)(11); --  Grant(2,11)
+Grant(27)  <= Signal_grant(13)(12) or Signal_grant(28)(12); --  Grant(2,12)
+Grant(28)  <= Signal_grant(14)(13) or Signal_grant(29)(13); --  Grant(2,13)
+Grant(29)  <= Signal_grant(15)(14) ;                      --  Grant(2,14)
+Grant(30)  <= Signal_grant(1)(15) or Signal_grant(16)(15); --  Grant(2,15)
+Grant(31)  <= Signal_grant(3)(1) or Signal_grant(18)(1); --  Grant(3,1)
+Grant(32)  <= Signal_grant(4)(2) or Signal_grant(19)(2); --  Grant(3,2)
+Grant(33)  <= Signal_grant(5)(3) or Signal_grant(20)(3); --  Grant(3,3)
+Grant(34)  <= Signal_grant(6)(4) or Signal_grant(21)(4); --  Grant(3,4)
+Grant(35)  <= Signal_grant(7)(5) or Signal_grant(22)(5); --  Grant(3,5)
+Grant(36)  <= Signal_grant(8)(6) or Signal_grant(23)(6); --  Grant(3,6)
+Grant(37)  <= Signal_grant(9)(7) or Signal_grant(24)(7); --  Grant(3,7)
+Grant(38)  <= Signal_grant(10)(8) or Signal_grant(25)(8); --  Grant(3,8)
+Grant(39)  <= Signal_grant(11)(9) or Signal_grant(26)(9); --  Grant(3,9)
+Grant(40)  <= Signal_grant(12)(10) or Signal_grant(27)(10); --  Grant(3,10)
+Grant(41)  <= Signal_grant(13)(11) or Signal_grant(28)(11); --  Grant(3,11)
+Grant(42)  <= Signal_grant(14)(12) or Signal_grant(29)(12); --  Grant(3,12)
+Grant(43)  <= Signal_grant(15)(13) ;                      --  Grant(3,13)
+Grant(44)  <= Signal_grant(1)(14) or Signal_grant(16)(14); --  Grant(3,14)
+Grant(45)  <= Signal_grant(2)(15) or Signal_grant(17)(15); --  Grant(3,15)
+Grant(46)  <= Signal_grant(4)(1) or Signal_grant(19)(1); --  Grant(4,1)
+Grant(47)  <= Signal_grant(5)(2) or Signal_grant(20)(2); --  Grant(4,2)
+Grant(48)  <= Signal_grant(6)(3) or Signal_grant(21)(3); --  Grant(4,3)
+Grant(49)  <= Signal_grant(7)(4) or Signal_grant(22)(4); --  Grant(4,4)
+Grant(50)  <= Signal_grant(8)(5) or Signal_grant(23)(5); --  Grant(4,5)
+Grant(51)  <= Signal_grant(9)(6) or Signal_grant(24)(6); --  Grant(4,6)
+Grant(52)  <= Signal_grant(10)(7) or Signal_grant(25)(7); --  Grant(4,7)
+Grant(53)  <= Signal_grant(11)(8) or Signal_grant(26)(8); --  Grant(4,8)
+Grant(54)  <= Signal_grant(12)(9) or Signal_grant(27)(9); --  Grant(4,9)
+Grant(55)  <= Signal_grant(13)(10) or Signal_grant(28)(10); --  Grant(4,10)
+Grant(56)  <= Signal_grant(14)(11) or Signal_grant(29)(11); --  Grant(4,11)
+Grant(57)  <= Signal_grant(15)(12) ;                      --  Grant(4,12)
+Grant(58)  <= Signal_grant(1)(13) or Signal_grant(16)(13); --  Grant(4,13)
+Grant(59)  <= Signal_grant(2)(14) or Signal_grant(17)(14); --  Grant(4,14)
+Grant(60)  <= Signal_grant(3)(15) or Signal_grant(18)(15); --  Grant(4,15)
+Grant(61)  <= Signal_grant(5)(1) or Signal_grant(20)(1); --  Grant(5,1)
+Grant(62)  <= Signal_grant(6)(2) or Signal_grant(21)(2); --  Grant(5,2)
+Grant(63)  <= Signal_grant(7)(3) or Signal_grant(22)(3); --  Grant(5,3)
+Grant(64)  <= Signal_grant(8)(4) or Signal_grant(23)(4); --  Grant(5,4)
+Grant(65)  <= Signal_grant(9)(5) or Signal_grant(24)(5); --  Grant(5,5)
+Grant(66)  <= Signal_grant(10)(6) or Signal_grant(25)(6); --  Grant(5,6)
+Grant(67)  <= Signal_grant(11)(7) or Signal_grant(26)(7); --  Grant(5,7)
+Grant(68)  <= Signal_grant(12)(8) or Signal_grant(27)(8); --  Grant(5,8)
+Grant(69)  <= Signal_grant(13)(9) or Signal_grant(28)(9); --  Grant(5,9)
+Grant(70)  <= Signal_grant(14)(10) or Signal_grant(29)(10); --  Grant(5,10)
+Grant(71)  <= Signal_grant(15)(11) ;                      --  Grant(5,11)
+Grant(72)  <= Signal_grant(1)(12) or Signal_grant(16)(12); --  Grant(5,12)
+Grant(73)  <= Signal_grant(2)(13) or Signal_grant(17)(13); --  Grant(5,13)
+Grant(74)  <= Signal_grant(3)(14) or Signal_grant(18)(14); --  Grant(5,14)
+Grant(75)  <= Signal_grant(4)(15) or Signal_grant(19)(15); --  Grant(5,15)
+Grant(76)  <= Signal_grant(6)(1) or Signal_grant(21)(1); --  Grant(6,1)
+Grant(77)  <= Signal_grant(7)(2) or Signal_grant(22)(2); --  Grant(6,2)
+Grant(78)  <= Signal_grant(8)(3) or Signal_grant(23)(3); --  Grant(6,3)
+Grant(79)  <= Signal_grant(9)(4) or Signal_grant(24)(4); --  Grant(6,4)
+Grant(80)  <= Signal_grant(10)(5) or Signal_grant(25)(5); --  Grant(6,5)
+Grant(81)  <= Signal_grant(11)(6) or Signal_grant(26)(6); --  Grant(6,6)
+Grant(82)  <= Signal_grant(12)(7) or Signal_grant(27)(7); --  Grant(6,7)
+Grant(83)  <= Signal_grant(13)(8) or Signal_grant(28)(8); --  Grant(6,8)
+Grant(84)  <= Signal_grant(14)(9) or Signal_grant(29)(9); --  Grant(6,9)
+Grant(85)  <= Signal_grant(15)(10) ;                      --  Grant(6,10)
+Grant(86)  <= Signal_grant(1)(11) or Signal_grant(16)(11); --  Grant(6,11)
+Grant(87)  <= Signal_grant(2)(12) or Signal_grant(17)(12); --  Grant(6,12)
+Grant(88)  <= Signal_grant(3)(13) or Signal_grant(18)(13); --  Grant(6,13)
+Grant(89)  <= Signal_grant(4)(14) or Signal_grant(19)(14); --  Grant(6,14)
+Grant(90)  <= Signal_grant(5)(15) or Signal_grant(20)(15); --  Grant(6,15)
+Grant(91)  <= Signal_grant(7)(1) or Signal_grant(22)(1); --  Grant(7,1)
+Grant(92)  <= Signal_grant(8)(2) or Signal_grant(23)(2); --  Grant(7,2)
+Grant(93)  <= Signal_grant(9)(3) or Signal_grant(24)(3); --  Grant(7,3)
+Grant(94)  <= Signal_grant(10)(4) or Signal_grant(25)(4); --  Grant(7,4)
+Grant(95)  <= Signal_grant(11)(5) or Signal_grant(26)(5); --  Grant(7,5)
+Grant(96)  <= Signal_grant(12)(6) or Signal_grant(27)(6); --  Grant(7,6)
+Grant(97)  <= Signal_grant(13)(7) or Signal_grant(28)(7); --  Grant(7,7)
+Grant(98)  <= Signal_grant(14)(8) or Signal_grant(29)(8); --  Grant(7,8)
+Grant(99)  <= Signal_grant(15)(9) ;                      --  Grant(7,9)
+Grant(100)  <= Signal_grant(1)(10) or Signal_grant(16)(10); --  Grant(7,10)
+Grant(101)  <= Signal_grant(2)(11) or Signal_grant(17)(11); --  Grant(7,11)
+Grant(102)  <= Signal_grant(3)(12) or Signal_grant(18)(12); --  Grant(7,12)
+Grant(103)  <= Signal_grant(4)(13) or Signal_grant(19)(13); --  Grant(7,13)
+Grant(104)  <= Signal_grant(5)(14) or Signal_grant(20)(14); --  Grant(7,14)
+Grant(105)  <= Signal_grant(6)(15) or Signal_grant(21)(15); --  Grant(7,15)
+Grant(106)  <= Signal_grant(8)(1) or Signal_grant(23)(1); --  Grant(8,1)
+Grant(107)  <= Signal_grant(9)(2) or Signal_grant(24)(2); --  Grant(8,2)
+Grant(108)  <= Signal_grant(10)(3) or Signal_grant(25)(3); --  Grant(8,3)
+Grant(109)  <= Signal_grant(11)(4) or Signal_grant(26)(4); --  Grant(8,4)
+Grant(110)  <= Signal_grant(12)(5) or Signal_grant(27)(5); --  Grant(8,5)
+Grant(111)  <= Signal_grant(13)(6) or Signal_grant(28)(6); --  Grant(8,6)
+Grant(112)  <= Signal_grant(14)(7) or Signal_grant(29)(7); --  Grant(8,7)
+Grant(113)  <= Signal_grant(15)(8) ;                      --  Grant(8,8)
+Grant(114)  <= Signal_grant(1)(9) or Signal_grant(16)(9); --  Grant(8,9)
+Grant(115)  <= Signal_grant(2)(10) or Signal_grant(17)(10); --  Grant(8,10)
+Grant(116)  <= Signal_grant(3)(11) or Signal_grant(18)(11); --  Grant(8,11)
+Grant(117)  <= Signal_grant(4)(12) or Signal_grant(19)(12); --  Grant(8,12)
+Grant(118)  <= Signal_grant(5)(13) or Signal_grant(20)(13); --  Grant(8,13)
+Grant(119)  <= Signal_grant(6)(14) or Signal_grant(21)(14); --  Grant(8,14)
+Grant(120)  <= Signal_grant(7)(15) or Signal_grant(22)(15); --  Grant(8,15)
+Grant(121)  <= Signal_grant(9)(1) or Signal_grant(24)(1); --  Grant(9,1)
+Grant(122)  <= Signal_grant(10)(2) or Signal_grant(25)(2); --  Grant(9,2)
+Grant(123)  <= Signal_grant(11)(3) or Signal_grant(26)(3); --  Grant(9,3)
+Grant(124)  <= Signal_grant(12)(4) or Signal_grant(27)(4); --  Grant(9,4)
+Grant(125)  <= Signal_grant(13)(5) or Signal_grant(28)(5); --  Grant(9,5)
+Grant(126)  <= Signal_grant(14)(6) or Signal_grant(29)(6); --  Grant(9,6)
+Grant(127)  <= Signal_grant(15)(7) ;                      --  Grant(9,7)
+Grant(128)  <= Signal_grant(1)(8) or Signal_grant(16)(8); --  Grant(9,8)
+Grant(129)  <= Signal_grant(2)(9) or Signal_grant(17)(9); --  Grant(9,9)
+Grant(130)  <= Signal_grant(3)(10) or Signal_grant(18)(10); --  Grant(9,10)
+Grant(131)  <= Signal_grant(4)(11) or Signal_grant(19)(11); --  Grant(9,11)
+Grant(132)  <= Signal_grant(5)(12) or Signal_grant(20)(12); --  Grant(9,12)
+Grant(133)  <= Signal_grant(6)(13) or Signal_grant(21)(13); --  Grant(9,13)
+Grant(134)  <= Signal_grant(7)(14) or Signal_grant(22)(14); --  Grant(9,14)
+Grant(135)  <= Signal_grant(8)(15) or Signal_grant(23)(15); --  Grant(9,15)
+Grant(136)  <= Signal_grant(10)(1) or Signal_grant(25)(1); --  Grant(10,1)
+Grant(137)  <= Signal_grant(11)(2) or Signal_grant(26)(2); --  Grant(10,2)
+Grant(138)  <= Signal_grant(12)(3) or Signal_grant(27)(3); --  Grant(10,3)
+Grant(139)  <= Signal_grant(13)(4) or Signal_grant(28)(4); --  Grant(10,4)
+Grant(140)  <= Signal_grant(14)(5) or Signal_grant(29)(5); --  Grant(10,5)
+Grant(141)  <= Signal_grant(15)(6) ;                      --  Grant(10,6)
+Grant(142)  <= Signal_grant(1)(7) or Signal_grant(16)(7); --  Grant(10,7)
+Grant(143)  <= Signal_grant(2)(8) or Signal_grant(17)(8); --  Grant(10,8)
+Grant(144)  <= Signal_grant(3)(9) or Signal_grant(18)(9); --  Grant(10,9)
+Grant(145)  <= Signal_grant(4)(10) or Signal_grant(19)(10); --  Grant(10,10)
+Grant(146)  <= Signal_grant(5)(11) or Signal_grant(20)(11); --  Grant(10,11)
+Grant(147)  <= Signal_grant(6)(12) or Signal_grant(21)(12); --  Grant(10,12)
+Grant(148)  <= Signal_grant(7)(13) or Signal_grant(22)(13); --  Grant(10,13)
+Grant(149)  <= Signal_grant(8)(14) or Signal_grant(23)(14); --  Grant(10,14)
+Grant(150)  <= Signal_grant(9)(15) or Signal_grant(24)(15); --  Grant(10,15)
+Grant(151)  <= Signal_grant(11)(1) or Signal_grant(26)(1); --  Grant(11,1)
+Grant(152)  <= Signal_grant(12)(2) or Signal_grant(27)(2); --  Grant(11,2)
+Grant(153)  <= Signal_grant(13)(3) or Signal_grant(28)(3); --  Grant(11,3)
+Grant(154)  <= Signal_grant(14)(4) or Signal_grant(29)(4); --  Grant(11,4)
+Grant(155)  <= Signal_grant(15)(5) ;                      --  Grant(11,5)
+Grant(156)  <= Signal_grant(1)(6) or Signal_grant(16)(6); --  Grant(11,6)
+Grant(157)  <= Signal_grant(2)(7) or Signal_grant(17)(7); --  Grant(11,7)
+Grant(158)  <= Signal_grant(3)(8) or Signal_grant(18)(8); --  Grant(11,8)
+Grant(159)  <= Signal_grant(4)(9) or Signal_grant(19)(9); --  Grant(11,9)
+Grant(160)  <= Signal_grant(5)(10) or Signal_grant(20)(10); --  Grant(11,10)
+Grant(161)  <= Signal_grant(6)(11) or Signal_grant(21)(11); --  Grant(11,11)
+Grant(162)  <= Signal_grant(7)(12) or Signal_grant(22)(12); --  Grant(11,12)
+Grant(163)  <= Signal_grant(8)(13) or Signal_grant(23)(13); --  Grant(11,13)
+Grant(164)  <= Signal_grant(9)(14) or Signal_grant(24)(14); --  Grant(11,14)
+Grant(165)  <= Signal_grant(10)(15) or Signal_grant(25)(15); --  Grant(11,15)
+Grant(166)  <= Signal_grant(12)(1) or Signal_grant(27)(1); --  Grant(12,1)
+Grant(167)  <= Signal_grant(13)(2) or Signal_grant(28)(2); --  Grant(12,2)
+Grant(168)  <= Signal_grant(14)(3) or Signal_grant(29)(3); --  Grant(12,3)
+Grant(169)  <= Signal_grant(15)(4) ;                      --  Grant(12,4)
+Grant(170)  <= Signal_grant(1)(5) or Signal_grant(16)(5); --  Grant(12,5)
+Grant(171)  <= Signal_grant(2)(6) or Signal_grant(17)(6); --  Grant(12,6)
+Grant(172)  <= Signal_grant(3)(7) or Signal_grant(18)(7); --  Grant(12,7)
+Grant(173)  <= Signal_grant(4)(8) or Signal_grant(19)(8); --  Grant(12,8)
+Grant(174)  <= Signal_grant(5)(9) or Signal_grant(20)(9); --  Grant(12,9)
+Grant(175)  <= Signal_grant(6)(10) or Signal_grant(21)(10); --  Grant(12,10)
+Grant(176)  <= Signal_grant(7)(11) or Signal_grant(22)(11); --  Grant(12,11)
+Grant(177)  <= Signal_grant(8)(12) or Signal_grant(23)(12); --  Grant(12,12)
+Grant(178)  <= Signal_grant(9)(13) or Signal_grant(24)(13); --  Grant(12,13)
+Grant(179)  <= Signal_grant(10)(14) or Signal_grant(25)(14); --  Grant(12,14)
+Grant(180)  <= Signal_grant(11)(15) or Signal_grant(26)(15); --  Grant(12,15)
+Grant(181)  <= Signal_grant(13)(1) or Signal_grant(28)(1); --  Grant(13,1)
+Grant(182)  <= Signal_grant(14)(2) or Signal_grant(29)(2); --  Grant(13,2)
+Grant(183)  <= Signal_grant(15)(3) ;                      --  Grant(13,3)
+Grant(184)  <= Signal_grant(1)(4) or Signal_grant(16)(4); --  Grant(13,4)
+Grant(185)  <= Signal_grant(2)(5) or Signal_grant(17)(5); --  Grant(13,5)
+Grant(186)  <= Signal_grant(3)(6) or Signal_grant(18)(6); --  Grant(13,6)
+Grant(187)  <= Signal_grant(4)(7) or Signal_grant(19)(7); --  Grant(13,7)
+Grant(188)  <= Signal_grant(5)(8) or Signal_grant(20)(8); --  Grant(13,8)
+Grant(189)  <= Signal_grant(6)(9) or Signal_grant(21)(9); --  Grant(13,9)
+Grant(190)  <= Signal_grant(7)(10) or Signal_grant(22)(10); --  Grant(13,10)
+Grant(191)  <= Signal_grant(8)(11) or Signal_grant(23)(11); --  Grant(13,11)
+Grant(192)  <= Signal_grant(9)(12) or Signal_grant(24)(12); --  Grant(13,12)
+Grant(193)  <= Signal_grant(10)(13) or Signal_grant(25)(13); --  Grant(13,13)
+Grant(194)  <= Signal_grant(11)(14) or Signal_grant(26)(14); --  Grant(13,14)
+Grant(195)  <= Signal_grant(12)(15) or Signal_grant(27)(15); --  Grant(13,15)
+Grant(196)  <= Signal_grant(14)(1) or Signal_grant(29)(1); --  Grant(14,1)
+Grant(197)  <= Signal_grant(15)(2) ;                      --  Grant(14,2)
+Grant(198)  <= Signal_grant(1)(3) or Signal_grant(16)(3); --  Grant(14,3)
+Grant(199)  <= Signal_grant(2)(4) or Signal_grant(17)(4); --  Grant(14,4)
+Grant(200)  <= Signal_grant(3)(5) or Signal_grant(18)(5); --  Grant(14,5)
+Grant(201)  <= Signal_grant(4)(6) or Signal_grant(19)(6); --  Grant(14,6)
+Grant(202)  <= Signal_grant(5)(7) or Signal_grant(20)(7); --  Grant(14,7)
+Grant(203)  <= Signal_grant(6)(8) or Signal_grant(21)(8); --  Grant(14,8)
+Grant(204)  <= Signal_grant(7)(9) or Signal_grant(22)(9); --  Grant(14,9)
+Grant(205)  <= Signal_grant(8)(10) or Signal_grant(23)(10); --  Grant(14,10)
+Grant(206)  <= Signal_grant(9)(11) or Signal_grant(24)(11); --  Grant(14,11)
+Grant(207)  <= Signal_grant(10)(12) or Signal_grant(25)(12); --  Grant(14,12)
+Grant(208)  <= Signal_grant(11)(13) or Signal_grant(26)(13); --  Grant(14,13)
+Grant(209)  <= Signal_grant(12)(14) or Signal_grant(27)(14); --  Grant(14,14)
+Grant(210)  <= Signal_grant(13)(15) or Signal_grant(28)(15); --  Grant(14,15)
+Grant(211)  <= Signal_grant(15)(1) ;                      --  Grant(15,1)
+Grant(212)  <= Signal_grant(1)(2) or Signal_grant(16)(2); --  Grant(15,2)
+Grant(213)  <= Signal_grant(2)(3) or Signal_grant(17)(3); --  Grant(15,3)
+Grant(214)  <= Signal_grant(3)(4) or Signal_grant(18)(4); --  Grant(15,4)
+Grant(215)  <= Signal_grant(4)(5) or Signal_grant(19)(5); --  Grant(15,5)
+Grant(216)  <= Signal_grant(5)(6) or Signal_grant(20)(6); --  Grant(15,6)
+Grant(217)  <= Signal_grant(6)(7) or Signal_grant(21)(7); --  Grant(15,7)
+Grant(218)  <= Signal_grant(7)(8) or Signal_grant(22)(8); --  Grant(15,8)
+Grant(219)  <= Signal_grant(8)(9) or Signal_grant(23)(9); --  Grant(15,9)
+Grant(220)  <= Signal_grant(9)(10) or Signal_grant(24)(10); --  Grant(15,10)
+Grant(221)  <= Signal_grant(10)(11) or Signal_grant(25)(11); --  Grant(15,11)
+Grant(222)  <= Signal_grant(11)(12) or Signal_grant(26)(12); --  Grant(15,12)
+Grant(223)  <= Signal_grant(12)(13) or Signal_grant(27)(13); --  Grant(15,13)
+Grant(224)  <= Signal_grant(13)(14) or Signal_grant(28)(14); --  Grant(15,14)
+Grant(225)  <= Signal_grant(14)(15) or Signal_grant(29)(15); --  Grant(15,15)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(212), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(198), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(184), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(170), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(156), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(142), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(128), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(114), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+Arbiter_1_10 : Arbiter
+
+PORT MAP (Request => Request(100), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(10),  
+South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); 
+
+Arbiter_1_11 : Arbiter
+
+PORT MAP (Request => Request(86), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(11),  
+South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); 
+
+Arbiter_1_12 : Arbiter
+
+PORT MAP (Request => Request(72), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(12),  
+South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); 
+
+Arbiter_1_13 : Arbiter
+
+PORT MAP (Request => Request(58), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(13),  
+South => south_2_north(1)(13), East => east_2_west(1)(13) , Grant => Signal_grant(1)(13)); 
+
+Arbiter_1_14 : Arbiter
+
+PORT MAP (Request => Request(44), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(14),  
+South => south_2_north(1)(14), East => east_2_west(1)(14) , Grant => Signal_grant(1)(14)); 
+
+Arbiter_1_15 : Arbiter
+
+PORT MAP (Request => Request(30), North => High, West => High, P => Signal_priority(29), Fifo_full => Fifo_full(15),  
+South => south_2_north(1)(15), East => east_2_west(1)(15) , Grant => Signal_grant(1)(15)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(1)(1), West => east_2_west(1)(15), P => Signal_priority(28), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(28), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(213), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(28), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(199), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(28), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(185), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(28), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(171), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(28), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(157), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(28), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(28), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(28), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+Arbiter_2_10 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(28), Fifo_full => Fifo_full(10),  
+South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); 
+
+Arbiter_2_11 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(28), Fifo_full => Fifo_full(11),  
+South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); 
+
+Arbiter_2_12 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(28), Fifo_full => Fifo_full(12),  
+South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); 
+
+Arbiter_2_13 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(1)(13), West => east_2_west(1)(12), P => Signal_priority(28), Fifo_full => Fifo_full(13),  
+South => south_2_north(2)(13), East => east_2_west(2)(13) , Grant => Signal_grant(2)(13)); 
+
+Arbiter_2_14 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(1)(14), West => east_2_west(1)(13), P => Signal_priority(28), Fifo_full => Fifo_full(14),  
+South => south_2_north(2)(14), East => east_2_west(2)(14) , Grant => Signal_grant(2)(14)); 
+
+Arbiter_2_15 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(1)(15), West => east_2_west(1)(14), P => Signal_priority(28), Fifo_full => Fifo_full(15),  
+South => south_2_north(2)(15), East => east_2_west(2)(15) , Grant => Signal_grant(2)(15)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(2)(1), West => east_2_west(2)(15), P => Signal_priority(27), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(27), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(27), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(214), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(27), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(200), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(27), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(186), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(27), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(172), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(27), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(158), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(27), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(27), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+Arbiter_3_10 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(27), Fifo_full => Fifo_full(10),  
+South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); 
+
+Arbiter_3_11 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(27), Fifo_full => Fifo_full(11),  
+South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); 
+
+Arbiter_3_12 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(27), Fifo_full => Fifo_full(12),  
+South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); 
+
+Arbiter_3_13 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(2)(13), West => east_2_west(2)(12), P => Signal_priority(27), Fifo_full => Fifo_full(13),  
+South => south_2_north(3)(13), East => east_2_west(3)(13) , Grant => Signal_grant(3)(13)); 
+
+Arbiter_3_14 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(2)(14), West => east_2_west(2)(13), P => Signal_priority(27), Fifo_full => Fifo_full(14),  
+South => south_2_north(3)(14), East => east_2_west(3)(14) , Grant => Signal_grant(3)(14)); 
+
+Arbiter_3_15 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(2)(15), West => east_2_west(2)(14), P => Signal_priority(27), Fifo_full => Fifo_full(15),  
+South => south_2_north(3)(15), East => east_2_west(3)(15) , Grant => Signal_grant(3)(15)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(3)(1), West => east_2_west(3)(15), P => Signal_priority(26), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(26), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(26), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(26), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(215), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(26), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(201), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(26), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(187), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(26), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(173), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(26), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(26), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+Arbiter_4_10 : Arbiter
+
+PORT MAP (Request => Request(145), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(26), Fifo_full => Fifo_full(10),  
+South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); 
+
+Arbiter_4_11 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(26), Fifo_full => Fifo_full(11),  
+South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); 
+
+Arbiter_4_12 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(26), Fifo_full => Fifo_full(12),  
+South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); 
+
+Arbiter_4_13 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(3)(13), West => east_2_west(3)(12), P => Signal_priority(26), Fifo_full => Fifo_full(13),  
+South => south_2_north(4)(13), East => east_2_west(4)(13) , Grant => Signal_grant(4)(13)); 
+
+Arbiter_4_14 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(3)(14), West => east_2_west(3)(13), P => Signal_priority(26), Fifo_full => Fifo_full(14),  
+South => south_2_north(4)(14), East => east_2_west(4)(14) , Grant => Signal_grant(4)(14)); 
+
+Arbiter_4_15 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(3)(15), West => east_2_west(3)(14), P => Signal_priority(26), Fifo_full => Fifo_full(15),  
+South => south_2_north(4)(15), East => east_2_west(4)(15) , Grant => Signal_grant(4)(15)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(4)(1), West => east_2_west(4)(15), P => Signal_priority(25), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(25), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(25), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(25), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(25), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(216), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(25), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(202), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(25), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(188), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(25), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(174), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(25), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+Arbiter_5_10 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(25), Fifo_full => Fifo_full(10),  
+South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); 
+
+Arbiter_5_11 : Arbiter
+
+PORT MAP (Request => Request(146), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(25), Fifo_full => Fifo_full(11),  
+South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); 
+
+Arbiter_5_12 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(25), Fifo_full => Fifo_full(12),  
+South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); 
+
+Arbiter_5_13 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(4)(13), West => east_2_west(4)(12), P => Signal_priority(25), Fifo_full => Fifo_full(13),  
+South => south_2_north(5)(13), East => east_2_west(5)(13) , Grant => Signal_grant(5)(13)); 
+
+Arbiter_5_14 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(4)(14), West => east_2_west(4)(13), P => Signal_priority(25), Fifo_full => Fifo_full(14),  
+South => south_2_north(5)(14), East => east_2_west(5)(14) , Grant => Signal_grant(5)(14)); 
+
+Arbiter_5_15 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(4)(15), West => east_2_west(4)(14), P => Signal_priority(25), Fifo_full => Fifo_full(15),  
+South => south_2_north(5)(15), East => east_2_west(5)(15) , Grant => Signal_grant(5)(15)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(5)(1), West => east_2_west(5)(15), P => Signal_priority(24), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(24), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(24), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(24), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(24), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(24), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(217), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(24), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(203), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(24), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(189), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(24), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+Arbiter_6_10 : Arbiter
+
+PORT MAP (Request => Request(175), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(24), Fifo_full => Fifo_full(10),  
+South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); 
+
+Arbiter_6_11 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(24), Fifo_full => Fifo_full(11),  
+South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); 
+
+Arbiter_6_12 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(24), Fifo_full => Fifo_full(12),  
+South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); 
+
+Arbiter_6_13 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(5)(13), West => east_2_west(5)(12), P => Signal_priority(24), Fifo_full => Fifo_full(13),  
+South => south_2_north(6)(13), East => east_2_west(6)(13) , Grant => Signal_grant(6)(13)); 
+
+Arbiter_6_14 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(5)(14), West => east_2_west(5)(13), P => Signal_priority(24), Fifo_full => Fifo_full(14),  
+South => south_2_north(6)(14), East => east_2_west(6)(14) , Grant => Signal_grant(6)(14)); 
+
+Arbiter_6_15 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(5)(15), West => east_2_west(5)(14), P => Signal_priority(24), Fifo_full => Fifo_full(15),  
+South => south_2_north(6)(15), East => east_2_west(6)(15) , Grant => Signal_grant(6)(15)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(6)(1), West => east_2_west(6)(15), P => Signal_priority(23), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(23), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(23), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(23), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(23), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(23), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(23), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(218), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(23), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(204), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(23), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+Arbiter_7_10 : Arbiter
+
+PORT MAP (Request => Request(190), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(23), Fifo_full => Fifo_full(10),  
+South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); 
+
+Arbiter_7_11 : Arbiter
+
+PORT MAP (Request => Request(176), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(23), Fifo_full => Fifo_full(11),  
+South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); 
+
+Arbiter_7_12 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(23), Fifo_full => Fifo_full(12),  
+South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); 
+
+Arbiter_7_13 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(6)(13), West => east_2_west(6)(12), P => Signal_priority(23), Fifo_full => Fifo_full(13),  
+South => south_2_north(7)(13), East => east_2_west(7)(13) , Grant => Signal_grant(7)(13)); 
+
+Arbiter_7_14 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(6)(14), West => east_2_west(6)(13), P => Signal_priority(23), Fifo_full => Fifo_full(14),  
+South => south_2_north(7)(14), East => east_2_west(7)(14) , Grant => Signal_grant(7)(14)); 
+
+Arbiter_7_15 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(6)(15), West => east_2_west(6)(14), P => Signal_priority(23), Fifo_full => Fifo_full(15),  
+South => south_2_north(7)(15), East => east_2_west(7)(15) , Grant => Signal_grant(7)(15)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(7)(1), West => east_2_west(7)(15), P => Signal_priority(22), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(219), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+Arbiter_8_10 : Arbiter
+
+PORT MAP (Request => Request(205), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10),  
+South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); 
+
+Arbiter_8_11 : Arbiter
+
+PORT MAP (Request => Request(191), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11),  
+South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); 
+
+Arbiter_8_12 : Arbiter
+
+PORT MAP (Request => Request(177), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12),  
+South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); 
+
+Arbiter_8_13 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(7)(13), West => east_2_west(7)(12), P => Signal_priority(22), Fifo_full => Fifo_full(13),  
+South => south_2_north(8)(13), East => east_2_west(8)(13) , Grant => Signal_grant(8)(13)); 
+
+Arbiter_8_14 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(7)(14), West => east_2_west(7)(13), P => Signal_priority(22), Fifo_full => Fifo_full(14),  
+South => south_2_north(8)(14), East => east_2_west(8)(14) , Grant => Signal_grant(8)(14)); 
+
+Arbiter_8_15 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(7)(15), West => east_2_west(7)(14), P => Signal_priority(22), Fifo_full => Fifo_full(15),  
+South => south_2_north(8)(15), East => east_2_west(8)(15) , Grant => Signal_grant(8)(15)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(8)(1), West => east_2_west(8)(15), P => Signal_priority(21), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+Arbiter_9_10 : Arbiter
+
+PORT MAP (Request => Request(220), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10),  
+South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); 
+
+Arbiter_9_11 : Arbiter
+
+PORT MAP (Request => Request(206), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11),  
+South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); 
+
+Arbiter_9_12 : Arbiter
+
+PORT MAP (Request => Request(192), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12),  
+South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); 
+
+Arbiter_9_13 : Arbiter
+
+PORT MAP (Request => Request(178), North => south_2_north(8)(13), West => east_2_west(8)(12), P => Signal_priority(21), Fifo_full => Fifo_full(13),  
+South => south_2_north(9)(13), East => east_2_west(9)(13) , Grant => Signal_grant(9)(13)); 
+
+Arbiter_9_14 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(8)(14), West => east_2_west(8)(13), P => Signal_priority(21), Fifo_full => Fifo_full(14),  
+South => south_2_north(9)(14), East => east_2_west(9)(14) , Grant => Signal_grant(9)(14)); 
+
+Arbiter_9_15 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(8)(15), West => east_2_west(8)(14), P => Signal_priority(21), Fifo_full => Fifo_full(15),  
+South => south_2_north(9)(15), East => east_2_west(9)(15) , Grant => Signal_grant(9)(15)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(9)(1), West => east_2_west(9)(15), P => Signal_priority(20), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(122), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+Arbiter_10_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10),  
+South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); 
+
+Arbiter_10_11 : Arbiter
+
+PORT MAP (Request => Request(221), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11),  
+South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); 
+
+Arbiter_10_12 : Arbiter
+
+PORT MAP (Request => Request(207), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12),  
+South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); 
+
+Arbiter_10_13 : Arbiter
+
+PORT MAP (Request => Request(193), North => south_2_north(9)(13), West => east_2_west(9)(12), P => Signal_priority(20), Fifo_full => Fifo_full(13),  
+South => south_2_north(10)(13), East => east_2_west(10)(13) , Grant => Signal_grant(10)(13)); 
+
+Arbiter_10_14 : Arbiter
+
+PORT MAP (Request => Request(179), North => south_2_north(9)(14), West => east_2_west(9)(13), P => Signal_priority(20), Fifo_full => Fifo_full(14),  
+South => south_2_north(10)(14), East => east_2_west(10)(14) , Grant => Signal_grant(10)(14)); 
+
+Arbiter_10_15 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(9)(15), West => east_2_west(9)(14), P => Signal_priority(20), Fifo_full => Fifo_full(15),  
+South => south_2_north(10)(15), East => east_2_west(10)(15) , Grant => Signal_grant(10)(15)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(151), North => south_2_north(10)(1), West => east_2_west(10)(15), P => Signal_priority(19), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+Arbiter_11_10 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10),  
+South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); 
+
+Arbiter_11_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11),  
+South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); 
+
+Arbiter_11_12 : Arbiter
+
+PORT MAP (Request => Request(222), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12),  
+South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); 
+
+Arbiter_11_13 : Arbiter
+
+PORT MAP (Request => Request(208), North => south_2_north(10)(13), West => east_2_west(10)(12), P => Signal_priority(19), Fifo_full => Fifo_full(13),  
+South => south_2_north(11)(13), East => east_2_west(11)(13) , Grant => Signal_grant(11)(13)); 
+
+Arbiter_11_14 : Arbiter
+
+PORT MAP (Request => Request(194), North => south_2_north(10)(14), West => east_2_west(10)(13), P => Signal_priority(19), Fifo_full => Fifo_full(14),  
+South => south_2_north(11)(14), East => east_2_west(11)(14) , Grant => Signal_grant(11)(14)); 
+
+Arbiter_11_15 : Arbiter
+
+PORT MAP (Request => Request(180), North => south_2_north(10)(15), West => east_2_west(10)(14), P => Signal_priority(19), Fifo_full => Fifo_full(15),  
+South => south_2_north(11)(15), East => east_2_west(11)(15) , Grant => Signal_grant(11)(15)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(166), North => south_2_north(11)(1), West => east_2_west(11)(15), P => Signal_priority(18), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(152), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+Arbiter_12_10 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10),  
+South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); 
+
+Arbiter_12_11 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11),  
+South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); 
+
+Arbiter_12_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12),  
+South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); 
+
+Arbiter_12_13 : Arbiter
+
+PORT MAP (Request => Request(223), North => south_2_north(11)(13), West => east_2_west(11)(12), P => Signal_priority(18), Fifo_full => Fifo_full(13),  
+South => south_2_north(12)(13), East => east_2_west(12)(13) , Grant => Signal_grant(12)(13)); 
+
+Arbiter_12_14 : Arbiter
+
+PORT MAP (Request => Request(209), North => south_2_north(11)(14), West => east_2_west(11)(13), P => Signal_priority(18), Fifo_full => Fifo_full(14),  
+South => south_2_north(12)(14), East => east_2_west(12)(14) , Grant => Signal_grant(12)(14)); 
+
+Arbiter_12_15 : Arbiter
+
+PORT MAP (Request => Request(195), North => south_2_north(11)(15), West => east_2_west(11)(14), P => Signal_priority(18), Fifo_full => Fifo_full(15),  
+South => south_2_north(12)(15), East => east_2_west(12)(15) , Grant => Signal_grant(12)(15)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(181), North => south_2_north(12)(1), West => east_2_west(12)(15), P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(167), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+Arbiter_13_10 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10),  
+South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); 
+
+Arbiter_13_11 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11),  
+South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); 
+
+Arbiter_13_12 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12),  
+South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); 
+
+Arbiter_13_13 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(12)(13), West => east_2_west(12)(12), P => Signal_priority(17), Fifo_full => Fifo_full(13),  
+South => south_2_north(13)(13), East => east_2_west(13)(13) , Grant => Signal_grant(13)(13)); 
+
+Arbiter_13_14 : Arbiter
+
+PORT MAP (Request => Request(224), North => south_2_north(12)(14), West => east_2_west(12)(13), P => Signal_priority(17), Fifo_full => Fifo_full(14),  
+South => south_2_north(13)(14), East => east_2_west(13)(14) , Grant => Signal_grant(13)(14)); 
+
+Arbiter_13_15 : Arbiter
+
+PORT MAP (Request => Request(210), North => south_2_north(12)(15), West => east_2_west(12)(14), P => Signal_priority(17), Fifo_full => Fifo_full(15),  
+South => south_2_north(13)(15), East => east_2_west(13)(15) , Grant => Signal_grant(13)(15)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(196), North => south_2_north(13)(1), West => east_2_west(13)(15), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(182), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+Arbiter_14_10 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10),  
+South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); 
+
+Arbiter_14_11 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11),  
+South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); 
+
+Arbiter_14_12 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12),  
+South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); 
+
+Arbiter_14_13 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(13)(13), West => east_2_west(13)(12), P => Signal_priority(16), Fifo_full => Fifo_full(13),  
+South => south_2_north(14)(13), East => east_2_west(14)(13) , Grant => Signal_grant(14)(13)); 
+
+Arbiter_14_14 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(13)(14), West => east_2_west(13)(13), P => Signal_priority(16), Fifo_full => Fifo_full(14),  
+South => south_2_north(14)(14), East => east_2_west(14)(14) , Grant => Signal_grant(14)(14)); 
+
+Arbiter_14_15 : Arbiter
+
+PORT MAP (Request => Request(225), North => south_2_north(13)(15), West => east_2_west(13)(14), P => Signal_priority(16), Fifo_full => Fifo_full(15),  
+South => south_2_north(14)(15), East => east_2_west(14)(15) , Grant => Signal_grant(14)(15)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(211), North => south_2_north(14)(1), West => east_2_west(14)(15), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(197), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(183), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(169), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(155), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+Arbiter_15_10 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10),  
+South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); 
+
+Arbiter_15_11 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11),  
+South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); 
+
+Arbiter_15_12 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12),  
+South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); 
+
+Arbiter_15_13 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(14)(13), West => east_2_west(14)(12), P => Signal_priority(15), Fifo_full => Fifo_full(13),  
+South => south_2_north(15)(13), East => east_2_west(15)(13) , Grant => Signal_grant(15)(13)); 
+
+Arbiter_15_14 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(14)(14), West => east_2_west(14)(13), P => Signal_priority(15), Fifo_full => Fifo_full(14),  
+South => south_2_north(15)(14), East => east_2_west(15)(14) , Grant => Signal_grant(15)(14)); 
+
+Arbiter_15_15 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(14)(15), West => east_2_west(14)(14), P => Signal_priority(15), Fifo_full => Fifo_full(15),  
+South => south_2_north(15)(15), East => east_2_west(15)(15) , Grant => Signal_grant(15)(15)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(15)(1), West => east_2_west(15)(15), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(212), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(198), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(184), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(170), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(156), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+Arbiter_16_10 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10),  
+South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); 
+
+Arbiter_16_11 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11),  
+South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); 
+
+Arbiter_16_12 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12),  
+South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); 
+
+Arbiter_16_13 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(15)(13), West => east_2_west(15)(12), P => Signal_priority(14), Fifo_full => Fifo_full(13),  
+South => south_2_north(16)(13), East => east_2_west(16)(13) , Grant => Signal_grant(16)(13)); 
+
+Arbiter_16_14 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(15)(14), West => east_2_west(15)(13), P => Signal_priority(14), Fifo_full => Fifo_full(14),  
+South => south_2_north(16)(14), East => east_2_west(16)(14) , Grant => Signal_grant(16)(14)); 
+
+Arbiter_16_15 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(15)(15), West => east_2_west(15)(14), P => Signal_priority(14), Fifo_full => Fifo_full(15),  
+South => south_2_north(16)(15), East => east_2_west(16)(15) , Grant => Signal_grant(16)(15)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(16)(1), West => east_2_west(16)(15), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(213), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(199), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(185), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(171), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(157), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+Arbiter_17_10 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10),  
+South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); 
+
+Arbiter_17_11 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11),  
+South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); 
+
+Arbiter_17_12 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12),  
+South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); 
+
+Arbiter_17_13 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(16)(13), West => east_2_west(16)(12), P => Signal_priority(13), Fifo_full => Fifo_full(13),  
+South => south_2_north(17)(13), East => east_2_west(17)(13) , Grant => Signal_grant(17)(13)); 
+
+Arbiter_17_14 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(16)(14), West => east_2_west(16)(13), P => Signal_priority(13), Fifo_full => Fifo_full(14),  
+South => south_2_north(17)(14), East => east_2_west(17)(14) , Grant => Signal_grant(17)(14)); 
+
+Arbiter_17_15 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(16)(15), West => east_2_west(16)(14), P => Signal_priority(13), Fifo_full => Fifo_full(15),  
+South => south_2_north(17)(15), East => east_2_west(17)(15) , Grant => Signal_grant(17)(15)); 
+
+-------------------------- Diagonale n° 18 
+
+
+Arbiter_18_1 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(17)(1), West => east_2_west(17)(15), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); 
+
+Arbiter_18_2 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); 
+
+Arbiter_18_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); 
+
+Arbiter_18_4 : Arbiter
+
+PORT MAP (Request => Request(214), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); 
+
+Arbiter_18_5 : Arbiter
+
+PORT MAP (Request => Request(200), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); 
+
+Arbiter_18_6 : Arbiter
+
+PORT MAP (Request => Request(186), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); 
+
+Arbiter_18_7 : Arbiter
+
+PORT MAP (Request => Request(172), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); 
+
+Arbiter_18_8 : Arbiter
+
+PORT MAP (Request => Request(158), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); 
+
+Arbiter_18_9 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); 
+
+Arbiter_18_10 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10),  
+South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); 
+
+Arbiter_18_11 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11),  
+South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); 
+
+Arbiter_18_12 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12),  
+South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); 
+
+Arbiter_18_13 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(17)(13), West => east_2_west(17)(12), P => Signal_priority(12), Fifo_full => Fifo_full(13),  
+South => south_2_north(18)(13), East => east_2_west(18)(13) , Grant => Signal_grant(18)(13)); 
+
+Arbiter_18_14 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(17)(14), West => east_2_west(17)(13), P => Signal_priority(12), Fifo_full => Fifo_full(14),  
+South => south_2_north(18)(14), East => east_2_west(18)(14) , Grant => Signal_grant(18)(14)); 
+
+Arbiter_18_15 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(17)(15), West => east_2_west(17)(14), P => Signal_priority(12), Fifo_full => Fifo_full(15),  
+South => south_2_north(18)(15), East => east_2_west(18)(15) , Grant => Signal_grant(18)(15)); 
+
+-------------------------- Diagonale n° 19 
+
+
+Arbiter_19_1 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(18)(1), West => east_2_west(18)(15), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); 
+
+Arbiter_19_2 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); 
+
+Arbiter_19_3 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); 
+
+Arbiter_19_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); 
+
+Arbiter_19_5 : Arbiter
+
+PORT MAP (Request => Request(215), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); 
+
+Arbiter_19_6 : Arbiter
+
+PORT MAP (Request => Request(201), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); 
+
+Arbiter_19_7 : Arbiter
+
+PORT MAP (Request => Request(187), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); 
+
+Arbiter_19_8 : Arbiter
+
+PORT MAP (Request => Request(173), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); 
+
+Arbiter_19_9 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); 
+
+Arbiter_19_10 : Arbiter
+
+PORT MAP (Request => Request(145), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10),  
+South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); 
+
+Arbiter_19_11 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11),  
+South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); 
+
+Arbiter_19_12 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12),  
+South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); 
+
+Arbiter_19_13 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(18)(13), West => east_2_west(18)(12), P => Signal_priority(11), Fifo_full => Fifo_full(13),  
+South => south_2_north(19)(13), East => east_2_west(19)(13) , Grant => Signal_grant(19)(13)); 
+
+Arbiter_19_14 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(18)(14), West => east_2_west(18)(13), P => Signal_priority(11), Fifo_full => Fifo_full(14),  
+South => south_2_north(19)(14), East => east_2_west(19)(14) , Grant => Signal_grant(19)(14)); 
+
+Arbiter_19_15 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(18)(15), West => east_2_west(18)(14), P => Signal_priority(11), Fifo_full => Fifo_full(15),  
+South => south_2_north(19)(15), East => east_2_west(19)(15) , Grant => Signal_grant(19)(15)); 
+
+-------------------------- Diagonale n° 20 
+
+
+Arbiter_20_1 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(19)(1), West => east_2_west(19)(15), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); 
+
+Arbiter_20_2 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); 
+
+Arbiter_20_3 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); 
+
+Arbiter_20_4 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); 
+
+Arbiter_20_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); 
+
+Arbiter_20_6 : Arbiter
+
+PORT MAP (Request => Request(216), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); 
+
+Arbiter_20_7 : Arbiter
+
+PORT MAP (Request => Request(202), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); 
+
+Arbiter_20_8 : Arbiter
+
+PORT MAP (Request => Request(188), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); 
+
+Arbiter_20_9 : Arbiter
+
+PORT MAP (Request => Request(174), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); 
+
+Arbiter_20_10 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10),  
+South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); 
+
+Arbiter_20_11 : Arbiter
+
+PORT MAP (Request => Request(146), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11),  
+South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); 
+
+Arbiter_20_12 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12),  
+South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); 
+
+Arbiter_20_13 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(19)(13), West => east_2_west(19)(12), P => Signal_priority(10), Fifo_full => Fifo_full(13),  
+South => south_2_north(20)(13), East => east_2_west(20)(13) , Grant => Signal_grant(20)(13)); 
+
+Arbiter_20_14 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(19)(14), West => east_2_west(19)(13), P => Signal_priority(10), Fifo_full => Fifo_full(14),  
+South => south_2_north(20)(14), East => east_2_west(20)(14) , Grant => Signal_grant(20)(14)); 
+
+Arbiter_20_15 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(19)(15), West => east_2_west(19)(14), P => Signal_priority(10), Fifo_full => Fifo_full(15),  
+South => south_2_north(20)(15), East => east_2_west(20)(15) , Grant => Signal_grant(20)(15)); 
+
+-------------------------- Diagonale n° 21 
+
+
+Arbiter_21_1 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(20)(1), West => east_2_west(20)(15), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); 
+
+Arbiter_21_2 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); 
+
+Arbiter_21_3 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); 
+
+Arbiter_21_4 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); 
+
+Arbiter_21_5 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); 
+
+Arbiter_21_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); 
+
+Arbiter_21_7 : Arbiter
+
+PORT MAP (Request => Request(217), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); 
+
+Arbiter_21_8 : Arbiter
+
+PORT MAP (Request => Request(203), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); 
+
+Arbiter_21_9 : Arbiter
+
+PORT MAP (Request => Request(189), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); 
+
+Arbiter_21_10 : Arbiter
+
+PORT MAP (Request => Request(175), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10),  
+South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); 
+
+Arbiter_21_11 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11),  
+South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); 
+
+Arbiter_21_12 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12),  
+South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); 
+
+Arbiter_21_13 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(20)(13), West => east_2_west(20)(12), P => Signal_priority(9), Fifo_full => Fifo_full(13),  
+South => south_2_north(21)(13), East => east_2_west(21)(13) , Grant => Signal_grant(21)(13)); 
+
+Arbiter_21_14 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(20)(14), West => east_2_west(20)(13), P => Signal_priority(9), Fifo_full => Fifo_full(14),  
+South => south_2_north(21)(14), East => east_2_west(21)(14) , Grant => Signal_grant(21)(14)); 
+
+Arbiter_21_15 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(20)(15), West => east_2_west(20)(14), P => Signal_priority(9), Fifo_full => Fifo_full(15),  
+South => south_2_north(21)(15), East => east_2_west(21)(15) , Grant => Signal_grant(21)(15)); 
+
+-------------------------- Diagonale n° 22 
+
+
+Arbiter_22_1 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(21)(1), West => east_2_west(21)(15), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); 
+
+Arbiter_22_2 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); 
+
+Arbiter_22_3 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); 
+
+Arbiter_22_4 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); 
+
+Arbiter_22_5 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); 
+
+Arbiter_22_6 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); 
+
+Arbiter_22_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); 
+
+Arbiter_22_8 : Arbiter
+
+PORT MAP (Request => Request(218), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); 
+
+Arbiter_22_9 : Arbiter
+
+PORT MAP (Request => Request(204), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); 
+
+Arbiter_22_10 : Arbiter
+
+PORT MAP (Request => Request(190), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10),  
+South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); 
+
+Arbiter_22_11 : Arbiter
+
+PORT MAP (Request => Request(176), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11),  
+South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); 
+
+Arbiter_22_12 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12),  
+South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); 
+
+Arbiter_22_13 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(21)(13), West => east_2_west(21)(12), P => Signal_priority(8), Fifo_full => Fifo_full(13),  
+South => south_2_north(22)(13), East => east_2_west(22)(13) , Grant => Signal_grant(22)(13)); 
+
+Arbiter_22_14 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(21)(14), West => east_2_west(21)(13), P => Signal_priority(8), Fifo_full => Fifo_full(14),  
+South => south_2_north(22)(14), East => east_2_west(22)(14) , Grant => Signal_grant(22)(14)); 
+
+Arbiter_22_15 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(21)(15), West => east_2_west(21)(14), P => Signal_priority(8), Fifo_full => Fifo_full(15),  
+South => south_2_north(22)(15), East => east_2_west(22)(15) , Grant => Signal_grant(22)(15)); 
+
+-------------------------- Diagonale n° 23 
+
+
+Arbiter_23_1 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(22)(1), West => east_2_west(22)(15), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); 
+
+Arbiter_23_2 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); 
+
+Arbiter_23_3 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); 
+
+Arbiter_23_4 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); 
+
+Arbiter_23_5 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); 
+
+Arbiter_23_6 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); 
+
+Arbiter_23_7 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); 
+
+Arbiter_23_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); 
+
+Arbiter_23_9 : Arbiter
+
+PORT MAP (Request => Request(219), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); 
+
+Arbiter_23_10 : Arbiter
+
+PORT MAP (Request => Request(205), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10),  
+South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); 
+
+Arbiter_23_11 : Arbiter
+
+PORT MAP (Request => Request(191), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11),  
+South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); 
+
+Arbiter_23_12 : Arbiter
+
+PORT MAP (Request => Request(177), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12),  
+South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); 
+
+Arbiter_23_13 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(22)(13), West => east_2_west(22)(12), P => Signal_priority(7), Fifo_full => Fifo_full(13),  
+South => south_2_north(23)(13), East => east_2_west(23)(13) , Grant => Signal_grant(23)(13)); 
+
+Arbiter_23_14 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(22)(14), West => east_2_west(22)(13), P => Signal_priority(7), Fifo_full => Fifo_full(14),  
+South => south_2_north(23)(14), East => east_2_west(23)(14) , Grant => Signal_grant(23)(14)); 
+
+Arbiter_23_15 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(22)(15), West => east_2_west(22)(14), P => Signal_priority(7), Fifo_full => Fifo_full(15),  
+South => south_2_north(23)(15), East => east_2_west(23)(15) , Grant => Signal_grant(23)(15)); 
+
+-------------------------- Diagonale n° 24 
+
+
+Arbiter_24_1 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(23)(1), West => east_2_west(23)(15), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(24)(1), East => east_2_west(24)(1) , Grant => Signal_grant(24)(1)); 
+
+Arbiter_24_2 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(23)(2), West => east_2_west(23)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(24)(2), East => east_2_west(24)(2) , Grant => Signal_grant(24)(2)); 
+
+Arbiter_24_3 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(23)(3), West => east_2_west(23)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(24)(3), East => east_2_west(24)(3) , Grant => Signal_grant(24)(3)); 
+
+Arbiter_24_4 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(23)(4), West => east_2_west(23)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(24)(4), East => east_2_west(24)(4) , Grant => Signal_grant(24)(4)); 
+
+Arbiter_24_5 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(23)(5), West => east_2_west(23)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(24)(5), East => east_2_west(24)(5) , Grant => Signal_grant(24)(5)); 
+
+Arbiter_24_6 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(23)(6), West => east_2_west(23)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(24)(6), East => east_2_west(24)(6) , Grant => Signal_grant(24)(6)); 
+
+Arbiter_24_7 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(23)(7), West => east_2_west(23)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(24)(7), East => east_2_west(24)(7) , Grant => Signal_grant(24)(7)); 
+
+Arbiter_24_8 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(23)(8), West => east_2_west(23)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(24)(8), East => east_2_west(24)(8) , Grant => Signal_grant(24)(8)); 
+
+Arbiter_24_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(23)(9), West => east_2_west(23)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(24)(9), East => east_2_west(24)(9) , Grant => Signal_grant(24)(9)); 
+
+Arbiter_24_10 : Arbiter
+
+PORT MAP (Request => Request(220), North => south_2_north(23)(10), West => east_2_west(23)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10),  
+South => south_2_north(24)(10), East => east_2_west(24)(10) , Grant => Signal_grant(24)(10)); 
+
+Arbiter_24_11 : Arbiter
+
+PORT MAP (Request => Request(206), North => south_2_north(23)(11), West => east_2_west(23)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11),  
+South => south_2_north(24)(11), East => east_2_west(24)(11) , Grant => Signal_grant(24)(11)); 
+
+Arbiter_24_12 : Arbiter
+
+PORT MAP (Request => Request(192), North => south_2_north(23)(12), West => east_2_west(23)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12),  
+South => south_2_north(24)(12), East => east_2_west(24)(12) , Grant => Signal_grant(24)(12)); 
+
+Arbiter_24_13 : Arbiter
+
+PORT MAP (Request => Request(178), North => south_2_north(23)(13), West => east_2_west(23)(12), P => Signal_priority(6), Fifo_full => Fifo_full(13),  
+South => south_2_north(24)(13), East => east_2_west(24)(13) , Grant => Signal_grant(24)(13)); 
+
+Arbiter_24_14 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(23)(14), West => east_2_west(23)(13), P => Signal_priority(6), Fifo_full => Fifo_full(14),  
+South => south_2_north(24)(14), East => east_2_west(24)(14) , Grant => Signal_grant(24)(14)); 
+
+Arbiter_24_15 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(23)(15), West => east_2_west(23)(14), P => Signal_priority(6), Fifo_full => Fifo_full(15),  
+South => south_2_north(24)(15), East => east_2_west(24)(15) , Grant => Signal_grant(24)(15)); 
+
+-------------------------- Diagonale n° 25 
+
+
+Arbiter_25_1 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(24)(1), West => east_2_west(24)(15), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(25)(1), East => east_2_west(25)(1) , Grant => Signal_grant(25)(1)); 
+
+Arbiter_25_2 : Arbiter
+
+PORT MAP (Request => Request(122), North => south_2_north(24)(2), West => east_2_west(24)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(25)(2), East => east_2_west(25)(2) , Grant => Signal_grant(25)(2)); 
+
+Arbiter_25_3 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(24)(3), West => east_2_west(24)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(25)(3), East => east_2_west(25)(3) , Grant => Signal_grant(25)(3)); 
+
+Arbiter_25_4 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(24)(4), West => east_2_west(24)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(25)(4), East => east_2_west(25)(4) , Grant => Signal_grant(25)(4)); 
+
+Arbiter_25_5 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(24)(5), West => east_2_west(24)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(25)(5), East => east_2_west(25)(5) , Grant => Signal_grant(25)(5)); 
+
+Arbiter_25_6 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(24)(6), West => east_2_west(24)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(25)(6), East => east_2_west(25)(6) , Grant => Signal_grant(25)(6)); 
+
+Arbiter_25_7 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(24)(7), West => east_2_west(24)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(25)(7), East => east_2_west(25)(7) , Grant => Signal_grant(25)(7)); 
+
+Arbiter_25_8 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(24)(8), West => east_2_west(24)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(25)(8), East => east_2_west(25)(8) , Grant => Signal_grant(25)(8)); 
+
+Arbiter_25_9 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(24)(9), West => east_2_west(24)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(25)(9), East => east_2_west(25)(9) , Grant => Signal_grant(25)(9)); 
+
+Arbiter_25_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(24)(10), West => east_2_west(24)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10),  
+South => south_2_north(25)(10), East => east_2_west(25)(10) , Grant => Signal_grant(25)(10)); 
+
+Arbiter_25_11 : Arbiter
+
+PORT MAP (Request => Request(221), North => south_2_north(24)(11), West => east_2_west(24)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11),  
+South => south_2_north(25)(11), East => east_2_west(25)(11) , Grant => Signal_grant(25)(11)); 
+
+Arbiter_25_12 : Arbiter
+
+PORT MAP (Request => Request(207), North => south_2_north(24)(12), West => east_2_west(24)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12),  
+South => south_2_north(25)(12), East => east_2_west(25)(12) , Grant => Signal_grant(25)(12)); 
+
+Arbiter_25_13 : Arbiter
+
+PORT MAP (Request => Request(193), North => south_2_north(24)(13), West => east_2_west(24)(12), P => Signal_priority(5), Fifo_full => Fifo_full(13),  
+South => south_2_north(25)(13), East => east_2_west(25)(13) , Grant => Signal_grant(25)(13)); 
+
+Arbiter_25_14 : Arbiter
+
+PORT MAP (Request => Request(179), North => south_2_north(24)(14), West => east_2_west(24)(13), P => Signal_priority(5), Fifo_full => Fifo_full(14),  
+South => south_2_north(25)(14), East => east_2_west(25)(14) , Grant => Signal_grant(25)(14)); 
+
+Arbiter_25_15 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(24)(15), West => east_2_west(24)(14), P => Signal_priority(5), Fifo_full => Fifo_full(15),  
+South => south_2_north(25)(15), East => east_2_west(25)(15) , Grant => Signal_grant(25)(15)); 
+
+-------------------------- Diagonale n° 26 
+
+
+Arbiter_26_1 : Arbiter
+
+PORT MAP (Request => Request(151), North => south_2_north(25)(1), West => east_2_west(25)(15), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(26)(1), East => east_2_west(26)(1) , Grant => Signal_grant(26)(1)); 
+
+Arbiter_26_2 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(25)(2), West => east_2_west(25)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(26)(2), East => east_2_west(26)(2) , Grant => Signal_grant(26)(2)); 
+
+Arbiter_26_3 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(25)(3), West => east_2_west(25)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(26)(3), East => east_2_west(26)(3) , Grant => Signal_grant(26)(3)); 
+
+Arbiter_26_4 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(25)(4), West => east_2_west(25)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(26)(4), East => east_2_west(26)(4) , Grant => Signal_grant(26)(4)); 
+
+Arbiter_26_5 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(25)(5), West => east_2_west(25)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(26)(5), East => east_2_west(26)(5) , Grant => Signal_grant(26)(5)); 
+
+Arbiter_26_6 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(25)(6), West => east_2_west(25)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(26)(6), East => east_2_west(26)(6) , Grant => Signal_grant(26)(6)); 
+
+Arbiter_26_7 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(25)(7), West => east_2_west(25)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(26)(7), East => east_2_west(26)(7) , Grant => Signal_grant(26)(7)); 
+
+Arbiter_26_8 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(25)(8), West => east_2_west(25)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(26)(8), East => east_2_west(26)(8) , Grant => Signal_grant(26)(8)); 
+
+Arbiter_26_9 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(25)(9), West => east_2_west(25)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(26)(9), East => east_2_west(26)(9) , Grant => Signal_grant(26)(9)); 
+
+Arbiter_26_10 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(25)(10), West => east_2_west(25)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10),  
+South => south_2_north(26)(10), East => east_2_west(26)(10) , Grant => Signal_grant(26)(10)); 
+
+Arbiter_26_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(25)(11), West => east_2_west(25)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11),  
+South => south_2_north(26)(11), East => east_2_west(26)(11) , Grant => Signal_grant(26)(11)); 
+
+Arbiter_26_12 : Arbiter
+
+PORT MAP (Request => Request(222), North => south_2_north(25)(12), West => east_2_west(25)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12),  
+South => south_2_north(26)(12), East => east_2_west(26)(12) , Grant => Signal_grant(26)(12)); 
+
+Arbiter_26_13 : Arbiter
+
+PORT MAP (Request => Request(208), North => south_2_north(25)(13), West => east_2_west(25)(12), P => Signal_priority(4), Fifo_full => Fifo_full(13),  
+South => south_2_north(26)(13), East => east_2_west(26)(13) , Grant => Signal_grant(26)(13)); 
+
+Arbiter_26_14 : Arbiter
+
+PORT MAP (Request => Request(194), North => south_2_north(25)(14), West => east_2_west(25)(13), P => Signal_priority(4), Fifo_full => Fifo_full(14),  
+South => south_2_north(26)(14), East => east_2_west(26)(14) , Grant => Signal_grant(26)(14)); 
+
+Arbiter_26_15 : Arbiter
+
+PORT MAP (Request => Request(180), North => south_2_north(25)(15), West => east_2_west(25)(14), P => Signal_priority(4), Fifo_full => Fifo_full(15),  
+South => south_2_north(26)(15), East => east_2_west(26)(15) , Grant => Signal_grant(26)(15)); 
+
+-------------------------- Diagonale n° 27 
+
+
+Arbiter_27_1 : Arbiter
+
+PORT MAP (Request => Request(166), North => south_2_north(26)(1), West => east_2_west(26)(15), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(27)(1), East => east_2_west(27)(1) , Grant => Signal_grant(27)(1)); 
+
+Arbiter_27_2 : Arbiter
+
+PORT MAP (Request => Request(152), North => south_2_north(26)(2), West => east_2_west(26)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(27)(2), East => east_2_west(27)(2) , Grant => Signal_grant(27)(2)); 
+
+Arbiter_27_3 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(26)(3), West => east_2_west(26)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(27)(3), East => east_2_west(27)(3) , Grant => Signal_grant(27)(3)); 
+
+Arbiter_27_4 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(26)(4), West => east_2_west(26)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(27)(4), East => east_2_west(27)(4) , Grant => Signal_grant(27)(4)); 
+
+Arbiter_27_5 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(26)(5), West => east_2_west(26)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(27)(5), East => east_2_west(27)(5) , Grant => Signal_grant(27)(5)); 
+
+Arbiter_27_6 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(26)(6), West => east_2_west(26)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(27)(6), East => east_2_west(27)(6) , Grant => Signal_grant(27)(6)); 
+
+Arbiter_27_7 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(26)(7), West => east_2_west(26)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(27)(7), East => east_2_west(27)(7) , Grant => Signal_grant(27)(7)); 
+
+Arbiter_27_8 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(26)(8), West => east_2_west(26)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(27)(8), East => east_2_west(27)(8) , Grant => Signal_grant(27)(8)); 
+
+Arbiter_27_9 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(26)(9), West => east_2_west(26)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(27)(9), East => east_2_west(27)(9) , Grant => Signal_grant(27)(9)); 
+
+Arbiter_27_10 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(26)(10), West => east_2_west(26)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10),  
+South => south_2_north(27)(10), East => east_2_west(27)(10) , Grant => Signal_grant(27)(10)); 
+
+Arbiter_27_11 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(26)(11), West => east_2_west(26)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11),  
+South => south_2_north(27)(11), East => east_2_west(27)(11) , Grant => Signal_grant(27)(11)); 
+
+Arbiter_27_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(26)(12), West => east_2_west(26)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12),  
+South => south_2_north(27)(12), East => east_2_west(27)(12) , Grant => Signal_grant(27)(12)); 
+
+Arbiter_27_13 : Arbiter
+
+PORT MAP (Request => Request(223), North => south_2_north(26)(13), West => east_2_west(26)(12), P => Signal_priority(3), Fifo_full => Fifo_full(13),  
+South => south_2_north(27)(13), East => east_2_west(27)(13) , Grant => Signal_grant(27)(13)); 
+
+Arbiter_27_14 : Arbiter
+
+PORT MAP (Request => Request(209), North => south_2_north(26)(14), West => east_2_west(26)(13), P => Signal_priority(3), Fifo_full => Fifo_full(14),  
+South => south_2_north(27)(14), East => east_2_west(27)(14) , Grant => Signal_grant(27)(14)); 
+
+Arbiter_27_15 : Arbiter
+
+PORT MAP (Request => Request(195), North => south_2_north(26)(15), West => east_2_west(26)(14), P => Signal_priority(3), Fifo_full => Fifo_full(15),  
+South => south_2_north(27)(15), East => east_2_west(27)(15) , Grant => Signal_grant(27)(15)); 
+
+-------------------------- Diagonale n° 28 
+
+
+Arbiter_28_1 : Arbiter
+
+PORT MAP (Request => Request(181), North => south_2_north(27)(1), West => east_2_west(27)(15), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(28)(1), East => east_2_west(28)(1) , Grant => Signal_grant(28)(1)); 
+
+Arbiter_28_2 : Arbiter
+
+PORT MAP (Request => Request(167), North => south_2_north(27)(2), West => east_2_west(27)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(28)(2), East => east_2_west(28)(2) , Grant => Signal_grant(28)(2)); 
+
+Arbiter_28_3 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(27)(3), West => east_2_west(27)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(28)(3), East => east_2_west(28)(3) , Grant => Signal_grant(28)(3)); 
+
+Arbiter_28_4 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(27)(4), West => east_2_west(27)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(28)(4), East => east_2_west(28)(4) , Grant => Signal_grant(28)(4)); 
+
+Arbiter_28_5 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(27)(5), West => east_2_west(27)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(28)(5), East => east_2_west(28)(5) , Grant => Signal_grant(28)(5)); 
+
+Arbiter_28_6 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(27)(6), West => east_2_west(27)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(28)(6), East => east_2_west(28)(6) , Grant => Signal_grant(28)(6)); 
+
+Arbiter_28_7 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(27)(7), West => east_2_west(27)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(28)(7), East => east_2_west(28)(7) , Grant => Signal_grant(28)(7)); 
+
+Arbiter_28_8 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(27)(8), West => east_2_west(27)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(28)(8), East => east_2_west(28)(8) , Grant => Signal_grant(28)(8)); 
+
+Arbiter_28_9 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(27)(9), West => east_2_west(27)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(28)(9), East => east_2_west(28)(9) , Grant => Signal_grant(28)(9)); 
+
+Arbiter_28_10 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(27)(10), West => east_2_west(27)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10),  
+South => south_2_north(28)(10), East => east_2_west(28)(10) , Grant => Signal_grant(28)(10)); 
+
+Arbiter_28_11 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(27)(11), West => east_2_west(27)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11),  
+South => south_2_north(28)(11), East => east_2_west(28)(11) , Grant => Signal_grant(28)(11)); 
+
+Arbiter_28_12 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(27)(12), West => east_2_west(27)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12),  
+South => south_2_north(28)(12), East => east_2_west(28)(12) , Grant => Signal_grant(28)(12)); 
+
+Arbiter_28_13 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(27)(13), West => east_2_west(27)(12), P => Signal_priority(2), Fifo_full => Fifo_full(13),  
+South => south_2_north(28)(13), East => east_2_west(28)(13) , Grant => Signal_grant(28)(13)); 
+
+Arbiter_28_14 : Arbiter
+
+PORT MAP (Request => Request(224), North => south_2_north(27)(14), West => east_2_west(27)(13), P => Signal_priority(2), Fifo_full => Fifo_full(14),  
+South => south_2_north(28)(14), East => east_2_west(28)(14) , Grant => Signal_grant(28)(14)); 
+
+Arbiter_28_15 : Arbiter
+
+PORT MAP (Request => Request(210), North => south_2_north(27)(15), West => east_2_west(27)(14), P => Signal_priority(2), Fifo_full => Fifo_full(15),  
+South => south_2_north(28)(15), East => east_2_west(28)(15) , Grant => Signal_grant(28)(15)); 
+
+-------------------------- Diagonale n° 29 
+
+
+Arbiter_29_1 : Arbiter
+
+PORT MAP (Request => Request(196), North => south_2_north(28)(1), West => east_2_west(28)(15), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(29)(1), East => east_2_west(29)(1) , Grant => Signal_grant(29)(1)); 
+
+Arbiter_29_2 : Arbiter
+
+PORT MAP (Request => Request(182), North => south_2_north(28)(2), West => east_2_west(28)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(29)(2), East => east_2_west(29)(2) , Grant => Signal_grant(29)(2)); 
+
+Arbiter_29_3 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(28)(3), West => east_2_west(28)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(29)(3), East => east_2_west(29)(3) , Grant => Signal_grant(29)(3)); 
+
+Arbiter_29_4 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(28)(4), West => east_2_west(28)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(29)(4), East => east_2_west(29)(4) , Grant => Signal_grant(29)(4)); 
+
+Arbiter_29_5 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(28)(5), West => east_2_west(28)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(29)(5), East => east_2_west(29)(5) , Grant => Signal_grant(29)(5)); 
+
+Arbiter_29_6 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(28)(6), West => east_2_west(28)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(29)(6), East => east_2_west(29)(6) , Grant => Signal_grant(29)(6)); 
+
+Arbiter_29_7 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(28)(7), West => east_2_west(28)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(29)(7), East => east_2_west(29)(7) , Grant => Signal_grant(29)(7)); 
+
+Arbiter_29_8 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(28)(8), West => east_2_west(28)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(29)(8), East => east_2_west(29)(8) , Grant => Signal_grant(29)(8)); 
+
+Arbiter_29_9 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(28)(9), West => east_2_west(28)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(29)(9), East => east_2_west(29)(9) , Grant => Signal_grant(29)(9)); 
+
+Arbiter_29_10 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(28)(10), West => east_2_west(28)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10),  
+South => south_2_north(29)(10), East => east_2_west(29)(10) , Grant => Signal_grant(29)(10)); 
+
+Arbiter_29_11 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(28)(11), West => east_2_west(28)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11),  
+South => south_2_north(29)(11), East => east_2_west(29)(11) , Grant => Signal_grant(29)(11)); 
+
+Arbiter_29_12 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(28)(12), West => east_2_west(28)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12),  
+South => south_2_north(29)(12), East => east_2_west(29)(12) , Grant => Signal_grant(29)(12)); 
+
+Arbiter_29_13 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(28)(13), West => east_2_west(28)(12), P => Signal_priority(1), Fifo_full => Fifo_full(13),  
+South => south_2_north(29)(13), East => east_2_west(29)(13) , Grant => Signal_grant(29)(13)); 
+
+Arbiter_29_14 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(28)(14), West => east_2_west(28)(13), P => Signal_priority(1), Fifo_full => Fifo_full(14),  
+South => south_2_north(29)(14), East => east_2_west(29)(14) , Grant => Signal_grant(29)(14)); 
+
+Arbiter_29_15 : Arbiter
+
+PORT MAP (Request => Request(225), North => south_2_north(28)(15), West => east_2_west(28)(14), P => Signal_priority(1), Fifo_full => Fifo_full(15),  
+South => south_2_north(29)(15), East => east_2_west(29)(15) , Grant => Signal_grant(29)(15)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "11111111111111100000000000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "11111111111111100000000000000" => Signal_priority <= "01111111111111110000000000000";
+		       when "01111111111111110000000000000" => Signal_priority <= "00111111111111111000000000000";
+		       when "00111111111111111000000000000" => Signal_priority <= "00011111111111111100000000000";
+		       when "00011111111111111100000000000" => Signal_priority <= "00001111111111111110000000000";
+		       when "00001111111111111110000000000" => Signal_priority <= "00000111111111111111000000000";
+		       when "00000111111111111111000000000" => Signal_priority <= "00000011111111111111100000000";
+		       when "00000011111111111111100000000" => Signal_priority <= "00000001111111111111110000000";
+		       when "00000001111111111111110000000" => Signal_priority <= "00000000111111111111111000000";
+		       when "00000000111111111111111000000" => Signal_priority <= "00000000011111111111111100000";
+		       when "00000000011111111111111100000" => Signal_priority <= "00000000001111111111111110000";
+		       when "00000000001111111111111110000" => Signal_priority <= "00000000000111111111111111000";
+		       when "00000000000111111111111111000" => Signal_priority <= "00000000000011111111111111100";
+		       when "00000000000011111111111111100" => Signal_priority <= "00000000000001111111111111110";
+		       when "00000000000001111111111111110" => Signal_priority <= "00000000000000111111111111111";
+		       when "00000000000000111111111111111" => Signal_priority <= "11111111111111100000000000000";
+		       when others    => Signal_priority <= "11111111111111100000000000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER16_16.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER16_16.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER16_16.VHD	(revision 20)
@@ -0,0 +1,2940 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler16_16 is
+    Port ( Request : in  STD_LOGIC_VECTOR (256 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (16 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (16 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (256 downto 1));
+end Scheduler16_16;
+
+architecture Behavioral of Scheduler16_16 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(31 downto 1) of STD_LOGIC_VECTOR(16 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (31 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(256 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(256 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 65535 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(17)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(18)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(19)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(20)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(21)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(22)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(23)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(24)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) or Signal_grant(25)(9); --  Grant(1,9)
+Grant(10)  <= Signal_grant(10)(10) or Signal_grant(26)(10); --  Grant(1,10)
+Grant(11)  <= Signal_grant(11)(11) or Signal_grant(27)(11); --  Grant(1,11)
+Grant(12)  <= Signal_grant(12)(12) or Signal_grant(28)(12); --  Grant(1,12)
+Grant(13)  <= Signal_grant(13)(13) or Signal_grant(29)(13); --  Grant(1,13)
+Grant(14)  <= Signal_grant(14)(14) or Signal_grant(30)(14); --  Grant(1,14)
+Grant(15)  <= Signal_grant(15)(15) or Signal_grant(31)(15); --  Grant(1,15)
+Grant(16)  <= Signal_grant(16)(16) ;                      --  Grant(1,16)
+Grant(17)  <= Signal_grant(2)(1) or Signal_grant(18)(1); --  Grant(2,1)
+Grant(18)  <= Signal_grant(3)(2) or Signal_grant(19)(2); --  Grant(2,2)
+Grant(19)  <= Signal_grant(4)(3) or Signal_grant(20)(3); --  Grant(2,3)
+Grant(20)  <= Signal_grant(5)(4) or Signal_grant(21)(4); --  Grant(2,4)
+Grant(21)  <= Signal_grant(6)(5) or Signal_grant(22)(5); --  Grant(2,5)
+Grant(22)  <= Signal_grant(7)(6) or Signal_grant(23)(6); --  Grant(2,6)
+Grant(23)  <= Signal_grant(8)(7) or Signal_grant(24)(7); --  Grant(2,7)
+Grant(24)  <= Signal_grant(9)(8) or Signal_grant(25)(8); --  Grant(2,8)
+Grant(25)  <= Signal_grant(10)(9) or Signal_grant(26)(9); --  Grant(2,9)
+Grant(26)  <= Signal_grant(11)(10) or Signal_grant(27)(10); --  Grant(2,10)
+Grant(27)  <= Signal_grant(12)(11) or Signal_grant(28)(11); --  Grant(2,11)
+Grant(28)  <= Signal_grant(13)(12) or Signal_grant(29)(12); --  Grant(2,12)
+Grant(29)  <= Signal_grant(14)(13) or Signal_grant(30)(13); --  Grant(2,13)
+Grant(30)  <= Signal_grant(15)(14) or Signal_grant(31)(14); --  Grant(2,14)
+Grant(31)  <= Signal_grant(16)(15) ;                      --  Grant(2,15)
+Grant(32)  <= Signal_grant(1)(16) or Signal_grant(17)(16); --  Grant(2,16)
+Grant(33)  <= Signal_grant(3)(1) or Signal_grant(19)(1); --  Grant(3,1)
+Grant(34)  <= Signal_grant(4)(2) or Signal_grant(20)(2); --  Grant(3,2)
+Grant(35)  <= Signal_grant(5)(3) or Signal_grant(21)(3); --  Grant(3,3)
+Grant(36)  <= Signal_grant(6)(4) or Signal_grant(22)(4); --  Grant(3,4)
+Grant(37)  <= Signal_grant(7)(5) or Signal_grant(23)(5); --  Grant(3,5)
+Grant(38)  <= Signal_grant(8)(6) or Signal_grant(24)(6); --  Grant(3,6)
+Grant(39)  <= Signal_grant(9)(7) or Signal_grant(25)(7); --  Grant(3,7)
+Grant(40)  <= Signal_grant(10)(8) or Signal_grant(26)(8); --  Grant(3,8)
+Grant(41)  <= Signal_grant(11)(9) or Signal_grant(27)(9); --  Grant(3,9)
+Grant(42)  <= Signal_grant(12)(10) or Signal_grant(28)(10); --  Grant(3,10)
+Grant(43)  <= Signal_grant(13)(11) or Signal_grant(29)(11); --  Grant(3,11)
+Grant(44)  <= Signal_grant(14)(12) or Signal_grant(30)(12); --  Grant(3,12)
+Grant(45)  <= Signal_grant(15)(13) or Signal_grant(31)(13); --  Grant(3,13)
+Grant(46)  <= Signal_grant(16)(14) ;                      --  Grant(3,14)
+Grant(47)  <= Signal_grant(1)(15) or Signal_grant(17)(15); --  Grant(3,15)
+Grant(48)  <= Signal_grant(2)(16) or Signal_grant(18)(16); --  Grant(3,16)
+Grant(49)  <= Signal_grant(4)(1) or Signal_grant(20)(1); --  Grant(4,1)
+Grant(50)  <= Signal_grant(5)(2) or Signal_grant(21)(2); --  Grant(4,2)
+Grant(51)  <= Signal_grant(6)(3) or Signal_grant(22)(3); --  Grant(4,3)
+Grant(52)  <= Signal_grant(7)(4) or Signal_grant(23)(4); --  Grant(4,4)
+Grant(53)  <= Signal_grant(8)(5) or Signal_grant(24)(5); --  Grant(4,5)
+Grant(54)  <= Signal_grant(9)(6) or Signal_grant(25)(6); --  Grant(4,6)
+Grant(55)  <= Signal_grant(10)(7) or Signal_grant(26)(7); --  Grant(4,7)
+Grant(56)  <= Signal_grant(11)(8) or Signal_grant(27)(8); --  Grant(4,8)
+Grant(57)  <= Signal_grant(12)(9) or Signal_grant(28)(9); --  Grant(4,9)
+Grant(58)  <= Signal_grant(13)(10) or Signal_grant(29)(10); --  Grant(4,10)
+Grant(59)  <= Signal_grant(14)(11) or Signal_grant(30)(11); --  Grant(4,11)
+Grant(60)  <= Signal_grant(15)(12) or Signal_grant(31)(12); --  Grant(4,12)
+Grant(61)  <= Signal_grant(16)(13) ;                      --  Grant(4,13)
+Grant(62)  <= Signal_grant(1)(14) or Signal_grant(17)(14); --  Grant(4,14)
+Grant(63)  <= Signal_grant(2)(15) or Signal_grant(18)(15); --  Grant(4,15)
+Grant(64)  <= Signal_grant(3)(16) or Signal_grant(19)(16); --  Grant(4,16)
+Grant(65)  <= Signal_grant(5)(1) or Signal_grant(21)(1); --  Grant(5,1)
+Grant(66)  <= Signal_grant(6)(2) or Signal_grant(22)(2); --  Grant(5,2)
+Grant(67)  <= Signal_grant(7)(3) or Signal_grant(23)(3); --  Grant(5,3)
+Grant(68)  <= Signal_grant(8)(4) or Signal_grant(24)(4); --  Grant(5,4)
+Grant(69)  <= Signal_grant(9)(5) or Signal_grant(25)(5); --  Grant(5,5)
+Grant(70)  <= Signal_grant(10)(6) or Signal_grant(26)(6); --  Grant(5,6)
+Grant(71)  <= Signal_grant(11)(7) or Signal_grant(27)(7); --  Grant(5,7)
+Grant(72)  <= Signal_grant(12)(8) or Signal_grant(28)(8); --  Grant(5,8)
+Grant(73)  <= Signal_grant(13)(9) or Signal_grant(29)(9); --  Grant(5,9)
+Grant(74)  <= Signal_grant(14)(10) or Signal_grant(30)(10); --  Grant(5,10)
+Grant(75)  <= Signal_grant(15)(11) or Signal_grant(31)(11); --  Grant(5,11)
+Grant(76)  <= Signal_grant(16)(12) ;                      --  Grant(5,12)
+Grant(77)  <= Signal_grant(1)(13) or Signal_grant(17)(13); --  Grant(5,13)
+Grant(78)  <= Signal_grant(2)(14) or Signal_grant(18)(14); --  Grant(5,14)
+Grant(79)  <= Signal_grant(3)(15) or Signal_grant(19)(15); --  Grant(5,15)
+Grant(80)  <= Signal_grant(4)(16) or Signal_grant(20)(16); --  Grant(5,16)
+Grant(81)  <= Signal_grant(6)(1) or Signal_grant(22)(1); --  Grant(6,1)
+Grant(82)  <= Signal_grant(7)(2) or Signal_grant(23)(2); --  Grant(6,2)
+Grant(83)  <= Signal_grant(8)(3) or Signal_grant(24)(3); --  Grant(6,3)
+Grant(84)  <= Signal_grant(9)(4) or Signal_grant(25)(4); --  Grant(6,4)
+Grant(85)  <= Signal_grant(10)(5) or Signal_grant(26)(5); --  Grant(6,5)
+Grant(86)  <= Signal_grant(11)(6) or Signal_grant(27)(6); --  Grant(6,6)
+Grant(87)  <= Signal_grant(12)(7) or Signal_grant(28)(7); --  Grant(6,7)
+Grant(88)  <= Signal_grant(13)(8) or Signal_grant(29)(8); --  Grant(6,8)
+Grant(89)  <= Signal_grant(14)(9) or Signal_grant(30)(9); --  Grant(6,9)
+Grant(90)  <= Signal_grant(15)(10) or Signal_grant(31)(10); --  Grant(6,10)
+Grant(91)  <= Signal_grant(16)(11) ;                      --  Grant(6,11)
+Grant(92)  <= Signal_grant(1)(12) or Signal_grant(17)(12); --  Grant(6,12)
+Grant(93)  <= Signal_grant(2)(13) or Signal_grant(18)(13); --  Grant(6,13)
+Grant(94)  <= Signal_grant(3)(14) or Signal_grant(19)(14); --  Grant(6,14)
+Grant(95)  <= Signal_grant(4)(15) or Signal_grant(20)(15); --  Grant(6,15)
+Grant(96)  <= Signal_grant(5)(16) or Signal_grant(21)(16); --  Grant(6,16)
+Grant(97)  <= Signal_grant(7)(1) or Signal_grant(23)(1); --  Grant(7,1)
+Grant(98)  <= Signal_grant(8)(2) or Signal_grant(24)(2); --  Grant(7,2)
+Grant(99)  <= Signal_grant(9)(3) or Signal_grant(25)(3); --  Grant(7,3)
+Grant(100)  <= Signal_grant(10)(4) or Signal_grant(26)(4); --  Grant(7,4)
+Grant(101)  <= Signal_grant(11)(5) or Signal_grant(27)(5); --  Grant(7,5)
+Grant(102)  <= Signal_grant(12)(6) or Signal_grant(28)(6); --  Grant(7,6)
+Grant(103)  <= Signal_grant(13)(7) or Signal_grant(29)(7); --  Grant(7,7)
+Grant(104)  <= Signal_grant(14)(8) or Signal_grant(30)(8); --  Grant(7,8)
+Grant(105)  <= Signal_grant(15)(9) or Signal_grant(31)(9); --  Grant(7,9)
+Grant(106)  <= Signal_grant(16)(10) ;                      --  Grant(7,10)
+Grant(107)  <= Signal_grant(1)(11) or Signal_grant(17)(11); --  Grant(7,11)
+Grant(108)  <= Signal_grant(2)(12) or Signal_grant(18)(12); --  Grant(7,12)
+Grant(109)  <= Signal_grant(3)(13) or Signal_grant(19)(13); --  Grant(7,13)
+Grant(110)  <= Signal_grant(4)(14) or Signal_grant(20)(14); --  Grant(7,14)
+Grant(111)  <= Signal_grant(5)(15) or Signal_grant(21)(15); --  Grant(7,15)
+Grant(112)  <= Signal_grant(6)(16) or Signal_grant(22)(16); --  Grant(7,16)
+Grant(113)  <= Signal_grant(8)(1) or Signal_grant(24)(1); --  Grant(8,1)
+Grant(114)  <= Signal_grant(9)(2) or Signal_grant(25)(2); --  Grant(8,2)
+Grant(115)  <= Signal_grant(10)(3) or Signal_grant(26)(3); --  Grant(8,3)
+Grant(116)  <= Signal_grant(11)(4) or Signal_grant(27)(4); --  Grant(8,4)
+Grant(117)  <= Signal_grant(12)(5) or Signal_grant(28)(5); --  Grant(8,5)
+Grant(118)  <= Signal_grant(13)(6) or Signal_grant(29)(6); --  Grant(8,6)
+Grant(119)  <= Signal_grant(14)(7) or Signal_grant(30)(7); --  Grant(8,7)
+Grant(120)  <= Signal_grant(15)(8) or Signal_grant(31)(8); --  Grant(8,8)
+Grant(121)  <= Signal_grant(16)(9) ;                      --  Grant(8,9)
+Grant(122)  <= Signal_grant(1)(10) or Signal_grant(17)(10); --  Grant(8,10)
+Grant(123)  <= Signal_grant(2)(11) or Signal_grant(18)(11); --  Grant(8,11)
+Grant(124)  <= Signal_grant(3)(12) or Signal_grant(19)(12); --  Grant(8,12)
+Grant(125)  <= Signal_grant(4)(13) or Signal_grant(20)(13); --  Grant(8,13)
+Grant(126)  <= Signal_grant(5)(14) or Signal_grant(21)(14); --  Grant(8,14)
+Grant(127)  <= Signal_grant(6)(15) or Signal_grant(22)(15); --  Grant(8,15)
+Grant(128)  <= Signal_grant(7)(16) or Signal_grant(23)(16); --  Grant(8,16)
+Grant(129)  <= Signal_grant(9)(1) or Signal_grant(25)(1); --  Grant(9,1)
+Grant(130)  <= Signal_grant(10)(2) or Signal_grant(26)(2); --  Grant(9,2)
+Grant(131)  <= Signal_grant(11)(3) or Signal_grant(27)(3); --  Grant(9,3)
+Grant(132)  <= Signal_grant(12)(4) or Signal_grant(28)(4); --  Grant(9,4)
+Grant(133)  <= Signal_grant(13)(5) or Signal_grant(29)(5); --  Grant(9,5)
+Grant(134)  <= Signal_grant(14)(6) or Signal_grant(30)(6); --  Grant(9,6)
+Grant(135)  <= Signal_grant(15)(7) or Signal_grant(31)(7); --  Grant(9,7)
+Grant(136)  <= Signal_grant(16)(8) ;                      --  Grant(9,8)
+Grant(137)  <= Signal_grant(1)(9) or Signal_grant(17)(9); --  Grant(9,9)
+Grant(138)  <= Signal_grant(2)(10) or Signal_grant(18)(10); --  Grant(9,10)
+Grant(139)  <= Signal_grant(3)(11) or Signal_grant(19)(11); --  Grant(9,11)
+Grant(140)  <= Signal_grant(4)(12) or Signal_grant(20)(12); --  Grant(9,12)
+Grant(141)  <= Signal_grant(5)(13) or Signal_grant(21)(13); --  Grant(9,13)
+Grant(142)  <= Signal_grant(6)(14) or Signal_grant(22)(14); --  Grant(9,14)
+Grant(143)  <= Signal_grant(7)(15) or Signal_grant(23)(15); --  Grant(9,15)
+Grant(144)  <= Signal_grant(8)(16) or Signal_grant(24)(16); --  Grant(9,16)
+Grant(145)  <= Signal_grant(10)(1) or Signal_grant(26)(1); --  Grant(10,1)
+Grant(146)  <= Signal_grant(11)(2) or Signal_grant(27)(2); --  Grant(10,2)
+Grant(147)  <= Signal_grant(12)(3) or Signal_grant(28)(3); --  Grant(10,3)
+Grant(148)  <= Signal_grant(13)(4) or Signal_grant(29)(4); --  Grant(10,4)
+Grant(149)  <= Signal_grant(14)(5) or Signal_grant(30)(5); --  Grant(10,5)
+Grant(150)  <= Signal_grant(15)(6) or Signal_grant(31)(6); --  Grant(10,6)
+Grant(151)  <= Signal_grant(16)(7) ;                      --  Grant(10,7)
+Grant(152)  <= Signal_grant(1)(8) or Signal_grant(17)(8); --  Grant(10,8)
+Grant(153)  <= Signal_grant(2)(9) or Signal_grant(18)(9); --  Grant(10,9)
+Grant(154)  <= Signal_grant(3)(10) or Signal_grant(19)(10); --  Grant(10,10)
+Grant(155)  <= Signal_grant(4)(11) or Signal_grant(20)(11); --  Grant(10,11)
+Grant(156)  <= Signal_grant(5)(12) or Signal_grant(21)(12); --  Grant(10,12)
+Grant(157)  <= Signal_grant(6)(13) or Signal_grant(22)(13); --  Grant(10,13)
+Grant(158)  <= Signal_grant(7)(14) or Signal_grant(23)(14); --  Grant(10,14)
+Grant(159)  <= Signal_grant(8)(15) or Signal_grant(24)(15); --  Grant(10,15)
+Grant(160)  <= Signal_grant(9)(16) or Signal_grant(25)(16); --  Grant(10,16)
+Grant(161)  <= Signal_grant(11)(1) or Signal_grant(27)(1); --  Grant(11,1)
+Grant(162)  <= Signal_grant(12)(2) or Signal_grant(28)(2); --  Grant(11,2)
+Grant(163)  <= Signal_grant(13)(3) or Signal_grant(29)(3); --  Grant(11,3)
+Grant(164)  <= Signal_grant(14)(4) or Signal_grant(30)(4); --  Grant(11,4)
+Grant(165)  <= Signal_grant(15)(5) or Signal_grant(31)(5); --  Grant(11,5)
+Grant(166)  <= Signal_grant(16)(6) ;                      --  Grant(11,6)
+Grant(167)  <= Signal_grant(1)(7) or Signal_grant(17)(7); --  Grant(11,7)
+Grant(168)  <= Signal_grant(2)(8) or Signal_grant(18)(8); --  Grant(11,8)
+Grant(169)  <= Signal_grant(3)(9) or Signal_grant(19)(9); --  Grant(11,9)
+Grant(170)  <= Signal_grant(4)(10) or Signal_grant(20)(10); --  Grant(11,10)
+Grant(171)  <= Signal_grant(5)(11) or Signal_grant(21)(11); --  Grant(11,11)
+Grant(172)  <= Signal_grant(6)(12) or Signal_grant(22)(12); --  Grant(11,12)
+Grant(173)  <= Signal_grant(7)(13) or Signal_grant(23)(13); --  Grant(11,13)
+Grant(174)  <= Signal_grant(8)(14) or Signal_grant(24)(14); --  Grant(11,14)
+Grant(175)  <= Signal_grant(9)(15) or Signal_grant(25)(15); --  Grant(11,15)
+Grant(176)  <= Signal_grant(10)(16) or Signal_grant(26)(16); --  Grant(11,16)
+Grant(177)  <= Signal_grant(12)(1) or Signal_grant(28)(1); --  Grant(12,1)
+Grant(178)  <= Signal_grant(13)(2) or Signal_grant(29)(2); --  Grant(12,2)
+Grant(179)  <= Signal_grant(14)(3) or Signal_grant(30)(3); --  Grant(12,3)
+Grant(180)  <= Signal_grant(15)(4) or Signal_grant(31)(4); --  Grant(12,4)
+Grant(181)  <= Signal_grant(16)(5) ;                      --  Grant(12,5)
+Grant(182)  <= Signal_grant(1)(6) or Signal_grant(17)(6); --  Grant(12,6)
+Grant(183)  <= Signal_grant(2)(7) or Signal_grant(18)(7); --  Grant(12,7)
+Grant(184)  <= Signal_grant(3)(8) or Signal_grant(19)(8); --  Grant(12,8)
+Grant(185)  <= Signal_grant(4)(9) or Signal_grant(20)(9); --  Grant(12,9)
+Grant(186)  <= Signal_grant(5)(10) or Signal_grant(21)(10); --  Grant(12,10)
+Grant(187)  <= Signal_grant(6)(11) or Signal_grant(22)(11); --  Grant(12,11)
+Grant(188)  <= Signal_grant(7)(12) or Signal_grant(23)(12); --  Grant(12,12)
+Grant(189)  <= Signal_grant(8)(13) or Signal_grant(24)(13); --  Grant(12,13)
+Grant(190)  <= Signal_grant(9)(14) or Signal_grant(25)(14); --  Grant(12,14)
+Grant(191)  <= Signal_grant(10)(15) or Signal_grant(26)(15); --  Grant(12,15)
+Grant(192)  <= Signal_grant(11)(16) or Signal_grant(27)(16); --  Grant(12,16)
+Grant(193)  <= Signal_grant(13)(1) or Signal_grant(29)(1); --  Grant(13,1)
+Grant(194)  <= Signal_grant(14)(2) or Signal_grant(30)(2); --  Grant(13,2)
+Grant(195)  <= Signal_grant(15)(3) or Signal_grant(31)(3); --  Grant(13,3)
+Grant(196)  <= Signal_grant(16)(4) ;                      --  Grant(13,4)
+Grant(197)  <= Signal_grant(1)(5) or Signal_grant(17)(5); --  Grant(13,5)
+Grant(198)  <= Signal_grant(2)(6) or Signal_grant(18)(6); --  Grant(13,6)
+Grant(199)  <= Signal_grant(3)(7) or Signal_grant(19)(7); --  Grant(13,7)
+Grant(200)  <= Signal_grant(4)(8) or Signal_grant(20)(8); --  Grant(13,8)
+Grant(201)  <= Signal_grant(5)(9) or Signal_grant(21)(9); --  Grant(13,9)
+Grant(202)  <= Signal_grant(6)(10) or Signal_grant(22)(10); --  Grant(13,10)
+Grant(203)  <= Signal_grant(7)(11) or Signal_grant(23)(11); --  Grant(13,11)
+Grant(204)  <= Signal_grant(8)(12) or Signal_grant(24)(12); --  Grant(13,12)
+Grant(205)  <= Signal_grant(9)(13) or Signal_grant(25)(13); --  Grant(13,13)
+Grant(206)  <= Signal_grant(10)(14) or Signal_grant(26)(14); --  Grant(13,14)
+Grant(207)  <= Signal_grant(11)(15) or Signal_grant(27)(15); --  Grant(13,15)
+Grant(208)  <= Signal_grant(12)(16) or Signal_grant(28)(16); --  Grant(13,16)
+Grant(209)  <= Signal_grant(14)(1) or Signal_grant(30)(1); --  Grant(14,1)
+Grant(210)  <= Signal_grant(15)(2) or Signal_grant(31)(2); --  Grant(14,2)
+Grant(211)  <= Signal_grant(16)(3) ;                      --  Grant(14,3)
+Grant(212)  <= Signal_grant(1)(4) or Signal_grant(17)(4); --  Grant(14,4)
+Grant(213)  <= Signal_grant(2)(5) or Signal_grant(18)(5); --  Grant(14,5)
+Grant(214)  <= Signal_grant(3)(6) or Signal_grant(19)(6); --  Grant(14,6)
+Grant(215)  <= Signal_grant(4)(7) or Signal_grant(20)(7); --  Grant(14,7)
+Grant(216)  <= Signal_grant(5)(8) or Signal_grant(21)(8); --  Grant(14,8)
+Grant(217)  <= Signal_grant(6)(9) or Signal_grant(22)(9); --  Grant(14,9)
+Grant(218)  <= Signal_grant(7)(10) or Signal_grant(23)(10); --  Grant(14,10)
+Grant(219)  <= Signal_grant(8)(11) or Signal_grant(24)(11); --  Grant(14,11)
+Grant(220)  <= Signal_grant(9)(12) or Signal_grant(25)(12); --  Grant(14,12)
+Grant(221)  <= Signal_grant(10)(13) or Signal_grant(26)(13); --  Grant(14,13)
+Grant(222)  <= Signal_grant(11)(14) or Signal_grant(27)(14); --  Grant(14,14)
+Grant(223)  <= Signal_grant(12)(15) or Signal_grant(28)(15); --  Grant(14,15)
+Grant(224)  <= Signal_grant(13)(16) or Signal_grant(29)(16); --  Grant(14,16)
+Grant(225)  <= Signal_grant(15)(1) or Signal_grant(31)(1); --  Grant(15,1)
+Grant(226)  <= Signal_grant(16)(2) ;                      --  Grant(15,2)
+Grant(227)  <= Signal_grant(1)(3) or Signal_grant(17)(3); --  Grant(15,3)
+Grant(228)  <= Signal_grant(2)(4) or Signal_grant(18)(4); --  Grant(15,4)
+Grant(229)  <= Signal_grant(3)(5) or Signal_grant(19)(5); --  Grant(15,5)
+Grant(230)  <= Signal_grant(4)(6) or Signal_grant(20)(6); --  Grant(15,6)
+Grant(231)  <= Signal_grant(5)(7) or Signal_grant(21)(7); --  Grant(15,7)
+Grant(232)  <= Signal_grant(6)(8) or Signal_grant(22)(8); --  Grant(15,8)
+Grant(233)  <= Signal_grant(7)(9) or Signal_grant(23)(9); --  Grant(15,9)
+Grant(234)  <= Signal_grant(8)(10) or Signal_grant(24)(10); --  Grant(15,10)
+Grant(235)  <= Signal_grant(9)(11) or Signal_grant(25)(11); --  Grant(15,11)
+Grant(236)  <= Signal_grant(10)(12) or Signal_grant(26)(12); --  Grant(15,12)
+Grant(237)  <= Signal_grant(11)(13) or Signal_grant(27)(13); --  Grant(15,13)
+Grant(238)  <= Signal_grant(12)(14) or Signal_grant(28)(14); --  Grant(15,14)
+Grant(239)  <= Signal_grant(13)(15) or Signal_grant(29)(15); --  Grant(15,15)
+Grant(240)  <= Signal_grant(14)(16) or Signal_grant(30)(16); --  Grant(15,16)
+Grant(241)  <= Signal_grant(16)(1) ;                      --  Grant(16,1)
+Grant(242)  <= Signal_grant(1)(2) or Signal_grant(17)(2); --  Grant(16,2)
+Grant(243)  <= Signal_grant(2)(3) or Signal_grant(18)(3); --  Grant(16,3)
+Grant(244)  <= Signal_grant(3)(4) or Signal_grant(19)(4); --  Grant(16,4)
+Grant(245)  <= Signal_grant(4)(5) or Signal_grant(20)(5); --  Grant(16,5)
+Grant(246)  <= Signal_grant(5)(6) or Signal_grant(21)(6); --  Grant(16,6)
+Grant(247)  <= Signal_grant(6)(7) or Signal_grant(22)(7); --  Grant(16,7)
+Grant(248)  <= Signal_grant(7)(8) or Signal_grant(23)(8); --  Grant(16,8)
+Grant(249)  <= Signal_grant(8)(9) or Signal_grant(24)(9); --  Grant(16,9)
+Grant(250)  <= Signal_grant(9)(10) or Signal_grant(25)(10); --  Grant(16,10)
+Grant(251)  <= Signal_grant(10)(11) or Signal_grant(26)(11); --  Grant(16,11)
+Grant(252)  <= Signal_grant(11)(12) or Signal_grant(27)(12); --  Grant(16,12)
+Grant(253)  <= Signal_grant(12)(13) or Signal_grant(28)(13); --  Grant(16,13)
+Grant(254)  <= Signal_grant(13)(14) or Signal_grant(29)(14); --  Grant(16,14)
+Grant(255)  <= Signal_grant(14)(15) or Signal_grant(30)(15); --  Grant(16,15)
+Grant(256)  <= Signal_grant(15)(16) or Signal_grant(31)(16); --  Grant(16,16)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(242), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(227), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(212), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(197), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(182), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(167), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(152), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(137), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+Arbiter_1_10 : Arbiter
+
+PORT MAP (Request => Request(122), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(10),  
+South => south_2_north(1)(10), East => east_2_west(1)(10) , Grant => Signal_grant(1)(10)); 
+
+Arbiter_1_11 : Arbiter
+
+PORT MAP (Request => Request(107), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(11),  
+South => south_2_north(1)(11), East => east_2_west(1)(11) , Grant => Signal_grant(1)(11)); 
+
+Arbiter_1_12 : Arbiter
+
+PORT MAP (Request => Request(92), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(12),  
+South => south_2_north(1)(12), East => east_2_west(1)(12) , Grant => Signal_grant(1)(12)); 
+
+Arbiter_1_13 : Arbiter
+
+PORT MAP (Request => Request(77), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(13),  
+South => south_2_north(1)(13), East => east_2_west(1)(13) , Grant => Signal_grant(1)(13)); 
+
+Arbiter_1_14 : Arbiter
+
+PORT MAP (Request => Request(62), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(14),  
+South => south_2_north(1)(14), East => east_2_west(1)(14) , Grant => Signal_grant(1)(14)); 
+
+Arbiter_1_15 : Arbiter
+
+PORT MAP (Request => Request(47), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(15),  
+South => south_2_north(1)(15), East => east_2_west(1)(15) , Grant => Signal_grant(1)(15)); 
+
+Arbiter_1_16 : Arbiter
+
+PORT MAP (Request => Request(32), North => High, West => High, P => Signal_priority(31), Fifo_full => Fifo_full(16),  
+South => south_2_north(1)(16), East => east_2_west(1)(16) , Grant => Signal_grant(1)(16)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(1)(1), West => east_2_west(1)(16), P => Signal_priority(30), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(30), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(243), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(30), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(228), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(30), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(213), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(30), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(198), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(30), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(183), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(30), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(30), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(30), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+Arbiter_2_10 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(1)(10), West => east_2_west(1)(9), P => Signal_priority(30), Fifo_full => Fifo_full(10),  
+South => south_2_north(2)(10), East => east_2_west(2)(10) , Grant => Signal_grant(2)(10)); 
+
+Arbiter_2_11 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(1)(11), West => east_2_west(1)(10), P => Signal_priority(30), Fifo_full => Fifo_full(11),  
+South => south_2_north(2)(11), East => east_2_west(2)(11) , Grant => Signal_grant(2)(11)); 
+
+Arbiter_2_12 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(1)(12), West => east_2_west(1)(11), P => Signal_priority(30), Fifo_full => Fifo_full(12),  
+South => south_2_north(2)(12), East => east_2_west(2)(12) , Grant => Signal_grant(2)(12)); 
+
+Arbiter_2_13 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(1)(13), West => east_2_west(1)(12), P => Signal_priority(30), Fifo_full => Fifo_full(13),  
+South => south_2_north(2)(13), East => east_2_west(2)(13) , Grant => Signal_grant(2)(13)); 
+
+Arbiter_2_14 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(1)(14), West => east_2_west(1)(13), P => Signal_priority(30), Fifo_full => Fifo_full(14),  
+South => south_2_north(2)(14), East => east_2_west(2)(14) , Grant => Signal_grant(2)(14)); 
+
+Arbiter_2_15 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(1)(15), West => east_2_west(1)(14), P => Signal_priority(30), Fifo_full => Fifo_full(15),  
+South => south_2_north(2)(15), East => east_2_west(2)(15) , Grant => Signal_grant(2)(15)); 
+
+Arbiter_2_16 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(1)(16), West => east_2_west(1)(15), P => Signal_priority(30), Fifo_full => Fifo_full(16),  
+South => south_2_north(2)(16), East => east_2_west(2)(16) , Grant => Signal_grant(2)(16)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(2)(1), West => east_2_west(2)(16), P => Signal_priority(29), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(29), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(29), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(244), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(29), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(229), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(29), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(214), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(29), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(199), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(29), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(184), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(29), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(169), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(29), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+Arbiter_3_10 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(2)(10), West => east_2_west(2)(9), P => Signal_priority(29), Fifo_full => Fifo_full(10),  
+South => south_2_north(3)(10), East => east_2_west(3)(10) , Grant => Signal_grant(3)(10)); 
+
+Arbiter_3_11 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(2)(11), West => east_2_west(2)(10), P => Signal_priority(29), Fifo_full => Fifo_full(11),  
+South => south_2_north(3)(11), East => east_2_west(3)(11) , Grant => Signal_grant(3)(11)); 
+
+Arbiter_3_12 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(2)(12), West => east_2_west(2)(11), P => Signal_priority(29), Fifo_full => Fifo_full(12),  
+South => south_2_north(3)(12), East => east_2_west(3)(12) , Grant => Signal_grant(3)(12)); 
+
+Arbiter_3_13 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(2)(13), West => east_2_west(2)(12), P => Signal_priority(29), Fifo_full => Fifo_full(13),  
+South => south_2_north(3)(13), East => east_2_west(3)(13) , Grant => Signal_grant(3)(13)); 
+
+Arbiter_3_14 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(2)(14), West => east_2_west(2)(13), P => Signal_priority(29), Fifo_full => Fifo_full(14),  
+South => south_2_north(3)(14), East => east_2_west(3)(14) , Grant => Signal_grant(3)(14)); 
+
+Arbiter_3_15 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(2)(15), West => east_2_west(2)(14), P => Signal_priority(29), Fifo_full => Fifo_full(15),  
+South => south_2_north(3)(15), East => east_2_west(3)(15) , Grant => Signal_grant(3)(15)); 
+
+Arbiter_3_16 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(2)(16), West => east_2_west(2)(15), P => Signal_priority(29), Fifo_full => Fifo_full(16),  
+South => south_2_north(3)(16), East => east_2_west(3)(16) , Grant => Signal_grant(3)(16)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(3)(1), West => east_2_west(3)(16), P => Signal_priority(28), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(28), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(28), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(28), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(245), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(28), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(230), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(28), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(215), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(28), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(200), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(28), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(185), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(28), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+Arbiter_4_10 : Arbiter
+
+PORT MAP (Request => Request(170), North => south_2_north(3)(10), West => east_2_west(3)(9), P => Signal_priority(28), Fifo_full => Fifo_full(10),  
+South => south_2_north(4)(10), East => east_2_west(4)(10) , Grant => Signal_grant(4)(10)); 
+
+Arbiter_4_11 : Arbiter
+
+PORT MAP (Request => Request(155), North => south_2_north(3)(11), West => east_2_west(3)(10), P => Signal_priority(28), Fifo_full => Fifo_full(11),  
+South => south_2_north(4)(11), East => east_2_west(4)(11) , Grant => Signal_grant(4)(11)); 
+
+Arbiter_4_12 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(3)(12), West => east_2_west(3)(11), P => Signal_priority(28), Fifo_full => Fifo_full(12),  
+South => south_2_north(4)(12), East => east_2_west(4)(12) , Grant => Signal_grant(4)(12)); 
+
+Arbiter_4_13 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(3)(13), West => east_2_west(3)(12), P => Signal_priority(28), Fifo_full => Fifo_full(13),  
+South => south_2_north(4)(13), East => east_2_west(4)(13) , Grant => Signal_grant(4)(13)); 
+
+Arbiter_4_14 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(3)(14), West => east_2_west(3)(13), P => Signal_priority(28), Fifo_full => Fifo_full(14),  
+South => south_2_north(4)(14), East => east_2_west(4)(14) , Grant => Signal_grant(4)(14)); 
+
+Arbiter_4_15 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(3)(15), West => east_2_west(3)(14), P => Signal_priority(28), Fifo_full => Fifo_full(15),  
+South => south_2_north(4)(15), East => east_2_west(4)(15) , Grant => Signal_grant(4)(15)); 
+
+Arbiter_4_16 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(3)(16), West => east_2_west(3)(15), P => Signal_priority(28), Fifo_full => Fifo_full(16),  
+South => south_2_north(4)(16), East => east_2_west(4)(16) , Grant => Signal_grant(4)(16)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(4)(1), West => east_2_west(4)(16), P => Signal_priority(27), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(27), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(27), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(27), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(27), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(246), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(27), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(231), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(27), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(216), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(27), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(201), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(27), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+Arbiter_5_10 : Arbiter
+
+PORT MAP (Request => Request(186), North => south_2_north(4)(10), West => east_2_west(4)(9), P => Signal_priority(27), Fifo_full => Fifo_full(10),  
+South => south_2_north(5)(10), East => east_2_west(5)(10) , Grant => Signal_grant(5)(10)); 
+
+Arbiter_5_11 : Arbiter
+
+PORT MAP (Request => Request(171), North => south_2_north(4)(11), West => east_2_west(4)(10), P => Signal_priority(27), Fifo_full => Fifo_full(11),  
+South => south_2_north(5)(11), East => east_2_west(5)(11) , Grant => Signal_grant(5)(11)); 
+
+Arbiter_5_12 : Arbiter
+
+PORT MAP (Request => Request(156), North => south_2_north(4)(12), West => east_2_west(4)(11), P => Signal_priority(27), Fifo_full => Fifo_full(12),  
+South => south_2_north(5)(12), East => east_2_west(5)(12) , Grant => Signal_grant(5)(12)); 
+
+Arbiter_5_13 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(4)(13), West => east_2_west(4)(12), P => Signal_priority(27), Fifo_full => Fifo_full(13),  
+South => south_2_north(5)(13), East => east_2_west(5)(13) , Grant => Signal_grant(5)(13)); 
+
+Arbiter_5_14 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(4)(14), West => east_2_west(4)(13), P => Signal_priority(27), Fifo_full => Fifo_full(14),  
+South => south_2_north(5)(14), East => east_2_west(5)(14) , Grant => Signal_grant(5)(14)); 
+
+Arbiter_5_15 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(4)(15), West => east_2_west(4)(14), P => Signal_priority(27), Fifo_full => Fifo_full(15),  
+South => south_2_north(5)(15), East => east_2_west(5)(15) , Grant => Signal_grant(5)(15)); 
+
+Arbiter_5_16 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(4)(16), West => east_2_west(4)(15), P => Signal_priority(27), Fifo_full => Fifo_full(16),  
+South => south_2_north(5)(16), East => east_2_west(5)(16) , Grant => Signal_grant(5)(16)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(5)(1), West => east_2_west(5)(16), P => Signal_priority(26), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(26), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(26), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(26), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(26), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(26), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(247), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(26), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(232), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(26), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(217), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(26), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+Arbiter_6_10 : Arbiter
+
+PORT MAP (Request => Request(202), North => south_2_north(5)(10), West => east_2_west(5)(9), P => Signal_priority(26), Fifo_full => Fifo_full(10),  
+South => south_2_north(6)(10), East => east_2_west(6)(10) , Grant => Signal_grant(6)(10)); 
+
+Arbiter_6_11 : Arbiter
+
+PORT MAP (Request => Request(187), North => south_2_north(5)(11), West => east_2_west(5)(10), P => Signal_priority(26), Fifo_full => Fifo_full(11),  
+South => south_2_north(6)(11), East => east_2_west(6)(11) , Grant => Signal_grant(6)(11)); 
+
+Arbiter_6_12 : Arbiter
+
+PORT MAP (Request => Request(172), North => south_2_north(5)(12), West => east_2_west(5)(11), P => Signal_priority(26), Fifo_full => Fifo_full(12),  
+South => south_2_north(6)(12), East => east_2_west(6)(12) , Grant => Signal_grant(6)(12)); 
+
+Arbiter_6_13 : Arbiter
+
+PORT MAP (Request => Request(157), North => south_2_north(5)(13), West => east_2_west(5)(12), P => Signal_priority(26), Fifo_full => Fifo_full(13),  
+South => south_2_north(6)(13), East => east_2_west(6)(13) , Grant => Signal_grant(6)(13)); 
+
+Arbiter_6_14 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(5)(14), West => east_2_west(5)(13), P => Signal_priority(26), Fifo_full => Fifo_full(14),  
+South => south_2_north(6)(14), East => east_2_west(6)(14) , Grant => Signal_grant(6)(14)); 
+
+Arbiter_6_15 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(5)(15), West => east_2_west(5)(14), P => Signal_priority(26), Fifo_full => Fifo_full(15),  
+South => south_2_north(6)(15), East => east_2_west(6)(15) , Grant => Signal_grant(6)(15)); 
+
+Arbiter_6_16 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(5)(16), West => east_2_west(5)(15), P => Signal_priority(26), Fifo_full => Fifo_full(16),  
+South => south_2_north(6)(16), East => east_2_west(6)(16) , Grant => Signal_grant(6)(16)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(6)(1), West => east_2_west(6)(16), P => Signal_priority(25), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(25), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(25), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(25), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(25), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(25), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(25), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(248), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(25), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(233), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(25), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+Arbiter_7_10 : Arbiter
+
+PORT MAP (Request => Request(218), North => south_2_north(6)(10), West => east_2_west(6)(9), P => Signal_priority(25), Fifo_full => Fifo_full(10),  
+South => south_2_north(7)(10), East => east_2_west(7)(10) , Grant => Signal_grant(7)(10)); 
+
+Arbiter_7_11 : Arbiter
+
+PORT MAP (Request => Request(203), North => south_2_north(6)(11), West => east_2_west(6)(10), P => Signal_priority(25), Fifo_full => Fifo_full(11),  
+South => south_2_north(7)(11), East => east_2_west(7)(11) , Grant => Signal_grant(7)(11)); 
+
+Arbiter_7_12 : Arbiter
+
+PORT MAP (Request => Request(188), North => south_2_north(6)(12), West => east_2_west(6)(11), P => Signal_priority(25), Fifo_full => Fifo_full(12),  
+South => south_2_north(7)(12), East => east_2_west(7)(12) , Grant => Signal_grant(7)(12)); 
+
+Arbiter_7_13 : Arbiter
+
+PORT MAP (Request => Request(173), North => south_2_north(6)(13), West => east_2_west(6)(12), P => Signal_priority(25), Fifo_full => Fifo_full(13),  
+South => south_2_north(7)(13), East => east_2_west(7)(13) , Grant => Signal_grant(7)(13)); 
+
+Arbiter_7_14 : Arbiter
+
+PORT MAP (Request => Request(158), North => south_2_north(6)(14), West => east_2_west(6)(13), P => Signal_priority(25), Fifo_full => Fifo_full(14),  
+South => south_2_north(7)(14), East => east_2_west(7)(14) , Grant => Signal_grant(7)(14)); 
+
+Arbiter_7_15 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(6)(15), West => east_2_west(6)(14), P => Signal_priority(25), Fifo_full => Fifo_full(15),  
+South => south_2_north(7)(15), East => east_2_west(7)(15) , Grant => Signal_grant(7)(15)); 
+
+Arbiter_7_16 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(6)(16), West => east_2_west(6)(15), P => Signal_priority(25), Fifo_full => Fifo_full(16),  
+South => south_2_north(7)(16), East => east_2_west(7)(16) , Grant => Signal_grant(7)(16)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(7)(1), West => east_2_west(7)(16), P => Signal_priority(24), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(24), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(24), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(24), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(24), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(24), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(24), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(24), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(249), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(24), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+Arbiter_8_10 : Arbiter
+
+PORT MAP (Request => Request(234), North => south_2_north(7)(10), West => east_2_west(7)(9), P => Signal_priority(24), Fifo_full => Fifo_full(10),  
+South => south_2_north(8)(10), East => east_2_west(8)(10) , Grant => Signal_grant(8)(10)); 
+
+Arbiter_8_11 : Arbiter
+
+PORT MAP (Request => Request(219), North => south_2_north(7)(11), West => east_2_west(7)(10), P => Signal_priority(24), Fifo_full => Fifo_full(11),  
+South => south_2_north(8)(11), East => east_2_west(8)(11) , Grant => Signal_grant(8)(11)); 
+
+Arbiter_8_12 : Arbiter
+
+PORT MAP (Request => Request(204), North => south_2_north(7)(12), West => east_2_west(7)(11), P => Signal_priority(24), Fifo_full => Fifo_full(12),  
+South => south_2_north(8)(12), East => east_2_west(8)(12) , Grant => Signal_grant(8)(12)); 
+
+Arbiter_8_13 : Arbiter
+
+PORT MAP (Request => Request(189), North => south_2_north(7)(13), West => east_2_west(7)(12), P => Signal_priority(24), Fifo_full => Fifo_full(13),  
+South => south_2_north(8)(13), East => east_2_west(8)(13) , Grant => Signal_grant(8)(13)); 
+
+Arbiter_8_14 : Arbiter
+
+PORT MAP (Request => Request(174), North => south_2_north(7)(14), West => east_2_west(7)(13), P => Signal_priority(24), Fifo_full => Fifo_full(14),  
+South => south_2_north(8)(14), East => east_2_west(8)(14) , Grant => Signal_grant(8)(14)); 
+
+Arbiter_8_15 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(7)(15), West => east_2_west(7)(14), P => Signal_priority(24), Fifo_full => Fifo_full(15),  
+South => south_2_north(8)(15), East => east_2_west(8)(15) , Grant => Signal_grant(8)(15)); 
+
+Arbiter_8_16 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(7)(16), West => east_2_west(7)(15), P => Signal_priority(24), Fifo_full => Fifo_full(16),  
+South => south_2_north(8)(16), East => east_2_west(8)(16) , Grant => Signal_grant(8)(16)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(8)(1), West => east_2_west(8)(16), P => Signal_priority(23), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(23), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(23), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(23), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(23), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(23), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(23), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(23), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(23), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+Arbiter_9_10 : Arbiter
+
+PORT MAP (Request => Request(250), North => south_2_north(8)(10), West => east_2_west(8)(9), P => Signal_priority(23), Fifo_full => Fifo_full(10),  
+South => south_2_north(9)(10), East => east_2_west(9)(10) , Grant => Signal_grant(9)(10)); 
+
+Arbiter_9_11 : Arbiter
+
+PORT MAP (Request => Request(235), North => south_2_north(8)(11), West => east_2_west(8)(10), P => Signal_priority(23), Fifo_full => Fifo_full(11),  
+South => south_2_north(9)(11), East => east_2_west(9)(11) , Grant => Signal_grant(9)(11)); 
+
+Arbiter_9_12 : Arbiter
+
+PORT MAP (Request => Request(220), North => south_2_north(8)(12), West => east_2_west(8)(11), P => Signal_priority(23), Fifo_full => Fifo_full(12),  
+South => south_2_north(9)(12), East => east_2_west(9)(12) , Grant => Signal_grant(9)(12)); 
+
+Arbiter_9_13 : Arbiter
+
+PORT MAP (Request => Request(205), North => south_2_north(8)(13), West => east_2_west(8)(12), P => Signal_priority(23), Fifo_full => Fifo_full(13),  
+South => south_2_north(9)(13), East => east_2_west(9)(13) , Grant => Signal_grant(9)(13)); 
+
+Arbiter_9_14 : Arbiter
+
+PORT MAP (Request => Request(190), North => south_2_north(8)(14), West => east_2_west(8)(13), P => Signal_priority(23), Fifo_full => Fifo_full(14),  
+South => south_2_north(9)(14), East => east_2_west(9)(14) , Grant => Signal_grant(9)(14)); 
+
+Arbiter_9_15 : Arbiter
+
+PORT MAP (Request => Request(175), North => south_2_north(8)(15), West => east_2_west(8)(14), P => Signal_priority(23), Fifo_full => Fifo_full(15),  
+South => south_2_north(9)(15), East => east_2_west(9)(15) , Grant => Signal_grant(9)(15)); 
+
+Arbiter_9_16 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(8)(16), West => east_2_west(8)(15), P => Signal_priority(23), Fifo_full => Fifo_full(16),  
+South => south_2_north(9)(16), East => east_2_west(9)(16) , Grant => Signal_grant(9)(16)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(145), North => south_2_north(9)(1), West => east_2_west(9)(16), P => Signal_priority(22), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(22), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(22), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(22), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(22), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(22), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(22), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(22), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(22), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+Arbiter_10_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(9)(10), West => east_2_west(9)(9), P => Signal_priority(22), Fifo_full => Fifo_full(10),  
+South => south_2_north(10)(10), East => east_2_west(10)(10) , Grant => Signal_grant(10)(10)); 
+
+Arbiter_10_11 : Arbiter
+
+PORT MAP (Request => Request(251), North => south_2_north(9)(11), West => east_2_west(9)(10), P => Signal_priority(22), Fifo_full => Fifo_full(11),  
+South => south_2_north(10)(11), East => east_2_west(10)(11) , Grant => Signal_grant(10)(11)); 
+
+Arbiter_10_12 : Arbiter
+
+PORT MAP (Request => Request(236), North => south_2_north(9)(12), West => east_2_west(9)(11), P => Signal_priority(22), Fifo_full => Fifo_full(12),  
+South => south_2_north(10)(12), East => east_2_west(10)(12) , Grant => Signal_grant(10)(12)); 
+
+Arbiter_10_13 : Arbiter
+
+PORT MAP (Request => Request(221), North => south_2_north(9)(13), West => east_2_west(9)(12), P => Signal_priority(22), Fifo_full => Fifo_full(13),  
+South => south_2_north(10)(13), East => east_2_west(10)(13) , Grant => Signal_grant(10)(13)); 
+
+Arbiter_10_14 : Arbiter
+
+PORT MAP (Request => Request(206), North => south_2_north(9)(14), West => east_2_west(9)(13), P => Signal_priority(22), Fifo_full => Fifo_full(14),  
+South => south_2_north(10)(14), East => east_2_west(10)(14) , Grant => Signal_grant(10)(14)); 
+
+Arbiter_10_15 : Arbiter
+
+PORT MAP (Request => Request(191), North => south_2_north(9)(15), West => east_2_west(9)(14), P => Signal_priority(22), Fifo_full => Fifo_full(15),  
+South => south_2_north(10)(15), East => east_2_west(10)(15) , Grant => Signal_grant(10)(15)); 
+
+Arbiter_10_16 : Arbiter
+
+PORT MAP (Request => Request(176), North => south_2_north(9)(16), West => east_2_west(9)(15), P => Signal_priority(22), Fifo_full => Fifo_full(16),  
+South => south_2_north(10)(16), East => east_2_west(10)(16) , Grant => Signal_grant(10)(16)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(10)(1), West => east_2_west(10)(16), P => Signal_priority(21), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(146), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(21), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(21), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(21), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(21), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(21), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(21), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(21), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(21), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+Arbiter_11_10 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(10)(10), West => east_2_west(10)(9), P => Signal_priority(21), Fifo_full => Fifo_full(10),  
+South => south_2_north(11)(10), East => east_2_west(11)(10) , Grant => Signal_grant(11)(10)); 
+
+Arbiter_11_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(10)(11), West => east_2_west(10)(10), P => Signal_priority(21), Fifo_full => Fifo_full(11),  
+South => south_2_north(11)(11), East => east_2_west(11)(11) , Grant => Signal_grant(11)(11)); 
+
+Arbiter_11_12 : Arbiter
+
+PORT MAP (Request => Request(252), North => south_2_north(10)(12), West => east_2_west(10)(11), P => Signal_priority(21), Fifo_full => Fifo_full(12),  
+South => south_2_north(11)(12), East => east_2_west(11)(12) , Grant => Signal_grant(11)(12)); 
+
+Arbiter_11_13 : Arbiter
+
+PORT MAP (Request => Request(237), North => south_2_north(10)(13), West => east_2_west(10)(12), P => Signal_priority(21), Fifo_full => Fifo_full(13),  
+South => south_2_north(11)(13), East => east_2_west(11)(13) , Grant => Signal_grant(11)(13)); 
+
+Arbiter_11_14 : Arbiter
+
+PORT MAP (Request => Request(222), North => south_2_north(10)(14), West => east_2_west(10)(13), P => Signal_priority(21), Fifo_full => Fifo_full(14),  
+South => south_2_north(11)(14), East => east_2_west(11)(14) , Grant => Signal_grant(11)(14)); 
+
+Arbiter_11_15 : Arbiter
+
+PORT MAP (Request => Request(207), North => south_2_north(10)(15), West => east_2_west(10)(14), P => Signal_priority(21), Fifo_full => Fifo_full(15),  
+South => south_2_north(11)(15), East => east_2_west(11)(15) , Grant => Signal_grant(11)(15)); 
+
+Arbiter_11_16 : Arbiter
+
+PORT MAP (Request => Request(192), North => south_2_north(10)(16), West => east_2_west(10)(15), P => Signal_priority(21), Fifo_full => Fifo_full(16),  
+South => south_2_north(11)(16), East => east_2_west(11)(16) , Grant => Signal_grant(11)(16)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(177), North => south_2_north(11)(1), West => east_2_west(11)(16), P => Signal_priority(20), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(20), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(20), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(20), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(20), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(20), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(20), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(20), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(20), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+Arbiter_12_10 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(11)(10), West => east_2_west(11)(9), P => Signal_priority(20), Fifo_full => Fifo_full(10),  
+South => south_2_north(12)(10), East => east_2_west(12)(10) , Grant => Signal_grant(12)(10)); 
+
+Arbiter_12_11 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(11)(11), West => east_2_west(11)(10), P => Signal_priority(20), Fifo_full => Fifo_full(11),  
+South => south_2_north(12)(11), East => east_2_west(12)(11) , Grant => Signal_grant(12)(11)); 
+
+Arbiter_12_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(11)(12), West => east_2_west(11)(11), P => Signal_priority(20), Fifo_full => Fifo_full(12),  
+South => south_2_north(12)(12), East => east_2_west(12)(12) , Grant => Signal_grant(12)(12)); 
+
+Arbiter_12_13 : Arbiter
+
+PORT MAP (Request => Request(253), North => south_2_north(11)(13), West => east_2_west(11)(12), P => Signal_priority(20), Fifo_full => Fifo_full(13),  
+South => south_2_north(12)(13), East => east_2_west(12)(13) , Grant => Signal_grant(12)(13)); 
+
+Arbiter_12_14 : Arbiter
+
+PORT MAP (Request => Request(238), North => south_2_north(11)(14), West => east_2_west(11)(13), P => Signal_priority(20), Fifo_full => Fifo_full(14),  
+South => south_2_north(12)(14), East => east_2_west(12)(14) , Grant => Signal_grant(12)(14)); 
+
+Arbiter_12_15 : Arbiter
+
+PORT MAP (Request => Request(223), North => south_2_north(11)(15), West => east_2_west(11)(14), P => Signal_priority(20), Fifo_full => Fifo_full(15),  
+South => south_2_north(12)(15), East => east_2_west(12)(15) , Grant => Signal_grant(12)(15)); 
+
+Arbiter_12_16 : Arbiter
+
+PORT MAP (Request => Request(208), North => south_2_north(11)(16), West => east_2_west(11)(15), P => Signal_priority(20), Fifo_full => Fifo_full(16),  
+South => south_2_north(12)(16), East => east_2_west(12)(16) , Grant => Signal_grant(12)(16)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(193), North => south_2_north(12)(1), West => east_2_west(12)(16), P => Signal_priority(19), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(178), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(19), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(19), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(19), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(19), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(19), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(19), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(19), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(19), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+Arbiter_13_10 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(12)(10), West => east_2_west(12)(9), P => Signal_priority(19), Fifo_full => Fifo_full(10),  
+South => south_2_north(13)(10), East => east_2_west(13)(10) , Grant => Signal_grant(13)(10)); 
+
+Arbiter_13_11 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(12)(11), West => east_2_west(12)(10), P => Signal_priority(19), Fifo_full => Fifo_full(11),  
+South => south_2_north(13)(11), East => east_2_west(13)(11) , Grant => Signal_grant(13)(11)); 
+
+Arbiter_13_12 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(12)(12), West => east_2_west(12)(11), P => Signal_priority(19), Fifo_full => Fifo_full(12),  
+South => south_2_north(13)(12), East => east_2_west(13)(12) , Grant => Signal_grant(13)(12)); 
+
+Arbiter_13_13 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(12)(13), West => east_2_west(12)(12), P => Signal_priority(19), Fifo_full => Fifo_full(13),  
+South => south_2_north(13)(13), East => east_2_west(13)(13) , Grant => Signal_grant(13)(13)); 
+
+Arbiter_13_14 : Arbiter
+
+PORT MAP (Request => Request(254), North => south_2_north(12)(14), West => east_2_west(12)(13), P => Signal_priority(19), Fifo_full => Fifo_full(14),  
+South => south_2_north(13)(14), East => east_2_west(13)(14) , Grant => Signal_grant(13)(14)); 
+
+Arbiter_13_15 : Arbiter
+
+PORT MAP (Request => Request(239), North => south_2_north(12)(15), West => east_2_west(12)(14), P => Signal_priority(19), Fifo_full => Fifo_full(15),  
+South => south_2_north(13)(15), East => east_2_west(13)(15) , Grant => Signal_grant(13)(15)); 
+
+Arbiter_13_16 : Arbiter
+
+PORT MAP (Request => Request(224), North => south_2_north(12)(16), West => east_2_west(12)(15), P => Signal_priority(19), Fifo_full => Fifo_full(16),  
+South => south_2_north(13)(16), East => east_2_west(13)(16) , Grant => Signal_grant(13)(16)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(209), North => south_2_north(13)(1), West => east_2_west(13)(16), P => Signal_priority(18), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(194), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(18), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(179), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(18), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(18), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(18), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(18), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(18), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(18), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(18), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+Arbiter_14_10 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(13)(10), West => east_2_west(13)(9), P => Signal_priority(18), Fifo_full => Fifo_full(10),  
+South => south_2_north(14)(10), East => east_2_west(14)(10) , Grant => Signal_grant(14)(10)); 
+
+Arbiter_14_11 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(13)(11), West => east_2_west(13)(10), P => Signal_priority(18), Fifo_full => Fifo_full(11),  
+South => south_2_north(14)(11), East => east_2_west(14)(11) , Grant => Signal_grant(14)(11)); 
+
+Arbiter_14_12 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(13)(12), West => east_2_west(13)(11), P => Signal_priority(18), Fifo_full => Fifo_full(12),  
+South => south_2_north(14)(12), East => east_2_west(14)(12) , Grant => Signal_grant(14)(12)); 
+
+Arbiter_14_13 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(13)(13), West => east_2_west(13)(12), P => Signal_priority(18), Fifo_full => Fifo_full(13),  
+South => south_2_north(14)(13), East => east_2_west(14)(13) , Grant => Signal_grant(14)(13)); 
+
+Arbiter_14_14 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(13)(14), West => east_2_west(13)(13), P => Signal_priority(18), Fifo_full => Fifo_full(14),  
+South => south_2_north(14)(14), East => east_2_west(14)(14) , Grant => Signal_grant(14)(14)); 
+
+Arbiter_14_15 : Arbiter
+
+PORT MAP (Request => Request(255), North => south_2_north(13)(15), West => east_2_west(13)(14), P => Signal_priority(18), Fifo_full => Fifo_full(15),  
+South => south_2_north(14)(15), East => east_2_west(14)(15) , Grant => Signal_grant(14)(15)); 
+
+Arbiter_14_16 : Arbiter
+
+PORT MAP (Request => Request(240), North => south_2_north(13)(16), West => east_2_west(13)(15), P => Signal_priority(18), Fifo_full => Fifo_full(16),  
+South => south_2_north(14)(16), East => east_2_west(14)(16) , Grant => Signal_grant(14)(16)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(225), North => south_2_north(14)(1), West => east_2_west(14)(16), P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(210), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(195), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(180), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+Arbiter_15_10 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(14)(10), West => east_2_west(14)(9), P => Signal_priority(17), Fifo_full => Fifo_full(10),  
+South => south_2_north(15)(10), East => east_2_west(15)(10) , Grant => Signal_grant(15)(10)); 
+
+Arbiter_15_11 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(14)(11), West => east_2_west(14)(10), P => Signal_priority(17), Fifo_full => Fifo_full(11),  
+South => south_2_north(15)(11), East => east_2_west(15)(11) , Grant => Signal_grant(15)(11)); 
+
+Arbiter_15_12 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(14)(12), West => east_2_west(14)(11), P => Signal_priority(17), Fifo_full => Fifo_full(12),  
+South => south_2_north(15)(12), East => east_2_west(15)(12) , Grant => Signal_grant(15)(12)); 
+
+Arbiter_15_13 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(14)(13), West => east_2_west(14)(12), P => Signal_priority(17), Fifo_full => Fifo_full(13),  
+South => south_2_north(15)(13), East => east_2_west(15)(13) , Grant => Signal_grant(15)(13)); 
+
+Arbiter_15_14 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(14)(14), West => east_2_west(14)(13), P => Signal_priority(17), Fifo_full => Fifo_full(14),  
+South => south_2_north(15)(14), East => east_2_west(15)(14) , Grant => Signal_grant(15)(14)); 
+
+Arbiter_15_15 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(14)(15), West => east_2_west(14)(14), P => Signal_priority(17), Fifo_full => Fifo_full(15),  
+South => south_2_north(15)(15), East => east_2_west(15)(15) , Grant => Signal_grant(15)(15)); 
+
+Arbiter_15_16 : Arbiter
+
+PORT MAP (Request => Request(256), North => south_2_north(14)(16), West => east_2_west(14)(15), P => Signal_priority(17), Fifo_full => Fifo_full(16),  
+South => south_2_north(15)(16), East => east_2_west(15)(16) , Grant => Signal_grant(15)(16)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(241), North => south_2_north(15)(1), West => east_2_west(15)(16), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(226), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(211), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(196), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(181), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(166), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(151), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(136), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(121), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+Arbiter_16_10 : Arbiter
+
+PORT MAP (Request => Request(106), North => south_2_north(15)(10), West => east_2_west(15)(9), P => Signal_priority(16), Fifo_full => Fifo_full(10),  
+South => south_2_north(16)(10), East => east_2_west(16)(10) , Grant => Signal_grant(16)(10)); 
+
+Arbiter_16_11 : Arbiter
+
+PORT MAP (Request => Request(91), North => south_2_north(15)(11), West => east_2_west(15)(10), P => Signal_priority(16), Fifo_full => Fifo_full(11),  
+South => south_2_north(16)(11), East => east_2_west(16)(11) , Grant => Signal_grant(16)(11)); 
+
+Arbiter_16_12 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(15)(12), West => east_2_west(15)(11), P => Signal_priority(16), Fifo_full => Fifo_full(12),  
+South => south_2_north(16)(12), East => east_2_west(16)(12) , Grant => Signal_grant(16)(12)); 
+
+Arbiter_16_13 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(15)(13), West => east_2_west(15)(12), P => Signal_priority(16), Fifo_full => Fifo_full(13),  
+South => south_2_north(16)(13), East => east_2_west(16)(13) , Grant => Signal_grant(16)(13)); 
+
+Arbiter_16_14 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(15)(14), West => east_2_west(15)(13), P => Signal_priority(16), Fifo_full => Fifo_full(14),  
+South => south_2_north(16)(14), East => east_2_west(16)(14) , Grant => Signal_grant(16)(14)); 
+
+Arbiter_16_15 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(15)(15), West => east_2_west(15)(14), P => Signal_priority(16), Fifo_full => Fifo_full(15),  
+South => south_2_north(16)(15), East => east_2_west(16)(15) , Grant => Signal_grant(16)(15)); 
+
+Arbiter_16_16 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(15)(16), West => east_2_west(15)(15), P => Signal_priority(16), Fifo_full => Fifo_full(16),  
+South => south_2_north(16)(16), East => east_2_west(16)(16) , Grant => Signal_grant(16)(16)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(16)(1), West => east_2_west(16)(16), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(242), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(227), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(212), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(197), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(182), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(167), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(152), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(137), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+Arbiter_17_10 : Arbiter
+
+PORT MAP (Request => Request(122), North => south_2_north(16)(10), West => east_2_west(16)(9), P => Signal_priority(15), Fifo_full => Fifo_full(10),  
+South => south_2_north(17)(10), East => east_2_west(17)(10) , Grant => Signal_grant(17)(10)); 
+
+Arbiter_17_11 : Arbiter
+
+PORT MAP (Request => Request(107), North => south_2_north(16)(11), West => east_2_west(16)(10), P => Signal_priority(15), Fifo_full => Fifo_full(11),  
+South => south_2_north(17)(11), East => east_2_west(17)(11) , Grant => Signal_grant(17)(11)); 
+
+Arbiter_17_12 : Arbiter
+
+PORT MAP (Request => Request(92), North => south_2_north(16)(12), West => east_2_west(16)(11), P => Signal_priority(15), Fifo_full => Fifo_full(12),  
+South => south_2_north(17)(12), East => east_2_west(17)(12) , Grant => Signal_grant(17)(12)); 
+
+Arbiter_17_13 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(16)(13), West => east_2_west(16)(12), P => Signal_priority(15), Fifo_full => Fifo_full(13),  
+South => south_2_north(17)(13), East => east_2_west(17)(13) , Grant => Signal_grant(17)(13)); 
+
+Arbiter_17_14 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(16)(14), West => east_2_west(16)(13), P => Signal_priority(15), Fifo_full => Fifo_full(14),  
+South => south_2_north(17)(14), East => east_2_west(17)(14) , Grant => Signal_grant(17)(14)); 
+
+Arbiter_17_15 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(16)(15), West => east_2_west(16)(14), P => Signal_priority(15), Fifo_full => Fifo_full(15),  
+South => south_2_north(17)(15), East => east_2_west(17)(15) , Grant => Signal_grant(17)(15)); 
+
+Arbiter_17_16 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(16)(16), West => east_2_west(16)(15), P => Signal_priority(15), Fifo_full => Fifo_full(16),  
+South => south_2_north(17)(16), East => east_2_west(17)(16) , Grant => Signal_grant(17)(16)); 
+
+-------------------------- Diagonale n° 18 
+
+
+Arbiter_18_1 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(17)(1), West => east_2_west(17)(16), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(18)(1), East => east_2_west(18)(1) , Grant => Signal_grant(18)(1)); 
+
+Arbiter_18_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(17)(2), West => east_2_west(17)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(18)(2), East => east_2_west(18)(2) , Grant => Signal_grant(18)(2)); 
+
+Arbiter_18_3 : Arbiter
+
+PORT MAP (Request => Request(243), North => south_2_north(17)(3), West => east_2_west(17)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(18)(3), East => east_2_west(18)(3) , Grant => Signal_grant(18)(3)); 
+
+Arbiter_18_4 : Arbiter
+
+PORT MAP (Request => Request(228), North => south_2_north(17)(4), West => east_2_west(17)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(18)(4), East => east_2_west(18)(4) , Grant => Signal_grant(18)(4)); 
+
+Arbiter_18_5 : Arbiter
+
+PORT MAP (Request => Request(213), North => south_2_north(17)(5), West => east_2_west(17)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(18)(5), East => east_2_west(18)(5) , Grant => Signal_grant(18)(5)); 
+
+Arbiter_18_6 : Arbiter
+
+PORT MAP (Request => Request(198), North => south_2_north(17)(6), West => east_2_west(17)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(18)(6), East => east_2_west(18)(6) , Grant => Signal_grant(18)(6)); 
+
+Arbiter_18_7 : Arbiter
+
+PORT MAP (Request => Request(183), North => south_2_north(17)(7), West => east_2_west(17)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(18)(7), East => east_2_west(18)(7) , Grant => Signal_grant(18)(7)); 
+
+Arbiter_18_8 : Arbiter
+
+PORT MAP (Request => Request(168), North => south_2_north(17)(8), West => east_2_west(17)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(18)(8), East => east_2_west(18)(8) , Grant => Signal_grant(18)(8)); 
+
+Arbiter_18_9 : Arbiter
+
+PORT MAP (Request => Request(153), North => south_2_north(17)(9), West => east_2_west(17)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(18)(9), East => east_2_west(18)(9) , Grant => Signal_grant(18)(9)); 
+
+Arbiter_18_10 : Arbiter
+
+PORT MAP (Request => Request(138), North => south_2_north(17)(10), West => east_2_west(17)(9), P => Signal_priority(14), Fifo_full => Fifo_full(10),  
+South => south_2_north(18)(10), East => east_2_west(18)(10) , Grant => Signal_grant(18)(10)); 
+
+Arbiter_18_11 : Arbiter
+
+PORT MAP (Request => Request(123), North => south_2_north(17)(11), West => east_2_west(17)(10), P => Signal_priority(14), Fifo_full => Fifo_full(11),  
+South => south_2_north(18)(11), East => east_2_west(18)(11) , Grant => Signal_grant(18)(11)); 
+
+Arbiter_18_12 : Arbiter
+
+PORT MAP (Request => Request(108), North => south_2_north(17)(12), West => east_2_west(17)(11), P => Signal_priority(14), Fifo_full => Fifo_full(12),  
+South => south_2_north(18)(12), East => east_2_west(18)(12) , Grant => Signal_grant(18)(12)); 
+
+Arbiter_18_13 : Arbiter
+
+PORT MAP (Request => Request(93), North => south_2_north(17)(13), West => east_2_west(17)(12), P => Signal_priority(14), Fifo_full => Fifo_full(13),  
+South => south_2_north(18)(13), East => east_2_west(18)(13) , Grant => Signal_grant(18)(13)); 
+
+Arbiter_18_14 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(17)(14), West => east_2_west(17)(13), P => Signal_priority(14), Fifo_full => Fifo_full(14),  
+South => south_2_north(18)(14), East => east_2_west(18)(14) , Grant => Signal_grant(18)(14)); 
+
+Arbiter_18_15 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(17)(15), West => east_2_west(17)(14), P => Signal_priority(14), Fifo_full => Fifo_full(15),  
+South => south_2_north(18)(15), East => east_2_west(18)(15) , Grant => Signal_grant(18)(15)); 
+
+Arbiter_18_16 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(17)(16), West => east_2_west(17)(15), P => Signal_priority(14), Fifo_full => Fifo_full(16),  
+South => south_2_north(18)(16), East => east_2_west(18)(16) , Grant => Signal_grant(18)(16)); 
+
+-------------------------- Diagonale n° 19 
+
+
+Arbiter_19_1 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(18)(1), West => east_2_west(18)(16), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(19)(1), East => east_2_west(19)(1) , Grant => Signal_grant(19)(1)); 
+
+Arbiter_19_2 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(18)(2), West => east_2_west(18)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(19)(2), East => east_2_west(19)(2) , Grant => Signal_grant(19)(2)); 
+
+Arbiter_19_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(18)(3), West => east_2_west(18)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(19)(3), East => east_2_west(19)(3) , Grant => Signal_grant(19)(3)); 
+
+Arbiter_19_4 : Arbiter
+
+PORT MAP (Request => Request(244), North => south_2_north(18)(4), West => east_2_west(18)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(19)(4), East => east_2_west(19)(4) , Grant => Signal_grant(19)(4)); 
+
+Arbiter_19_5 : Arbiter
+
+PORT MAP (Request => Request(229), North => south_2_north(18)(5), West => east_2_west(18)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(19)(5), East => east_2_west(19)(5) , Grant => Signal_grant(19)(5)); 
+
+Arbiter_19_6 : Arbiter
+
+PORT MAP (Request => Request(214), North => south_2_north(18)(6), West => east_2_west(18)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(19)(6), East => east_2_west(19)(6) , Grant => Signal_grant(19)(6)); 
+
+Arbiter_19_7 : Arbiter
+
+PORT MAP (Request => Request(199), North => south_2_north(18)(7), West => east_2_west(18)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(19)(7), East => east_2_west(19)(7) , Grant => Signal_grant(19)(7)); 
+
+Arbiter_19_8 : Arbiter
+
+PORT MAP (Request => Request(184), North => south_2_north(18)(8), West => east_2_west(18)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(19)(8), East => east_2_west(19)(8) , Grant => Signal_grant(19)(8)); 
+
+Arbiter_19_9 : Arbiter
+
+PORT MAP (Request => Request(169), North => south_2_north(18)(9), West => east_2_west(18)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(19)(9), East => east_2_west(19)(9) , Grant => Signal_grant(19)(9)); 
+
+Arbiter_19_10 : Arbiter
+
+PORT MAP (Request => Request(154), North => south_2_north(18)(10), West => east_2_west(18)(9), P => Signal_priority(13), Fifo_full => Fifo_full(10),  
+South => south_2_north(19)(10), East => east_2_west(19)(10) , Grant => Signal_grant(19)(10)); 
+
+Arbiter_19_11 : Arbiter
+
+PORT MAP (Request => Request(139), North => south_2_north(18)(11), West => east_2_west(18)(10), P => Signal_priority(13), Fifo_full => Fifo_full(11),  
+South => south_2_north(19)(11), East => east_2_west(19)(11) , Grant => Signal_grant(19)(11)); 
+
+Arbiter_19_12 : Arbiter
+
+PORT MAP (Request => Request(124), North => south_2_north(18)(12), West => east_2_west(18)(11), P => Signal_priority(13), Fifo_full => Fifo_full(12),  
+South => south_2_north(19)(12), East => east_2_west(19)(12) , Grant => Signal_grant(19)(12)); 
+
+Arbiter_19_13 : Arbiter
+
+PORT MAP (Request => Request(109), North => south_2_north(18)(13), West => east_2_west(18)(12), P => Signal_priority(13), Fifo_full => Fifo_full(13),  
+South => south_2_north(19)(13), East => east_2_west(19)(13) , Grant => Signal_grant(19)(13)); 
+
+Arbiter_19_14 : Arbiter
+
+PORT MAP (Request => Request(94), North => south_2_north(18)(14), West => east_2_west(18)(13), P => Signal_priority(13), Fifo_full => Fifo_full(14),  
+South => south_2_north(19)(14), East => east_2_west(19)(14) , Grant => Signal_grant(19)(14)); 
+
+Arbiter_19_15 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(18)(15), West => east_2_west(18)(14), P => Signal_priority(13), Fifo_full => Fifo_full(15),  
+South => south_2_north(19)(15), East => east_2_west(19)(15) , Grant => Signal_grant(19)(15)); 
+
+Arbiter_19_16 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(18)(16), West => east_2_west(18)(15), P => Signal_priority(13), Fifo_full => Fifo_full(16),  
+South => south_2_north(19)(16), East => east_2_west(19)(16) , Grant => Signal_grant(19)(16)); 
+
+-------------------------- Diagonale n° 20 
+
+
+Arbiter_20_1 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(19)(1), West => east_2_west(19)(16), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(20)(1), East => east_2_west(20)(1) , Grant => Signal_grant(20)(1)); 
+
+Arbiter_20_2 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(19)(2), West => east_2_west(19)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(20)(2), East => east_2_west(20)(2) , Grant => Signal_grant(20)(2)); 
+
+Arbiter_20_3 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(19)(3), West => east_2_west(19)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(20)(3), East => east_2_west(20)(3) , Grant => Signal_grant(20)(3)); 
+
+Arbiter_20_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(19)(4), West => east_2_west(19)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(20)(4), East => east_2_west(20)(4) , Grant => Signal_grant(20)(4)); 
+
+Arbiter_20_5 : Arbiter
+
+PORT MAP (Request => Request(245), North => south_2_north(19)(5), West => east_2_west(19)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(20)(5), East => east_2_west(20)(5) , Grant => Signal_grant(20)(5)); 
+
+Arbiter_20_6 : Arbiter
+
+PORT MAP (Request => Request(230), North => south_2_north(19)(6), West => east_2_west(19)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(20)(6), East => east_2_west(20)(6) , Grant => Signal_grant(20)(6)); 
+
+Arbiter_20_7 : Arbiter
+
+PORT MAP (Request => Request(215), North => south_2_north(19)(7), West => east_2_west(19)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(20)(7), East => east_2_west(20)(7) , Grant => Signal_grant(20)(7)); 
+
+Arbiter_20_8 : Arbiter
+
+PORT MAP (Request => Request(200), North => south_2_north(19)(8), West => east_2_west(19)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(20)(8), East => east_2_west(20)(8) , Grant => Signal_grant(20)(8)); 
+
+Arbiter_20_9 : Arbiter
+
+PORT MAP (Request => Request(185), North => south_2_north(19)(9), West => east_2_west(19)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(20)(9), East => east_2_west(20)(9) , Grant => Signal_grant(20)(9)); 
+
+Arbiter_20_10 : Arbiter
+
+PORT MAP (Request => Request(170), North => south_2_north(19)(10), West => east_2_west(19)(9), P => Signal_priority(12), Fifo_full => Fifo_full(10),  
+South => south_2_north(20)(10), East => east_2_west(20)(10) , Grant => Signal_grant(20)(10)); 
+
+Arbiter_20_11 : Arbiter
+
+PORT MAP (Request => Request(155), North => south_2_north(19)(11), West => east_2_west(19)(10), P => Signal_priority(12), Fifo_full => Fifo_full(11),  
+South => south_2_north(20)(11), East => east_2_west(20)(11) , Grant => Signal_grant(20)(11)); 
+
+Arbiter_20_12 : Arbiter
+
+PORT MAP (Request => Request(140), North => south_2_north(19)(12), West => east_2_west(19)(11), P => Signal_priority(12), Fifo_full => Fifo_full(12),  
+South => south_2_north(20)(12), East => east_2_west(20)(12) , Grant => Signal_grant(20)(12)); 
+
+Arbiter_20_13 : Arbiter
+
+PORT MAP (Request => Request(125), North => south_2_north(19)(13), West => east_2_west(19)(12), P => Signal_priority(12), Fifo_full => Fifo_full(13),  
+South => south_2_north(20)(13), East => east_2_west(20)(13) , Grant => Signal_grant(20)(13)); 
+
+Arbiter_20_14 : Arbiter
+
+PORT MAP (Request => Request(110), North => south_2_north(19)(14), West => east_2_west(19)(13), P => Signal_priority(12), Fifo_full => Fifo_full(14),  
+South => south_2_north(20)(14), East => east_2_west(20)(14) , Grant => Signal_grant(20)(14)); 
+
+Arbiter_20_15 : Arbiter
+
+PORT MAP (Request => Request(95), North => south_2_north(19)(15), West => east_2_west(19)(14), P => Signal_priority(12), Fifo_full => Fifo_full(15),  
+South => south_2_north(20)(15), East => east_2_west(20)(15) , Grant => Signal_grant(20)(15)); 
+
+Arbiter_20_16 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(19)(16), West => east_2_west(19)(15), P => Signal_priority(12), Fifo_full => Fifo_full(16),  
+South => south_2_north(20)(16), East => east_2_west(20)(16) , Grant => Signal_grant(20)(16)); 
+
+-------------------------- Diagonale n° 21 
+
+
+Arbiter_21_1 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(20)(1), West => east_2_west(20)(16), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(21)(1), East => east_2_west(21)(1) , Grant => Signal_grant(21)(1)); 
+
+Arbiter_21_2 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(20)(2), West => east_2_west(20)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(21)(2), East => east_2_west(21)(2) , Grant => Signal_grant(21)(2)); 
+
+Arbiter_21_3 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(20)(3), West => east_2_west(20)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(21)(3), East => east_2_west(21)(3) , Grant => Signal_grant(21)(3)); 
+
+Arbiter_21_4 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(20)(4), West => east_2_west(20)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(21)(4), East => east_2_west(21)(4) , Grant => Signal_grant(21)(4)); 
+
+Arbiter_21_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(20)(5), West => east_2_west(20)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(21)(5), East => east_2_west(21)(5) , Grant => Signal_grant(21)(5)); 
+
+Arbiter_21_6 : Arbiter
+
+PORT MAP (Request => Request(246), North => south_2_north(20)(6), West => east_2_west(20)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(21)(6), East => east_2_west(21)(6) , Grant => Signal_grant(21)(6)); 
+
+Arbiter_21_7 : Arbiter
+
+PORT MAP (Request => Request(231), North => south_2_north(20)(7), West => east_2_west(20)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(21)(7), East => east_2_west(21)(7) , Grant => Signal_grant(21)(7)); 
+
+Arbiter_21_8 : Arbiter
+
+PORT MAP (Request => Request(216), North => south_2_north(20)(8), West => east_2_west(20)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(21)(8), East => east_2_west(21)(8) , Grant => Signal_grant(21)(8)); 
+
+Arbiter_21_9 : Arbiter
+
+PORT MAP (Request => Request(201), North => south_2_north(20)(9), West => east_2_west(20)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(21)(9), East => east_2_west(21)(9) , Grant => Signal_grant(21)(9)); 
+
+Arbiter_21_10 : Arbiter
+
+PORT MAP (Request => Request(186), North => south_2_north(20)(10), West => east_2_west(20)(9), P => Signal_priority(11), Fifo_full => Fifo_full(10),  
+South => south_2_north(21)(10), East => east_2_west(21)(10) , Grant => Signal_grant(21)(10)); 
+
+Arbiter_21_11 : Arbiter
+
+PORT MAP (Request => Request(171), North => south_2_north(20)(11), West => east_2_west(20)(10), P => Signal_priority(11), Fifo_full => Fifo_full(11),  
+South => south_2_north(21)(11), East => east_2_west(21)(11) , Grant => Signal_grant(21)(11)); 
+
+Arbiter_21_12 : Arbiter
+
+PORT MAP (Request => Request(156), North => south_2_north(20)(12), West => east_2_west(20)(11), P => Signal_priority(11), Fifo_full => Fifo_full(12),  
+South => south_2_north(21)(12), East => east_2_west(21)(12) , Grant => Signal_grant(21)(12)); 
+
+Arbiter_21_13 : Arbiter
+
+PORT MAP (Request => Request(141), North => south_2_north(20)(13), West => east_2_west(20)(12), P => Signal_priority(11), Fifo_full => Fifo_full(13),  
+South => south_2_north(21)(13), East => east_2_west(21)(13) , Grant => Signal_grant(21)(13)); 
+
+Arbiter_21_14 : Arbiter
+
+PORT MAP (Request => Request(126), North => south_2_north(20)(14), West => east_2_west(20)(13), P => Signal_priority(11), Fifo_full => Fifo_full(14),  
+South => south_2_north(21)(14), East => east_2_west(21)(14) , Grant => Signal_grant(21)(14)); 
+
+Arbiter_21_15 : Arbiter
+
+PORT MAP (Request => Request(111), North => south_2_north(20)(15), West => east_2_west(20)(14), P => Signal_priority(11), Fifo_full => Fifo_full(15),  
+South => south_2_north(21)(15), East => east_2_west(21)(15) , Grant => Signal_grant(21)(15)); 
+
+Arbiter_21_16 : Arbiter
+
+PORT MAP (Request => Request(96), North => south_2_north(20)(16), West => east_2_west(20)(15), P => Signal_priority(11), Fifo_full => Fifo_full(16),  
+South => south_2_north(21)(16), East => east_2_west(21)(16) , Grant => Signal_grant(21)(16)); 
+
+-------------------------- Diagonale n° 22 
+
+
+Arbiter_22_1 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(21)(1), West => east_2_west(21)(16), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(22)(1), East => east_2_west(22)(1) , Grant => Signal_grant(22)(1)); 
+
+Arbiter_22_2 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(21)(2), West => east_2_west(21)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(22)(2), East => east_2_west(22)(2) , Grant => Signal_grant(22)(2)); 
+
+Arbiter_22_3 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(21)(3), West => east_2_west(21)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(22)(3), East => east_2_west(22)(3) , Grant => Signal_grant(22)(3)); 
+
+Arbiter_22_4 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(21)(4), West => east_2_west(21)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(22)(4), East => east_2_west(22)(4) , Grant => Signal_grant(22)(4)); 
+
+Arbiter_22_5 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(21)(5), West => east_2_west(21)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(22)(5), East => east_2_west(22)(5) , Grant => Signal_grant(22)(5)); 
+
+Arbiter_22_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(21)(6), West => east_2_west(21)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(22)(6), East => east_2_west(22)(6) , Grant => Signal_grant(22)(6)); 
+
+Arbiter_22_7 : Arbiter
+
+PORT MAP (Request => Request(247), North => south_2_north(21)(7), West => east_2_west(21)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(22)(7), East => east_2_west(22)(7) , Grant => Signal_grant(22)(7)); 
+
+Arbiter_22_8 : Arbiter
+
+PORT MAP (Request => Request(232), North => south_2_north(21)(8), West => east_2_west(21)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(22)(8), East => east_2_west(22)(8) , Grant => Signal_grant(22)(8)); 
+
+Arbiter_22_9 : Arbiter
+
+PORT MAP (Request => Request(217), North => south_2_north(21)(9), West => east_2_west(21)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(22)(9), East => east_2_west(22)(9) , Grant => Signal_grant(22)(9)); 
+
+Arbiter_22_10 : Arbiter
+
+PORT MAP (Request => Request(202), North => south_2_north(21)(10), West => east_2_west(21)(9), P => Signal_priority(10), Fifo_full => Fifo_full(10),  
+South => south_2_north(22)(10), East => east_2_west(22)(10) , Grant => Signal_grant(22)(10)); 
+
+Arbiter_22_11 : Arbiter
+
+PORT MAP (Request => Request(187), North => south_2_north(21)(11), West => east_2_west(21)(10), P => Signal_priority(10), Fifo_full => Fifo_full(11),  
+South => south_2_north(22)(11), East => east_2_west(22)(11) , Grant => Signal_grant(22)(11)); 
+
+Arbiter_22_12 : Arbiter
+
+PORT MAP (Request => Request(172), North => south_2_north(21)(12), West => east_2_west(21)(11), P => Signal_priority(10), Fifo_full => Fifo_full(12),  
+South => south_2_north(22)(12), East => east_2_west(22)(12) , Grant => Signal_grant(22)(12)); 
+
+Arbiter_22_13 : Arbiter
+
+PORT MAP (Request => Request(157), North => south_2_north(21)(13), West => east_2_west(21)(12), P => Signal_priority(10), Fifo_full => Fifo_full(13),  
+South => south_2_north(22)(13), East => east_2_west(22)(13) , Grant => Signal_grant(22)(13)); 
+
+Arbiter_22_14 : Arbiter
+
+PORT MAP (Request => Request(142), North => south_2_north(21)(14), West => east_2_west(21)(13), P => Signal_priority(10), Fifo_full => Fifo_full(14),  
+South => south_2_north(22)(14), East => east_2_west(22)(14) , Grant => Signal_grant(22)(14)); 
+
+Arbiter_22_15 : Arbiter
+
+PORT MAP (Request => Request(127), North => south_2_north(21)(15), West => east_2_west(21)(14), P => Signal_priority(10), Fifo_full => Fifo_full(15),  
+South => south_2_north(22)(15), East => east_2_west(22)(15) , Grant => Signal_grant(22)(15)); 
+
+Arbiter_22_16 : Arbiter
+
+PORT MAP (Request => Request(112), North => south_2_north(21)(16), West => east_2_west(21)(15), P => Signal_priority(10), Fifo_full => Fifo_full(16),  
+South => south_2_north(22)(16), East => east_2_west(22)(16) , Grant => Signal_grant(22)(16)); 
+
+-------------------------- Diagonale n° 23 
+
+
+Arbiter_23_1 : Arbiter
+
+PORT MAP (Request => Request(97), North => south_2_north(22)(1), West => east_2_west(22)(16), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(23)(1), East => east_2_west(23)(1) , Grant => Signal_grant(23)(1)); 
+
+Arbiter_23_2 : Arbiter
+
+PORT MAP (Request => Request(82), North => south_2_north(22)(2), West => east_2_west(22)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(23)(2), East => east_2_west(23)(2) , Grant => Signal_grant(23)(2)); 
+
+Arbiter_23_3 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(22)(3), West => east_2_west(22)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(23)(3), East => east_2_west(23)(3) , Grant => Signal_grant(23)(3)); 
+
+Arbiter_23_4 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(22)(4), West => east_2_west(22)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(23)(4), East => east_2_west(23)(4) , Grant => Signal_grant(23)(4)); 
+
+Arbiter_23_5 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(22)(5), West => east_2_west(22)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(23)(5), East => east_2_west(23)(5) , Grant => Signal_grant(23)(5)); 
+
+Arbiter_23_6 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(22)(6), West => east_2_west(22)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(23)(6), East => east_2_west(23)(6) , Grant => Signal_grant(23)(6)); 
+
+Arbiter_23_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(22)(7), West => east_2_west(22)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(23)(7), East => east_2_west(23)(7) , Grant => Signal_grant(23)(7)); 
+
+Arbiter_23_8 : Arbiter
+
+PORT MAP (Request => Request(248), North => south_2_north(22)(8), West => east_2_west(22)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(23)(8), East => east_2_west(23)(8) , Grant => Signal_grant(23)(8)); 
+
+Arbiter_23_9 : Arbiter
+
+PORT MAP (Request => Request(233), North => south_2_north(22)(9), West => east_2_west(22)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(23)(9), East => east_2_west(23)(9) , Grant => Signal_grant(23)(9)); 
+
+Arbiter_23_10 : Arbiter
+
+PORT MAP (Request => Request(218), North => south_2_north(22)(10), West => east_2_west(22)(9), P => Signal_priority(9), Fifo_full => Fifo_full(10),  
+South => south_2_north(23)(10), East => east_2_west(23)(10) , Grant => Signal_grant(23)(10)); 
+
+Arbiter_23_11 : Arbiter
+
+PORT MAP (Request => Request(203), North => south_2_north(22)(11), West => east_2_west(22)(10), P => Signal_priority(9), Fifo_full => Fifo_full(11),  
+South => south_2_north(23)(11), East => east_2_west(23)(11) , Grant => Signal_grant(23)(11)); 
+
+Arbiter_23_12 : Arbiter
+
+PORT MAP (Request => Request(188), North => south_2_north(22)(12), West => east_2_west(22)(11), P => Signal_priority(9), Fifo_full => Fifo_full(12),  
+South => south_2_north(23)(12), East => east_2_west(23)(12) , Grant => Signal_grant(23)(12)); 
+
+Arbiter_23_13 : Arbiter
+
+PORT MAP (Request => Request(173), North => south_2_north(22)(13), West => east_2_west(22)(12), P => Signal_priority(9), Fifo_full => Fifo_full(13),  
+South => south_2_north(23)(13), East => east_2_west(23)(13) , Grant => Signal_grant(23)(13)); 
+
+Arbiter_23_14 : Arbiter
+
+PORT MAP (Request => Request(158), North => south_2_north(22)(14), West => east_2_west(22)(13), P => Signal_priority(9), Fifo_full => Fifo_full(14),  
+South => south_2_north(23)(14), East => east_2_west(23)(14) , Grant => Signal_grant(23)(14)); 
+
+Arbiter_23_15 : Arbiter
+
+PORT MAP (Request => Request(143), North => south_2_north(22)(15), West => east_2_west(22)(14), P => Signal_priority(9), Fifo_full => Fifo_full(15),  
+South => south_2_north(23)(15), East => east_2_west(23)(15) , Grant => Signal_grant(23)(15)); 
+
+Arbiter_23_16 : Arbiter
+
+PORT MAP (Request => Request(128), North => south_2_north(22)(16), West => east_2_west(22)(15), P => Signal_priority(9), Fifo_full => Fifo_full(16),  
+South => south_2_north(23)(16), East => east_2_west(23)(16) , Grant => Signal_grant(23)(16)); 
+
+-------------------------- Diagonale n° 24 
+
+
+Arbiter_24_1 : Arbiter
+
+PORT MAP (Request => Request(113), North => south_2_north(23)(1), West => east_2_west(23)(16), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(24)(1), East => east_2_west(24)(1) , Grant => Signal_grant(24)(1)); 
+
+Arbiter_24_2 : Arbiter
+
+PORT MAP (Request => Request(98), North => south_2_north(23)(2), West => east_2_west(23)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(24)(2), East => east_2_west(24)(2) , Grant => Signal_grant(24)(2)); 
+
+Arbiter_24_3 : Arbiter
+
+PORT MAP (Request => Request(83), North => south_2_north(23)(3), West => east_2_west(23)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(24)(3), East => east_2_west(24)(3) , Grant => Signal_grant(24)(3)); 
+
+Arbiter_24_4 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(23)(4), West => east_2_west(23)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(24)(4), East => east_2_west(24)(4) , Grant => Signal_grant(24)(4)); 
+
+Arbiter_24_5 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(23)(5), West => east_2_west(23)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(24)(5), East => east_2_west(24)(5) , Grant => Signal_grant(24)(5)); 
+
+Arbiter_24_6 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(23)(6), West => east_2_west(23)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(24)(6), East => east_2_west(24)(6) , Grant => Signal_grant(24)(6)); 
+
+Arbiter_24_7 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(23)(7), West => east_2_west(23)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(24)(7), East => east_2_west(24)(7) , Grant => Signal_grant(24)(7)); 
+
+Arbiter_24_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(23)(8), West => east_2_west(23)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(24)(8), East => east_2_west(24)(8) , Grant => Signal_grant(24)(8)); 
+
+Arbiter_24_9 : Arbiter
+
+PORT MAP (Request => Request(249), North => south_2_north(23)(9), West => east_2_west(23)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(24)(9), East => east_2_west(24)(9) , Grant => Signal_grant(24)(9)); 
+
+Arbiter_24_10 : Arbiter
+
+PORT MAP (Request => Request(234), North => south_2_north(23)(10), West => east_2_west(23)(9), P => Signal_priority(8), Fifo_full => Fifo_full(10),  
+South => south_2_north(24)(10), East => east_2_west(24)(10) , Grant => Signal_grant(24)(10)); 
+
+Arbiter_24_11 : Arbiter
+
+PORT MAP (Request => Request(219), North => south_2_north(23)(11), West => east_2_west(23)(10), P => Signal_priority(8), Fifo_full => Fifo_full(11),  
+South => south_2_north(24)(11), East => east_2_west(24)(11) , Grant => Signal_grant(24)(11)); 
+
+Arbiter_24_12 : Arbiter
+
+PORT MAP (Request => Request(204), North => south_2_north(23)(12), West => east_2_west(23)(11), P => Signal_priority(8), Fifo_full => Fifo_full(12),  
+South => south_2_north(24)(12), East => east_2_west(24)(12) , Grant => Signal_grant(24)(12)); 
+
+Arbiter_24_13 : Arbiter
+
+PORT MAP (Request => Request(189), North => south_2_north(23)(13), West => east_2_west(23)(12), P => Signal_priority(8), Fifo_full => Fifo_full(13),  
+South => south_2_north(24)(13), East => east_2_west(24)(13) , Grant => Signal_grant(24)(13)); 
+
+Arbiter_24_14 : Arbiter
+
+PORT MAP (Request => Request(174), North => south_2_north(23)(14), West => east_2_west(23)(13), P => Signal_priority(8), Fifo_full => Fifo_full(14),  
+South => south_2_north(24)(14), East => east_2_west(24)(14) , Grant => Signal_grant(24)(14)); 
+
+Arbiter_24_15 : Arbiter
+
+PORT MAP (Request => Request(159), North => south_2_north(23)(15), West => east_2_west(23)(14), P => Signal_priority(8), Fifo_full => Fifo_full(15),  
+South => south_2_north(24)(15), East => east_2_west(24)(15) , Grant => Signal_grant(24)(15)); 
+
+Arbiter_24_16 : Arbiter
+
+PORT MAP (Request => Request(144), North => south_2_north(23)(16), West => east_2_west(23)(15), P => Signal_priority(8), Fifo_full => Fifo_full(16),  
+South => south_2_north(24)(16), East => east_2_west(24)(16) , Grant => Signal_grant(24)(16)); 
+
+-------------------------- Diagonale n° 25 
+
+
+Arbiter_25_1 : Arbiter
+
+PORT MAP (Request => Request(129), North => south_2_north(24)(1), West => east_2_west(24)(16), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(25)(1), East => east_2_west(25)(1) , Grant => Signal_grant(25)(1)); 
+
+Arbiter_25_2 : Arbiter
+
+PORT MAP (Request => Request(114), North => south_2_north(24)(2), West => east_2_west(24)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(25)(2), East => east_2_west(25)(2) , Grant => Signal_grant(25)(2)); 
+
+Arbiter_25_3 : Arbiter
+
+PORT MAP (Request => Request(99), North => south_2_north(24)(3), West => east_2_west(24)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(25)(3), East => east_2_west(25)(3) , Grant => Signal_grant(25)(3)); 
+
+Arbiter_25_4 : Arbiter
+
+PORT MAP (Request => Request(84), North => south_2_north(24)(4), West => east_2_west(24)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(25)(4), East => east_2_west(25)(4) , Grant => Signal_grant(25)(4)); 
+
+Arbiter_25_5 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(24)(5), West => east_2_west(24)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(25)(5), East => east_2_west(25)(5) , Grant => Signal_grant(25)(5)); 
+
+Arbiter_25_6 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(24)(6), West => east_2_west(24)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(25)(6), East => east_2_west(25)(6) , Grant => Signal_grant(25)(6)); 
+
+Arbiter_25_7 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(24)(7), West => east_2_west(24)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(25)(7), East => east_2_west(25)(7) , Grant => Signal_grant(25)(7)); 
+
+Arbiter_25_8 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(24)(8), West => east_2_west(24)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(25)(8), East => east_2_west(25)(8) , Grant => Signal_grant(25)(8)); 
+
+Arbiter_25_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(24)(9), West => east_2_west(24)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(25)(9), East => east_2_west(25)(9) , Grant => Signal_grant(25)(9)); 
+
+Arbiter_25_10 : Arbiter
+
+PORT MAP (Request => Request(250), North => south_2_north(24)(10), West => east_2_west(24)(9), P => Signal_priority(7), Fifo_full => Fifo_full(10),  
+South => south_2_north(25)(10), East => east_2_west(25)(10) , Grant => Signal_grant(25)(10)); 
+
+Arbiter_25_11 : Arbiter
+
+PORT MAP (Request => Request(235), North => south_2_north(24)(11), West => east_2_west(24)(10), P => Signal_priority(7), Fifo_full => Fifo_full(11),  
+South => south_2_north(25)(11), East => east_2_west(25)(11) , Grant => Signal_grant(25)(11)); 
+
+Arbiter_25_12 : Arbiter
+
+PORT MAP (Request => Request(220), North => south_2_north(24)(12), West => east_2_west(24)(11), P => Signal_priority(7), Fifo_full => Fifo_full(12),  
+South => south_2_north(25)(12), East => east_2_west(25)(12) , Grant => Signal_grant(25)(12)); 
+
+Arbiter_25_13 : Arbiter
+
+PORT MAP (Request => Request(205), North => south_2_north(24)(13), West => east_2_west(24)(12), P => Signal_priority(7), Fifo_full => Fifo_full(13),  
+South => south_2_north(25)(13), East => east_2_west(25)(13) , Grant => Signal_grant(25)(13)); 
+
+Arbiter_25_14 : Arbiter
+
+PORT MAP (Request => Request(190), North => south_2_north(24)(14), West => east_2_west(24)(13), P => Signal_priority(7), Fifo_full => Fifo_full(14),  
+South => south_2_north(25)(14), East => east_2_west(25)(14) , Grant => Signal_grant(25)(14)); 
+
+Arbiter_25_15 : Arbiter
+
+PORT MAP (Request => Request(175), North => south_2_north(24)(15), West => east_2_west(24)(14), P => Signal_priority(7), Fifo_full => Fifo_full(15),  
+South => south_2_north(25)(15), East => east_2_west(25)(15) , Grant => Signal_grant(25)(15)); 
+
+Arbiter_25_16 : Arbiter
+
+PORT MAP (Request => Request(160), North => south_2_north(24)(16), West => east_2_west(24)(15), P => Signal_priority(7), Fifo_full => Fifo_full(16),  
+South => south_2_north(25)(16), East => east_2_west(25)(16) , Grant => Signal_grant(25)(16)); 
+
+-------------------------- Diagonale n° 26 
+
+
+Arbiter_26_1 : Arbiter
+
+PORT MAP (Request => Request(145), North => south_2_north(25)(1), West => east_2_west(25)(16), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(26)(1), East => east_2_west(26)(1) , Grant => Signal_grant(26)(1)); 
+
+Arbiter_26_2 : Arbiter
+
+PORT MAP (Request => Request(130), North => south_2_north(25)(2), West => east_2_west(25)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(26)(2), East => east_2_west(26)(2) , Grant => Signal_grant(26)(2)); 
+
+Arbiter_26_3 : Arbiter
+
+PORT MAP (Request => Request(115), North => south_2_north(25)(3), West => east_2_west(25)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(26)(3), East => east_2_west(26)(3) , Grant => Signal_grant(26)(3)); 
+
+Arbiter_26_4 : Arbiter
+
+PORT MAP (Request => Request(100), North => south_2_north(25)(4), West => east_2_west(25)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(26)(4), East => east_2_west(26)(4) , Grant => Signal_grant(26)(4)); 
+
+Arbiter_26_5 : Arbiter
+
+PORT MAP (Request => Request(85), North => south_2_north(25)(5), West => east_2_west(25)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(26)(5), East => east_2_west(26)(5) , Grant => Signal_grant(26)(5)); 
+
+Arbiter_26_6 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(25)(6), West => east_2_west(25)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(26)(6), East => east_2_west(26)(6) , Grant => Signal_grant(26)(6)); 
+
+Arbiter_26_7 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(25)(7), West => east_2_west(25)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(26)(7), East => east_2_west(26)(7) , Grant => Signal_grant(26)(7)); 
+
+Arbiter_26_8 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(25)(8), West => east_2_west(25)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(26)(8), East => east_2_west(26)(8) , Grant => Signal_grant(26)(8)); 
+
+Arbiter_26_9 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(25)(9), West => east_2_west(25)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(26)(9), East => east_2_west(26)(9) , Grant => Signal_grant(26)(9)); 
+
+Arbiter_26_10 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(25)(10), West => east_2_west(25)(9), P => Signal_priority(6), Fifo_full => Fifo_full(10),  
+South => south_2_north(26)(10), East => east_2_west(26)(10) , Grant => Signal_grant(26)(10)); 
+
+Arbiter_26_11 : Arbiter
+
+PORT MAP (Request => Request(251), North => south_2_north(25)(11), West => east_2_west(25)(10), P => Signal_priority(6), Fifo_full => Fifo_full(11),  
+South => south_2_north(26)(11), East => east_2_west(26)(11) , Grant => Signal_grant(26)(11)); 
+
+Arbiter_26_12 : Arbiter
+
+PORT MAP (Request => Request(236), North => south_2_north(25)(12), West => east_2_west(25)(11), P => Signal_priority(6), Fifo_full => Fifo_full(12),  
+South => south_2_north(26)(12), East => east_2_west(26)(12) , Grant => Signal_grant(26)(12)); 
+
+Arbiter_26_13 : Arbiter
+
+PORT MAP (Request => Request(221), North => south_2_north(25)(13), West => east_2_west(25)(12), P => Signal_priority(6), Fifo_full => Fifo_full(13),  
+South => south_2_north(26)(13), East => east_2_west(26)(13) , Grant => Signal_grant(26)(13)); 
+
+Arbiter_26_14 : Arbiter
+
+PORT MAP (Request => Request(206), North => south_2_north(25)(14), West => east_2_west(25)(13), P => Signal_priority(6), Fifo_full => Fifo_full(14),  
+South => south_2_north(26)(14), East => east_2_west(26)(14) , Grant => Signal_grant(26)(14)); 
+
+Arbiter_26_15 : Arbiter
+
+PORT MAP (Request => Request(191), North => south_2_north(25)(15), West => east_2_west(25)(14), P => Signal_priority(6), Fifo_full => Fifo_full(15),  
+South => south_2_north(26)(15), East => east_2_west(26)(15) , Grant => Signal_grant(26)(15)); 
+
+Arbiter_26_16 : Arbiter
+
+PORT MAP (Request => Request(176), North => south_2_north(25)(16), West => east_2_west(25)(15), P => Signal_priority(6), Fifo_full => Fifo_full(16),  
+South => south_2_north(26)(16), East => east_2_west(26)(16) , Grant => Signal_grant(26)(16)); 
+
+-------------------------- Diagonale n° 27 
+
+
+Arbiter_27_1 : Arbiter
+
+PORT MAP (Request => Request(161), North => south_2_north(26)(1), West => east_2_west(26)(16), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(27)(1), East => east_2_west(27)(1) , Grant => Signal_grant(27)(1)); 
+
+Arbiter_27_2 : Arbiter
+
+PORT MAP (Request => Request(146), North => south_2_north(26)(2), West => east_2_west(26)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(27)(2), East => east_2_west(27)(2) , Grant => Signal_grant(27)(2)); 
+
+Arbiter_27_3 : Arbiter
+
+PORT MAP (Request => Request(131), North => south_2_north(26)(3), West => east_2_west(26)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(27)(3), East => east_2_west(27)(3) , Grant => Signal_grant(27)(3)); 
+
+Arbiter_27_4 : Arbiter
+
+PORT MAP (Request => Request(116), North => south_2_north(26)(4), West => east_2_west(26)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(27)(4), East => east_2_west(27)(4) , Grant => Signal_grant(27)(4)); 
+
+Arbiter_27_5 : Arbiter
+
+PORT MAP (Request => Request(101), North => south_2_north(26)(5), West => east_2_west(26)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(27)(5), East => east_2_west(27)(5) , Grant => Signal_grant(27)(5)); 
+
+Arbiter_27_6 : Arbiter
+
+PORT MAP (Request => Request(86), North => south_2_north(26)(6), West => east_2_west(26)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(27)(6), East => east_2_west(27)(6) , Grant => Signal_grant(27)(6)); 
+
+Arbiter_27_7 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(26)(7), West => east_2_west(26)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(27)(7), East => east_2_west(27)(7) , Grant => Signal_grant(27)(7)); 
+
+Arbiter_27_8 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(26)(8), West => east_2_west(26)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(27)(8), East => east_2_west(27)(8) , Grant => Signal_grant(27)(8)); 
+
+Arbiter_27_9 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(26)(9), West => east_2_west(26)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(27)(9), East => east_2_west(27)(9) , Grant => Signal_grant(27)(9)); 
+
+Arbiter_27_10 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(26)(10), West => east_2_west(26)(9), P => Signal_priority(5), Fifo_full => Fifo_full(10),  
+South => south_2_north(27)(10), East => east_2_west(27)(10) , Grant => Signal_grant(27)(10)); 
+
+Arbiter_27_11 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(26)(11), West => east_2_west(26)(10), P => Signal_priority(5), Fifo_full => Fifo_full(11),  
+South => south_2_north(27)(11), East => east_2_west(27)(11) , Grant => Signal_grant(27)(11)); 
+
+Arbiter_27_12 : Arbiter
+
+PORT MAP (Request => Request(252), North => south_2_north(26)(12), West => east_2_west(26)(11), P => Signal_priority(5), Fifo_full => Fifo_full(12),  
+South => south_2_north(27)(12), East => east_2_west(27)(12) , Grant => Signal_grant(27)(12)); 
+
+Arbiter_27_13 : Arbiter
+
+PORT MAP (Request => Request(237), North => south_2_north(26)(13), West => east_2_west(26)(12), P => Signal_priority(5), Fifo_full => Fifo_full(13),  
+South => south_2_north(27)(13), East => east_2_west(27)(13) , Grant => Signal_grant(27)(13)); 
+
+Arbiter_27_14 : Arbiter
+
+PORT MAP (Request => Request(222), North => south_2_north(26)(14), West => east_2_west(26)(13), P => Signal_priority(5), Fifo_full => Fifo_full(14),  
+South => south_2_north(27)(14), East => east_2_west(27)(14) , Grant => Signal_grant(27)(14)); 
+
+Arbiter_27_15 : Arbiter
+
+PORT MAP (Request => Request(207), North => south_2_north(26)(15), West => east_2_west(26)(14), P => Signal_priority(5), Fifo_full => Fifo_full(15),  
+South => south_2_north(27)(15), East => east_2_west(27)(15) , Grant => Signal_grant(27)(15)); 
+
+Arbiter_27_16 : Arbiter
+
+PORT MAP (Request => Request(192), North => south_2_north(26)(16), West => east_2_west(26)(15), P => Signal_priority(5), Fifo_full => Fifo_full(16),  
+South => south_2_north(27)(16), East => east_2_west(27)(16) , Grant => Signal_grant(27)(16)); 
+
+-------------------------- Diagonale n° 28 
+
+
+Arbiter_28_1 : Arbiter
+
+PORT MAP (Request => Request(177), North => south_2_north(27)(1), West => east_2_west(27)(16), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(28)(1), East => east_2_west(28)(1) , Grant => Signal_grant(28)(1)); 
+
+Arbiter_28_2 : Arbiter
+
+PORT MAP (Request => Request(162), North => south_2_north(27)(2), West => east_2_west(27)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(28)(2), East => east_2_west(28)(2) , Grant => Signal_grant(28)(2)); 
+
+Arbiter_28_3 : Arbiter
+
+PORT MAP (Request => Request(147), North => south_2_north(27)(3), West => east_2_west(27)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(28)(3), East => east_2_west(28)(3) , Grant => Signal_grant(28)(3)); 
+
+Arbiter_28_4 : Arbiter
+
+PORT MAP (Request => Request(132), North => south_2_north(27)(4), West => east_2_west(27)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(28)(4), East => east_2_west(28)(4) , Grant => Signal_grant(28)(4)); 
+
+Arbiter_28_5 : Arbiter
+
+PORT MAP (Request => Request(117), North => south_2_north(27)(5), West => east_2_west(27)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(28)(5), East => east_2_west(28)(5) , Grant => Signal_grant(28)(5)); 
+
+Arbiter_28_6 : Arbiter
+
+PORT MAP (Request => Request(102), North => south_2_north(27)(6), West => east_2_west(27)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(28)(6), East => east_2_west(28)(6) , Grant => Signal_grant(28)(6)); 
+
+Arbiter_28_7 : Arbiter
+
+PORT MAP (Request => Request(87), North => south_2_north(27)(7), West => east_2_west(27)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(28)(7), East => east_2_west(28)(7) , Grant => Signal_grant(28)(7)); 
+
+Arbiter_28_8 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(27)(8), West => east_2_west(27)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(28)(8), East => east_2_west(28)(8) , Grant => Signal_grant(28)(8)); 
+
+Arbiter_28_9 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(27)(9), West => east_2_west(27)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(28)(9), East => east_2_west(28)(9) , Grant => Signal_grant(28)(9)); 
+
+Arbiter_28_10 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(27)(10), West => east_2_west(27)(9), P => Signal_priority(4), Fifo_full => Fifo_full(10),  
+South => south_2_north(28)(10), East => east_2_west(28)(10) , Grant => Signal_grant(28)(10)); 
+
+Arbiter_28_11 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(27)(11), West => east_2_west(27)(10), P => Signal_priority(4), Fifo_full => Fifo_full(11),  
+South => south_2_north(28)(11), East => east_2_west(28)(11) , Grant => Signal_grant(28)(11)); 
+
+Arbiter_28_12 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(27)(12), West => east_2_west(27)(11), P => Signal_priority(4), Fifo_full => Fifo_full(12),  
+South => south_2_north(28)(12), East => east_2_west(28)(12) , Grant => Signal_grant(28)(12)); 
+
+Arbiter_28_13 : Arbiter
+
+PORT MAP (Request => Request(253), North => south_2_north(27)(13), West => east_2_west(27)(12), P => Signal_priority(4), Fifo_full => Fifo_full(13),  
+South => south_2_north(28)(13), East => east_2_west(28)(13) , Grant => Signal_grant(28)(13)); 
+
+Arbiter_28_14 : Arbiter
+
+PORT MAP (Request => Request(238), North => south_2_north(27)(14), West => east_2_west(27)(13), P => Signal_priority(4), Fifo_full => Fifo_full(14),  
+South => south_2_north(28)(14), East => east_2_west(28)(14) , Grant => Signal_grant(28)(14)); 
+
+Arbiter_28_15 : Arbiter
+
+PORT MAP (Request => Request(223), North => south_2_north(27)(15), West => east_2_west(27)(14), P => Signal_priority(4), Fifo_full => Fifo_full(15),  
+South => south_2_north(28)(15), East => east_2_west(28)(15) , Grant => Signal_grant(28)(15)); 
+
+Arbiter_28_16 : Arbiter
+
+PORT MAP (Request => Request(208), North => south_2_north(27)(16), West => east_2_west(27)(15), P => Signal_priority(4), Fifo_full => Fifo_full(16),  
+South => south_2_north(28)(16), East => east_2_west(28)(16) , Grant => Signal_grant(28)(16)); 
+
+-------------------------- Diagonale n° 29 
+
+
+Arbiter_29_1 : Arbiter
+
+PORT MAP (Request => Request(193), North => south_2_north(28)(1), West => east_2_west(28)(16), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(29)(1), East => east_2_west(29)(1) , Grant => Signal_grant(29)(1)); 
+
+Arbiter_29_2 : Arbiter
+
+PORT MAP (Request => Request(178), North => south_2_north(28)(2), West => east_2_west(28)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(29)(2), East => east_2_west(29)(2) , Grant => Signal_grant(29)(2)); 
+
+Arbiter_29_3 : Arbiter
+
+PORT MAP (Request => Request(163), North => south_2_north(28)(3), West => east_2_west(28)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(29)(3), East => east_2_west(29)(3) , Grant => Signal_grant(29)(3)); 
+
+Arbiter_29_4 : Arbiter
+
+PORT MAP (Request => Request(148), North => south_2_north(28)(4), West => east_2_west(28)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(29)(4), East => east_2_west(29)(4) , Grant => Signal_grant(29)(4)); 
+
+Arbiter_29_5 : Arbiter
+
+PORT MAP (Request => Request(133), North => south_2_north(28)(5), West => east_2_west(28)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(29)(5), East => east_2_west(29)(5) , Grant => Signal_grant(29)(5)); 
+
+Arbiter_29_6 : Arbiter
+
+PORT MAP (Request => Request(118), North => south_2_north(28)(6), West => east_2_west(28)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(29)(6), East => east_2_west(29)(6) , Grant => Signal_grant(29)(6)); 
+
+Arbiter_29_7 : Arbiter
+
+PORT MAP (Request => Request(103), North => south_2_north(28)(7), West => east_2_west(28)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(29)(7), East => east_2_west(29)(7) , Grant => Signal_grant(29)(7)); 
+
+Arbiter_29_8 : Arbiter
+
+PORT MAP (Request => Request(88), North => south_2_north(28)(8), West => east_2_west(28)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(29)(8), East => east_2_west(29)(8) , Grant => Signal_grant(29)(8)); 
+
+Arbiter_29_9 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(28)(9), West => east_2_west(28)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(29)(9), East => east_2_west(29)(9) , Grant => Signal_grant(29)(9)); 
+
+Arbiter_29_10 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(28)(10), West => east_2_west(28)(9), P => Signal_priority(3), Fifo_full => Fifo_full(10),  
+South => south_2_north(29)(10), East => east_2_west(29)(10) , Grant => Signal_grant(29)(10)); 
+
+Arbiter_29_11 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(28)(11), West => east_2_west(28)(10), P => Signal_priority(3), Fifo_full => Fifo_full(11),  
+South => south_2_north(29)(11), East => east_2_west(29)(11) , Grant => Signal_grant(29)(11)); 
+
+Arbiter_29_12 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(28)(12), West => east_2_west(28)(11), P => Signal_priority(3), Fifo_full => Fifo_full(12),  
+South => south_2_north(29)(12), East => east_2_west(29)(12) , Grant => Signal_grant(29)(12)); 
+
+Arbiter_29_13 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(28)(13), West => east_2_west(28)(12), P => Signal_priority(3), Fifo_full => Fifo_full(13),  
+South => south_2_north(29)(13), East => east_2_west(29)(13) , Grant => Signal_grant(29)(13)); 
+
+Arbiter_29_14 : Arbiter
+
+PORT MAP (Request => Request(254), North => south_2_north(28)(14), West => east_2_west(28)(13), P => Signal_priority(3), Fifo_full => Fifo_full(14),  
+South => south_2_north(29)(14), East => east_2_west(29)(14) , Grant => Signal_grant(29)(14)); 
+
+Arbiter_29_15 : Arbiter
+
+PORT MAP (Request => Request(239), North => south_2_north(28)(15), West => east_2_west(28)(14), P => Signal_priority(3), Fifo_full => Fifo_full(15),  
+South => south_2_north(29)(15), East => east_2_west(29)(15) , Grant => Signal_grant(29)(15)); 
+
+Arbiter_29_16 : Arbiter
+
+PORT MAP (Request => Request(224), North => south_2_north(28)(16), West => east_2_west(28)(15), P => Signal_priority(3), Fifo_full => Fifo_full(16),  
+South => south_2_north(29)(16), East => east_2_west(29)(16) , Grant => Signal_grant(29)(16)); 
+
+-------------------------- Diagonale n° 30 
+
+
+Arbiter_30_1 : Arbiter
+
+PORT MAP (Request => Request(209), North => south_2_north(29)(1), West => east_2_west(29)(16), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(30)(1), East => east_2_west(30)(1) , Grant => Signal_grant(30)(1)); 
+
+Arbiter_30_2 : Arbiter
+
+PORT MAP (Request => Request(194), North => south_2_north(29)(2), West => east_2_west(29)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(30)(2), East => east_2_west(30)(2) , Grant => Signal_grant(30)(2)); 
+
+Arbiter_30_3 : Arbiter
+
+PORT MAP (Request => Request(179), North => south_2_north(29)(3), West => east_2_west(29)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(30)(3), East => east_2_west(30)(3) , Grant => Signal_grant(30)(3)); 
+
+Arbiter_30_4 : Arbiter
+
+PORT MAP (Request => Request(164), North => south_2_north(29)(4), West => east_2_west(29)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(30)(4), East => east_2_west(30)(4) , Grant => Signal_grant(30)(4)); 
+
+Arbiter_30_5 : Arbiter
+
+PORT MAP (Request => Request(149), North => south_2_north(29)(5), West => east_2_west(29)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(30)(5), East => east_2_west(30)(5) , Grant => Signal_grant(30)(5)); 
+
+Arbiter_30_6 : Arbiter
+
+PORT MAP (Request => Request(134), North => south_2_north(29)(6), West => east_2_west(29)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(30)(6), East => east_2_west(30)(6) , Grant => Signal_grant(30)(6)); 
+
+Arbiter_30_7 : Arbiter
+
+PORT MAP (Request => Request(119), North => south_2_north(29)(7), West => east_2_west(29)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(30)(7), East => east_2_west(30)(7) , Grant => Signal_grant(30)(7)); 
+
+Arbiter_30_8 : Arbiter
+
+PORT MAP (Request => Request(104), North => south_2_north(29)(8), West => east_2_west(29)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(30)(8), East => east_2_west(30)(8) , Grant => Signal_grant(30)(8)); 
+
+Arbiter_30_9 : Arbiter
+
+PORT MAP (Request => Request(89), North => south_2_north(29)(9), West => east_2_west(29)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(30)(9), East => east_2_west(30)(9) , Grant => Signal_grant(30)(9)); 
+
+Arbiter_30_10 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(29)(10), West => east_2_west(29)(9), P => Signal_priority(2), Fifo_full => Fifo_full(10),  
+South => south_2_north(30)(10), East => east_2_west(30)(10) , Grant => Signal_grant(30)(10)); 
+
+Arbiter_30_11 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(29)(11), West => east_2_west(29)(10), P => Signal_priority(2), Fifo_full => Fifo_full(11),  
+South => south_2_north(30)(11), East => east_2_west(30)(11) , Grant => Signal_grant(30)(11)); 
+
+Arbiter_30_12 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(29)(12), West => east_2_west(29)(11), P => Signal_priority(2), Fifo_full => Fifo_full(12),  
+South => south_2_north(30)(12), East => east_2_west(30)(12) , Grant => Signal_grant(30)(12)); 
+
+Arbiter_30_13 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(29)(13), West => east_2_west(29)(12), P => Signal_priority(2), Fifo_full => Fifo_full(13),  
+South => south_2_north(30)(13), East => east_2_west(30)(13) , Grant => Signal_grant(30)(13)); 
+
+Arbiter_30_14 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(29)(14), West => east_2_west(29)(13), P => Signal_priority(2), Fifo_full => Fifo_full(14),  
+South => south_2_north(30)(14), East => east_2_west(30)(14) , Grant => Signal_grant(30)(14)); 
+
+Arbiter_30_15 : Arbiter
+
+PORT MAP (Request => Request(255), North => south_2_north(29)(15), West => east_2_west(29)(14), P => Signal_priority(2), Fifo_full => Fifo_full(15),  
+South => south_2_north(30)(15), East => east_2_west(30)(15) , Grant => Signal_grant(30)(15)); 
+
+Arbiter_30_16 : Arbiter
+
+PORT MAP (Request => Request(240), North => south_2_north(29)(16), West => east_2_west(29)(15), P => Signal_priority(2), Fifo_full => Fifo_full(16),  
+South => south_2_north(30)(16), East => east_2_west(30)(16) , Grant => Signal_grant(30)(16)); 
+
+-------------------------- Diagonale n° 31 
+
+
+Arbiter_31_1 : Arbiter
+
+PORT MAP (Request => Request(225), North => south_2_north(30)(1), West => east_2_west(30)(16), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(31)(1), East => east_2_west(31)(1) , Grant => Signal_grant(31)(1)); 
+
+Arbiter_31_2 : Arbiter
+
+PORT MAP (Request => Request(210), North => south_2_north(30)(2), West => east_2_west(30)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(31)(2), East => east_2_west(31)(2) , Grant => Signal_grant(31)(2)); 
+
+Arbiter_31_3 : Arbiter
+
+PORT MAP (Request => Request(195), North => south_2_north(30)(3), West => east_2_west(30)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(31)(3), East => east_2_west(31)(3) , Grant => Signal_grant(31)(3)); 
+
+Arbiter_31_4 : Arbiter
+
+PORT MAP (Request => Request(180), North => south_2_north(30)(4), West => east_2_west(30)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(31)(4), East => east_2_west(31)(4) , Grant => Signal_grant(31)(4)); 
+
+Arbiter_31_5 : Arbiter
+
+PORT MAP (Request => Request(165), North => south_2_north(30)(5), West => east_2_west(30)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(31)(5), East => east_2_west(31)(5) , Grant => Signal_grant(31)(5)); 
+
+Arbiter_31_6 : Arbiter
+
+PORT MAP (Request => Request(150), North => south_2_north(30)(6), West => east_2_west(30)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(31)(6), East => east_2_west(31)(6) , Grant => Signal_grant(31)(6)); 
+
+Arbiter_31_7 : Arbiter
+
+PORT MAP (Request => Request(135), North => south_2_north(30)(7), West => east_2_west(30)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(31)(7), East => east_2_west(31)(7) , Grant => Signal_grant(31)(7)); 
+
+Arbiter_31_8 : Arbiter
+
+PORT MAP (Request => Request(120), North => south_2_north(30)(8), West => east_2_west(30)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(31)(8), East => east_2_west(31)(8) , Grant => Signal_grant(31)(8)); 
+
+Arbiter_31_9 : Arbiter
+
+PORT MAP (Request => Request(105), North => south_2_north(30)(9), West => east_2_west(30)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(31)(9), East => east_2_west(31)(9) , Grant => Signal_grant(31)(9)); 
+
+Arbiter_31_10 : Arbiter
+
+PORT MAP (Request => Request(90), North => south_2_north(30)(10), West => east_2_west(30)(9), P => Signal_priority(1), Fifo_full => Fifo_full(10),  
+South => south_2_north(31)(10), East => east_2_west(31)(10) , Grant => Signal_grant(31)(10)); 
+
+Arbiter_31_11 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(30)(11), West => east_2_west(30)(10), P => Signal_priority(1), Fifo_full => Fifo_full(11),  
+South => south_2_north(31)(11), East => east_2_west(31)(11) , Grant => Signal_grant(31)(11)); 
+
+Arbiter_31_12 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(30)(12), West => east_2_west(30)(11), P => Signal_priority(1), Fifo_full => Fifo_full(12),  
+South => south_2_north(31)(12), East => east_2_west(31)(12) , Grant => Signal_grant(31)(12)); 
+
+Arbiter_31_13 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(30)(13), West => east_2_west(30)(12), P => Signal_priority(1), Fifo_full => Fifo_full(13),  
+South => south_2_north(31)(13), East => east_2_west(31)(13) , Grant => Signal_grant(31)(13)); 
+
+Arbiter_31_14 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(30)(14), West => east_2_west(30)(13), P => Signal_priority(1), Fifo_full => Fifo_full(14),  
+South => south_2_north(31)(14), East => east_2_west(31)(14) , Grant => Signal_grant(31)(14)); 
+
+Arbiter_31_15 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(30)(15), West => east_2_west(30)(14), P => Signal_priority(1), Fifo_full => Fifo_full(15),  
+South => south_2_north(31)(15), East => east_2_west(31)(15) , Grant => Signal_grant(31)(15)); 
+
+Arbiter_31_16 : Arbiter
+
+PORT MAP (Request => Request(256), North => south_2_north(30)(16), West => east_2_west(30)(15), P => Signal_priority(1), Fifo_full => Fifo_full(16),  
+South => south_2_north(31)(16), East => east_2_west(31)(16) , Grant => Signal_grant(31)(16)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "1111111111111111000000000000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "1111111111111111000000000000000" => Signal_priority <= "0111111111111111100000000000000";
+		       when "0111111111111111100000000000000" => Signal_priority <= "0011111111111111110000000000000";
+		       when "0011111111111111110000000000000" => Signal_priority <= "0001111111111111111000000000000";
+		       when "0001111111111111111000000000000" => Signal_priority <= "0000111111111111111100000000000";
+		       when "0000111111111111111100000000000" => Signal_priority <= "0000011111111111111110000000000";
+		       when "0000011111111111111110000000000" => Signal_priority <= "0000001111111111111111000000000";
+		       when "0000001111111111111111000000000" => Signal_priority <= "0000000111111111111111100000000";
+		       when "0000000111111111111111100000000" => Signal_priority <= "0000000011111111111111110000000";
+		       when "0000000011111111111111110000000" => Signal_priority <= "0000000001111111111111111000000";
+		       when "0000000001111111111111111000000" => Signal_priority <= "0000000000111111111111111100000";
+		       when "0000000000111111111111111100000" => Signal_priority <= "0000000000011111111111111110000";
+		       when "0000000000011111111111111110000" => Signal_priority <= "0000000000001111111111111111000";
+		       when "0000000000001111111111111111000" => Signal_priority <= "0000000000000111111111111111100";
+		       when "0000000000000111111111111111100" => Signal_priority <= "0000000000000011111111111111110";
+		       when "0000000000000011111111111111110" => Signal_priority <= "0000000000000001111111111111111";
+		       when "0000000000000001111111111111111" => Signal_priority <= "1111111111111111000000000000000";
+		       when others    => Signal_priority <= "1111111111111111000000000000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER2_2.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER2_2.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER2_2.VHD	(revision 20)
@@ -0,0 +1,141 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler2_2 is
+    Port ( Request : in  STD_LOGIC_VECTOR (4 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (2 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (2 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (4 downto 1));
+end Scheduler2_2;
+
+architecture Behavioral of Scheduler2_2 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(3 downto 1) of STD_LOGIC_VECTOR(2 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (3 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(4 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant ,req_grant :  std_logic_vector(4 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 3 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(3)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) ;                      --  Grant(1,2)
+Grant(3)  <= Signal_grant(2)(1) ;                      --  Grant(2,1)
+Grant(4)  <= Signal_grant(1)(2) or Signal_grant(3)(2); --  Grant(2,2)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(4), North => High, West => High, P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(1)(1), West => east_2_west(1)(2), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(2)(1), West => east_2_west(2)(2), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "110";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "110" => Signal_priority <= "011";
+		       when "011" => Signal_priority <= "110";
+		       when others    => Signal_priority <= "110";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER3_3.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER3_3.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER3_3.VHD	(revision 20)
@@ -0,0 +1,198 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler3_3 is
+    Port ( Request : in  STD_LOGIC_VECTOR (9 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (3 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (3 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (9 downto 1));
+end Scheduler3_3;
+
+architecture Behavioral of Scheduler3_3 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(5 downto 1) of STD_LOGIC_VECTOR(3 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (5 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(9 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant,req_grant :  std_logic_vector(9 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 7 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(4)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(5)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) ;                      --  Grant(1,3)
+Grant(4)  <= Signal_grant(2)(1) or Signal_grant(5)(1); --  Grant(2,1)
+Grant(5)  <= Signal_grant(3)(2) ;                      --  Grant(2,2)
+Grant(6)  <= Signal_grant(1)(3) or Signal_grant(4)(3); --  Grant(2,3)
+Grant(7)  <= Signal_grant(3)(1) ;                      --  Grant(3,1)
+Grant(8)  <= Signal_grant(1)(2) or Signal_grant(4)(2); --  Grant(3,2)
+Grant(9)  <= Signal_grant(2)(3) or Signal_grant(5)(3); --  Grant(3,3)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(8), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(6), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(1)(1), West => east_2_west(1)(3), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(2)(1), West => east_2_west(2)(3), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(3)(1), West => east_2_west(3)(3), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(4)(1), West => east_2_west(4)(3), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "11100";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "11100" => Signal_priority <= "01110";
+		       when "01110" => Signal_priority <= "00111";
+		       when "00111" => Signal_priority <= "11100";
+		       when others    => Signal_priority <= "11100";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER3_3.stx
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER3_3.stx	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER3_3.stx	(revision 20)
@@ -0,0 +1,35 @@
+Release 11.1 - xst L.33 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
+--> Parameter TMPDIR set to C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 1.00 secs
+Total CPU time to Xst completion: 0.17 secs
+ 
+--> Parameter xsthdpdir set to C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst
+
+
+Total REAL time to Xst completion: 1.00 secs
+Total CPU time to Xst completion: 0.17 secs
+ 
+--> 
+=========================================================================
+*                          HDL Compilation                              *
+=========================================================================
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/Arbiter.vhd" in Library work.
+Architecture behavioral of Entity arbiter is up to date.
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/SCHEDULER3_3.VHD" in Library work.
+Architecture behavioral of Entity scheduler3_3 is up to date.
+
+
+Total REAL time to Xst completion: 1.00 secs
+Total CPU time to Xst completion: 0.35 secs
+ 
+--> 
+
+Total memory usage is 119772 kilobytes
+
+Number of errors   :    0 (   0 filtered)
+Number of warnings :    0 (   0 filtered)
+Number of infos    :    0 (   0 filtered)
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER3_3.xst
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER3_3.xst	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER3_3.xst	(revision 20)
@@ -0,0 +1,5 @@
+set -tmpdir "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst/projnav.tmp"
+set -xsthdpdir "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst"
+elaborate
+-ifn SCHEDULER3_3.prj
+-ifmt mixed
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER4_4.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER4_4.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER4_4.VHD	(revision 20)
@@ -0,0 +1,278 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler4_4 is
+    Port ( Request : in  STD_LOGIC_VECTOR (16 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (4 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (4 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (16 downto 1));
+end Scheduler4_4;
+
+architecture Behavioral of Scheduler4_4 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(7 downto 1) of STD_LOGIC_VECTOR(4 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (7 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch,req_grant: std_logic_vector(16 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(16 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 15 else 	'0'; 
+
+--latch  qui memorise le signal grant pendant la transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <=  grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(5)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(6)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(7)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) ;                      --  Grant(1,4)
+Grant(5)  <= Signal_grant(2)(1) or Signal_grant(6)(1); --  Grant(2,1)
+Grant(6)  <= Signal_grant(3)(2) or Signal_grant(7)(2); --  Grant(2,2)
+Grant(7)  <= Signal_grant(4)(3) ;                      --  Grant(2,3)
+Grant(8)  <= Signal_grant(1)(4) or Signal_grant(5)(4); --  Grant(2,4)
+Grant(9)  <= Signal_grant(3)(1) or Signal_grant(7)(1); --  Grant(3,1)
+Grant(10)  <= Signal_grant(4)(2) ;                      --  Grant(3,2)
+Grant(11)  <= Signal_grant(1)(3) or Signal_grant(5)(3); --  Grant(3,3)
+Grant(12)  <= Signal_grant(2)(4) or Signal_grant(6)(4); --  Grant(3,4)
+Grant(13)  <= Signal_grant(4)(1) ;                      --  Grant(4,1)
+Grant(14)  <= Signal_grant(1)(2) or Signal_grant(5)(2); --  Grant(4,2)
+Grant(15)  <= Signal_grant(2)(3) or Signal_grant(6)(3); --  Grant(4,3)
+Grant(16)  <= Signal_grant(3)(4) or Signal_grant(7)(4); --  Grant(4,4)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(14), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(11), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(8), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(1)(1), West => east_2_west(1)(4), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(2)(1), West => east_2_west(2)(4), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(3)(1), West => east_2_west(3)(4), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(4)(1), West => east_2_west(4)(4), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(5)(1), West => east_2_west(5)(4), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(6)(1), West => east_2_west(6)(4), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "1111000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "1111000" => Signal_priority <= "0111100";
+		       when "0111100" => Signal_priority <= "0011110";
+		       when "0011110" => Signal_priority <= "0001111";
+		       when "0001111" => Signal_priority <= "1111000";
+		       when others    => Signal_priority <= "1111000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER5_5.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER5_5.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER5_5.VHD	(revision 20)
@@ -0,0 +1,378 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler5_5 is
+    Port ( Request : in  STD_LOGIC_VECTOR (25 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (5 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (5 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (25 downto 1));
+end Scheduler5_5;
+
+architecture Behavioral of Scheduler5_5 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(9 downto 1) of STD_LOGIC_VECTOR(5 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (9 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(25 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant ,req_grant:  std_logic_vector(25 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+  req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when   unsigned(req_grant) = 0 or unsigned(priority_rotation) = 31 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(6)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(7)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(8)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(9)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) ;                      --  Grant(1,5)
+Grant(6)  <= Signal_grant(2)(1) or Signal_grant(7)(1); --  Grant(2,1)
+Grant(7)  <= Signal_grant(3)(2) or Signal_grant(8)(2); --  Grant(2,2)
+Grant(8)  <= Signal_grant(4)(3) or Signal_grant(9)(3); --  Grant(2,3)
+Grant(9)  <= Signal_grant(5)(4) ;                      --  Grant(2,4)
+Grant(10)  <= Signal_grant(1)(5) or Signal_grant(6)(5); --  Grant(2,5)
+Grant(11)  <= Signal_grant(3)(1) or Signal_grant(8)(1); --  Grant(3,1)
+Grant(12)  <= Signal_grant(4)(2) or Signal_grant(9)(2); --  Grant(3,2)
+Grant(13)  <= Signal_grant(5)(3) ;                      --  Grant(3,3)
+Grant(14)  <= Signal_grant(1)(4) or Signal_grant(6)(4); --  Grant(3,4)
+Grant(15)  <= Signal_grant(2)(5) or Signal_grant(7)(5); --  Grant(3,5)
+Grant(16)  <= Signal_grant(4)(1) or Signal_grant(9)(1); --  Grant(4,1)
+Grant(17)  <= Signal_grant(5)(2) ;                      --  Grant(4,2)
+Grant(18)  <= Signal_grant(1)(3) or Signal_grant(6)(3); --  Grant(4,3)
+Grant(19)  <= Signal_grant(2)(4) or Signal_grant(7)(4); --  Grant(4,4)
+Grant(20)  <= Signal_grant(3)(5) or Signal_grant(8)(5); --  Grant(4,5)
+Grant(21)  <= Signal_grant(5)(1) ;                      --  Grant(5,1)
+Grant(22)  <= Signal_grant(1)(2) or Signal_grant(6)(2); --  Grant(5,2)
+Grant(23)  <= Signal_grant(2)(3) or Signal_grant(7)(3); --  Grant(5,3)
+Grant(24)  <= Signal_grant(3)(4) or Signal_grant(8)(4); --  Grant(5,4)
+Grant(25)  <= Signal_grant(4)(5) or Signal_grant(9)(5); --  Grant(5,5)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(22), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(18), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(14), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(10), North => High, West => High, P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(1)(1), West => east_2_west(1)(5), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(2)(1), West => east_2_west(2)(5), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(3)(1), West => east_2_west(3)(5), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(4)(1), West => east_2_west(4)(5), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(5)(1), West => east_2_west(5)(5), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(6)(1), West => east_2_west(6)(5), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(7)(1), West => east_2_west(7)(5), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(8)(1), West => east_2_west(8)(5), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "111110000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "111110000" => Signal_priority <= "011111000";
+		       when "011111000" => Signal_priority <= "001111100";
+		       when "001111100" => Signal_priority <= "000111110";
+		       when "000111110" => Signal_priority <= "000011111";
+		       when "000011111" => Signal_priority <= "111110000";
+		       when others    => Signal_priority <= "111110000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER6_6.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER6_6.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER6_6.VHD	(revision 20)
@@ -0,0 +1,501 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler6_6 is
+    Port ( Request : in  STD_LOGIC_VECTOR (36 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (6 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (6 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (36 downto 1));
+end Scheduler6_6;
+
+architecture Behavioral of Scheduler6_6 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(11 downto 1) of STD_LOGIC_VECTOR(6 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (11 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(36 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant,req_grant :  std_logic_vector(36 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when   unsigned(req_grant) = 0 or unsigned(priority_rotation) = 63 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(7)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(8)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(9)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(10)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(11)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) ;                      --  Grant(1,6)
+Grant(7)  <= Signal_grant(2)(1) or Signal_grant(8)(1); --  Grant(2,1)
+Grant(8)  <= Signal_grant(3)(2) or Signal_grant(9)(2); --  Grant(2,2)
+Grant(9)  <= Signal_grant(4)(3) or Signal_grant(10)(3); --  Grant(2,3)
+Grant(10)  <= Signal_grant(5)(4) or Signal_grant(11)(4); --  Grant(2,4)
+Grant(11)  <= Signal_grant(6)(5) ;                      --  Grant(2,5)
+Grant(12)  <= Signal_grant(1)(6) or Signal_grant(7)(6); --  Grant(2,6)
+Grant(13)  <= Signal_grant(3)(1) or Signal_grant(9)(1); --  Grant(3,1)
+Grant(14)  <= Signal_grant(4)(2) or Signal_grant(10)(2); --  Grant(3,2)
+Grant(15)  <= Signal_grant(5)(3) or Signal_grant(11)(3); --  Grant(3,3)
+Grant(16)  <= Signal_grant(6)(4) ;                      --  Grant(3,4)
+Grant(17)  <= Signal_grant(1)(5) or Signal_grant(7)(5); --  Grant(3,5)
+Grant(18)  <= Signal_grant(2)(6) or Signal_grant(8)(6); --  Grant(3,6)
+Grant(19)  <= Signal_grant(4)(1) or Signal_grant(10)(1); --  Grant(4,1)
+Grant(20)  <= Signal_grant(5)(2) or Signal_grant(11)(2); --  Grant(4,2)
+Grant(21)  <= Signal_grant(6)(3) ;                      --  Grant(4,3)
+Grant(22)  <= Signal_grant(1)(4) or Signal_grant(7)(4); --  Grant(4,4)
+Grant(23)  <= Signal_grant(2)(5) or Signal_grant(8)(5); --  Grant(4,5)
+Grant(24)  <= Signal_grant(3)(6) or Signal_grant(9)(6); --  Grant(4,6)
+Grant(25)  <= Signal_grant(5)(1) or Signal_grant(11)(1); --  Grant(5,1)
+Grant(26)  <= Signal_grant(6)(2) ;                      --  Grant(5,2)
+Grant(27)  <= Signal_grant(1)(3) or Signal_grant(7)(3); --  Grant(5,3)
+Grant(28)  <= Signal_grant(2)(4) or Signal_grant(8)(4); --  Grant(5,4)
+Grant(29)  <= Signal_grant(3)(5) or Signal_grant(9)(5); --  Grant(5,5)
+Grant(30)  <= Signal_grant(4)(6) or Signal_grant(10)(6); --  Grant(5,6)
+Grant(31)  <= Signal_grant(6)(1) ;                      --  Grant(6,1)
+Grant(32)  <= Signal_grant(1)(2) or Signal_grant(7)(2); --  Grant(6,2)
+Grant(33)  <= Signal_grant(2)(3) or Signal_grant(8)(3); --  Grant(6,3)
+Grant(34)  <= Signal_grant(3)(4) or Signal_grant(9)(4); --  Grant(6,4)
+Grant(35)  <= Signal_grant(4)(5) or Signal_grant(10)(5); --  Grant(6,5)
+Grant(36)  <= Signal_grant(5)(6) or Signal_grant(11)(6); --  Grant(6,6)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(32), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(27), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(22), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(17), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(12), North => High, West => High, P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(1)(1), West => east_2_west(1)(6), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(2)(1), West => east_2_west(2)(6), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(3)(1), West => east_2_west(3)(6), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(4)(1), West => east_2_west(4)(6), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(5)(1), West => east_2_west(5)(6), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(6)(1), West => east_2_west(6)(6), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(7)(1), West => east_2_west(7)(6), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(8)(1), West => east_2_west(8)(6), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(9)(1), West => east_2_west(9)(6), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(10)(1), West => east_2_west(10)(6), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "11111100000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "11111100000" => Signal_priority <= "01111110000";
+		       when "01111110000" => Signal_priority <= "00111111000";
+		       when "00111111000" => Signal_priority <= "00011111100";
+		       when "00011111100" => Signal_priority <= "00001111110";
+		       when "00001111110" => Signal_priority <= "00000111111";
+		       when "00000111111" => Signal_priority <= "11111100000";
+		       when others    => Signal_priority <= "11111100000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER7_7.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER7_7.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER7_7.VHD	(revision 20)
@@ -0,0 +1,646 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler7_7 is
+    Port ( Request : in  STD_LOGIC_VECTOR (49 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (7 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (7 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (49 downto 1));
+end Scheduler7_7;
+
+architecture Behavioral of Scheduler7_7 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(13 downto 1) of STD_LOGIC_VECTOR(7 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (13 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(49 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant,req_grant :  std_logic_vector(49 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when   unsigned(req_grant) = 0 or unsigned(priority_rotation) = 127 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(8)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(9)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(10)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(11)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(12)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(13)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) ;                      --  Grant(1,7)
+Grant(8)  <= Signal_grant(2)(1) or Signal_grant(9)(1); --  Grant(2,1)
+Grant(9)  <= Signal_grant(3)(2) or Signal_grant(10)(2); --  Grant(2,2)
+Grant(10)  <= Signal_grant(4)(3) or Signal_grant(11)(3); --  Grant(2,3)
+Grant(11)  <= Signal_grant(5)(4) or Signal_grant(12)(4); --  Grant(2,4)
+Grant(12)  <= Signal_grant(6)(5) or Signal_grant(13)(5); --  Grant(2,5)
+Grant(13)  <= Signal_grant(7)(6) ;                      --  Grant(2,6)
+Grant(14)  <= Signal_grant(1)(7) or Signal_grant(8)(7); --  Grant(2,7)
+Grant(15)  <= Signal_grant(3)(1) or Signal_grant(10)(1); --  Grant(3,1)
+Grant(16)  <= Signal_grant(4)(2) or Signal_grant(11)(2); --  Grant(3,2)
+Grant(17)  <= Signal_grant(5)(3) or Signal_grant(12)(3); --  Grant(3,3)
+Grant(18)  <= Signal_grant(6)(4) or Signal_grant(13)(4); --  Grant(3,4)
+Grant(19)  <= Signal_grant(7)(5) ;                      --  Grant(3,5)
+Grant(20)  <= Signal_grant(1)(6) or Signal_grant(8)(6); --  Grant(3,6)
+Grant(21)  <= Signal_grant(2)(7) or Signal_grant(9)(7); --  Grant(3,7)
+Grant(22)  <= Signal_grant(4)(1) or Signal_grant(11)(1); --  Grant(4,1)
+Grant(23)  <= Signal_grant(5)(2) or Signal_grant(12)(2); --  Grant(4,2)
+Grant(24)  <= Signal_grant(6)(3) or Signal_grant(13)(3); --  Grant(4,3)
+Grant(25)  <= Signal_grant(7)(4) ;                      --  Grant(4,4)
+Grant(26)  <= Signal_grant(1)(5) or Signal_grant(8)(5); --  Grant(4,5)
+Grant(27)  <= Signal_grant(2)(6) or Signal_grant(9)(6); --  Grant(4,6)
+Grant(28)  <= Signal_grant(3)(7) or Signal_grant(10)(7); --  Grant(4,7)
+Grant(29)  <= Signal_grant(5)(1) or Signal_grant(12)(1); --  Grant(5,1)
+Grant(30)  <= Signal_grant(6)(2) or Signal_grant(13)(2); --  Grant(5,2)
+Grant(31)  <= Signal_grant(7)(3) ;                      --  Grant(5,3)
+Grant(32)  <= Signal_grant(1)(4) or Signal_grant(8)(4); --  Grant(5,4)
+Grant(33)  <= Signal_grant(2)(5) or Signal_grant(9)(5); --  Grant(5,5)
+Grant(34)  <= Signal_grant(3)(6) or Signal_grant(10)(6); --  Grant(5,6)
+Grant(35)  <= Signal_grant(4)(7) or Signal_grant(11)(7); --  Grant(5,7)
+Grant(36)  <= Signal_grant(6)(1) or Signal_grant(13)(1); --  Grant(6,1)
+Grant(37)  <= Signal_grant(7)(2) ;                      --  Grant(6,2)
+Grant(38)  <= Signal_grant(1)(3) or Signal_grant(8)(3); --  Grant(6,3)
+Grant(39)  <= Signal_grant(2)(4) or Signal_grant(9)(4); --  Grant(6,4)
+Grant(40)  <= Signal_grant(3)(5) or Signal_grant(10)(5); --  Grant(6,5)
+Grant(41)  <= Signal_grant(4)(6) or Signal_grant(11)(6); --  Grant(6,6)
+Grant(42)  <= Signal_grant(5)(7) or Signal_grant(12)(7); --  Grant(6,7)
+Grant(43)  <= Signal_grant(7)(1) ;                      --  Grant(7,1)
+Grant(44)  <= Signal_grant(1)(2) or Signal_grant(8)(2); --  Grant(7,2)
+Grant(45)  <= Signal_grant(2)(3) or Signal_grant(9)(3); --  Grant(7,3)
+Grant(46)  <= Signal_grant(3)(4) or Signal_grant(10)(4); --  Grant(7,4)
+Grant(47)  <= Signal_grant(4)(5) or Signal_grant(11)(5); --  Grant(7,5)
+Grant(48)  <= Signal_grant(5)(6) or Signal_grant(12)(6); --  Grant(7,6)
+Grant(49)  <= Signal_grant(6)(7) or Signal_grant(13)(7); --  Grant(7,7)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(44), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(38), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(32), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(26), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(20), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(14), North => High, West => High, P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(1)(1), West => east_2_west(1)(7), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(2)(1), West => east_2_west(2)(7), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(3)(1), West => east_2_west(3)(7), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(4)(1), West => east_2_west(4)(7), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(5)(1), West => east_2_west(5)(7), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(6)(1), West => east_2_west(6)(7), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(7)(1), West => east_2_west(7)(7), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(8)(1), West => east_2_west(8)(7), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(9)(1), West => east_2_west(9)(7), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(10)(1), West => east_2_west(10)(7), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(11)(1), West => east_2_west(11)(7), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(12)(1), West => east_2_west(12)(7), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "1111111000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "1111111000000" => Signal_priority <= "0111111100000";
+		       when "0111111100000" => Signal_priority <= "0011111110000";
+		       when "0011111110000" => Signal_priority <= "0001111111000";
+		       when "0001111111000" => Signal_priority <= "0000111111100";
+		       when "0000111111100" => Signal_priority <= "0000011111110";
+		       when "0000011111110" => Signal_priority <= "0000001111111";
+		       when "0000001111111" => Signal_priority <= "1111111000000";
+		       when others    => Signal_priority <= "1111111000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER8_8.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER8_8.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER8_8.VHD	(revision 20)
@@ -0,0 +1,813 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler8_8 is
+    Port ( Request : in  STD_LOGIC_VECTOR (64 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (8 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (8 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (64 downto 1));
+end Scheduler8_8;
+
+architecture Behavioral of Scheduler8_8 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(15 downto 1) of STD_LOGIC_VECTOR(8 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (15 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(64 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant,req_grant :  std_logic_vector(64 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when  unsigned(req_grant) = 0 or unsigned(priority_rotation) = 255 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' or unsigned(Grant_latch)=0 then 
+	   grant_latch <= Grant;
+   end if; 
+   end if; 
+ end process; 
+ port_grant <=  grant_latch ; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(9)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(10)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(11)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(12)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(13)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(14)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(15)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) ;                      --  Grant(1,8)
+Grant(9)  <= Signal_grant(2)(1) or Signal_grant(10)(1); --  Grant(2,1)
+Grant(10)  <= Signal_grant(3)(2) or Signal_grant(11)(2); --  Grant(2,2)
+Grant(11)  <= Signal_grant(4)(3) or Signal_grant(12)(3); --  Grant(2,3)
+Grant(12)  <= Signal_grant(5)(4) or Signal_grant(13)(4); --  Grant(2,4)
+Grant(13)  <= Signal_grant(6)(5) or Signal_grant(14)(5); --  Grant(2,5)
+Grant(14)  <= Signal_grant(7)(6) or Signal_grant(15)(6); --  Grant(2,6)
+Grant(15)  <= Signal_grant(8)(7) ;                      --  Grant(2,7)
+Grant(16)  <= Signal_grant(1)(8) or Signal_grant(9)(8); --  Grant(2,8)
+Grant(17)  <= Signal_grant(3)(1) or Signal_grant(11)(1); --  Grant(3,1)
+Grant(18)  <= Signal_grant(4)(2) or Signal_grant(12)(2); --  Grant(3,2)
+Grant(19)  <= Signal_grant(5)(3) or Signal_grant(13)(3); --  Grant(3,3)
+Grant(20)  <= Signal_grant(6)(4) or Signal_grant(14)(4); --  Grant(3,4)
+Grant(21)  <= Signal_grant(7)(5) or Signal_grant(15)(5); --  Grant(3,5)
+Grant(22)  <= Signal_grant(8)(6) ;                      --  Grant(3,6)
+Grant(23)  <= Signal_grant(1)(7) or Signal_grant(9)(7); --  Grant(3,7)
+Grant(24)  <= Signal_grant(2)(8) or Signal_grant(10)(8); --  Grant(3,8)
+Grant(25)  <= Signal_grant(4)(1) or Signal_grant(12)(1); --  Grant(4,1)
+Grant(26)  <= Signal_grant(5)(2) or Signal_grant(13)(2); --  Grant(4,2)
+Grant(27)  <= Signal_grant(6)(3) or Signal_grant(14)(3); --  Grant(4,3)
+Grant(28)  <= Signal_grant(7)(4) or Signal_grant(15)(4); --  Grant(4,4)
+Grant(29)  <= Signal_grant(8)(5) ;                      --  Grant(4,5)
+Grant(30)  <= Signal_grant(1)(6) or Signal_grant(9)(6); --  Grant(4,6)
+Grant(31)  <= Signal_grant(2)(7) or Signal_grant(10)(7); --  Grant(4,7)
+Grant(32)  <= Signal_grant(3)(8) or Signal_grant(11)(8); --  Grant(4,8)
+Grant(33)  <= Signal_grant(5)(1) or Signal_grant(13)(1); --  Grant(5,1)
+Grant(34)  <= Signal_grant(6)(2) or Signal_grant(14)(2); --  Grant(5,2)
+Grant(35)  <= Signal_grant(7)(3) or Signal_grant(15)(3); --  Grant(5,3)
+Grant(36)  <= Signal_grant(8)(4) ;                      --  Grant(5,4)
+Grant(37)  <= Signal_grant(1)(5) or Signal_grant(9)(5); --  Grant(5,5)
+Grant(38)  <= Signal_grant(2)(6) or Signal_grant(10)(6); --  Grant(5,6)
+Grant(39)  <= Signal_grant(3)(7) or Signal_grant(11)(7); --  Grant(5,7)
+Grant(40)  <= Signal_grant(4)(8) or Signal_grant(12)(8); --  Grant(5,8)
+Grant(41)  <= Signal_grant(6)(1) or Signal_grant(14)(1); --  Grant(6,1)
+Grant(42)  <= Signal_grant(7)(2) or Signal_grant(15)(2); --  Grant(6,2)
+Grant(43)  <= Signal_grant(8)(3) ;                      --  Grant(6,3)
+Grant(44)  <= Signal_grant(1)(4) or Signal_grant(9)(4); --  Grant(6,4)
+Grant(45)  <= Signal_grant(2)(5) or Signal_grant(10)(5); --  Grant(6,5)
+Grant(46)  <= Signal_grant(3)(6) or Signal_grant(11)(6); --  Grant(6,6)
+Grant(47)  <= Signal_grant(4)(7) or Signal_grant(12)(7); --  Grant(6,7)
+Grant(48)  <= Signal_grant(5)(8) or Signal_grant(13)(8); --  Grant(6,8)
+Grant(49)  <= Signal_grant(7)(1) or Signal_grant(15)(1); --  Grant(7,1)
+Grant(50)  <= Signal_grant(8)(2) ;                      --  Grant(7,2)
+Grant(51)  <= Signal_grant(1)(3) or Signal_grant(9)(3); --  Grant(7,3)
+Grant(52)  <= Signal_grant(2)(4) or Signal_grant(10)(4); --  Grant(7,4)
+Grant(53)  <= Signal_grant(3)(5) or Signal_grant(11)(5); --  Grant(7,5)
+Grant(54)  <= Signal_grant(4)(6) or Signal_grant(12)(6); --  Grant(7,6)
+Grant(55)  <= Signal_grant(5)(7) or Signal_grant(13)(7); --  Grant(7,7)
+Grant(56)  <= Signal_grant(6)(8) or Signal_grant(14)(8); --  Grant(7,8)
+Grant(57)  <= Signal_grant(8)(1) ;                      --  Grant(8,1)
+Grant(58)  <= Signal_grant(1)(2) or Signal_grant(9)(2); --  Grant(8,2)
+Grant(59)  <= Signal_grant(2)(3) or Signal_grant(10)(3); --  Grant(8,3)
+Grant(60)  <= Signal_grant(3)(4) or Signal_grant(11)(4); --  Grant(8,4)
+Grant(61)  <= Signal_grant(4)(5) or Signal_grant(12)(5); --  Grant(8,5)
+Grant(62)  <= Signal_grant(5)(6) or Signal_grant(13)(6); --  Grant(8,6)
+Grant(63)  <= Signal_grant(6)(7) or Signal_grant(14)(7); --  Grant(8,7)
+Grant(64)  <= Signal_grant(7)(8) or Signal_grant(15)(8); --  Grant(8,8)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(58), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(51), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(44), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(37), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(30), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(23), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(16), North => High, West => High, P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(1)(1), West => east_2_west(1)(8), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(2)(1), West => east_2_west(2)(8), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(3)(1), West => east_2_west(3)(8), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(4)(1), West => east_2_west(4)(8), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(5)(1), West => east_2_west(5)(8), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(6)(1), West => east_2_west(6)(8), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(7)(1), West => east_2_west(7)(8), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(8)(1), West => east_2_west(8)(8), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(9)(1), West => east_2_west(9)(8), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(10)(1), West => east_2_west(10)(8), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(11)(1), West => east_2_west(11)(8), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(12)(1), West => east_2_west(12)(8), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(13)(1), West => east_2_west(13)(8), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(14)(1), West => east_2_west(14)(8), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "111111110000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "111111110000000" => Signal_priority <= "011111111000000";
+		       when "011111111000000" => Signal_priority <= "001111111100000";
+		       when "001111111100000" => Signal_priority <= "000111111110000";
+		       when "000111111110000" => Signal_priority <= "000011111111000";
+		       when "000011111111000" => Signal_priority <= "000001111111100";
+		       when "000001111111100" => Signal_priority <= "000000111111110";
+		       when "000000111111110" => Signal_priority <= "000000011111111";
+		       when "000000011111111" => Signal_priority <= "111111110000000";
+		       when others    => Signal_priority <= "111111110000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER9_9.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER9_9.VHD	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SCHEDULER9_9.VHD	(revision 20)
@@ -0,0 +1,1001 @@
+---------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    03:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity Scheduler9_9 is
+    Port ( Request : in  STD_LOGIC_VECTOR (81 downto 1);
+		   Fifo_full : in STD_LOGIC_VECTOR (9 downto 1);
+           clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+            priority_rotation : in  STD_LOGIC_VECTOR (9 downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (81 downto 1));
+end Scheduler9_9;
+
+architecture Behavioral of Scheduler9_9 is
+--Declaration du types
+--tableau de signaux de connexion des cellules arbitres
+TYPE C_Bar_Signal_Array IS ARRAY(17 downto 1) of STD_LOGIC_VECTOR(9 downto 1);
+-- declaration du composant cellule d'arbitrage
+Component Arbiter 
+  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
+        Grant,East,South : out  STD_LOGIC );
+End Component;--Signaux de connexion des cellues
+SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
+SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
+SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
+SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
+SIGNAL Signal_priority  : STD_LOGIC_VECTOR (17 DOWNTO 1);--signal pour la connection des vecteur de priorité
+SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
+ signal grant_latch : std_logic_vector(81 downto 1); 
+ signal priority_rotation_en : std_logic; 
+ signal Grant :  std_logic_vector(81 downto 1);
+ begin
+
+--validation de la rotation de priorité lorsque aucun port n'emet 
+ priority_rotation_en <= '1' when unsigned(priority_rotation) = 511 else 	'0'; 
+--latch servant qui memorise le signal grant pendant a transmission 
+grant_latch_process : process(clk)
+ begin 
+  if rising_edge(clk) then 
+   if reset = '1' then 
+ 		grant_latch <= (others => '0'); 
+ 	 elsif priority_rotation_en = '1' then 
+	   grant_latch <= Grant; 
+   end if; 
+   end if; 
+ end process; 
+ port_grant <= Grant and grant_latch; 
+ Grant(1)  <= Signal_grant(1)(1) or Signal_grant(10)(1); --  Grant(1,1)
+Grant(2)  <= Signal_grant(2)(2) or Signal_grant(11)(2); --  Grant(1,2)
+Grant(3)  <= Signal_grant(3)(3) or Signal_grant(12)(3); --  Grant(1,3)
+Grant(4)  <= Signal_grant(4)(4) or Signal_grant(13)(4); --  Grant(1,4)
+Grant(5)  <= Signal_grant(5)(5) or Signal_grant(14)(5); --  Grant(1,5)
+Grant(6)  <= Signal_grant(6)(6) or Signal_grant(15)(6); --  Grant(1,6)
+Grant(7)  <= Signal_grant(7)(7) or Signal_grant(16)(7); --  Grant(1,7)
+Grant(8)  <= Signal_grant(8)(8) or Signal_grant(17)(8); --  Grant(1,8)
+Grant(9)  <= Signal_grant(9)(9) ;                      --  Grant(1,9)
+Grant(10)  <= Signal_grant(2)(1) or Signal_grant(11)(1); --  Grant(2,1)
+Grant(11)  <= Signal_grant(3)(2) or Signal_grant(12)(2); --  Grant(2,2)
+Grant(12)  <= Signal_grant(4)(3) or Signal_grant(13)(3); --  Grant(2,3)
+Grant(13)  <= Signal_grant(5)(4) or Signal_grant(14)(4); --  Grant(2,4)
+Grant(14)  <= Signal_grant(6)(5) or Signal_grant(15)(5); --  Grant(2,5)
+Grant(15)  <= Signal_grant(7)(6) or Signal_grant(16)(6); --  Grant(2,6)
+Grant(16)  <= Signal_grant(8)(7) or Signal_grant(17)(7); --  Grant(2,7)
+Grant(17)  <= Signal_grant(9)(8) ;                      --  Grant(2,8)
+Grant(18)  <= Signal_grant(1)(9) or Signal_grant(10)(9); --  Grant(2,9)
+Grant(19)  <= Signal_grant(3)(1) or Signal_grant(12)(1); --  Grant(3,1)
+Grant(20)  <= Signal_grant(4)(2) or Signal_grant(13)(2); --  Grant(3,2)
+Grant(21)  <= Signal_grant(5)(3) or Signal_grant(14)(3); --  Grant(3,3)
+Grant(22)  <= Signal_grant(6)(4) or Signal_grant(15)(4); --  Grant(3,4)
+Grant(23)  <= Signal_grant(7)(5) or Signal_grant(16)(5); --  Grant(3,5)
+Grant(24)  <= Signal_grant(8)(6) or Signal_grant(17)(6); --  Grant(3,6)
+Grant(25)  <= Signal_grant(9)(7) ;                      --  Grant(3,7)
+Grant(26)  <= Signal_grant(1)(8) or Signal_grant(10)(8); --  Grant(3,8)
+Grant(27)  <= Signal_grant(2)(9) or Signal_grant(11)(9); --  Grant(3,9)
+Grant(28)  <= Signal_grant(4)(1) or Signal_grant(13)(1); --  Grant(4,1)
+Grant(29)  <= Signal_grant(5)(2) or Signal_grant(14)(2); --  Grant(4,2)
+Grant(30)  <= Signal_grant(6)(3) or Signal_grant(15)(3); --  Grant(4,3)
+Grant(31)  <= Signal_grant(7)(4) or Signal_grant(16)(4); --  Grant(4,4)
+Grant(32)  <= Signal_grant(8)(5) or Signal_grant(17)(5); --  Grant(4,5)
+Grant(33)  <= Signal_grant(9)(6) ;                      --  Grant(4,6)
+Grant(34)  <= Signal_grant(1)(7) or Signal_grant(10)(7); --  Grant(4,7)
+Grant(35)  <= Signal_grant(2)(8) or Signal_grant(11)(8); --  Grant(4,8)
+Grant(36)  <= Signal_grant(3)(9) or Signal_grant(12)(9); --  Grant(4,9)
+Grant(37)  <= Signal_grant(5)(1) or Signal_grant(14)(1); --  Grant(5,1)
+Grant(38)  <= Signal_grant(6)(2) or Signal_grant(15)(2); --  Grant(5,2)
+Grant(39)  <= Signal_grant(7)(3) or Signal_grant(16)(3); --  Grant(5,3)
+Grant(40)  <= Signal_grant(8)(4) or Signal_grant(17)(4); --  Grant(5,4)
+Grant(41)  <= Signal_grant(9)(5) ;                      --  Grant(5,5)
+Grant(42)  <= Signal_grant(1)(6) or Signal_grant(10)(6); --  Grant(5,6)
+Grant(43)  <= Signal_grant(2)(7) or Signal_grant(11)(7); --  Grant(5,7)
+Grant(44)  <= Signal_grant(3)(8) or Signal_grant(12)(8); --  Grant(5,8)
+Grant(45)  <= Signal_grant(4)(9) or Signal_grant(13)(9); --  Grant(5,9)
+Grant(46)  <= Signal_grant(6)(1) or Signal_grant(15)(1); --  Grant(6,1)
+Grant(47)  <= Signal_grant(7)(2) or Signal_grant(16)(2); --  Grant(6,2)
+Grant(48)  <= Signal_grant(8)(3) or Signal_grant(17)(3); --  Grant(6,3)
+Grant(49)  <= Signal_grant(9)(4) ;                      --  Grant(6,4)
+Grant(50)  <= Signal_grant(1)(5) or Signal_grant(10)(5); --  Grant(6,5)
+Grant(51)  <= Signal_grant(2)(6) or Signal_grant(11)(6); --  Grant(6,6)
+Grant(52)  <= Signal_grant(3)(7) or Signal_grant(12)(7); --  Grant(6,7)
+Grant(53)  <= Signal_grant(4)(8) or Signal_grant(13)(8); --  Grant(6,8)
+Grant(54)  <= Signal_grant(5)(9) or Signal_grant(14)(9); --  Grant(6,9)
+Grant(55)  <= Signal_grant(7)(1) or Signal_grant(16)(1); --  Grant(7,1)
+Grant(56)  <= Signal_grant(8)(2) or Signal_grant(17)(2); --  Grant(7,2)
+Grant(57)  <= Signal_grant(9)(3) ;                      --  Grant(7,3)
+Grant(58)  <= Signal_grant(1)(4) or Signal_grant(10)(4); --  Grant(7,4)
+Grant(59)  <= Signal_grant(2)(5) or Signal_grant(11)(5); --  Grant(7,5)
+Grant(60)  <= Signal_grant(3)(6) or Signal_grant(12)(6); --  Grant(7,6)
+Grant(61)  <= Signal_grant(4)(7) or Signal_grant(13)(7); --  Grant(7,7)
+Grant(62)  <= Signal_grant(5)(8) or Signal_grant(14)(8); --  Grant(7,8)
+Grant(63)  <= Signal_grant(6)(9) or Signal_grant(15)(9); --  Grant(7,9)
+Grant(64)  <= Signal_grant(8)(1) or Signal_grant(17)(1); --  Grant(8,1)
+Grant(65)  <= Signal_grant(9)(2) ;                      --  Grant(8,2)
+Grant(66)  <= Signal_grant(1)(3) or Signal_grant(10)(3); --  Grant(8,3)
+Grant(67)  <= Signal_grant(2)(4) or Signal_grant(11)(4); --  Grant(8,4)
+Grant(68)  <= Signal_grant(3)(5) or Signal_grant(12)(5); --  Grant(8,5)
+Grant(69)  <= Signal_grant(4)(6) or Signal_grant(13)(6); --  Grant(8,6)
+Grant(70)  <= Signal_grant(5)(7) or Signal_grant(14)(7); --  Grant(8,7)
+Grant(71)  <= Signal_grant(6)(8) or Signal_grant(15)(8); --  Grant(8,8)
+Grant(72)  <= Signal_grant(7)(9) or Signal_grant(16)(9); --  Grant(8,9)
+Grant(73)  <= Signal_grant(9)(1) ;                      --  Grant(9,1)
+Grant(74)  <= Signal_grant(1)(2) or Signal_grant(10)(2); --  Grant(9,2)
+Grant(75)  <= Signal_grant(2)(3) or Signal_grant(11)(3); --  Grant(9,3)
+Grant(76)  <= Signal_grant(3)(4) or Signal_grant(12)(4); --  Grant(9,4)
+Grant(77)  <= Signal_grant(4)(5) or Signal_grant(13)(5); --  Grant(9,5)
+Grant(78)  <= Signal_grant(5)(6) or Signal_grant(14)(6); --  Grant(9,6)
+Grant(79)  <= Signal_grant(6)(7) or Signal_grant(15)(7); --  Grant(9,7)
+Grant(80)  <= Signal_grant(7)(8) or Signal_grant(16)(8); --  Grant(9,8)
+Grant(81)  <= Signal_grant(8)(9) or Signal_grant(17)(9); --  Grant(9,9)
+High <= '1';
+
+----instantiations des cellules arbitres et interconnection
+
+-------------------------- Diagonale n° 1 
+
+
+Arbiter_1_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(1),  
+South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 
+
+Arbiter_1_2 : Arbiter
+
+PORT MAP (Request => Request(74), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(2),  
+South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 
+
+Arbiter_1_3 : Arbiter
+
+PORT MAP (Request => Request(66), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(3),  
+South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); 
+
+Arbiter_1_4 : Arbiter
+
+PORT MAP (Request => Request(58), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(4),  
+South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); 
+
+Arbiter_1_5 : Arbiter
+
+PORT MAP (Request => Request(50), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(5),  
+South => south_2_north(1)(5), East => east_2_west(1)(5) , Grant => Signal_grant(1)(5)); 
+
+Arbiter_1_6 : Arbiter
+
+PORT MAP (Request => Request(42), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(6),  
+South => south_2_north(1)(6), East => east_2_west(1)(6) , Grant => Signal_grant(1)(6)); 
+
+Arbiter_1_7 : Arbiter
+
+PORT MAP (Request => Request(34), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(7),  
+South => south_2_north(1)(7), East => east_2_west(1)(7) , Grant => Signal_grant(1)(7)); 
+
+Arbiter_1_8 : Arbiter
+
+PORT MAP (Request => Request(26), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(8),  
+South => south_2_north(1)(8), East => east_2_west(1)(8) , Grant => Signal_grant(1)(8)); 
+
+Arbiter_1_9 : Arbiter
+
+PORT MAP (Request => Request(18), North => High, West => High, P => Signal_priority(17), Fifo_full => Fifo_full(9),  
+South => south_2_north(1)(9), East => east_2_west(1)(9) , Grant => Signal_grant(1)(9)); 
+
+-------------------------- Diagonale n° 2 
+
+
+Arbiter_2_1 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(1)(1), West => east_2_west(1)(9), P => Signal_priority(16), Fifo_full => Fifo_full(1),  
+South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 
+
+Arbiter_2_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(16), Fifo_full => Fifo_full(2),  
+South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 
+
+Arbiter_2_3 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(16), Fifo_full => Fifo_full(3),  
+South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); 
+
+Arbiter_2_4 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(16), Fifo_full => Fifo_full(4),  
+South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); 
+
+Arbiter_2_5 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(1)(5), West => east_2_west(1)(4), P => Signal_priority(16), Fifo_full => Fifo_full(5),  
+South => south_2_north(2)(5), East => east_2_west(2)(5) , Grant => Signal_grant(2)(5)); 
+
+Arbiter_2_6 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(1)(6), West => east_2_west(1)(5), P => Signal_priority(16), Fifo_full => Fifo_full(6),  
+South => south_2_north(2)(6), East => east_2_west(2)(6) , Grant => Signal_grant(2)(6)); 
+
+Arbiter_2_7 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(1)(7), West => east_2_west(1)(6), P => Signal_priority(16), Fifo_full => Fifo_full(7),  
+South => south_2_north(2)(7), East => east_2_west(2)(7) , Grant => Signal_grant(2)(7)); 
+
+Arbiter_2_8 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(1)(8), West => east_2_west(1)(7), P => Signal_priority(16), Fifo_full => Fifo_full(8),  
+South => south_2_north(2)(8), East => east_2_west(2)(8) , Grant => Signal_grant(2)(8)); 
+
+Arbiter_2_9 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(1)(9), West => east_2_west(1)(8), P => Signal_priority(16), Fifo_full => Fifo_full(9),  
+South => south_2_north(2)(9), East => east_2_west(2)(9) , Grant => Signal_grant(2)(9)); 
+
+-------------------------- Diagonale n° 3 
+
+
+Arbiter_3_1 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(2)(1), West => east_2_west(2)(9), P => Signal_priority(15), Fifo_full => Fifo_full(1),  
+South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 
+
+Arbiter_3_2 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(15), Fifo_full => Fifo_full(2),  
+South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 
+
+Arbiter_3_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(15), Fifo_full => Fifo_full(3),  
+South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); 
+
+Arbiter_3_4 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(15), Fifo_full => Fifo_full(4),  
+South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); 
+
+Arbiter_3_5 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(2)(5), West => east_2_west(2)(4), P => Signal_priority(15), Fifo_full => Fifo_full(5),  
+South => south_2_north(3)(5), East => east_2_west(3)(5) , Grant => Signal_grant(3)(5)); 
+
+Arbiter_3_6 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(2)(6), West => east_2_west(2)(5), P => Signal_priority(15), Fifo_full => Fifo_full(6),  
+South => south_2_north(3)(6), East => east_2_west(3)(6) , Grant => Signal_grant(3)(6)); 
+
+Arbiter_3_7 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(2)(7), West => east_2_west(2)(6), P => Signal_priority(15), Fifo_full => Fifo_full(7),  
+South => south_2_north(3)(7), East => east_2_west(3)(7) , Grant => Signal_grant(3)(7)); 
+
+Arbiter_3_8 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(2)(8), West => east_2_west(2)(7), P => Signal_priority(15), Fifo_full => Fifo_full(8),  
+South => south_2_north(3)(8), East => east_2_west(3)(8) , Grant => Signal_grant(3)(8)); 
+
+Arbiter_3_9 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(2)(9), West => east_2_west(2)(8), P => Signal_priority(15), Fifo_full => Fifo_full(9),  
+South => south_2_north(3)(9), East => east_2_west(3)(9) , Grant => Signal_grant(3)(9)); 
+
+-------------------------- Diagonale n° 4 
+
+
+Arbiter_4_1 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(3)(1), West => east_2_west(3)(9), P => Signal_priority(14), Fifo_full => Fifo_full(1),  
+South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); 
+
+Arbiter_4_2 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(14), Fifo_full => Fifo_full(2),  
+South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); 
+
+Arbiter_4_3 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(14), Fifo_full => Fifo_full(3),  
+South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); 
+
+Arbiter_4_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(14), Fifo_full => Fifo_full(4),  
+South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); 
+
+Arbiter_4_5 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(3)(5), West => east_2_west(3)(4), P => Signal_priority(14), Fifo_full => Fifo_full(5),  
+South => south_2_north(4)(5), East => east_2_west(4)(5) , Grant => Signal_grant(4)(5)); 
+
+Arbiter_4_6 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(3)(6), West => east_2_west(3)(5), P => Signal_priority(14), Fifo_full => Fifo_full(6),  
+South => south_2_north(4)(6), East => east_2_west(4)(6) , Grant => Signal_grant(4)(6)); 
+
+Arbiter_4_7 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(3)(7), West => east_2_west(3)(6), P => Signal_priority(14), Fifo_full => Fifo_full(7),  
+South => south_2_north(4)(7), East => east_2_west(4)(7) , Grant => Signal_grant(4)(7)); 
+
+Arbiter_4_8 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(3)(8), West => east_2_west(3)(7), P => Signal_priority(14), Fifo_full => Fifo_full(8),  
+South => south_2_north(4)(8), East => east_2_west(4)(8) , Grant => Signal_grant(4)(8)); 
+
+Arbiter_4_9 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(3)(9), West => east_2_west(3)(8), P => Signal_priority(14), Fifo_full => Fifo_full(9),  
+South => south_2_north(4)(9), East => east_2_west(4)(9) , Grant => Signal_grant(4)(9)); 
+
+-------------------------- Diagonale n° 5 
+
+
+Arbiter_5_1 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(4)(1), West => east_2_west(4)(9), P => Signal_priority(13), Fifo_full => Fifo_full(1),  
+South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); 
+
+Arbiter_5_2 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(13), Fifo_full => Fifo_full(2),  
+South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); 
+
+Arbiter_5_3 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(13), Fifo_full => Fifo_full(3),  
+South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); 
+
+Arbiter_5_4 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(13), Fifo_full => Fifo_full(4),  
+South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); 
+
+Arbiter_5_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(4)(5), West => east_2_west(4)(4), P => Signal_priority(13), Fifo_full => Fifo_full(5),  
+South => south_2_north(5)(5), East => east_2_west(5)(5) , Grant => Signal_grant(5)(5)); 
+
+Arbiter_5_6 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(4)(6), West => east_2_west(4)(5), P => Signal_priority(13), Fifo_full => Fifo_full(6),  
+South => south_2_north(5)(6), East => east_2_west(5)(6) , Grant => Signal_grant(5)(6)); 
+
+Arbiter_5_7 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(4)(7), West => east_2_west(4)(6), P => Signal_priority(13), Fifo_full => Fifo_full(7),  
+South => south_2_north(5)(7), East => east_2_west(5)(7) , Grant => Signal_grant(5)(7)); 
+
+Arbiter_5_8 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(4)(8), West => east_2_west(4)(7), P => Signal_priority(13), Fifo_full => Fifo_full(8),  
+South => south_2_north(5)(8), East => east_2_west(5)(8) , Grant => Signal_grant(5)(8)); 
+
+Arbiter_5_9 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(4)(9), West => east_2_west(4)(8), P => Signal_priority(13), Fifo_full => Fifo_full(9),  
+South => south_2_north(5)(9), East => east_2_west(5)(9) , Grant => Signal_grant(5)(9)); 
+
+-------------------------- Diagonale n° 6 
+
+
+Arbiter_6_1 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(5)(1), West => east_2_west(5)(9), P => Signal_priority(12), Fifo_full => Fifo_full(1),  
+South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); 
+
+Arbiter_6_2 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(12), Fifo_full => Fifo_full(2),  
+South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); 
+
+Arbiter_6_3 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(12), Fifo_full => Fifo_full(3),  
+South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); 
+
+Arbiter_6_4 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(12), Fifo_full => Fifo_full(4),  
+South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); 
+
+Arbiter_6_5 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(5)(5), West => east_2_west(5)(4), P => Signal_priority(12), Fifo_full => Fifo_full(5),  
+South => south_2_north(6)(5), East => east_2_west(6)(5) , Grant => Signal_grant(6)(5)); 
+
+Arbiter_6_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(5)(6), West => east_2_west(5)(5), P => Signal_priority(12), Fifo_full => Fifo_full(6),  
+South => south_2_north(6)(6), East => east_2_west(6)(6) , Grant => Signal_grant(6)(6)); 
+
+Arbiter_6_7 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(5)(7), West => east_2_west(5)(6), P => Signal_priority(12), Fifo_full => Fifo_full(7),  
+South => south_2_north(6)(7), East => east_2_west(6)(7) , Grant => Signal_grant(6)(7)); 
+
+Arbiter_6_8 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(5)(8), West => east_2_west(5)(7), P => Signal_priority(12), Fifo_full => Fifo_full(8),  
+South => south_2_north(6)(8), East => east_2_west(6)(8) , Grant => Signal_grant(6)(8)); 
+
+Arbiter_6_9 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(5)(9), West => east_2_west(5)(8), P => Signal_priority(12), Fifo_full => Fifo_full(9),  
+South => south_2_north(6)(9), East => east_2_west(6)(9) , Grant => Signal_grant(6)(9)); 
+
+-------------------------- Diagonale n° 7 
+
+
+Arbiter_7_1 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(6)(1), West => east_2_west(6)(9), P => Signal_priority(11), Fifo_full => Fifo_full(1),  
+South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); 
+
+Arbiter_7_2 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(11), Fifo_full => Fifo_full(2),  
+South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); 
+
+Arbiter_7_3 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(11), Fifo_full => Fifo_full(3),  
+South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); 
+
+Arbiter_7_4 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(11), Fifo_full => Fifo_full(4),  
+South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); 
+
+Arbiter_7_5 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(6)(5), West => east_2_west(6)(4), P => Signal_priority(11), Fifo_full => Fifo_full(5),  
+South => south_2_north(7)(5), East => east_2_west(7)(5) , Grant => Signal_grant(7)(5)); 
+
+Arbiter_7_6 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(6)(6), West => east_2_west(6)(5), P => Signal_priority(11), Fifo_full => Fifo_full(6),  
+South => south_2_north(7)(6), East => east_2_west(7)(6) , Grant => Signal_grant(7)(6)); 
+
+Arbiter_7_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(6)(7), West => east_2_west(6)(6), P => Signal_priority(11), Fifo_full => Fifo_full(7),  
+South => south_2_north(7)(7), East => east_2_west(7)(7) , Grant => Signal_grant(7)(7)); 
+
+Arbiter_7_8 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(6)(8), West => east_2_west(6)(7), P => Signal_priority(11), Fifo_full => Fifo_full(8),  
+South => south_2_north(7)(8), East => east_2_west(7)(8) , Grant => Signal_grant(7)(8)); 
+
+Arbiter_7_9 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(6)(9), West => east_2_west(6)(8), P => Signal_priority(11), Fifo_full => Fifo_full(9),  
+South => south_2_north(7)(9), East => east_2_west(7)(9) , Grant => Signal_grant(7)(9)); 
+
+-------------------------- Diagonale n° 8 
+
+
+Arbiter_8_1 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(7)(1), West => east_2_west(7)(9), P => Signal_priority(10), Fifo_full => Fifo_full(1),  
+South => south_2_north(8)(1), East => east_2_west(8)(1) , Grant => Signal_grant(8)(1)); 
+
+Arbiter_8_2 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(7)(2), West => east_2_west(7)(1), P => Signal_priority(10), Fifo_full => Fifo_full(2),  
+South => south_2_north(8)(2), East => east_2_west(8)(2) , Grant => Signal_grant(8)(2)); 
+
+Arbiter_8_3 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(7)(3), West => east_2_west(7)(2), P => Signal_priority(10), Fifo_full => Fifo_full(3),  
+South => south_2_north(8)(3), East => east_2_west(8)(3) , Grant => Signal_grant(8)(3)); 
+
+Arbiter_8_4 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(7)(4), West => east_2_west(7)(3), P => Signal_priority(10), Fifo_full => Fifo_full(4),  
+South => south_2_north(8)(4), East => east_2_west(8)(4) , Grant => Signal_grant(8)(4)); 
+
+Arbiter_8_5 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(7)(5), West => east_2_west(7)(4), P => Signal_priority(10), Fifo_full => Fifo_full(5),  
+South => south_2_north(8)(5), East => east_2_west(8)(5) , Grant => Signal_grant(8)(5)); 
+
+Arbiter_8_6 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(7)(6), West => east_2_west(7)(5), P => Signal_priority(10), Fifo_full => Fifo_full(6),  
+South => south_2_north(8)(6), East => east_2_west(8)(6) , Grant => Signal_grant(8)(6)); 
+
+Arbiter_8_7 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(7)(7), West => east_2_west(7)(6), P => Signal_priority(10), Fifo_full => Fifo_full(7),  
+South => south_2_north(8)(7), East => east_2_west(8)(7) , Grant => Signal_grant(8)(7)); 
+
+Arbiter_8_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(7)(8), West => east_2_west(7)(7), P => Signal_priority(10), Fifo_full => Fifo_full(8),  
+South => south_2_north(8)(8), East => east_2_west(8)(8) , Grant => Signal_grant(8)(8)); 
+
+Arbiter_8_9 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(7)(9), West => east_2_west(7)(8), P => Signal_priority(10), Fifo_full => Fifo_full(9),  
+South => south_2_north(8)(9), East => east_2_west(8)(9) , Grant => Signal_grant(8)(9)); 
+
+-------------------------- Diagonale n° 9 
+
+
+Arbiter_9_1 : Arbiter
+
+PORT MAP (Request => Request(73), North => south_2_north(8)(1), West => east_2_west(8)(9), P => Signal_priority(9), Fifo_full => Fifo_full(1),  
+South => south_2_north(9)(1), East => east_2_west(9)(1) , Grant => Signal_grant(9)(1)); 
+
+Arbiter_9_2 : Arbiter
+
+PORT MAP (Request => Request(65), North => south_2_north(8)(2), West => east_2_west(8)(1), P => Signal_priority(9), Fifo_full => Fifo_full(2),  
+South => south_2_north(9)(2), East => east_2_west(9)(2) , Grant => Signal_grant(9)(2)); 
+
+Arbiter_9_3 : Arbiter
+
+PORT MAP (Request => Request(57), North => south_2_north(8)(3), West => east_2_west(8)(2), P => Signal_priority(9), Fifo_full => Fifo_full(3),  
+South => south_2_north(9)(3), East => east_2_west(9)(3) , Grant => Signal_grant(9)(3)); 
+
+Arbiter_9_4 : Arbiter
+
+PORT MAP (Request => Request(49), North => south_2_north(8)(4), West => east_2_west(8)(3), P => Signal_priority(9), Fifo_full => Fifo_full(4),  
+South => south_2_north(9)(4), East => east_2_west(9)(4) , Grant => Signal_grant(9)(4)); 
+
+Arbiter_9_5 : Arbiter
+
+PORT MAP (Request => Request(41), North => south_2_north(8)(5), West => east_2_west(8)(4), P => Signal_priority(9), Fifo_full => Fifo_full(5),  
+South => south_2_north(9)(5), East => east_2_west(9)(5) , Grant => Signal_grant(9)(5)); 
+
+Arbiter_9_6 : Arbiter
+
+PORT MAP (Request => Request(33), North => south_2_north(8)(6), West => east_2_west(8)(5), P => Signal_priority(9), Fifo_full => Fifo_full(6),  
+South => south_2_north(9)(6), East => east_2_west(9)(6) , Grant => Signal_grant(9)(6)); 
+
+Arbiter_9_7 : Arbiter
+
+PORT MAP (Request => Request(25), North => south_2_north(8)(7), West => east_2_west(8)(6), P => Signal_priority(9), Fifo_full => Fifo_full(7),  
+South => south_2_north(9)(7), East => east_2_west(9)(7) , Grant => Signal_grant(9)(7)); 
+
+Arbiter_9_8 : Arbiter
+
+PORT MAP (Request => Request(17), North => south_2_north(8)(8), West => east_2_west(8)(7), P => Signal_priority(9), Fifo_full => Fifo_full(8),  
+South => south_2_north(9)(8), East => east_2_west(9)(8) , Grant => Signal_grant(9)(8)); 
+
+Arbiter_9_9 : Arbiter
+
+PORT MAP (Request => Request(9), North => south_2_north(8)(9), West => east_2_west(8)(8), P => Signal_priority(9), Fifo_full => Fifo_full(9),  
+South => south_2_north(9)(9), East => east_2_west(9)(9) , Grant => Signal_grant(9)(9)); 
+
+-------------------------- Diagonale n° 10 
+
+
+Arbiter_10_1 : Arbiter
+
+PORT MAP (Request => Request(1), North => south_2_north(9)(1), West => east_2_west(9)(9), P => Signal_priority(8), Fifo_full => Fifo_full(1),  
+South => south_2_north(10)(1), East => east_2_west(10)(1) , Grant => Signal_grant(10)(1)); 
+
+Arbiter_10_2 : Arbiter
+
+PORT MAP (Request => Request(74), North => south_2_north(9)(2), West => east_2_west(9)(1), P => Signal_priority(8), Fifo_full => Fifo_full(2),  
+South => south_2_north(10)(2), East => east_2_west(10)(2) , Grant => Signal_grant(10)(2)); 
+
+Arbiter_10_3 : Arbiter
+
+PORT MAP (Request => Request(66), North => south_2_north(9)(3), West => east_2_west(9)(2), P => Signal_priority(8), Fifo_full => Fifo_full(3),  
+South => south_2_north(10)(3), East => east_2_west(10)(3) , Grant => Signal_grant(10)(3)); 
+
+Arbiter_10_4 : Arbiter
+
+PORT MAP (Request => Request(58), North => south_2_north(9)(4), West => east_2_west(9)(3), P => Signal_priority(8), Fifo_full => Fifo_full(4),  
+South => south_2_north(10)(4), East => east_2_west(10)(4) , Grant => Signal_grant(10)(4)); 
+
+Arbiter_10_5 : Arbiter
+
+PORT MAP (Request => Request(50), North => south_2_north(9)(5), West => east_2_west(9)(4), P => Signal_priority(8), Fifo_full => Fifo_full(5),  
+South => south_2_north(10)(5), East => east_2_west(10)(5) , Grant => Signal_grant(10)(5)); 
+
+Arbiter_10_6 : Arbiter
+
+PORT MAP (Request => Request(42), North => south_2_north(9)(6), West => east_2_west(9)(5), P => Signal_priority(8), Fifo_full => Fifo_full(6),  
+South => south_2_north(10)(6), East => east_2_west(10)(6) , Grant => Signal_grant(10)(6)); 
+
+Arbiter_10_7 : Arbiter
+
+PORT MAP (Request => Request(34), North => south_2_north(9)(7), West => east_2_west(9)(6), P => Signal_priority(8), Fifo_full => Fifo_full(7),  
+South => south_2_north(10)(7), East => east_2_west(10)(7) , Grant => Signal_grant(10)(7)); 
+
+Arbiter_10_8 : Arbiter
+
+PORT MAP (Request => Request(26), North => south_2_north(9)(8), West => east_2_west(9)(7), P => Signal_priority(8), Fifo_full => Fifo_full(8),  
+South => south_2_north(10)(8), East => east_2_west(10)(8) , Grant => Signal_grant(10)(8)); 
+
+Arbiter_10_9 : Arbiter
+
+PORT MAP (Request => Request(18), North => south_2_north(9)(9), West => east_2_west(9)(8), P => Signal_priority(8), Fifo_full => Fifo_full(9),  
+South => south_2_north(10)(9), East => east_2_west(10)(9) , Grant => Signal_grant(10)(9)); 
+
+-------------------------- Diagonale n° 11 
+
+
+Arbiter_11_1 : Arbiter
+
+PORT MAP (Request => Request(10), North => south_2_north(10)(1), West => east_2_west(10)(9), P => Signal_priority(7), Fifo_full => Fifo_full(1),  
+South => south_2_north(11)(1), East => east_2_west(11)(1) , Grant => Signal_grant(11)(1)); 
+
+Arbiter_11_2 : Arbiter
+
+PORT MAP (Request => Request(2), North => south_2_north(10)(2), West => east_2_west(10)(1), P => Signal_priority(7), Fifo_full => Fifo_full(2),  
+South => south_2_north(11)(2), East => east_2_west(11)(2) , Grant => Signal_grant(11)(2)); 
+
+Arbiter_11_3 : Arbiter
+
+PORT MAP (Request => Request(75), North => south_2_north(10)(3), West => east_2_west(10)(2), P => Signal_priority(7), Fifo_full => Fifo_full(3),  
+South => south_2_north(11)(3), East => east_2_west(11)(3) , Grant => Signal_grant(11)(3)); 
+
+Arbiter_11_4 : Arbiter
+
+PORT MAP (Request => Request(67), North => south_2_north(10)(4), West => east_2_west(10)(3), P => Signal_priority(7), Fifo_full => Fifo_full(4),  
+South => south_2_north(11)(4), East => east_2_west(11)(4) , Grant => Signal_grant(11)(4)); 
+
+Arbiter_11_5 : Arbiter
+
+PORT MAP (Request => Request(59), North => south_2_north(10)(5), West => east_2_west(10)(4), P => Signal_priority(7), Fifo_full => Fifo_full(5),  
+South => south_2_north(11)(5), East => east_2_west(11)(5) , Grant => Signal_grant(11)(5)); 
+
+Arbiter_11_6 : Arbiter
+
+PORT MAP (Request => Request(51), North => south_2_north(10)(6), West => east_2_west(10)(5), P => Signal_priority(7), Fifo_full => Fifo_full(6),  
+South => south_2_north(11)(6), East => east_2_west(11)(6) , Grant => Signal_grant(11)(6)); 
+
+Arbiter_11_7 : Arbiter
+
+PORT MAP (Request => Request(43), North => south_2_north(10)(7), West => east_2_west(10)(6), P => Signal_priority(7), Fifo_full => Fifo_full(7),  
+South => south_2_north(11)(7), East => east_2_west(11)(7) , Grant => Signal_grant(11)(7)); 
+
+Arbiter_11_8 : Arbiter
+
+PORT MAP (Request => Request(35), North => south_2_north(10)(8), West => east_2_west(10)(7), P => Signal_priority(7), Fifo_full => Fifo_full(8),  
+South => south_2_north(11)(8), East => east_2_west(11)(8) , Grant => Signal_grant(11)(8)); 
+
+Arbiter_11_9 : Arbiter
+
+PORT MAP (Request => Request(27), North => south_2_north(10)(9), West => east_2_west(10)(8), P => Signal_priority(7), Fifo_full => Fifo_full(9),  
+South => south_2_north(11)(9), East => east_2_west(11)(9) , Grant => Signal_grant(11)(9)); 
+
+-------------------------- Diagonale n° 12 
+
+
+Arbiter_12_1 : Arbiter
+
+PORT MAP (Request => Request(19), North => south_2_north(11)(1), West => east_2_west(11)(9), P => Signal_priority(6), Fifo_full => Fifo_full(1),  
+South => south_2_north(12)(1), East => east_2_west(12)(1) , Grant => Signal_grant(12)(1)); 
+
+Arbiter_12_2 : Arbiter
+
+PORT MAP (Request => Request(11), North => south_2_north(11)(2), West => east_2_west(11)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2),  
+South => south_2_north(12)(2), East => east_2_west(12)(2) , Grant => Signal_grant(12)(2)); 
+
+Arbiter_12_3 : Arbiter
+
+PORT MAP (Request => Request(3), North => south_2_north(11)(3), West => east_2_west(11)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3),  
+South => south_2_north(12)(3), East => east_2_west(12)(3) , Grant => Signal_grant(12)(3)); 
+
+Arbiter_12_4 : Arbiter
+
+PORT MAP (Request => Request(76), North => south_2_north(11)(4), West => east_2_west(11)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4),  
+South => south_2_north(12)(4), East => east_2_west(12)(4) , Grant => Signal_grant(12)(4)); 
+
+Arbiter_12_5 : Arbiter
+
+PORT MAP (Request => Request(68), North => south_2_north(11)(5), West => east_2_west(11)(4), P => Signal_priority(6), Fifo_full => Fifo_full(5),  
+South => south_2_north(12)(5), East => east_2_west(12)(5) , Grant => Signal_grant(12)(5)); 
+
+Arbiter_12_6 : Arbiter
+
+PORT MAP (Request => Request(60), North => south_2_north(11)(6), West => east_2_west(11)(5), P => Signal_priority(6), Fifo_full => Fifo_full(6),  
+South => south_2_north(12)(6), East => east_2_west(12)(6) , Grant => Signal_grant(12)(6)); 
+
+Arbiter_12_7 : Arbiter
+
+PORT MAP (Request => Request(52), North => south_2_north(11)(7), West => east_2_west(11)(6), P => Signal_priority(6), Fifo_full => Fifo_full(7),  
+South => south_2_north(12)(7), East => east_2_west(12)(7) , Grant => Signal_grant(12)(7)); 
+
+Arbiter_12_8 : Arbiter
+
+PORT MAP (Request => Request(44), North => south_2_north(11)(8), West => east_2_west(11)(7), P => Signal_priority(6), Fifo_full => Fifo_full(8),  
+South => south_2_north(12)(8), East => east_2_west(12)(8) , Grant => Signal_grant(12)(8)); 
+
+Arbiter_12_9 : Arbiter
+
+PORT MAP (Request => Request(36), North => south_2_north(11)(9), West => east_2_west(11)(8), P => Signal_priority(6), Fifo_full => Fifo_full(9),  
+South => south_2_north(12)(9), East => east_2_west(12)(9) , Grant => Signal_grant(12)(9)); 
+
+-------------------------- Diagonale n° 13 
+
+
+Arbiter_13_1 : Arbiter
+
+PORT MAP (Request => Request(28), North => south_2_north(12)(1), West => east_2_west(12)(9), P => Signal_priority(5), Fifo_full => Fifo_full(1),  
+South => south_2_north(13)(1), East => east_2_west(13)(1) , Grant => Signal_grant(13)(1)); 
+
+Arbiter_13_2 : Arbiter
+
+PORT MAP (Request => Request(20), North => south_2_north(12)(2), West => east_2_west(12)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2),  
+South => south_2_north(13)(2), East => east_2_west(13)(2) , Grant => Signal_grant(13)(2)); 
+
+Arbiter_13_3 : Arbiter
+
+PORT MAP (Request => Request(12), North => south_2_north(12)(3), West => east_2_west(12)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3),  
+South => south_2_north(13)(3), East => east_2_west(13)(3) , Grant => Signal_grant(13)(3)); 
+
+Arbiter_13_4 : Arbiter
+
+PORT MAP (Request => Request(4), North => south_2_north(12)(4), West => east_2_west(12)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4),  
+South => south_2_north(13)(4), East => east_2_west(13)(4) , Grant => Signal_grant(13)(4)); 
+
+Arbiter_13_5 : Arbiter
+
+PORT MAP (Request => Request(77), North => south_2_north(12)(5), West => east_2_west(12)(4), P => Signal_priority(5), Fifo_full => Fifo_full(5),  
+South => south_2_north(13)(5), East => east_2_west(13)(5) , Grant => Signal_grant(13)(5)); 
+
+Arbiter_13_6 : Arbiter
+
+PORT MAP (Request => Request(69), North => south_2_north(12)(6), West => east_2_west(12)(5), P => Signal_priority(5), Fifo_full => Fifo_full(6),  
+South => south_2_north(13)(6), East => east_2_west(13)(6) , Grant => Signal_grant(13)(6)); 
+
+Arbiter_13_7 : Arbiter
+
+PORT MAP (Request => Request(61), North => south_2_north(12)(7), West => east_2_west(12)(6), P => Signal_priority(5), Fifo_full => Fifo_full(7),  
+South => south_2_north(13)(7), East => east_2_west(13)(7) , Grant => Signal_grant(13)(7)); 
+
+Arbiter_13_8 : Arbiter
+
+PORT MAP (Request => Request(53), North => south_2_north(12)(8), West => east_2_west(12)(7), P => Signal_priority(5), Fifo_full => Fifo_full(8),  
+South => south_2_north(13)(8), East => east_2_west(13)(8) , Grant => Signal_grant(13)(8)); 
+
+Arbiter_13_9 : Arbiter
+
+PORT MAP (Request => Request(45), North => south_2_north(12)(9), West => east_2_west(12)(8), P => Signal_priority(5), Fifo_full => Fifo_full(9),  
+South => south_2_north(13)(9), East => east_2_west(13)(9) , Grant => Signal_grant(13)(9)); 
+
+-------------------------- Diagonale n° 14 
+
+
+Arbiter_14_1 : Arbiter
+
+PORT MAP (Request => Request(37), North => south_2_north(13)(1), West => east_2_west(13)(9), P => Signal_priority(4), Fifo_full => Fifo_full(1),  
+South => south_2_north(14)(1), East => east_2_west(14)(1) , Grant => Signal_grant(14)(1)); 
+
+Arbiter_14_2 : Arbiter
+
+PORT MAP (Request => Request(29), North => south_2_north(13)(2), West => east_2_west(13)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2),  
+South => south_2_north(14)(2), East => east_2_west(14)(2) , Grant => Signal_grant(14)(2)); 
+
+Arbiter_14_3 : Arbiter
+
+PORT MAP (Request => Request(21), North => south_2_north(13)(3), West => east_2_west(13)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3),  
+South => south_2_north(14)(3), East => east_2_west(14)(3) , Grant => Signal_grant(14)(3)); 
+
+Arbiter_14_4 : Arbiter
+
+PORT MAP (Request => Request(13), North => south_2_north(13)(4), West => east_2_west(13)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4),  
+South => south_2_north(14)(4), East => east_2_west(14)(4) , Grant => Signal_grant(14)(4)); 
+
+Arbiter_14_5 : Arbiter
+
+PORT MAP (Request => Request(5), North => south_2_north(13)(5), West => east_2_west(13)(4), P => Signal_priority(4), Fifo_full => Fifo_full(5),  
+South => south_2_north(14)(5), East => east_2_west(14)(5) , Grant => Signal_grant(14)(5)); 
+
+Arbiter_14_6 : Arbiter
+
+PORT MAP (Request => Request(78), North => south_2_north(13)(6), West => east_2_west(13)(5), P => Signal_priority(4), Fifo_full => Fifo_full(6),  
+South => south_2_north(14)(6), East => east_2_west(14)(6) , Grant => Signal_grant(14)(6)); 
+
+Arbiter_14_7 : Arbiter
+
+PORT MAP (Request => Request(70), North => south_2_north(13)(7), West => east_2_west(13)(6), P => Signal_priority(4), Fifo_full => Fifo_full(7),  
+South => south_2_north(14)(7), East => east_2_west(14)(7) , Grant => Signal_grant(14)(7)); 
+
+Arbiter_14_8 : Arbiter
+
+PORT MAP (Request => Request(62), North => south_2_north(13)(8), West => east_2_west(13)(7), P => Signal_priority(4), Fifo_full => Fifo_full(8),  
+South => south_2_north(14)(8), East => east_2_west(14)(8) , Grant => Signal_grant(14)(8)); 
+
+Arbiter_14_9 : Arbiter
+
+PORT MAP (Request => Request(54), North => south_2_north(13)(9), West => east_2_west(13)(8), P => Signal_priority(4), Fifo_full => Fifo_full(9),  
+South => south_2_north(14)(9), East => east_2_west(14)(9) , Grant => Signal_grant(14)(9)); 
+
+-------------------------- Diagonale n° 15 
+
+
+Arbiter_15_1 : Arbiter
+
+PORT MAP (Request => Request(46), North => south_2_north(14)(1), West => east_2_west(14)(9), P => Signal_priority(3), Fifo_full => Fifo_full(1),  
+South => south_2_north(15)(1), East => east_2_west(15)(1) , Grant => Signal_grant(15)(1)); 
+
+Arbiter_15_2 : Arbiter
+
+PORT MAP (Request => Request(38), North => south_2_north(14)(2), West => east_2_west(14)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2),  
+South => south_2_north(15)(2), East => east_2_west(15)(2) , Grant => Signal_grant(15)(2)); 
+
+Arbiter_15_3 : Arbiter
+
+PORT MAP (Request => Request(30), North => south_2_north(14)(3), West => east_2_west(14)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3),  
+South => south_2_north(15)(3), East => east_2_west(15)(3) , Grant => Signal_grant(15)(3)); 
+
+Arbiter_15_4 : Arbiter
+
+PORT MAP (Request => Request(22), North => south_2_north(14)(4), West => east_2_west(14)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4),  
+South => south_2_north(15)(4), East => east_2_west(15)(4) , Grant => Signal_grant(15)(4)); 
+
+Arbiter_15_5 : Arbiter
+
+PORT MAP (Request => Request(14), North => south_2_north(14)(5), West => east_2_west(14)(4), P => Signal_priority(3), Fifo_full => Fifo_full(5),  
+South => south_2_north(15)(5), East => east_2_west(15)(5) , Grant => Signal_grant(15)(5)); 
+
+Arbiter_15_6 : Arbiter
+
+PORT MAP (Request => Request(6), North => south_2_north(14)(6), West => east_2_west(14)(5), P => Signal_priority(3), Fifo_full => Fifo_full(6),  
+South => south_2_north(15)(6), East => east_2_west(15)(6) , Grant => Signal_grant(15)(6)); 
+
+Arbiter_15_7 : Arbiter
+
+PORT MAP (Request => Request(79), North => south_2_north(14)(7), West => east_2_west(14)(6), P => Signal_priority(3), Fifo_full => Fifo_full(7),  
+South => south_2_north(15)(7), East => east_2_west(15)(7) , Grant => Signal_grant(15)(7)); 
+
+Arbiter_15_8 : Arbiter
+
+PORT MAP (Request => Request(71), North => south_2_north(14)(8), West => east_2_west(14)(7), P => Signal_priority(3), Fifo_full => Fifo_full(8),  
+South => south_2_north(15)(8), East => east_2_west(15)(8) , Grant => Signal_grant(15)(8)); 
+
+Arbiter_15_9 : Arbiter
+
+PORT MAP (Request => Request(63), North => south_2_north(14)(9), West => east_2_west(14)(8), P => Signal_priority(3), Fifo_full => Fifo_full(9),  
+South => south_2_north(15)(9), East => east_2_west(15)(9) , Grant => Signal_grant(15)(9)); 
+
+-------------------------- Diagonale n° 16 
+
+
+Arbiter_16_1 : Arbiter
+
+PORT MAP (Request => Request(55), North => south_2_north(15)(1), West => east_2_west(15)(9), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
+South => south_2_north(16)(1), East => east_2_west(16)(1) , Grant => Signal_grant(16)(1)); 
+
+Arbiter_16_2 : Arbiter
+
+PORT MAP (Request => Request(47), North => south_2_north(15)(2), West => east_2_west(15)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
+South => south_2_north(16)(2), East => east_2_west(16)(2) , Grant => Signal_grant(16)(2)); 
+
+Arbiter_16_3 : Arbiter
+
+PORT MAP (Request => Request(39), North => south_2_north(15)(3), West => east_2_west(15)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3),  
+South => south_2_north(16)(3), East => east_2_west(16)(3) , Grant => Signal_grant(16)(3)); 
+
+Arbiter_16_4 : Arbiter
+
+PORT MAP (Request => Request(31), North => south_2_north(15)(4), West => east_2_west(15)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4),  
+South => south_2_north(16)(4), East => east_2_west(16)(4) , Grant => Signal_grant(16)(4)); 
+
+Arbiter_16_5 : Arbiter
+
+PORT MAP (Request => Request(23), North => south_2_north(15)(5), West => east_2_west(15)(4), P => Signal_priority(2), Fifo_full => Fifo_full(5),  
+South => south_2_north(16)(5), East => east_2_west(16)(5) , Grant => Signal_grant(16)(5)); 
+
+Arbiter_16_6 : Arbiter
+
+PORT MAP (Request => Request(15), North => south_2_north(15)(6), West => east_2_west(15)(5), P => Signal_priority(2), Fifo_full => Fifo_full(6),  
+South => south_2_north(16)(6), East => east_2_west(16)(6) , Grant => Signal_grant(16)(6)); 
+
+Arbiter_16_7 : Arbiter
+
+PORT MAP (Request => Request(7), North => south_2_north(15)(7), West => east_2_west(15)(6), P => Signal_priority(2), Fifo_full => Fifo_full(7),  
+South => south_2_north(16)(7), East => east_2_west(16)(7) , Grant => Signal_grant(16)(7)); 
+
+Arbiter_16_8 : Arbiter
+
+PORT MAP (Request => Request(80), North => south_2_north(15)(8), West => east_2_west(15)(7), P => Signal_priority(2), Fifo_full => Fifo_full(8),  
+South => south_2_north(16)(8), East => east_2_west(16)(8) , Grant => Signal_grant(16)(8)); 
+
+Arbiter_16_9 : Arbiter
+
+PORT MAP (Request => Request(72), North => south_2_north(15)(9), West => east_2_west(15)(8), P => Signal_priority(2), Fifo_full => Fifo_full(9),  
+South => south_2_north(16)(9), East => east_2_west(16)(9) , Grant => Signal_grant(16)(9)); 
+
+-------------------------- Diagonale n° 17 
+
+
+Arbiter_17_1 : Arbiter
+
+PORT MAP (Request => Request(64), North => south_2_north(16)(1), West => east_2_west(16)(9), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
+South => south_2_north(17)(1), East => east_2_west(17)(1) , Grant => Signal_grant(17)(1)); 
+
+Arbiter_17_2 : Arbiter
+
+PORT MAP (Request => Request(56), North => south_2_north(16)(2), West => east_2_west(16)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
+South => south_2_north(17)(2), East => east_2_west(17)(2) , Grant => Signal_grant(17)(2)); 
+
+Arbiter_17_3 : Arbiter
+
+PORT MAP (Request => Request(48), North => south_2_north(16)(3), West => east_2_west(16)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3),  
+South => south_2_north(17)(3), East => east_2_west(17)(3) , Grant => Signal_grant(17)(3)); 
+
+Arbiter_17_4 : Arbiter
+
+PORT MAP (Request => Request(40), North => south_2_north(16)(4), West => east_2_west(16)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4),  
+South => south_2_north(17)(4), East => east_2_west(17)(4) , Grant => Signal_grant(17)(4)); 
+
+Arbiter_17_5 : Arbiter
+
+PORT MAP (Request => Request(32), North => south_2_north(16)(5), West => east_2_west(16)(4), P => Signal_priority(1), Fifo_full => Fifo_full(5),  
+South => south_2_north(17)(5), East => east_2_west(17)(5) , Grant => Signal_grant(17)(5)); 
+
+Arbiter_17_6 : Arbiter
+
+PORT MAP (Request => Request(24), North => south_2_north(16)(6), West => east_2_west(16)(5), P => Signal_priority(1), Fifo_full => Fifo_full(6),  
+South => south_2_north(17)(6), East => east_2_west(17)(6) , Grant => Signal_grant(17)(6)); 
+
+Arbiter_17_7 : Arbiter
+
+PORT MAP (Request => Request(16), North => south_2_north(16)(7), West => east_2_west(16)(6), P => Signal_priority(1), Fifo_full => Fifo_full(7),  
+South => south_2_north(17)(7), East => east_2_west(17)(7) , Grant => Signal_grant(17)(7)); 
+
+Arbiter_17_8 : Arbiter
+
+PORT MAP (Request => Request(8), North => south_2_north(16)(8), West => east_2_west(16)(7), P => Signal_priority(1), Fifo_full => Fifo_full(8),  
+South => south_2_north(17)(8), East => east_2_west(17)(8) , Grant => Signal_grant(17)(8)); 
+
+Arbiter_17_9 : Arbiter
+
+PORT MAP (Request => Request(81), North => south_2_north(16)(9), West => east_2_west(16)(8), P => Signal_priority(1), Fifo_full => Fifo_full(9),  
+South => south_2_north(17)(9), East => east_2_west(17)(9) , Grant => Signal_grant(17)(9)); 
+
+
+--processus permettant de roter la priorité des diagonales à chaque front d'horloge
+ -- rotation round robin
+	 round_robin : process(clk)
+	begin
+		if rising_edge(clk) then
+		 if reset ='1' then
+		    Signal_priority <= "11111111100000000";
+		  elsif priority_rotation_en = '1' then 
+ 		    case Signal_priority is
+		       when "11111111100000000" => Signal_priority <= "01111111110000000";
+		       when "01111111110000000" => Signal_priority <= "00111111111000000";
+		       when "00111111111000000" => Signal_priority <= "00011111111100000";
+		       when "00011111111100000" => Signal_priority <= "00001111111110000";
+		       when "00001111111110000" => Signal_priority <= "00000111111111000";
+		       when "00000111111111000" => Signal_priority <= "00000011111111100";
+		       when "00000011111111100" => Signal_priority <= "00000001111111110";
+		       when "00000001111111110" => Signal_priority <= "00000000111111111";
+		       when "00000000111111111" => Signal_priority <= "11111111100000000";
+		       when others    => Signal_priority <= "11111111100000000";
+		  end case;
+		 end if;
+	     end if;
+	 end process;
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GEN.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GEN.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GEN.vhd	(revision 20)
@@ -0,0 +1,7432 @@
+----------------------------------------------------------------------------------
+-- Company: ENSET 2011
+-- Engineer: GAMOM NGOUNOU
+-- 
+-- Create Date:    03:40:47 11/19/2011 
+-- Design Name: 
+-- Module Name:    SWITCH_GEN - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+-- fichier principal du switch générique; en fonction du parametre generique le 
+-- les directive de generation conditionnelle permettent de ne générer et synthétiser uniquement  la logique 
+-- nécessaire à l'implémentation  du switch de la dimension voulue
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.Coretypes.all ;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity SWITCH_GEN is 
+ --type portio is array(positive range) of std_logic_vector (7 downto 0);    
+ generic(number_of_ports : positive := 8);
+     port(
+	        -- ports d'entree
+           Port_in : in typ_portIO(1 to number_of_ports) ;
+--			  Port1_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--           Port2_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--           Port3_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--           Port4_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--			  Port5_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--           Port6_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--           Port7_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--           Port8_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--			  Port9_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+--           Port10_in : in  STD_LOGIC_VECTOR (7 downto 0);
+--           Port11_in : in  STD_LOGIC_VECTOR (7 downto 0);
+--           Port12_in : in  STD_LOGIC_VECTOR (7 downto 0);
+--			  Port13_in : in  STD_LOGIC_VECTOR (7 downto 0);
+--           Port14_in : in  STD_LOGIC_VECTOR (7 downto 0);
+--           Port15_in : in  STD_LOGIC_VECTOR (7 downto 0);
+--           Port16_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			 
+			  -- port de sortie
+			  Port_out : out  typ_portIO(1 to number_of_ports);
+--			  Port1_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port2_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port3_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port4_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--			  Port5_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port6_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port7_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port8_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--			  Port9_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port10_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port11_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port12_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--			  Port13_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port14_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port15_out : out  STD_LOGIC_VECTOR (7 downto 0);
+--           Port16_out : out  STD_LOGIC_VECTOR (7 downto 0);
+			  -- signaux de controle
+			  data_in_en : in std_logic_vector(number_of_ports downto 1);
+			  cmd_in_en :  in std_logic_vector(number_of_ports downto 1);
+			  data_out_en : in std_logic_vector(number_of_ports downto 1);
+			  fifo_in_full : out std_logic_vector(number_of_ports downto 1);
+			  fifo_in_empty : out std_logic_vector(number_of_ports downto 1);
+			  data_available : out std_logic_vector(number_of_ports downto 1);
+			  clk       : in   STD_LOGIC;
+			  reset     : in   STD_LOGIC);
+end SWITCH_GEN;
+
+architecture Behavioral of SWITCH_GEN is
+-- declaration des modules du switch generique
+-- le module de gestion des ports d'entrée
+
+COMPONENT INPUT_PORT_MODULE
+  generic(number_of_ports : positive := 4;
+			Port_num: natural);
+    Port ( data_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           data_in_en : in  STD_LOGIC;
+			  cmd_in_en : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+			  clk   : in  STD_LOGIC;
+			  request : out  STD_LOGIC_VECTOR (number_of_ports downto 1);
+           grant : in  STD_LOGIC_VECTOR (number_of_ports  downto 1);			  
+           fifo_full : out  STD_LOGIC;
+			  fifo_empty : out  STD_LOGIC;
+			  priority_rotation : out std_logic;
+           data_out : out  STD_LOGIC_VECTOR (7 downto 0);
+			  data_out_pulse : out std_logic);
+END COMPONENT;
+
+-- le module des ports de sortie
+
+COMPONENT OUTPUT_PORT_MODULE
+	PORT(
+		data_in : IN std_logic_vector(7 downto 0);
+		reset : IN std_logic;
+		clk : IN std_logic;
+		wr_en : IN std_logic;
+		rd_out_en : IN std_logic;          
+		data_out : OUT std_logic_vector(7 downto 0);
+		fifo_full : OUT std_logic;
+		data_avalaible : OUT std_logic
+		);
+END COMPONENT;
+	
+-- le module du crossbar
+COMPONENT Crossbar
+ generic
+	      (
+			  number_of_crossbar_ports: positive := 4
+			);
+    Port ( 
+	        --Port_in : in Typ_PortIO(1 to number_of_crossbar_ports);
+			  Port1_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port2_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port3_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port4_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port5_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port6_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port7_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port8_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port9_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port10_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port13_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  
+			  --Port_pulse_in : in std_logic_vector(1 to number_of_ports);
+			  Port1_pulse_in : in std_logic;
+			  Port2_pulse_in : in std_logic;
+			  Port3_pulse_in : in std_logic;
+			  Port4_pulse_in : in std_logic;
+			  Port5_pulse_in : in std_logic;
+			  Port6_pulse_in : in std_logic;
+			  Port7_pulse_in : in std_logic;
+			  Port8_pulse_in : in std_logic;
+			  Port9_pulse_in : in std_logic;
+			  Port10_pulse_in : in std_logic;
+			  Port11_pulse_in : in std_logic;
+			  Port12_pulse_in : in std_logic;
+			  Port13_pulse_in : in std_logic;
+			  Port14_pulse_in : in std_logic;
+			  Port15_pulse_in : in std_logic;
+			  Port16_pulse_in : in std_logic;
+			  
+			  --Port_pulse_out : in std_logic_vector(1 to number_of_ports);
+			  Port1_pulse_out : out std_logic;
+			  Port2_pulse_out : out std_logic;
+			  Port3_pulse_out : out std_logic;
+			  Port4_pulse_out : out std_logic;
+			  Port5_pulse_out : out std_logic;
+			  Port6_pulse_out : out std_logic;
+			  Port7_pulse_out : out std_logic;
+			  Port8_pulse_out : out std_logic;
+			  Port9_pulse_out : out std_logic;
+			  Port10_pulse_out : out std_logic;
+			  Port11_pulse_out : out std_logic;
+			  Port12_pulse_out : out std_logic;
+			  Port13_pulse_out : out std_logic;
+			  Port14_pulse_out : out std_logic;
+			  Port15_pulse_out : out std_logic;
+			  Port16_pulse_out : out std_logic;
+			  
+			  --Port_out : out Typ_PortIO(1 to number_of_crossbar_ports);
+			  Port1_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port2_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port3_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port4_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port5_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port6_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port7_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port8_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port9_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port10_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port13_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  
+           Ctrl : in  STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1)
+       ); 
+ END COMPONENT;
+
+-- déclaration du  scheduler
+COMPONENT Scheduler
+	generic(number_of_ports : positive := 4);
+    Port ( Request : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
+			  Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1);
+           clk : in  STD_LOGIC;
+	        reset : in  STD_LOGIC;
+			  priority_rotation : in  STD_LOGIC_VECTOR (number_of_ports downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1));
+END COMPONENT;
+
+--declaration des signaux de connection entre les modules du switch
+--type port_connection_type is array(16 downto 1) of std_logic_vector(7 downto 1);
+--signal crossbar_port_in_connetion : port_connection_type;
+--signal crossbar_port_out_connetion :port_connection_type;
+--signal request_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
+--signal grant_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
+--signal priority_rotation_connection : std_logic_vector(number_of_ports downto 1);
+--signal fifo_out_full_connection : std_logic_vector(1 to number_of_ports);
+--signal crossbar_in_pulse(_connection : std_logic_vector(number_of_ports downto 1);
+--signal crossbar_out_pulse_connection : std_logic_vector(number_of_ports downto 1);
+--variable i,j : integer;
+
+Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
+Signal grant_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
+Signal priority_rotation_signal : STD_LOGIC_VECTOR(number_of_ports downto 1);
+signal fifo_out_full_signal : std_logic_vector(number_of_ports downto 1);
+
+signal crossbar_in_port :  Typ_PortIO(1 to number_of_ports);
+
+--signal crossbar_in_port1 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port2 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port3 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port4 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port5 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port6 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port7 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port8 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port9 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port10 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port11 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port12 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port13 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port14 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port15 : std_logic_vector(7 downto 0);
+--signal crossbar_in_port16 : std_logic_vector(7 downto 0);
+
+signal crossbar_out_port  :  Typ_PortIO(1 to number_of_ports);
+--signal crossbar_out_port1 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port2 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port3 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port4 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port5 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port6 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port7 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port8 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port9 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port10 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port11 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port12 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port13 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port14 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port15 : std_logic_vector(7 downto 0);
+--signal crossbar_out_port16 : std_logic_vector(7 downto 0);
+
+signal crossbar_in_pulse  : std_logic_vector(number_of_ports downto 1);
+--signal crossbar_in_pulse1 : std_logic;
+--signal crossbar_in_pulse2 : std_logic;
+--signal crossbar_in_pulse3 : std_logic;
+--signal crossbar_in_pulse4 : std_logic;
+--signal crossbar_in_pulse5 : std_logic;
+--signal crossbar_in_pulse6 : std_logic;
+--signal crossbar_in_pulse7 : std_logic;
+--signal crossbar_in_pulse8 : std_logic;
+--signal crossbar_in_pulse9 : std_logic;
+--signal crossbar_in_pulse10 : std_logic;
+--signal crossbar_in_pulse11 : std_logic;
+--signal crossbar_in_pulse12 : std_logic;
+--signal crossbar_in_pulse13 : std_logic;
+--signal crossbar_in_pulse14 : std_logic;
+--signal crossbar_in_pulse15 : std_logic;
+--signal crossbar_in_pulse16 : std_logic;
+
+signal crossbar_out_pulse  : std_logic_vector(number_of_ports downto 1);
+--signal crossbar_out_pulse1 : std_logic;
+--signal crossbar_out_pulse2 : std_logic;
+--signal crossbar_out_pulse3 : std_logic;
+--signal crossbar_out_pulse4 : std_logic;
+--signal crossbar_out_pulse5 : std_logic;
+--signal crossbar_out_pulse6 : std_logic;
+--signal crossbar_out_pulse7 : std_logic;
+--signal crossbar_out_pulse8 : std_logic;
+--signal crossbar_out_pulse9 : std_logic;
+--signal crossbar_out_pulse10 : std_logic;
+--signal crossbar_out_pulse11 : std_logic;
+--signal crossbar_out_pulse12 : std_logic;
+--signal crossbar_out_pulse13 : std_logic;
+--signal crossbar_out_pulse14 : std_logic;
+--signal crossbar_out_pulse15 : std_logic;
+--signal crossbar_out_pulse16 : std_logic;
+
+
+begin
+-- intstanciation et connexion des modules du switch en fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+switch2x2 : if number_of_ports = 2 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>2,Port_num=>1)
+PORT MAP(
+   data_in => Port_in(1),
+   data_in_en => data_in_en(1),
+	cmd_in_en => cmd_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port(1),
+   data_out_pulse =>crossbar_in_pulse(1),
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>2,Port_num=>2)
+PORT MAP(
+   data_in => Port_in(2),
+   data_in_en => data_in_en(2),
+	cmd_in_en => cmd_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(3),
+   grant(2) => grant_signal(4),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port(2),
+   data_out_pulse =>crossbar_in_pulse(2),
+   request(1) =>request_signal(3),
+   request(2) =>request_signal(4)
+);
+
+end generate switch2x2;
+
+
+-- switch 3 ports
+switch3x3 : if number_of_ports = 3 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>3,Port_num=>1)
+PORT MAP(
+   data_in => Port_in(1),
+   data_in_en => data_in_en(1),
+	cmd_in_en => cmd_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port(1),
+   data_out_pulse =>crossbar_in_pulse(1),
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>3,Port_num=>2)
+PORT MAP(
+   data_in => Port_in(2),
+   data_in_en => data_in_en(2),
+	cmd_in_en => cmd_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port(2),
+   data_out_pulse =>crossbar_in_pulse(2),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>3,Port_num=>3)
+PORT MAP(
+   data_in => Port_in(3),
+   data_in_en => data_in_en(3),
+	cmd_in_en => cmd_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port(3),
+   data_out_pulse =>crossbar_in_pulse(3),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9)
+);
+
+end generate switch3x3;
+
+
+-- switch 4 à 7 ports
+switch4x4_7x7 : if number_of_ports >= 4 and number_of_ports <=7 generate
+
+switch_4x4_7x7:for i in 1 to number_of_ports generate
+
+constant j: natural:=number_of_ports*(i-1);
+begin
+--j=number_of_ports*(i-1);
+PORTx4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>4,Port_num=>i)
+PORT MAP(
+   data_in => Port_in(i),
+   data_in_en => data_in_en(i),
+	cmd_in_en => cmd_in_en(i),
+   reset => reset,
+   clk =>clk,
+	grant =>grant_signal(j+NUMBER_OF_PORTS downto j+1),
+ 
+   fifo_full =>fifo_in_full(i),
+   priority_rotation =>  priority_rotation_signal(i),
+   fifo_empty => fifo_in_empty(i),
+   data_out =>crossbar_in_port(i),
+   data_out_pulse =>crossbar_in_pulse(i),
+	request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
+   
+);
+end generate switch_4x4_7x7;
+end generate switch4x4_7x7;
+
+
+---- switch 5 ports
+--switch5x5 : if number_of_ports = 5 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>5)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>5)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(6),
+--   grant(2) => grant_signal(7),
+--   grant(3) => grant_signal(8),
+--   grant(4) => grant_signal(9),
+--   grant(5) => grant_signal(10),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>5)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(11) => grant_signal(11),
+--   grant(12) => grant_signal(12),
+--   grant(13) => grant_signal(13),
+--   grant(14) => grant_signal(14),
+--   grant(15) => grant_signal(15),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(11) =>request_signal(11),
+--   request(12) =>request_signal(12),
+--   request(13) =>request_signal(13),
+--   request(14) =>request_signal(14),
+--   request(15) =>request_signal(15)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>5)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(16) => grant_signal(16),
+--   grant(17) => grant_signal(17),
+--   grant(18) => grant_signal(18),
+--   grant(19) => grant_signal(19),
+--   grant(20) => grant_signal(20),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(16) =>request_signal(16),
+--   request(17) =>request_signal(17),
+--   request(18) =>request_signal(18),
+--   request(19) =>request_signal(19),
+--   request(20) =>request_signal(20)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>5)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(21) => grant_signal(21),
+--   grant(22) => grant_signal(22),
+--   grant(23) => grant_signal(23),
+--   grant(24) => grant_signal(24),
+--   grant(25) => grant_signal(25),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(21) =>request_signal(21),
+--   request(22) =>request_signal(22),
+--   request(23) =>request_signal(23),
+--   request(24) =>request_signal(24),
+--   request(25) =>request_signal(25)
+--);
+--
+--end generate switch5x5;
+--
+--
+---- switch 6 ports
+--switch6x6 : if number_of_ports = 6 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>6)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--	cmd_in_en => cmd_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>6)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(7),
+--   grant(2) => grant_signal(8),
+--   grant(3) => grant_signal(9),
+--   grant(4) => grant_signal(10),
+--   grant(5) => grant_signal(11),
+--   grant(6) => grant_signal(12),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(1) =>request_signal(7),
+--   request(2) =>request_signal(8),
+--   request(3) =>request_signal(9),
+--   request(4) =>request_signal(10),
+--   request(5) =>request_signal(11),
+--   request(6) =>request_signal(12)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>6)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(13) => grant_signal(13),
+--   grant(14) => grant_signal(14),
+--   grant(15) => grant_signal(15),
+--   grant(16) => grant_signal(16),
+--   grant(17) => grant_signal(17),
+--   grant(18) => grant_signal(18),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(13) =>request_signal(13),
+--   request(14) =>request_signal(14),
+--   request(15) =>request_signal(15),
+--   request(16) =>request_signal(16),
+--   request(17) =>request_signal(17),
+--   request(18) =>request_signal(18)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>6)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--	cmd_in_en => cmd_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(19) => grant_signal(19),
+--   grant(20) => grant_signal(20),
+--   grant(21) => grant_signal(21),
+--   grant(22) => grant_signal(22),
+--   grant(23) => grant_signal(23),
+--   grant(24) => grant_signal(24),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(19) =>request_signal(19),
+--   request(20) =>request_signal(20),
+--   request(21) =>request_signal(21),
+--   request(22) =>request_signal(22),
+--   request(23) =>request_signal(23),
+--   request(24) =>request_signal(24)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>6)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--	cmd_in_en => cmd_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(25) => grant_signal(25),
+--   grant(26) => grant_signal(26),
+--   grant(27) => grant_signal(27),
+--   grant(28) => grant_signal(28),
+--   grant(29) => grant_signal(29),
+--   grant(30) => grant_signal(30),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(25) =>request_signal(25),
+--   request(26) =>request_signal(26),
+--   request(27) =>request_signal(27),
+--   request(28) =>request_signal(28),
+--   request(29) =>request_signal(29),
+--   request(30) =>request_signal(30)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>6)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(31) => grant_signal(31),
+--   grant(32) => grant_signal(32),
+--   grant(33) => grant_signal(33),
+--   grant(34) => grant_signal(34),
+--   grant(35) => grant_signal(35),
+--   grant(36) => grant_signal(36),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(31) =>request_signal(31),
+--   request(32) =>request_signal(32),
+--   request(33) =>request_signal(33),
+--   request(34) =>request_signal(34),
+--   request(35) =>request_signal(35),
+--   request(36) =>request_signal(36)
+--);
+--
+--end generate switch6x6;
+--
+--
+---- switch 7 ports
+--switch7x7 : if number_of_ports = 7 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>7)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--	cmd_in_en => cmd_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   grant(7) => grant_signal(7),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>7)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(8),
+--   grant(2) => grant_signal(9),
+--   grant(3) => grant_signal(10),
+--   grant(4) => grant_signal(11),
+--   grant(5) => grant_signal(12),
+--   grant(6) => grant_signal(13),
+--   grant(7) => grant_signal(14),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10),
+--   request(11) =>request_signal(11),
+--   request(12) =>request_signal(12),
+--   request(13) =>request_signal(13),
+--   request(14) =>request_signal(14)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>7)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(15) => grant_signal(15),
+--   grant(16) => grant_signal(16),
+--   grant(17) => grant_signal(17),
+--   grant(18) => grant_signal(18),
+--   grant(19) => grant_signal(19),
+--   grant(20) => grant_signal(20),
+--   grant(21) => grant_signal(21),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(15) =>request_signal(15),
+--   request(16) =>request_signal(16),
+--   request(17) =>request_signal(17),
+--   request(18) =>request_signal(18),
+--   request(19) =>request_signal(19),
+--   request(20) =>request_signal(20),
+--   request(21) =>request_signal(21)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>7)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(22) => grant_signal(22),
+--   grant(23) => grant_signal(23),
+--   grant(24) => grant_signal(24),
+--   grant(25) => grant_signal(25),
+--   grant(26) => grant_signal(26),
+--   grant(27) => grant_signal(27),
+--   grant(28) => grant_signal(28),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(22) =>request_signal(22),
+--   request(23) =>request_signal(23),
+--   request(24) =>request_signal(24),
+--   request(25) =>request_signal(25),
+--   request(26) =>request_signal(26),
+--   request(27) =>request_signal(27),
+--   request(28) =>request_signal(28)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>7)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(29) => grant_signal(29),
+--   grant(30) => grant_signal(30),
+--   grant(31) => grant_signal(31),
+--   grant(32) => grant_signal(32),
+--   grant(33) => grant_signal(33),
+--   grant(34) => grant_signal(34),
+--   grant(35) => grant_signal(35),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(29) =>request_signal(29),
+--   request(30) =>request_signal(30),
+--   request(31) =>request_signal(31),
+--   request(32) =>request_signal(32),
+--   request(33) =>request_signal(33),
+--   request(34) =>request_signal(34),
+--   request(35) =>request_signal(35)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>7)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(36) => grant_signal(36),
+--   grant(37) => grant_signal(37),
+--   grant(38) => grant_signal(38),
+--   grant(39) => grant_signal(39),
+--   grant(40) => grant_signal(40),
+--   grant(41) => grant_signal(41),
+--   grant(42) => grant_signal(42),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(36) =>request_signal(36),
+--   request(37) =>request_signal(37),
+--   request(38) =>request_signal(38),
+--   request(39) =>request_signal(39),
+--   request(40) =>request_signal(40),
+--   request(41) =>request_signal(41),
+--   request(42) =>request_signal(42)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>7)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(43) => grant_signal(43),
+--   grant(44) => grant_signal(44),
+--   grant(45) => grant_signal(45),
+--   grant(46) => grant_signal(46),
+--   grant(47) => grant_signal(47),
+--   grant(48) => grant_signal(48),
+--   grant(49) => grant_signal(49),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(7),
+--   request(43) =>request_signal(43),
+--   request(44) =>request_signal(44),
+--   request(45) =>request_signal(45),
+--   request(46) =>request_signal(46),
+--   request(47) =>request_signal(47),
+--   request(48) =>request_signal(48),
+--   request(49) =>request_signal(49)
+--);
+--
+--end generate switch7x7;
+
+
+-- switch 8 ports
+switch8x8 : if number_of_ports = 8 generate
+switch_8x8:for i in 1 to number_of_ports generate
+constant j: natural:=number_of_ports*(i-1);
+begin
+--j<=number_of_ports*(i-1);
+PORTx8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8,Port_num=>i)
+PORT MAP(
+   data_in => Port_in(i),
+   data_in_en => data_in_en(i),
+	cmd_in_en => cmd_in_en(i),
+   reset => reset,
+   clk =>clk,
+	grant =>grant_signal(j+NUMBER_OF_PORTS downto j+1),
+   fifo_full =>fifo_in_full(i),
+   priority_rotation =>  priority_rotation_signal(i),
+   fifo_empty => fifo_in_empty(i),
+   data_out =>crossbar_in_port(i),
+   data_out_pulse =>crossbar_in_pulse(i),
+
+	request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
+);
+end generate switch_8x8;
+end generate switch8x8;
+
+-- switch 9 ports
+switch9x9_to_15 : if (number_of_ports >= 9)and (number_of_ports <= 15) generate
+
+switch_9x9_to_15:for i in 1 to number_of_ports generate
+
+constant j: natural:=number_of_ports*(i-1);
+begin
+
+PORTx9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>NUMBER_OF_PORTS,Port_num=>i)
+PORT MAP(
+   data_in => Port_in(i),
+   data_in_en => data_in_en(i),
+	cmd_in_en => cmd_in_en(i),
+   reset => reset,
+   clk =>clk,
+   grant => grant_signal(j+NUMBER_OF_PORTS downto j+1),
+   fifo_full =>fifo_in_full(i),
+   priority_rotation =>  priority_rotation_signal(i),
+   fifo_empty => fifo_in_empty(i),
+   data_out =>crossbar_in_port(i),
+   data_out_pulse =>crossbar_in_pulse(i),
+
+	request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
+);
+end generate switch_9x9_to_15;
+end generate switch9x9_to_15;
+
+
+
+-- switch 10 ports
+--switch10x10 : if number_of_ports = 10 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   grant(7) => grant_signal(7),
+--   grant(8) => grant_signal(8),
+--   grant(9) => grant_signal(9),
+--   grant(10) => grant_signal(10),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(11),
+--   grant(2) => grant_signal(12),
+--   grant(3) => grant_signal(13),
+--   grant(4) => grant_signal(14),
+--   grant(5) => grant_signal(15),
+--   grant(6) => grant_signal(16),
+--   grant(7) => grant_signal(17),
+--   grant(8) => grant_signal(18),
+--   grant(9) => grant_signal(19),
+--   grant(10) => grant_signal(20),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(1) =>request_signal(11),
+--   request(2) =>request_signal(12),
+--   request(3) =>request_signal(13),
+--   request(4) =>request_signal(14),
+--   request(5) =>request_signal(15),
+--   request(6) =>request_signal(16),
+--   request(7) =>request_signal(17),
+--   request(8) =>request_signal(18),
+--   request(9) =>request_signal(19),
+--   request(10) =>request_signal(20)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(21),
+--   grant(2) => grant_signal(22),
+--   grant(3) => grant_signal(23),
+--   grant(4) => grant_signal(24),
+--   grant(5) => grant_signal(25),
+--   grant(6) => grant_signal(26),
+--   grant(7) => grant_signal(27),
+--   grant(8) => grant_signal(28),
+--   grant(9) => grant_signal(29),
+--   grant(10) => grant_signal(30),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(1) =>request_signal(21),
+--   request(2) =>request_signal(22),
+--   request(3) =>request_signal(23),
+--   request(4) =>request_signal(24),
+--   request(5) =>request_signal(25),
+--   request(6) =>request_signal(26),
+--   request(7) =>request_signal(27),
+--   request(8) =>request_signal(28),
+--   request(9) =>request_signal(29),
+--   request(10) =>request_signal(30)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(31),
+--   grant(2) => grant_signal(32),
+--   grant(3) => grant_signal(33),
+--   grant(4) => grant_signal(34),
+--   grant(5) => grant_signal(35),
+--   grant(6) => grant_signal(36),
+--   grant(7) => grant_signal(37),
+--   grant(8) => grant_signal(38),
+--   grant(9) => grant_signal(39),
+--   grant(10) => grant_signal(40),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(1) =>request_signal(31),
+--   request(2) =>request_signal(32),
+--   request(3) =>request_signal(33),
+--   request(4) =>request_signal(34),
+--   request(5) =>request_signal(35),
+--   request(6) =>request_signal(36),
+--   request(7) =>request_signal(37),
+--   request(8) =>request_signal(38),
+--   request(9) =>request_signal(39),
+--   request(10) =>request_signal(40)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(41),
+--   grant(2) => grant_signal(42),
+--   grant(3) => grant_signal(43),
+--   grant(4) => grant_signal(44),
+--   grant(5) => grant_signal(45),
+--   grant(6) => grant_signal(46),
+--   grant(7) => grant_signal(47),
+--   grant(8) => grant_signal(48),
+--   grant(9) => grant_signal(49),
+--   grant(10) => grant_signal(50),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(1) =>request_signal(41),
+--   request(2) =>request_signal(42),
+--   request(3) =>request_signal(43),
+--   request(4) =>request_signal(44),
+--   request(5) =>request_signal(45),
+--   request(6) =>request_signal(46),
+--   request(7) =>request_signal(47),
+--   request(8) =>request_signal(48),
+--   request(9) =>request_signal(49),
+--   request(10) =>request_signal(50)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(51),
+--   grant(2) => grant_signal(52),
+--   grant(3) => grant_signal(53),
+--   grant(4) => grant_signal(54),
+--   grant(5) => grant_signal(55),
+--   grant(6) => grant_signal(56),
+--   grant(7) => grant_signal(57),
+--   grant(8) => grant_signal(58),
+--   grant(9) => grant_signal(59),
+--   grant(10) => grant_signal(60),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(1) =>request_signal(51),
+--   request(2) =>request_signal(52),
+--   request(3) =>request_signal(53),
+--   request(4) =>request_signal(54),
+--   request(5) =>request_signal(55),
+--   request(6) =>request_signal(56),
+--   request(7) =>request_signal(57),
+--   request(8) =>request_signal(58),
+--   request(9) =>request_signal(59),
+--   request(10) =>request_signal(60)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(61),
+--   grant(2) => grant_signal(62),
+--   grant(3) => grant_signal(63),
+--   grant(4) => grant_signal(64),
+--   grant(5) => grant_signal(65),
+--   grant(6) => grant_signal(66),
+--   grant(7) => grant_signal(67),
+--   grant(8) => grant_signal(68),
+--   grant(9) => grant_signal(69),
+--   grant(10) => grant_signal(70),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(7),
+--   data_out_pulse =>crossbar_in_pulse(7),
+--   request(1) =>request_signal(61),
+--   request(2) =>request_signal(62),
+--   request(3) =>request_signal(63),
+--   request(4) =>request_signal(64),
+--   request(5) =>request_signal(65),
+--   request(6) =>request_signal(66),
+--   request(7) =>request_signal(67),
+--   request(8) =>request_signal(68),
+--   request(9) =>request_signal(69),
+--   request(10) =>request_signal(70)
+--);
+--
+--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(8),
+--   data_in_en => data_in_en(8),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(71),
+--   grant(2) => grant_signal(72),
+--   grant(3) => grant_signal(73),
+--   grant(4) => grant_signal(74),
+--   grant(5) => grant_signal(75),
+--   grant(6) => grant_signal(76),
+--   grant(7) => grant_signal(77),
+--   grant(8) => grant_signal(78),
+--   grant(9) => grant_signal(79),
+--   grant(10) => grant_signal(80),
+--   fifo_full =>fifo_in_full(8),
+--   priority_rotation =>  priority_rotation_signal(8),
+--   fifo_empty => fifo_in_empty(8),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(8),
+--   request(1) =>request_signal(71),
+--   request(2) =>request_signal(72),
+--   request(3) =>request_signal(73),
+--   request(4) =>request_signal(74),
+--   request(5) =>request_signal(75),
+--   request(6) =>request_signal(76),
+--   request(7) =>request_signal(77),
+--   request(8) =>request_signal(78),
+--   request(9) =>request_signal(79),
+--   request(10) =>request_signal(80)
+--);
+--
+--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(9),
+--   data_in_en => data_in_en(9),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(81),
+--   grant(2) => grant_signal(82),
+--   grant(3) => grant_signal(83),
+--   grant(4) => grant_signal(84),
+--   grant(5) => grant_signal(85),
+--   grant(6) => grant_signal(86),
+--   grant(7) => grant_signal(87),
+--   grant(8) => grant_signal(88),
+--   grant(9) => grant_signal(89),
+--   grant(10) => grant_signal(90),
+--   fifo_full =>fifo_in_full(9),
+--   priority_rotation =>  priority_rotation_signal(9),
+--   fifo_empty => fifo_in_empty(9),
+--   data_out =>crossbar_in_port(9),
+--   data_out_pulse =>crossbar_in_pulse(9),
+--   request(1) =>request_signal(81),
+--   request(2) =>request_signal(82),
+--   request(3) =>request_signal(83),
+--   request(4) =>request_signal(84),
+--   request(5) =>request_signal(85),
+--   request(6) =>request_signal(86),
+--   request(7) =>request_signal(87),
+--   request(8) =>request_signal(88),
+--   request(9) =>request_signal(89),
+--   request(10) =>request_signal(90)
+--);
+--
+--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>10)
+--PORT MAP(
+--   data_in => Port_in(10),
+--   data_in_en => data_in_en(10),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(91),
+--   grant(2) => grant_signal(92),
+--   grant(3) => grant_signal(93),
+--   grant(4) => grant_signal(94),
+--   grant(5) => grant_signal(95),
+--   grant(6) => grant_signal(96),
+--   grant(7) => grant_signal(97),
+--   grant(8) => grant_signal(98),
+--   grant(9) => grant_signal(99),
+--   grant(10) => grant_signal(100),
+--   fifo_full =>fifo_in_full(10),
+--   priority_rotation =>  priority_rotation_signal(10),
+--   fifo_empty => fifo_in_empty(10),
+--   data_out =>crossbar_in_port(10),
+--   data_out_pulse =>crossbar_in_pulse(10),
+--   request(1) =>request_signal(91),
+--   request(2) =>request_signal(92),
+--   request(3) =>request_signal(93),
+--   request(4) =>request_signal(94),
+--   request(5) =>request_signal(95),
+--   request(6) =>request_signal(96),
+--   request(7) =>request_signal(97),
+--   request(8) =>request_signal(98),
+--   request(9) =>request_signal(99),
+--   request(10) =>request_signal(100)
+--);
+--
+--end generate switch10x10;
+--
+--
+---- switch 11 ports
+--switch11x11 : if number_of_ports = 11 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   grant(7) => grant_signal(7),
+--   grant(8) => grant_signal(8),
+--   grant(9) => grant_signal(9),
+--   grant(10) => grant_signal(10),
+--   grant(11) => grant_signal(11),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10),
+--   request(11) =>request_signal(11)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(12),
+--   grant(02) => grant_signal(13),
+--   grant(03) => grant_signal(14),
+--   grant(04) => grant_signal(15),
+--   grant(05) => grant_signal(16),
+--   grant(06) => grant_signal(17),
+--   grant(07) => grant_signal(18),
+--   grant(08) => grant_signal(19),
+--   grant(09) => grant_signal(20),
+--   grant(10) => grant_signal(21),
+--   grant(11) => grant_signal(22),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(01) =>request_signal(12),
+--   request(02) =>request_signal(13),
+--   request(03) =>request_signal(14),
+--   request(04) =>request_signal(15),
+--   request(05) =>request_signal(16),
+--   request(06) =>request_signal(17),
+--   request(07) =>request_signal(18),
+--   request(08) =>request_signal(19),
+--   request(09) =>request_signal(20),
+--   request(10) =>request_signal(21),
+--   request(11) =>request_signal(22)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(01) => grant_signal(23),
+--   grant(02) => grant_signal(24),
+--   grant(03) => grant_signal(25),
+--   grant(04) => grant_signal(26),
+--   grant(05) => grant_signal(27),
+--   grant(06) => grant_signal(28),
+--   grant(07) => grant_signal(29),
+--   grant(08) => grant_signal(30),
+--   grant(09) => grant_signal(31),
+--   grant(10) => grant_signal(32),
+--   grant(11) => grant_signal(33),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(01) =>request_signal(23),
+--   request(02) =>request_signal(24),
+--   request(03) =>request_signal(25),
+--   request(04) =>request_signal(26),
+--   request(05) =>request_signal(27),
+--   request(06) =>request_signal(28),
+--   request(07) =>request_signal(29),
+--   request(08) =>request_signal(30),
+--   request(09) =>request_signal(31),
+--   request(10) =>request_signal(32),
+--   request(11) =>request_signal(33)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(01) => grant_signal(34),
+--   grant(02) => grant_signal(35),
+--   grant(03) => grant_signal(36),
+--   grant(04) => grant_signal(37),
+--   grant(05) => grant_signal(38),
+--   grant(06) => grant_signal(39),
+--   grant(07) => grant_signal(40),
+--   grant(08) => grant_signal(41),
+--   grant(09) => grant_signal(42),
+--   grant(10) => grant_signal(43),
+--   grant(11) => grant_signal(44),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(01) =>request_signal(34),
+--   request(02) =>request_signal(35),
+--   request(03) =>request_signal(36),
+--   request(04) =>request_signal(37),
+--   request(05) =>request_signal(38),
+--   request(06) =>request_signal(39),
+--   request(07) =>request_signal(40),
+--   request(08) =>request_signal(41),
+--   request(09) =>request_signal(42),
+--   request(10) =>request_signal(43),
+--   request(11) =>request_signal(44)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(45) => grant_signal(45),
+--   grant(46) => grant_signal(46),
+--   grant(47) => grant_signal(47),
+--   grant(48) => grant_signal(48),
+--   grant(49) => grant_signal(49),
+--   grant(50) => grant_signal(50),
+--   grant(51) => grant_signal(51),
+--   grant(52) => grant_signal(52),
+--   grant(53) => grant_signal(53),
+--   grant(54) => grant_signal(54),
+--   grant(55) => grant_signal(55),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(45) =>request_signal(45),
+--   request(46) =>request_signal(46),
+--   request(47) =>request_signal(47),
+--   request(48) =>request_signal(48),
+--   request(49) =>request_signal(49),
+--   request(50) =>request_signal(50),
+--   request(51) =>request_signal(51),
+--   request(52) =>request_signal(52),
+--   request(53) =>request_signal(53),
+--   request(54) =>request_signal(54),
+--   request(55) =>request_signal(55)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(56) => grant_signal(56),
+--   grant(57) => grant_signal(57),
+--   grant(58) => grant_signal(58),
+--   grant(59) => grant_signal(59),
+--   grant(60) => grant_signal(60),
+--   grant(61) => grant_signal(61),
+--   grant(62) => grant_signal(62),
+--   grant(63) => grant_signal(63),
+--   grant(64) => grant_signal(64),
+--   grant(65) => grant_signal(65),
+--   grant(66) => grant_signal(66),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(56) =>request_signal(56),
+--   request(57) =>request_signal(57),
+--   request(58) =>request_signal(58),
+--   request(59) =>request_signal(59),
+--   request(60) =>request_signal(60),
+--   request(61) =>request_signal(61),
+--   request(62) =>request_signal(62),
+--   request(63) =>request_signal(63),
+--   request(64) =>request_signal(64),
+--   request(65) =>request_signal(65),
+--   request(66) =>request_signal(66)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(67) => grant_signal(67),
+--   grant(68) => grant_signal(68),
+--   grant(69) => grant_signal(69),
+--   grant(70) => grant_signal(70),
+--   grant(71) => grant_signal(71),
+--   grant(72) => grant_signal(72),
+--   grant(73) => grant_signal(73),
+--   grant(74) => grant_signal(74),
+--   grant(75) => grant_signal(75),
+--   grant(76) => grant_signal(76),
+--   grant(77) => grant_signal(77),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(7),
+--   request(67) =>request_signal(67),
+--   request(68) =>request_signal(68),
+--   request(69) =>request_signal(69),
+--   request(70) =>request_signal(70),
+--   request(71) =>request_signal(71),
+--   request(72) =>request_signal(72),
+--   request(73) =>request_signal(73),
+--   request(74) =>request_signal(74),
+--   request(75) =>request_signal(75),
+--   request(76) =>request_signal(76),
+--   request(77) =>request_signal(77)
+--);
+--
+--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(8),
+--   data_in_en => data_in_en(8),
+--   reset => reset,
+--   clk =>clk,
+--   grant(78) => grant_signal(78),
+--   grant(79) => grant_signal(79),
+--   grant(80) => grant_signal(80),
+--   grant(81) => grant_signal(81),
+--   grant(82) => grant_signal(82),
+--   grant(83) => grant_signal(83),
+--   grant(84) => grant_signal(84),
+--   grant(85) => grant_signal(85),
+--   grant(86) => grant_signal(86),
+--   grant(87) => grant_signal(87),
+--   grant(88) => grant_signal(88),
+--   fifo_full =>fifo_in_full(8),
+--   priority_rotation =>  priority_rotation_signal(8),
+--   fifo_empty => fifo_in_empty(8),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(8),
+--   request(78) =>request_signal(78),
+--   request(79) =>request_signal(79),
+--   request(80) =>request_signal(80),
+--   request(81) =>request_signal(81),
+--   request(82) =>request_signal(82),
+--   request(83) =>request_signal(83),
+--   request(84) =>request_signal(84),
+--   request(85) =>request_signal(85),
+--   request(86) =>request_signal(86),
+--   request(87) =>request_signal(87),
+--   request(88) =>request_signal(88)
+--);
+--
+--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(9),
+--   data_in_en => data_in_en(9),
+--   reset => reset,
+--   clk =>clk,
+--   grant(89) => grant_signal(89),
+--   grant(90) => grant_signal(90),
+--   grant(91) => grant_signal(91),
+--   grant(92) => grant_signal(92),
+--   grant(93) => grant_signal(93),
+--   grant(94) => grant_signal(94),
+--   grant(95) => grant_signal(95),
+--   grant(96) => grant_signal(96),
+--   grant(97) => grant_signal(97),
+--   grant(98) => grant_signal(98),
+--   grant(99) => grant_signal(99),
+--   fifo_full =>fifo_in_full(9),
+--   priority_rotation =>  priority_rotation_signal(9),
+--   fifo_empty => fifo_in_empty(9),
+--   data_out =>crossbar_in_port(9),
+--   data_out_pulse =>crossbar_in_pulse(9),
+--   request(89) =>request_signal(89),
+--   request(90) =>request_signal(90),
+--   request(91) =>request_signal(91),
+--   request(92) =>request_signal(92),
+--   request(93) =>request_signal(93),
+--   request(94) =>request_signal(94),
+--   request(95) =>request_signal(95),
+--   request(96) =>request_signal(96),
+--   request(97) =>request_signal(97),
+--   request(98) =>request_signal(98),
+--   request(99) =>request_signal(99)
+--);
+--
+--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(10),
+--   data_in_en => data_in_en(10),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(100),
+--   grant(2) => grant_signal(101),
+--   grant(3) => grant_signal(102),
+--   grant(4) => grant_signal(103),
+--   grant(5) => grant_signal(104),
+--   grant(6) => grant_signal(105),
+--   grant(7) => grant_signal(106),
+--   grant(8) => grant_signal(107),
+--   grant(9) => grant_signal(108),
+--   grant(10) => grant_signal(109),
+--   grant(11) => grant_signal(110),
+--   fifo_full =>fifo_in_full(10),
+--   priority_rotation =>  priority_rotation_signal(10),
+--   fifo_empty => fifo_in_empty(10),
+--   data_out =>crossbar_in_port(10),
+--   data_out_pulse =>crossbar_in_pulse(10),
+--   request(1) =>request_signal(100),
+--   request(2) =>request_signal(101),
+--   request(3) =>request_signal(102),
+--   request(4) =>request_signal(103),
+--   request(5) =>request_signal(104),
+--   request(6) =>request_signal(105),
+--   request(7) =>request_signal(106),
+--   request(8) =>request_signal(107),
+--   request(9) =>request_signal(108),
+--   request(10) =>request_signal(109),
+--   request(11) =>request_signal(110)
+--);
+--
+--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>11)
+--PORT MAP(
+--   data_in => Port_in(11),
+--   data_in_en => data_in_en(11),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(111),
+--   grant(2) => grant_signal(112),
+--   grant(3) => grant_signal(113),
+--   grant(4) => grant_signal(114),
+--   grant(5) => grant_signal(115),
+--   grant(6) => grant_signal(116),
+--   grant(7) => grant_signal(117),
+--   grant(8) => grant_signal(118),
+--   grant(9) => grant_signal(119),
+--   grant(10) => grant_signal(120),
+--   grant(11) => grant_signal(121),
+--   fifo_full =>fifo_in_full(11),
+--   priority_rotation =>  priority_rotation_signal(11),
+--   fifo_empty => fifo_in_empty(11),
+--   data_out =>crossbar_in_port(11),
+--   data_out_pulse =>crossbar_in_pulse(11),
+--   request(1) =>request_signal(111),
+--   request(2) =>request_signal(112),
+--   request(3) =>request_signal(113),
+--   request(4) =>request_signal(114),
+--   request(5) =>request_signal(115),
+--   request(6) =>request_signal(116),
+--   request(7) =>request_signal(117),
+--   request(8) =>request_signal(118),
+--   request(9) =>request_signal(119),
+--   request(10) =>request_signal(120),
+--   request(11) =>request_signal(121)
+--);
+--
+--end generate switch11x11;
+--
+--
+---- switch 12 ports
+--switch12x12 : if number_of_ports = 12 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   grant(7) => grant_signal(7),
+--   grant(8) => grant_signal(8),
+--   grant(9) => grant_signal(9),
+--   grant(10) => grant_signal(10),
+--   grant(11) => grant_signal(11),
+--   grant(12) => grant_signal(12),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10),
+--   request(11) =>request_signal(11),
+--   request(12) =>request_signal(12)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(13) => grant_signal(13),
+--   grant(14) => grant_signal(14),
+--   grant(15) => grant_signal(15),
+--   grant(16) => grant_signal(16),
+--   grant(17) => grant_signal(17),
+--   grant(18) => grant_signal(18),
+--   grant(19) => grant_signal(19),
+--   grant(20) => grant_signal(20),
+--   grant(21) => grant_signal(21),
+--   grant(22) => grant_signal(22),
+--   grant(23) => grant_signal(23),
+--   grant(24) => grant_signal(24),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(13) =>request_signal(13),
+--   request(14) =>request_signal(14),
+--   request(15) =>request_signal(15),
+--   request(16) =>request_signal(16),
+--   request(17) =>request_signal(17),
+--   request(18) =>request_signal(18),
+--   request(19) =>request_signal(19),
+--   request(20) =>request_signal(20),
+--   request(21) =>request_signal(21),
+--   request(22) =>request_signal(22),
+--   request(23) =>request_signal(23),
+--   request(24) =>request_signal(24)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(25) => grant_signal(25),
+--   grant(26) => grant_signal(26),
+--   grant(27) => grant_signal(27),
+--   grant(28) => grant_signal(28),
+--   grant(29) => grant_signal(29),
+--   grant(30) => grant_signal(30),
+--   grant(31) => grant_signal(31),
+--   grant(32) => grant_signal(32),
+--   grant(33) => grant_signal(33),
+--   grant(34) => grant_signal(34),
+--   grant(35) => grant_signal(35),
+--   grant(36) => grant_signal(36),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(25) =>request_signal(25),
+--   request(26) =>request_signal(26),
+--   request(27) =>request_signal(27),
+--   request(28) =>request_signal(28),
+--   request(29) =>request_signal(29),
+--   request(30) =>request_signal(30),
+--   request(31) =>request_signal(31),
+--   request(32) =>request_signal(32),
+--   request(33) =>request_signal(33),
+--   request(34) =>request_signal(34),
+--   request(35) =>request_signal(35),
+--   request(36) =>request_signal(36)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(37) => grant_signal(37),
+--   grant(38) => grant_signal(38),
+--   grant(39) => grant_signal(39),
+--   grant(40) => grant_signal(40),
+--   grant(41) => grant_signal(41),
+--   grant(42) => grant_signal(42),
+--   grant(43) => grant_signal(43),
+--   grant(44) => grant_signal(44),
+--   grant(45) => grant_signal(45),
+--   grant(46) => grant_signal(46),
+--   grant(47) => grant_signal(47),
+--   grant(48) => grant_signal(48),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(37) =>request_signal(37),
+--   request(38) =>request_signal(38),
+--   request(39) =>request_signal(39),
+--   request(40) =>request_signal(40),
+--   request(41) =>request_signal(41),
+--   request(42) =>request_signal(42),
+--   request(43) =>request_signal(43),
+--   request(44) =>request_signal(44),
+--   request(45) =>request_signal(45),
+--   request(46) =>request_signal(46),
+--   request(47) =>request_signal(47),
+--   request(48) =>request_signal(48)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(49) => grant_signal(49),
+--   grant(50) => grant_signal(50),
+--   grant(51) => grant_signal(51),
+--   grant(52) => grant_signal(52),
+--   grant(53) => grant_signal(53),
+--   grant(54) => grant_signal(54),
+--   grant(55) => grant_signal(55),
+--   grant(56) => grant_signal(56),
+--   grant(57) => grant_signal(57),
+--   grant(58) => grant_signal(58),
+--   grant(59) => grant_signal(59),
+--   grant(60) => grant_signal(60),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(49) =>request_signal(49),
+--   request(50) =>request_signal(50),
+--   request(51) =>request_signal(51),
+--   request(52) =>request_signal(52),
+--   request(53) =>request_signal(53),
+--   request(54) =>request_signal(54),
+--   request(55) =>request_signal(55),
+--   request(56) =>request_signal(56),
+--   request(57) =>request_signal(57),
+--   request(58) =>request_signal(58),
+--   request(59) =>request_signal(59),
+--   request(60) =>request_signal(60)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(61) => grant_signal(61),
+--   grant(62) => grant_signal(62),
+--   grant(63) => grant_signal(63),
+--   grant(64) => grant_signal(64),
+--   grant(65) => grant_signal(65),
+--   grant(66) => grant_signal(66),
+--   grant(67) => grant_signal(67),
+--   grant(68) => grant_signal(68),
+--   grant(69) => grant_signal(69),
+--   grant(70) => grant_signal(70),
+--   grant(71) => grant_signal(71),
+--   grant(72) => grant_signal(72),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(61) =>request_signal(61),
+--   request(62) =>request_signal(62),
+--   request(63) =>request_signal(63),
+--   request(64) =>request_signal(64),
+--   request(65) =>request_signal(65),
+--   request(66) =>request_signal(66),
+--   request(67) =>request_signal(67),
+--   request(68) =>request_signal(68),
+--   request(69) =>request_signal(69),
+--   request(70) =>request_signal(70),
+--   request(71) =>request_signal(71),
+--   request(72) =>request_signal(72)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(73) => grant_signal(73),
+--   grant(74) => grant_signal(74),
+--   grant(75) => grant_signal(75),
+--   grant(76) => grant_signal(76),
+--   grant(77) => grant_signal(77),
+--   grant(78) => grant_signal(78),
+--   grant(79) => grant_signal(79),
+--   grant(80) => grant_signal(80),
+--   grant(81) => grant_signal(81),
+--   grant(82) => grant_signal(82),
+--   grant(83) => grant_signal(83),
+--   grant(84) => grant_signal(84),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(7),
+--   data_out_pulse =>crossbar_in_pulse(7),
+--   request(73) =>request_signal(73),
+--   request(74) =>request_signal(74),
+--   request(75) =>request_signal(75),
+--   request(76) =>request_signal(76),
+--   request(77) =>request_signal(77),
+--   request(78) =>request_signal(78),
+--   request(79) =>request_signal(79),
+--   request(80) =>request_signal(80),
+--   request(81) =>request_signal(81),
+--   request(82) =>request_signal(82),
+--   request(83) =>request_signal(83),
+--   request(84) =>request_signal(84)
+--);
+--
+--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(8),
+--   data_in_en => data_in_en(8),
+--   reset => reset,
+--   clk =>clk,
+--   grant(85) => grant_signal(85),
+--   grant(86) => grant_signal(86),
+--   grant(87) => grant_signal(87),
+--   grant(88) => grant_signal(88),
+--   grant(89) => grant_signal(89),
+--   grant(90) => grant_signal(90),
+--   grant(91) => grant_signal(91),
+--   grant(92) => grant_signal(92),
+--   grant(93) => grant_signal(93),
+--   grant(94) => grant_signal(94),
+--   grant(95) => grant_signal(95),
+--   grant(96) => grant_signal(96),
+--   fifo_full =>fifo_in_full(8),
+--   priority_rotation =>  priority_rotation_signal(8),
+--   fifo_empty => fifo_in_empty(8),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(8),
+--   request(85) =>request_signal(85),
+--   request(86) =>request_signal(86),
+--   request(87) =>request_signal(87),
+--   request(88) =>request_signal(88),
+--   request(89) =>request_signal(89),
+--   request(90) =>request_signal(90),
+--   request(91) =>request_signal(91),
+--   request(92) =>request_signal(92),
+--   request(93) =>request_signal(93),
+--   request(94) =>request_signal(94),
+--   request(95) =>request_signal(95),
+--   request(96) =>request_signal(96)
+--);
+--
+--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(9),
+--   data_in_en => data_in_en(9),
+--   reset => reset,
+--   clk =>clk,
+--   grant(97) => grant_signal(97),
+--   grant(98) => grant_signal(98),
+--   grant(99) => grant_signal(99),
+--   grant(100) => grant_signal(100),
+--   grant(101) => grant_signal(101),
+--   grant(102) => grant_signal(102),
+--   grant(103) => grant_signal(103),
+--   grant(104) => grant_signal(104),
+--   grant(105) => grant_signal(105),
+--   grant(106) => grant_signal(106),
+--   grant(107) => grant_signal(107),
+--   grant(108) => grant_signal(108),
+--   fifo_full =>fifo_in_full(9),
+--   priority_rotation =>  priority_rotation_signal(9),
+--   fifo_empty => fifo_in_empty(9),
+--   data_out =>crossbar_in_port(9),
+--   data_out_pulse =>crossbar_in_pulse(9),
+--   request(97) =>request_signal(97),
+--   request(98) =>request_signal(98),
+--   request(99) =>request_signal(99),
+--   request(100) =>request_signal(100),
+--   request(101) =>request_signal(101),
+--   request(102) =>request_signal(102),
+--   request(103) =>request_signal(103),
+--   request(104) =>request_signal(104),
+--   request(105) =>request_signal(105),
+--   request(106) =>request_signal(106),
+--   request(107) =>request_signal(107),
+--   request(108) =>request_signal(108)
+--);
+--
+--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(10),
+--   data_in_en => data_in_en(10),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(109),
+--   grant(2) => grant_signal(110),
+--   grant(3) => grant_signal(111),
+--   grant(4) => grant_signal(112),
+--   grant(5) => grant_signal(113),
+--   grant(6) => grant_signal(114),
+--   grant(7) => grant_signal(115),
+--   grant(8) => grant_signal(116),
+--   grant(9) => grant_signal(117),
+--   grant(10) => grant_signal(118),
+--   grant(11) => grant_signal(119),
+--   grant(12) => grant_signal(120),
+--   fifo_full =>fifo_in_full(10),
+--   priority_rotation =>  priority_rotation_signal(10),
+--   fifo_empty => fifo_in_empty(10),
+--   data_out =>crossbar_in_port(10),
+--   data_out_pulse =>crossbar_in_pulse(10),
+--   request(109) =>request_signal(109),
+--   request(110) =>request_signal(110),
+--   request(111) =>request_signal(111),
+--   request(112) =>request_signal(112),
+--   request(113) =>request_signal(113),
+--   request(114) =>request_signal(114),
+--   request(115) =>request_signal(115),
+--   request(116) =>request_signal(116),
+--   request(117) =>request_signal(117),
+--   request(118) =>request_signal(118),
+--   request(119) =>request_signal(119),
+--   request(120) =>request_signal(120)
+--);
+--
+--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(11),
+--   data_in_en => data_in_en(11),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(121),
+--   grant(2) => grant_signal(122),
+--   grant(3) => grant_signal(123),
+--   grant(4) => grant_signal(124),
+--   grant(5) => grant_signal(125),
+--   grant(6) => grant_signal(126),
+--   grant(7) => grant_signal(127),
+--   grant(8) => grant_signal(128),
+--   grant(9) => grant_signal(129),
+--   grant(10) => grant_signal(130),
+--   grant(11) => grant_signal(131),
+--   grant(12) => grant_signal(132),
+--   fifo_full =>fifo_in_full(11),
+--   priority_rotation =>  priority_rotation_signal(11),
+--   fifo_empty => fifo_in_empty(11),
+--   data_out =>crossbar_in_port(11),
+--   data_out_pulse =>crossbar_in_pulse(11),
+--   request(121) =>request_signal(121),
+--   request(122) =>request_signal(122),
+--   request(123) =>request_signal(123),
+--   request(124) =>request_signal(124),
+--   request(125) =>request_signal(125),
+--   request(126) =>request_signal(126),
+--   request(127) =>request_signal(127),
+--   request(128) =>request_signal(128),
+--   request(129) =>request_signal(129),
+--   request(130) =>request_signal(130),
+--   request(131) =>request_signal(131),
+--   request(132) =>request_signal(132)
+--);
+--
+--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>12)
+--PORT MAP(
+--   data_in => Port_in(12),
+--   data_in_en => data_in_en(12),
+--   reset => reset,
+--   clk =>clk,
+--   grant(133) => grant_signal(133),
+--   grant(134) => grant_signal(134),
+--   grant(135) => grant_signal(135),
+--   grant(136) => grant_signal(136),
+--   grant(137) => grant_signal(137),
+--   grant(138) => grant_signal(138),
+--   grant(139) => grant_signal(139),
+--   grant(140) => grant_signal(140),
+--   grant(141) => grant_signal(141),
+--   grant(142) => grant_signal(142),
+--   grant(143) => grant_signal(143),
+--   grant(144) => grant_signal(144),
+--   fifo_full =>fifo_in_full(12),
+--   priority_rotation =>  priority_rotation_signal(12),
+--   fifo_empty => fifo_in_empty(12),
+--   data_out =>crossbar_in_port(12),
+--   data_out_pulse =>crossbar_in_pulse(12),
+--   request(133) =>request_signal(133),
+--   request(134) =>request_signal(134),
+--   request(135) =>request_signal(135),
+--   request(136) =>request_signal(136),
+--   request(137) =>request_signal(137),
+--   request(138) =>request_signal(138),
+--   request(139) =>request_signal(139),
+--   request(140) =>request_signal(140),
+--   request(141) =>request_signal(141),
+--   request(142) =>request_signal(142),
+--   request(143) =>request_signal(143),
+--   request(144) =>request_signal(144)
+--);
+--
+--end generate switch12x12;
+--
+--
+---- switch 13 ports
+--switch13x13 : if number_of_ports = 13 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   grant(7) => grant_signal(7),
+--   grant(8) => grant_signal(8),
+--   grant(9) => grant_signal(9),
+--   grant(10) => grant_signal(10),
+--   grant(11) => grant_signal(11),
+--   grant(12) => grant_signal(12),
+--   grant(13) => grant_signal(13),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10),
+--   request(11) =>request_signal(11),
+--   request(12) =>request_signal(12),
+--   request(13) =>request_signal(13)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(14) => grant_signal(14),
+--   grant(15) => grant_signal(15),
+--   grant(16) => grant_signal(16),
+--   grant(17) => grant_signal(17),
+--   grant(18) => grant_signal(18),
+--   grant(19) => grant_signal(19),
+--   grant(20) => grant_signal(20),
+--   grant(21) => grant_signal(21),
+--   grant(22) => grant_signal(22),
+--   grant(23) => grant_signal(23),
+--   grant(24) => grant_signal(24),
+--   grant(25) => grant_signal(25),
+--   grant(26) => grant_signal(26),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(14) =>request_signal(14),
+--   request(15) =>request_signal(15),
+--   request(16) =>request_signal(16),
+--   request(17) =>request_signal(17),
+--   request(18) =>request_signal(18),
+--   request(19) =>request_signal(19),
+--   request(20) =>request_signal(20),
+--   request(21) =>request_signal(21),
+--   request(22) =>request_signal(22),
+--   request(23) =>request_signal(23),
+--   request(24) =>request_signal(24),
+--   request(25) =>request_signal(25),
+--   request(26) =>request_signal(26)
+--);
+
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(27) => grant_signal(27),
+--   grant(28) => grant_signal(28),
+--   grant(29) => grant_signal(29),
+--   grant(30) => grant_signal(30),
+--   grant(31) => grant_signal(31),
+--   grant(32) => grant_signal(32),
+--   grant(33) => grant_signal(33),
+--   grant(34) => grant_signal(34),
+--   grant(35) => grant_signal(35),
+--   grant(36) => grant_signal(36),
+--   grant(37) => grant_signal(37),
+--   grant(38) => grant_signal(38),
+--   grant(39) => grant_signal(39),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(27) =>request_signal(27),
+--   request(28) =>request_signal(28),
+--   request(29) =>request_signal(29),
+--   request(30) =>request_signal(30),
+--   request(31) =>request_signal(31),
+--   request(32) =>request_signal(32),
+--   request(33) =>request_signal(33),
+--   request(34) =>request_signal(34),
+--   request(35) =>request_signal(35),
+--   request(36) =>request_signal(36),
+--   request(37) =>request_signal(37),
+--   request(38) =>request_signal(38),
+--   request(39) =>request_signal(39)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(40) => grant_signal(40),
+--   grant(41) => grant_signal(41),
+--   grant(42) => grant_signal(42),
+--   grant(43) => grant_signal(43),
+--   grant(44) => grant_signal(44),
+--   grant(45) => grant_signal(45),
+--   grant(46) => grant_signal(46),
+--   grant(47) => grant_signal(47),
+--   grant(48) => grant_signal(48),
+--   grant(49) => grant_signal(49),
+--   grant(50) => grant_signal(50),
+--   grant(51) => grant_signal(51),
+--   grant(52) => grant_signal(52),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(40) =>request_signal(40),
+--   request(41) =>request_signal(41),
+--   request(42) =>request_signal(42),
+--   request(43) =>request_signal(43),
+--   request(44) =>request_signal(44),
+--   request(45) =>request_signal(45),
+--   request(46) =>request_signal(46),
+--   request(47) =>request_signal(47),
+--   request(48) =>request_signal(48),
+--   request(49) =>request_signal(49),
+--   request(50) =>request_signal(50),
+--   request(51) =>request_signal(51),
+--   request(52) =>request_signal(52)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(53) => grant_signal(53),
+--   grant(54) => grant_signal(54),
+--   grant(55) => grant_signal(55),
+--   grant(56) => grant_signal(56),
+--   grant(57) => grant_signal(57),
+--   grant(58) => grant_signal(58),
+--   grant(59) => grant_signal(59),
+--   grant(60) => grant_signal(60),
+--   grant(61) => grant_signal(61),
+--   grant(62) => grant_signal(62),
+--   grant(63) => grant_signal(63),
+--   grant(64) => grant_signal(64),
+--   grant(65) => grant_signal(65),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(53) =>request_signal(53),
+--   request(54) =>request_signal(54),
+--   request(55) =>request_signal(55),
+--   request(56) =>request_signal(56),
+--   request(57) =>request_signal(57),
+--   request(58) =>request_signal(58),
+--   request(59) =>request_signal(59),
+--   request(60) =>request_signal(60),
+--   request(61) =>request_signal(61),
+--   request(62) =>request_signal(62),
+--   request(63) =>request_signal(63),
+--   request(64) =>request_signal(64),
+--   request(65) =>request_signal(65)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(66) => grant_signal(66),
+--   grant(67) => grant_signal(67),
+--   grant(68) => grant_signal(68),
+--   grant(69) => grant_signal(69),
+--   grant(70) => grant_signal(70),
+--   grant(71) => grant_signal(71),
+--   grant(72) => grant_signal(72),
+--   grant(73) => grant_signal(73),
+--   grant(74) => grant_signal(74),
+--   grant(75) => grant_signal(75),
+--   grant(76) => grant_signal(76),
+--   grant(77) => grant_signal(77),
+--   grant(78) => grant_signal(78),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(66) =>request_signal(66),
+--   request(67) =>request_signal(67),
+--   request(68) =>request_signal(68),
+--   request(69) =>request_signal(69),
+--   request(70) =>request_signal(70),
+--   request(71) =>request_signal(71),
+--   request(72) =>request_signal(72),
+--   request(73) =>request_signal(73),
+--   request(74) =>request_signal(74),
+--   request(75) =>request_signal(75),
+--   request(76) =>request_signal(76),
+--   request(77) =>request_signal(77),
+--   request(78) =>request_signal(78)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(79) => grant_signal(79),
+--   grant(80) => grant_signal(80),
+--   grant(81) => grant_signal(81),
+--   grant(82) => grant_signal(82),
+--   grant(83) => grant_signal(83),
+--   grant(84) => grant_signal(84),
+--   grant(85) => grant_signal(85),
+--   grant(86) => grant_signal(86),
+--   grant(87) => grant_signal(87),
+--   grant(88) => grant_signal(88),
+--   grant(89) => grant_signal(89),
+--   grant(90) => grant_signal(90),
+--   grant(91) => grant_signal(91),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(7),
+--   data_out_pulse =>crossbar_in_pulse(7),
+--   request(79) =>request_signal(79),
+--   request(80) =>request_signal(80),
+--   request(81) =>request_signal(81),
+--   request(82) =>request_signal(82),
+--   request(83) =>request_signal(83),
+--   request(84) =>request_signal(84),
+--   request(85) =>request_signal(85),
+--   request(86) =>request_signal(86),
+--   request(87) =>request_signal(87),
+--   request(88) =>request_signal(88),
+--   request(89) =>request_signal(89),
+--   request(90) =>request_signal(90),
+--   request(91) =>request_signal(91)
+--);
+--
+--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(8),
+--   data_in_en => data_in_en(8),
+--   reset => reset,
+--   clk =>clk,
+--   grant(92) => grant_signal(92),
+--   grant(93) => grant_signal(93),
+--   grant(94) => grant_signal(94),
+--   grant(95) => grant_signal(95),
+--   grant(96) => grant_signal(96),
+--   grant(97) => grant_signal(97),
+--   grant(98) => grant_signal(98),
+--   grant(99) => grant_signal(99),
+--   grant(100) => grant_signal(100),
+--   grant(101) => grant_signal(101),
+--   grant(102) => grant_signal(102),
+--   grant(103) => grant_signal(103),
+--   grant(104) => grant_signal(104),
+--   fifo_full =>fifo_in_full(8),
+--   priority_rotation =>  priority_rotation_signal(8),
+--   fifo_empty => fifo_in_empty(8),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(8),
+--   request(92) =>request_signal(92),
+--   request(93) =>request_signal(93),
+--   request(94) =>request_signal(94),
+--   request(95) =>request_signal(95),
+--   request(96) =>request_signal(96),
+--   request(97) =>request_signal(97),
+--   request(98) =>request_signal(98),
+--   request(99) =>request_signal(99),
+--   request(100) =>request_signal(100),
+--   request(101) =>request_signal(101),
+--   request(102) =>request_signal(102),
+--   request(103) =>request_signal(103),
+--   request(104) =>request_signal(104)
+--);
+--
+--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(9),
+--   data_in_en => data_in_en(9),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(105),
+--   grant(2) => grant_signal(106),
+--   grant(3) => grant_signal(107),
+--   grant(4) => grant_signal(108),
+--   grant(5) => grant_signal(109),
+--   grant(6) => grant_signal(110),
+--   grant(7) => grant_signal(111),
+--   grant(8) => grant_signal(112),
+--   grant(9) => grant_signal(113),
+--   grant(10) => grant_signal(114),
+--   grant(11) => grant_signal(115),
+--   grant(12) => grant_signal(116),
+--   grant(13) => grant_signal(117),
+--   fifo_full =>fifo_in_full(9),
+--   priority_rotation =>  priority_rotation_signal(9),
+--   fifo_empty => fifo_in_empty(9),
+--   data_out =>crossbar_in_port(9),
+--   data_out_pulse =>crossbar_in_pulse(9),
+--   request(105) =>request_signal(105),
+--   request(106) =>request_signal(106),
+--   request(107) =>request_signal(107),
+--   request(108) =>request_signal(108),
+--   request(109) =>request_signal(109),
+--   request(110) =>request_signal(110),
+--   request(111) =>request_signal(111),
+--   request(112) =>request_signal(112),
+--   request(113) =>request_signal(113),
+--   request(114) =>request_signal(114),
+--   request(115) =>request_signal(115),
+--   request(116) =>request_signal(116),
+--   request(117) =>request_signal(117)
+--);
+--
+--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(10),
+--   data_in_en => data_in_en(10),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(118),
+--   grant(2) => grant_signal(119),
+--   grant(3) => grant_signal(120),
+--   grant(4) => grant_signal(121),
+--   grant(5) => grant_signal(122),
+--   grant(6) => grant_signal(123),
+--   grant(7) => grant_signal(124),
+--   grant(8) => grant_signal(125),
+--   grant(9) => grant_signal(126),
+--   grant(10) => grant_signal(127),
+--   grant(11) => grant_signal(128),
+--   grant(12) => grant_signal(129),
+--   grant(13) => grant_signal(130),
+--   fifo_full =>fifo_in_full(10),
+--   priority_rotation =>  priority_rotation_signal(10),
+--   fifo_empty => fifo_in_empty(10),
+--   data_out =>crossbar_in_port(10),
+--   data_out_pulse =>crossbar_in_pulse(10),
+--   request(1) =>request_signal(118),
+--   request(2) =>request_signal(119),
+--   request(3) =>request_signal(120),
+--   request(4) =>request_signal(121),
+--   request(5) =>request_signal(122),
+--   request(6) =>request_signal(123),
+--   request(7) =>request_signal(124),
+--   request(8) =>request_signal(125),
+--   request(9) =>request_signal(126),
+--   request(10) =>request_signal(127),
+--   request(11) =>request_signal(128),
+--   request(12) =>request_signal(129),
+--   request(13) =>request_signal(130)
+--);
+--
+--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(11),
+--   data_in_en => data_in_en(11),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(131),
+--   grant(2) => grant_signal(132),
+--   grant(3) => grant_signal(133),
+--   grant(4) => grant_signal(134),
+--   grant(5) => grant_signal(135),
+--   grant(6) => grant_signal(136),
+--   grant(7) => grant_signal(137),
+--   grant(8) => grant_signal(138),
+--   grant(9) => grant_signal(139),
+--   grant(10) => grant_signal(140),
+--   grant(11) => grant_signal(141),
+--   grant(12) => grant_signal(142),
+--   grant(13) => grant_signal(143),
+--   fifo_full =>fifo_in_full(11),
+--   priority_rotation =>  priority_rotation_signal(11),
+--   fifo_empty => fifo_in_empty(11),
+--   data_out =>crossbar_in_port(11),
+--   data_out_pulse =>crossbar_in_pulse(11),
+--   request(1) =>request_signal(131),
+--   request(2) =>request_signal(132),
+--   request(3) =>request_signal(133),
+--   request(4) =>request_signal(134),
+--   request(5) =>request_signal(135),
+--   request(6) =>request_signal(136),
+--   request(7) =>request_signal(137),
+--   request(8) =>request_signal(138),
+--   request(9) =>request_signal(139),
+--   request(10) =>request_signal(140),
+--   request(11) =>request_signal(141),
+--   request(12) =>request_signal(142),
+--   request(13) =>request_signal(143)
+--);
+--
+--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(12),
+--   data_in_en => data_in_en(12),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(144),
+--   grant(2) => grant_signal(145),
+--   grant(3) => grant_signal(146),
+--   grant(4) => grant_signal(147),
+--   grant(5) => grant_signal(148),
+--   grant(6) => grant_signal(149),
+--   grant(7) => grant_signal(150),
+--   grant(8) => grant_signal(151),
+--   grant(9) => grant_signal(152),
+--   grant(10) => grant_signal(153),
+--   grant(11) => grant_signal(154),
+--   grant(12) => grant_signal(155),
+--   grant(13) => grant_signal(156),
+--   fifo_full =>fifo_in_full(12),
+--   priority_rotation =>  priority_rotation_signal(12),
+--   fifo_empty => fifo_in_empty(12),
+--   data_out =>crossbar_in_port(12),
+--   data_out_pulse =>crossbar_in_pulse(12),
+--   request(1) =>request_signal(144),
+--   request(2) =>request_signal(145),
+--   request(3) =>request_signal(146),
+--   request(4) =>request_signal(147),
+--   request(5) =>request_signal(148),
+--   request(6) =>request_signal(149),
+--   request(7) =>request_signal(150),
+--   request(8) =>request_signal(151),
+--   request(9) =>request_signal(152),
+--   request(10) =>request_signal(153),
+--   request(11) =>request_signal(154),
+--   request(12) =>request_signal(155),
+--   request(13) =>request_signal(156)
+--);
+--
+--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>13)
+--PORT MAP(
+--   data_in => Port_in(13),
+--   data_in_en => data_in_en(13),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(157),
+--   grant(2) => grant_signal(158),
+--   grant(3) => grant_signal(159),
+--   grant(4) => grant_signal(160),
+--   grant(5) => grant_signal(161),
+--   grant(6) => grant_signal(162),
+--   grant(7) => grant_signal(163),
+--   grant(8) => grant_signal(164),
+--   grant(9) => grant_signal(165),
+--   grant(10) => grant_signal(166),
+--   grant(11) => grant_signal(167),
+--   grant(12) => grant_signal(168),
+--   grant(13) => grant_signal(169),
+--   fifo_full =>fifo_in_full(13),
+--   priority_rotation =>  priority_rotation_signal(13),
+--   fifo_empty => fifo_in_empty(13),
+--   data_out =>crossbar_in_port(13),
+--   data_out_pulse =>crossbar_in_pulse(13),
+--   request(1) =>request_signal(157),
+--   request(2) =>request_signal(158),
+--   request(3) =>request_signal(159),
+--   request(4) =>request_signal(160),
+--   request(5) =>request_signal(161),
+--   request(6) =>request_signal(162),
+--   request(7) =>request_signal(163),
+--   request(8) =>request_signal(164),
+--   request(9) =>request_signal(165),
+--   request(10) =>request_signal(166),
+--   request(11) =>request_signal(167),
+--   request(12) =>request_signal(168),
+--   request(13) =>request_signal(169)
+--);
+--
+--end generate switch13x13;
+--
+--
+---- switch 14 ports
+--switch14x14 : if number_of_ports = 14 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   grant(7) => grant_signal(7),
+--   grant(8) => grant_signal(8),
+--   grant(9) => grant_signal(9),
+--   grant(10) => grant_signal(10),
+--   grant(11) => grant_signal(11),
+--   grant(12) => grant_signal(12),
+--   grant(13) => grant_signal(13),
+--   grant(14) => grant_signal(14),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10),
+--   request(11) =>request_signal(11),
+--   request(12) =>request_signal(12),
+--   request(13) =>request_signal(13),
+--   request(14) =>request_signal(14)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(15),
+--   grant(2) => grant_signal(16),
+--   grant(3) => grant_signal(17),
+--   grant(4) => grant_signal(18),
+--   grant(5) => grant_signal(19),
+--   grant(6) => grant_signal(20),
+--   grant(7) => grant_signal(21),
+--   grant(8) => grant_signal(22),
+--   grant(9) => grant_signal(23),
+--   grant(10) => grant_signal(24),
+--   grant(11) => grant_signal(25),
+--   grant(12) => grant_signal(26),
+--   grant(13) => grant_signal(27),
+--   grant(14) => grant_signal(28),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(1) =>request_signal(15),
+--   request(2) =>request_signal(16),
+--   request(3) =>request_signal(17),
+--   request(4) =>request_signal(18),
+--   request(5) =>request_signal(19),
+--   request(6) =>request_signal(20),
+--   request(7) =>request_signal(21),
+--   request(8) =>request_signal(22),
+--   request(9) =>request_signal(23),
+--   request(10) =>request_signal(24),
+--   request(11) =>request_signal(25),
+--   request(12) =>request_signal(26),
+--   request(13) =>request_signal(27),
+--   request(14) =>request_signal(28)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(29),
+--   grant(2) => grant_signal(30),
+--   grant(3) => grant_signal(31),
+--   grant(4) => grant_signal(32),
+--   grant(5) => grant_signal(33),
+--   grant(6) => grant_signal(34),
+--   grant(7) => grant_signal(35),
+--   grant(8) => grant_signal(36),
+--   grant(9) => grant_signal(37),
+--   grant(10)=> grant_signal(38),
+--   grant(11) => grant_signal(39),
+--   grant(12) => grant_signal(40),
+--   grant(13) => grant_signal(41),
+--   grant(14) => grant_signal(42),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(01) =>request_signal(29),
+--   request(02) =>request_signal(30),
+--   request(03) =>request_signal(31),
+--   request(04) =>request_signal(32),
+--   request(05) =>request_signal(33),
+--   request(06) =>request_signal(34),
+--   request(07) =>request_signal(35),
+--   request(08) =>request_signal(36),
+--   request(09) =>request_signal(37),
+--   request(10) =>request_signal(38),
+--   request(11) =>request_signal(39),
+--   request(12) =>request_signal(40),
+--   request(13) =>request_signal(41),
+--   request(14) =>request_signal(42)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(01) => grant_signal(43),
+--   grant(02) => grant_signal(44),
+--   grant(03) => grant_signal(45),
+--   grant(04) => grant_signal(46),
+--   grant(05) => grant_signal(47),
+--   grant(06) => grant_signal(48),
+--   grant(07) => grant_signal(49),
+--   grant(08) => grant_signal(50),
+--   grant(09) => grant_signal(51),
+--   grant(10) => grant_signal(52),
+--   grant(11) => grant_signal(53),
+--   grant(12) => grant_signal(54),
+--   grant(13) => grant_signal(55),
+--   grant(14) => grant_signal(56),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(01) =>request_signal(43),
+--   request(02) =>request_signal(44),
+--   request(03) =>request_signal(45),
+--   request(04) =>request_signal(46),
+--   request(05) =>request_signal(47),
+--   request(06) =>request_signal(48),
+--   request(07) =>request_signal(49),
+--   request(08) =>request_signal(50),
+--   request(09) =>request_signal(51),
+--   request(10) =>request_signal(52),
+--   request(11) =>request_signal(53),
+--   request(12) =>request_signal(54),
+--   request(13) =>request_signal(55),
+--   request(14) =>request_signal(56)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(01) => grant_signal(57),
+--   grant(02) => grant_signal(58),
+--   grant(03) => grant_signal(59),
+--   grant(04) => grant_signal(60),
+--   grant(05) => grant_signal(61),
+--   grant(06) => grant_signal(62),
+--   grant(07) => grant_signal(63),
+--   grant(08) => grant_signal(64),
+--   grant(09) => grant_signal(65),
+--   grant(10) => grant_signal(66),
+--   grant(11) => grant_signal(67),
+--   grant(12) => grant_signal(68),
+--   grant(13) => grant_signal(69),
+--   grant(14) => grant_signal(70),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(01) =>request_signal(57),
+--   request(02) =>request_signal(58),
+--   request(03) =>request_signal(59),
+--   request(04) =>request_signal(60),
+--   request(05) =>request_signal(61),
+--   request(06) =>request_signal(62),
+--   request(07) =>request_signal(63),
+--   request(08) =>request_signal(64),
+--   request(09) =>request_signal(65),
+--   request(10) =>request_signal(66),
+--   request(11) =>request_signal(67),
+--   request(12) =>request_signal(68),
+--   request(13) =>request_signal(69),
+--   request(14) =>request_signal(70)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(01) => grant_signal(71),
+--   grant(02) => grant_signal(72),
+--   grant(03) => grant_signal(73),
+--   grant(04) => grant_signal(74),
+--   grant(05) => grant_signal(75),
+--   grant(06) => grant_signal(76),
+--   grant(07) => grant_signal(77),
+--   grant(08) => grant_signal(78),
+--   grant(09) => grant_signal(79),
+--   grant(10) => grant_signal(80),
+--   grant(11) => grant_signal(81),
+--   grant(12) => grant_signal(82),
+--   grant(13) => grant_signal(83),
+--   grant(14) => grant_signal(84),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(01) =>request_signal(71),
+--   request(02) =>request_signal(72),
+--   request(03) =>request_signal(73),
+--   request(04) =>request_signal(74),
+--   request(05) =>request_signal(75),
+--   request(06) =>request_signal(76),
+--   request(07) =>request_signal(77),
+--   request(08) =>request_signal(78),
+--   request(09) =>request_signal(79),
+--   request(10) =>request_signal(80),
+--   request(11) =>request_signal(81),
+--   request(12) =>request_signal(82),
+--   request(13) =>request_signal(83),
+--   request(14) =>request_signal(84)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(01) => grant_signal(85),
+--   grant(02) => grant_signal(86),
+--   grant(03) => grant_signal(87),
+--   grant(04) => grant_signal(88),
+--   grant(05) => grant_signal(89),
+--   grant(06) => grant_signal(90),
+--   grant(07) => grant_signal(91),
+--   grant(08) => grant_signal(92),
+--   grant(09) => grant_signal(93),
+--   grant(10) => grant_signal(94),
+--   grant(11) => grant_signal(95),
+--   grant(12) => grant_signal(96),
+--   grant(13) => grant_signal(97),
+--   grant(14) => grant_signal(98),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(7),
+--   data_out_pulse =>crossbar_in_pulse(7),
+--   request(01) =>request_signal(85),
+--   request(02) =>request_signal(86),
+--   request(03) =>request_signal(87),
+--   request(04) =>request_signal(88),
+--   request(05) =>request_signal(89),
+--   request(06) =>request_signal(90),
+--   request(07) =>request_signal(91),
+--   request(08) =>request_signal(92),
+--   request(09) =>request_signal(93),
+--   request(10) =>request_signal(94),
+--   request(11) =>request_signal(95),
+--   request(12) =>request_signal(96),
+--   request(13) =>request_signal(97),
+--   request(14) =>request_signal(98)
+--);
+--
+--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(8),
+--   data_in_en => data_in_en(8),
+--   reset => reset,
+--   clk =>clk,
+--   grant(01) => grant_signal(99),
+--   grant(02) => grant_signal(100),
+--   grant(03) => grant_signal(101),
+--   grant(04) => grant_signal(102),
+--   grant(05) => grant_signal(103),
+--   grant(06) => grant_signal(104),
+--   grant(07) => grant_signal(105),
+--   grant(08) => grant_signal(106),
+--   grant(09) => grant_signal(107),
+--   grant(10) => grant_signal(108),
+--   grant(11) => grant_signal(109),
+--   grant(12) => grant_signal(110),
+--   grant(13) => grant_signal(111),
+--   grant(14) => grant_signal(112),
+--   fifo_full =>fifo_in_full(8),
+--   priority_rotation =>  priority_rotation_signal(8),
+--   fifo_empty => fifo_in_empty(8),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(8),
+--   request(1) =>request_signal(99),
+--   request(2) =>request_signal(100),
+--   request(3) =>request_signal(101),
+--   request(4) =>request_signal(102),
+--   request(5) =>request_signal(103),
+--   request(6) =>request_signal(104),
+--   request(7) =>request_signal(105),
+--   request(8) =>request_signal(106),
+--   request(9) =>request_signal(107),
+--   request(10) =>request_signal(108),
+--   request(11) =>request_signal(109),
+--   request(12) =>request_signal(110),
+--   request(13) =>request_signal(111),
+--   request(14) =>request_signal(112)
+--);
+--
+--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(9),
+--   data_in_en => data_in_en(9),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(113),
+--   grant(2) => grant_signal(114),
+--   grant(3) => grant_signal(115),
+--   grant(4) => grant_signal(116),
+--   grant(5) => grant_signal(117),
+--   grant(6) => grant_signal(118),
+--   grant(7) => grant_signal(119),
+--   grant(8) => grant_signal(120),
+--   grant(9) => grant_signal(121),
+--   grant(10) => grant_signal(122),
+--   grant(11) => grant_signal(123),
+--   grant(12) => grant_signal(124),
+--   grant(13) => grant_signal(125),
+--   grant(14) => grant_signal(126),
+--   fifo_full =>fifo_in_full(9),
+--   priority_rotation =>  priority_rotation_signal(9),
+--   fifo_empty => fifo_in_empty(9),
+--   data_out =>crossbar_in_port(9),
+--   data_out_pulse =>crossbar_in_pulse(9),
+--   request(1) =>request_signal(113),
+--   request(2) =>request_signal(114),
+--   request(3) =>request_signal(115),
+--   request(4) =>request_signal(116),
+--   request(5) =>request_signal(117),
+--   request(6) =>request_signal(118),
+--   request(7) =>request_signal(119),
+--   request(8) =>request_signal(120),
+--   request(9) =>request_signal(121),
+--   request(10) =>request_signal(122),
+--   request(11) =>request_signal(123),
+--   request(12) =>request_signal(124),
+--   request(13) =>request_signal(125),
+--   request(14) =>request_signal(126)
+--);
+--
+--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(10),
+--   data_in_en => data_in_en(10),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(127),
+--   grant(2) => grant_signal(128),
+--   grant(3) => grant_signal(129),
+--   grant(4) => grant_signal(130),
+--   grant(5) => grant_signal(131),
+--   grant(6) => grant_signal(132),
+--   grant(7) => grant_signal(133),
+--   grant(8) => grant_signal(134),
+--   grant(9) => grant_signal(135),
+--   grant(10) => grant_signal(136),
+--   grant(11) => grant_signal(137),
+--   grant(12) => grant_signal(138),
+--   grant(13) => grant_signal(139),
+--   grant(14) => grant_signal(140),
+--   fifo_full =>fifo_in_full(10),
+--   priority_rotation =>  priority_rotation_signal(10),
+--   fifo_empty => fifo_in_empty(10),
+--   data_out =>crossbar_in_port(10),
+--   data_out_pulse =>crossbar_in_pulse(10),
+--   request(1) =>request_signal(127),
+--   request(2) =>request_signal(128),
+--   request(3) =>request_signal(129),
+--   request(4) =>request_signal(130),
+--   request(5) =>request_signal(131),
+--   request(6) =>request_signal(132),
+--   request(7) =>request_signal(133),
+--   request(8) =>request_signal(134),
+--   request(9) =>request_signal(135),
+--   request(10) =>request_signal(136),
+--   request(11) =>request_signal(137),
+--   request(12) =>request_signal(138),
+--   request(13) =>request_signal(139),
+--   request(14) =>request_signal(140)
+--);
+--
+--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(11),
+--   data_in_en => data_in_en(11),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(141),
+--   grant(2) => grant_signal(142),
+--   grant(3) => grant_signal(143),
+--   grant(4) => grant_signal(144),
+--   grant(5) => grant_signal(145),
+--   grant(6) => grant_signal(146),
+--   grant(7) => grant_signal(147),
+--   grant(8) => grant_signal(148),
+--   grant(9) => grant_signal(149),
+--   grant(10) => grant_signal(150),
+--   grant(11) => grant_signal(151),
+--   grant(12) => grant_signal(152),
+--   grant(13) => grant_signal(153),
+--   grant(14) => grant_signal(154),
+--   fifo_full =>fifo_in_full(11),
+--   priority_rotation =>  priority_rotation_signal(11),
+--   fifo_empty => fifo_in_empty(11),
+--   data_out =>crossbar_in_port(11),
+--   data_out_pulse =>crossbar_in_pulse(11),
+--   request(1) =>request_signal(141),
+--   request(2) =>request_signal(142),
+--   request(3) =>request_signal(143),
+--   request(4) =>request_signal(144),
+--   request(5) =>request_signal(145),
+--   request(6) =>request_signal(146),
+--   request(7) =>request_signal(147),
+--   request(8) =>request_signal(148),
+--   request(9) =>request_signal(149),
+--   request(10) =>request_signal(150),
+--   request(11) =>request_signal(151),
+--   request(12) =>request_signal(152),
+--   request(13) =>request_signal(153),
+--   request(14) =>request_signal(154)
+--);
+--
+--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(12),
+--   data_in_en => data_in_en(12),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(155),
+--   grant(2) => grant_signal(156),
+--   grant(3) => grant_signal(157),
+--   grant(4) => grant_signal(158),
+--   grant(5) => grant_signal(159),
+--   grant(6) => grant_signal(160),
+--   grant(7) => grant_signal(161),
+--   grant(8) => grant_signal(162),
+--   grant(9) => grant_signal(163),
+--   grant(10) => grant_signal(164),
+--   grant(11) => grant_signal(165),
+--   grant(12) => grant_signal(166),
+--   grant(13) => grant_signal(167),
+--   grant(14) => grant_signal(168),
+--   fifo_full =>fifo_in_full(12),
+--   priority_rotation =>  priority_rotation_signal(12),
+--   fifo_empty => fifo_in_empty(12),
+--   data_out =>crossbar_in_port(12),
+--   data_out_pulse =>crossbar_in_pulse(12),
+--   request(1) =>request_signal(155),
+--   request(2) =>request_signal(156),
+--   request(3) =>request_signal(157),
+--   request(4) =>request_signal(158),
+--   request(5) =>request_signal(159),
+--   request(6) =>request_signal(160),
+--   request(7) =>request_signal(161),
+--   request(8) =>request_signal(162),
+--   request(9) =>request_signal(163),
+--   request(10) =>request_signal(164),
+--   request(11) =>request_signal(165),
+--   request(12) =>request_signal(166),
+--   request(13) =>request_signal(167),
+--   request(14) =>request_signal(168)
+--);
+--
+--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(13),
+--   data_in_en => data_in_en(13),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(169),
+--   grant(2) => grant_signal(170),
+--   grant(3) => grant_signal(171),
+--   grant(4) => grant_signal(172),
+--   grant(5) => grant_signal(173),
+--   grant(6) => grant_signal(174),
+--   grant(7) => grant_signal(175),
+--   grant(8) => grant_signal(176),
+--   grant(9) => grant_signal(177),
+--   grant(10) => grant_signal(178),
+--   grant(11) => grant_signal(179),
+--   grant(12) => grant_signal(180),
+--   grant(13) => grant_signal(181),
+--   grant(14) => grant_signal(182),
+--   fifo_full =>fifo_in_full(13),
+--   priority_rotation =>  priority_rotation_signal(13),
+--   fifo_empty => fifo_in_empty(13),
+--   data_out =>crossbar_in_port(13),
+--   data_out_pulse =>crossbar_in_pulse(13),
+--   request(1) =>request_signal(169),
+--   request(2) =>request_signal(170),
+--   request(3) =>request_signal(171),
+--   request(4) =>request_signal(172),
+--   request(5) =>request_signal(173),
+--   request(6) =>request_signal(174),
+--   request(7) =>request_signal(175),
+--   request(8) =>request_signal(176),
+--   request(9) =>request_signal(177),
+--   request(10) =>request_signal(178),
+--   request(11) =>request_signal(179),
+--   request(12) =>request_signal(180),
+--   request(13) =>request_signal(181),
+--   request(14) =>request_signal(182)
+--);
+--
+--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>14)
+--PORT MAP(
+--   data_in => Port_in(14),
+--   data_in_en => data_in_en(14),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(183),
+--   grant(2) => grant_signal(184),
+--   grant(3) => grant_signal(185),
+--   grant(4) => grant_signal(186),
+--   grant(5) => grant_signal(187),
+--   grant(6) => grant_signal(188),
+--   grant(7) => grant_signal(189),
+--   grant(8) => grant_signal(190),
+--   grant(9) => grant_signal(191),
+--   grant(10) => grant_signal(192),
+--   grant(11) => grant_signal(193),
+--   grant(12) => grant_signal(194),
+--   grant(13) => grant_signal(195),
+--   grant(14) => grant_signal(196),
+--   fifo_full =>fifo_in_full(14),
+--   priority_rotation =>  priority_rotation_signal(14),
+--   fifo_empty => fifo_in_empty(14),
+--   data_out =>crossbar_in_port(14),
+--   data_out_pulse =>crossbar_in_pulse(14),
+--   request(1) =>request_signal(183),
+--   request(2) =>request_signal(184),
+--   request(3) =>request_signal(185),
+--   request(4) =>request_signal(186),
+--   request(5) =>request_signal(187),
+--   request(6) =>request_signal(188),
+--   request(7) =>request_signal(189),
+--   request(8) =>request_signal(190),
+--   request(9) =>request_signal(191),
+--   request(10) =>request_signal(192),
+--   request(11) =>request_signal(193),
+--   request(12) =>request_signal(194),
+--   request(13) =>request_signal(195),
+--   request(14) =>request_signal(196)
+--);
+--
+--end generate switch14x14;
+--
+--
+---- switch 15 ports
+--switch15x15 : if number_of_ports = 15 generate
+--
+--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(1),
+--   data_in_en => data_in_en(1),
+--   reset => reset,
+--   clk =>clk,
+--   grant(1) => grant_signal(1),
+--   grant(2) => grant_signal(2),
+--   grant(3) => grant_signal(3),
+--   grant(4) => grant_signal(4),
+--   grant(5) => grant_signal(5),
+--   grant(6) => grant_signal(6),
+--   grant(7) => grant_signal(7),
+--   grant(8) => grant_signal(8),
+--   grant(9) => grant_signal(9),
+--   grant(10) => grant_signal(10),
+--   grant(11) => grant_signal(11),
+--   grant(12) => grant_signal(12),
+--   grant(13) => grant_signal(13),
+--   grant(14) => grant_signal(14),
+--   grant(15) => grant_signal(15),
+--   fifo_full =>fifo_in_full(1),
+--   priority_rotation =>  priority_rotation_signal(1),
+--   fifo_empty => fifo_in_empty(1),
+--   data_out =>crossbar_in_port(1),
+--   data_out_pulse =>crossbar_in_pulse(1),
+--   request(1) =>request_signal(1),
+--   request(2) =>request_signal(2),
+--   request(3) =>request_signal(3),
+--   request(4) =>request_signal(4),
+--   request(5) =>request_signal(5),
+--   request(6) =>request_signal(6),
+--   request(7) =>request_signal(7),
+--   request(8) =>request_signal(8),
+--   request(9) =>request_signal(9),
+--   request(10) =>request_signal(10),
+--   request(11) =>request_signal(11),
+--   request(12) =>request_signal(12),
+--   request(13) =>request_signal(13),
+--   request(14) =>request_signal(14),
+--   request(15) =>request_signal(15)
+--);
+--
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(16) => grant_signal(16),
+--   grant(17) => grant_signal(17),
+--   grant(18) => grant_signal(18),
+--   grant(19) => grant_signal(19),
+--   grant(20) => grant_signal(20),
+--   grant(21) => grant_signal(21),
+--   grant(22) => grant_signal(22),
+--   grant(23) => grant_signal(23),
+--   grant(24) => grant_signal(24),
+--   grant(25) => grant_signal(25),
+--   grant(26) => grant_signal(26),
+--   grant(27) => grant_signal(27),
+--   grant(28) => grant_signal(28),
+--   grant(29) => grant_signal(29),
+--   grant(30) => grant_signal(30),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port(2),
+--   data_out_pulse =>crossbar_in_pulse(2),
+--   request(16) =>request_signal(16),
+--   request(17) =>request_signal(17),
+--   request(18) =>request_signal(18),
+--   request(19) =>request_signal(19),
+--   request(20) =>request_signal(20),
+--   request(21) =>request_signal(21),
+--   request(22) =>request_signal(22),
+--   request(23) =>request_signal(23),
+--   request(24) =>request_signal(24),
+--   request(25) =>request_signal(25),
+--   request(26) =>request_signal(26),
+--   request(27) =>request_signal(27),
+--   request(28) =>request_signal(28),
+--   request(29) =>request_signal(29),
+--   request(30) =>request_signal(30)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(31) => grant_signal(31),
+--   grant(32) => grant_signal(32),
+--   grant(33) => grant_signal(33),
+--   grant(34) => grant_signal(34),
+--   grant(35) => grant_signal(35),
+--   grant(36) => grant_signal(36),
+--   grant(37) => grant_signal(37),
+--   grant(38) => grant_signal(38),
+--   grant(39) => grant_signal(39),
+--   grant(40) => grant_signal(40),
+--   grant(41) => grant_signal(41),
+--   grant(42) => grant_signal(42),
+--   grant(43) => grant_signal(43),
+--   grant(44) => grant_signal(44),
+--   grant(45) => grant_signal(45),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port(3),
+--   data_out_pulse =>crossbar_in_pulse(3),
+--   request(31) =>request_signal(31),
+--   request(32) =>request_signal(32),
+--   request(33) =>request_signal(33),
+--   request(34) =>request_signal(34),
+--   request(35) =>request_signal(35),
+--   request(36) =>request_signal(36),
+--   request(37) =>request_signal(37),
+--   request(38) =>request_signal(38),
+--   request(39) =>request_signal(39),
+--   request(40) =>request_signal(40),
+--   request(41) =>request_signal(41),
+--   request(42) =>request_signal(42),
+--   request(43) =>request_signal(43),
+--   request(44) =>request_signal(44),
+--   request(45) =>request_signal(45)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(46) => grant_signal(46),
+--   grant(47) => grant_signal(47),
+--   grant(48) => grant_signal(48),
+--   grant(49) => grant_signal(49),
+--   grant(50) => grant_signal(50),
+--   grant(51) => grant_signal(51),
+--   grant(52) => grant_signal(52),
+--   grant(53) => grant_signal(53),
+--   grant(54) => grant_signal(54),
+--   grant(55) => grant_signal(55),
+--   grant(56) => grant_signal(56),
+--   grant(57) => grant_signal(57),
+--   grant(58) => grant_signal(58),
+--   grant(59) => grant_signal(59),
+--   grant(60) => grant_signal(60),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4),
+--   request(46) =>request_signal(46),
+--   request(47) =>request_signal(47),
+--   request(48) =>request_signal(48),
+--   request(49) =>request_signal(49),
+--   request(50) =>request_signal(50),
+--   request(51) =>request_signal(51),
+--   request(52) =>request_signal(52),
+--   request(53) =>request_signal(53),
+--   request(54) =>request_signal(54),
+--   request(55) =>request_signal(55),
+--   request(56) =>request_signal(56),
+--   request(57) =>request_signal(57),
+--   request(58) =>request_signal(58),
+--   request(59) =>request_signal(59),
+--   request(60) =>request_signal(60)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(61) => grant_signal(61),
+--   grant(62) => grant_signal(62),
+--   grant(63) => grant_signal(63),
+--   grant(64) => grant_signal(64),
+--   grant(65) => grant_signal(65),
+--   grant(66) => grant_signal(66),
+--   grant(67) => grant_signal(67),
+--   grant(68) => grant_signal(68),
+--   grant(69) => grant_signal(69),
+--   grant(70) => grant_signal(70),
+--   grant(71) => grant_signal(71),
+--   grant(72) => grant_signal(72),
+--   grant(73) => grant_signal(73),
+--   grant(74) => grant_signal(74),
+--   grant(75) => grant_signal(75),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5),
+--   request(61) =>request_signal(61),
+--   request(62) =>request_signal(62),
+--   request(63) =>request_signal(63),
+--   request(64) =>request_signal(64),
+--   request(65) =>request_signal(65),
+--   request(66) =>request_signal(66),
+--   request(67) =>request_signal(67),
+--   request(68) =>request_signal(68),
+--   request(69) =>request_signal(69),
+--   request(70) =>request_signal(70),
+--   request(71) =>request_signal(71),
+--   request(72) =>request_signal(72),
+--   request(73) =>request_signal(73),
+--   request(74) =>request_signal(74),
+--   request(75) =>request_signal(75)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(76) => grant_signal(76),
+--   grant(77) => grant_signal(77),
+--   grant(78) => grant_signal(78),
+--   grant(79) => grant_signal(79),
+--   grant(80) => grant_signal(80),
+--   grant(81) => grant_signal(81),
+--   grant(82) => grant_signal(82),
+--   grant(83) => grant_signal(83),
+--   grant(84) => grant_signal(84),
+--   grant(85) => grant_signal(85),
+--   grant(86) => grant_signal(86),
+--   grant(87) => grant_signal(87),
+--   grant(88) => grant_signal(88),
+--   grant(89) => grant_signal(89),
+--   grant(90) => grant_signal(90),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6),
+--   request(76) =>request_signal(76),
+--   request(77) =>request_signal(77),
+--   request(78) =>request_signal(78),
+--   request(79) =>request_signal(79),
+--   request(80) =>request_signal(80),
+--   request(81) =>request_signal(81),
+--   request(82) =>request_signal(82),
+--   request(83) =>request_signal(83),
+--   request(84) =>request_signal(84),
+--   request(85) =>request_signal(85),
+--   request(86) =>request_signal(86),
+--   request(87) =>request_signal(87),
+--   request(88) =>request_signal(88),
+--   request(89) =>request_signal(89),
+--   request(90) =>request_signal(90)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(91) => grant_signal(91),
+--   grant(92) => grant_signal(92),
+--   grant(93) => grant_signal(93),
+--   grant(94) => grant_signal(94),
+--   grant(95) => grant_signal(95),
+--   grant(96) => grant_signal(96),
+--   grant(97) => grant_signal(97),
+--   grant(98) => grant_signal(98),
+--   grant(99) => grant_signal(99),
+--   grant(100) => grant_signal(100),
+--   grant(101) => grant_signal(101),
+--   grant(102) => grant_signal(102),
+--   grant(103) => grant_signal(103),
+--   grant(104) => grant_signal(104),
+--   grant(105) => grant_signal(105),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(7),
+--   data_out_pulse =>crossbar_in_pulse(7),
+--   request(91) =>request_signal(91),
+--   request(92) =>request_signal(92),
+--   request(93) =>request_signal(93),
+--   request(94) =>request_signal(94),
+--   request(95) =>request_signal(95),
+--   request(96) =>request_signal(96),
+--   request(97) =>request_signal(97),
+--   request(98) =>request_signal(98),
+--   request(99) =>request_signal(99),
+--   request(100) =>request_signal(100),
+--   request(101) =>request_signal(101),
+--   request(102) =>request_signal(102),
+--   request(103) =>request_signal(103),
+--   request(104) =>request_signal(104),
+--   request(105) =>request_signal(105)
+--);
+--
+--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(8),
+--   data_in_en => data_in_en(8),
+--   reset => reset,
+--   clk =>clk,
+--   grant(106) => grant_signal(106),
+--   grant(107) => grant_signal(107),
+--   grant(108) => grant_signal(108),
+--   grant(109) => grant_signal(109),
+--   grant(110) => grant_signal(110),
+--   grant(111) => grant_signal(111),
+--   grant(112) => grant_signal(112),
+--   grant(113) => grant_signal(113),
+--   grant(114) => grant_signal(114),
+--   grant(115) => grant_signal(115),
+--   grant(116) => grant_signal(116),
+--   grant(117) => grant_signal(117),
+--   grant(118) => grant_signal(118),
+--   grant(119) => grant_signal(119),
+--   grant(120) => grant_signal(120),
+--   fifo_full =>fifo_in_full(8),
+--   priority_rotation =>  priority_rotation_signal(8),
+--   fifo_empty => fifo_in_empty(8),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(8),
+--   request(106) =>request_signal(106),
+--   request(107) =>request_signal(107),
+--   request(108) =>request_signal(108),
+--   request(109) =>request_signal(109),
+--   request(110) =>request_signal(110),
+--   request(111) =>request_signal(111),
+--   request(112) =>request_signal(112),
+--   request(113) =>request_signal(113),
+--   request(114) =>request_signal(114),
+--   request(115) =>request_signal(115),
+--   request(116) =>request_signal(116),
+--   request(117) =>request_signal(117),
+--   request(118) =>request_signal(118),
+--   request(119) =>request_signal(119),
+--   request(120) =>request_signal(120)
+--);
+--
+--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(9),
+--   data_in_en => data_in_en(9),
+--   reset => reset,
+--   clk =>clk,
+--   grant(121) => grant_signal(121),
+--   grant(122) => grant_signal(122),
+--   grant(123) => grant_signal(123),
+--   grant(124) => grant_signal(124),
+--   grant(125) => grant_signal(125),
+--   grant(126) => grant_signal(126),
+--   grant(127) => grant_signal(127),
+--   grant(128) => grant_signal(128),
+--   grant(129) => grant_signal(129),
+--   grant(130) => grant_signal(130),
+--   grant(131) => grant_signal(131),
+--   grant(132) => grant_signal(132),
+--   grant(133) => grant_signal(133),
+--   grant(134) => grant_signal(134),
+--   grant(135) => grant_signal(135),
+--   fifo_full =>fifo_in_full(9),
+--   priority_rotation =>  priority_rotation_signal(9),
+--   fifo_empty => fifo_in_empty(9),
+--   data_out =>crossbar_in_port(9),
+--   data_out_pulse =>crossbar_in_pulse(9),
+--   request(121) =>request_signal(121),
+--   request(122) =>request_signal(122),
+--   request(123) =>request_signal(123),
+--   request(124) =>request_signal(124),
+--   request(125) =>request_signal(125),
+--   request(126) =>request_signal(126),
+--   request(127) =>request_signal(127),
+--   request(128) =>request_signal(128),
+--   request(129) =>request_signal(129),
+--   request(130) =>request_signal(130),
+--   request(131) =>request_signal(131),
+--   request(132) =>request_signal(132),
+--   request(133) =>request_signal(133),
+--   request(134) =>request_signal(134),
+--   request(135) =>request_signal(135)
+--);
+--
+--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(10),
+--   data_in_en => data_in_en(10),
+--   reset => reset,
+--   clk =>clk,
+--   grant(136) => grant_signal(136),
+--   grant(137) => grant_signal(137),
+--   grant(138) => grant_signal(138),
+--   grant(139) => grant_signal(139),
+--   grant(140) => grant_signal(140),
+--   grant(141) => grant_signal(141),
+--   grant(142) => grant_signal(142),
+--   grant(143) => grant_signal(143),
+--   grant(144) => grant_signal(144),
+--   grant(145) => grant_signal(145),
+--   grant(146) => grant_signal(146),
+--   grant(147) => grant_signal(147),
+--   grant(148) => grant_signal(148),
+--   grant(149) => grant_signal(149),
+--   grant(150) => grant_signal(150),
+--   fifo_full =>fifo_in_full(10),
+--   priority_rotation =>  priority_rotation_signal(10),
+--   fifo_empty => fifo_in_empty(10),
+--   data_out =>crossbar_in_port(10),
+--   data_out_pulse =>crossbar_in_pulse(10),
+--   request(136) =>request_signal(136),
+--   request(137) =>request_signal(137),
+--   request(138) =>request_signal(138),
+--   request(139) =>request_signal(139),
+--   request(140) =>request_signal(140),
+--   request(141) =>request_signal(141),
+--   request(142) =>request_signal(142),
+--   request(143) =>request_signal(143),
+--   request(144) =>request_signal(144),
+--   request(145) =>request_signal(145),
+--   request(146) =>request_signal(146),
+--   request(147) =>request_signal(147),
+--   request(148) =>request_signal(148),
+--   request(149) =>request_signal(149),
+--   request(150) =>request_signal(150)
+--);
+--
+--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(11),
+--   data_in_en => data_in_en(11),
+--   reset => reset,
+--   clk =>clk,
+--   grant(151) => grant_signal(151),
+--   grant(152) => grant_signal(152),
+--   grant(153) => grant_signal(153),
+--   grant(154) => grant_signal(154),
+--   grant(155) => grant_signal(155),
+--   grant(156) => grant_signal(156),
+--   grant(157) => grant_signal(157),
+--   grant(158) => grant_signal(158),
+--   grant(159) => grant_signal(159),
+--   grant(160) => grant_signal(160),
+--   grant(161) => grant_signal(161),
+--   grant(162) => grant_signal(162),
+--   grant(163) => grant_signal(163),
+--   grant(164) => grant_signal(164),
+--   grant(165) => grant_signal(165),
+--   fifo_full =>fifo_in_full(11),
+--   priority_rotation =>  priority_rotation_signal(11),
+--   fifo_empty => fifo_in_empty(11),
+--   data_out =>crossbar_in_port(11),
+--   data_out_pulse =>crossbar_in_pulse(11),
+--   request(151) =>request_signal(151),
+--   request(152) =>request_signal(152),
+--   request(153) =>request_signal(153),
+--   request(154) =>request_signal(154),
+--   request(155) =>request_signal(155),
+--   request(156) =>request_signal(156),
+--   request(157) =>request_signal(157),
+--   request(158) =>request_signal(158),
+--   request(159) =>request_signal(159),
+--   request(160) =>request_signal(160),
+--   request(161) =>request_signal(161),
+--   request(162) =>request_signal(162),
+--   request(163) =>request_signal(163),
+--   request(164) =>request_signal(164),
+--   request(165) =>request_signal(165)
+--);
+--
+--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(12),
+--   data_in_en => data_in_en(12),
+--   reset => reset,
+--   clk =>clk,
+--   grant(166) => grant_signal(166),
+--   grant(167) => grant_signal(167),
+--   grant(168) => grant_signal(168),
+--   grant(169) => grant_signal(169),
+--   grant(170) => grant_signal(170),
+--   grant(171) => grant_signal(171),
+--   grant(172) => grant_signal(172),
+--   grant(173) => grant_signal(173),
+--   grant(174) => grant_signal(174),
+--   grant(175) => grant_signal(175),
+--   grant(176) => grant_signal(176),
+--   grant(177) => grant_signal(177),
+--   grant(178) => grant_signal(178),
+--   grant(179) => grant_signal(179),
+--   grant(180) => grant_signal(180),
+--   fifo_full =>fifo_in_full(12),
+--   priority_rotation =>  priority_rotation_signal(12),
+--   fifo_empty => fifo_in_empty(12),
+--   data_out =>crossbar_in_port(12),
+--   data_out_pulse =>crossbar_in_pulse(12),
+--   request(166) =>request_signal(166),
+--   request(167) =>request_signal(167),
+--   request(168) =>request_signal(168),
+--   request(169) =>request_signal(169),
+--   request(170) =>request_signal(170),
+--   request(171) =>request_signal(171),
+--   request(172) =>request_signal(172),
+--   request(173) =>request_signal(173),
+--   request(174) =>request_signal(174),
+--   request(175) =>request_signal(175),
+--   request(176) =>request_signal(176),
+--   request(177) =>request_signal(177),
+--   request(178) =>request_signal(178),
+--   request(179) =>request_signal(179),
+--   request(180) =>request_signal(180)
+--);
+--
+--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(13),
+--   data_in_en => data_in_en(13),
+--   reset => reset,
+--   clk =>clk,
+--   grant(181) => grant_signal(181),
+--   grant(182) => grant_signal(182),
+--   grant(183) => grant_signal(183),
+--   grant(184) => grant_signal(184),
+--   grant(185) => grant_signal(185),
+--   grant(186) => grant_signal(186),
+--   grant(187) => grant_signal(187),
+--   grant(188) => grant_signal(188),
+--   grant(189) => grant_signal(189),
+--   grant(190) => grant_signal(190),
+--   grant(191) => grant_signal(191),
+--   grant(192) => grant_signal(192),
+--   grant(193) => grant_signal(193),
+--   grant(194) => grant_signal(194),
+--   grant(195) => grant_signal(195),
+--   fifo_full =>fifo_in_full(13),
+--   priority_rotation =>  priority_rotation_signal(13),
+--   fifo_empty => fifo_in_empty(13),
+--   data_out =>crossbar_in_port(13),
+--   data_out_pulse =>crossbar_in_pulse(13),
+--   request(181) =>request_signal(181),
+--   request(182) =>request_signal(182),
+--   request(183) =>request_signal(183),
+--   request(184) =>request_signal(184),
+--   request(185) =>request_signal(185),
+--   request(186) =>request_signal(186),
+--   request(187) =>request_signal(187),
+--   request(188) =>request_signal(188),
+--   request(189) =>request_signal(189),
+--   request(190) =>request_signal(190),
+--   request(191) =>request_signal(191),
+--   request(192) =>request_signal(192),
+--   request(193) =>request_signal(193),
+--   request(194) =>request_signal(194),
+--   request(195) =>request_signal(195)
+--);
+--
+--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(14),
+--   data_in_en => data_in_en(14),
+--   reset => reset,
+--   clk =>clk,
+--   grant(196) => grant_signal(196),
+--   grant(197) => grant_signal(197),
+--   grant(198) => grant_signal(198),
+--   grant(199) => grant_signal(199),
+--   grant(200) => grant_signal(200),
+--   grant(201) => grant_signal(201),
+--   grant(202) => grant_signal(202),
+--   grant(203) => grant_signal(203),
+--   grant(204) => grant_signal(204),
+--   grant(205) => grant_signal(205),
+--   grant(206) => grant_signal(206),
+--   grant(207) => grant_signal(207),
+--   grant(208) => grant_signal(208),
+--   grant(209) => grant_signal(209),
+--   grant(210) => grant_signal(210),
+--   fifo_full =>fifo_in_full(14),
+--   priority_rotation =>  priority_rotation_signal(14),
+--   fifo_empty => fifo_in_empty(14),
+--   data_out =>crossbar_in_port(14),
+--   data_out_pulse =>crossbar_in_pulse(14),
+--   request(196) =>request_signal(196),
+--   request(197) =>request_signal(197),
+--   request(198) =>request_signal(198),
+--   request(199) =>request_signal(199),
+--   request(200) =>request_signal(200),
+--   request(201) =>request_signal(201),
+--   request(202) =>request_signal(202),
+--   request(203) =>request_signal(203),
+--   request(204) =>request_signal(204),
+--   request(205) =>request_signal(205),
+--   request(206) =>request_signal(206),
+--   request(207) =>request_signal(207),
+--   request(208) =>request_signal(208),
+--   request(209) =>request_signal(209),
+--   request(210) =>request_signal(210)
+--);
+--
+--PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>15)
+--PORT MAP(
+--   data_in => Port_in(15),
+--   data_in_en => data_in_en(15),
+--   reset => reset,
+--   clk =>clk,
+--   grant(211) => grant_signal(211),
+--   grant(212) => grant_signal(212),
+--   grant(213) => grant_signal(213),
+--   grant(214) => grant_signal(214),
+--   grant(215) => grant_signal(215),
+--   grant(216) => grant_signal(216),
+--   grant(217) => grant_signal(217),
+--   grant(218) => grant_signal(218),
+--   grant(219) => grant_signal(219),
+--   grant(220) => grant_signal(220),
+--   grant(221) => grant_signal(221),
+--   grant(222) => grant_signal(222),
+--   grant(223) => grant_signal(223),
+--   grant(224) => grant_signal(224),
+--   grant(225) => grant_signal(225),
+--   fifo_full =>fifo_in_full(15),
+--   priority_rotation =>  priority_rotation_signal(15),
+--   fifo_empty => fifo_in_empty(15),
+--   data_out =>crossbar_in_port(15),
+--   data_out_pulse =>crossbar_in_pulse(15),
+--   request(211) =>request_signal(211),
+--   request(212) =>request_signal(212),
+--   request(213) =>request_signal(213),
+--   request(214) =>request_signal(214),
+--   request(215) =>request_signal(215),
+--   request(216) =>request_signal(216),
+--   request(217) =>request_signal(217),
+--   request(218) =>request_signal(218),
+--   request(219) =>request_signal(219),
+--   request(220) =>request_signal(220),
+--   request(221) =>request_signal(221),
+--   request(222) =>request_signal(222),
+--   request(223) =>request_signal(223),
+--   request(224) =>request_signal(224),
+--   request(225) =>request_signal(225)
+--);
+--
+--end generate switch15x15;
+
+
+-- switch 16 ports
+switch16x16 : if number_of_ports = 16 generate
+switch_16x16 :for i in 1 to number_of_ports generate
+Constant j : natural:=number_of_ports*(i-1);
+begin
+--j<=number_of_ports*(i-1);
+PORTx16_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16,port_num=>i)
+PORT MAP(
+   data_in => Port_in(i),
+   data_in_en => data_in_en(i),
+	cmd_in_en => cmd_in_en(i),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(j+1),
+   grant(2) => grant_signal(j+2),
+   grant(3) => grant_signal(j+3),
+   grant(4) => grant_signal(j+4),
+   grant(5) => grant_signal(j+5),
+   grant(6) => grant_signal(j+6),
+   grant(7) => grant_signal(j+7),
+   grant(8) => grant_signal(j+8),
+   grant(9) => grant_signal(j+9),
+   grant(10) => grant_signal(j+10),
+   grant(11) => grant_signal(j+11),
+   grant(12) => grant_signal(j+12),
+   grant(13) => grant_signal(j+13),
+   grant(14) => grant_signal(j+14),
+   grant(15) => grant_signal(j+15),
+   grant(16) => grant_signal(j+16),
+   fifo_full =>fifo_in_full(i),
+   priority_rotation => priority_rotation_signal(i),
+   fifo_empty => fifo_in_empty(i),
+   data_out =>crossbar_in_port(i),
+   data_out_pulse =>crossbar_in_pulse(i),
+   request(1) =>request_signal(j+1),
+   request(2) =>request_signal(j+2),
+   request(3) =>request_signal(j+3),
+   request(4) =>request_signal(j+4),
+   request(5) =>request_signal(j+5),
+   request(6) =>request_signal(j+6),
+   request(7) =>request_signal(j+7),
+   request(8) =>request_signal(j+8),
+   request(9) =>request_signal(j+9),
+   request(10) =>request_signal(j+10),
+   request(11) =>request_signal(j+11),
+   request(12) =>request_signal(j+12),
+   request(13) =>request_signal(j+13),
+   request(14) =>request_signal(j+14),
+   request(15) =>request_signal(j+15),
+   request(16) =>request_signal(j+16)
+);
+end generate switch_16x16;
+end generate switch16x16;
+--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(2),
+--   data_in_en => data_in_en(2),
+--   reset => reset,
+--   clk =>clk,
+--   grant(17) => grant_signal(17),
+--   grant(18) => grant_signal(18),
+--   grant(19) => grant_signal(19),
+--   grant(20) => grant_signal(20),
+--   grant(21) => grant_signal(21),
+--   grant(22) => grant_signal(22),
+--   grant(23) => grant_signal(23),
+--   grant(24) => grant_signal(24),
+--   grant(25) => grant_signal(25),
+--   grant(26) => grant_signal(26),
+--   grant(27) => grant_signal(27),
+--   grant(28) => grant_signal(28),
+--   grant(29) => grant_signal(29),
+--   grant(30) => grant_signal(30),
+--   grant(31) => grant_signal(31),
+--   grant(32) => grant_signal(32),
+--   fifo_full =>fifo_in_full(2),
+--   priority_rotation =>  priority_rotation_signal(2),
+--   fifo_empty => fifo_in_empty(2),
+--   data_out =>crossbar_in_port2,
+--   data_out_pulse =>crossbar_in_pulse(2,
+--   request(17) =>request_signal(17),
+--   request(18) =>request_signal(18),
+--   request(19) =>request_signal(19),
+--   request(20) =>request_signal(20),
+--   request(21) =>request_signal(21),
+--   request(22) =>request_signal(22),
+--   request(23) =>request_signal(23),
+--   request(24) =>request_signal(24),
+--   request(25) =>request_signal(25),
+--   request(26) =>request_signal(26),
+--   request(27) =>request_signal(27),
+--   request(28) =>request_signal(28),
+--   request(29) =>request_signal(29),
+--   request(30) =>request_signal(30),
+--   request(31) =>request_signal(31),
+--   request(32) =>request_signal(32)
+--);
+--
+--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(3),
+--   data_in_en => data_in_en(3),
+--   reset => reset,
+--   clk =>clk,
+--   grant(33) => grant_signal(33),
+--   grant(34) => grant_signal(34),
+--   grant(35) => grant_signal(35),
+--   grant(36) => grant_signal(36),
+--   grant(37) => grant_signal(37),
+--   grant(38) => grant_signal(38),
+--   grant(39) => grant_signal(39),
+--   grant(40) => grant_signal(40),
+--   grant(41) => grant_signal(41),
+--   grant(42) => grant_signal(42),
+--   grant(43) => grant_signal(43),
+--   grant(44) => grant_signal(44),
+--   grant(45) => grant_signal(45),
+--   grant(46) => grant_signal(46),
+--   grant(47) => grant_signal(47),
+--   grant(48) => grant_signal(48),
+--   fifo_full =>fifo_in_full(3),
+--   priority_rotation =>  priority_rotation_signal(3),
+--   fifo_empty => fifo_in_empty(3),
+--   data_out =>crossbar_in_port3,
+--   data_out_pulse =>crossbar_in_pulse(3,
+--   request(33) =>request_signal(33),
+--   request(34) =>request_signal(34),
+--   request(35) =>request_signal(35),
+--   request(36) =>request_signal(36),
+--   request(37) =>request_signal(37),
+--   request(38) =>request_signal(38),
+--   request(39) =>request_signal(39),
+--   request(40) =>request_signal(40),
+--   request(41) =>request_signal(41),
+--   request(42) =>request_signal(42),
+--   request(43) =>request_signal(43),
+--   request(44) =>request_signal(44),
+--   request(45) =>request_signal(45),
+--   request(46) =>request_signal(46),
+--   request(47) =>request_signal(47),
+--   request(48) =>request_signal(48)
+--);
+--
+--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(4),
+--   data_in_en => data_in_en(4),
+--   reset => reset,
+--   clk =>clk,
+--   grant(49) => grant_signal(49),
+--   grant(50) => grant_signal(50),
+--   grant(51) => grant_signal(51),
+--   grant(52) => grant_signal(52),
+--   grant(53) => grant_signal(53),
+--   grant(54) => grant_signal(54),
+--   grant(55) => grant_signal(55),
+--   grant(56) => grant_signal(56),
+--   grant(57) => grant_signal(57),
+--   grant(58) => grant_signal(58),
+--   grant(59) => grant_signal(59),
+--   grant(60) => grant_signal(60),
+--   grant(61) => grant_signal(61),
+--   grant(62) => grant_signal(62),
+--   grant(63) => grant_signal(63),
+--   grant(64) => grant_signal(64),
+--   fifo_full =>fifo_in_full(4),
+--   priority_rotation =>  priority_rotation_signal(4),
+--   fifo_empty => fifo_in_empty(4),
+--   data_out =>crossbar_in_port(4),
+--   data_out_pulse =>crossbar_in_pulse(4,
+--   request(49) =>request_signal(49),
+--   request(50) =>request_signal(50),
+--   request(51) =>request_signal(51),
+--   request(52) =>request_signal(52),
+--   request(53) =>request_signal(53),
+--   request(54) =>request_signal(54),
+--   request(55) =>request_signal(55),
+--   request(56) =>request_signal(56),
+--   request(57) =>request_signal(57),
+--   request(58) =>request_signal(58),
+--   request(59) =>request_signal(59),
+--   request(60) =>request_signal(60),
+--   request(61) =>request_signal(61),
+--   request(62) =>request_signal(62),
+--   request(63) =>request_signal(63),
+--   request(64) =>request_signal(64)
+--);
+--
+--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(5),
+--   data_in_en => data_in_en(5),
+--   reset => reset,
+--   clk =>clk,
+--   grant(65) => grant_signal(65),
+--   grant(66) => grant_signal(66),
+--   grant(67) => grant_signal(67),
+--   grant(68) => grant_signal(68),
+--   grant(69) => grant_signal(69),
+--   grant(70) => grant_signal(70),
+--   grant(71) => grant_signal(71),
+--   grant(72) => grant_signal(72),
+--   grant(73) => grant_signal(73),
+--   grant(74) => grant_signal(74),
+--   grant(75) => grant_signal(75),
+--   grant(76) => grant_signal(76),
+--   grant(77) => grant_signal(77),
+--   grant(78) => grant_signal(78),
+--   grant(79) => grant_signal(79),
+--   grant(80) => grant_signal(80),
+--   fifo_full =>fifo_in_full(5),
+--   priority_rotation =>  priority_rotation_signal(5),
+--   fifo_empty => fifo_in_empty(5),
+--   data_out =>crossbar_in_port(5),
+--   data_out_pulse =>crossbar_in_pulse(5,
+--   request(65) =>request_signal(65),
+--   request(66) =>request_signal(66),
+--   request(67) =>request_signal(67),
+--   request(68) =>request_signal(68),
+--   request(69) =>request_signal(69),
+--   request(70) =>request_signal(70),
+--   request(71) =>request_signal(71),
+--   request(72) =>request_signal(72),
+--   request(73) =>request_signal(73),
+--   request(74) =>request_signal(74),
+--   request(75) =>request_signal(75),
+--   request(76) =>request_signal(76),
+--   request(77) =>request_signal(77),
+--   request(78) =>request_signal(78),
+--   request(79) =>request_signal(79),
+--   request(80) =>request_signal(80)
+--);
+--
+--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(6),
+--   data_in_en => data_in_en(6),
+--   reset => reset,
+--   clk =>clk,
+--   grant(81) => grant_signal(81),
+--   grant(82) => grant_signal(82),
+--   grant(83) => grant_signal(83),
+--   grant(84) => grant_signal(84),
+--   grant(85) => grant_signal(85),
+--   grant(86) => grant_signal(86),
+--   grant(87) => grant_signal(87),
+--   grant(88) => grant_signal(88),
+--   grant(89) => grant_signal(89),
+--   grant(90) => grant_signal(90),
+--   grant(91) => grant_signal(91),
+--   grant(92) => grant_signal(92),
+--   grant(93) => grant_signal(93),
+--   grant(94) => grant_signal(94),
+--   grant(95) => grant_signal(95),
+--   grant(96) => grant_signal(96),
+--   fifo_full =>fifo_in_full(6),
+--   priority_rotation =>  priority_rotation_signal(6),
+--   fifo_empty => fifo_in_empty(6),
+--   data_out =>crossbar_in_port(6),
+--   data_out_pulse =>crossbar_in_pulse(6,
+--   request(81) =>request_signal(81),
+--   request(82) =>request_signal(82),
+--   request(83) =>request_signal(83),
+--   request(84) =>request_signal(84),
+--   request(85) =>request_signal(85),
+--   request(86) =>request_signal(86),
+--   request(87) =>request_signal(87),
+--   request(88) =>request_signal(88),
+--   request(89) =>request_signal(89),
+--   request(90) =>request_signal(90),
+--   request(91) =>request_signal(91),
+--   request(92) =>request_signal(92),
+--   request(93) =>request_signal(93),
+--   request(94) =>request_signal(94),
+--   request(95) =>request_signal(95),
+--   request(96) =>request_signal(96)
+--);
+--
+--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(7),
+--   data_in_en => data_in_en(7),
+--   reset => reset,
+--   clk =>clk,
+--   grant(97) => grant_signal(97),
+--   grant(98) => grant_signal(98),
+--   grant(99) => grant_signal(99),
+--   grant(0) => grant_signal(100),
+--   grant(1) => grant_signal(101),
+--   grant(2) => grant_signal(102),
+--   grant(3) => grant_signal(103),
+--   grant(4) => grant_signal(104),
+--   grant(5) => grant_signal(105),
+--   grant(6) => grant_signal(106),
+--   grant(7) => grant_signal(107),
+--   grant(8) => grant_signal(108),
+--   grant(9) => grant_signal(109),
+--   grant(110) => grant_signal(110),
+--   grant(111) => grant_signal(111),
+--   grant(112) => grant_signal(112),
+--   fifo_full =>fifo_in_full(7),
+--   priority_rotation =>  priority_rotation_signal(7),
+--   fifo_empty => fifo_in_empty(7),
+--   data_out =>crossbar_in_port(8),
+--   data_out_pulse =>crossbar_in_pulse(7,
+--   request(97) =>request_signal(97),
+--   request(98) =>request_signal(98),
+--   request(99) =>request_signal(99),
+--   request(100) =>request_signal(100),
+--   request(101) =>request_signal(101),
+--   request(102) =>request_signal(102),
+--   request(103) =>request_signal(103),
+--   request(104) =>request_signal(104),
+--   request(105) =>request_signal(105),
+--   request(106) =>request_signal(106),
+--   request(107) =>request_signal(107),
+--   request(108) =>request_signal(108),
+--   request(109) =>request_signal(109),
+--   request(110) =>request_signal(110),
+--   request(111) =>request_signal(111),
+--   request(112) =>request_signal(112)
+--);
+--
+--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(8),
+--   data_in_en => data_in_en(8),
+--   reset => reset,
+--   clk =>clk,
+--   grant(113) => grant_signal(113),
+--   grant(114) => grant_signal(114),
+--   grant(115) => grant_signal(115),
+--   grant(116) => grant_signal(116),
+--   grant(117) => grant_signal(117),
+--   grant(118) => grant_signal(118),
+--   grant(119) => grant_signal(119),
+--   grant(120) => grant_signal(120),
+--   grant(121) => grant_signal(121),
+--   grant(122) => grant_signal(122),
+--   grant(123) => grant_signal(123),
+--   grant(124) => grant_signal(124),
+--   grant(125) => grant_signal(125),
+--   grant(126) => grant_signal(126),
+--   grant(127) => grant_signal(127),
+--   grant(128) => grant_signal(128),
+--   fifo_full =>fifo_in_full(8),
+--   priority_rotation =>  priority_rotation_signal(8),
+--   fifo_empty => fifo_in_empty(8),
+--   data_out =>crossbar_in_port8,
+--   data_out_pulse =>crossbar_in_pulse(8,
+--   request(113) =>request_signal(113),
+--   request(114) =>request_signal(114),
+--   request(115) =>request_signal(115),
+--   request(116) =>request_signal(116),
+--   request(117) =>request_signal(117),
+--   request(118) =>request_signal(118),
+--   request(119) =>request_signal(119),
+--   request(120) =>request_signal(120),
+--   request(121) =>request_signal(121),
+--   request(122) =>request_signal(122),
+--   request(123) =>request_signal(123),
+--   request(124) =>request_signal(124),
+--   request(125) =>request_signal(125),
+--   request(126) =>request_signal(126),
+--   request(127) =>request_signal(127),
+--   request(128) =>request_signal(128)
+--);
+--
+--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(9),
+--   data_in_en => data_in_en(9),
+--   reset => reset,
+--   clk =>clk,
+--   grant(129) => grant_signal(129),
+--   grant(130) => grant_signal(130),
+--   grant(131) => grant_signal(131),
+--   grant(132) => grant_signal(132),
+--   grant(133) => grant_signal(133),
+--   grant(134) => grant_signal(134),
+--   grant(135) => grant_signal(135),
+--   grant(136) => grant_signal(136),
+--   grant(137) => grant_signal(137),
+--   grant(138) => grant_signal(138),
+--   grant(139) => grant_signal(139),
+--   grant(140) => grant_signal(140),
+--   grant(141) => grant_signal(141),
+--   grant(142) => grant_signal(142),
+--   grant(143) => grant_signal(143),
+--   grant(144) => grant_signal(144),
+--   fifo_full =>fifo_in_full(9),
+--   priority_rotation =>  priority_rotation_signal(9),
+--   fifo_empty => fifo_in_empty(9),
+--   data_out =>crossbar_in_port9,
+--   data_out_pulse =>crossbar_in_pulse(9),
+--   request(129) =>request_signal(129),
+--   request(130) =>request_signal(130),
+--   request(131) =>request_signal(131),
+--   request(132) =>request_signal(132),
+--   request(133) =>request_signal(133),
+--   request(134) =>request_signal(134),
+--   request(135) =>request_signal(135),
+--   request(136) =>request_signal(136),
+--   request(137) =>request_signal(137),
+--   request(138) =>request_signal(138),
+--   request(139) =>request_signal(139),
+--   request(140) =>request_signal(140),
+--   request(141) =>request_signal(141),
+--   request(142) =>request_signal(142),
+--   request(143) =>request_signal(143),
+--   request(144) =>request_signal(144)
+--);
+--
+--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(10),
+--   data_in_en => data_in_en(10),
+--   reset => reset,
+--   clk =>clk,
+--   grant(145) => grant_signal(145),
+--   grant(146) => grant_signal(146),
+--   grant(147) => grant_signal(147),
+--   grant(148) => grant_signal(148),
+--   grant(149) => grant_signal(149),
+--   grant(150) => grant_signal(150),
+--   grant(151) => grant_signal(151),
+--   grant(152) => grant_signal(152),
+--   grant(153) => grant_signal(153),
+--   grant(154) => grant_signal(154),
+--   grant(155) => grant_signal(155),
+--   grant(156) => grant_signal(156),
+--   grant(157) => grant_signal(157),
+--   grant(158) => grant_signal(158),
+--   grant(159) => grant_signal(159),
+--   grant(160) => grant_signal(160),
+--   fifo_full =>fifo_in_full(10),
+--   priority_rotation =>  priority_rotation_signal(10),
+--   fifo_empty => fifo_in_empty(10),
+--   data_out =>crossbar_in_port(10),
+--   data_out_pulse =>crossbar_in_pulse(10),
+--   request(145) =>request_signal(145),
+--   request(146) =>request_signal(146),
+--   request(147) =>request_signal(147),
+--   request(148) =>request_signal(148),
+--   request(149) =>request_signal(149),
+--   request(150) =>request_signal(150),
+--   request(151) =>request_signal(151),
+--   request(152) =>request_signal(152),
+--   request(153) =>request_signal(153),
+--   request(154) =>request_signal(154),
+--   request(155) =>request_signal(155),
+--   request(156) =>request_signal(156),
+--   request(157) =>request_signal(157),
+--   request(158) =>request_signal(158),
+--   request(159) =>request_signal(159),
+--   request(160) =>request_signal(160)
+--);
+--
+--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(11),
+--   data_in_en => data_in_en(11),
+--   reset => reset,
+--   clk =>clk,
+--   grant(161) => grant_signal(161),
+--   grant(162) => grant_signal(162),
+--   grant(163) => grant_signal(163),
+--   grant(164) => grant_signal(164),
+--   grant(165) => grant_signal(165),
+--   grant(166) => grant_signal(166),
+--   grant(167) => grant_signal(167),
+--   grant(168) => grant_signal(168),
+--   grant(169) => grant_signal(169),
+--   grant(170) => grant_signal(170),
+--   grant(171) => grant_signal(171),
+--   grant(172) => grant_signal(172),
+--   grant(173) => grant_signal(173),
+--   grant(174) => grant_signal(174),
+--   grant(175) => grant_signal(175),
+--   grant(176) => grant_signal(176),
+--   fifo_full =>fifo_in_full(11),
+--   priority_rotation =>  priority_rotation_signal(11),
+--   fifo_empty => fifo_in_empty(11),
+--   data_out =>crossbar_in_port(11),
+--   data_out_pulse =>crossbar_in_pulse(11),
+--   request(161) =>request_signal(161),
+--   request(162) =>request_signal(162),
+--   request(163) =>request_signal(163),
+--   request(164) =>request_signal(164),
+--   request(165) =>request_signal(165),
+--   request(166) =>request_signal(166),
+--   request(167) =>request_signal(167),
+--   request(168) =>request_signal(168),
+--   request(169) =>request_signal(169),
+--   request(170) =>request_signal(170),
+--   request(171) =>request_signal(171),
+--   request(172) =>request_signal(172),
+--   request(173) =>request_signal(173),
+--   request(174) =>request_signal(174),
+--   request(175) =>request_signal(175),
+--   request(176) =>request_signal(176)
+--);
+--
+--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(12),
+--   data_in_en => data_in_en(12),
+--   reset => reset,
+--   clk =>clk,
+--   grant(177) => grant_signal(177),
+--   grant(178) => grant_signal(178),
+--   grant(179) => grant_signal(179),
+--   grant(180) => grant_signal(180),
+--   grant(181) => grant_signal(181),
+--   grant(182) => grant_signal(182),
+--   grant(183) => grant_signal(183),
+--   grant(184) => grant_signal(184),
+--   grant(185) => grant_signal(185),
+--   grant(186) => grant_signal(186),
+--   grant(187) => grant_signal(187),
+--   grant(188) => grant_signal(188),
+--   grant(189) => grant_signal(189),
+--   grant(190) => grant_signal(190),
+--   grant(191) => grant_signal(191),
+--   grant(192) => grant_signal(192),
+--   fifo_full =>fifo_in_full(12),
+--   priority_rotation =>  priority_rotation_signal(12),
+--   fifo_empty => fifo_in_empty(12),
+--   data_out =>crossbar_in_port(12),
+--   data_out_pulse =>crossbar_in_pulse(12),
+--   request(177) =>request_signal(177),
+--   request(178) =>request_signal(178),
+--   request(179) =>request_signal(179),
+--   request(180) =>request_signal(180),
+--   request(181) =>request_signal(181),
+--   request(182) =>request_signal(182),
+--   request(183) =>request_signal(183),
+--   request(184) =>request_signal(184),
+--   request(185) =>request_signal(185),
+--   request(186) =>request_signal(186),
+--   request(187) =>request_signal(187),
+--   request(188) =>request_signal(188),
+--   request(189) =>request_signal(189),
+--   request(190) =>request_signal(190),
+--   request(191) =>request_signal(191),
+--   request(192) =>request_signal(192)
+--);
+--
+--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(13),
+--   data_in_en => data_in_en(13),
+--   reset => reset,
+--   clk =>clk,
+--   grant(193) => grant_signal(193),
+--   grant(194) => grant_signal(194),
+--   grant(195) => grant_signal(195),
+--   grant(196) => grant_signal(196),
+--   grant(197) => grant_signal(197),
+--   grant(198) => grant_signal(198),
+--   grant(199) => grant_signal(199),
+--   grant(200) => grant_signal(200),
+--   grant(201) => grant_signal(201),
+--   grant(202) => grant_signal(202),
+--   grant(203) => grant_signal(203),
+--   grant(204) => grant_signal(204),
+--   grant(205) => grant_signal(205),
+--   grant(206) => grant_signal(206),
+--   grant(207) => grant_signal(207),
+--   grant(208) => grant_signal(208),
+--   fifo_full =>fifo_in_full(13),
+--   priority_rotation =>  priority_rotation_signal(13),
+--   fifo_empty => fifo_in_empty(13),
+--   data_out =>crossbar_in_port13,
+--   data_out_pulse =>crossbar_in_pulse(13,
+--   request(193) =>request_signal(193),
+--   request(194) =>request_signal(194),
+--   request(195) =>request_signal(195),
+--   request(196) =>request_signal(196),
+--   request(197) =>request_signal(197),
+--   request(198) =>request_signal(198),
+--   request(199) =>request_signal(199),
+--   request(200) =>request_signal(200),
+--   request(201) =>request_signal(201),
+--   request(202) =>request_signal(202),
+--   request(203) =>request_signal(203),
+--   request(204) =>request_signal(204),
+--   request(205) =>request_signal(205),
+--   request(206) =>request_signal(206),
+--   request(207) =>request_signal(207),
+--   request(208) =>request_signal(208)
+--);
+--
+--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(14),
+--   data_in_en => data_in_en(14),
+--   reset => reset,
+--   clk =>clk,
+--   grant(209) => grant_signal(209),
+--   grant(210) => grant_signal(210),
+--   grant(211) => grant_signal(211),
+--   grant(212) => grant_signal(212),
+--   grant(213) => grant_signal(213),
+--   grant(214) => grant_signal(214),
+--   grant(215) => grant_signal(215),
+--   grant(216) => grant_signal(216),
+--   grant(217) => grant_signal(217),
+--   grant(218) => grant_signal(218),
+--   grant(219) => grant_signal(219),
+--   grant(220) => grant_signal(220),
+--   grant(221) => grant_signal(221),
+--   grant(222) => grant_signal(222),
+--   grant(223) => grant_signal(223),
+--   grant(224) => grant_signal(224),
+--   fifo_full =>fifo_in_full(14),
+--   priority_rotation =>  priority_rotation_signal(14),
+--   fifo_empty => fifo_in_empty(14),
+--   data_out =>crossbar_in_port(14),
+--   data_out_pulse =>crossbar_in_pulse(14),
+--   request(209) =>request_signal(209),
+--   request(210) =>request_signal(210),
+--   request(211) =>request_signal(211),
+--   request(212) =>request_signal(212),
+--   request(213) =>request_signal(213),
+--   request(214) =>request_signal(214),
+--   request(215) =>request_signal(215),
+--   request(216) =>request_signal(216),
+--   request(217) =>request_signal(217),
+--   request(218) =>request_signal(218),
+--   request(219) =>request_signal(219),
+--   request(220) =>request_signal(220),
+--   request(221) =>request_signal(221),
+--   request(222) =>request_signal(222),
+--   request(223) =>request_signal(223),
+--   request(224) =>request_signal(224)
+--);
+--
+--PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(15),
+--   data_in_en => data_in_en(15),
+--   reset => reset,
+--   clk =>clk,
+--   grant(225) => grant_signal(225),
+--   grant(226) => grant_signal(226),
+--   grant(227) => grant_signal(227),
+--   grant(228) => grant_signal(228),
+--   grant(229) => grant_signal(229),
+--   grant(230) => grant_signal(230),
+--   grant(231) => grant_signal(231),
+--   grant(232) => grant_signal(232),
+--   grant(233) => grant_signal(233),
+--   grant(234) => grant_signal(234),
+--   grant(235) => grant_signal(235),
+--   grant(236) => grant_signal(236),
+--   grant(237) => grant_signal(237),
+--   grant(238) => grant_signal(238),
+--   grant(239) => grant_signal(239),
+--   grant(240) => grant_signal(240),
+--   fifo_full =>fifo_in_full(15),
+--   priority_rotation =>  priority_rotation_signal(15),
+--   fifo_empty => fifo_in_empty(15),
+--   data_out =>crossbar_in_port(15),
+--   data_out_pulse =>crossbar_in_pulse(15),
+--   request(225) =>request_signal(225),
+--   request(226) =>request_signal(226),
+--   request(227) =>request_signal(227),
+--   request(228) =>request_signal(228),
+--   request(229) =>request_signal(229),
+--   request(230) =>request_signal(230),
+--   request(231) =>request_signal(231),
+--   request(232) =>request_signal(232),
+--   request(233) =>request_signal(233),
+--   request(234) =>request_signal(234),
+--   request(235) =>request_signal(235),
+--   request(236) =>request_signal(236),
+--   request(237) =>request_signal(237),
+--   request(238) =>request_signal(238),
+--   request(239) =>request_signal(239),
+--   request(240) =>request_signal(240)
+--);
+--
+--PORT16_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+--GENERIC MAP(number_of_ports =>16)
+--PORT MAP(
+--   data_in => Port_in(16),
+--   data_in_en => data_in_en(16),
+--   reset => reset,
+--   clk =>clk,
+--   grant(241) => grant_signal(241),
+--   grant(242) => grant_signal(242),
+--   grant(243) => grant_signal(243),
+--   grant(244) => grant_signal(244),
+--   grant(245) => grant_signal(245),
+--   grant(246) => grant_signal(246),
+--   grant(247) => grant_signal(247),
+--   grant(248) => grant_signal(248),
+--   grant(249) => grant_signal(249),
+--   grant(250) => grant_signal(250),
+--   grant(251) => grant_signal(251),
+--   grant(252) => grant_signal(252),
+--   grant(253) => grant_signal(253),
+--   grant(254) => grant_signal(254),
+--   grant(255) => grant_signal(255),
+--   grant(256) => grant_signal(256),
+--   fifo_full =>fifo_in_full(16),
+--   priority_rotation =>  priority_rotation_signal(16),
+--   fifo_empty => fifo_in_empty(16),
+--   data_out =>crossbar_in_port(16),
+--   data_out_pulse =>crossbar_in_pulse(16),
+--   request(241) =>request_signal(241),
+--   request(242) =>request_signal(242),
+--   request(243) =>request_signal(243),
+--   request(244) =>request_signal(244),
+--   request(245) =>request_signal(245),
+--   request(246) =>request_signal(246),
+--   request(247) =>request_signal(247),
+--   request(248) =>request_signal(248),
+--   request(249) =>request_signal(249),
+--   request(250) =>request_signal(250),
+--   request(251) =>request_signal(251),
+--   request(252) =>request_signal(252),
+--   request(253) =>request_signal(253),
+--   request(254) =>request_signal(254),
+--   request(255) =>request_signal(255),
+--   request(256) =>request_signal(256)
+--);
+--
+--end generate switch16x16;
+-- intstanciation et connexion des modules des ports de sorties fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+port_out_switch2x2 : if number_of_ports = 2 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+end generate port_out_switch2x2;
+
+
+-- switch 3 ports
+port_out_switch3x3 : if number_of_ports = 3 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+end generate port_out_switch3x3;
+
+
+-- switch 4 ports
+port_out_switch4x4 : if number_of_ports = 4 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+end generate port_out_switch4x4;
+
+
+-- switch 5 ports
+port_out_switch5x5 : if number_of_ports = 5 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+end generate port_out_switch5x5;
+
+
+-- switch 6 ports
+port_out_switch6x6 : if number_of_ports = 6 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+end generate port_out_switch6x6;
+
+
+-- switch 7 ports
+port_out_switch7x7 : if number_of_ports = 7 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+end generate port_out_switch7x7;
+
+
+-- switch 8 ports
+port_out_switch8x8 : if number_of_ports = 8 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+end generate port_out_switch8x8;
+
+
+-- switch 9 ports
+port_out_switch9x9 : if number_of_ports = 9 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(9),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(9),
+     data_out =>Port_out(9),
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+end generate port_out_switch9x9;
+
+
+-- switch 10 ports
+port_out_switch10x10 : if number_of_ports = 10 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(9),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(9),
+     data_out =>Port_out(9),
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(10),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(10),
+     data_out =>Port_out(10),
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+end generate port_out_switch10x10;
+
+
+-- switch 11 ports
+port_out_switch11x11 : if number_of_ports = 11 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(9),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(9),
+     data_out =>Port_out(9),
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(10),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(10),
+     data_out =>Port_out(10),
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(11),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(11),
+     data_out =>Port_out(11),
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+end generate port_out_switch11x11;
+
+
+-- switch 12 ports
+port_out_switch12x12 : if number_of_ports = 12 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(9),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(9),
+     data_out =>Port_out(9),
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(10),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(10),
+     data_out =>Port_out(10),
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(11),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(11),
+     data_out =>Port_out(11),
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(12),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(12),
+     data_out =>Port_out(12),
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+end generate port_out_switch12x12;
+
+
+-- switch 13 ports
+port_out_switch13x13 : if number_of_ports = 13 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(9),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(9),
+     data_out =>Port_out(9),
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(10),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(10),
+     data_out =>Port_out(10),
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(11),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(11),
+     data_out =>Port_out(11),
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(12),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(12),
+     data_out =>Port_out(12),
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(13),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(13),
+     data_out =>Port_out(13),
+     fifo_full =>fifo_out_full_signal(13),
+     data_avalaible => data_available(13),
+     rd_out_en => data_out_en(13)
+    );
+
+end generate port_out_switch13x13;
+
+
+-- switch 14 ports
+port_out_switch14x14 : if number_of_ports = 14 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(9),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(9),
+     data_out =>Port_out(9),
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(10),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(10),
+     data_out =>Port_out(10),
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(11),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(11),
+     data_out =>Port_out(11),
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(12),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(12),
+     data_out =>Port_out(12),
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(13),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(13),
+     data_out =>Port_out(13),
+     fifo_full =>fifo_out_full_signal(13),
+     data_avalaible => data_available(13),
+     rd_out_en => data_out_en(13)
+    );
+
+PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(14),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(14),
+     data_out =>Port_out(14),
+     fifo_full =>fifo_out_full_signal(14),
+     data_avalaible => data_available(14),
+     rd_out_en => data_out_en(14)
+    );
+
+end generate port_out_switch14x14;
+
+
+-- switch 15 ports
+port_out_switch15x15 : if number_of_ports = 15 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(1),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(1),
+     data_out =>Port_out(1),
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(2),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(2),
+     data_out =>Port_out(2),
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(3),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(3),
+     data_out =>Port_out(3),
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(4),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(4),
+     data_out =>Port_out(4),
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(5),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(5),
+     data_out =>Port_out(5),
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(6),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(6),
+     data_out =>Port_out(6),
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(7),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(7),
+     data_out =>Port_out(7),
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(8),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(8),
+     data_out =>Port_out(8),
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(9),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(9),
+     data_out =>Port_out(9),
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(10),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(10),
+     data_out =>Port_out(10),
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(11),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(11),
+     data_out =>Port_out(11),
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(12),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(12),
+     data_out =>Port_out(12),
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(13),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(13),
+     data_out =>Port_out(13),
+     fifo_full =>fifo_out_full_signal(13),
+     data_avalaible => data_available(13),
+     rd_out_en => data_out_en(13)
+    );
+
+PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(14),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(14),
+     data_out =>Port_out(14),
+     fifo_full =>fifo_out_full_signal(14),
+     data_avalaible => data_available(14),
+     rd_out_en => data_out_en(14)
+    );
+
+PORT15_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(15),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(15),
+     data_out =>Port_out(15),
+     fifo_full =>fifo_out_full_signal(15),
+     data_avalaible => data_available(15),
+     rd_out_en => data_out_en(15)
+    );
+
+end generate port_out_switch15x15;
+
+
+-- switch 16 ports
+port_out_switch16x16 : if number_of_ports = 16 generate
+port_out_switch_16x16:for i in 1 to number_of_ports generate
+  begin
+  PORTx16_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port(i),
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse(i),
+     data_out =>Port_out(i),
+     fifo_full =>fifo_out_full_signal(i),
+     data_avalaible => data_available(i),
+     rd_out_en => data_out_en(i)
+    );
+end generate port_out_switch_16x16;
+
+end generate port_out_switch16x16;
+
+-- intstanciation et connexion des crossbars du  switch en fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+crossbar_switch2x2 : if number_of_ports = 2 generate
+
+Switch_Crossbar2_2: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>2)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => "00000000",
+   Port4_in => "00000000",
+   Port5_in => "00000000",
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in =>'0' ,
+   Port4_pulse_in =>'0' ,
+   Port5_pulse_in =>'0' ,
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+   Ctrl => Grant_signal);
+end generate crossbar_switch2x2;
+
+
+-- switch 3 ports
+crossbar_switch3x3 : if number_of_ports = 3 generate
+
+Switch_Crossbar3_3: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>3)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => "00000000",
+   Port5_in => "00000000",
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in =>'0' ,
+   Port5_pulse_in =>'0' ,
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+   Ctrl => Grant_signal);
+end generate crossbar_switch3x3;
+
+
+-- switch 4 ports
+crossbar_switch4x4 : if number_of_ports = 4 generate
+
+Switch_Crossbar4_4: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>4)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => "00000000",
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in =>'0' ,
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+   Ctrl => Grant_signal);
+end generate crossbar_switch4x4;
+
+
+-- switch 5 ports
+crossbar_switch5x5 : if number_of_ports = 5 generate
+
+Switch_Crossbar5_5: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>5)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+   Ctrl => Grant_signal);
+end generate crossbar_switch5x5;
+
+
+-- switch 6 ports
+crossbar_switch6x6 : if number_of_ports = 6 generate
+
+Switch_Crossbar6_6: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>6)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+   Ctrl => Grant_signal);
+end generate crossbar_switch6x6;
+
+
+-- switch 7 ports
+crossbar_switch7x7 : if number_of_ports = 7 generate
+
+Switch_Crossbar7_7: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>7)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+   Ctrl => Grant_signal);
+end generate crossbar_switch7x7;
+
+
+-- switch 8 ports
+crossbar_switch8x8 : if number_of_ports = 8 generate
+
+Switch_Crossbar8_8: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>8)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+   Ctrl => Grant_signal);
+end generate crossbar_switch8x8;
+
+
+-- switch 9 ports
+crossbar_switch9x9 : if number_of_ports = 9 generate
+
+Switch_Crossbar9_9: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>9)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+   Ctrl => Grant_signal);
+end generate crossbar_switch9x9;
+
+
+-- switch 10 ports
+crossbar_switch10x10 : if number_of_ports = 10 generate
+
+Switch_Crossbar10_10: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>10)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => crossbar_in_port(10),
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in => crossbar_in_pulse(10),
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+   Port10_pulse_out => crossbar_out_pulse(10),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+  Port10_out => crossbar_out_port(10),
+   Ctrl => Grant_signal);
+end generate crossbar_switch10x10;
+
+
+-- switch 11 ports
+crossbar_switch11x11 : if number_of_ports = 11 generate
+
+Switch_Crossbar11_11: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>11)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => crossbar_in_port(10),
+   Port11_in => crossbar_in_port(11),
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in => crossbar_in_pulse(10),
+   Port11_pulse_in => crossbar_in_pulse(11),
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+   Port10_pulse_out => crossbar_out_pulse(10),
+   Port11_pulse_out => crossbar_out_pulse(11),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+  Port10_out => crossbar_out_port(10),
+  Port11_out => crossbar_out_port(11),
+   Ctrl => Grant_signal);
+end generate crossbar_switch11x11;
+
+
+-- switch 12 ports
+crossbar_switch12x12 : if number_of_ports = 12 generate
+
+Switch_Crossbar12_12: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>12)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => crossbar_in_port(10),
+   Port11_in => crossbar_in_port(11),
+   Port12_in => crossbar_in_port(12),
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in => crossbar_in_pulse(10),
+   Port11_pulse_in => crossbar_in_pulse(11),
+   Port12_pulse_in => crossbar_in_pulse(12),
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+   Port10_pulse_out => crossbar_out_pulse(10),
+   Port11_pulse_out => crossbar_out_pulse(11),
+   Port12_pulse_out => crossbar_out_pulse(12),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+  Port10_out => crossbar_out_port(10),
+  Port11_out => crossbar_out_port(11),
+  Port12_out => crossbar_out_port(12),
+   Ctrl => Grant_signal);
+end generate crossbar_switch12x12;
+
+
+-- switch 13 ports
+crossbar_switch13x13 : if number_of_ports = 13 generate
+
+Switch_Crossbar13_13: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>13)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => crossbar_in_port(10),
+   Port11_in => crossbar_in_port(11),
+   Port12_in => crossbar_in_port(12),
+   Port13_in => crossbar_in_port(13),
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in => crossbar_in_pulse(10),
+   Port11_pulse_in => crossbar_in_pulse(11),
+   Port12_pulse_in => crossbar_in_pulse(12),
+   Port13_pulse_in => crossbar_in_pulse(13),
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+   Port10_pulse_out => crossbar_out_pulse(10),
+   Port11_pulse_out => crossbar_out_pulse(11),
+   Port12_pulse_out => crossbar_out_pulse(12),
+   Port13_pulse_out => crossbar_out_pulse(13),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+  Port10_out => crossbar_out_port(10),
+  Port11_out => crossbar_out_port(11),
+  Port12_out => crossbar_out_port(12),
+  Port13_out => crossbar_out_port(13),
+   Ctrl => Grant_signal);
+end generate crossbar_switch13x13;
+
+
+-- switch 14 ports
+crossbar_switch14x14 : if number_of_ports = 14 generate
+
+Switch_Crossbar14_14: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>14)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => crossbar_in_port(10),
+   Port11_in => crossbar_in_port(11),
+   Port12_in => crossbar_in_port(12),
+   Port13_in => crossbar_in_port(13),
+   Port14_in => crossbar_in_port(14),
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in => crossbar_in_pulse(10),
+   Port11_pulse_in => crossbar_in_pulse(11),
+   Port12_pulse_in => crossbar_in_pulse(12),
+   Port13_pulse_in => crossbar_in_pulse(13),
+   Port14_pulse_in => crossbar_in_pulse(14),
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+   Port10_pulse_out => crossbar_out_pulse(10),
+   Port11_pulse_out => crossbar_out_pulse(11),
+   Port12_pulse_out => crossbar_out_pulse(12),
+   Port13_pulse_out => crossbar_out_pulse(13),
+   Port14_pulse_out => crossbar_out_pulse(14),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+  Port10_out => crossbar_out_port(10),
+  Port11_out => crossbar_out_port(11),
+  Port12_out => crossbar_out_port(12),
+  Port13_out => crossbar_out_port(13),
+  Port14_out => crossbar_out_port(14),
+   Ctrl => Grant_signal);
+end generate crossbar_switch14x14;
+
+
+-- switch 15 ports
+crossbar_switch15x15 : if number_of_ports = 15 generate
+
+Switch_Crossbar15_15: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>15)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => crossbar_in_port(10),
+   Port11_in => crossbar_in_port(11),
+   Port12_in => crossbar_in_port(12),
+   Port13_in => crossbar_in_port(13),
+   Port14_in => crossbar_in_port(14),
+   Port15_in => crossbar_in_port(15),
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in => crossbar_in_pulse(10),
+   Port11_pulse_in => crossbar_in_pulse(11),
+   Port12_pulse_in => crossbar_in_pulse(12),
+   Port13_pulse_in => crossbar_in_pulse(13),
+   Port14_pulse_in => crossbar_in_pulse(14),
+   Port15_pulse_in => crossbar_in_pulse(15),
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+   Port10_pulse_out => crossbar_out_pulse(10),
+   Port11_pulse_out => crossbar_out_pulse(11),
+   Port12_pulse_out => crossbar_out_pulse(12),
+   Port13_pulse_out => crossbar_out_pulse(13),
+   Port14_pulse_out => crossbar_out_pulse(14),
+   Port15_pulse_out => crossbar_out_pulse(15),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+  Port10_out => crossbar_out_port(10),
+  Port11_out => crossbar_out_port(11),
+  Port12_out => crossbar_out_port(12),
+  Port13_out => crossbar_out_port(13),
+  Port14_out => crossbar_out_port(14),
+  Port15_out => crossbar_out_port(15),
+   Ctrl => Grant_signal);
+end generate crossbar_switch15x15;
+
+
+-- switch 16 ports
+crossbar_switch16x16 : if number_of_ports = 16 generate
+
+Switch_Crossbar16_16: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>16)
+  PORT MAP(
+   Port1_in => crossbar_in_port(1),
+   Port2_in => crossbar_in_port(2),
+   Port3_in => crossbar_in_port(3),
+   Port4_in => crossbar_in_port(4),
+   Port5_in => crossbar_in_port(5),
+   Port6_in => crossbar_in_port(6),
+   Port7_in => crossbar_in_port(7),
+   Port8_in => crossbar_in_port(8),
+   Port9_in => crossbar_in_port(9),
+   Port10_in => crossbar_in_port(10),
+   Port11_in => crossbar_in_port(11),
+   Port12_in => crossbar_in_port(12),
+   Port13_in => crossbar_in_port(13),
+   Port14_in => crossbar_in_port(14),
+   Port15_in => crossbar_in_port(15),
+   Port16_in => crossbar_in_port(16),
+   Port1_pulse_in => crossbar_in_pulse(1),
+   Port2_pulse_in => crossbar_in_pulse(2),
+   Port3_pulse_in => crossbar_in_pulse(3),
+   Port4_pulse_in => crossbar_in_pulse(4),
+   Port5_pulse_in => crossbar_in_pulse(5),
+   Port6_pulse_in => crossbar_in_pulse(6),
+   Port7_pulse_in => crossbar_in_pulse(7),
+   Port8_pulse_in => crossbar_in_pulse(8),
+   Port9_pulse_in => crossbar_in_pulse(9),
+   Port10_pulse_in => crossbar_in_pulse(10),
+   Port11_pulse_in => crossbar_in_pulse(11),
+   Port12_pulse_in => crossbar_in_pulse(12),
+   Port13_pulse_in => crossbar_in_pulse(13),
+   Port14_pulse_in => crossbar_in_pulse(14),
+   Port15_pulse_in => crossbar_in_pulse(15),
+   Port16_pulse_in => crossbar_in_pulse(16),
+   Port1_pulse_out => crossbar_out_pulse(1),
+   Port2_pulse_out => crossbar_out_pulse(2),
+   Port3_pulse_out => crossbar_out_pulse(3),
+   Port4_pulse_out => crossbar_out_pulse(4),
+   Port5_pulse_out => crossbar_out_pulse(5),
+   Port6_pulse_out => crossbar_out_pulse(6),
+   Port7_pulse_out => crossbar_out_pulse(7),
+   Port8_pulse_out => crossbar_out_pulse(8),
+   Port9_pulse_out => crossbar_out_pulse(9),
+   Port10_pulse_out => crossbar_out_pulse(10),
+   Port11_pulse_out => crossbar_out_pulse(11),
+   Port12_pulse_out => crossbar_out_pulse(12),
+   Port13_pulse_out => crossbar_out_pulse(13),
+   Port14_pulse_out => crossbar_out_pulse(14),
+   Port15_pulse_out => crossbar_out_pulse(15),
+   Port16_pulse_out => crossbar_out_pulse(16),
+  Port1_out => crossbar_out_port(1),
+  Port2_out => crossbar_out_port(2),
+  Port3_out => crossbar_out_port(3),
+  Port4_out => crossbar_out_port(4),
+  Port5_out => crossbar_out_port(5),
+  Port6_out => crossbar_out_port(6),
+  Port7_out => crossbar_out_port(7),
+  Port8_out => crossbar_out_port(8),
+  Port9_out => crossbar_out_port(9),
+  Port10_out => crossbar_out_port(10),
+  Port11_out => crossbar_out_port(11),
+  Port12_out => crossbar_out_port(12),
+  Port13_out => crossbar_out_port(13),
+  Port14_out => crossbar_out_port(14),
+  Port15_out => crossbar_out_port(15),
+  Port16_out => crossbar_out_port(16),
+   Ctrl => Grant_signal);
+end generate crossbar_switch16x16;
+-- intstanciation et connexion du scheduler en fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+scheduler_switch2x2 : if number_of_ports = 2 generate
+
+Scheduler2_2: Scheduler 
+   GENERIC MAP(number_of_ports => 2 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch2x2;
+
+
+-- switch 3 ports
+scheduler_switch3x3 : if number_of_ports = 3 generate
+
+Scheduler3_3: Scheduler 
+   GENERIC MAP(number_of_ports => 3 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch3x3;
+
+
+-- switch 4 ports
+scheduler_switch4x4 : if number_of_ports = 4 generate
+
+Scheduler4_4: Scheduler 
+   GENERIC MAP(number_of_ports => 4 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch4x4;
+
+
+-- switch 5 ports
+scheduler_switch5x5 : if number_of_ports = 5 generate
+
+Scheduler5_5: Scheduler 
+   GENERIC MAP(number_of_ports => 5 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch5x5;
+
+
+-- switch 6 ports
+scheduler_switch6x6 : if number_of_ports = 6 generate
+
+Scheduler6_6: Scheduler 
+   GENERIC MAP(number_of_ports => 6 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch6x6;
+
+
+-- switch 7 ports
+scheduler_switch7x7 : if number_of_ports = 7 generate
+
+Scheduler7_7: Scheduler 
+   GENERIC MAP(number_of_ports => 7 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch7x7;
+
+
+-- switch 8 ports
+scheduler_switch8x8 : if number_of_ports = 8 generate
+
+Scheduler8_8: Scheduler 
+   GENERIC MAP(number_of_ports => 8 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch8x8;
+
+
+-- switch 9 ports
+scheduler_switch9x9 : if number_of_ports = 9 generate
+
+Scheduler9_9: Scheduler 
+   GENERIC MAP(number_of_ports => 9 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch9x9;
+
+
+-- switch 10 ports
+scheduler_switch10x10 : if number_of_ports = 10 generate
+
+Scheduler10_10: Scheduler 
+   GENERIC MAP(number_of_ports => 10 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch10x10;
+
+
+-- switch 11 ports
+scheduler_switch11x11 : if number_of_ports = 11 generate
+
+Scheduler11_11: Scheduler 
+   GENERIC MAP(number_of_ports => 11 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch11x11;
+
+
+-- switch 12 ports
+scheduler_switch12x12 : if number_of_ports = 12 generate
+
+Scheduler12_12: Scheduler 
+   GENERIC MAP(number_of_ports => 12 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch12x12;
+
+
+-- switch 13 ports
+scheduler_switch13x13 : if number_of_ports = 13 generate
+
+Scheduler13_13: Scheduler 
+   GENERIC MAP(number_of_ports => 13 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch13x13;
+
+
+-- switch 14 ports
+scheduler_switch14x14 : if number_of_ports = 14 generate
+
+Scheduler14_14: Scheduler 
+   GENERIC MAP(number_of_ports => 14 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch14x14;
+
+
+-- switch 15 ports
+scheduler_switch15x15 : if number_of_ports = 15 generate
+
+Scheduler15_15: Scheduler 
+   GENERIC MAP(number_of_ports => 15 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch15x15;
+
+
+-- switch 16 ports
+scheduler_switch16x16 : if number_of_ports = 16 generate
+
+Scheduler16_16: Scheduler 
+   GENERIC MAP(number_of_ports => 16 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch16x16;
+
+
+end Behavioral;
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GENERIQUE.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GENERIQUE.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GENERIQUE.vhd	(revision 20)
@@ -0,0 +1,8134 @@
+----------------------------------------------------------------------------------
+-- Company: ENSET 2011
+-- Engineer: GAMOM NGOUNOU ET KIEGAING EMMANUEL ET TAGNE FRANKLIN EN 5
+-- 
+-- Create Date:    03:40:47 06/18/2011 
+-- Design Name: 
+-- Module Name:    SWITCH_GENERIQUE - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+-- fichier principal du switch générique; en fonction du parametre generique le 
+-- les directive de generation conditionnelle permettent de ne générer et synthétiser uniquement  la logique 
+-- nécessaire à l'implémentation  du switch de la dimension voulue
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity SWITCH_GENERIQUE is
+     generic(number_of_ports : positive := 8);
+     port(
+	        -- ports d'entree
+           Port1_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+           Port2_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+           Port3_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+           Port4_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+			  Port5_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+           Port6_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+           Port7_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+           Port8_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+			  Port9_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+           Port10_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port13_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			 
+			  -- port de sortie
+			  Port1_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port2_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port3_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port4_out : out  STD_LOGIC_VECTOR (7 downto 0);
+			  Port5_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port6_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port7_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port8_out : out  STD_LOGIC_VECTOR (7 downto 0);
+			  Port9_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port10_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_out : out  STD_LOGIC_VECTOR (7 downto 0);
+			  Port13_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_out : out  STD_LOGIC_VECTOR (7 downto 0);
+			  -- signaux de controle
+			  data_in_en : in std_logic_vector(number_of_ports downto 1);
+			  data_out_en : in std_logic_vector(number_of_ports downto 1);
+			  fifo_in_full : out std_logic_vector(number_of_ports downto 1);
+			  fifo_in_empty : out std_logic_vector(number_of_ports downto 1);
+			  data_available : out std_logic_vector(number_of_ports downto 1);
+			  clk       : in   STD_LOGIC;
+			  reset     : in   STD_LOGIC);
+end SWITCH_GENERIQUE;
+
+architecture Behavioral of SWITCH_GENERIQUE is
+-- declaration des modules du switch generique
+-- le module de gestion des ports d'entrée
+
+COMPONENT INPUT_PORT_MODULE
+  generic(number_of_ports : positive := 4);
+    Port ( data_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           data_in_en : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+			  clk   : in  STD_LOGIC;
+			  request : out  STD_LOGIC_VECTOR (number_of_ports downto 1);
+           grant : in  STD_LOGIC_VECTOR (number_of_ports  downto 1);			  
+           fifo_full : out  STD_LOGIC;
+			  fifo_empty : out  STD_LOGIC;
+			  priority_rotation : out std_logic;
+           data_out : out  STD_LOGIC_VECTOR (7 downto 0);
+			  data_out_pulse : out std_logic);
+END COMPONENT;
+
+-- le module des ports de sortie
+
+COMPONENT OUTPUT_PORT_MODULE
+	PORT(
+		data_in : IN std_logic_vector(7 downto 0);
+		reset : IN std_logic;
+		clk : IN std_logic;
+		wr_en : IN std_logic;
+		rd_out_en : IN std_logic;          
+		data_out : OUT std_logic_vector(7 downto 0);
+		fifo_full : OUT std_logic;
+		data_avalaible : OUT std_logic
+		);
+END COMPONENT;
+	
+-- le module du crossbar
+COMPONENT Crossbar
+ generic
+	      (
+			  number_of_crossbar_ports: positive := 4
+			);
+    Port ( Port1_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port2_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port3_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port4_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port5_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port6_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port7_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port8_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port9_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port10_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port13_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  
+			  Port1_pulse_in : in std_logic;
+			  Port2_pulse_in : in std_logic;
+			  Port3_pulse_in : in std_logic;
+			  Port4_pulse_in : in std_logic;
+			  Port5_pulse_in : in std_logic;
+			  Port6_pulse_in : in std_logic;
+			  Port7_pulse_in : in std_logic;
+			  Port8_pulse_in : in std_logic;
+			  Port9_pulse_in : in std_logic;
+			  Port10_pulse_in : in std_logic;
+			  Port11_pulse_in : in std_logic;
+			  Port12_pulse_in : in std_logic;
+			  Port13_pulse_in : in std_logic;
+			  Port14_pulse_in : in std_logic;
+			  Port15_pulse_in : in std_logic;
+			  Port16_pulse_in : in std_logic;
+			  
+			  Port1_pulse_out : out std_logic;
+			  Port2_pulse_out : out std_logic;
+			  Port3_pulse_out : out std_logic;
+			  Port4_pulse_out : out std_logic;
+			  Port5_pulse_out : out std_logic;
+			  Port6_pulse_out : out std_logic;
+			  Port7_pulse_out : out std_logic;
+			  Port8_pulse_out : out std_logic;
+			  Port9_pulse_out : out std_logic;
+			  Port10_pulse_out : out std_logic;
+			  Port11_pulse_out : out std_logic;
+			  Port12_pulse_out : out std_logic;
+			  Port13_pulse_out : out std_logic;
+			  Port14_pulse_out : out std_logic;
+			  Port15_pulse_out : out std_logic;
+			  Port16_pulse_out : out std_logic;
+			  
+			  Port1_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port2_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port3_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port4_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port5_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port6_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port7_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port8_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port9_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port10_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port13_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  
+           Ctrl : in  STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1)
+       ); 
+ END COMPONENT;
+
+-- déclaration du  scheduler
+COMPONENT Scheduler
+	generic(number_of_ports : positive := 4);
+    Port ( Request : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
+			  Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1);
+           clk : in  STD_LOGIC;
+	        reset : in  STD_LOGIC;
+			  priority_rotation : in  STD_LOGIC_VECTOR (number_of_ports downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1));
+END COMPONENT;
+
+--declaration des signaux de connection entre les modules du switch
+--type port_connection_type is array(16 downto 1) of std_logic_vector(7 downto 1);
+--signal crossbar_port_in_connetion : port_connection_type;
+--signal crossbar_port_out_connetion :port_connection_type;
+--signal request_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
+--signal grant_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
+--signal priority_rotation_connection : std_logic_vector(number_of_ports downto 1);
+--signal fifo_out_full_connection : std_logic_vector(1 to number_of_ports);
+--signal crossbar_in_pulse_connection : std_logic_vector(number_of_ports downto 1);
+--signal crossbar_out_pulse_connection : std_logic_vector(number_of_ports downto 1);
+
+Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
+Signal grant_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
+Signal priority_rotation_signal : STD_LOGIC_VECTOR(number_of_ports downto 1);
+signal fifo_out_full_signal : std_logic_vector(number_of_ports downto 1);
+signal crossbar_in_port1 : std_logic_vector(7 downto 0);
+signal crossbar_in_port2 : std_logic_vector(7 downto 0);
+signal crossbar_in_port3 : std_logic_vector(7 downto 0);
+signal crossbar_in_port4 : std_logic_vector(7 downto 0);
+signal crossbar_in_port5 : std_logic_vector(7 downto 0);
+signal crossbar_in_port6 : std_logic_vector(7 downto 0);
+signal crossbar_in_port7 : std_logic_vector(7 downto 0);
+signal crossbar_in_port8 : std_logic_vector(7 downto 0);
+signal crossbar_in_port9 : std_logic_vector(7 downto 0);
+signal crossbar_in_port10 : std_logic_vector(7 downto 0);
+signal crossbar_in_port11 : std_logic_vector(7 downto 0);
+signal crossbar_in_port12 : std_logic_vector(7 downto 0);
+signal crossbar_in_port13 : std_logic_vector(7 downto 0);
+signal crossbar_in_port14 : std_logic_vector(7 downto 0);
+signal crossbar_in_port15 : std_logic_vector(7 downto 0);
+signal crossbar_in_port16: std_logic_vector(7 downto 0);
+
+signal crossbar_out_port1 : std_logic_vector(7 downto 0);
+signal crossbar_out_port2 : std_logic_vector(7 downto 0);
+signal crossbar_out_port3 : std_logic_vector(7 downto 0);
+signal crossbar_out_port4 : std_logic_vector(7 downto 0);
+signal crossbar_out_port5 : std_logic_vector(7 downto 0);
+signal crossbar_out_port6 : std_logic_vector(7 downto 0);
+signal crossbar_out_port7 : std_logic_vector(7 downto 0);
+signal crossbar_out_port8 : std_logic_vector(7 downto 0);
+signal crossbar_out_port9 : std_logic_vector(7 downto 0);
+signal crossbar_out_port10 : std_logic_vector(7 downto 0);
+signal crossbar_out_port11 : std_logic_vector(7 downto 0);
+signal crossbar_out_port12 : std_logic_vector(7 downto 0);
+signal crossbar_out_port13 : std_logic_vector(7 downto 0);
+signal crossbar_out_port14 : std_logic_vector(7 downto 0);
+signal crossbar_out_port15 : std_logic_vector(7 downto 0);
+signal crossbar_out_port16 : std_logic_vector(7 downto 0);
+
+signal crossbar_in_pulse1 : std_logic;
+signal crossbar_in_pulse2 : std_logic;
+signal crossbar_in_pulse3 : std_logic;
+signal crossbar_in_pulse4 : std_logic;
+signal crossbar_in_pulse5 : std_logic;
+signal crossbar_in_pulse6 : std_logic;
+signal crossbar_in_pulse7 : std_logic;
+signal crossbar_in_pulse8 : std_logic;
+signal crossbar_in_pulse9 : std_logic;
+signal crossbar_in_pulse10 : std_logic;
+signal crossbar_in_pulse11 : std_logic;
+signal crossbar_in_pulse12 : std_logic;
+signal crossbar_in_pulse13 : std_logic;
+signal crossbar_in_pulse14 : std_logic;
+signal crossbar_in_pulse15 : std_logic;
+signal crossbar_in_pulse16 : std_logic;
+
+
+signal crossbar_out_pulse1 : std_logic;
+signal crossbar_out_pulse2 : std_logic;
+signal crossbar_out_pulse3 : std_logic;
+signal crossbar_out_pulse4 : std_logic;
+signal crossbar_out_pulse5 : std_logic;
+signal crossbar_out_pulse6 : std_logic;
+signal crossbar_out_pulse7 : std_logic;
+signal crossbar_out_pulse8 : std_logic;
+signal crossbar_out_pulse9 : std_logic;
+signal crossbar_out_pulse10 : std_logic;
+signal crossbar_out_pulse11 : std_logic;
+signal crossbar_out_pulse12 : std_logic;
+signal crossbar_out_pulse13 : std_logic;
+signal crossbar_out_pulse14 : std_logic;
+signal crossbar_out_pulse15 : std_logic;
+signal crossbar_out_pulse16 : std_logic;
+
+
+begin
+-- intstanciation et connexion des modules du switch en fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+switch2x2 : if number_of_ports = 2 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>2)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>2)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4)
+);
+
+end generate switch2x2;
+
+
+-- switch 3 ports
+switch3x3 : if number_of_ports = 3 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>3)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>3)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>3)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9)
+);
+
+end generate switch3x3;
+
+
+-- switch 4 ports
+switch4x4 : if number_of_ports = 4 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>4)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>4)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>4)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>4)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16)
+);
+
+end generate switch4x4;
+
+
+-- switch 5 ports
+switch5x5 : if number_of_ports = 5 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>5)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>5)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>5)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>5)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>5)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25)
+);
+
+end generate switch5x5;
+
+
+-- switch 6 ports
+switch6x6 : if number_of_ports = 6 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>6)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>6)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>6)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>6)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>6)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>6)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36)
+);
+
+end generate switch6x6;
+
+
+-- switch 7 ports
+switch7x7 : if number_of_ports = 7 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>7)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>7)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>7)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>7)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>7)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30),
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>7)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(36) => grant_signal(36),
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(36) =>request_signal(36),
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>7)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   grant(49) => grant_signal(49),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45),
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48),
+   request(49) =>request_signal(49)
+);
+
+end generate switch7x7;
+
+
+-- switch 8 ports
+switch8x8 : if number_of_ports = 8 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(9),
+   grant(2) => grant_signal(10),
+   grant(3) => grant_signal(11),
+   grant(4) => grant_signal(12),
+   grant(5) => grant_signal(13),
+   grant(6) => grant_signal(14),
+   grant(7) => grant_signal(15),
+   grant(8) => grant_signal(16),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(1) =>request_signal(9),
+   request(2) =>request_signal(10),
+   request(3) =>request_signal(11),
+   request(4) =>request_signal(12),
+   request(5) =>request_signal(13),
+   request(6) =>request_signal(14),
+   request(7) =>request_signal(15),
+   request(8) =>request_signal(16)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(17),
+   grant(2) => grant_signal(18),
+   grant(3) => grant_signal(19),
+   grant(4) => grant_signal(20),
+   grant(5) => grant_signal(21),
+   grant(6) => grant_signal(22),
+   grant(7) => grant_signal(23),
+   grant(8) => grant_signal(24),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(1) =>request_signal(17),
+   request(2) =>request_signal(18),
+   request(3) =>request_signal(19),
+   request(4) =>request_signal(20),
+   request(5) =>request_signal(21),
+   request(6) =>request_signal(22),
+   request(7) =>request_signal(23),
+   request(8) =>request_signal(24)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(25),
+   grant(2) => grant_signal(26),
+   grant(3) => grant_signal(27),
+   grant(4) => grant_signal(28),
+   grant(5) => grant_signal(29),
+   grant(6) => grant_signal(30),
+   grant(7) => grant_signal(31),
+   grant(8) => grant_signal(32),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(1) =>request_signal(25),
+   request(2) =>request_signal(26),
+   request(3) =>request_signal(27),
+   request(4) =>request_signal(28),
+   request(5) =>request_signal(29),
+   request(6) =>request_signal(30),
+   request(7) =>request_signal(31),
+   request(8) =>request_signal(32)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(33),
+   grant(2) => grant_signal(34),
+   grant(3) => grant_signal(35),
+   grant(4) => grant_signal(36),
+   grant(5) => grant_signal(37),
+   grant(6) => grant_signal(38),
+   grant(7) => grant_signal(39),
+   grant(8) => grant_signal(40),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(1) =>request_signal(33),
+   request(2) =>request_signal(34),
+   request(3) =>request_signal(35),
+   request(4) =>request_signal(36),
+   request(5) =>request_signal(37),
+   request(6) =>request_signal(38),
+   request(7) =>request_signal(39),
+   request(8) =>request_signal(40)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(41),
+   grant(2) => grant_signal(42),
+   grant(3) => grant_signal(43),
+   grant(4) => grant_signal(44),
+   grant(5) => grant_signal(45),
+   grant(6) => grant_signal(46),
+   grant(7) => grant_signal(47),
+   grant(8) => grant_signal(48),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(1) =>request_signal(41),
+   request(2) =>request_signal(42),
+   request(3) =>request_signal(43),
+   request(4) =>request_signal(44),
+   request(5) =>request_signal(45),
+   request(6) =>request_signal(46),
+   request(7) =>request_signal(47),
+   request(8) =>request_signal(48)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(49),
+   grant(2) => grant_signal(50),
+   grant(3) => grant_signal(51),
+   grant(4) => grant_signal(52),
+   grant(5) => grant_signal(53),
+   grant(6) => grant_signal(54),
+   grant(7) => grant_signal(55),
+   grant(8) => grant_signal(56),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(1) =>request_signal(49),
+   request(2) =>request_signal(50),
+   request(3) =>request_signal(51),
+   request(4) =>request_signal(52),
+   request(5) =>request_signal(53),
+   request(6) =>request_signal(54),
+   request(7) =>request_signal(55),
+   request(8) =>request_signal(56)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(57),
+   grant(2) => grant_signal(58),
+   grant(3) => grant_signal(59),
+   grant(4) => grant_signal(60),
+   grant(5) => grant_signal(61),
+   grant(6) => grant_signal(62),
+   grant(7) => grant_signal(63),
+   grant(8) => grant_signal(64),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(1) =>request_signal(57),
+   request(2) =>request_signal(58),
+   request(3) =>request_signal(59),
+   request(4) =>request_signal(60),
+   request(5) =>request_signal(61),
+   request(6) =>request_signal(62),
+   request(7) =>request_signal(63),
+   request(8) =>request_signal(64)
+);
+
+end generate switch8x8;
+
+
+-- switch 9 ports
+switch9x9 : if number_of_ports = 9 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30),
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42),
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48),
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50),
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52),
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(55) => grant_signal(55),
+   grant(56) => grant_signal(56),
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(55) =>request_signal(55),
+   request(56) =>request_signal(56),
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60),
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(64) => grant_signal(64),
+   grant(65) => grant_signal(65),
+   grant(66) => grant_signal(66),
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(64) =>request_signal(64),
+   request(65) =>request_signal(65),
+   request(66) =>request_signal(66),
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70),
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   grant(78) => grant_signal(78),
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   grant(81) => grant_signal(81),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75),
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77),
+   request(78) =>request_signal(78),
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80),
+   request(81) =>request_signal(81)
+);
+
+end generate switch9x9;
+
+
+-- switch 10 ports
+switch10x10 : if number_of_ports = 10 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36),
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42),
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45),
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48),
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   grant(55) => grant_signal(55),
+   grant(56) => grant_signal(56),
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52),
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54),
+   request(55) =>request_signal(55),
+   request(56) =>request_signal(56),
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   grant(64) => grant_signal(64),
+   grant(65) => grant_signal(65),
+   grant(66) => grant_signal(66),
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63),
+   request(64) =>request_signal(64),
+   request(65) =>request_signal(65),
+   request(66) =>request_signal(66),
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   grant(78) => grant_signal(78),
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72),
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75),
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77),
+   request(78) =>request_signal(78),
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(81) => grant_signal(81),
+   grant(82) => grant_signal(82),
+   grant(83) => grant_signal(83),
+   grant(84) => grant_signal(84),
+   grant(85) => grant_signal(85),
+   grant(86) => grant_signal(86),
+   grant(87) => grant_signal(87),
+   grant(88) => grant_signal(88),
+   grant(89) => grant_signal(89),
+   grant(90) => grant_signal(90),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(81) =>request_signal(81),
+   request(82) =>request_signal(82),
+   request(83) =>request_signal(83),
+   request(84) =>request_signal(84),
+   request(85) =>request_signal(85),
+   request(86) =>request_signal(86),
+   request(87) =>request_signal(87),
+   request(88) =>request_signal(88),
+   request(89) =>request_signal(89),
+   request(90) =>request_signal(90)
+);
+
+PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port10_in,
+   data_in_en => data_in_en(10),
+   reset => reset,
+   clk =>clk,
+   grant(91) => grant_signal(91),
+   grant(92) => grant_signal(92),
+   grant(93) => grant_signal(93),
+   grant(94) => grant_signal(94),
+   grant(95) => grant_signal(95),
+   grant(96) => grant_signal(96),
+   grant(97) => grant_signal(97),
+   grant(98) => grant_signal(98),
+   grant(99) => grant_signal(99),
+   grant(100) => grant_signal(100),
+   fifo_full =>fifo_in_full(10),
+   priority_rotation =>  priority_rotation_signal(10),
+   fifo_empty => fifo_in_empty(10),
+   data_out =>crossbar_in_port10,
+   data_out_pulse =>crossbar_in_pulse10,
+   request(91) =>request_signal(91),
+   request(92) =>request_signal(92),
+   request(93) =>request_signal(93),
+   request(94) =>request_signal(94),
+   request(95) =>request_signal(95),
+   request(96) =>request_signal(96),
+   request(97) =>request_signal(97),
+   request(98) =>request_signal(98),
+   request(99) =>request_signal(99),
+   request(100) =>request_signal(100)
+);
+
+end generate switch10x10;
+
+
+-- switch 11 ports
+switch11x11 : if number_of_ports = 11 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30),
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36),
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42),
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(45) => grant_signal(45),
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   grant(55) => grant_signal(55),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(45) =>request_signal(45),
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48),
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50),
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52),
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54),
+   request(55) =>request_signal(55)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(56) => grant_signal(56),
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   grant(64) => grant_signal(64),
+   grant(65) => grant_signal(65),
+   grant(66) => grant_signal(66),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(56) =>request_signal(56),
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60),
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63),
+   request(64) =>request_signal(64),
+   request(65) =>request_signal(65),
+   request(66) =>request_signal(66)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70),
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72),
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75),
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(78) => grant_signal(78),
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   grant(81) => grant_signal(81),
+   grant(82) => grant_signal(82),
+   grant(83) => grant_signal(83),
+   grant(84) => grant_signal(84),
+   grant(85) => grant_signal(85),
+   grant(86) => grant_signal(86),
+   grant(87) => grant_signal(87),
+   grant(88) => grant_signal(88),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(78) =>request_signal(78),
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80),
+   request(81) =>request_signal(81),
+   request(82) =>request_signal(82),
+   request(83) =>request_signal(83),
+   request(84) =>request_signal(84),
+   request(85) =>request_signal(85),
+   request(86) =>request_signal(86),
+   request(87) =>request_signal(87),
+   request(88) =>request_signal(88)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(89) => grant_signal(89),
+   grant(90) => grant_signal(90),
+   grant(91) => grant_signal(91),
+   grant(92) => grant_signal(92),
+   grant(93) => grant_signal(93),
+   grant(94) => grant_signal(94),
+   grant(95) => grant_signal(95),
+   grant(96) => grant_signal(96),
+   grant(97) => grant_signal(97),
+   grant(98) => grant_signal(98),
+   grant(99) => grant_signal(99),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(89) =>request_signal(89),
+   request(90) =>request_signal(90),
+   request(91) =>request_signal(91),
+   request(92) =>request_signal(92),
+   request(93) =>request_signal(93),
+   request(94) =>request_signal(94),
+   request(95) =>request_signal(95),
+   request(96) =>request_signal(96),
+   request(97) =>request_signal(97),
+   request(98) =>request_signal(98),
+   request(99) =>request_signal(99)
+);
+
+PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port10_in,
+   data_in_en => data_in_en(10),
+   reset => reset,
+   clk =>clk,
+   grant(100) => grant_signal(100),
+   grant(101) => grant_signal(101),
+   grant(102) => grant_signal(102),
+   grant(103) => grant_signal(103),
+   grant(104) => grant_signal(104),
+   grant(105) => grant_signal(105),
+   grant(106) => grant_signal(106),
+   grant(107) => grant_signal(107),
+   grant(108) => grant_signal(108),
+   grant(109) => grant_signal(109),
+   grant(110) => grant_signal(110),
+   fifo_full =>fifo_in_full(10),
+   priority_rotation =>  priority_rotation_signal(10),
+   fifo_empty => fifo_in_empty(10),
+   data_out =>crossbar_in_port10,
+   data_out_pulse =>crossbar_in_pulse10,
+   request(100) =>request_signal(100),
+   request(101) =>request_signal(101),
+   request(102) =>request_signal(102),
+   request(103) =>request_signal(103),
+   request(104) =>request_signal(104),
+   request(105) =>request_signal(105),
+   request(106) =>request_signal(106),
+   request(107) =>request_signal(107),
+   request(108) =>request_signal(108),
+   request(109) =>request_signal(109),
+   request(110) =>request_signal(110)
+);
+
+PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port11_in,
+   data_in_en => data_in_en(11),
+   reset => reset,
+   clk =>clk,
+   grant(111) => grant_signal(111),
+   grant(112) => grant_signal(112),
+   grant(113) => grant_signal(113),
+   grant(114) => grant_signal(114),
+   grant(115) => grant_signal(115),
+   grant(116) => grant_signal(116),
+   grant(117) => grant_signal(117),
+   grant(118) => grant_signal(118),
+   grant(119) => grant_signal(119),
+   grant(120) => grant_signal(120),
+   grant(121) => grant_signal(121),
+   fifo_full =>fifo_in_full(11),
+   priority_rotation =>  priority_rotation_signal(11),
+   fifo_empty => fifo_in_empty(11),
+   data_out =>crossbar_in_port11,
+   data_out_pulse =>crossbar_in_pulse11,
+   request(111) =>request_signal(111),
+   request(112) =>request_signal(112),
+   request(113) =>request_signal(113),
+   request(114) =>request_signal(114),
+   request(115) =>request_signal(115),
+   request(116) =>request_signal(116),
+   request(117) =>request_signal(117),
+   request(118) =>request_signal(118),
+   request(119) =>request_signal(119),
+   request(120) =>request_signal(120),
+   request(121) =>request_signal(121)
+);
+
+end generate switch11x11;
+
+
+-- switch 12 ports
+switch12x12 : if number_of_ports = 12 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30),
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42),
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45),
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   grant(55) => grant_signal(55),
+   grant(56) => grant_signal(56),
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50),
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52),
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54),
+   request(55) =>request_signal(55),
+   request(56) =>request_signal(56),
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   grant(64) => grant_signal(64),
+   grant(65) => grant_signal(65),
+   grant(66) => grant_signal(66),
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63),
+   request(64) =>request_signal(64),
+   request(65) =>request_signal(65),
+   request(66) =>request_signal(66),
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70),
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   grant(78) => grant_signal(78),
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   grant(81) => grant_signal(81),
+   grant(82) => grant_signal(82),
+   grant(83) => grant_signal(83),
+   grant(84) => grant_signal(84),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75),
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77),
+   request(78) =>request_signal(78),
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80),
+   request(81) =>request_signal(81),
+   request(82) =>request_signal(82),
+   request(83) =>request_signal(83),
+   request(84) =>request_signal(84)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(85) => grant_signal(85),
+   grant(86) => grant_signal(86),
+   grant(87) => grant_signal(87),
+   grant(88) => grant_signal(88),
+   grant(89) => grant_signal(89),
+   grant(90) => grant_signal(90),
+   grant(91) => grant_signal(91),
+   grant(92) => grant_signal(92),
+   grant(93) => grant_signal(93),
+   grant(94) => grant_signal(94),
+   grant(95) => grant_signal(95),
+   grant(96) => grant_signal(96),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(85) =>request_signal(85),
+   request(86) =>request_signal(86),
+   request(87) =>request_signal(87),
+   request(88) =>request_signal(88),
+   request(89) =>request_signal(89),
+   request(90) =>request_signal(90),
+   request(91) =>request_signal(91),
+   request(92) =>request_signal(92),
+   request(93) =>request_signal(93),
+   request(94) =>request_signal(94),
+   request(95) =>request_signal(95),
+   request(96) =>request_signal(96)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(97) => grant_signal(97),
+   grant(98) => grant_signal(98),
+   grant(99) => grant_signal(99),
+   grant(100) => grant_signal(100),
+   grant(101) => grant_signal(101),
+   grant(102) => grant_signal(102),
+   grant(103) => grant_signal(103),
+   grant(104) => grant_signal(104),
+   grant(105) => grant_signal(105),
+   grant(106) => grant_signal(106),
+   grant(107) => grant_signal(107),
+   grant(108) => grant_signal(108),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(97) =>request_signal(97),
+   request(98) =>request_signal(98),
+   request(99) =>request_signal(99),
+   request(100) =>request_signal(100),
+   request(101) =>request_signal(101),
+   request(102) =>request_signal(102),
+   request(103) =>request_signal(103),
+   request(104) =>request_signal(104),
+   request(105) =>request_signal(105),
+   request(106) =>request_signal(106),
+   request(107) =>request_signal(107),
+   request(108) =>request_signal(108)
+);
+
+PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port10_in,
+   data_in_en => data_in_en(10),
+   reset => reset,
+   clk =>clk,
+   grant(109) => grant_signal(109),
+   grant(110) => grant_signal(110),
+   grant(111) => grant_signal(111),
+   grant(112) => grant_signal(112),
+   grant(113) => grant_signal(113),
+   grant(114) => grant_signal(114),
+   grant(115) => grant_signal(115),
+   grant(116) => grant_signal(116),
+   grant(117) => grant_signal(117),
+   grant(118) => grant_signal(118),
+   grant(119) => grant_signal(119),
+   grant(120) => grant_signal(120),
+   fifo_full =>fifo_in_full(10),
+   priority_rotation =>  priority_rotation_signal(10),
+   fifo_empty => fifo_in_empty(10),
+   data_out =>crossbar_in_port10,
+   data_out_pulse =>crossbar_in_pulse10,
+   request(109) =>request_signal(109),
+   request(110) =>request_signal(110),
+   request(111) =>request_signal(111),
+   request(112) =>request_signal(112),
+   request(113) =>request_signal(113),
+   request(114) =>request_signal(114),
+   request(115) =>request_signal(115),
+   request(116) =>request_signal(116),
+   request(117) =>request_signal(117),
+   request(118) =>request_signal(118),
+   request(119) =>request_signal(119),
+   request(120) =>request_signal(120)
+);
+
+PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port11_in,
+   data_in_en => data_in_en(11),
+   reset => reset,
+   clk =>clk,
+   grant(121) => grant_signal(121),
+   grant(122) => grant_signal(122),
+   grant(123) => grant_signal(123),
+   grant(124) => grant_signal(124),
+   grant(125) => grant_signal(125),
+   grant(126) => grant_signal(126),
+   grant(127) => grant_signal(127),
+   grant(128) => grant_signal(128),
+   grant(129) => grant_signal(129),
+   grant(130) => grant_signal(130),
+   grant(131) => grant_signal(131),
+   grant(132) => grant_signal(132),
+   fifo_full =>fifo_in_full(11),
+   priority_rotation =>  priority_rotation_signal(11),
+   fifo_empty => fifo_in_empty(11),
+   data_out =>crossbar_in_port11,
+   data_out_pulse =>crossbar_in_pulse11,
+   request(121) =>request_signal(121),
+   request(122) =>request_signal(122),
+   request(123) =>request_signal(123),
+   request(124) =>request_signal(124),
+   request(125) =>request_signal(125),
+   request(126) =>request_signal(126),
+   request(127) =>request_signal(127),
+   request(128) =>request_signal(128),
+   request(129) =>request_signal(129),
+   request(130) =>request_signal(130),
+   request(131) =>request_signal(131),
+   request(132) =>request_signal(132)
+);
+
+PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port12_in,
+   data_in_en => data_in_en(12),
+   reset => reset,
+   clk =>clk,
+   grant(133) => grant_signal(133),
+   grant(134) => grant_signal(134),
+   grant(135) => grant_signal(135),
+   grant(136) => grant_signal(136),
+   grant(137) => grant_signal(137),
+   grant(138) => grant_signal(138),
+   grant(139) => grant_signal(139),
+   grant(140) => grant_signal(140),
+   grant(141) => grant_signal(141),
+   grant(142) => grant_signal(142),
+   grant(143) => grant_signal(143),
+   grant(144) => grant_signal(144),
+   fifo_full =>fifo_in_full(12),
+   priority_rotation =>  priority_rotation_signal(12),
+   fifo_empty => fifo_in_empty(12),
+   data_out =>crossbar_in_port12,
+   data_out_pulse =>crossbar_in_pulse12,
+   request(133) =>request_signal(133),
+   request(134) =>request_signal(134),
+   request(135) =>request_signal(135),
+   request(136) =>request_signal(136),
+   request(137) =>request_signal(137),
+   request(138) =>request_signal(138),
+   request(139) =>request_signal(139),
+   request(140) =>request_signal(140),
+   request(141) =>request_signal(141),
+   request(142) =>request_signal(142),
+   request(143) =>request_signal(143),
+   request(144) =>request_signal(144)
+);
+
+end generate switch12x12;
+
+
+-- switch 13 ports
+switch13x13 : if number_of_ports = 13 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30),
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36),
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42),
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45),
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48),
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50),
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   grant(55) => grant_signal(55),
+   grant(56) => grant_signal(56),
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   grant(64) => grant_signal(64),
+   grant(65) => grant_signal(65),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54),
+   request(55) =>request_signal(55),
+   request(56) =>request_signal(56),
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60),
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63),
+   request(64) =>request_signal(64),
+   request(65) =>request_signal(65)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(66) => grant_signal(66),
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   grant(78) => grant_signal(78),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(66) =>request_signal(66),
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70),
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72),
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75),
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77),
+   request(78) =>request_signal(78)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   grant(81) => grant_signal(81),
+   grant(82) => grant_signal(82),
+   grant(83) => grant_signal(83),
+   grant(84) => grant_signal(84),
+   grant(85) => grant_signal(85),
+   grant(86) => grant_signal(86),
+   grant(87) => grant_signal(87),
+   grant(88) => grant_signal(88),
+   grant(89) => grant_signal(89),
+   grant(90) => grant_signal(90),
+   grant(91) => grant_signal(91),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80),
+   request(81) =>request_signal(81),
+   request(82) =>request_signal(82),
+   request(83) =>request_signal(83),
+   request(84) =>request_signal(84),
+   request(85) =>request_signal(85),
+   request(86) =>request_signal(86),
+   request(87) =>request_signal(87),
+   request(88) =>request_signal(88),
+   request(89) =>request_signal(89),
+   request(90) =>request_signal(90),
+   request(91) =>request_signal(91)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(92) => grant_signal(92),
+   grant(93) => grant_signal(93),
+   grant(94) => grant_signal(94),
+   grant(95) => grant_signal(95),
+   grant(96) => grant_signal(96),
+   grant(97) => grant_signal(97),
+   grant(98) => grant_signal(98),
+   grant(99) => grant_signal(99),
+   grant(100) => grant_signal(100),
+   grant(101) => grant_signal(101),
+   grant(102) => grant_signal(102),
+   grant(103) => grant_signal(103),
+   grant(104) => grant_signal(104),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(92) =>request_signal(92),
+   request(93) =>request_signal(93),
+   request(94) =>request_signal(94),
+   request(95) =>request_signal(95),
+   request(96) =>request_signal(96),
+   request(97) =>request_signal(97),
+   request(98) =>request_signal(98),
+   request(99) =>request_signal(99),
+   request(100) =>request_signal(100),
+   request(101) =>request_signal(101),
+   request(102) =>request_signal(102),
+   request(103) =>request_signal(103),
+   request(104) =>request_signal(104)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(105) => grant_signal(105),
+   grant(106) => grant_signal(106),
+   grant(107) => grant_signal(107),
+   grant(108) => grant_signal(108),
+   grant(109) => grant_signal(109),
+   grant(110) => grant_signal(110),
+   grant(111) => grant_signal(111),
+   grant(112) => grant_signal(112),
+   grant(113) => grant_signal(113),
+   grant(114) => grant_signal(114),
+   grant(115) => grant_signal(115),
+   grant(116) => grant_signal(116),
+   grant(117) => grant_signal(117),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(105) =>request_signal(105),
+   request(106) =>request_signal(106),
+   request(107) =>request_signal(107),
+   request(108) =>request_signal(108),
+   request(109) =>request_signal(109),
+   request(110) =>request_signal(110),
+   request(111) =>request_signal(111),
+   request(112) =>request_signal(112),
+   request(113) =>request_signal(113),
+   request(114) =>request_signal(114),
+   request(115) =>request_signal(115),
+   request(116) =>request_signal(116),
+   request(117) =>request_signal(117)
+);
+
+PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port10_in,
+   data_in_en => data_in_en(10),
+   reset => reset,
+   clk =>clk,
+   grant(118) => grant_signal(118),
+   grant(119) => grant_signal(119),
+   grant(120) => grant_signal(120),
+   grant(121) => grant_signal(121),
+   grant(122) => grant_signal(122),
+   grant(123) => grant_signal(123),
+   grant(124) => grant_signal(124),
+   grant(125) => grant_signal(125),
+   grant(126) => grant_signal(126),
+   grant(127) => grant_signal(127),
+   grant(128) => grant_signal(128),
+   grant(129) => grant_signal(129),
+   grant(130) => grant_signal(130),
+   fifo_full =>fifo_in_full(10),
+   priority_rotation =>  priority_rotation_signal(10),
+   fifo_empty => fifo_in_empty(10),
+   data_out =>crossbar_in_port10,
+   data_out_pulse =>crossbar_in_pulse10,
+   request(118) =>request_signal(118),
+   request(119) =>request_signal(119),
+   request(120) =>request_signal(120),
+   request(121) =>request_signal(121),
+   request(122) =>request_signal(122),
+   request(123) =>request_signal(123),
+   request(124) =>request_signal(124),
+   request(125) =>request_signal(125),
+   request(126) =>request_signal(126),
+   request(127) =>request_signal(127),
+   request(128) =>request_signal(128),
+   request(129) =>request_signal(129),
+   request(130) =>request_signal(130)
+);
+
+PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port11_in,
+   data_in_en => data_in_en(11),
+   reset => reset,
+   clk =>clk,
+   grant(131) => grant_signal(131),
+   grant(132) => grant_signal(132),
+   grant(133) => grant_signal(133),
+   grant(134) => grant_signal(134),
+   grant(135) => grant_signal(135),
+   grant(136) => grant_signal(136),
+   grant(137) => grant_signal(137),
+   grant(138) => grant_signal(138),
+   grant(139) => grant_signal(139),
+   grant(140) => grant_signal(140),
+   grant(141) => grant_signal(141),
+   grant(142) => grant_signal(142),
+   grant(143) => grant_signal(143),
+   fifo_full =>fifo_in_full(11),
+   priority_rotation =>  priority_rotation_signal(11),
+   fifo_empty => fifo_in_empty(11),
+   data_out =>crossbar_in_port11,
+   data_out_pulse =>crossbar_in_pulse11,
+   request(131) =>request_signal(131),
+   request(132) =>request_signal(132),
+   request(133) =>request_signal(133),
+   request(134) =>request_signal(134),
+   request(135) =>request_signal(135),
+   request(136) =>request_signal(136),
+   request(137) =>request_signal(137),
+   request(138) =>request_signal(138),
+   request(139) =>request_signal(139),
+   request(140) =>request_signal(140),
+   request(141) =>request_signal(141),
+   request(142) =>request_signal(142),
+   request(143) =>request_signal(143)
+);
+
+PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port12_in,
+   data_in_en => data_in_en(12),
+   reset => reset,
+   clk =>clk,
+   grant(144) => grant_signal(144),
+   grant(145) => grant_signal(145),
+   grant(146) => grant_signal(146),
+   grant(147) => grant_signal(147),
+   grant(148) => grant_signal(148),
+   grant(149) => grant_signal(149),
+   grant(150) => grant_signal(150),
+   grant(151) => grant_signal(151),
+   grant(152) => grant_signal(152),
+   grant(153) => grant_signal(153),
+   grant(154) => grant_signal(154),
+   grant(155) => grant_signal(155),
+   grant(156) => grant_signal(156),
+   fifo_full =>fifo_in_full(12),
+   priority_rotation =>  priority_rotation_signal(12),
+   fifo_empty => fifo_in_empty(12),
+   data_out =>crossbar_in_port12,
+   data_out_pulse =>crossbar_in_pulse12,
+   request(144) =>request_signal(144),
+   request(145) =>request_signal(145),
+   request(146) =>request_signal(146),
+   request(147) =>request_signal(147),
+   request(148) =>request_signal(148),
+   request(149) =>request_signal(149),
+   request(150) =>request_signal(150),
+   request(151) =>request_signal(151),
+   request(152) =>request_signal(152),
+   request(153) =>request_signal(153),
+   request(154) =>request_signal(154),
+   request(155) =>request_signal(155),
+   request(156) =>request_signal(156)
+);
+
+PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port13_in,
+   data_in_en => data_in_en(13),
+   reset => reset,
+   clk =>clk,
+   grant(157) => grant_signal(157),
+   grant(158) => grant_signal(158),
+   grant(159) => grant_signal(159),
+   grant(160) => grant_signal(160),
+   grant(161) => grant_signal(161),
+   grant(162) => grant_signal(162),
+   grant(163) => grant_signal(163),
+   grant(164) => grant_signal(164),
+   grant(165) => grant_signal(165),
+   grant(166) => grant_signal(166),
+   grant(167) => grant_signal(167),
+   grant(168) => grant_signal(168),
+   grant(169) => grant_signal(169),
+   fifo_full =>fifo_in_full(13),
+   priority_rotation =>  priority_rotation_signal(13),
+   fifo_empty => fifo_in_empty(13),
+   data_out =>crossbar_in_port13,
+   data_out_pulse =>crossbar_in_pulse13,
+   request(157) =>request_signal(157),
+   request(158) =>request_signal(158),
+   request(159) =>request_signal(159),
+   request(160) =>request_signal(160),
+   request(161) =>request_signal(161),
+   request(162) =>request_signal(162),
+   request(163) =>request_signal(163),
+   request(164) =>request_signal(164),
+   request(165) =>request_signal(165),
+   request(166) =>request_signal(166),
+   request(167) =>request_signal(167),
+   request(168) =>request_signal(168),
+   request(169) =>request_signal(169)
+);
+
+end generate switch13x13;
+
+
+-- switch 14 ports
+switch14x14 : if number_of_ports = 14 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30),
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36),
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   grant(55) => grant_signal(55),
+   grant(56) => grant_signal(56),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45),
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48),
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50),
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52),
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54),
+   request(55) =>request_signal(55),
+   request(56) =>request_signal(56)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   grant(64) => grant_signal(64),
+   grant(65) => grant_signal(65),
+   grant(66) => grant_signal(66),
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60),
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63),
+   request(64) =>request_signal(64),
+   request(65) =>request_signal(65),
+   request(66) =>request_signal(66),
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   grant(78) => grant_signal(78),
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   grant(81) => grant_signal(81),
+   grant(82) => grant_signal(82),
+   grant(83) => grant_signal(83),
+   grant(84) => grant_signal(84),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72),
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75),
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77),
+   request(78) =>request_signal(78),
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80),
+   request(81) =>request_signal(81),
+   request(82) =>request_signal(82),
+   request(83) =>request_signal(83),
+   request(84) =>request_signal(84)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(85) => grant_signal(85),
+   grant(86) => grant_signal(86),
+   grant(87) => grant_signal(87),
+   grant(88) => grant_signal(88),
+   grant(89) => grant_signal(89),
+   grant(90) => grant_signal(90),
+   grant(91) => grant_signal(91),
+   grant(92) => grant_signal(92),
+   grant(93) => grant_signal(93),
+   grant(94) => grant_signal(94),
+   grant(95) => grant_signal(95),
+   grant(96) => grant_signal(96),
+   grant(97) => grant_signal(97),
+   grant(98) => grant_signal(98),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(85) =>request_signal(85),
+   request(86) =>request_signal(86),
+   request(87) =>request_signal(87),
+   request(88) =>request_signal(88),
+   request(89) =>request_signal(89),
+   request(90) =>request_signal(90),
+   request(91) =>request_signal(91),
+   request(92) =>request_signal(92),
+   request(93) =>request_signal(93),
+   request(94) =>request_signal(94),
+   request(95) =>request_signal(95),
+   request(96) =>request_signal(96),
+   request(97) =>request_signal(97),
+   request(98) =>request_signal(98)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(99) => grant_signal(99),
+   grant(100) => grant_signal(100),
+   grant(101) => grant_signal(101),
+   grant(102) => grant_signal(102),
+   grant(103) => grant_signal(103),
+   grant(104) => grant_signal(104),
+   grant(105) => grant_signal(105),
+   grant(106) => grant_signal(106),
+   grant(107) => grant_signal(107),
+   grant(108) => grant_signal(108),
+   grant(109) => grant_signal(109),
+   grant(110) => grant_signal(110),
+   grant(111) => grant_signal(111),
+   grant(112) => grant_signal(112),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(99) =>request_signal(99),
+   request(100) =>request_signal(100),
+   request(101) =>request_signal(101),
+   request(102) =>request_signal(102),
+   request(103) =>request_signal(103),
+   request(104) =>request_signal(104),
+   request(105) =>request_signal(105),
+   request(106) =>request_signal(106),
+   request(107) =>request_signal(107),
+   request(108) =>request_signal(108),
+   request(109) =>request_signal(109),
+   request(110) =>request_signal(110),
+   request(111) =>request_signal(111),
+   request(112) =>request_signal(112)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(113) => grant_signal(113),
+   grant(114) => grant_signal(114),
+   grant(115) => grant_signal(115),
+   grant(116) => grant_signal(116),
+   grant(117) => grant_signal(117),
+   grant(118) => grant_signal(118),
+   grant(119) => grant_signal(119),
+   grant(120) => grant_signal(120),
+   grant(121) => grant_signal(121),
+   grant(122) => grant_signal(122),
+   grant(123) => grant_signal(123),
+   grant(124) => grant_signal(124),
+   grant(125) => grant_signal(125),
+   grant(126) => grant_signal(126),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(113) =>request_signal(113),
+   request(114) =>request_signal(114),
+   request(115) =>request_signal(115),
+   request(116) =>request_signal(116),
+   request(117) =>request_signal(117),
+   request(118) =>request_signal(118),
+   request(119) =>request_signal(119),
+   request(120) =>request_signal(120),
+   request(121) =>request_signal(121),
+   request(122) =>request_signal(122),
+   request(123) =>request_signal(123),
+   request(124) =>request_signal(124),
+   request(125) =>request_signal(125),
+   request(126) =>request_signal(126)
+);
+
+PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port10_in,
+   data_in_en => data_in_en(10),
+   reset => reset,
+   clk =>clk,
+   grant(127) => grant_signal(127),
+   grant(128) => grant_signal(128),
+   grant(129) => grant_signal(129),
+   grant(130) => grant_signal(130),
+   grant(131) => grant_signal(131),
+   grant(132) => grant_signal(132),
+   grant(133) => grant_signal(133),
+   grant(134) => grant_signal(134),
+   grant(135) => grant_signal(135),
+   grant(136) => grant_signal(136),
+   grant(137) => grant_signal(137),
+   grant(138) => grant_signal(138),
+   grant(139) => grant_signal(139),
+   grant(140) => grant_signal(140),
+   fifo_full =>fifo_in_full(10),
+   priority_rotation =>  priority_rotation_signal(10),
+   fifo_empty => fifo_in_empty(10),
+   data_out =>crossbar_in_port10,
+   data_out_pulse =>crossbar_in_pulse10,
+   request(127) =>request_signal(127),
+   request(128) =>request_signal(128),
+   request(129) =>request_signal(129),
+   request(130) =>request_signal(130),
+   request(131) =>request_signal(131),
+   request(132) =>request_signal(132),
+   request(133) =>request_signal(133),
+   request(134) =>request_signal(134),
+   request(135) =>request_signal(135),
+   request(136) =>request_signal(136),
+   request(137) =>request_signal(137),
+   request(138) =>request_signal(138),
+   request(139) =>request_signal(139),
+   request(140) =>request_signal(140)
+);
+
+PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port11_in,
+   data_in_en => data_in_en(11),
+   reset => reset,
+   clk =>clk,
+   grant(141) => grant_signal(141),
+   grant(142) => grant_signal(142),
+   grant(143) => grant_signal(143),
+   grant(144) => grant_signal(144),
+   grant(145) => grant_signal(145),
+   grant(146) => grant_signal(146),
+   grant(147) => grant_signal(147),
+   grant(148) => grant_signal(148),
+   grant(149) => grant_signal(149),
+   grant(150) => grant_signal(150),
+   grant(151) => grant_signal(151),
+   grant(152) => grant_signal(152),
+   grant(153) => grant_signal(153),
+   grant(154) => grant_signal(154),
+   fifo_full =>fifo_in_full(11),
+   priority_rotation =>  priority_rotation_signal(11),
+   fifo_empty => fifo_in_empty(11),
+   data_out =>crossbar_in_port11,
+   data_out_pulse =>crossbar_in_pulse11,
+   request(141) =>request_signal(141),
+   request(142) =>request_signal(142),
+   request(143) =>request_signal(143),
+   request(144) =>request_signal(144),
+   request(145) =>request_signal(145),
+   request(146) =>request_signal(146),
+   request(147) =>request_signal(147),
+   request(148) =>request_signal(148),
+   request(149) =>request_signal(149),
+   request(150) =>request_signal(150),
+   request(151) =>request_signal(151),
+   request(152) =>request_signal(152),
+   request(153) =>request_signal(153),
+   request(154) =>request_signal(154)
+);
+
+PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port12_in,
+   data_in_en => data_in_en(12),
+   reset => reset,
+   clk =>clk,
+   grant(155) => grant_signal(155),
+   grant(156) => grant_signal(156),
+   grant(157) => grant_signal(157),
+   grant(158) => grant_signal(158),
+   grant(159) => grant_signal(159),
+   grant(160) => grant_signal(160),
+   grant(161) => grant_signal(161),
+   grant(162) => grant_signal(162),
+   grant(163) => grant_signal(163),
+   grant(164) => grant_signal(164),
+   grant(165) => grant_signal(165),
+   grant(166) => grant_signal(166),
+   grant(167) => grant_signal(167),
+   grant(168) => grant_signal(168),
+   fifo_full =>fifo_in_full(12),
+   priority_rotation =>  priority_rotation_signal(12),
+   fifo_empty => fifo_in_empty(12),
+   data_out =>crossbar_in_port12,
+   data_out_pulse =>crossbar_in_pulse12,
+   request(155) =>request_signal(155),
+   request(156) =>request_signal(156),
+   request(157) =>request_signal(157),
+   request(158) =>request_signal(158),
+   request(159) =>request_signal(159),
+   request(160) =>request_signal(160),
+   request(161) =>request_signal(161),
+   request(162) =>request_signal(162),
+   request(163) =>request_signal(163),
+   request(164) =>request_signal(164),
+   request(165) =>request_signal(165),
+   request(166) =>request_signal(166),
+   request(167) =>request_signal(167),
+   request(168) =>request_signal(168)
+);
+
+PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port13_in,
+   data_in_en => data_in_en(13),
+   reset => reset,
+   clk =>clk,
+   grant(169) => grant_signal(169),
+   grant(170) => grant_signal(170),
+   grant(171) => grant_signal(171),
+   grant(172) => grant_signal(172),
+   grant(173) => grant_signal(173),
+   grant(174) => grant_signal(174),
+   grant(175) => grant_signal(175),
+   grant(176) => grant_signal(176),
+   grant(177) => grant_signal(177),
+   grant(178) => grant_signal(178),
+   grant(179) => grant_signal(179),
+   grant(180) => grant_signal(180),
+   grant(181) => grant_signal(181),
+   grant(182) => grant_signal(182),
+   fifo_full =>fifo_in_full(13),
+   priority_rotation =>  priority_rotation_signal(13),
+   fifo_empty => fifo_in_empty(13),
+   data_out =>crossbar_in_port13,
+   data_out_pulse =>crossbar_in_pulse13,
+   request(169) =>request_signal(169),
+   request(170) =>request_signal(170),
+   request(171) =>request_signal(171),
+   request(172) =>request_signal(172),
+   request(173) =>request_signal(173),
+   request(174) =>request_signal(174),
+   request(175) =>request_signal(175),
+   request(176) =>request_signal(176),
+   request(177) =>request_signal(177),
+   request(178) =>request_signal(178),
+   request(179) =>request_signal(179),
+   request(180) =>request_signal(180),
+   request(181) =>request_signal(181),
+   request(182) =>request_signal(182)
+);
+
+PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port14_in,
+   data_in_en => data_in_en(14),
+   reset => reset,
+   clk =>clk,
+   grant(183) => grant_signal(183),
+   grant(184) => grant_signal(184),
+   grant(185) => grant_signal(185),
+   grant(186) => grant_signal(186),
+   grant(187) => grant_signal(187),
+   grant(188) => grant_signal(188),
+   grant(189) => grant_signal(189),
+   grant(190) => grant_signal(190),
+   grant(191) => grant_signal(191),
+   grant(192) => grant_signal(192),
+   grant(193) => grant_signal(193),
+   grant(194) => grant_signal(194),
+   grant(195) => grant_signal(195),
+   grant(196) => grant_signal(196),
+   fifo_full =>fifo_in_full(14),
+   priority_rotation =>  priority_rotation_signal(14),
+   fifo_empty => fifo_in_empty(14),
+   data_out =>crossbar_in_port14,
+   data_out_pulse =>crossbar_in_pulse14,
+   request(183) =>request_signal(183),
+   request(184) =>request_signal(184),
+   request(185) =>request_signal(185),
+   request(186) =>request_signal(186),
+   request(187) =>request_signal(187),
+   request(188) =>request_signal(188),
+   request(189) =>request_signal(189),
+   request(190) =>request_signal(190),
+   request(191) =>request_signal(191),
+   request(192) =>request_signal(192),
+   request(193) =>request_signal(193),
+   request(194) =>request_signal(194),
+   request(195) =>request_signal(195),
+   request(196) =>request_signal(196)
+);
+
+end generate switch14x14;
+
+
+-- switch 15 ports
+switch15x15 : if number_of_ports = 15 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36),
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42),
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   grant(55) => grant_signal(55),
+   grant(56) => grant_signal(56),
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48),
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50),
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52),
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54),
+   request(55) =>request_signal(55),
+   request(56) =>request_signal(56),
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   grant(64) => grant_signal(64),
+   grant(65) => grant_signal(65),
+   grant(66) => grant_signal(66),
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63),
+   request(64) =>request_signal(64),
+   request(65) =>request_signal(65),
+   request(66) =>request_signal(66),
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70),
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72),
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   grant(78) => grant_signal(78),
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   grant(81) => grant_signal(81),
+   grant(82) => grant_signal(82),
+   grant(83) => grant_signal(83),
+   grant(84) => grant_signal(84),
+   grant(85) => grant_signal(85),
+   grant(86) => grant_signal(86),
+   grant(87) => grant_signal(87),
+   grant(88) => grant_signal(88),
+   grant(89) => grant_signal(89),
+   grant(90) => grant_signal(90),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77),
+   request(78) =>request_signal(78),
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80),
+   request(81) =>request_signal(81),
+   request(82) =>request_signal(82),
+   request(83) =>request_signal(83),
+   request(84) =>request_signal(84),
+   request(85) =>request_signal(85),
+   request(86) =>request_signal(86),
+   request(87) =>request_signal(87),
+   request(88) =>request_signal(88),
+   request(89) =>request_signal(89),
+   request(90) =>request_signal(90)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(91) => grant_signal(91),
+   grant(92) => grant_signal(92),
+   grant(93) => grant_signal(93),
+   grant(94) => grant_signal(94),
+   grant(95) => grant_signal(95),
+   grant(96) => grant_signal(96),
+   grant(97) => grant_signal(97),
+   grant(98) => grant_signal(98),
+   grant(99) => grant_signal(99),
+   grant(100) => grant_signal(100),
+   grant(101) => grant_signal(101),
+   grant(102) => grant_signal(102),
+   grant(103) => grant_signal(103),
+   grant(104) => grant_signal(104),
+   grant(105) => grant_signal(105),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(91) =>request_signal(91),
+   request(92) =>request_signal(92),
+   request(93) =>request_signal(93),
+   request(94) =>request_signal(94),
+   request(95) =>request_signal(95),
+   request(96) =>request_signal(96),
+   request(97) =>request_signal(97),
+   request(98) =>request_signal(98),
+   request(99) =>request_signal(99),
+   request(100) =>request_signal(100),
+   request(101) =>request_signal(101),
+   request(102) =>request_signal(102),
+   request(103) =>request_signal(103),
+   request(104) =>request_signal(104),
+   request(105) =>request_signal(105)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(106) => grant_signal(106),
+   grant(107) => grant_signal(107),
+   grant(108) => grant_signal(108),
+   grant(109) => grant_signal(109),
+   grant(110) => grant_signal(110),
+   grant(111) => grant_signal(111),
+   grant(112) => grant_signal(112),
+   grant(113) => grant_signal(113),
+   grant(114) => grant_signal(114),
+   grant(115) => grant_signal(115),
+   grant(116) => grant_signal(116),
+   grant(117) => grant_signal(117),
+   grant(118) => grant_signal(118),
+   grant(119) => grant_signal(119),
+   grant(120) => grant_signal(120),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(106) =>request_signal(106),
+   request(107) =>request_signal(107),
+   request(108) =>request_signal(108),
+   request(109) =>request_signal(109),
+   request(110) =>request_signal(110),
+   request(111) =>request_signal(111),
+   request(112) =>request_signal(112),
+   request(113) =>request_signal(113),
+   request(114) =>request_signal(114),
+   request(115) =>request_signal(115),
+   request(116) =>request_signal(116),
+   request(117) =>request_signal(117),
+   request(118) =>request_signal(118),
+   request(119) =>request_signal(119),
+   request(120) =>request_signal(120)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(121) => grant_signal(121),
+   grant(122) => grant_signal(122),
+   grant(123) => grant_signal(123),
+   grant(124) => grant_signal(124),
+   grant(125) => grant_signal(125),
+   grant(126) => grant_signal(126),
+   grant(127) => grant_signal(127),
+   grant(128) => grant_signal(128),
+   grant(129) => grant_signal(129),
+   grant(130) => grant_signal(130),
+   grant(131) => grant_signal(131),
+   grant(132) => grant_signal(132),
+   grant(133) => grant_signal(133),
+   grant(134) => grant_signal(134),
+   grant(135) => grant_signal(135),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(121) =>request_signal(121),
+   request(122) =>request_signal(122),
+   request(123) =>request_signal(123),
+   request(124) =>request_signal(124),
+   request(125) =>request_signal(125),
+   request(126) =>request_signal(126),
+   request(127) =>request_signal(127),
+   request(128) =>request_signal(128),
+   request(129) =>request_signal(129),
+   request(130) =>request_signal(130),
+   request(131) =>request_signal(131),
+   request(132) =>request_signal(132),
+   request(133) =>request_signal(133),
+   request(134) =>request_signal(134),
+   request(135) =>request_signal(135)
+);
+
+PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port10_in,
+   data_in_en => data_in_en(10),
+   reset => reset,
+   clk =>clk,
+   grant(136) => grant_signal(136),
+   grant(137) => grant_signal(137),
+   grant(138) => grant_signal(138),
+   grant(139) => grant_signal(139),
+   grant(140) => grant_signal(140),
+   grant(141) => grant_signal(141),
+   grant(142) => grant_signal(142),
+   grant(143) => grant_signal(143),
+   grant(144) => grant_signal(144),
+   grant(145) => grant_signal(145),
+   grant(146) => grant_signal(146),
+   grant(147) => grant_signal(147),
+   grant(148) => grant_signal(148),
+   grant(149) => grant_signal(149),
+   grant(150) => grant_signal(150),
+   fifo_full =>fifo_in_full(10),
+   priority_rotation =>  priority_rotation_signal(10),
+   fifo_empty => fifo_in_empty(10),
+   data_out =>crossbar_in_port10,
+   data_out_pulse =>crossbar_in_pulse10,
+   request(136) =>request_signal(136),
+   request(137) =>request_signal(137),
+   request(138) =>request_signal(138),
+   request(139) =>request_signal(139),
+   request(140) =>request_signal(140),
+   request(141) =>request_signal(141),
+   request(142) =>request_signal(142),
+   request(143) =>request_signal(143),
+   request(144) =>request_signal(144),
+   request(145) =>request_signal(145),
+   request(146) =>request_signal(146),
+   request(147) =>request_signal(147),
+   request(148) =>request_signal(148),
+   request(149) =>request_signal(149),
+   request(150) =>request_signal(150)
+);
+
+PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port11_in,
+   data_in_en => data_in_en(11),
+   reset => reset,
+   clk =>clk,
+   grant(151) => grant_signal(151),
+   grant(152) => grant_signal(152),
+   grant(153) => grant_signal(153),
+   grant(154) => grant_signal(154),
+   grant(155) => grant_signal(155),
+   grant(156) => grant_signal(156),
+   grant(157) => grant_signal(157),
+   grant(158) => grant_signal(158),
+   grant(159) => grant_signal(159),
+   grant(160) => grant_signal(160),
+   grant(161) => grant_signal(161),
+   grant(162) => grant_signal(162),
+   grant(163) => grant_signal(163),
+   grant(164) => grant_signal(164),
+   grant(165) => grant_signal(165),
+   fifo_full =>fifo_in_full(11),
+   priority_rotation =>  priority_rotation_signal(11),
+   fifo_empty => fifo_in_empty(11),
+   data_out =>crossbar_in_port11,
+   data_out_pulse =>crossbar_in_pulse11,
+   request(151) =>request_signal(151),
+   request(152) =>request_signal(152),
+   request(153) =>request_signal(153),
+   request(154) =>request_signal(154),
+   request(155) =>request_signal(155),
+   request(156) =>request_signal(156),
+   request(157) =>request_signal(157),
+   request(158) =>request_signal(158),
+   request(159) =>request_signal(159),
+   request(160) =>request_signal(160),
+   request(161) =>request_signal(161),
+   request(162) =>request_signal(162),
+   request(163) =>request_signal(163),
+   request(164) =>request_signal(164),
+   request(165) =>request_signal(165)
+);
+
+PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port12_in,
+   data_in_en => data_in_en(12),
+   reset => reset,
+   clk =>clk,
+   grant(166) => grant_signal(166),
+   grant(167) => grant_signal(167),
+   grant(168) => grant_signal(168),
+   grant(169) => grant_signal(169),
+   grant(170) => grant_signal(170),
+   grant(171) => grant_signal(171),
+   grant(172) => grant_signal(172),
+   grant(173) => grant_signal(173),
+   grant(174) => grant_signal(174),
+   grant(175) => grant_signal(175),
+   grant(176) => grant_signal(176),
+   grant(177) => grant_signal(177),
+   grant(178) => grant_signal(178),
+   grant(179) => grant_signal(179),
+   grant(180) => grant_signal(180),
+   fifo_full =>fifo_in_full(12),
+   priority_rotation =>  priority_rotation_signal(12),
+   fifo_empty => fifo_in_empty(12),
+   data_out =>crossbar_in_port12,
+   data_out_pulse =>crossbar_in_pulse12,
+   request(166) =>request_signal(166),
+   request(167) =>request_signal(167),
+   request(168) =>request_signal(168),
+   request(169) =>request_signal(169),
+   request(170) =>request_signal(170),
+   request(171) =>request_signal(171),
+   request(172) =>request_signal(172),
+   request(173) =>request_signal(173),
+   request(174) =>request_signal(174),
+   request(175) =>request_signal(175),
+   request(176) =>request_signal(176),
+   request(177) =>request_signal(177),
+   request(178) =>request_signal(178),
+   request(179) =>request_signal(179),
+   request(180) =>request_signal(180)
+);
+
+PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port13_in,
+   data_in_en => data_in_en(13),
+   reset => reset,
+   clk =>clk,
+   grant(181) => grant_signal(181),
+   grant(182) => grant_signal(182),
+   grant(183) => grant_signal(183),
+   grant(184) => grant_signal(184),
+   grant(185) => grant_signal(185),
+   grant(186) => grant_signal(186),
+   grant(187) => grant_signal(187),
+   grant(188) => grant_signal(188),
+   grant(189) => grant_signal(189),
+   grant(190) => grant_signal(190),
+   grant(191) => grant_signal(191),
+   grant(192) => grant_signal(192),
+   grant(193) => grant_signal(193),
+   grant(194) => grant_signal(194),
+   grant(195) => grant_signal(195),
+   fifo_full =>fifo_in_full(13),
+   priority_rotation =>  priority_rotation_signal(13),
+   fifo_empty => fifo_in_empty(13),
+   data_out =>crossbar_in_port13,
+   data_out_pulse =>crossbar_in_pulse13,
+   request(181) =>request_signal(181),
+   request(182) =>request_signal(182),
+   request(183) =>request_signal(183),
+   request(184) =>request_signal(184),
+   request(185) =>request_signal(185),
+   request(186) =>request_signal(186),
+   request(187) =>request_signal(187),
+   request(188) =>request_signal(188),
+   request(189) =>request_signal(189),
+   request(190) =>request_signal(190),
+   request(191) =>request_signal(191),
+   request(192) =>request_signal(192),
+   request(193) =>request_signal(193),
+   request(194) =>request_signal(194),
+   request(195) =>request_signal(195)
+);
+
+PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port14_in,
+   data_in_en => data_in_en(14),
+   reset => reset,
+   clk =>clk,
+   grant(196) => grant_signal(196),
+   grant(197) => grant_signal(197),
+   grant(198) => grant_signal(198),
+   grant(199) => grant_signal(199),
+   grant(200) => grant_signal(200),
+   grant(201) => grant_signal(201),
+   grant(202) => grant_signal(202),
+   grant(203) => grant_signal(203),
+   grant(204) => grant_signal(204),
+   grant(205) => grant_signal(205),
+   grant(206) => grant_signal(206),
+   grant(207) => grant_signal(207),
+   grant(208) => grant_signal(208),
+   grant(209) => grant_signal(209),
+   grant(210) => grant_signal(210),
+   fifo_full =>fifo_in_full(14),
+   priority_rotation =>  priority_rotation_signal(14),
+   fifo_empty => fifo_in_empty(14),
+   data_out =>crossbar_in_port14,
+   data_out_pulse =>crossbar_in_pulse14,
+   request(196) =>request_signal(196),
+   request(197) =>request_signal(197),
+   request(198) =>request_signal(198),
+   request(199) =>request_signal(199),
+   request(200) =>request_signal(200),
+   request(201) =>request_signal(201),
+   request(202) =>request_signal(202),
+   request(203) =>request_signal(203),
+   request(204) =>request_signal(204),
+   request(205) =>request_signal(205),
+   request(206) =>request_signal(206),
+   request(207) =>request_signal(207),
+   request(208) =>request_signal(208),
+   request(209) =>request_signal(209),
+   request(210) =>request_signal(210)
+);
+
+PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port15_in,
+   data_in_en => data_in_en(15),
+   reset => reset,
+   clk =>clk,
+   grant(211) => grant_signal(211),
+   grant(212) => grant_signal(212),
+   grant(213) => grant_signal(213),
+   grant(214) => grant_signal(214),
+   grant(215) => grant_signal(215),
+   grant(216) => grant_signal(216),
+   grant(217) => grant_signal(217),
+   grant(218) => grant_signal(218),
+   grant(219) => grant_signal(219),
+   grant(220) => grant_signal(220),
+   grant(221) => grant_signal(221),
+   grant(222) => grant_signal(222),
+   grant(223) => grant_signal(223),
+   grant(224) => grant_signal(224),
+   grant(225) => grant_signal(225),
+   fifo_full =>fifo_in_full(15),
+   priority_rotation =>  priority_rotation_signal(15),
+   fifo_empty => fifo_in_empty(15),
+   data_out =>crossbar_in_port15,
+   data_out_pulse =>crossbar_in_pulse15,
+   request(211) =>request_signal(211),
+   request(212) =>request_signal(212),
+   request(213) =>request_signal(213),
+   request(214) =>request_signal(214),
+   request(215) =>request_signal(215),
+   request(216) =>request_signal(216),
+   request(217) =>request_signal(217),
+   request(218) =>request_signal(218),
+   request(219) =>request_signal(219),
+   request(220) =>request_signal(220),
+   request(221) =>request_signal(221),
+   request(222) =>request_signal(222),
+   request(223) =>request_signal(223),
+   request(224) =>request_signal(224),
+   request(225) =>request_signal(225)
+);
+
+end generate switch15x15;
+
+
+-- switch 16 ports
+switch16x16 : if number_of_ports = 16 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30),
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36),
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42),
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45),
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   grant(55) => grant_signal(55),
+   grant(56) => grant_signal(56),
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   grant(64) => grant_signal(64),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50),
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52),
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54),
+   request(55) =>request_signal(55),
+   request(56) =>request_signal(56),
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60),
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63),
+   request(64) =>request_signal(64)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(65) => grant_signal(65),
+   grant(66) => grant_signal(66),
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   grant(78) => grant_signal(78),
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(65) =>request_signal(65),
+   request(66) =>request_signal(66),
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70),
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72),
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75),
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77),
+   request(78) =>request_signal(78),
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(81) => grant_signal(81),
+   grant(82) => grant_signal(82),
+   grant(83) => grant_signal(83),
+   grant(84) => grant_signal(84),
+   grant(85) => grant_signal(85),
+   grant(86) => grant_signal(86),
+   grant(87) => grant_signal(87),
+   grant(88) => grant_signal(88),
+   grant(89) => grant_signal(89),
+   grant(90) => grant_signal(90),
+   grant(91) => grant_signal(91),
+   grant(92) => grant_signal(92),
+   grant(93) => grant_signal(93),
+   grant(94) => grant_signal(94),
+   grant(95) => grant_signal(95),
+   grant(96) => grant_signal(96),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(81) =>request_signal(81),
+   request(82) =>request_signal(82),
+   request(83) =>request_signal(83),
+   request(84) =>request_signal(84),
+   request(85) =>request_signal(85),
+   request(86) =>request_signal(86),
+   request(87) =>request_signal(87),
+   request(88) =>request_signal(88),
+   request(89) =>request_signal(89),
+   request(90) =>request_signal(90),
+   request(91) =>request_signal(91),
+   request(92) =>request_signal(92),
+   request(93) =>request_signal(93),
+   request(94) =>request_signal(94),
+   request(95) =>request_signal(95),
+   request(96) =>request_signal(96)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(97) => grant_signal(97),
+   grant(98) => grant_signal(98),
+   grant(99) => grant_signal(99),
+   grant(100) => grant_signal(100),
+   grant(101) => grant_signal(101),
+   grant(102) => grant_signal(102),
+   grant(103) => grant_signal(103),
+   grant(104) => grant_signal(104),
+   grant(105) => grant_signal(105),
+   grant(106) => grant_signal(106),
+   grant(107) => grant_signal(107),
+   grant(108) => grant_signal(108),
+   grant(109) => grant_signal(109),
+   grant(110) => grant_signal(110),
+   grant(111) => grant_signal(111),
+   grant(112) => grant_signal(112),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(97) =>request_signal(97),
+   request(98) =>request_signal(98),
+   request(99) =>request_signal(99),
+   request(100) =>request_signal(100),
+   request(101) =>request_signal(101),
+   request(102) =>request_signal(102),
+   request(103) =>request_signal(103),
+   request(104) =>request_signal(104),
+   request(105) =>request_signal(105),
+   request(106) =>request_signal(106),
+   request(107) =>request_signal(107),
+   request(108) =>request_signal(108),
+   request(109) =>request_signal(109),
+   request(110) =>request_signal(110),
+   request(111) =>request_signal(111),
+   request(112) =>request_signal(112)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(113) => grant_signal(113),
+   grant(114) => grant_signal(114),
+   grant(115) => grant_signal(115),
+   grant(116) => grant_signal(116),
+   grant(117) => grant_signal(117),
+   grant(118) => grant_signal(118),
+   grant(119) => grant_signal(119),
+   grant(120) => grant_signal(120),
+   grant(121) => grant_signal(121),
+   grant(122) => grant_signal(122),
+   grant(123) => grant_signal(123),
+   grant(124) => grant_signal(124),
+   grant(125) => grant_signal(125),
+   grant(126) => grant_signal(126),
+   grant(127) => grant_signal(127),
+   grant(128) => grant_signal(128),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(113) =>request_signal(113),
+   request(114) =>request_signal(114),
+   request(115) =>request_signal(115),
+   request(116) =>request_signal(116),
+   request(117) =>request_signal(117),
+   request(118) =>request_signal(118),
+   request(119) =>request_signal(119),
+   request(120) =>request_signal(120),
+   request(121) =>request_signal(121),
+   request(122) =>request_signal(122),
+   request(123) =>request_signal(123),
+   request(124) =>request_signal(124),
+   request(125) =>request_signal(125),
+   request(126) =>request_signal(126),
+   request(127) =>request_signal(127),
+   request(128) =>request_signal(128)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(129) => grant_signal(129),
+   grant(130) => grant_signal(130),
+   grant(131) => grant_signal(131),
+   grant(132) => grant_signal(132),
+   grant(133) => grant_signal(133),
+   grant(134) => grant_signal(134),
+   grant(135) => grant_signal(135),
+   grant(136) => grant_signal(136),
+   grant(137) => grant_signal(137),
+   grant(138) => grant_signal(138),
+   grant(139) => grant_signal(139),
+   grant(140) => grant_signal(140),
+   grant(141) => grant_signal(141),
+   grant(142) => grant_signal(142),
+   grant(143) => grant_signal(143),
+   grant(144) => grant_signal(144),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(129) =>request_signal(129),
+   request(130) =>request_signal(130),
+   request(131) =>request_signal(131),
+   request(132) =>request_signal(132),
+   request(133) =>request_signal(133),
+   request(134) =>request_signal(134),
+   request(135) =>request_signal(135),
+   request(136) =>request_signal(136),
+   request(137) =>request_signal(137),
+   request(138) =>request_signal(138),
+   request(139) =>request_signal(139),
+   request(140) =>request_signal(140),
+   request(141) =>request_signal(141),
+   request(142) =>request_signal(142),
+   request(143) =>request_signal(143),
+   request(144) =>request_signal(144)
+);
+
+PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port10_in,
+   data_in_en => data_in_en(10),
+   reset => reset,
+   clk =>clk,
+   grant(145) => grant_signal(145),
+   grant(146) => grant_signal(146),
+   grant(147) => grant_signal(147),
+   grant(148) => grant_signal(148),
+   grant(149) => grant_signal(149),
+   grant(150) => grant_signal(150),
+   grant(151) => grant_signal(151),
+   grant(152) => grant_signal(152),
+   grant(153) => grant_signal(153),
+   grant(154) => grant_signal(154),
+   grant(155) => grant_signal(155),
+   grant(156) => grant_signal(156),
+   grant(157) => grant_signal(157),
+   grant(158) => grant_signal(158),
+   grant(159) => grant_signal(159),
+   grant(160) => grant_signal(160),
+   fifo_full =>fifo_in_full(10),
+   priority_rotation =>  priority_rotation_signal(10),
+   fifo_empty => fifo_in_empty(10),
+   data_out =>crossbar_in_port10,
+   data_out_pulse =>crossbar_in_pulse10,
+   request(145) =>request_signal(145),
+   request(146) =>request_signal(146),
+   request(147) =>request_signal(147),
+   request(148) =>request_signal(148),
+   request(149) =>request_signal(149),
+   request(150) =>request_signal(150),
+   request(151) =>request_signal(151),
+   request(152) =>request_signal(152),
+   request(153) =>request_signal(153),
+   request(154) =>request_signal(154),
+   request(155) =>request_signal(155),
+   request(156) =>request_signal(156),
+   request(157) =>request_signal(157),
+   request(158) =>request_signal(158),
+   request(159) =>request_signal(159),
+   request(160) =>request_signal(160)
+);
+
+PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port11_in,
+   data_in_en => data_in_en(11),
+   reset => reset,
+   clk =>clk,
+   grant(161) => grant_signal(161),
+   grant(162) => grant_signal(162),
+   grant(163) => grant_signal(163),
+   grant(164) => grant_signal(164),
+   grant(165) => grant_signal(165),
+   grant(166) => grant_signal(166),
+   grant(167) => grant_signal(167),
+   grant(168) => grant_signal(168),
+   grant(169) => grant_signal(169),
+   grant(170) => grant_signal(170),
+   grant(171) => grant_signal(171),
+   grant(172) => grant_signal(172),
+   grant(173) => grant_signal(173),
+   grant(174) => grant_signal(174),
+   grant(175) => grant_signal(175),
+   grant(176) => grant_signal(176),
+   fifo_full =>fifo_in_full(11),
+   priority_rotation =>  priority_rotation_signal(11),
+   fifo_empty => fifo_in_empty(11),
+   data_out =>crossbar_in_port11,
+   data_out_pulse =>crossbar_in_pulse11,
+   request(161) =>request_signal(161),
+   request(162) =>request_signal(162),
+   request(163) =>request_signal(163),
+   request(164) =>request_signal(164),
+   request(165) =>request_signal(165),
+   request(166) =>request_signal(166),
+   request(167) =>request_signal(167),
+   request(168) =>request_signal(168),
+   request(169) =>request_signal(169),
+   request(170) =>request_signal(170),
+   request(171) =>request_signal(171),
+   request(172) =>request_signal(172),
+   request(173) =>request_signal(173),
+   request(174) =>request_signal(174),
+   request(175) =>request_signal(175),
+   request(176) =>request_signal(176)
+);
+
+PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port12_in,
+   data_in_en => data_in_en(12),
+   reset => reset,
+   clk =>clk,
+   grant(177) => grant_signal(177),
+   grant(178) => grant_signal(178),
+   grant(179) => grant_signal(179),
+   grant(180) => grant_signal(180),
+   grant(181) => grant_signal(181),
+   grant(182) => grant_signal(182),
+   grant(183) => grant_signal(183),
+   grant(184) => grant_signal(184),
+   grant(185) => grant_signal(185),
+   grant(186) => grant_signal(186),
+   grant(187) => grant_signal(187),
+   grant(188) => grant_signal(188),
+   grant(189) => grant_signal(189),
+   grant(190) => grant_signal(190),
+   grant(191) => grant_signal(191),
+   grant(192) => grant_signal(192),
+   fifo_full =>fifo_in_full(12),
+   priority_rotation =>  priority_rotation_signal(12),
+   fifo_empty => fifo_in_empty(12),
+   data_out =>crossbar_in_port12,
+   data_out_pulse =>crossbar_in_pulse12,
+   request(177) =>request_signal(177),
+   request(178) =>request_signal(178),
+   request(179) =>request_signal(179),
+   request(180) =>request_signal(180),
+   request(181) =>request_signal(181),
+   request(182) =>request_signal(182),
+   request(183) =>request_signal(183),
+   request(184) =>request_signal(184),
+   request(185) =>request_signal(185),
+   request(186) =>request_signal(186),
+   request(187) =>request_signal(187),
+   request(188) =>request_signal(188),
+   request(189) =>request_signal(189),
+   request(190) =>request_signal(190),
+   request(191) =>request_signal(191),
+   request(192) =>request_signal(192)
+);
+
+PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port13_in,
+   data_in_en => data_in_en(13),
+   reset => reset,
+   clk =>clk,
+   grant(193) => grant_signal(193),
+   grant(194) => grant_signal(194),
+   grant(195) => grant_signal(195),
+   grant(196) => grant_signal(196),
+   grant(197) => grant_signal(197),
+   grant(198) => grant_signal(198),
+   grant(199) => grant_signal(199),
+   grant(200) => grant_signal(200),
+   grant(201) => grant_signal(201),
+   grant(202) => grant_signal(202),
+   grant(203) => grant_signal(203),
+   grant(204) => grant_signal(204),
+   grant(205) => grant_signal(205),
+   grant(206) => grant_signal(206),
+   grant(207) => grant_signal(207),
+   grant(208) => grant_signal(208),
+   fifo_full =>fifo_in_full(13),
+   priority_rotation =>  priority_rotation_signal(13),
+   fifo_empty => fifo_in_empty(13),
+   data_out =>crossbar_in_port13,
+   data_out_pulse =>crossbar_in_pulse13,
+   request(193) =>request_signal(193),
+   request(194) =>request_signal(194),
+   request(195) =>request_signal(195),
+   request(196) =>request_signal(196),
+   request(197) =>request_signal(197),
+   request(198) =>request_signal(198),
+   request(199) =>request_signal(199),
+   request(200) =>request_signal(200),
+   request(201) =>request_signal(201),
+   request(202) =>request_signal(202),
+   request(203) =>request_signal(203),
+   request(204) =>request_signal(204),
+   request(205) =>request_signal(205),
+   request(206) =>request_signal(206),
+   request(207) =>request_signal(207),
+   request(208) =>request_signal(208)
+);
+
+PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port14_in,
+   data_in_en => data_in_en(14),
+   reset => reset,
+   clk =>clk,
+   grant(209) => grant_signal(209),
+   grant(210) => grant_signal(210),
+   grant(211) => grant_signal(211),
+   grant(212) => grant_signal(212),
+   grant(213) => grant_signal(213),
+   grant(214) => grant_signal(214),
+   grant(215) => grant_signal(215),
+   grant(216) => grant_signal(216),
+   grant(217) => grant_signal(217),
+   grant(218) => grant_signal(218),
+   grant(219) => grant_signal(219),
+   grant(220) => grant_signal(220),
+   grant(221) => grant_signal(221),
+   grant(222) => grant_signal(222),
+   grant(223) => grant_signal(223),
+   grant(224) => grant_signal(224),
+   fifo_full =>fifo_in_full(14),
+   priority_rotation =>  priority_rotation_signal(14),
+   fifo_empty => fifo_in_empty(14),
+   data_out =>crossbar_in_port14,
+   data_out_pulse =>crossbar_in_pulse14,
+   request(209) =>request_signal(209),
+   request(210) =>request_signal(210),
+   request(211) =>request_signal(211),
+   request(212) =>request_signal(212),
+   request(213) =>request_signal(213),
+   request(214) =>request_signal(214),
+   request(215) =>request_signal(215),
+   request(216) =>request_signal(216),
+   request(217) =>request_signal(217),
+   request(218) =>request_signal(218),
+   request(219) =>request_signal(219),
+   request(220) =>request_signal(220),
+   request(221) =>request_signal(221),
+   request(222) =>request_signal(222),
+   request(223) =>request_signal(223),
+   request(224) =>request_signal(224)
+);
+
+PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port15_in,
+   data_in_en => data_in_en(15),
+   reset => reset,
+   clk =>clk,
+   grant(225) => grant_signal(225),
+   grant(226) => grant_signal(226),
+   grant(227) => grant_signal(227),
+   grant(228) => grant_signal(228),
+   grant(229) => grant_signal(229),
+   grant(230) => grant_signal(230),
+   grant(231) => grant_signal(231),
+   grant(232) => grant_signal(232),
+   grant(233) => grant_signal(233),
+   grant(234) => grant_signal(234),
+   grant(235) => grant_signal(235),
+   grant(236) => grant_signal(236),
+   grant(237) => grant_signal(237),
+   grant(238) => grant_signal(238),
+   grant(239) => grant_signal(239),
+   grant(240) => grant_signal(240),
+   fifo_full =>fifo_in_full(15),
+   priority_rotation =>  priority_rotation_signal(15),
+   fifo_empty => fifo_in_empty(15),
+   data_out =>crossbar_in_port15,
+   data_out_pulse =>crossbar_in_pulse15,
+   request(225) =>request_signal(225),
+   request(226) =>request_signal(226),
+   request(227) =>request_signal(227),
+   request(228) =>request_signal(228),
+   request(229) =>request_signal(229),
+   request(230) =>request_signal(230),
+   request(231) =>request_signal(231),
+   request(232) =>request_signal(232),
+   request(233) =>request_signal(233),
+   request(234) =>request_signal(234),
+   request(235) =>request_signal(235),
+   request(236) =>request_signal(236),
+   request(237) =>request_signal(237),
+   request(238) =>request_signal(238),
+   request(239) =>request_signal(239),
+   request(240) =>request_signal(240)
+);
+
+PORT16_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port16_in,
+   data_in_en => data_in_en(16),
+   reset => reset,
+   clk =>clk,
+   grant(241) => grant_signal(241),
+   grant(242) => grant_signal(242),
+   grant(243) => grant_signal(243),
+   grant(244) => grant_signal(244),
+   grant(245) => grant_signal(245),
+   grant(246) => grant_signal(246),
+   grant(247) => grant_signal(247),
+   grant(248) => grant_signal(248),
+   grant(249) => grant_signal(249),
+   grant(250) => grant_signal(250),
+   grant(251) => grant_signal(251),
+   grant(252) => grant_signal(252),
+   grant(253) => grant_signal(253),
+   grant(254) => grant_signal(254),
+   grant(255) => grant_signal(255),
+   grant(256) => grant_signal(256),
+   fifo_full =>fifo_in_full(16),
+   priority_rotation =>  priority_rotation_signal(16),
+   fifo_empty => fifo_in_empty(16),
+   data_out =>crossbar_in_port16,
+   data_out_pulse =>crossbar_in_pulse16,
+   request(241) =>request_signal(241),
+   request(242) =>request_signal(242),
+   request(243) =>request_signal(243),
+   request(244) =>request_signal(244),
+   request(245) =>request_signal(245),
+   request(246) =>request_signal(246),
+   request(247) =>request_signal(247),
+   request(248) =>request_signal(248),
+   request(249) =>request_signal(249),
+   request(250) =>request_signal(250),
+   request(251) =>request_signal(251),
+   request(252) =>request_signal(252),
+   request(253) =>request_signal(253),
+   request(254) =>request_signal(254),
+   request(255) =>request_signal(255),
+   request(256) =>request_signal(256)
+);
+
+end generate switch16x16;
+-- intstanciation et connexion des modules des ports de sorties fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+port_out_switch2x2 : if number_of_ports = 2 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+end generate port_out_switch2x2;
+
+
+-- switch 3 ports
+port_out_switch3x3 : if number_of_ports = 3 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+end generate port_out_switch3x3;
+
+
+-- switch 4 ports
+port_out_switch4x4 : if number_of_ports = 4 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+end generate port_out_switch4x4;
+
+
+-- switch 5 ports
+port_out_switch5x5 : if number_of_ports = 5 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+end generate port_out_switch5x5;
+
+
+-- switch 6 ports
+port_out_switch6x6 : if number_of_ports = 6 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+end generate port_out_switch6x6;
+
+
+-- switch 7 ports
+port_out_switch7x7 : if number_of_ports = 7 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+end generate port_out_switch7x7;
+
+
+-- switch 8 ports
+port_out_switch8x8 : if number_of_ports = 8 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+end generate port_out_switch8x8;
+
+
+-- switch 9 ports
+port_out_switch9x9 : if number_of_ports = 9 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+end generate port_out_switch9x9;
+
+
+-- switch 10 ports
+port_out_switch10x10 : if number_of_ports = 10 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port10,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse10,
+     data_out =>Port10_out,
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+end generate port_out_switch10x10;
+
+
+-- switch 11 ports
+port_out_switch11x11 : if number_of_ports = 11 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port10,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse10,
+     data_out =>Port10_out,
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port11,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse11,
+     data_out =>Port11_out,
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+end generate port_out_switch11x11;
+
+
+-- switch 12 ports
+port_out_switch12x12 : if number_of_ports = 12 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port10,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse10,
+     data_out =>Port10_out,
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port11,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse11,
+     data_out =>Port11_out,
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port12,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse12,
+     data_out =>Port12_out,
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+end generate port_out_switch12x12;
+
+
+-- switch 13 ports
+port_out_switch13x13 : if number_of_ports = 13 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port10,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse10,
+     data_out =>Port10_out,
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port11,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse11,
+     data_out =>Port11_out,
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port12,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse12,
+     data_out =>Port12_out,
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port13,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse13,
+     data_out =>Port13_out,
+     fifo_full =>fifo_out_full_signal(13),
+     data_avalaible => data_available(13),
+     rd_out_en => data_out_en(13)
+    );
+
+end generate port_out_switch13x13;
+
+
+-- switch 14 ports
+port_out_switch14x14 : if number_of_ports = 14 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port10,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse10,
+     data_out =>Port10_out,
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port11,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse11,
+     data_out =>Port11_out,
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port12,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse12,
+     data_out =>Port12_out,
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port13,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse13,
+     data_out =>Port13_out,
+     fifo_full =>fifo_out_full_signal(13),
+     data_avalaible => data_available(13),
+     rd_out_en => data_out_en(13)
+    );
+
+PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port14,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse14,
+     data_out =>Port14_out,
+     fifo_full =>fifo_out_full_signal(14),
+     data_avalaible => data_available(14),
+     rd_out_en => data_out_en(14)
+    );
+
+end generate port_out_switch14x14;
+
+
+-- switch 15 ports
+port_out_switch15x15 : if number_of_ports = 15 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port10,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse10,
+     data_out =>Port10_out,
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port11,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse11,
+     data_out =>Port11_out,
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port12,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse12,
+     data_out =>Port12_out,
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port13,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse13,
+     data_out =>Port13_out,
+     fifo_full =>fifo_out_full_signal(13),
+     data_avalaible => data_available(13),
+     rd_out_en => data_out_en(13)
+    );
+
+PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port14,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse14,
+     data_out =>Port14_out,
+     fifo_full =>fifo_out_full_signal(14),
+     data_avalaible => data_available(14),
+     rd_out_en => data_out_en(14)
+    );
+
+PORT15_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port15,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse15,
+     data_out =>Port15_out,
+     fifo_full =>fifo_out_full_signal(15),
+     data_avalaible => data_available(15),
+     rd_out_en => data_out_en(15)
+    );
+
+end generate port_out_switch15x15;
+
+
+-- switch 16 ports
+port_out_switch16x16 : if number_of_ports = 16 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port10,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse10,
+     data_out =>Port10_out,
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port11,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse11,
+     data_out =>Port11_out,
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port12,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse12,
+     data_out =>Port12_out,
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port13,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse13,
+     data_out =>Port13_out,
+     fifo_full =>fifo_out_full_signal(13),
+     data_avalaible => data_available(13),
+     rd_out_en => data_out_en(13)
+    );
+
+PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port14,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse14,
+     data_out =>Port14_out,
+     fifo_full =>fifo_out_full_signal(14),
+     data_avalaible => data_available(14),
+     rd_out_en => data_out_en(14)
+    );
+
+PORT15_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port15,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse15,
+     data_out =>Port15_out,
+     fifo_full =>fifo_out_full_signal(15),
+     data_avalaible => data_available(15),
+     rd_out_en => data_out_en(15)
+    );
+
+PORT16_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port16,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse16,
+     data_out =>Port16_out,
+     fifo_full =>fifo_out_full_signal(16),
+     data_avalaible => data_available(16),
+     rd_out_en => data_out_en(16)
+    );
+
+end generate port_out_switch16x16;
+
+-- intstanciation et connexion des crossbars du  switch en fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+crossbar_switch2x2 : if number_of_ports = 2 generate
+
+Switch_Crossbar2_2: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>2)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => "00000000",
+   Port4_in => "00000000",
+   Port5_in => "00000000",
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in =>'0' ,
+   Port4_pulse_in =>'0' ,
+   Port5_pulse_in =>'0' ,
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+   Ctrl => Grant_signal);
+end generate crossbar_switch2x2;
+
+
+-- switch 3 ports
+crossbar_switch3x3 : if number_of_ports = 3 generate
+
+Switch_Crossbar3_3: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>3)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => "00000000",
+   Port5_in => "00000000",
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in =>'0' ,
+   Port5_pulse_in =>'0' ,
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+   Ctrl => Grant_signal);
+end generate crossbar_switch3x3;
+
+
+-- switch 4 ports
+crossbar_switch4x4 : if number_of_ports = 4 generate
+
+Switch_Crossbar4_4: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>4)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => "00000000",
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in =>'0' ,
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+   Ctrl => Grant_signal);
+end generate crossbar_switch4x4;
+
+
+-- switch 5 ports
+crossbar_switch5x5 : if number_of_ports = 5 generate
+
+Switch_Crossbar5_5: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>5)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+   Ctrl => Grant_signal);
+end generate crossbar_switch5x5;
+
+
+-- switch 6 ports
+crossbar_switch6x6 : if number_of_ports = 6 generate
+
+Switch_Crossbar6_6: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>6)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+   Ctrl => Grant_signal);
+end generate crossbar_switch6x6;
+
+
+-- switch 7 ports
+crossbar_switch7x7 : if number_of_ports = 7 generate
+
+Switch_Crossbar7_7: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>7)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+   Ctrl => Grant_signal);
+end generate crossbar_switch7x7;
+
+
+-- switch 8 ports
+crossbar_switch8x8 : if number_of_ports = 8 generate
+
+Switch_Crossbar8_8: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>8)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+   Ctrl => Grant_signal);
+end generate crossbar_switch8x8;
+
+
+-- switch 9 ports
+crossbar_switch9x9 : if number_of_ports = 9 generate
+
+Switch_Crossbar9_9: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>9)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+   Ctrl => Grant_signal);
+end generate crossbar_switch9x9;
+
+
+-- switch 10 ports
+crossbar_switch10x10 : if number_of_ports = 10 generate
+
+Switch_Crossbar10_10: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>10)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => crossbar_in_port10,
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in => crossbar_in_pulse10,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+   Port10_pulse_out => crossbar_out_pulse10,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+  Port10_out => crossbar_out_port10,
+   Ctrl => Grant_signal);
+end generate crossbar_switch10x10;
+
+
+-- switch 11 ports
+crossbar_switch11x11 : if number_of_ports = 11 generate
+
+Switch_Crossbar11_11: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>11)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => crossbar_in_port10,
+   Port11_in => crossbar_in_port11,
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in => crossbar_in_pulse10,
+   Port11_pulse_in => crossbar_in_pulse11,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+   Port10_pulse_out => crossbar_out_pulse10,
+   Port11_pulse_out => crossbar_out_pulse11,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+  Port10_out => crossbar_out_port10,
+  Port11_out => crossbar_out_port11,
+   Ctrl => Grant_signal);
+end generate crossbar_switch11x11;
+
+
+-- switch 12 ports
+crossbar_switch12x12 : if number_of_ports = 12 generate
+
+Switch_Crossbar12_12: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>12)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => crossbar_in_port10,
+   Port11_in => crossbar_in_port11,
+   Port12_in => crossbar_in_port12,
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in => crossbar_in_pulse10,
+   Port11_pulse_in => crossbar_in_pulse11,
+   Port12_pulse_in => crossbar_in_pulse12,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+   Port10_pulse_out => crossbar_out_pulse10,
+   Port11_pulse_out => crossbar_out_pulse11,
+   Port12_pulse_out => crossbar_out_pulse12,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+  Port10_out => crossbar_out_port10,
+  Port11_out => crossbar_out_port11,
+  Port12_out => crossbar_out_port12,
+   Ctrl => Grant_signal);
+end generate crossbar_switch12x12;
+
+
+-- switch 13 ports
+crossbar_switch13x13 : if number_of_ports = 13 generate
+
+Switch_Crossbar13_13: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>13)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => crossbar_in_port10,
+   Port11_in => crossbar_in_port11,
+   Port12_in => crossbar_in_port12,
+   Port13_in => crossbar_in_port13,
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in => crossbar_in_pulse10,
+   Port11_pulse_in => crossbar_in_pulse11,
+   Port12_pulse_in => crossbar_in_pulse12,
+   Port13_pulse_in => crossbar_in_pulse13,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+   Port10_pulse_out => crossbar_out_pulse10,
+   Port11_pulse_out => crossbar_out_pulse11,
+   Port12_pulse_out => crossbar_out_pulse12,
+   Port13_pulse_out => crossbar_out_pulse13,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+  Port10_out => crossbar_out_port10,
+  Port11_out => crossbar_out_port11,
+  Port12_out => crossbar_out_port12,
+  Port13_out => crossbar_out_port13,
+   Ctrl => Grant_signal);
+end generate crossbar_switch13x13;
+
+
+-- switch 14 ports
+crossbar_switch14x14 : if number_of_ports = 14 generate
+
+Switch_Crossbar14_14: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>14)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => crossbar_in_port10,
+   Port11_in => crossbar_in_port11,
+   Port12_in => crossbar_in_port12,
+   Port13_in => crossbar_in_port13,
+   Port14_in => crossbar_in_port14,
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in => crossbar_in_pulse10,
+   Port11_pulse_in => crossbar_in_pulse11,
+   Port12_pulse_in => crossbar_in_pulse12,
+   Port13_pulse_in => crossbar_in_pulse13,
+   Port14_pulse_in => crossbar_in_pulse14,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+   Port10_pulse_out => crossbar_out_pulse10,
+   Port11_pulse_out => crossbar_out_pulse11,
+   Port12_pulse_out => crossbar_out_pulse12,
+   Port13_pulse_out => crossbar_out_pulse13,
+   Port14_pulse_out => crossbar_out_pulse14,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+  Port10_out => crossbar_out_port10,
+  Port11_out => crossbar_out_port11,
+  Port12_out => crossbar_out_port12,
+  Port13_out => crossbar_out_port13,
+  Port14_out => crossbar_out_port14,
+   Ctrl => Grant_signal);
+end generate crossbar_switch14x14;
+
+
+-- switch 15 ports
+crossbar_switch15x15 : if number_of_ports = 15 generate
+
+Switch_Crossbar15_15: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>15)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => crossbar_in_port10,
+   Port11_in => crossbar_in_port11,
+   Port12_in => crossbar_in_port12,
+   Port13_in => crossbar_in_port13,
+   Port14_in => crossbar_in_port14,
+   Port15_in => crossbar_in_port15,
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in => crossbar_in_pulse10,
+   Port11_pulse_in => crossbar_in_pulse11,
+   Port12_pulse_in => crossbar_in_pulse12,
+   Port13_pulse_in => crossbar_in_pulse13,
+   Port14_pulse_in => crossbar_in_pulse14,
+   Port15_pulse_in => crossbar_in_pulse15,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+   Port10_pulse_out => crossbar_out_pulse10,
+   Port11_pulse_out => crossbar_out_pulse11,
+   Port12_pulse_out => crossbar_out_pulse12,
+   Port13_pulse_out => crossbar_out_pulse13,
+   Port14_pulse_out => crossbar_out_pulse14,
+   Port15_pulse_out => crossbar_out_pulse15,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+  Port10_out => crossbar_out_port10,
+  Port11_out => crossbar_out_port11,
+  Port12_out => crossbar_out_port12,
+  Port13_out => crossbar_out_port13,
+  Port14_out => crossbar_out_port14,
+  Port15_out => crossbar_out_port15,
+   Ctrl => Grant_signal);
+end generate crossbar_switch15x15;
+
+
+-- switch 16 ports
+crossbar_switch16x16 : if number_of_ports = 16 generate
+
+Switch_Crossbar16_16: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>16)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => crossbar_in_port10,
+   Port11_in => crossbar_in_port11,
+   Port12_in => crossbar_in_port12,
+   Port13_in => crossbar_in_port13,
+   Port14_in => crossbar_in_port14,
+   Port15_in => crossbar_in_port15,
+   Port16_in => crossbar_in_port16,
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in => crossbar_in_pulse10,
+   Port11_pulse_in => crossbar_in_pulse11,
+   Port12_pulse_in => crossbar_in_pulse12,
+   Port13_pulse_in => crossbar_in_pulse13,
+   Port14_pulse_in => crossbar_in_pulse14,
+   Port15_pulse_in => crossbar_in_pulse15,
+   Port16_pulse_in => crossbar_in_pulse16,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+   Port10_pulse_out => crossbar_out_pulse10,
+   Port11_pulse_out => crossbar_out_pulse11,
+   Port12_pulse_out => crossbar_out_pulse12,
+   Port13_pulse_out => crossbar_out_pulse13,
+   Port14_pulse_out => crossbar_out_pulse14,
+   Port15_pulse_out => crossbar_out_pulse15,
+   Port16_pulse_out => crossbar_out_pulse16,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+  Port10_out => crossbar_out_port10,
+  Port11_out => crossbar_out_port11,
+  Port12_out => crossbar_out_port12,
+  Port13_out => crossbar_out_port13,
+  Port14_out => crossbar_out_port14,
+  Port15_out => crossbar_out_port15,
+  Port16_out => crossbar_out_port16,
+   Ctrl => Grant_signal);
+end generate crossbar_switch16x16;
+-- intstanciation et connexion du scheduler en fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+scheduler_switch2x2 : if number_of_ports = 2 generate
+
+Scheduler2_2: Scheduler 
+   GENERIC MAP(number_of_ports => 2 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch2x2;
+
+
+-- switch 3 ports
+scheduler_switch3x3 : if number_of_ports = 3 generate
+
+Scheduler3_3: Scheduler 
+   GENERIC MAP(number_of_ports => 3 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch3x3;
+
+
+-- switch 4 ports
+scheduler_switch4x4 : if number_of_ports = 4 generate
+
+Scheduler4_4: Scheduler 
+   GENERIC MAP(number_of_ports => 4 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch4x4;
+
+
+-- switch 5 ports
+scheduler_switch5x5 : if number_of_ports = 5 generate
+
+Scheduler5_5: Scheduler 
+   GENERIC MAP(number_of_ports => 5 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch5x5;
+
+
+-- switch 6 ports
+scheduler_switch6x6 : if number_of_ports = 6 generate
+
+Scheduler6_6: Scheduler 
+   GENERIC MAP(number_of_ports => 6 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch6x6;
+
+
+-- switch 7 ports
+scheduler_switch7x7 : if number_of_ports = 7 generate
+
+Scheduler7_7: Scheduler 
+   GENERIC MAP(number_of_ports => 7 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch7x7;
+
+
+-- switch 8 ports
+scheduler_switch8x8 : if number_of_ports = 8 generate
+
+Scheduler8_8: Scheduler 
+   GENERIC MAP(number_of_ports => 8 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch8x8;
+
+
+-- switch 9 ports
+scheduler_switch9x9 : if number_of_ports = 9 generate
+
+Scheduler9_9: Scheduler 
+   GENERIC MAP(number_of_ports => 9 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch9x9;
+
+
+-- switch 10 ports
+scheduler_switch10x10 : if number_of_ports = 10 generate
+
+Scheduler10_10: Scheduler 
+   GENERIC MAP(number_of_ports => 10 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch10x10;
+
+
+-- switch 11 ports
+scheduler_switch11x11 : if number_of_ports = 11 generate
+
+Scheduler11_11: Scheduler 
+   GENERIC MAP(number_of_ports => 11 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch11x11;
+
+
+-- switch 12 ports
+scheduler_switch12x12 : if number_of_ports = 12 generate
+
+Scheduler12_12: Scheduler 
+   GENERIC MAP(number_of_ports => 12 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch12x12;
+
+
+-- switch 13 ports
+scheduler_switch13x13 : if number_of_ports = 13 generate
+
+Scheduler13_13: Scheduler 
+   GENERIC MAP(number_of_ports => 13 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch13x13;
+
+
+-- switch 14 ports
+scheduler_switch14x14 : if number_of_ports = 14 generate
+
+Scheduler14_14: Scheduler 
+   GENERIC MAP(number_of_ports => 14 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch14x14;
+
+
+-- switch 15 ports
+scheduler_switch15x15 : if number_of_ports = 15 generate
+
+Scheduler15_15: Scheduler 
+   GENERIC MAP(number_of_ports => 15 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch15x15;
+
+
+-- switch 16 ports
+scheduler_switch16x16 : if number_of_ports = 16 generate
+
+Scheduler16_16: Scheduler 
+   GENERIC MAP(number_of_ports => 16 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch16x16;
+
+
+
+
+
+
+
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GENERIQUE_guide.ncd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GENERIQUE_guide.ncd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GENERIQUE_guide.ncd	(revision 20)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
+###3472:XlxV32DM    3f97     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NFgKZCenPpNpU8RgC6is9Z6E0bz/Ymhc3MS3iW8S3wA+DbmGbxKLQGF5u8WazYBRwV1iB642y+mgh9STUmv/3EAHquUo6/VDpTSPXgKA8618iCrG8NPCPl4YNh/K8VsVetBNT+Fk8Wp+vg1eCCxIZ392ME+VcrjH0jGCqb6k8E1ODdwIZz54BmpvUWcbV+xLXdZ6iR6woIfNeP1mdTYLPbxjLag+o5FysO9HURvUX3YDFnTMPt60ZiqX3iFeXbTm/4H0ANTqv327vcdoT0/trAah07QzxvoUvYfRyuyu5eC1CEX8I2OnjIMyLsho0mb0bg12cZmMmzKK6nt20zTJNiSLlIyQ5li29+ypt9Hb6ycmI8t8unsmY4SMkTIOyOgVMy2ZvhRxQETbqJ5oXVC8bWOEiPZtYMtMxEgRt4mo112T9aVg7Lq2GvBzy2mx0FV0zgfvKjJIuooAbYekq8ihdhukXUUOndu6QdJV5FAdDklXkUOXU9OuIodOJDVIuooMkq4ioyZdRYDAn3QVOcRR6SpyiKPSVQRoOiRdRQ5xVLqKHJouuXQVGYAx6SpyALikq8ihCOrSVeTQGNDYTS1GjEpXkUMTOpGuIocidCJdRYBeaOx+AMUI3XV8k64i11gDf9JV5BprgRBGI3ZAu4pcY9gf7SpyjT3gXq6HrrHnJuSj0lVkwOPYpKvIgAw+BtcNYpWuIoc2uJSuIocKeJOuIoc2pJauIkATGlsYla4i11jGqHQVucZgHdpV5Bp7b0LgT7qKHOKodBU5xFHpKgIEm5WuIoc4Kl1FDnWXXLqKDMDYgoMu+udzI5d5YHfarON6go61WQej9KxCa8uEFjQrzTr+DZ6gLTq+UwN2PBZHx4cDYJG01KHMb/MDga405jgWrNDGHOADXUkynb9ZCdFCJr0QvqpJnEOJkWkwgnFXpM0Ga8GLVOuxlvjSZ5S+jHikfQtuUwnfwkOuNqMpLE6bD1zKh1G3YN8SPViaCvwbNSRNBW6FlDdxP6SpwO0RcUrTa7dl7oKk/9A91gZ800In6BIzpQzUgdQ83dI7PEwaCNzSG2xeGghccp4tcqg6Po7K8y90ADk68cmN3KHx+QauItdKA4G5TOE0mkuDCWmzABigaImBgis6DyN5YvO1DQFfmgUgGla8kaGaCm8MwVKscgjhS5sFnPmbSkNQ0AKWz2uL+BDwYifdmikH4kihHi9E9MZTXdoB3KoCBaefSDsAGJ3EAmXsm/bVaVWJa2OnaLRcKEjbAYAvcv+IOXBjuKfSDiCQPBre26822pShyY12LtjvYAkVIYEss9cuBZsn7/h6yREsclWQq82wq80oXq7xe0rFPaX6PUUztcQf3+yeUnk9eXk9eXk9megdMaIJybqxOcnmIJsv2bRy1YMLe0I9akXn/HwLfrWx0QuYrWkhPV4ZXN52b10VB5K1z/KbjUQeu8VoCYm/gvm3ZJmpLIk3NP94TVK76/VKYvMiOeBazZJNykXZNO1/tQApab+pXglLy7SqSDu0rID7XFjMe0To/rwg6bwPSiOSGkEefHgquCjpg54tTTdeZfR3q9vFIGCvkj2BJa2A6n2m4uctk7FBHjO9e/Pfvk6dab3xI+OgjAsy+u8v8es51O4RKmPZkHFTxk0ZB2UclDFSsgjJAGz+XWeMiGT64muSDUrWKdmmZBclIzTtGb9uu9qoiEmvkQPqEVntpojHJpf15S7eEMygii4ZZaoGMjXAlM27N/RUO0rDa8BEl6DWWoA28aq6FdLgsKY/U2kmYf6nXTfrRfut+t/QeqPUPQzLJpZJLINYJrFMYlFtLHMI/eFWn1rCW1AJ8d939ccf+71wNzzSrOTQvb1ysqcV1U9oYAuGMmTvRRNtRUvLTZmjFxi3BqOJpyOBzH30ncFiw9KeqsTFN8vBzTMfiw1yBqCCPLJXPUL7JmfFQSWc2VAdqDv5RW/jgdFUp/soJ5NXBLT73HiFzxukzwJrcxSvRtahrarcFyKH4rYaQvBvti14jNr4KVa/PPiL8XkdGPjP6vFfCy/7wfJYxP+DGG/S###7244:XlxV32DM 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1360eNqtmk2S5LgNhS/jA4gi+KfaTNgbL7yww74ASUnLiZiFvanou/t7yMyu7Gl541FMDAoSSUAEgQeA2W0rrXz8u6a6rR/ffu1zLduyhc9fa2oMjfehFr+G1vjDSH4bSe8j/X1NeBvZ4/mm6HwfsfE1Un9Yk5a3kbcvGOsIXyOz97ehuNT3HZ3vQ2F9H9rfhtL70J7th6H8PvS23ZHXt+3G+MPIfBt5X9Ni+xoZ7wP2dhTv3zaP4/0DyvvQmd6H8tvQ3t8+O59vdh1HfvuE/MOOjvz23aV8fca3//wr7W5Z/ls+/2lL2NKR+J9Xcd3P5dxibiF//DXt/eO3tB8fYyxdszes9Mnr/eNPac9bnAzNffrQ8jY0tmjza863EUYNl7PG+6w1tUtZ+N/XrMcG2v+5gfDzBkYel0qTmAljP2j/9u2XX/7yuee6bEc+15kCL/78GdtnTe5EhMu2h9G3OWOC21fI0bd9XeDWIC6KM3FZXBHXxHVxU9wu7oSLfPoeVzjTCtMK0wrTCtMK0wrTCtOKpBVJK1IUl8RlcVVcEzfWj99qSh/fPqt5QG+Hf3YVySILpJ+QqV3MKKIpuwbmIaLJs+jdLjJEmnargUNSDk3eJeWUlFNSziBbaOCUlFOTz6J3u8gQabJUFckii94hZV2TSBSRlKiB9RDR5FVSoqRESYmSYhowSTFNjpKSJCVJSpKUrIEkKUmTk6RkScmSkiWlaKBIStHkLClVUqqkVElpGqiSUjW5SkqTlCYpTVK6BrqkdE1ukjIkZUjKkJSpgSEpOop1SMqUlCkpU1J2DeySoqNYp6QcknJIio5xPTVwSIqOYj0k5ZSUU1LOJq+qIllEk0+kxJBEokiQzy3iDhFNDkXvdpEh0uSRVSSLMNlkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1Wddk3STrJlk3ybom6yZZN8m6SdZNsm6SdZOsm2TdJOsmWTfJuilqIEqKHD2tkmKSYpJikpI0YJKio0gmKUlSkqQomaSsgSwpOoqUJKVISpGUIilVA0VSdBSpSEqVlCopVVKaBpqk6ChSlZQuKV1SuqQIMlKXFB1F6pIyJGVIyiDBH6G9YGdkge66xbCRjcDzvhH6C1lr3xbyJKBE2C+YalFKx25LMP4nTyqPY64Fuy2BlUDqElgbWBxYjVGXwHosvAATC0i4KMGvrAdAlpX1KpfAjAU7LyvrMfqiVM8JLADKgq0XjL7weQtovUTWR9YD6QsnskTWx/rxp5EjKWJhQ2m3B/wrtZftVPopb+/D2TVSSU51KkP1LRa8Ixa+IRbTYz4ggHQs+HEsQ+9wr1j5pFgLaakC9bHii7FhgtjKDmmMNpw0dkwU+yoO8ItdK/rQ49QjGSL2g3dD8wbuFQd1QhySMji5OAbJc+yIH7h6nPhTnARqnPrmOcRNcQcrJvgdd04n7pgk4jcQbXDvTNk5+rjvSNnZeTw41HgU9B4EWzwOFJ1YOJ64azxxw3h2PRKe8SRgTOdvC7BgC3nYAo5hgbO1wLYs8H224jW26t1aDYJDmkDS1r1sFjkwiwSMxYQUDAgBAixqrbE3M8LEbOoR+5mdzEucrSlqwCpEJU7BEqFtGQezbHxGrszLjXkZVwe1WFs4IyvYACTTO60tBJEVkr9VohXo4rFyWlbHCsHOVk8+soGU1kjq1sA4axwy+JW3VNkMAdcheDhByLtGAiX0JgS4TB0YTH0aRAODTRNr55amlk0iPU0tm3xumuTsNA+ETg6FsobRHaBLBxkzqWhMB6ZLB/CWTqk88f50EqzpBHnTKcknLpAVAnnp65Z1MlknkwNhkwOpIAd2lMNgnrJyVnWTlYJyxPVyRFuOVDI5YqYca4eAIdkAgMzpQSLyjNIl29AjFUdOOHVOHQEJv8oJ/8toUunLvJxVBGPEnLs4Tjpn/DSXhRWFrEL0RUjTI66Sy8wbhRxTakRvBbEoHBHVSGS5VXES1UgKuR3itIWON6GC0U6Y5gFG5VEQMIjVPLXBCZ7kaUyZKs0nB5VpbyD4Wp7kjTzx8UxZA8ks23HqvONNeaf+yvuud9RG+QBh8qHtn9r+qe2fBGI+qSzzyVcVIWFZCNOygCplIZLLQjlWAnmoBA65BFyqqEoqK1stK3kD3CkQTV41WSVBiYBrieSXEnHlEgmrEvnmQnhvxYDVYhpVHi+GXwFc4sinxSj+ilJfUatVlH2IBxQlSUkdHWo9Sjr1jsMrmaRVMpbkdOAKBiuFVFUKHlYqDlwqTlgqrlIqrlKqNlhJ5qUeekeQlAa4FwVOaZwqzS9rdVqlyy4dnyy9ipPyTl1aBk5ThgwxCOcyhh5BpDKJHryCd5MwLVOipj6Xkg2CU5ddBtupC8p+MnqAUuWg6CxHYi09AQS3KAeFRVH0lLOqU+56BAqqAqcuQD2eR/ILHEoNfH1VZVxX8nNVfVhVxVUhV416NMoJUGSHJKSoBKpG2NN2rBBNUSzUjK0qzgbBxJVDgvBVpA8ISiBESq04f61soTYSYm1sujYqoqokUpVEaifr1Z71CALXQY6qA7vUwUmTiVg2KQTqPBjdo4ged40eHEo9igi9Qz2DCE5TTwk4aQeaEmlbwMS2gLEEHu8CPk5mKxD2xslWSDkh+F9TG9TIkBA204xYbYZ7N6PRaCqVmiqTlhcEgAUQTqsRIBCJFyq3AmICthqgt2mVXTZ2DQETm9r31sDn1nFlPIopncKndbJuk9O00Xg3OY829fUTl2pKgW3XPnbM3g5OtR3ASJNbtEOfe4KE7aSkAkWOrS9AeF9wvR6ofLB6g3BufeUA+prFAX0cApPJ9BA8opvmGR/Ula16wvW6Aqyrbe3ALQQj9kyd1jPZpRfcoqu26IVurdcgwsn0CkT2Bv71xkf2hlP3zof3Ti3YO2jWdeZ9SPkgdfRJkuuTbfVJ2Pcp8VSEEAzWD+3jwF8oMsLWz0UEZ+0nk8dCsTMWkH8sIPBYiIURSJVDXeJQLzdWyoBBT70NnfSInMwQDo0oAZHSZZgEGMc4VJsPFcVDeXok4HBkUsfIkgIYb6MAzUM7B57hKh8+KsXuUBIelZTPUbKsgU2jkyZG53NH7+JIgQNNEGKLwggysf3QrdnYFz5N91pjp+wdQgHQv/2+6KN8BN3bFnAbdbAroBU5cnUxKtHzKqgWqijIitySc2UP5IVBtzwJ0p3uRpn5JIjDUtYtBJJ6UE8aqBG3QIWxhaQblowfhEKeCZWkHlRChEHVEpSKwo6x6c2ZfA7jc0CQNbDfdcVqq/pAmue4rWqiVtl0Je1unAnfXc51WysnQydbN5rYsdG1Hts6Q/j9pof2TMkX2WRUmRXVCsXEaus4n03yvR2kUroeao9IYKWc8pec9FVJH++V9Nt7yke67dfQUOOwUVy6pUNXNa/iHGufziwquz/+NkDX9fNvEWyOn79Ry378OuhNF/7oLu3j2/8aCrr7Qc3+VOOHWY4rNeOPq1Fn81Ajf0nhSs3xx9X4rafUuEt6e/R7NSXcoOZ4qpHX21mu1NgfV6OWzNUosNLsV2rKDWpeZ6PYpTS8UtNvUNOeahweynKlZr9BTX+pEQJZvPK0dIOa8VTjIKcG/mc16w3h+fI04ahKwJ/VpPMGNedTjaCaxHilZt6AAstTjWeDel6paTeoCS81Sjh5vVKTb1CzPtV4TtM9ys9q4g1qXpjmaVO/If2sZrlBjT3VKDMf52Xc3GG09FSj5H+el3FzhwvkV/b0+mI5ryIn3+HSL4x+1DDhvIqdfEOIhhd8Puok3W9fAOgNkBP698LDa7HlKn7KDRAaXhD6rPeWqwgqN9Q44Xsp9agpL2Oo3FHlvIqpZ916nRbuwIRXWnjWxvHS6+5AhVdieNbf12B6Q9peX6nhUePreuNC0Q1lyPpKDo8+QpfEF4puKKvWV3p49Cpzv6pG0w1l4vpC7kc/pMvpC0V3lL0v7H72XOtVDWd3lPHf0fvR162X2eiOMyrfux/1jst1PrrD6773P96fhnmZj+6Io1eaePTAa7tChnIDMqyvNPHss/NlProB69bxXZH38naZj24oTdZXmnjeF4TLfHRDcbJ+77n9TiIdl/nohuJkfaH3494jj8tbhDs61Rd6P+9W6uU9wg0QFMN3RX5/k69uEtINEBRf6P28I4qX6H1DzRBf5f3zHmq5uk1IN1RB8ZUmHndd+u30QtEdrfErTTzu00a/ulFIN1Sq8ZUmdGcHqZf56A/X3t9++eXvn//AWsvHP/Sj/Mdv6mMX/gR/2nPJW/W/++MvH3L63/D8a7rFc061zXCuKd84N3Tx5tyh+zFx7ZGyxflllnN+peVc1c2Tc133T87tuiZyTj+VdnH6LXN1yfqNre3OFV3AOKd/R7c4N3Vb4tyhOxNxI+hqw7moCw7nsu4hnNOPAc25oUsD5/zqQNzUzbdLnqv6fOeS2nHnippy5/RvylzynOqgnTvV6Irbg9pd50xdqXNZvalzTS2kc0ONpHOH93ti9W/n6PqcfTRnzj5aNGerd1LOdu+nnN297XH29OZHLFCjHsVZ807F2eINhbPN2wpnp1f/zh7eA8DqykulurPRC3Zns9fVzlavrp0dXgQ7u3spLBafU8Xq7Op1q7PJy0tnixeZznavBZ2dXhE6e3rhJnYNXr45a15lOZu91nK2eUnk7PDCyNnD6xexIL6qGGcfxYazyUsOZ6tXBs52rw+c3T2NO3t6MhdLSlfOddY88zpbPEE6+0iTzk7PZs4entPEpuCpx9noCcjZ7HnC2erZwtnhoO7s7tAuFqwQAju7Og47mxwunS0Oms52xzZnpyOcs+fjxwPY8oCjD6Djv7UfTts=
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GEN_bitgen.xwbt
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GEN_bitgen.xwbt	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GEN_bitgen.xwbt	(revision 20)
@@ -0,0 +1,8 @@
+INTSTYLE=ise
+INFILE=C:\Core MPI\SWITCH_GENERIC_16_16\SWITCH_GEN.ncd
+OUTFILE=C:\Core MPI\SWITCH_GENERIC_16_16\SWITCH_GEN.bit
+FAMILY=Spartan3E
+PART=xc3s1200e-4ft256
+WORKINGDIR=C:\Core MPI\SWITCH_GENERIC_16_16
+LICENSE=ISE
+USER_INFO=No user information available.
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GEN_envsettings.html
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GEN_envsettings.html	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GEN_envsettings.html	(revision 20)
@@ -0,0 +1,382 @@
+<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<center><big><big><b>System Settings</b></big></big></center><br>
+<A NAME="Environment Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Environment Variable</b></td>
+<td><b>xst</b></td>
+<td><b>ngdbuild</b></td>
+<td><b>map</b></td>
+<td><b>par</b></td>
+</tr>
+<tr>
+<td>PATHEXT</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>Path</td>
+<td>d:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>D:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>D:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Windows Live\Shared;<br>C:\Program Files (x86)\CMake 2.8\bin;<br>C:\qtsdk\mingw\bin;<br>C:\qtsdk\qtcreator\bin;<br>C:\Program Files (x86)\Graphviz 2.28\bin;<br>C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;<br>C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;<br>C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;<br>c:\altera\90sp1\quartus\bin;<br>C:\Program Files\Oracle\VirtualBox</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>XILINX</td>
+<td>d:\Xilinx\12.3\ISE_DS\ISE\</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>XILINX_DSP</td>
+<td>D:\Xilinx\12.3\ISE_DS\ISE</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>XILINX_EDK</td>
+<td>D:\Xilinx\12.3\ISE_DS\EDK</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>XILINX_PLANAHEAD</td>
+<td>D:\Xilinx\12.3\ISE_DS\PlanAhead</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+</TABLE>
+<A NAME="Synthesis Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-ifn</td>
+<td>&nbsp;</td>
+<td>SWITCH_GEN.prj</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ifmt</td>
+<td>&nbsp;</td>
+<td>mixed</td>
+<td>MIXED</td>
+</tr>
+<tr>
+<td>-ofn</td>
+<td>&nbsp;</td>
+<td>SWITCH_GEN</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ofmt</td>
+<td>&nbsp;</td>
+<td>NGC</td>
+<td>NGC</td>
+</tr>
+<tr>
+<td>-p</td>
+<td>&nbsp;</td>
+<td>xc3s1200e-4-ft256</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-top</td>
+<td>&nbsp;</td>
+<td>SWITCH_GEN</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-opt_mode</td>
+<td>Optimization Goal</td>
+<td>Speed</td>
+<td>Speed</td>
+</tr>
+<tr>
+<td>-opt_level</td>
+<td>Optimization Effort</td>
+<td>1</td>
+<td>1</td>
+</tr>
+<tr>
+<td>-iuc</td>
+<td>Use synthesis Constraints File</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-keep_hierarchy</td>
+<td>Keep Hierarchy</td>
+<td>No</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-netlist_hierarchy</td>
+<td>Netlist Hierarchy</td>
+<td>As_Optimized</td>
+<td>As_Optimized</td>
+</tr>
+<tr>
+<td>-rtlview</td>
+<td>Generate RTL Schematic</td>
+<td>Yes</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-glob_opt</td>
+<td>Global Optimization Goal</td>
+<td>AllClockNets</td>
+<td>AllClockNets</td>
+</tr>
+<tr>
+<td>-read_cores</td>
+<td>Read Cores</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-write_timing_constraints</td>
+<td>Write Timing Constraints</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-cross_clock_analysis</td>
+<td>Cross Clock Analysis</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-bus_delimiter</td>
+<td>Bus Delimiter</td>
+<td>&lt;&gt;</td>
+<td>&lt;&gt;</td>
+</tr>
+<tr>
+<td>-slice_utilization_ratio</td>
+<td>Slice Utilization Ratio</td>
+<td>100</td>
+<td>100%</td>
+</tr>
+<tr>
+<td>-bram_utilization_ratio</td>
+<td>BRAM Utilization Ratio</td>
+<td>100</td>
+<td>100%</td>
+</tr>
+<tr>
+<td>-verilog2001</td>
+<td>Verilog 2001</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-fsm_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-fsm_encoding</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-safe_implementation</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-fsm_style</td>
+<td>&nbsp;</td>
+<td>LUT</td>
+<td>LUT</td>
+</tr>
+<tr>
+<td>-ram_extract</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-ram_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-rom_extract</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-shreg_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-rom_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-auto_bram_packing</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-resource_sharing</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-async_to_sync</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-mult_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-iobuf</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-max_fanout</td>
+<td>&nbsp;</td>
+<td>100000</td>
+<td>500</td>
+</tr>
+<tr>
+<td>-bufg</td>
+<td>&nbsp;</td>
+<td>24</td>
+<td>24</td>
+</tr>
+<tr>
+<td>-register_duplication</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-register_balancing</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-optimize_primitives</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-use_clock_enable</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-use_sync_set</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-use_sync_reset</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-iob</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-equivalent_register_removal</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-slice_utilization_ratio_maxmargin</td>
+<td>&nbsp;</td>
+<td>5</td>
+<td>0%</td>
+</tr>
+</TABLE>
+<A NAME="Operating System Information"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Operating System Information</b></td>
+<td><b>xst</b></td>
+<td><b>ngdbuild</b></td>
+<td><b>map</b></td>
+<td><b>par</b></td>
+</tr>
+<tr>
+<td>CPU Architecture/Speed</td>
+<td>Intel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHz</td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>Host</td>
+<td>GAMOM-PC</td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>OS Name</td>
+<td>Microsoft </td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>OS Release</td>
+<td>Service Pack 1  (build 7601)</td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+</tr>
+</TABLE>
+</BODY> </HTML>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GEN_guide.ncd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GEN_guide.ncd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/SWITCH_GEN_guide.ncd	(revision 20)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
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Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Scheduler.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Scheduler.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Scheduler.vhd	(revision 20)
@@ -0,0 +1,432 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    19:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisé est le DPA (diagonal propagation arbiter)
+-- intencie un scheduler particulier en fonction du nombre de port
+-- Dependencies: 
+--
+-- Revision: 1.0
+-- reconstruction du dpa
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Scheduler is
+   generic(number_of_ports : positive := 4);
+    Port ( Request : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
+			  Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1);
+           clk : in  STD_LOGIC;
+	        reset : in  STD_LOGIC;
+			  priority_rotation : in  STD_LOGIC_VECTOR (number_of_ports downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1));
+      end Scheduler;
+		
+architecture Behavioral of Scheduler is
+-- composants du scheduler
+
+-- composants du scheduler
+
+
+COMPONENT Scheduler2_2
+   PORT(
+      Request : IN std_logic_vector(4 downto 1);
+      Fifo_full : IN std_logic_vector(2 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(4 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (2 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler3_3
+   PORT(
+      Request : IN std_logic_vector(9 downto 1);
+      Fifo_full : IN std_logic_vector(3 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(9 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (3 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler4_4
+   PORT(
+      Request : IN std_logic_vector(16 downto 1);
+      Fifo_full : IN std_logic_vector(4 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(16 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (4 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler5_5
+   PORT(
+      Request : IN std_logic_vector(25 downto 1);
+      Fifo_full : IN std_logic_vector(5 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(25 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (5 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler6_6
+   PORT(
+      Request : IN std_logic_vector(36 downto 1);
+      Fifo_full : IN std_logic_vector(6 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(36 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (6 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler7_7
+   PORT(
+      Request : IN std_logic_vector(49 downto 1);
+      Fifo_full : IN std_logic_vector(7 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(49 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (7 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler8_8
+   PORT(
+      Request : IN std_logic_vector(64 downto 1);
+      Fifo_full : IN std_logic_vector(8 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(64 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (8 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler9_9
+   PORT(
+      Request : IN std_logic_vector(81 downto 1);
+      Fifo_full : IN std_logic_vector(9 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(81 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (9 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler10_10
+   PORT(
+      Request : IN std_logic_vector(100 downto 1);
+      Fifo_full : IN std_logic_vector(10 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(100 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (10 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler11_11
+   PORT(
+      Request : IN std_logic_vector(121 downto 1);
+      Fifo_full : IN std_logic_vector(11 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(121 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (11 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler12_12
+   PORT(
+      Request : IN std_logic_vector(144 downto 1);
+      Fifo_full : IN std_logic_vector(12 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(144 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (12 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler13_13
+   PORT(
+      Request : IN std_logic_vector(169 downto 1);
+      Fifo_full : IN std_logic_vector(13 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(169 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (13 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler14_14
+   PORT(
+      Request : IN std_logic_vector(196 downto 1);
+      Fifo_full : IN std_logic_vector(14 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(196 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (14 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler15_15
+   PORT(
+      Request : IN std_logic_vector(225 downto 1);
+      Fifo_full : IN std_logic_vector(15 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(225 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (15 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler16_16
+   PORT(
+      Request : IN std_logic_vector(256 downto 1);
+      Fifo_full : IN std_logic_vector(16 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(256 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (16 downto 1)
+   );
+ END COMPONENT;
+
+
+-- instanciation des scheduler
+--======================scheduler 2 ports=======================
+
+begin
+
+-- instanciation des scheduler
+--======================scheduler 2 ports=======================
+
+scheduler2x2 : if number_of_ports = 2 generate
+
+  Inst_Scheduler2_2 : Scheduler2_2
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler2x2; 
+
+--======================scheduler 3 ports=======================
+
+scheduler3x3 : if number_of_ports = 3 generate
+
+  Inst_Scheduler3_3 : Scheduler3_3
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler3x3; 
+
+--======================scheduler 4 ports=======================
+
+scheduler4x4 : if number_of_ports = 4 generate
+
+  Inst_Scheduler4_4 : Scheduler4_4
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler4x4; 
+
+--======================scheduler 5 ports=======================
+
+scheduler5x5 : if number_of_ports = 5 generate
+
+  Inst_Scheduler5_5 : Scheduler5_5
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler5x5; 
+
+--======================scheduler 6 ports=======================
+
+scheduler6x6 : if number_of_ports = 6 generate
+
+  Inst_Scheduler6_6 : Scheduler6_6
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler6x6; 
+
+--======================scheduler 7 ports=======================
+
+scheduler7x7 : if number_of_ports = 7 generate
+
+  Inst_Scheduler7_7 : Scheduler7_7
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler7x7; 
+
+--======================scheduler 8 ports=======================
+
+scheduler8x8 : if number_of_ports = 8 generate
+
+  Inst_Scheduler8_8 : Scheduler8_8
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler8x8; 
+
+--======================scheduler 9 ports=======================
+
+scheduler9x9 : if number_of_ports = 9 generate
+
+  Inst_Scheduler9_9 : Scheduler9_9
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler9x9; 
+
+--======================scheduler 10 ports=======================
+
+scheduler10x10 : if number_of_ports = 10 generate
+
+  Inst_Scheduler10_10 : Scheduler10_10
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler10x10; 
+
+--======================scheduler 11 ports=======================
+
+scheduler11x11 : if number_of_ports = 11 generate
+
+  Inst_Scheduler11_11 : Scheduler11_11
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler11x11; 
+
+--======================scheduler 12 ports=======================
+
+scheduler12x12 : if number_of_ports = 12 generate
+
+  Inst_Scheduler12_12 : Scheduler12_12
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler12x12; 
+
+--======================scheduler 13 ports=======================
+
+scheduler13x13 : if number_of_ports = 13 generate
+
+  Inst_Scheduler13_13 : Scheduler13_13
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler13x13; 
+
+--======================scheduler 14 ports=======================
+
+scheduler14x14 : if number_of_ports = 14 generate
+
+  Inst_Scheduler14_14 : Scheduler14_14
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler14x14; 
+
+--======================scheduler 15 ports=======================
+
+scheduler15x15 : if number_of_ports = 15 generate
+
+  Inst_Scheduler15_15 : Scheduler15_15
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler15x15; 
+
+--======================scheduler 16 ports=======================
+
+scheduler16x16 : if number_of_ports = 16 generate
+
+  Inst_Scheduler16_16 : Scheduler16_16
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler16x16; 
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Scheduler4_4.vhi
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Scheduler4_4.vhi	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Scheduler4_4.vhi	(revision 20)
@@ -0,0 +1,29 @@
+
+-- VHDL Instantiation Created from source file Scheduler4_4.vhd -- 13:38:35 06/19/2011
+--
+-- Notes: 
+-- 1) This instantiation template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the instantiated module
+-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
+
+	COMPONENT Scheduler4_4
+	PORT(
+		Request : IN std_logic_vector(16 downto 1);
+		Fifo_full : IN std_logic_vector(4 downto 1);
+		clk : IN std_logic;
+		reset : IN std_logic;
+		priority_rotation : IN std_logic_vector(4 downto 1);          
+		port_grant : OUT std_logic_vector(16 downto 1)
+		);
+	END COMPONENT;
+
+	Inst_Scheduler4_4: Scheduler4_4 PORT MAP(
+		Request => ,
+		Fifo_full => ,
+		clk => ,
+		reset => ,
+		priority_rotation => ,
+		port_grant => 
+	);
+
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Scheduler_summary.html
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Scheduler_summary.html	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Scheduler_summary.html	(revision 20)
@@ -0,0 +1,73 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>GENERIC_16_16 Project Status</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>GENERIC_16_16.ise</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>New</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>Scheduler</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc3s1200e-4fg320</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 11.1</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD>Xilinx Default (unlocked)</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 06/19/2011 - 14:29:40</center>
+</BODY></HTML>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Test_fifo.wcfg
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Test_fifo.wcfg	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/Test_fifo.wcfg	(revision 20)
@@ -0,0 +1,98 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="C:/Core MPI/SWITCH_GENERIC_16_16/testbench_isim_beh.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="coretypes" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="testbench" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="20" />
+   <wvobject fp_name="/testbench/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/fifo_empty" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">fifo_empty</obj_property>
+      <obj_property name="ObjectShortName">fifo_empty</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/pipo" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">pipo</obj_property>
+      <obj_property name="ObjectShortName">pipo</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/fifo_full" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">fifo_full</obj_property>
+      <obj_property name="ObjectShortName">fifo_full</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/push" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">push</obj_property>
+      <obj_property name="ObjectShortName">push</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/pop" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">pop</obj_property>
+      <obj_property name="ObjectShortName">pop</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/data_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_in[7:0]</obj_property>
+      <obj_property name="ObjectShortName">data_in[7:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/data_out" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_out[7:0]</obj_property>
+      <obj_property name="ObjectShortName">data_out[7:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/rec_pro/etrec" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">etrec</obj_property>
+      <obj_property name="ObjectShortName">etrec</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/rd_en_signal" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rd_en_signal</obj_property>
+      <obj_property name="ObjectShortName">rd_en_signal</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/rec_pro/pop" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">pop</obj_property>
+      <obj_property name="ObjectShortName">pop</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/ron" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ron</obj_property>
+      <obj_property name="ObjectShortName">ron</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/rdone" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rdone</obj_property>
+      <obj_property name="ObjectShortName">rdone</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/rack" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rack</obj_property>
+      <obj_property name="ObjectShortName">rack</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/son" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">son</obj_property>
+      <obj_property name="ObjectShortName">son</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/sdone" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdone</obj_property>
+      <obj_property name="ObjectShortName">sdone</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/sack" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sack</obj_property>
+      <obj_property name="ObjectShortName">sack</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/clk_period" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_period</obj_property>
+      <obj_property name="ObjectShortName">clk_period</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/msize" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">msize</obj_property>
+      <obj_property name="ObjectShortName">msize</obj_property>
+   </wvobject>
+</wave_config>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/_xmsgs/ibiswriter.xmsgs
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/_xmsgs/ibiswriter.xmsgs	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/_xmsgs/ibiswriter.xmsgs	(revision 20)
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="PostProcessors" num="123" delta="new" >Uppercase letters not recommended in file names.  Refer to the IBIS Specification (http://www.eigroup.org/ibis/ibis.htm) for allowed characters.  
+</msg>
+
+</messages>
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/_xmsgs/netgen.xmsgs
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/_xmsgs/netgen.xmsgs	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/_xmsgs/netgen.xmsgs	(revision 20)
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="NetListWriters" num="635" delta="old" >The generated VHDL netlist contains Xilinx <arg fmt="%s" index="1">SIMPRIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">SIMPRIM</arg> library for correct compilation and simulation. 
+</msg>
+
+<msg type="info" file="NetListWriters" num="0" delta="new" >Xilinx recommends running separate simulations to check for setup by specifying the MAX field in the SDF file and for hold by specifying the MIN field in the SDF file. Please refer to Simulator documentation for more details on specifying MIN and MAX field in the SDF.
+</msg>
+
+<msg type="info" file="NetListWriters" num="665" delta="old" >For more information on how to pass the SDF switches to the simulator, see your Simulator tool documentation.
+</msg>
+
+</messages>
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/compxlib.cfg
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/compxlib.cfg	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/compxlib.cfg	(revision 20)
@@ -0,0 +1,216 @@
+#*****************************************************************
+#   d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe configuration file - compxlib.cfg
+#   Fri Oct 07 10:37:42 2011
+#                                                                
+#   Important :-                                                 
+#       All options/variables must start from first column       
+#                                                                
+#*****************************************************************
+
+#
+RELEASE_VERSION:12.3
+#
+RELEASE_BUILD:M.70d
+#
+# set current simulator name
+SIMULATOR_NAME:mti_pe
+#
+# set current language name
+LANGUAGE_NAME:vhdl
+#
+# set compilation execution mode
+EXECUTE:on
+#
+# print compilation command template in log file
+LOG_CMD_TEMPLATE:off
+#
+# Hierarchical Output Directories
+HIER_OUT_DIR:off
+#
+# print Pre-Compiled library info
+PRECOMPILED_INFO:on
+#
+# create backup copy of setup files
+BACKUP_SETUP_FILES:on
+#
+# use enhanced compilation techniques for faster library compilation
+# (applicable to selected libraries only)
+FAST_COMPILE:on
+#
+# save compilation results to log file with the name specified with -log option
+ADD_COMPILATION_RESULTS_TO_LOG:on
+#
+# abort compilation process if errors are detected in the library
+ABORT_ON_ERROR:off
+#
+# compile library in the directory specified by the environment variable if the
+# -dir option is not specified
+OUTPUT_DIR_ENV:
+#
+#///////////////////////////////////////////////////////////////////////
+# Setup file name: ModelSim SE
+SET:mti_se:MODELSIM=modelsim.ini
+#
+# ModelSim SE options for VHDL Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vcom -work <library> <OPTION> <file_name>
+#
+OPTION:mti_se:vhdl:u:-source -93 -novopt -explicit
+OPTION:mti_se:vhdl:s:-source -93 -novopt -explicit
+OPTION:mti_se:vhdl:c:-source -93 -novopt -explicit
+OPTION:mti_se:vhdl:r:-source -93 -novopt -explicit
+OPTION:mti_se:vhdl:i:-source -93 -novopt -explicit
+OPTION:mti_se:vhdl:e:-93 -novopt -quiet -explicit
+#
+# ModelSim SE options for VERILOG Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vlog -work <library> <OPTION> <file_name>
+#
+OPTION:mti_se:verilog:u:-source -novopt
+OPTION:mti_se:verilog:s:-source -novopt
+OPTION:mti_se:verilog:n:-source -novopt
+OPTION:mti_se:verilog:c:-source -novopt
+OPTION:mti_se:verilog:r:-source -novopt
+OPTION:mti_se:verilog:i:-source -novopt
+OPTION:mti_se:verilog:e:-novopt -quiet
+#
+#///////////////////////////////////////////////////////////////////////
+# Setup file name: ModelSim PE
+SET:mti_pe:MODELSIM=modelsim.ini
+#
+# ModelSim PE options for VHDL Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vcom -work <library> <OPTION> <file_name>
+#
+OPTION:mti_pe:vhdl:u:-source -93 -explicit
+OPTION:mti_pe:vhdl:s:-source -93 -explicit
+OPTION:mti_pe:vhdl:c:-source -93 -explicit
+OPTION:mti_pe:vhdl:r:-source -93 -explicit
+OPTION:mti_pe:vhdl:i:-source -93 -explicit
+OPTION:mti_pe:vhdl:e:-93 -novopt -quiet -explicit
+#
+# ModelSim PE options for VERILOG Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vlog -work <library> <OPTION> <file_name>
+#
+OPTION:mti_pe:verilog:u:-source
+OPTION:mti_pe:verilog:s:-source
+OPTION:mti_pe:verilog:n:-source
+OPTION:mti_pe:verilog:c:-source
+OPTION:mti_pe:verilog:r:-source
+OPTION:mti_pe:verilog:i:-source
+OPTION:mti_pe:verilog:e:-novopt -quiet
+#
+#///////////////////////////////////////////////////////////////////////
+# Setup file name: ModelSim DE
+SET:mti_de:MODELSIM=modelsim.ini
+#
+# ModelSim DE options for VHDL Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vcom -work <library> <OPTION> <file_name>
+#
+OPTION:mti_de:vhdl:u:-source -93 -novopt -explicit
+OPTION:mti_de:vhdl:s:-source -93 -novopt -explicit
+OPTION:mti_de:vhdl:c:-source -93 -novopt -explicit
+OPTION:mti_de:vhdl:r:-source -93 -novopt -explicit
+OPTION:mti_de:vhdl:i:-source -93 -novopt -explicit
+OPTION:mti_de:vhdl:e:-93 -novopt -quiet -explicit
+#
+# ModelSim DE options for VERILOG Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vlog -work <library> <OPTION> <file_name>
+#
+OPTION:mti_de:verilog:u:-source -novopt
+OPTION:mti_de:verilog:s:-source -novopt
+OPTION:mti_de:verilog:n:-source -novopt
+OPTION:mti_de:verilog:c:-source -novopt
+OPTION:mti_de:verilog:r:-source -novopt
+OPTION:mti_de:verilog:i:-source -novopt
+OPTION:mti_de:verilog:e:-novopt -quiet
+#
+#///////////////////////////////////////////////////////////////////////
+# Setup file name: QuestaSim
+SET:questa:MODELSIM=modelsim.ini
+#
+# QuestaSim options for VHDL Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vcom -work <library> <OPTION> <file_name>
+#
+OPTION:questa:vhdl:u:-source -93 -novopt -explicit
+OPTION:questa:vhdl:s:-source -93 -novopt -explicit
+OPTION:questa:vhdl:c:-source -93 -novopt -explicit
+OPTION:questa:vhdl:r:-source -93 -novopt -explicit
+OPTION:questa:vhdl:i:-source -93 -novopt -explicit
+OPTION:questa:vhdl:e:-93 -novopt -quiet -explicit
+#
+# QuestaSim options for VERILOG Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vlog -work <library> <OPTION> <file_name>
+#
+OPTION:questa:verilog:u:-source -novopt
+OPTION:questa:verilog:s:-source -novopt
+OPTION:questa:verilog:n:-source -novopt
+OPTION:questa:verilog:c:-source -novopt
+OPTION:questa:verilog:r:-source -novopt
+OPTION:questa:verilog:i:-source -novopt
+OPTION:questa:verilog:e:-novopt -quiet
+#
+#///////////////////////////////////////////////////////////////////////
+# Setup file name: Aldec
+SET:riviera:LIBRARY=library.cfg
+#
+# Aldec options for VHDL Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vcom -work <library> <OPTION> <file_name>
+#
+OPTION:riviera:vhdl:u:-93 -quiet -nowarn ELAB1_0026
+OPTION:riviera:vhdl:s:-93 -quiet -nowarn ELAB1_0026
+OPTION:riviera:vhdl:c:-93 -quiet -nowarn ELAB1_0026
+OPTION:riviera:vhdl:r:-93 -quiet -nowarn ELAB1_0026
+OPTION:riviera:vhdl:i:-93 -quiet -nowarn ELAB1_0026
+OPTION:riviera:vhdl:e:-93 -quiet -nowarn ELAB1_0026
+#
+# Aldec options for VERILOG Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vlog -work <library> <OPTION> <file_name>
+#
+OPTION:riviera:verilog:u:-v2k5 -quiet -msg 0
+OPTION:riviera:verilog:s:-v2k5 -quiet -msg 0
+OPTION:riviera:verilog:n:-v2k5 -quiet -msg 0
+OPTION:riviera:verilog:c:-v2k5 -quiet -msg 0
+OPTION:riviera:verilog:r:-v2k5 -quiet -msg 0
+OPTION:riviera:verilog:i:-v2k5 -quiet -msg 0
+OPTION:riviera:verilog:e:-v2k5 -quiet -msg 0
+#///////////////////////////////////////////////////////////////////////
+# End
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/compxlib.log.bak
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/compxlib.log.bak	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/compxlib.log.bak	(revision 20)
@@ -0,0 +1,47 @@
+    ____  ____
+   /   /\/   /
+  /___/  \  /    VENDOR      : Xilinx Inc.
+  \   \   \/     VERSION     : 12.3 (M.70d)
+   \   \         APPLICATION : d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe
+   /   /         CONTENTS    : Compilation Log
+  /___/   /\     FILENAME    : compxlib.log
+  \   \  /  \    
+   \___\/\___\
+
+Release 12.3 - d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe 12.3 (nt64)
+Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
+
+Processing command line ...
+Reading the compxlib configuration file - 'compxlib.cfg' ...
+WARNING:Compxlib - The legacy option '-exclude_deprecated' will be obsolete in version 13.1. Please use the option '-exclude_superseded' for the same.
+Library Source Paths => 'D:/Xilinx/12.3/ISE_DS/ISE d:/Xilinx/12.3/ISE_DS/ISE'
+Current Working Directory => 'C:\Core MPI\SWITCH_GENERIC_16_16'
+Compilation Mode = FAST
+Execute Mode = ON
+Scheduling library installation & compilation for architectures: virtex5
+
+Scheduling library installation & compilation for libraries: simprim unisim xilinxcorelib edk
+
+Signature:-
+------------------------------------------------------------------------------
+d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe -s mti_pe -l vhdl -source_lib D:/Xilinx/12.3/ISE_DS/ISE -arch virtex5 -lib unisim -lib simprim -lib xilinxcorelib -lib edk -exclude_deprecated -intstyle ise 
+------------------------------------------------------------------------------
+ERROR:Compxlib - COMPXLIB[sim]: Unable to automatically find executables for simulator 'mti_pe' from the following paths:
+    d:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64
+   d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64
+   D:\Xilinx\12.3\ISE_DS\PlanAhead\bin
+   D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64
+   D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64
+   D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64
+   D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64
+   D:\Xilinx\12.3\ISE_DS\common\bin\nt64
+   D:\Xilinx\12.3\ISE_DS\common\lib\nt64
+   C:\Program Files\Common Files\Microsoft Shared\Windows Live
+   C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live
+   C:\Windows\system32
+   C:\Windows
+   C:\Windows\System32\Wbem
+   C:\Windows\System32\WindowsPowerShell\v1.0\
+   C:\Program Files (x86)\Windows Live\Shared
+   C:\Program Files\Trend Micro\AMSP.
+Simulator 'mti_pe' is ignored.
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/conv.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/conv.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/conv.vhd	(revision 20)
@@ -0,0 +1,72 @@
+--	Package File Template
+--
+--	Purpose: This package defines supplemental types, subtypes, 
+--		 constants, and functions 
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package conversions is
+
+  
+ -- type <new_type> is
+  --  record
+    --    <type_name>        : std_logic_vector( 7 downto 0);
+      --  <type_name>        : std_logic;
+    --end record;
+
+-- Declare constants
+
+  --constant <constant_name>		: time := <time_unit> ns;
+  --constant <constant_name>		: integer := <value>;
+ 
+-- Declare functions and procedure
+
+  function to_uint ( a: in std_ulogic_vector) return integer;
+  function to_vector (size: integer; val: integer) return std_ulogic_vector;
+  
+end conversions;
+
+
+package body conversions is
+  
+    -- Convert a std_ulogic_vector to an unsigned integer
+    --
+    function to_uint (a: std_ulogic_vector) return integer is
+        alias av: std_ulogic_vector (1 to a'length) is a;
+        variable val: integer := 0;
+        variable b: integer := 1;
+    begin
+        for i in a'length downto 1 loop
+            if (av(i) = '1') then    -- if LSB is '1',
+                val := val + b;       -- add value for current bit position
+            end if;
+            b := b * 2;    -- Shift left 1 bit
+        end loop;
+ 
+        return val;
+    end to_uint;
+ 
+-------------------------------------------------------- 
+    -- Convert an integer to a std_ulogic_vector
+    --
+    function to_vector (size: integer; val: integer) return std_ulogic_vector is
+        variable vec: std_ulogic_vector (1 to size);
+        variable a: integer;
+    begin
+        a := val;
+        for i in size downto 1 loop
+            if ((a mod 2) = 1) then
+                vec(i) := '1';
+            else 
+                vec(i) := '0';
+            end if;
+            a := a / 2;
+        end loop;
+        return vec;
+    end to_vector;
+ 
+
+ 
+end conversions;
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/conversions_vhdl.prj
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/conversions_vhdl.prj	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/conversions_vhdl.prj	(revision 20)
@@ -0,0 +1,1 @@
+vhdl work "C:\Core MPI\SWITCH_GENERIC_16_16\conv.vhd"
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/FIFO_256_FWFT.xreport
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/FIFO_256_FWFT.xreport	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/FIFO_256_FWFT.xreport	(revision 20)
@@ -0,0 +1,217 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+  <DateModified>2012-10-24T11:30:47</DateModified>
+  <ModuleName>testbench</ModuleName>
+  <SummaryTimeStamp>2012-10-24T11:26:11</SummaryTimeStamp>
+  <SavedFilePath>C:/Core MPI/SWITCH_GENERIC_16_16/iseconfig/FIFO_256_FWFT.xreport</SavedFilePath>
+  <ImplementationReportsDirectory>C:/Core MPI/SWITCH_GENERIC_16_16</ImplementationReportsDirectory>
+  <DateInitialized>2012-10-24T11:30:47</DateInitialized>
+  <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+  <viewgroup label="Design Overview" >
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="testbench_summary.html" label="Summary" >
+    <toc-item title="Design Overview" target="Design Overview" />
+    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+    <toc-item title="Performance Summary" target="Performance Summary" />
+    <toc-item title="Failing Constraints" target="Failing Constraints" />
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="testbench_envsettings.html" label="System Settings" />
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="testbench_map.xrpt" label="IOB Properties" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="testbench_map.xrpt" label="Control Set Information" />
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="testbench_map.xrpt" label="Module Level Utilization" />
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="testbench.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="testbench_par.xrpt" label="Pinout Report" />
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="testbench_par.xrpt" label="Clock Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="testbench.twx" label="Static Timing" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="testbench_html/fit/report.htm" label="CPLD Fitter Report" />
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="testbench_html/tim/report.htm" label="CPLD Timing Report" />
+  </viewgroup>
+  <viewgroup label="XPS Errors and Warnings" >
+   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+   <view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" />
+   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+  </viewgroup>
+  <viewgroup label="XPS Reports" >
+   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+   <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
+   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="testbench.log" label="System Log File" />
+  </viewgroup>
+  <viewgroup label="Errors and Warnings" >
+   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
+   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
+  </viewgroup>
+  <viewgroup label="Detailed Reports" >
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="testbench.syr" label="Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
+    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
+    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
+    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
+    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
+    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
+    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
+    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
+    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
+    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
+    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
+    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
+    <toc-item title="Partition Report" target="   Partition Report     " />
+    <toc-item title="Final Report" target="   Final Report   " />
+    <toc-item title="Design Summary" target="   Design Summary   " />
+    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
+    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
+    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
+    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
+    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
+    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
+    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
+    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
+    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
+   </view>
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.srr" label="Synplify Report" />
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.prec_log" label="Precision Report" />
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="testbench.bld" label="Translation Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Command Line" target="Command Line:" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+   </view>
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="testbench_map.mrp" label="Map Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
+    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
+    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
+    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
+    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
+    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
+    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
+    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
+    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
+    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
+    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
+    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
+    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="testbench.par" label="Place and Route Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+    <toc-item title="Router Information" target="Starting Router" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Clock Report" target="Generating Clock Report" />
+    <toc-item title="Timing Results" target="Timing Score:" />
+    <toc-item title="Final Summary" target="Peak Memory Usage:" />
+   </view>
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="testbench.twr" label="Post-PAR Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.rpt" label="CPLD Fitter Report (Text)" >
+    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
+    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
+    <toc-item title="Pin Resources" target="** Pin Resources **" />
+    <toc-item title="Global Resources" target="** Global Control Resources **" />
+   </view>
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.tim" label="CPLD Timing Report (Text)" >
+    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
+    <toc-item title="Performance Summary" target="Performance Summary:" />
+   </view>
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="testbench.pwr" label="Power Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Power summary" target="Power summary" />
+    <toc-item title="Thermal summary" target="Thermal summary" />
+   </view>
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="testbench.bgn" label="Bitgen Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+    <toc-item title="Final Summary" target="DRC detected" />
+   </view>
+  </viewgroup>
+  <viewgroup label="Secondary Reports" >
+   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/testbench_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/testbench_translate.nlf" label="Post-Translate Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="testbench_map.map" label="Map Log File" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Design Information" target="Design Information" />
+    <toc-item title="Design Summary" target="Design Summary" />
+   </view>
+   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_preroute.twr" label="Post-Map Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/testbench_map.nlf" label="Post-Map Simulation Model Report" />
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_map.psr" label="Physical Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="testbench_pad.txt" label="Pad Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="testbench.unroutes" label="Unroutes Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_preroute.tsi" label="Post-Map Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.grf" label="Guide Results Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.dly" label="Asynchronous Delay Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.clk_rgn" label="Clock Region Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.tsi" label="Post-Place and Route Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/testbench_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_sta.nlf" label="Primetime Netlist Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="testbench.ibs" label="IBIS Model" >
+    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
+    <toc-item title="Component" target="Component " />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.lck" label="Back-annotate Pin Report" >
+    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
+    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.lpc" label="Locked Pin Constraints" >
+    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
+    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+   </view>
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/testbench_timesim.nlf" label="Post-Fit Simulation Model Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+  </viewgroup>
+ </body>
+</report-views>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/GENERIC_16_16.projectmgr
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/GENERIC_16_16.projectmgr	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/GENERIC_16_16.projectmgr	(revision 20)
@@ -0,0 +1,691 @@
+<?xml version='1.0' encoding='utf-8'?>
+<!--This is an ISE project configuration file.-->
+<!--It holds project specific layout data for the projectmgr plugin.-->
+<!--Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.-->
+<Project version="2" owner="projectmgr" name="GENERIC_16_16" >
+   <!--This is an ISE project configuration file.-->
+   <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
+      <ClosedNodes>
+         <ClosedNodesVersion>2</ClosedNodesVersion>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT11_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT12_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT13_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT14_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT14_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT15_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT15_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT1_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description/OUTPUT_PORT_FIFO - FIFO_256_FWFT - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT2_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT2_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT3_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT3_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT4_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT5_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT5_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT6_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT6_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT7_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT7_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT8_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT9_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORTx16_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORTx16_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORTx4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORTx8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORTx9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler10_10 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler11_11 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler12_12 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler13_13 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler14_14 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler15_15 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler16_16 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler3_3 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler4_4 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler5_5 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler6_6 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler7_7 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler8_8 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler9_9 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar10_10 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar11_11 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar12_12 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar13_13 - Crossbar - Behavioral</ClosedNode>
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+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler16_16 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler14_14 - Scheduler14_14 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler15_15 - Scheduler15_15 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler16_16 - Scheduler16_16 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler10_10 - Scheduler10_10 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler11_11 - Scheduler11_11 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler12_12 - Scheduler12_12 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler13_13 - Scheduler13_13 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler14_14 - Scheduler14_14 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler15_15 - Scheduler15_15 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler16_16 - Scheduler16_16 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler2_2 - Scheduler2_2 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler3_3 - Scheduler3_3 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler4_4 - Scheduler4_4 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler5_5 - Scheduler5_5 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler6_6 - Scheduler6_6 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler7_7 - Scheduler7_7 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler8_8 - Scheduler8_8 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler9_9 - Scheduler9_9 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler3_3 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler4_4 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler5_5 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler6_6 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler7_7 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler8_8 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler9_9 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar10_10 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar11_11 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar12_12 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar13_13 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar14_14 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar15_15 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar16_16 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar2_2 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar3_3 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar4_4 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar5_5 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar6_6 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar7_7 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar8_8 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar9_9 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT11_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT12_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT13_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT14_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT14_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT15_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT15_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT16_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT16_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT1_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT2_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT2_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT3_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT3_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT4_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT5_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT5_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT6_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT6_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT7_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT7_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT8_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT9_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler10_10 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler11_11 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler12_12 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler13_13 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler14_14 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler15_15 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler16_16 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler10_10 - Scheduler10_10 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler11_11 - Scheduler11_11 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler12_12 - Scheduler12_12 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler13_13 - Scheduler13_13 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler14_14 - Scheduler14_14 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler15_15 - Scheduler15_15 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler16_16 - Scheduler16_16 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler2_2 - Scheduler2_2 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler3_3 - Scheduler3_3 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler4_4 - Scheduler4_4 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler5_5 - Scheduler5_5 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler6_6 - Scheduler6_6 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler7_7 - Scheduler7_7 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler8_8 - Scheduler8_8 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler9_9 - Scheduler9_9 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler3_3 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler10_10 - Scheduler10_10 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler11_11 - Scheduler11_11 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler12_12 - Scheduler12_12 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler13_13 - Scheduler13_13 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler14_14 - Scheduler14_14 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler15_15 - Scheduler15_15 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler16_16 - Scheduler16_16 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler2_2 - Scheduler2_2 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler3_3 - Scheduler3_3 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler4_4 - Scheduler4_4 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler5_5 - Scheduler5_5 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler6_6 - Scheduler6_6 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler7_7 - Scheduler7_7 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler8_8 - Scheduler8_8 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler9_9 - Scheduler9_9 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler5_5 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler6_6 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler7_7 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler8_8 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler9_9 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar10_10 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar11_11 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar12_12 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar13_13 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar14_14 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar15_15 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar16_16 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar2_2 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar3_3 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar4_4 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar5_5 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar6_6 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar7_7 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar8_8 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar9_9 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Xilinx|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd</ClosedNode>
+         <ClosedNode>/conversions C:|Core MPI|SWITCH_GENERIC_16_16|conv.vhd</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT14_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT15_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT1_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT2_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT2_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT3_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT3_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT4_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT5_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT6_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT7_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT8_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT9_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORTx16_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORTx16_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORTx4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORTx8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORTx9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler10_10 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler11_11 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler12_12 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler13_13 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler14_14 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler15_15 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler10_10 - Scheduler10_10 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler11_11 - Scheduler11_11 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler12_12 - Scheduler12_12 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler13_13 - Scheduler13_13 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler14_14 - Scheduler14_14 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler15_15 - Scheduler15_15 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler16_16 - Scheduler16_16 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler2_2 - Scheduler2_2 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler3_3 - Scheduler3_3 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler4_4 - Scheduler4_4 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler5_5 - Scheduler5_5 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler6_6 - Scheduler6_6 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler7_7 - Scheduler7_7 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler8_8 - Scheduler8_8 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler9_9 - Scheduler9_9 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler2_2 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler3_3 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler4_4 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler5_5 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler6_6 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler7_7 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler10_10 - Scheduler10_10 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler11_11 - Scheduler11_11 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler12_12 - Scheduler12_12 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler13_13 - Scheduler13_13 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler14_14 - Scheduler14_14 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler15_15 - Scheduler15_15 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler16_16 - Scheduler16_16 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler2_2 - Scheduler2_2 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler3_3 - Scheduler3_3 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler4_4 - Scheduler4_4 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler5_5 - Scheduler5_5 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler6_6 - Scheduler6_6 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler7_7 - Scheduler7_7 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler8_8 - Scheduler8_8 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler9_9 - Scheduler9_9 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler9_9 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar10_10 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar11_11 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar12_12 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar13_13 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar14_14 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar15_15 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar16_16 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar2_2 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar3_3 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar4_4 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar5_5 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar6_6 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar7_7 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar8_8 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar9_9 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT11_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT12_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT13_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
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+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Scheduler7_7 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Scheduler8_8 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Scheduler9_9 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar10_10 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar11_11 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar12_12 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar13_13 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar14_14 - Crossbar - Behavioral</ClosedNode>
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+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar16_16 - Crossbar - Behavioral</ClosedNode>
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+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar6_6 - Crossbar - Behavioral</ClosedNode>
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+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar9_9 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Documents and Settings|user|Mes documents|These|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral</ClosedNode>
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+      </ClosedNodes>
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+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
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+         <SelectedItem>Simulate Behavioral Model</SelectedItem>
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+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
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+   </ItemView>
+   <ItemView engineview="PostRouteSim" sourcetype="" guiview="Process" >
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+      </ClosedNodes>
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+   </ItemView>
+   <ItemView engineview="PostTransSim" guiview="Source" compilemode="AutoCompile" >
+      <ClosedNodes>
+         <ClosedNodesVersion>2</ClosedNodesVersion>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Structure</ClosedNode>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem>Unassigned User Library Modules</SelectedItem>
+      </SelectedItems>
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+      <CurrentItem>Unassigned User Library Modules</CurrentItem>
+   </ItemView>
+   <ItemView engineview="PostTransSim" sourcetype="" guiview="Process" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
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+         <SelectedItem>Compile HDL Simulation Libraries</SelectedItem>
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+   </ItemView>
+   <ItemView engineview="PostTransSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
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+         <ClosedNodesVersion>1</ClosedNodesVersion>
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+   </ItemView>
+   <ItemView engineview="PostMapSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
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+         <ClosedNodesVersion>1</ClosedNodesVersion>
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+         <SelectedItem/>
+      </SelectedItems>
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+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem/>
+   </ItemView>
+</Project>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/SWITCH_GEN.xreport
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/SWITCH_GEN.xreport	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/SWITCH_GEN.xreport	(revision 20)
@@ -0,0 +1,217 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+  <DateModified>2012-10-22T15:05:29</DateModified>
+  <ModuleName>FIFO_256_FWFT</ModuleName>
+  <SummaryTimeStamp>2012-07-18T16:27:43</SummaryTimeStamp>
+  <SavedFilePath>C:/Core MPI/SWITCH_GENERIC_16_16/iseconfig/SWITCH_GEN.xreport</SavedFilePath>
+  <ImplementationReportsDirectory>C:/Core MPI/SWITCH_GENERIC_16_16\</ImplementationReportsDirectory>
+  <DateInitialized>2012-10-22T15:05:29</DateInitialized>
+  <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+  <viewgroup label="Design Overview" >
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="FIFO_256_FWFT_summary.html" label="Summary" >
+    <toc-item title="Design Overview" target="Design Overview" />
+    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+    <toc-item title="Performance Summary" target="Performance Summary" />
+    <toc-item title="Failing Constraints" target="Failing Constraints" />
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="FIFO_256_FWFT_envsettings.html" label="System Settings" />
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="FIFO_256_FWFT_map.xrpt" showConstraints="0" label="IOB Properties" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="FIFO_256_FWFT_map.xrpt" label="Control Set Information" />
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="FIFO_256_FWFT_map.xrpt" label="Module Level Utilization" />
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="FIFO_256_FWFT.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="FIFO_256_FWFT_par.xrpt" label="Pinout Report" />
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="FIFO_256_FWFT_par.xrpt" label="Clock Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="FIFO_256_FWFT.twx" label="Static Timing" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="FIFO_256_FWFT_html/fit/report.htm" label="CPLD Fitter Report" />
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="FIFO_256_FWFT_html/tim/report.htm" label="CPLD Timing Report" />
+  </viewgroup>
+  <viewgroup label="XPS Errors and Warnings" >
+   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+   <view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" />
+   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+  </viewgroup>
+  <viewgroup label="XPS Reports" >
+   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+   <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
+   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="FIFO_256_FWFT.log" label="System Log File" />
+  </viewgroup>
+  <viewgroup label="Errors and Warnings" >
+   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
+   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
+  </viewgroup>
+  <viewgroup label="Detailed Reports" >
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="FIFO_256_FWFT.syr" label="Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
+    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
+    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
+    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
+    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
+    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
+    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
+    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
+    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
+    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
+    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
+    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
+    <toc-item title="Partition Report" target="   Partition Report     " />
+    <toc-item title="Final Report" target="   Final Report   " />
+    <toc-item title="Design Summary" target="   Design Summary   " />
+    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
+    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
+    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
+    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
+    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
+    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
+    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
+    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
+    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
+   </view>
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="FIFO_256_FWFT.srr" label="Synplify Report" />
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="FIFO_256_FWFT.prec_log" label="Precision Report" />
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="FIFO_256_FWFT.bld" label="Translation Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Command Line" target="Command Line:" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+   </view>
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="FIFO_256_FWFT_map.mrp" label="Map Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
+    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
+    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
+    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
+    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
+    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
+    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
+    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
+    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
+    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
+    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
+    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
+    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="FIFO_256_FWFT.par" label="Place and Route Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+    <toc-item title="Router Information" target="Starting Router" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Clock Report" target="Generating Clock Report" />
+    <toc-item title="Timing Results" target="Timing Score:" />
+    <toc-item title="Final Summary" target="Peak Memory Usage:" />
+   </view>
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="FIFO_256_FWFT.twr" label="Post-PAR Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="FIFO_256_FWFT.rpt" label="CPLD Fitter Report (Text)" >
+    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
+    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
+    <toc-item title="Pin Resources" target="** Pin Resources **" />
+    <toc-item title="Global Resources" target="** Global Control Resources **" />
+   </view>
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="FIFO_256_FWFT.tim" label="CPLD Timing Report (Text)" >
+    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
+    <toc-item title="Performance Summary" target="Performance Summary:" />
+   </view>
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="FIFO_256_FWFT.pwr" label="Power Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Power summary" target="Power summary" />
+    <toc-item title="Thermal summary" target="Thermal summary" />
+   </view>
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="FIFO_256_FWFT.bgn" label="Bitgen Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+    <toc-item title="Final Summary" target="DRC detected" />
+   </view>
+  </viewgroup>
+  <viewgroup label="Secondary Reports" >
+   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/FIFO_256_FWFT_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/FIFO_256_FWFT_translate.nlf" label="Post-Translate Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="FIFO_256_FWFT_map.map" label="Map Log File" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Design Information" target="Design Information" />
+    <toc-item title="Design Summary" target="Design Summary" />
+   </view>
+   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT_preroute.twr" label="Post-Map Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/FIFO_256_FWFT_map.nlf" label="Post-Map Simulation Model Report" />
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT_map.psr" label="Physical Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="FIFO_256_FWFT_pad.txt" label="Pad Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="FIFO_256_FWFT.unroutes" label="Unroutes Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT_preroute.tsi" label="Post-Map Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT.grf" label="Guide Results Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT.dly" label="Asynchronous Delay Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT.clk_rgn" label="Clock Region Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT.tsi" label="Post-Place and Route Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/FIFO_256_FWFT_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT_sta.nlf" label="Primetime Netlist Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT.ibs" label="IBIS Model" >
+    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
+    <toc-item title="Component" target="Component " />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT.lck" label="Back-annotate Pin Report" >
+    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
+    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT.lpc" label="Locked Pin Constraints" >
+    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
+    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+   </view>
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/FIFO_256_FWFT_timesim.nlf" label="Post-Fit Simulation Model Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+  </viewgroup>
+ </body>
+</report-views>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/SWITCH_GENERIQUE.xreport
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/SWITCH_GENERIQUE.xreport	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/SWITCH_GENERIQUE.xreport	(revision 20)
@@ -0,0 +1,181 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="1.7" >
+ <header>
+  <DateModified>2011-11-19T23:52:40</DateModified>
+  <ModuleName>SWITCH_GEN</ModuleName>
+  <SummaryTimeStamp>2011-11-19T23:36:21</SummaryTimeStamp>
+  <DateInitialized>2011-11-19T23:52:40</DateInitialized>
+  <ImplementationReportsDirectory>C:/Core MPI/SWITCH_GENERIC_16_16\</ImplementationReportsDirectory>
+  <SavedFilePath>C:/Core MPI/SWITCH_GENERIC_16_16/iseconfig/SWITCH_GENERIQUE.xreport</SavedFilePath>
+  <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+  <viewgroup label="Design Overview" >
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="SWITCH_GEN_summary.html" label="Summary" >
+    <toc-item title="Design Overview" target="Design Overview" />
+    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+    <toc-item title="Performance Summary" target="Performance Summary" />
+    <toc-item title="Failing Constraints" target="Failing Constraints" />
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY,EDK_OFF" hidden="true" type="HTML" file="SWITCH_GEN_partitions.html" label="Partition Report" >
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="SWITCH_GEN_map.xrpt" label="IOB Properties" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="SWITCH_GEN_map.xrpt" label="Control Set Information" />
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="SWITCH_GEN_map.xrpt" label="Module Level Utilization" />
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="SWITCH_GEN.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="SWITCH_GEN_par.xrpt" label="Pinout Report" />
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="SWITCH_GEN_par.xrpt" label="Clock Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="SWITCH_GEN.twx" label="Static Timing" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/fit/report.htm" label="CPLD Fitter Report" />
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/tim/report.htm" label="CPLD Timing Report" />
+  </viewgroup>
+  <viewgroup label="XPS Errors and Warnings" >
+   <view program="platgen" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+   <view program="libgen" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/libgen.xmsgs" label="Libgen Messages" />
+   <view program="simgen" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+   <view program="bitinit" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+  </viewgroup>
+  <viewgroup label="XPS Reports" >
+   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="../platgen.log" label="Platgen Log File" />
+   <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="../libgen.log" label="Libgen Log File" />
+   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="../simgen.log" label="Simgen Log File" />
+   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="../bitinit.log" label="BitInit Log File" />
+  </viewgroup>
+  <viewgroup label="Errors and Warnings" >
+   <view inputState="Unknown" program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+   <view inputState="Synthesized" program="ngdbuild" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+   <view inputState="Current" program="implementation" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Current Messages" />
+   <view inputState="Current" program="fitting" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Current Messages (CPLD)" />
+  </viewgroup>
+  <viewgroup label="Detailed Reports" >
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="SWITCH_GEN.syr" label="Synthesis Report" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
+    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
+    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
+    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
+    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
+    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " />
+    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
+    <toc-item title="Partition Report" target="   Partition Report     " />
+    <toc-item title="Final Report" target="   Final Report   " />
+   </view>
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.srr" label="Synplify Report" />
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.prec_log" label="Precision Report" />
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="SWITCH_GEN.bld" label="Translation Report" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Command Line" target="Command Line:" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+   </view>
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN_map.mrp" label="Map Report" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Section 1: Errors" target="Section 1 - " />
+    <toc-item title="Section 2: Warnings" target="Section 2 - " />
+    <toc-item title="Section 3: Infos" target="Section 3 - " />
+    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 - " />
+    <toc-item title="Section 5: Removed Logic" target="Section 5 - " />
+    <toc-item title="Section 6: IOB Properties" target="Section 6 - " />
+    <toc-item title="Section 7: RPMs" target="Section 7 - " />
+    <toc-item title="Section 8: Guide Report" target="Section 8 - " />
+    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 - " />
+    <toc-item title="Section 10: Modular Design Summary" target="Section 10 - " />
+    <toc-item title="Section 11: Timing Report" target="Section 11 - " />
+    <toc-item title="Section 12: Configuration String Details" target="Section 12 - " />
+    <toc-item title="Section 13: Control Set Information" target="Section 13 - " />
+    <toc-item title="Section 14: Utilization by Hierarchy" target="Section 14 - " />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.par" label="Place and Route Report" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+    <toc-item title="Router Information" target="Starting Router" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Clock Report" target="Generating Clock Report" />
+    <toc-item title="Timing Results" target="Timing Score:" />
+    <toc-item title="Final Summary" target="Peak Memory Usage:" />
+   </view>
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.twr" label="Post-PAR Static Timing Report" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Data Sheet Report" target="Data Sheet" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+   </view>
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.rpt" label="CPLD Fitter Report (Text)" >
+    <toc-item title="Top of Report" target="cpldfit:" />
+    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
+    <toc-item title="Pin Resources" target="** Pin Resources **" />
+    <toc-item title="Global Resources" target="** Global Control Resources **" />
+   </view>
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.tim" label="CPLD Timing Report (Text)" >
+    <toc-item title="Top of Report" target="Performance Summary Report" />
+    <toc-item title="Performance Summary" target="Performance Summary:" />
+   </view>
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="SWITCH_GEN.pwr" label="Power Report" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Power summary" target="Power summary" />
+    <toc-item title="Thermal summary" target="Thermal summary" />
+   </view>
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.bgn" label="Bitgen Report" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+    <toc-item title="Final Summary" target="DRC detected" />
+   </view>
+  </viewgroup>
+  <viewgroup label="Secondary Reports" >
+   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/SWITCH_GEN_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/SWITCH_GEN_translate.nlf" label="Post-Translate Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN_map.map" label="Map Log File" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Design Information" target="Design Information" />
+    <toc-item title="Design Summary" target="Design Summary" />
+   </view>
+   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.twr" label="Post-Map Static Timing Report" />
+   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/SWITCH_GEN_map.nlf" label="Post-Map Simulation Model Report" />
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_map.psr" label="Physical Synthesis Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="SWITCH_GEN_pad.txt" label="Pad Report" >
+    <toc-item title="Top of Report" target="Release" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN.unroutes" label="Unroutes Report" >
+    <toc-item title="Top of Report" target="Release" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.grf" label="Guide Results Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.dly" label="Asynchronous Delay Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.clk_rgn" label="Clock Region Report" />
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/SWITCH_GEN_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_sta.nlf" label="Primetime Netlist Report" >
+    <toc-item title="Top of Report" target="Release" />
+   </view>
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.ibs" label="IBIS Model" >
+    <toc-item title="Top of Report" target="IBIS Models for" />
+    <toc-item title="Component" target="Component " />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lck" label="Back-annotate Pin Report" >
+    <toc-item title="Top of Report" target="pin2ucf Report File" />
+    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lpc" label="Locked Pin Constraints" >
+    <toc-item title="Top of Report" target="top.lpc" />
+    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+   </view>
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/SWITCH_GEN_timesim.nlf" label="Post-Fit Simulation Model Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+  </viewgroup>
+ </body>
+</report-views>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/testbench.xreport
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/testbench.xreport	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/iseconfig/testbench.xreport	(revision 20)
@@ -0,0 +1,217 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+  <DateModified>2012-11-29T18:08:12</DateModified>
+  <ModuleName>testbench</ModuleName>
+  <SummaryTimeStamp>Unknown</SummaryTimeStamp>
+  <SavedFilePath>C:/Core MPI/SWITCH_GENERIC_16_16/iseconfig/testbench.xreport</SavedFilePath>
+  <ImplementationReportsDirectory>C:/Core MPI/SWITCH_GENERIC_16_16\</ImplementationReportsDirectory>
+  <DateInitialized>2012-10-24T12:13:41</DateInitialized>
+  <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+  <viewgroup label="Design Overview" >
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="testbench_summary.html" label="Summary" >
+    <toc-item title="Design Overview" target="Design Overview" />
+    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+    <toc-item title="Performance Summary" target="Performance Summary" />
+    <toc-item title="Failing Constraints" target="Failing Constraints" />
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="testbench_envsettings.html" label="System Settings" />
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="testbench_map.xrpt" label="IOB Properties" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="testbench_map.xrpt" label="Control Set Information" />
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="testbench_map.xrpt" label="Module Level Utilization" />
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="testbench.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="testbench_par.xrpt" label="Pinout Report" />
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="testbench_par.xrpt" label="Clock Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="testbench.twx" label="Static Timing" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="testbench_html/fit/report.htm" label="CPLD Fitter Report" />
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="testbench_html/tim/report.htm" label="CPLD Timing Report" />
+  </viewgroup>
+  <viewgroup label="XPS Errors and Warnings" >
+   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+   <view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" />
+   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+  </viewgroup>
+  <viewgroup label="XPS Reports" >
+   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+   <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
+   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="testbench.log" label="System Log File" />
+  </viewgroup>
+  <viewgroup label="Errors and Warnings" >
+   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
+   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
+  </viewgroup>
+  <viewgroup label="Detailed Reports" >
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="testbench.syr" label="Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
+    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
+    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
+    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
+    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
+    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
+    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
+    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
+    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
+    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
+    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
+    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
+    <toc-item title="Partition Report" target="   Partition Report     " />
+    <toc-item title="Final Report" target="   Final Report   " />
+    <toc-item title="Design Summary" target="   Design Summary   " />
+    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
+    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
+    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
+    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
+    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
+    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
+    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
+    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
+    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
+   </view>
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.srr" label="Synplify Report" />
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.prec_log" label="Precision Report" />
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="testbench.bld" label="Translation Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Command Line" target="Command Line:" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+   </view>
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="testbench_map.mrp" label="Map Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
+    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
+    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
+    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
+    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
+    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
+    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
+    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
+    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
+    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
+    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
+    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
+    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="testbench.par" label="Place and Route Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+    <toc-item title="Router Information" target="Starting Router" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Clock Report" target="Generating Clock Report" />
+    <toc-item title="Timing Results" target="Timing Score:" />
+    <toc-item title="Final Summary" target="Peak Memory Usage:" />
+   </view>
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="testbench.twr" label="Post-PAR Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.rpt" label="CPLD Fitter Report (Text)" >
+    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
+    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
+    <toc-item title="Pin Resources" target="** Pin Resources **" />
+    <toc-item title="Global Resources" target="** Global Control Resources **" />
+   </view>
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.tim" label="CPLD Timing Report (Text)" >
+    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
+    <toc-item title="Performance Summary" target="Performance Summary:" />
+   </view>
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="testbench.pwr" label="Power Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Power summary" target="Power summary" />
+    <toc-item title="Thermal summary" target="Thermal summary" />
+   </view>
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="testbench.bgn" label="Bitgen Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+    <toc-item title="Final Summary" target="DRC detected" />
+   </view>
+  </viewgroup>
+  <viewgroup label="Secondary Reports" >
+   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/testbench_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/testbench_translate.nlf" label="Post-Translate Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="testbench_map.map" label="Map Log File" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Design Information" target="Design Information" />
+    <toc-item title="Design Summary" target="Design Summary" />
+   </view>
+   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_preroute.twr" label="Post-Map Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/testbench_map.nlf" label="Post-Map Simulation Model Report" />
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_map.psr" label="Physical Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="testbench_pad.txt" label="Pad Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="testbench.unroutes" label="Unroutes Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_preroute.tsi" label="Post-Map Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.grf" label="Guide Results Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.dly" label="Asynchronous Delay Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.clk_rgn" label="Clock Region Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.tsi" label="Post-Place and Route Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/testbench_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_sta.nlf" label="Primetime Netlist Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="testbench.ibs" label="IBIS Model" >
+    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
+    <toc-item title="Component" target="Component " />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.lck" label="Back-annotate Pin Report" >
+    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
+    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.lpc" label="Locked Pin Constraints" >
+    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
+    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+   </view>
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/testbench_timesim.nlf" label="Post-Fit Simulation Model Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+  </viewgroup>
+ </body>
+</report-views>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/pepExtractor.prj
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/pepExtractor.prj	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/pepExtractor.prj	(revision 20)
@@ -0,0 +1,1 @@
+work	"C:/Core MPI/SWITCH_GENERIC_16_16//OUTPUT_PORT_MODULE.vhd"
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/pinlock.rpt
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/pinlock.rpt	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/pinlock.rpt	(revision 20)
@@ -0,0 +1,53 @@
+
+		pin2ucf Report File
+Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
+	   Created : Fri Feb 10 18:11:10 2012
+
+
+
+Constraint Conflicts Information
+================================
+
+   This section provides information on the constraint conflicts 
+   if pin2ucf were to write a ucf file using the provided design and
+   the existing ucf file. There are 2 types of conflicts that can
+   occur.
+
+   1. Multiple pins could be constrained on the same net
+   2. Same pin could have multiple nets 
+
+   pin2ucf provides a list each for both.
+
+   Note:- "New NET" and "New PIN" indicates the Net and Pin
+   locations found suitable by pin2ucf for pin locking, while
+   "Old Net" and "Old PIN" indicates the Net and Pin locations
+   already set by the user in the ucf file, which were left 
+   untouched by pin2ucf.
+
+
+Net name conflicts on the pins
+-------------------------------
+
+
+----------------------------------------------------------------------
+PIN Location                           New NET              Old NET
+
+----------------------------------------------------------------------
+
+"No net name conflicts were found on pins"
+
+
+Pin name conflicts on the nets
+-------------------------------
+
+
+----------------------------------------------------------------------
+NET Name                               New PIN              Old PIN
+
+----------------------------------------------------------------------
+
+"No pin name conflicts were found on nets"
+
+
+PinLocking Successful. Constraints written to UCF File
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/proto_send.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/proto_send.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/proto_send.vhd	(revision 20)
@@ -0,0 +1,125 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    18:01:21 10/23/2012 
+-- Design Name: 
+-- Module Name:    proto_send - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use work.CoreTypes.all;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity proto_send is
+generic (sizemem : natural := 64);
+ port (
+ clk,reset : in std_logic;
+ fifo_empty,fifo_full : in std_logic;
+  push : out std_logic:='0';
+ fifo_in : out std_logic_vector(Word-1 downto 0);
+ snd_start : in std_logic; --début de la réception
+ snd_ack :in std_logic;   -- acquittement de la réception
+ snd_comp : out std_logic; -- fin de la réception
+ mem :in memory(0 to sizemem-1));
+
+end proto_send;
+
+architecture Behavioral of proto_send is
+type typ_send is (s_head,s_len,s_len2,s_data,s_pulse,s_end);
+ signal etsnd : typ_send;
+ signal sfifo_in : std_logic_vector(Word-1 downto 0);
+ signal spush : std_logic:='0';
+begin
+
+proc_send : process (clk,reset)
+variable dlen,i: natural range 0 to 255 :=0;
+	begin
+	if reset='1' then 
+				 etsnd<=s_head;
+				 
+				else  
+						if rising_edge(clk) then -- le process s'exécute sur chaque front 
+															-- montant de l'horloge
+						case etsnd is
+						when s_head  =>
+							sfifo_in<=mem(0);
+							snd_comp<='0';
+							i:=0;
+							
+							if fifo_empty='1' and snd_start='1' then
+							spush<='1';
+							snd_comp<='0';
+							etsnd<=s_len;
+							end if;
+						when s_pulse =>
+							spush<='1';
+							etsnd<=s_len;
+						when s_len  =>
+							sfifo_in<=mem(1); --8 données
+							i:=i+1;
+							dlen:=to_integer(unsigned(mem(i)));
+							spush<='1';
+							snd_comp<='0';
+							etsnd<=s_data;
+						when s_len2 =>
+							snd_comp<='0';
+								etsnd<=s_data;
+								
+						when s_data  =>
+								if fifo_full='0' then
+								i:=i+1;
+								sfifo_in<=mem(i);
+									if i=dlen-2 then
+										etsnd<=s_end;
+										snd_comp<='1';
+										spush<='1';
+									else
+										spush<='1';
+									end if;
+									
+								else
+								spush<='0';
+								end if;
+						
+						when s_end  =>
+								spush<='0';
+								etsnd<=s_head;
+								sfifo_in<=(others=>'-');
+								if snd_ack='1' then
+									etsnd<=s_head;
+								end if;
+						when others =>
+								spush<='0';
+								etsnd<=s_head;
+								sfifo_in<=(others=>'0');
+						end case;
+						end if;
+				end if;
+	end process;
+	
+	-- affectation concurentes
+	
+	push<=spush;
+	fifo_in<=sfifo_in;
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/scheduler2_2.stx
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/scheduler2_2.stx	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/scheduler2_2.stx	(revision 20)
@@ -0,0 +1,36 @@
+Release 11.1 - xst L.33 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
+--> Parameter TMPDIR set to C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 1.00 secs
+Total CPU time to Xst completion: 0.18 secs
+ 
+--> Parameter xsthdpdir set to C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst
+
+
+Total REAL time to Xst completion: 1.00 secs
+Total CPU time to Xst completion: 0.18 secs
+ 
+--> 
+=========================================================================
+*                          HDL Compilation                              *
+=========================================================================
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/Arbiter.vhd" in Library work.
+Architecture behavioral of Entity arbiter is up to date.
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/scheduler2_2.vhd" in Library work.
+Entity <scheduler2_2> compiled.
+Entity <scheduler2_2> (Architecture <behavioral>) compiled.
+
+
+Total REAL time to Xst completion: 1.00 secs
+Total CPU time to Xst completion: 0.34 secs
+ 
+--> 
+
+Total memory usage is 119772 kilobytes
+
+Number of errors   :    0 (   0 filtered)
+Number of warnings :    0 (   0 filtered)
+Number of infos    :    0 (   0 filtered)
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/scheduler2_2.xst
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/scheduler2_2.xst	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/scheduler2_2.xst	(revision 20)
@@ -0,0 +1,5 @@
+set -tmpdir "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst/projnav.tmp"
+set -xsthdpdir "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst"
+elaborate
+-ifn scheduler2_2.prj
+-ifmt mixed
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/stimuli1.v
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/stimuli1.v	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/stimuli1.v	(revision 20)
@@ -0,0 +1,50 @@
+-- GENERATEUR DE STIMILUS POUR LE TEST DU SWITCH CROSSBAR
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+
+entity stimuli45 is 
+port (clk : in std_logic;
+      reset : in std_logic;
+       wr_en : out std_logic;
+      data : out std_logic_vector(7 downto 0));
+end stimuli45;
+
+architecture behavioral of stimuli45 is
+type rom_type is array (69 downto 0) of std_logic_vector (7 downto 0);
+signal ROM : rom_type:= (
+						X"01", X"28", X"00" ,X"01" ,X"02" ,X"03" ,
+						X"04" ,X"05" ,X"06" ,X"07" ,X"08" ,X"09" ,
+						X"0a" ,X"0b" ,X"0c" ,X"0d" ,X"0e" ,X"0f" ,
+						X"10" ,X"11" ,X"12" ,X"13" ,X"14" ,X"15" ,
+						X"16" ,X"17" ,X"18" ,X"19" ,X"1a" ,X"1b" ,
+						X"1c" ,X"1d" ,X"1e" ,X"1f" ,X"20" ,X"21" ,
+						X"22" ,X"23" ,X"24" ,X"25" ,X"02", X"1e", 
+						X"00" ,X"01" ,X"02" ,X"03" ,X"04" ,X"05" ,
+						X"06" ,X"07" ,X"08" ,X"09" ,X"0a" ,X"0b" ,
+						X"0c" ,X"0d" ,X"0e" ,X"0f" ,X"10" ,X"11" ,
+						X"12" ,X"13" ,X"14" ,X"15" ,X"16" ,X"17" ,
+						X"18" ,X"19" ,X"1a" ,X"1b" );
+
+constant max_address : std_logic_vector(6 downto 0) :="1000101";
+signal address_counter : std_logic_vector(6 downto 0) := (others => '0');
+begin
+
+data <= ROM(conv_integer(address_counter));
+process (clk)
+  begin
+     if rising_edge(clk) then
+        if reset = '1' then
+            wr_en <='1';
+            address_counter <= (others=>'0');
+        elsif address_counter < max_address then
+             wr_en <='1';
+              address_counter <= address_counter +1;
+             else
+             wr_en <='0';
+             end if;
+    end if;
+  end process;
+end behavioral;
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/stimuli1.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/stimuli1.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/stimuli1.vhd	(revision 20)
@@ -0,0 +1,50 @@
+-- GENERATEUR DE STIMILUS POUR LE TEST DU SWITCH CROSSBAR
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+
+entity stimuli45 is 
+port (clk : in std_logic;
+      reset : in std_logic;
+       wr_en : out std_logic;
+      data : out std_logic_vector(7 downto 0));
+end stimuli45;
+
+architecture behavioral of stimuli45 is
+type rom_type is array (0 to 69) of std_logic_vector (7 downto 0);
+signal ROM : rom_type:= (
+						X"55", X"28", X"00" ,X"01" ,X"02" ,X"03" ,
+						X"04" ,X"05" ,X"06" ,X"07" ,X"08" ,X"09" ,
+						X"0a" ,X"0b" ,X"0c" ,X"0d" ,X"0e" ,X"0f" ,
+						X"10" ,X"11" ,X"12" ,X"13" ,X"14" ,X"15" ,
+						X"16" ,X"17" ,X"18" ,X"19" ,X"1a" ,X"1b" ,
+						X"1c" ,X"1d" ,X"1e" ,X"1f" ,X"20" ,X"21" ,
+						X"22" ,X"23" ,X"24" ,X"25" ,X"52", X"1e", 
+						X"00" ,X"01" ,X"02" ,X"03" ,X"04" ,X"05" ,
+						X"06" ,X"07" ,X"08" ,X"09" ,X"0a" ,X"0b" ,
+						X"0c" ,X"0d" ,X"0e" ,X"0f" ,X"10" ,X"11" ,
+						X"12" ,X"13" ,X"14" ,X"15" ,X"16" ,X"17" ,
+						X"18" ,X"19" ,X"1a" ,X"1b" );
+
+constant max_address : std_logic_vector(6 downto 0) :="1000101";
+signal address_counter : std_logic_vector(6 downto 0) := (others => '0');
+begin
+
+data <= ROM(conv_integer(address_counter));
+process (clk)
+  begin
+     if rising_edge(clk) then
+        if reset = '1' then
+            wr_en <='1';
+            address_counter <= (others=>'0');
+        elsif address_counter < max_address then
+             wr_en <='1';
+              address_counter <= address_counter +1;
+             else
+             wr_en <='0';
+             end if;
+    end if;
+  end process;
+end behavioral;
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_16x16_map.prj
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_16x16_map.prj	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_16x16_map.prj	(revision 20)
@@ -0,0 +1,2 @@
+vhdl work "netgen/map/SWITCH_GEN_map.vhd"
+vhdl work "test_xbar_8x8.vhd"
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_16x16_translate.prj
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_16x16_translate.prj	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_16x16_translate.prj	(revision 20)
@@ -0,0 +1,2 @@
+vhdl work "netgen/translate/SWITCH_GEN_translate.vhd"
+vhdl work "test_xbar_8x8.vhd"
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_8x8.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_8x8.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_8x8.vhd	(revision 20)
@@ -0,0 +1,716 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:	GAMOM NGOUNOU
+--
+-- Create Date:   19:03:05 07/11/2011
+-- Design Name:   
+-- Module Name:   C:/Xilinx/SWITCH_GENERIC_16_16/test_xbar_8x8.vhd
+-- Project Name:  GENERIC_16_16
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: SWITCH_GENERIQUE
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+--use IEEE.std_logic_textio.ALL;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+use work.Coretypes.all;
+
+
+ENTITY test_xbar_8x8 IS
+END test_xbar_8x8;
+ 
+ARCHITECTURE behavior OF test_xbar_8x8 IS 
+ CONSTANT MAXPORT :natural:=8; 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT SWITCH_GEN
+	 GENERIC (number_of_ports : positive := MAXPORT);
+    PORT(
+	      clk : IN  std_logic;
+			reset : IN  std_logic;
+			
+			Port_in : in typ_portIO(1 to MAXPORT) ;
+			Port_out : out  typ_portIO(1 to MAXPORT);
+
+         cmd_in_en : IN  std_logic_vector(MAXPORT downto 1);
+			data_in_en : IN  std_logic_vector(MAXPORT downto 1);
+			data_out_en : IN  std_logic_vector(MAXPORT downto 1);
+         fifo_in_full : OUT  std_logic_vector(MAXPORT downto 1);
+         fifo_in_empty : OUT  std_logic_vector(MAXPORT downto 1);
+         data_available : OUT  std_logic_vector(MAXPORT downto 1)
+         
+        );
+    END COMPONENT;
+    COMPONENT Stimport5
+	 port (
+			 clk : in std_logic;
+			 reset : in std_logic;
+			 clk_en : in std_logic;
+			 wr_en : out std_logic;
+			 data : out std_logic_vector (7 downto 0)
+			 );
+	 
+	 END COMPONENT;
+	type naturel is array (natural range <>) of natural  range 0 to 511; 
+	type typ_send is (s_head,s_len,s_len2,s_data,s_end);
+	type typ_receiv is (r_wait,r_head,r_dlen,r_glen,r_start,r_end);
+	type typ_cmd is (cmdstart,cmdpost,cmdpostidle,cmdread,cmdlen,cmdglen,cmddata,cmdend,cmdtimeout);
+
+		signal etsnd1,etsnd2,etsnd3 : typ_send;
+		signal etrec:typ_receiv;   --pour la machine à état de réception
+		signal etcmd :typ_cmd;     --pour la machine à état de commande
+   --Inputs
+  signal PortIn : Typ_portio (1 to MAXPORT);  
+  --Outputs
+	signal portOut : Typ_portio(1 to maxport);
+	
+   signal data_in_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
+	signal cmd_in_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
+   signal data_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
+	signal rdata_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
+	signal rcount : naturel(1 to MAXPORT) ;
+	
+	signal cdata_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
+   signal clk : std_logic := '0';
+   signal reset : std_logic := '0';
+	signal din1,din2,din3,din4: std_logic_vector(MAXPORT downto 1):= (others => '0');
+ 	--signaux utiliser pour la mise à jour des MAE
+	signal sdestport,rdestport,rorigport:natural range 0 to 15;
+	signal csend1,csend2,csend3,csend4:natural;
+	signal sorigport :natural range 0 to 15:=1;
+	
+
+   signal fifo_in_full : std_logic_vector(MAXPORT downto 1);
+   signal fifo_in_empty : std_logic_vector(MAXPORT downto 1);
+   signal data_available : std_logic_vector(MAXPORT downto 1);
+
+   -- Clock period definitions
+   constant clk_period : time := 10 ns;
+   -- autres signaux de simulation
+	-- ici nous mettons les signaux permettant de gérer le processus de simulation
+	signal time_out:std_logic_vector(8 downto 1);
+	signal header : std_logic_vector(7 downto 0);
+	signal tosend1,tosend2,tosend3,tosend4 : std_logic_vector(7 downto 0);
+	
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: SWITCH_GEN generic map (MAXPORT) PORT MAP (
+          Port_In  => PortIn,
+			 Port_Out =>PortOut,
+
+          --signaux de contrôle de la lecture des ports
+			 data_in_en => data_in_en,
+			 cmd_in_en =>cmd_in_en,
+          data_out_en => data_out_en,
+          fifo_in_full => fifo_in_full,
+          fifo_in_empty => fifo_in_empty,
+          data_available => data_available,
+          clk => clk,
+          reset => reset
+        );
+--Utilisation de la ROM pour envoyer des stimulis
+--stimport: stimport5 port map (clk,reset,not (fifo_in_full(5)),din3(5),port5_in);
+data_in_en<=din1 or din2 or din3 or din4;
+data_out_en<=rdata_out_en or cdata_out_en;					
+ -- Clock process definitions
+   clk_process :process
+   begin
+		clk <= '0';
+		wait for clk_period/2;
+		clk <= '1';
+		wait for clk_period/2;
+   end process;
+
+ init_process:process (reset)
+ 
+ variable i: natural range 0 to 15;
+ begin
+ if reset='1' then
+ for i in 1 to maxport
+	loop
+	--Portin(i)<=(others=>'0');
+end loop	;
+end if ;
+end process init_process;
+		psend1:process(clk,reset)
+		--génération des paquets à partir du premier port
+		variable pactype :natural range 0 to 15;
+		variable origport,destport : natural range 0 to 15;
+		variable datalen,i,i_pair : natural range 0 to 255;
+		
+		
+		
+				begin
+				if reset='1' then 
+				 etsnd1<=s_head;
+				 
+				else  --reset ='0'
+						origport:=6;
+						if rising_edge(clk) then -- le process s'exécute sur chaque front 
+															-- montant de l'horloge
+						case etsnd1 is
+						when s_head  =>    -- construction et envoie de l'en-tête
+						pactype:=5;-- fonction put
+						destport:=6; -- le port de destination
+						datalen :=4;
+						header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4));
+						 tosend1<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
+						 din1(origport)<='1';   -- en fait data_in_en(origport)
+						 i:=1;i_pair:=i /2;
+						 etsnd1<=s_len;  -- passer à l'état suivant
+						 --port1_in<=tosend1;
+						when s_len => 
+							--tosend1<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
+							tosend1<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
+						
+							din1(origport)<='1';
+
+							--port1_in<=tosend1; --copie directe sur le port 
+							etsnd1<=s_len2;
+						when s_len2 => 
+							tosend1<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
+							din1(origport)<='1';
+
+							--port1_in<=tosend1; --copie directe sur le port 
+							etsnd1<=s_data;	
+						when s_data =>
+							
+							if (fifo_in_full(origport)='0') then
+								din1(origport)<='1';
+								i_pair:=i_pair *2;
+								if i=i_pair then        -- modulo
+									tosend1<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
+									--port1_in<="00001101";  --origport=1
+								else
+									--tosend1<="00001111";
+									tosend1<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
+									--port1_in<="00001111";   --origport=1
+								end if;
+								i:=i+1;i_pair:=i / 2;
+								if i>datalen then
+									etsnd1<=s_end;
+									din1(origport)<='0';
+								end if;
+							else
+								din1(origport)<='1';
+							end if;
+						when s_end  =>
+						tosend1<="--------";
+							din1(origport)<='0';
+							if fifo_in_empty(origport)='1' then
+								etsnd1<=s_head;
+							else
+								etsnd1<=s_end;
+							end if;
+						end case;	
+						
+						end if;
+					 
+					
+						
+					end if; --reset='1'
+		end process psend1;
+		
+		Portin(6)<=tosend1 when reset='0';
+		Portin(2)<=tosend2 when reset='0';
+		Portin(4)<=tosend3 when reset='0';
+		Portin(1)<=tosend4 when reset='0';
+		psend2:process(clk,reset)
+		--génération des paquets à partir du premier port
+		variable pactype :natural range 0 to 15;
+		variable origport,destport : natural range 0 to 15;
+		variable datalen,i,i_pair : natural range 0 to 255;
+		
+		
+		
+				begin
+				if reset='1' then 
+				 etsnd2<=s_head;
+				 
+				else  --reset ='0'
+						origport:=2;
+						if rising_edge(clk) then -- le process s'exécute sur chaque front 
+															-- montant de l'horloge
+						case etsnd2 is
+						when s_head  =>    -- construction et envoie de l'en-tête
+						pactype:=5;-- fonction put
+						destport:=2; -- le port de destination
+						datalen :=9;
+						header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4));
+						 tosend2<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
+						 din2(origport)<='1';
+						 i:=1;i_pair:=i /2;
+						 etsnd2<=s_len;  -- passer à l'état suivant
+						 
+						when s_len => 
+							--tosend2<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
+							tosend2<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
+						
+							din2(origport)<='1';
+
+							--port2_in<=tosend2; --copie directe sur le port 
+							etsnd2<=s_len2;
+						when s_len2 => 
+							tosend2<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
+							din2(origport)<='1';
+
+							--port1_in<=tosend1; --copie directe sur le port 
+							etsnd2<=s_data;
+						when s_data =>
+							
+							if (fifo_in_full(origport)='0') then
+								din2(origport)<='1';
+								i_pair:=i_pair * 2;
+								if i=i_pair then        -- modulo
+									--tosend2<="00000001";
+									tosend2<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
+									--port2_in<="00000001";  --origport=1
+								else
+									--tosend2<="00000010";
+									tosend2<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
+									--port2_in<="00000001";   --origport=1
+								end if;
+								i:=i+1;i_pair:=i / 2;
+								if i>datalen then
+									etsnd2<=s_end;
+									din2(origport)<='0';
+								else
+									din2(origport)<='1';
+								end if;
+							else
+								din2(origport)<='0';
+							end if;
+						when s_end  =>
+							tosend2<="--------";
+							din2(origport)<='0';
+							if fifo_in_empty(origport)='1' then
+								etsnd2<=s_head;
+							else
+								etsnd2<=s_end;
+							end if;
+						end case;	
+						
+						end if;
+					 
+					
+						
+					end if; --reset='1'
+		end process psend2;
+
+		psend3:process(clk,reset)
+		--génération des paquets à partir du premier port
+		variable pactype :natural range 0 to 15;
+		variable origport,destport : natural range 0 to 15;
+		variable datalen,i,i_pair : natural range 0 to 255;
+		
+		
+		
+				begin
+				if reset='1' then 
+				 etsnd3<=s_head;
+				 
+				else  --reset ='0'
+						origport:=4; --attention à régler  tosend3 =Portin(....) !!!!!!!
+						if rising_edge(clk) then -- le process s'exécute sur chaque front 
+															-- montant de l'horloge
+						case etsnd3 is
+						when s_head  =>    -- construction et envoie de l'en-tête
+						pactype:=5;-- fonction put
+						destport:=MAXPORT; -- le port de destination
+						datalen :=4;
+						--header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4));
+						 tosend3<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
+						 din3(origport)<='1';   -- en fait data_in_en(origport)
+						 i:=1;i_pair:=i /2;
+						 etsnd3<=s_len;  -- passer à l'état suivant
+						 --port1_in<=tosend1;
+						when s_len => 
+							--tosend3<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
+							din3(origport)<='1';
+							tosend3<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
+						
+							--port1_in<=tosend1; --copie directe sur le port 
+							etsnd3<=s_len2;
+						when s_len2 => 
+							tosend3<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
+							din3(origport)<='1';
+
+							--port1_in<=tosend1; --copie directe sur le port 
+							etsnd3<=s_data;	
+						when s_data =>
+							
+							if (fifo_in_full(origport)='0') then
+								din3(origport)<='1';
+								i_pair:=i_pair * 2;
+								if i=i_pair then        -- modulo
+									tosend3<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
+									--tosend3<="00001100";
+									--port1_in<="00001101";  --origport=1
+								else
+									tosend3<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
+									--tosend3<="00000110";
+									--port1_in<="00001111";   --origport=1
+								end if;
+								i:=i+1;i_pair:=i / 2;
+								if i>datalen then
+									din3(origport)<='0';
+									etsnd3<=s_end;
+								else
+									din3(origport)<='1';
+								end if;
+							else
+								din3(origport)<='0';
+							end if;
+						when s_end  =>
+						tosend3<="--------";
+							din3(origport)<='0';
+							if fifo_in_empty(origport)='1' then
+								etsnd3<=s_head;
+							else
+								etsnd3<=s_end;
+							end if;
+						end case;	
+						
+						end if;				
+						
+					end if; --reset='1'
+		end process psend3;		
+
+	preceiv:process(clk,reset)
+	
+	variable origport,ptype : natural range 0 to 15;
+	variable datalen,dcount ,timeout:natural range 0 to 255;
+	variable destport  : natural range 0 to 15:=1;
+	begin
+	
+	if reset='1' then
+		etrec<=r_wait;
+		destport:=1;
+		timeout:=0;
+	elsif rising_edge(clk) then
+			case  etrec is
+			when r_wait =>
+				if destport=0 then 
+					destport:=1;
+				end if;
+				timeout:=0;
+				time_out(destport)<='0';
+				if data_available(destport)='1' and cmd_in_en(destport)='0' then 
+				rdata_out_en(destport)<='1';
+				 etrec<=r_head;
+				else
+					if destport>=MAXPORT then 
+					destport:=1;
+					else 
+						destport:=destport+1;
+					end if;
+				etrec<=r_wait;
+				end if;
+			when r_head =>
+			
+				ptype:=to_integer(unsigned(portout(destport)(7 downto 4)));
+				origport:=to_integer(unsigned(portout(destport)(3 downto 0)));
+				rdata_out_en(destport)<='1';
+				if ptype=5 then 
+						etrec<=r_Dlen; --identification de la signature d'en tête valide
+					else
+						etrec<=r_wait;
+				end if;
+			
+
+			
+			
+			
+			when r_Dlen =>   --positionnement du mot de longueur des données
+			if data_available(destport)='1' then 
+			
+			rdata_out_en(destport)<='1';
+			etrec<=r_glen;
+			timeout:=0;
+			else
+				timeout:=timeout+1;
+					if timeout>=30 then 
+					time_out(destport)<='1';
+						etrec<=r_end;             -- données pas prêtes
+					end if;
+			
+			
+			end if;
+			when r_glen =>   --lecture effective de la longueur des données
+			if data_available(destport)='1' then 
+			datalen:=to_integer(unsigned(portout(destport)(7 downto 0)))-3;
+			rdata_out_en(destport)<='1';
+			etrec<=r_start;
+			dcount:=1;  -- initialisation du compteur de reception
+			else
+				timeout:=timeout+1;
+					if timeout>=30 then 
+					time_out(destport)<='1';
+						etrec<=r_end;             -- données pas prêtes
+					end if;
+			
+			end if;
+			
+			when r_start =>
+			if data_available(destport)='1'  then 
+				
+					dcount:=dcount+1;
+					assert true report "Donnée lue :"; --& string(unsigned(port4_out(7 downto 0)))
+					rdata_out_en(destport)<='1';
+					
+					--severity note;
+					if datalen<=dcount then 
+						etrec<=r_end;
+						
+					elsif dcount=255 then   --dépassement de la capacité
+						etrec<=r_end;
+					end if;
+			else
+					timeout:=timeout+1;
+					if timeout>=30 then 
+					   time_out(destport)<='1';
+						etrec<=r_end;             -- données pas prêtes
+					end if;
+				
+					
+			end if;
+			when r_end =>
+			
+			
+			rdata_out_en(destport)<='0';
+			rcount(destport)<=rcount(destport)+1;
+			etrec<=r_wait;
+			if destport>=MAXPORT then -- provoquer le passage au prochain port de réception
+					destport:=1;
+					else 
+						destport:=destport+1;
+					end if;
+			end case;
+		end if;   --reset='1'
+  end process preceiv;	
+	
+	pcmd:process(clk,reset)
+	
+	variable origport,destport,pid,mport : natural range 0 to 15;
+	variable datalen,dcount ,timeout:natural range 0 to 255;
+	begin
+	
+	if reset='1' then
+		etcmd<=cmdstart;
+		destport:=0;
+		timeout:=0;
+		origport:=1;
+		sorigport<=origport;
+	elsif rising_edge(clk) then
+			case  etcmd is
+			when cmdstart =>
+				if fifo_in_empty(origport)='1' then 
+					
+				
+				
+				
+				etcmd<=cmdpost;
+				end if;
+		 when cmdpost =>
+			if fifo_in_empty(origport)='1' then 
+			---assignations de l'état
+				--din4(origport)<='1';
+				--tosend4<="00000001"; ---code pour getportid
+				etcmd<=cmdpostidle;
+			end if;
+		when cmdpostidle  =>   --permet juste la prise en compte de la commande
+				if data_available(origport)='1' then 
+						etcmd<=cmdread;
+				end if;
+		 when cmdread =>
+				
+				
+				timeout:=0;
+				--time_out(destport)<='0';
+			if data_available(origport)='1' then 
+				mport:=to_integer(unsigned(portout(origport)(7 downto 4)));
+				pid:=to_integer(unsigned(portout(origport)(3 downto 0)))+1;
+				--cdata_out_en(origport)<='1';
+				if pid=origport then --le port a été bien identifié
+						etcmd<=cmdglen; --
+					else
+					etcmd<=cmdtimeout;
+				end if;
+			else
+--				if destport>=MAXPORT then 
+--					destport:=1;
+--					else 
+--						destport:=destport+1;
+--					end if;
+				etcmd<=cmdread;
+			end if;
+			
+			
+			when cmdlen =>   --positionnement du mot de longueur des données
+			if data_available(origport)='1' then 
+			
+			--cdata_out_en(origport)<='1';
+			etcmd<=cmdglen;
+			timeout:=0;
+			else
+				timeout:=timeout+1;
+					if timeout>=30 then 
+					--time_out(destport)<='1';
+						etcmd<=cmdtimeout;             -- données pas prêtes
+					end if;
+			
+			
+			end if;
+			when cmdglen =>   --lecture effective de la longueur des données
+			if data_available(origport)='1' then 
+			datalen:=to_integer(unsigned(portout(origport)(7 downto 0)))-3;
+			
+			etcmd<=cmddata;
+			dcount:=0;  -- initialisation du compteur de reception
+			else
+				timeout:=timeout+1;
+					if timeout>=30 then 
+					--time_out(destport)<='1';
+						etcmd<=cmdtimeout;             -- données pas prêtes
+					end if;
+			
+			end if;
+			
+			when cmddata =>
+			if data_available(origport)='1' and timeout<30 then 
+					
+					--cdata_out_en(origport)<='1';
+					mport:=to_integer(unsigned(portout(origport)(7 downto 4)));
+					--attention les ports sont numérotés à partir de 0
+					pid:=to_integer(unsigned(portout(origport)(3 downto 0)))+1;
+					
+					--severity note;
+					if Pid=origport then 
+						etcmd<=cmdend;
+						
+					else   --dépassement de la capacité
+						
+						timeout:=timeout+1;
+						if timeout>=30 then 
+							etcmd<=cmdtimeout;
+						end if;
+						
+					end if;
+			else
+					
+					if timeout>=30 then 
+					   time_out(origport)<='1';
+						etcmd<=cmdtimeout;             -- données pas prêtes
+					end if;
+				   timeout:=timeout+1;
+					
+			end if;
+			when cmdend =>
+			
+			
+			--cdata_out_en(origport)<='0';
+			
+--					if origport>=mport then -- provoquer le passage au prochain port de réception
+--						origport:=1;
+--					else 
+--						origport:=origport+1;
+--					end if;
+					etcmd<=cmdstart;
+					--cmd_in_en(origport)<='0';
+			when cmdtimeout =>
+			  etcmd<=cmdtimeout;
+			  --cmd_in_en(origport)<='0';
+			  etcmd<=cmdstart;
+			end case;
+		sorigport<=origport;	
+		end if;   --reset='1'
+		
+  end process pcmd;	
+
+majetcmd:process (etcmd)
+variable origport : natural:=1;-- =sorigport ;
+	begin
+			case  etcmd is
+			when cmdstart =>
+			
+				cmd_in_en(origport)<='1';
+
+		 when cmdpost  =>
+				din4(origport)<='1';
+				tosend4<="00000001"; ---code pour getportid
+				cmd_in_en(origport)<='1';
+				cdata_out_en(origport)<='0';
+		 when cmdpostidle =>
+				din4(origport)<='0';
+				cdata_out_en(origport)<=data_available(origport);
+				cmd_in_en(origport)<='1';
+	
+		 when cmdread =>
+				din4(origport)<='0';
+				cdata_out_en(origport)<=data_available(origport);
+				cmd_in_en(origport)<='1';
+	
+			when cmdlen |cmdglen =>   --positionnement du mot de longueur des données
+	
+					din4(origport)<='0';
+					cdata_out_en(origport)<=data_available(origport);
+					cmd_in_en(origport)<='1';
+
+			when cmddata =>
+			
+					din4(origport)<='0';
+					cdata_out_en(origport)<=data_available(origport);
+					cmd_in_en(origport)<='1';
+						
+			
+			when cmdend =>
+			
+				din4(origport)<='0';
+				cdata_out_en(origport)<='0';
+				cmd_in_en(origport)<='0';
+			
+			when cmdtimeout =>
+				  din4(origport)<='0';
+				  cdata_out_en(origport)<='0';
+				  cmd_in_en(origport)<='0';
+			 
+			end case;
+		
+end process majetcmd ; 
+   -- Stimulus process
+   stim_proc: process 
+   begin		
+      -- hold reset state for 100 ns.
+      reset<='1';
+		wait for 1 ns;	
+		reset<='1';
+      wait for clk_period*10;
+		reset<='0';
+		wait;
+      -- insert stimulus here 
+	
+      
+		
+		
+	end process;
+
+END;
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_8x8.wcfg
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_8x8.wcfg	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_8x8.wcfg	(revision 20)
@@ -0,0 +1,132 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="C:/Core MPI/SWITCH_GENERIC_16_16/test_xbar_16x16_isim_beh.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="coretypes" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="test_xbar_16x16" />
+            <top_module name="textio" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="14" />
+   <wave_markers>
+      <marker time="890107000" label="" />
+      <marker time="885107000" label="" />
+      <marker time="110000000" label="" />
+      <marker time="105000000" label="" />
+      <marker time="100000000" label="" />
+      <marker time="95000000" label="" />
+      <marker time="1137027000" label="" />
+      <marker time="97800000" label="" />
+   </wave_markers>
+   <wvobject fp_name="/test_xbar_16x16/etsnd1" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">etsnd1</obj_property>
+      <obj_property name="ObjectShortName">etsnd1</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/etsnd2" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">etsnd2</obj_property>
+      <obj_property name="ObjectShortName">etsnd2</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/etsnd3" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">etsnd3</obj_property>
+      <obj_property name="ObjectShortName">etsnd3</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/data_in_en" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_in_en[8:1]</obj_property>
+      <obj_property name="ObjectShortName">data_in_en[8:1]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/fifo_in_empty" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">fifo_in_empty[8:1]</obj_property>
+      <obj_property name="ObjectShortName">fifo_in_empty[8:1]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/portin" type="array" db_ref_id="1">
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="ElementShortName">portin[1:8]</obj_property>
+      <obj_property name="ObjectShortName">portin[1:8]</obj_property>
+      <obj_property name="label">portin[1:8]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/rcount" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rcount[1:8]</obj_property>
+      <obj_property name="ObjectShortName">rcount[1:8]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/reset" type="logic" db_ref_id="1">
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+      <obj_property name="label">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/etcmd" type="other" db_ref_id="1">
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="ElementShortName">etcmd</obj_property>
+      <obj_property name="ObjectShortName">etcmd</obj_property>
+      <obj_property name="label">etcmd</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/data_available" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_available[8:1]</obj_property>
+      <obj_property name="ObjectShortName">data_available[8:1]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/etrec" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">etrec</obj_property>
+      <obj_property name="ObjectShortName">etrec</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/portout" type="array" db_ref_id="1">
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="ElementShortName">portout[1:8]</obj_property>
+      <obj_property name="ObjectShortName">portout[1:8]</obj_property>
+      <obj_property name="label">portout[1:4]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/test_xbar_16x16/portout[1]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[1]</obj_property>
+         <obj_property name="ObjectShortName">portout[1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/test_xbar_16x16/portout[2]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[2]</obj_property>
+         <obj_property name="ObjectShortName">portout[2]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/test_xbar_16x16/portout[3]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[3]</obj_property>
+         <obj_property name="ObjectShortName">portout[3]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/test_xbar_16x16/portout[4]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[4]</obj_property>
+         <obj_property name="ObjectShortName">portout[4]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/test_xbar_16x16/portout[5]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[5]</obj_property>
+         <obj_property name="ObjectShortName">portout[5]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/test_xbar_16x16/portout[6]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[6]</obj_property>
+         <obj_property name="ObjectShortName">portout[6]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/test_xbar_16x16/portout[7]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[7]</obj_property>
+         <obj_property name="ObjectShortName">portout[7]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/test_xbar_16x16/portout[8]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[8]</obj_property>
+         <obj_property name="ObjectShortName">portout[8]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/data_out_en" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_out_en[8:1]</obj_property>
+      <obj_property name="ObjectShortName">data_out_en[8:1]</obj_property>
+   </wvobject>
+</wave_config>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_8x8_beh.prj
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_8x8_beh.prj	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/test_xbar_8x8_beh.prj	(revision 20)
@@ -0,0 +1,26 @@
+vhdl work "CoreTypes.vhd"
+vhdl work "RAM_256.vhd"
+vhdl work "Arbiter.vhd"
+vhdl work "SCHEDULER9_9.VHD"
+vhdl work "SCHEDULER8_8.VHD"
+vhdl work "SCHEDULER7_7.VHD"
+vhdl work "SCHEDULER6_6.VHD"
+vhdl work "SCHEDULER5_5.VHD"
+vhdl work "SCHEDULER4_4.VHD"
+vhdl work "SCHEDULER3_3.VHD"
+vhdl work "SCHEDULER2_2.VHD"
+vhdl work "SCHEDULER16_16.VHD"
+vhdl work "SCHEDULER15_15.VHD"
+vhdl work "SCHEDULER14_14.VHD"
+vhdl work "SCHEDULER13_13.VHD"
+vhdl work "SCHEDULER12_12.VHD"
+vhdl work "SCHEDULER11_11.VHD"
+vhdl work "SCHEDULER10_10.VHD"
+vhdl work "FIFO_256_FWFT.vhd"
+vhdl work "Crossbit.vhd"
+vhdl work "Scheduler.vhd"
+vhdl work "OUTPUT_PORT_MODULE.vhd"
+vhdl work "INPUT_PORT_MODULE.vhd"
+vhdl work "Crossbar.vhd"
+vhdl work "SWITCH_GEN.vhd"
+vhdl work "test_xbar_8x8.vhd"
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/testbench_summary.html
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/testbench_summary.html	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN/testbench_summary.html	(revision 20)
@@ -0,0 +1,78 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>testbench Project Status</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>GENERIC_16_16.xise</TD>
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>testbench</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>New</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc3s1200e-4ft256</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
+<TD>&nbsp;</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 11/29/2012 - 18:08:12</center>
+</BODY></HTML>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GENERIQUE.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GENERIQUE.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GENERIQUE.vhd	(revision 20)
@@ -0,0 +1,8134 @@
+----------------------------------------------------------------------------------
+-- Company: ENSET 2011
+-- Engineer: GAMOM NGOUNOU ET KIEGAING EMMANUEL ET TAGNE FRANKLIN EN 5
+-- 
+-- Create Date:    03:40:47 06/18/2011 
+-- Design Name: 
+-- Module Name:    SWITCH_GENERIQUE - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+-- fichier principal du switch générique; en fonction du parametre generique le 
+-- les directive de generation conditionnelle permettent de ne générer et synthétiser uniquement  la logique 
+-- nécessaire à l'implémentation  du switch de la dimension voulue
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity SWITCH_GENERIQUE is
+     generic(number_of_ports : positive := 8);
+     port(
+	        -- ports d'entree
+           Port1_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+           Port2_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+           Port3_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+           Port4_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+			  Port5_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+           Port6_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+           Port7_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+           Port8_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+			  Port9_in : in  STD_LOGIC_VECTOR  (7 downto 0);
+           Port10_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port13_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			 
+			  -- port de sortie
+			  Port1_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port2_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port3_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port4_out : out  STD_LOGIC_VECTOR (7 downto 0);
+			  Port5_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port6_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port7_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port8_out : out  STD_LOGIC_VECTOR (7 downto 0);
+			  Port9_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port10_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_out : out  STD_LOGIC_VECTOR (7 downto 0);
+			  Port13_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_out : out  STD_LOGIC_VECTOR (7 downto 0);
+			  -- signaux de controle
+			  data_in_en : in std_logic_vector(number_of_ports downto 1);
+			  data_out_en : in std_logic_vector(number_of_ports downto 1);
+			  fifo_in_full : out std_logic_vector(number_of_ports downto 1);
+			  fifo_in_empty : out std_logic_vector(number_of_ports downto 1);
+			  data_available : out std_logic_vector(number_of_ports downto 1);
+			  clk       : in   STD_LOGIC;
+			  reset     : in   STD_LOGIC);
+end SWITCH_GENERIQUE;
+
+architecture Behavioral of SWITCH_GENERIQUE is
+-- declaration des modules du switch generique
+-- le module de gestion des ports d'entrée
+
+COMPONENT INPUT_PORT_MODULE
+  generic(number_of_ports : positive := 4);
+    Port ( data_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           data_in_en : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+			  clk   : in  STD_LOGIC;
+			  request : out  STD_LOGIC_VECTOR (number_of_ports downto 1);
+           grant : in  STD_LOGIC_VECTOR (number_of_ports  downto 1);			  
+           fifo_full : out  STD_LOGIC;
+			  fifo_empty : out  STD_LOGIC;
+			  priority_rotation : out std_logic;
+           data_out : out  STD_LOGIC_VECTOR (7 downto 0);
+			  data_out_pulse : out std_logic);
+END COMPONENT;
+
+-- le module des ports de sortie
+
+COMPONENT OUTPUT_PORT_MODULE
+	PORT(
+		data_in : IN std_logic_vector(7 downto 0);
+		reset : IN std_logic;
+		clk : IN std_logic;
+		wr_en : IN std_logic;
+		rd_out_en : IN std_logic;          
+		data_out : OUT std_logic_vector(7 downto 0);
+		fifo_full : OUT std_logic;
+		data_avalaible : OUT std_logic
+		);
+END COMPONENT;
+	
+-- le module du crossbar
+COMPONENT Crossbar
+ generic
+	      (
+			  number_of_crossbar_ports: positive := 4
+			);
+    Port ( Port1_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port2_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port3_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port4_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port5_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port6_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port7_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port8_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port9_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port10_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  Port13_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_in : in  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_in : in  STD_LOGIC_VECTOR (7 downto 0);
+			  
+			  Port1_pulse_in : in std_logic;
+			  Port2_pulse_in : in std_logic;
+			  Port3_pulse_in : in std_logic;
+			  Port4_pulse_in : in std_logic;
+			  Port5_pulse_in : in std_logic;
+			  Port6_pulse_in : in std_logic;
+			  Port7_pulse_in : in std_logic;
+			  Port8_pulse_in : in std_logic;
+			  Port9_pulse_in : in std_logic;
+			  Port10_pulse_in : in std_logic;
+			  Port11_pulse_in : in std_logic;
+			  Port12_pulse_in : in std_logic;
+			  Port13_pulse_in : in std_logic;
+			  Port14_pulse_in : in std_logic;
+			  Port15_pulse_in : in std_logic;
+			  Port16_pulse_in : in std_logic;
+			  
+			  Port1_pulse_out : out std_logic;
+			  Port2_pulse_out : out std_logic;
+			  Port3_pulse_out : out std_logic;
+			  Port4_pulse_out : out std_logic;
+			  Port5_pulse_out : out std_logic;
+			  Port6_pulse_out : out std_logic;
+			  Port7_pulse_out : out std_logic;
+			  Port8_pulse_out : out std_logic;
+			  Port9_pulse_out : out std_logic;
+			  Port10_pulse_out : out std_logic;
+			  Port11_pulse_out : out std_logic;
+			  Port12_pulse_out : out std_logic;
+			  Port13_pulse_out : out std_logic;
+			  Port14_pulse_out : out std_logic;
+			  Port15_pulse_out : out std_logic;
+			  Port16_pulse_out : out std_logic;
+			  
+			  Port1_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port2_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port3_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port4_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port5_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port6_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port7_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port8_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port9_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port10_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port11_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port12_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  Port13_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port14_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port15_out : out  STD_LOGIC_VECTOR (7 downto 0);
+           Port16_out : out  STD_LOGIC_VECTOR (7 downto 0); 
+			  
+           Ctrl : in  STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1)
+       ); 
+ END COMPONENT;
+
+-- déclaration du  scheduler
+COMPONENT Scheduler
+	generic(number_of_ports : positive := 4);
+    Port ( Request : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
+			  Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1);
+           clk : in  STD_LOGIC;
+	        reset : in  STD_LOGIC;
+			  priority_rotation : in  STD_LOGIC_VECTOR (number_of_ports downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1));
+END COMPONENT;
+
+--declaration des signaux de connection entre les modules du switch
+--type port_connection_type is array(16 downto 1) of std_logic_vector(7 downto 1);
+--signal crossbar_port_in_connetion : port_connection_type;
+--signal crossbar_port_out_connetion :port_connection_type;
+--signal request_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
+--signal grant_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
+--signal priority_rotation_connection : std_logic_vector(number_of_ports downto 1);
+--signal fifo_out_full_connection : std_logic_vector(1 to number_of_ports);
+--signal crossbar_in_pulse_connection : std_logic_vector(number_of_ports downto 1);
+--signal crossbar_out_pulse_connection : std_logic_vector(number_of_ports downto 1);
+
+Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
+Signal grant_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
+Signal priority_rotation_signal : STD_LOGIC_VECTOR(number_of_ports downto 1);
+signal fifo_out_full_signal : std_logic_vector(number_of_ports downto 1);
+signal crossbar_in_port1 : std_logic_vector(7 downto 0);
+signal crossbar_in_port2 : std_logic_vector(7 downto 0);
+signal crossbar_in_port3 : std_logic_vector(7 downto 0);
+signal crossbar_in_port4 : std_logic_vector(7 downto 0);
+signal crossbar_in_port5 : std_logic_vector(7 downto 0);
+signal crossbar_in_port6 : std_logic_vector(7 downto 0);
+signal crossbar_in_port7 : std_logic_vector(7 downto 0);
+signal crossbar_in_port8 : std_logic_vector(7 downto 0);
+signal crossbar_in_port9 : std_logic_vector(7 downto 0);
+signal crossbar_in_port10 : std_logic_vector(7 downto 0);
+signal crossbar_in_port11 : std_logic_vector(7 downto 0);
+signal crossbar_in_port12 : std_logic_vector(7 downto 0);
+signal crossbar_in_port13 : std_logic_vector(7 downto 0);
+signal crossbar_in_port14 : std_logic_vector(7 downto 0);
+signal crossbar_in_port15 : std_logic_vector(7 downto 0);
+signal crossbar_in_port16: std_logic_vector(7 downto 0);
+
+signal crossbar_out_port1 : std_logic_vector(7 downto 0);
+signal crossbar_out_port2 : std_logic_vector(7 downto 0);
+signal crossbar_out_port3 : std_logic_vector(7 downto 0);
+signal crossbar_out_port4 : std_logic_vector(7 downto 0);
+signal crossbar_out_port5 : std_logic_vector(7 downto 0);
+signal crossbar_out_port6 : std_logic_vector(7 downto 0);
+signal crossbar_out_port7 : std_logic_vector(7 downto 0);
+signal crossbar_out_port8 : std_logic_vector(7 downto 0);
+signal crossbar_out_port9 : std_logic_vector(7 downto 0);
+signal crossbar_out_port10 : std_logic_vector(7 downto 0);
+signal crossbar_out_port11 : std_logic_vector(7 downto 0);
+signal crossbar_out_port12 : std_logic_vector(7 downto 0);
+signal crossbar_out_port13 : std_logic_vector(7 downto 0);
+signal crossbar_out_port14 : std_logic_vector(7 downto 0);
+signal crossbar_out_port15 : std_logic_vector(7 downto 0);
+signal crossbar_out_port16 : std_logic_vector(7 downto 0);
+
+signal crossbar_in_pulse1 : std_logic;
+signal crossbar_in_pulse2 : std_logic;
+signal crossbar_in_pulse3 : std_logic;
+signal crossbar_in_pulse4 : std_logic;
+signal crossbar_in_pulse5 : std_logic;
+signal crossbar_in_pulse6 : std_logic;
+signal crossbar_in_pulse7 : std_logic;
+signal crossbar_in_pulse8 : std_logic;
+signal crossbar_in_pulse9 : std_logic;
+signal crossbar_in_pulse10 : std_logic;
+signal crossbar_in_pulse11 : std_logic;
+signal crossbar_in_pulse12 : std_logic;
+signal crossbar_in_pulse13 : std_logic;
+signal crossbar_in_pulse14 : std_logic;
+signal crossbar_in_pulse15 : std_logic;
+signal crossbar_in_pulse16 : std_logic;
+
+
+signal crossbar_out_pulse1 : std_logic;
+signal crossbar_out_pulse2 : std_logic;
+signal crossbar_out_pulse3 : std_logic;
+signal crossbar_out_pulse4 : std_logic;
+signal crossbar_out_pulse5 : std_logic;
+signal crossbar_out_pulse6 : std_logic;
+signal crossbar_out_pulse7 : std_logic;
+signal crossbar_out_pulse8 : std_logic;
+signal crossbar_out_pulse9 : std_logic;
+signal crossbar_out_pulse10 : std_logic;
+signal crossbar_out_pulse11 : std_logic;
+signal crossbar_out_pulse12 : std_logic;
+signal crossbar_out_pulse13 : std_logic;
+signal crossbar_out_pulse14 : std_logic;
+signal crossbar_out_pulse15 : std_logic;
+signal crossbar_out_pulse16 : std_logic;
+
+
+begin
+-- intstanciation et connexion des modules du switch en fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+switch2x2 : if number_of_ports = 2 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>2)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>2)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4)
+);
+
+end generate switch2x2;
+
+
+-- switch 3 ports
+switch3x3 : if number_of_ports = 3 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>3)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>3)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>3)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9)
+);
+
+end generate switch3x3;
+
+
+-- switch 4 ports
+switch4x4 : if number_of_ports = 4 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>4)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>4)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>4)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>4)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16)
+);
+
+end generate switch4x4;
+
+
+-- switch 5 ports
+switch5x5 : if number_of_ports = 5 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>5)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>5)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>5)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>5)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>5)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25)
+);
+
+end generate switch5x5;
+
+
+-- switch 6 ports
+switch6x6 : if number_of_ports = 6 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>6)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>6)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>6)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>6)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>6)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>6)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36)
+);
+
+end generate switch6x6;
+
+
+-- switch 7 ports
+switch7x7 : if number_of_ports = 7 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>7)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>7)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>7)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>7)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>7)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30),
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>7)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(36) => grant_signal(36),
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(36) =>request_signal(36),
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>7)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   grant(49) => grant_signal(49),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45),
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48),
+   request(49) =>request_signal(49)
+);
+
+end generate switch7x7;
+
+
+-- switch 8 ports
+switch8x8 : if number_of_ports = 8 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(9),
+   grant(2) => grant_signal(10),
+   grant(3) => grant_signal(11),
+   grant(4) => grant_signal(12),
+   grant(5) => grant_signal(13),
+   grant(6) => grant_signal(14),
+   grant(7) => grant_signal(15),
+   grant(8) => grant_signal(16),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(1) =>request_signal(9),
+   request(2) =>request_signal(10),
+   request(3) =>request_signal(11),
+   request(4) =>request_signal(12),
+   request(5) =>request_signal(13),
+   request(6) =>request_signal(14),
+   request(7) =>request_signal(15),
+   request(8) =>request_signal(16)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(17),
+   grant(2) => grant_signal(18),
+   grant(3) => grant_signal(19),
+   grant(4) => grant_signal(20),
+   grant(5) => grant_signal(21),
+   grant(6) => grant_signal(22),
+   grant(7) => grant_signal(23),
+   grant(8) => grant_signal(24),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(1) =>request_signal(17),
+   request(2) =>request_signal(18),
+   request(3) =>request_signal(19),
+   request(4) =>request_signal(20),
+   request(5) =>request_signal(21),
+   request(6) =>request_signal(22),
+   request(7) =>request_signal(23),
+   request(8) =>request_signal(24)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(25),
+   grant(2) => grant_signal(26),
+   grant(3) => grant_signal(27),
+   grant(4) => grant_signal(28),
+   grant(5) => grant_signal(29),
+   grant(6) => grant_signal(30),
+   grant(7) => grant_signal(31),
+   grant(8) => grant_signal(32),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(1) =>request_signal(25),
+   request(2) =>request_signal(26),
+   request(3) =>request_signal(27),
+   request(4) =>request_signal(28),
+   request(5) =>request_signal(29),
+   request(6) =>request_signal(30),
+   request(7) =>request_signal(31),
+   request(8) =>request_signal(32)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(33),
+   grant(2) => grant_signal(34),
+   grant(3) => grant_signal(35),
+   grant(4) => grant_signal(36),
+   grant(5) => grant_signal(37),
+   grant(6) => grant_signal(38),
+   grant(7) => grant_signal(39),
+   grant(8) => grant_signal(40),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(1) =>request_signal(33),
+   request(2) =>request_signal(34),
+   request(3) =>request_signal(35),
+   request(4) =>request_signal(36),
+   request(5) =>request_signal(37),
+   request(6) =>request_signal(38),
+   request(7) =>request_signal(39),
+   request(8) =>request_signal(40)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(41),
+   grant(2) => grant_signal(42),
+   grant(3) => grant_signal(43),
+   grant(4) => grant_signal(44),
+   grant(5) => grant_signal(45),
+   grant(6) => grant_signal(46),
+   grant(7) => grant_signal(47),
+   grant(8) => grant_signal(48),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(1) =>request_signal(41),
+   request(2) =>request_signal(42),
+   request(3) =>request_signal(43),
+   request(4) =>request_signal(44),
+   request(5) =>request_signal(45),
+   request(6) =>request_signal(46),
+   request(7) =>request_signal(47),
+   request(8) =>request_signal(48)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(49),
+   grant(2) => grant_signal(50),
+   grant(3) => grant_signal(51),
+   grant(4) => grant_signal(52),
+   grant(5) => grant_signal(53),
+   grant(6) => grant_signal(54),
+   grant(7) => grant_signal(55),
+   grant(8) => grant_signal(56),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(1) =>request_signal(49),
+   request(2) =>request_signal(50),
+   request(3) =>request_signal(51),
+   request(4) =>request_signal(52),
+   request(5) =>request_signal(53),
+   request(6) =>request_signal(54),
+   request(7) =>request_signal(55),
+   request(8) =>request_signal(56)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>8)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(57),
+   grant(2) => grant_signal(58),
+   grant(3) => grant_signal(59),
+   grant(4) => grant_signal(60),
+   grant(5) => grant_signal(61),
+   grant(6) => grant_signal(62),
+   grant(7) => grant_signal(63),
+   grant(8) => grant_signal(64),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(1) =>request_signal(57),
+   request(2) =>request_signal(58),
+   request(3) =>request_signal(59),
+   request(4) =>request_signal(60),
+   request(5) =>request_signal(61),
+   request(6) =>request_signal(62),
+   request(7) =>request_signal(63),
+   request(8) =>request_signal(64)
+);
+
+end generate switch8x8;
+
+
+-- switch 9 ports
+switch9x9 : if number_of_ports = 9 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30),
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42),
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48),
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50),
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52),
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(55) => grant_signal(55),
+   grant(56) => grant_signal(56),
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(55) =>request_signal(55),
+   request(56) =>request_signal(56),
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60),
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(64) => grant_signal(64),
+   grant(65) => grant_signal(65),
+   grant(66) => grant_signal(66),
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(64) =>request_signal(64),
+   request(65) =>request_signal(65),
+   request(66) =>request_signal(66),
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70),
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>9)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   grant(78) => grant_signal(78),
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   grant(81) => grant_signal(81),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75),
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77),
+   request(78) =>request_signal(78),
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80),
+   request(81) =>request_signal(81)
+);
+
+end generate switch9x9;
+
+
+-- switch 10 ports
+switch10x10 : if number_of_ports = 10 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36),
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42),
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45),
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48),
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   grant(55) => grant_signal(55),
+   grant(56) => grant_signal(56),
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52),
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54),
+   request(55) =>request_signal(55),
+   request(56) =>request_signal(56),
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   grant(64) => grant_signal(64),
+   grant(65) => grant_signal(65),
+   grant(66) => grant_signal(66),
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63),
+   request(64) =>request_signal(64),
+   request(65) =>request_signal(65),
+   request(66) =>request_signal(66),
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   grant(78) => grant_signal(78),
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72),
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75),
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77),
+   request(78) =>request_signal(78),
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(81) => grant_signal(81),
+   grant(82) => grant_signal(82),
+   grant(83) => grant_signal(83),
+   grant(84) => grant_signal(84),
+   grant(85) => grant_signal(85),
+   grant(86) => grant_signal(86),
+   grant(87) => grant_signal(87),
+   grant(88) => grant_signal(88),
+   grant(89) => grant_signal(89),
+   grant(90) => grant_signal(90),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(81) =>request_signal(81),
+   request(82) =>request_signal(82),
+   request(83) =>request_signal(83),
+   request(84) =>request_signal(84),
+   request(85) =>request_signal(85),
+   request(86) =>request_signal(86),
+   request(87) =>request_signal(87),
+   request(88) =>request_signal(88),
+   request(89) =>request_signal(89),
+   request(90) =>request_signal(90)
+);
+
+PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>10)
+PORT MAP(
+   data_in => Port10_in,
+   data_in_en => data_in_en(10),
+   reset => reset,
+   clk =>clk,
+   grant(91) => grant_signal(91),
+   grant(92) => grant_signal(92),
+   grant(93) => grant_signal(93),
+   grant(94) => grant_signal(94),
+   grant(95) => grant_signal(95),
+   grant(96) => grant_signal(96),
+   grant(97) => grant_signal(97),
+   grant(98) => grant_signal(98),
+   grant(99) => grant_signal(99),
+   grant(100) => grant_signal(100),
+   fifo_full =>fifo_in_full(10),
+   priority_rotation =>  priority_rotation_signal(10),
+   fifo_empty => fifo_in_empty(10),
+   data_out =>crossbar_in_port10,
+   data_out_pulse =>crossbar_in_pulse10,
+   request(91) =>request_signal(91),
+   request(92) =>request_signal(92),
+   request(93) =>request_signal(93),
+   request(94) =>request_signal(94),
+   request(95) =>request_signal(95),
+   request(96) =>request_signal(96),
+   request(97) =>request_signal(97),
+   request(98) =>request_signal(98),
+   request(99) =>request_signal(99),
+   request(100) =>request_signal(100)
+);
+
+end generate switch10x10;
+
+
+-- switch 11 ports
+switch11x11 : if number_of_ports = 11 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30),
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36),
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42),
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(45) => grant_signal(45),
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   grant(55) => grant_signal(55),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(45) =>request_signal(45),
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48),
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50),
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52),
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54),
+   request(55) =>request_signal(55)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(56) => grant_signal(56),
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   grant(64) => grant_signal(64),
+   grant(65) => grant_signal(65),
+   grant(66) => grant_signal(66),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(56) =>request_signal(56),
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60),
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63),
+   request(64) =>request_signal(64),
+   request(65) =>request_signal(65),
+   request(66) =>request_signal(66)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70),
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72),
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75),
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(78) => grant_signal(78),
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   grant(81) => grant_signal(81),
+   grant(82) => grant_signal(82),
+   grant(83) => grant_signal(83),
+   grant(84) => grant_signal(84),
+   grant(85) => grant_signal(85),
+   grant(86) => grant_signal(86),
+   grant(87) => grant_signal(87),
+   grant(88) => grant_signal(88),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(78) =>request_signal(78),
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80),
+   request(81) =>request_signal(81),
+   request(82) =>request_signal(82),
+   request(83) =>request_signal(83),
+   request(84) =>request_signal(84),
+   request(85) =>request_signal(85),
+   request(86) =>request_signal(86),
+   request(87) =>request_signal(87),
+   request(88) =>request_signal(88)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(89) => grant_signal(89),
+   grant(90) => grant_signal(90),
+   grant(91) => grant_signal(91),
+   grant(92) => grant_signal(92),
+   grant(93) => grant_signal(93),
+   grant(94) => grant_signal(94),
+   grant(95) => grant_signal(95),
+   grant(96) => grant_signal(96),
+   grant(97) => grant_signal(97),
+   grant(98) => grant_signal(98),
+   grant(99) => grant_signal(99),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(89) =>request_signal(89),
+   request(90) =>request_signal(90),
+   request(91) =>request_signal(91),
+   request(92) =>request_signal(92),
+   request(93) =>request_signal(93),
+   request(94) =>request_signal(94),
+   request(95) =>request_signal(95),
+   request(96) =>request_signal(96),
+   request(97) =>request_signal(97),
+   request(98) =>request_signal(98),
+   request(99) =>request_signal(99)
+);
+
+PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port10_in,
+   data_in_en => data_in_en(10),
+   reset => reset,
+   clk =>clk,
+   grant(100) => grant_signal(100),
+   grant(101) => grant_signal(101),
+   grant(102) => grant_signal(102),
+   grant(103) => grant_signal(103),
+   grant(104) => grant_signal(104),
+   grant(105) => grant_signal(105),
+   grant(106) => grant_signal(106),
+   grant(107) => grant_signal(107),
+   grant(108) => grant_signal(108),
+   grant(109) => grant_signal(109),
+   grant(110) => grant_signal(110),
+   fifo_full =>fifo_in_full(10),
+   priority_rotation =>  priority_rotation_signal(10),
+   fifo_empty => fifo_in_empty(10),
+   data_out =>crossbar_in_port10,
+   data_out_pulse =>crossbar_in_pulse10,
+   request(100) =>request_signal(100),
+   request(101) =>request_signal(101),
+   request(102) =>request_signal(102),
+   request(103) =>request_signal(103),
+   request(104) =>request_signal(104),
+   request(105) =>request_signal(105),
+   request(106) =>request_signal(106),
+   request(107) =>request_signal(107),
+   request(108) =>request_signal(108),
+   request(109) =>request_signal(109),
+   request(110) =>request_signal(110)
+);
+
+PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>11)
+PORT MAP(
+   data_in => Port11_in,
+   data_in_en => data_in_en(11),
+   reset => reset,
+   clk =>clk,
+   grant(111) => grant_signal(111),
+   grant(112) => grant_signal(112),
+   grant(113) => grant_signal(113),
+   grant(114) => grant_signal(114),
+   grant(115) => grant_signal(115),
+   grant(116) => grant_signal(116),
+   grant(117) => grant_signal(117),
+   grant(118) => grant_signal(118),
+   grant(119) => grant_signal(119),
+   grant(120) => grant_signal(120),
+   grant(121) => grant_signal(121),
+   fifo_full =>fifo_in_full(11),
+   priority_rotation =>  priority_rotation_signal(11),
+   fifo_empty => fifo_in_empty(11),
+   data_out =>crossbar_in_port11,
+   data_out_pulse =>crossbar_in_pulse11,
+   request(111) =>request_signal(111),
+   request(112) =>request_signal(112),
+   request(113) =>request_signal(113),
+   request(114) =>request_signal(114),
+   request(115) =>request_signal(115),
+   request(116) =>request_signal(116),
+   request(117) =>request_signal(117),
+   request(118) =>request_signal(118),
+   request(119) =>request_signal(119),
+   request(120) =>request_signal(120),
+   request(121) =>request_signal(121)
+);
+
+end generate switch11x11;
+
+
+-- switch 12 ports
+switch12x12 : if number_of_ports = 12 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30),
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42),
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45),
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   grant(55) => grant_signal(55),
+   grant(56) => grant_signal(56),
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50),
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52),
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54),
+   request(55) =>request_signal(55),
+   request(56) =>request_signal(56),
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   grant(64) => grant_signal(64),
+   grant(65) => grant_signal(65),
+   grant(66) => grant_signal(66),
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63),
+   request(64) =>request_signal(64),
+   request(65) =>request_signal(65),
+   request(66) =>request_signal(66),
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70),
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   grant(78) => grant_signal(78),
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   grant(81) => grant_signal(81),
+   grant(82) => grant_signal(82),
+   grant(83) => grant_signal(83),
+   grant(84) => grant_signal(84),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75),
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77),
+   request(78) =>request_signal(78),
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80),
+   request(81) =>request_signal(81),
+   request(82) =>request_signal(82),
+   request(83) =>request_signal(83),
+   request(84) =>request_signal(84)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(85) => grant_signal(85),
+   grant(86) => grant_signal(86),
+   grant(87) => grant_signal(87),
+   grant(88) => grant_signal(88),
+   grant(89) => grant_signal(89),
+   grant(90) => grant_signal(90),
+   grant(91) => grant_signal(91),
+   grant(92) => grant_signal(92),
+   grant(93) => grant_signal(93),
+   grant(94) => grant_signal(94),
+   grant(95) => grant_signal(95),
+   grant(96) => grant_signal(96),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(85) =>request_signal(85),
+   request(86) =>request_signal(86),
+   request(87) =>request_signal(87),
+   request(88) =>request_signal(88),
+   request(89) =>request_signal(89),
+   request(90) =>request_signal(90),
+   request(91) =>request_signal(91),
+   request(92) =>request_signal(92),
+   request(93) =>request_signal(93),
+   request(94) =>request_signal(94),
+   request(95) =>request_signal(95),
+   request(96) =>request_signal(96)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(97) => grant_signal(97),
+   grant(98) => grant_signal(98),
+   grant(99) => grant_signal(99),
+   grant(100) => grant_signal(100),
+   grant(101) => grant_signal(101),
+   grant(102) => grant_signal(102),
+   grant(103) => grant_signal(103),
+   grant(104) => grant_signal(104),
+   grant(105) => grant_signal(105),
+   grant(106) => grant_signal(106),
+   grant(107) => grant_signal(107),
+   grant(108) => grant_signal(108),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(97) =>request_signal(97),
+   request(98) =>request_signal(98),
+   request(99) =>request_signal(99),
+   request(100) =>request_signal(100),
+   request(101) =>request_signal(101),
+   request(102) =>request_signal(102),
+   request(103) =>request_signal(103),
+   request(104) =>request_signal(104),
+   request(105) =>request_signal(105),
+   request(106) =>request_signal(106),
+   request(107) =>request_signal(107),
+   request(108) =>request_signal(108)
+);
+
+PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port10_in,
+   data_in_en => data_in_en(10),
+   reset => reset,
+   clk =>clk,
+   grant(109) => grant_signal(109),
+   grant(110) => grant_signal(110),
+   grant(111) => grant_signal(111),
+   grant(112) => grant_signal(112),
+   grant(113) => grant_signal(113),
+   grant(114) => grant_signal(114),
+   grant(115) => grant_signal(115),
+   grant(116) => grant_signal(116),
+   grant(117) => grant_signal(117),
+   grant(118) => grant_signal(118),
+   grant(119) => grant_signal(119),
+   grant(120) => grant_signal(120),
+   fifo_full =>fifo_in_full(10),
+   priority_rotation =>  priority_rotation_signal(10),
+   fifo_empty => fifo_in_empty(10),
+   data_out =>crossbar_in_port10,
+   data_out_pulse =>crossbar_in_pulse10,
+   request(109) =>request_signal(109),
+   request(110) =>request_signal(110),
+   request(111) =>request_signal(111),
+   request(112) =>request_signal(112),
+   request(113) =>request_signal(113),
+   request(114) =>request_signal(114),
+   request(115) =>request_signal(115),
+   request(116) =>request_signal(116),
+   request(117) =>request_signal(117),
+   request(118) =>request_signal(118),
+   request(119) =>request_signal(119),
+   request(120) =>request_signal(120)
+);
+
+PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port11_in,
+   data_in_en => data_in_en(11),
+   reset => reset,
+   clk =>clk,
+   grant(121) => grant_signal(121),
+   grant(122) => grant_signal(122),
+   grant(123) => grant_signal(123),
+   grant(124) => grant_signal(124),
+   grant(125) => grant_signal(125),
+   grant(126) => grant_signal(126),
+   grant(127) => grant_signal(127),
+   grant(128) => grant_signal(128),
+   grant(129) => grant_signal(129),
+   grant(130) => grant_signal(130),
+   grant(131) => grant_signal(131),
+   grant(132) => grant_signal(132),
+   fifo_full =>fifo_in_full(11),
+   priority_rotation =>  priority_rotation_signal(11),
+   fifo_empty => fifo_in_empty(11),
+   data_out =>crossbar_in_port11,
+   data_out_pulse =>crossbar_in_pulse11,
+   request(121) =>request_signal(121),
+   request(122) =>request_signal(122),
+   request(123) =>request_signal(123),
+   request(124) =>request_signal(124),
+   request(125) =>request_signal(125),
+   request(126) =>request_signal(126),
+   request(127) =>request_signal(127),
+   request(128) =>request_signal(128),
+   request(129) =>request_signal(129),
+   request(130) =>request_signal(130),
+   request(131) =>request_signal(131),
+   request(132) =>request_signal(132)
+);
+
+PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>12)
+PORT MAP(
+   data_in => Port12_in,
+   data_in_en => data_in_en(12),
+   reset => reset,
+   clk =>clk,
+   grant(133) => grant_signal(133),
+   grant(134) => grant_signal(134),
+   grant(135) => grant_signal(135),
+   grant(136) => grant_signal(136),
+   grant(137) => grant_signal(137),
+   grant(138) => grant_signal(138),
+   grant(139) => grant_signal(139),
+   grant(140) => grant_signal(140),
+   grant(141) => grant_signal(141),
+   grant(142) => grant_signal(142),
+   grant(143) => grant_signal(143),
+   grant(144) => grant_signal(144),
+   fifo_full =>fifo_in_full(12),
+   priority_rotation =>  priority_rotation_signal(12),
+   fifo_empty => fifo_in_empty(12),
+   data_out =>crossbar_in_port12,
+   data_out_pulse =>crossbar_in_pulse12,
+   request(133) =>request_signal(133),
+   request(134) =>request_signal(134),
+   request(135) =>request_signal(135),
+   request(136) =>request_signal(136),
+   request(137) =>request_signal(137),
+   request(138) =>request_signal(138),
+   request(139) =>request_signal(139),
+   request(140) =>request_signal(140),
+   request(141) =>request_signal(141),
+   request(142) =>request_signal(142),
+   request(143) =>request_signal(143),
+   request(144) =>request_signal(144)
+);
+
+end generate switch12x12;
+
+
+-- switch 13 ports
+switch13x13 : if number_of_ports = 13 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30),
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36),
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42),
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45),
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48),
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50),
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   grant(55) => grant_signal(55),
+   grant(56) => grant_signal(56),
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   grant(64) => grant_signal(64),
+   grant(65) => grant_signal(65),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54),
+   request(55) =>request_signal(55),
+   request(56) =>request_signal(56),
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60),
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63),
+   request(64) =>request_signal(64),
+   request(65) =>request_signal(65)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(66) => grant_signal(66),
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   grant(78) => grant_signal(78),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(66) =>request_signal(66),
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70),
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72),
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75),
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77),
+   request(78) =>request_signal(78)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   grant(81) => grant_signal(81),
+   grant(82) => grant_signal(82),
+   grant(83) => grant_signal(83),
+   grant(84) => grant_signal(84),
+   grant(85) => grant_signal(85),
+   grant(86) => grant_signal(86),
+   grant(87) => grant_signal(87),
+   grant(88) => grant_signal(88),
+   grant(89) => grant_signal(89),
+   grant(90) => grant_signal(90),
+   grant(91) => grant_signal(91),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80),
+   request(81) =>request_signal(81),
+   request(82) =>request_signal(82),
+   request(83) =>request_signal(83),
+   request(84) =>request_signal(84),
+   request(85) =>request_signal(85),
+   request(86) =>request_signal(86),
+   request(87) =>request_signal(87),
+   request(88) =>request_signal(88),
+   request(89) =>request_signal(89),
+   request(90) =>request_signal(90),
+   request(91) =>request_signal(91)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(92) => grant_signal(92),
+   grant(93) => grant_signal(93),
+   grant(94) => grant_signal(94),
+   grant(95) => grant_signal(95),
+   grant(96) => grant_signal(96),
+   grant(97) => grant_signal(97),
+   grant(98) => grant_signal(98),
+   grant(99) => grant_signal(99),
+   grant(100) => grant_signal(100),
+   grant(101) => grant_signal(101),
+   grant(102) => grant_signal(102),
+   grant(103) => grant_signal(103),
+   grant(104) => grant_signal(104),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(92) =>request_signal(92),
+   request(93) =>request_signal(93),
+   request(94) =>request_signal(94),
+   request(95) =>request_signal(95),
+   request(96) =>request_signal(96),
+   request(97) =>request_signal(97),
+   request(98) =>request_signal(98),
+   request(99) =>request_signal(99),
+   request(100) =>request_signal(100),
+   request(101) =>request_signal(101),
+   request(102) =>request_signal(102),
+   request(103) =>request_signal(103),
+   request(104) =>request_signal(104)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(105) => grant_signal(105),
+   grant(106) => grant_signal(106),
+   grant(107) => grant_signal(107),
+   grant(108) => grant_signal(108),
+   grant(109) => grant_signal(109),
+   grant(110) => grant_signal(110),
+   grant(111) => grant_signal(111),
+   grant(112) => grant_signal(112),
+   grant(113) => grant_signal(113),
+   grant(114) => grant_signal(114),
+   grant(115) => grant_signal(115),
+   grant(116) => grant_signal(116),
+   grant(117) => grant_signal(117),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(105) =>request_signal(105),
+   request(106) =>request_signal(106),
+   request(107) =>request_signal(107),
+   request(108) =>request_signal(108),
+   request(109) =>request_signal(109),
+   request(110) =>request_signal(110),
+   request(111) =>request_signal(111),
+   request(112) =>request_signal(112),
+   request(113) =>request_signal(113),
+   request(114) =>request_signal(114),
+   request(115) =>request_signal(115),
+   request(116) =>request_signal(116),
+   request(117) =>request_signal(117)
+);
+
+PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port10_in,
+   data_in_en => data_in_en(10),
+   reset => reset,
+   clk =>clk,
+   grant(118) => grant_signal(118),
+   grant(119) => grant_signal(119),
+   grant(120) => grant_signal(120),
+   grant(121) => grant_signal(121),
+   grant(122) => grant_signal(122),
+   grant(123) => grant_signal(123),
+   grant(124) => grant_signal(124),
+   grant(125) => grant_signal(125),
+   grant(126) => grant_signal(126),
+   grant(127) => grant_signal(127),
+   grant(128) => grant_signal(128),
+   grant(129) => grant_signal(129),
+   grant(130) => grant_signal(130),
+   fifo_full =>fifo_in_full(10),
+   priority_rotation =>  priority_rotation_signal(10),
+   fifo_empty => fifo_in_empty(10),
+   data_out =>crossbar_in_port10,
+   data_out_pulse =>crossbar_in_pulse10,
+   request(118) =>request_signal(118),
+   request(119) =>request_signal(119),
+   request(120) =>request_signal(120),
+   request(121) =>request_signal(121),
+   request(122) =>request_signal(122),
+   request(123) =>request_signal(123),
+   request(124) =>request_signal(124),
+   request(125) =>request_signal(125),
+   request(126) =>request_signal(126),
+   request(127) =>request_signal(127),
+   request(128) =>request_signal(128),
+   request(129) =>request_signal(129),
+   request(130) =>request_signal(130)
+);
+
+PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port11_in,
+   data_in_en => data_in_en(11),
+   reset => reset,
+   clk =>clk,
+   grant(131) => grant_signal(131),
+   grant(132) => grant_signal(132),
+   grant(133) => grant_signal(133),
+   grant(134) => grant_signal(134),
+   grant(135) => grant_signal(135),
+   grant(136) => grant_signal(136),
+   grant(137) => grant_signal(137),
+   grant(138) => grant_signal(138),
+   grant(139) => grant_signal(139),
+   grant(140) => grant_signal(140),
+   grant(141) => grant_signal(141),
+   grant(142) => grant_signal(142),
+   grant(143) => grant_signal(143),
+   fifo_full =>fifo_in_full(11),
+   priority_rotation =>  priority_rotation_signal(11),
+   fifo_empty => fifo_in_empty(11),
+   data_out =>crossbar_in_port11,
+   data_out_pulse =>crossbar_in_pulse11,
+   request(131) =>request_signal(131),
+   request(132) =>request_signal(132),
+   request(133) =>request_signal(133),
+   request(134) =>request_signal(134),
+   request(135) =>request_signal(135),
+   request(136) =>request_signal(136),
+   request(137) =>request_signal(137),
+   request(138) =>request_signal(138),
+   request(139) =>request_signal(139),
+   request(140) =>request_signal(140),
+   request(141) =>request_signal(141),
+   request(142) =>request_signal(142),
+   request(143) =>request_signal(143)
+);
+
+PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port12_in,
+   data_in_en => data_in_en(12),
+   reset => reset,
+   clk =>clk,
+   grant(144) => grant_signal(144),
+   grant(145) => grant_signal(145),
+   grant(146) => grant_signal(146),
+   grant(147) => grant_signal(147),
+   grant(148) => grant_signal(148),
+   grant(149) => grant_signal(149),
+   grant(150) => grant_signal(150),
+   grant(151) => grant_signal(151),
+   grant(152) => grant_signal(152),
+   grant(153) => grant_signal(153),
+   grant(154) => grant_signal(154),
+   grant(155) => grant_signal(155),
+   grant(156) => grant_signal(156),
+   fifo_full =>fifo_in_full(12),
+   priority_rotation =>  priority_rotation_signal(12),
+   fifo_empty => fifo_in_empty(12),
+   data_out =>crossbar_in_port12,
+   data_out_pulse =>crossbar_in_pulse12,
+   request(144) =>request_signal(144),
+   request(145) =>request_signal(145),
+   request(146) =>request_signal(146),
+   request(147) =>request_signal(147),
+   request(148) =>request_signal(148),
+   request(149) =>request_signal(149),
+   request(150) =>request_signal(150),
+   request(151) =>request_signal(151),
+   request(152) =>request_signal(152),
+   request(153) =>request_signal(153),
+   request(154) =>request_signal(154),
+   request(155) =>request_signal(155),
+   request(156) =>request_signal(156)
+);
+
+PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>13)
+PORT MAP(
+   data_in => Port13_in,
+   data_in_en => data_in_en(13),
+   reset => reset,
+   clk =>clk,
+   grant(157) => grant_signal(157),
+   grant(158) => grant_signal(158),
+   grant(159) => grant_signal(159),
+   grant(160) => grant_signal(160),
+   grant(161) => grant_signal(161),
+   grant(162) => grant_signal(162),
+   grant(163) => grant_signal(163),
+   grant(164) => grant_signal(164),
+   grant(165) => grant_signal(165),
+   grant(166) => grant_signal(166),
+   grant(167) => grant_signal(167),
+   grant(168) => grant_signal(168),
+   grant(169) => grant_signal(169),
+   fifo_full =>fifo_in_full(13),
+   priority_rotation =>  priority_rotation_signal(13),
+   fifo_empty => fifo_in_empty(13),
+   data_out =>crossbar_in_port13,
+   data_out_pulse =>crossbar_in_pulse13,
+   request(157) =>request_signal(157),
+   request(158) =>request_signal(158),
+   request(159) =>request_signal(159),
+   request(160) =>request_signal(160),
+   request(161) =>request_signal(161),
+   request(162) =>request_signal(162),
+   request(163) =>request_signal(163),
+   request(164) =>request_signal(164),
+   request(165) =>request_signal(165),
+   request(166) =>request_signal(166),
+   request(167) =>request_signal(167),
+   request(168) =>request_signal(168),
+   request(169) =>request_signal(169)
+);
+
+end generate switch13x13;
+
+
+-- switch 14 ports
+switch14x14 : if number_of_ports = 14 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30),
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36),
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   grant(55) => grant_signal(55),
+   grant(56) => grant_signal(56),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45),
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48),
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50),
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52),
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54),
+   request(55) =>request_signal(55),
+   request(56) =>request_signal(56)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   grant(64) => grant_signal(64),
+   grant(65) => grant_signal(65),
+   grant(66) => grant_signal(66),
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60),
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63),
+   request(64) =>request_signal(64),
+   request(65) =>request_signal(65),
+   request(66) =>request_signal(66),
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   grant(78) => grant_signal(78),
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   grant(81) => grant_signal(81),
+   grant(82) => grant_signal(82),
+   grant(83) => grant_signal(83),
+   grant(84) => grant_signal(84),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72),
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75),
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77),
+   request(78) =>request_signal(78),
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80),
+   request(81) =>request_signal(81),
+   request(82) =>request_signal(82),
+   request(83) =>request_signal(83),
+   request(84) =>request_signal(84)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(85) => grant_signal(85),
+   grant(86) => grant_signal(86),
+   grant(87) => grant_signal(87),
+   grant(88) => grant_signal(88),
+   grant(89) => grant_signal(89),
+   grant(90) => grant_signal(90),
+   grant(91) => grant_signal(91),
+   grant(92) => grant_signal(92),
+   grant(93) => grant_signal(93),
+   grant(94) => grant_signal(94),
+   grant(95) => grant_signal(95),
+   grant(96) => grant_signal(96),
+   grant(97) => grant_signal(97),
+   grant(98) => grant_signal(98),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(85) =>request_signal(85),
+   request(86) =>request_signal(86),
+   request(87) =>request_signal(87),
+   request(88) =>request_signal(88),
+   request(89) =>request_signal(89),
+   request(90) =>request_signal(90),
+   request(91) =>request_signal(91),
+   request(92) =>request_signal(92),
+   request(93) =>request_signal(93),
+   request(94) =>request_signal(94),
+   request(95) =>request_signal(95),
+   request(96) =>request_signal(96),
+   request(97) =>request_signal(97),
+   request(98) =>request_signal(98)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(99) => grant_signal(99),
+   grant(100) => grant_signal(100),
+   grant(101) => grant_signal(101),
+   grant(102) => grant_signal(102),
+   grant(103) => grant_signal(103),
+   grant(104) => grant_signal(104),
+   grant(105) => grant_signal(105),
+   grant(106) => grant_signal(106),
+   grant(107) => grant_signal(107),
+   grant(108) => grant_signal(108),
+   grant(109) => grant_signal(109),
+   grant(110) => grant_signal(110),
+   grant(111) => grant_signal(111),
+   grant(112) => grant_signal(112),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(99) =>request_signal(99),
+   request(100) =>request_signal(100),
+   request(101) =>request_signal(101),
+   request(102) =>request_signal(102),
+   request(103) =>request_signal(103),
+   request(104) =>request_signal(104),
+   request(105) =>request_signal(105),
+   request(106) =>request_signal(106),
+   request(107) =>request_signal(107),
+   request(108) =>request_signal(108),
+   request(109) =>request_signal(109),
+   request(110) =>request_signal(110),
+   request(111) =>request_signal(111),
+   request(112) =>request_signal(112)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(113) => grant_signal(113),
+   grant(114) => grant_signal(114),
+   grant(115) => grant_signal(115),
+   grant(116) => grant_signal(116),
+   grant(117) => grant_signal(117),
+   grant(118) => grant_signal(118),
+   grant(119) => grant_signal(119),
+   grant(120) => grant_signal(120),
+   grant(121) => grant_signal(121),
+   grant(122) => grant_signal(122),
+   grant(123) => grant_signal(123),
+   grant(124) => grant_signal(124),
+   grant(125) => grant_signal(125),
+   grant(126) => grant_signal(126),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(113) =>request_signal(113),
+   request(114) =>request_signal(114),
+   request(115) =>request_signal(115),
+   request(116) =>request_signal(116),
+   request(117) =>request_signal(117),
+   request(118) =>request_signal(118),
+   request(119) =>request_signal(119),
+   request(120) =>request_signal(120),
+   request(121) =>request_signal(121),
+   request(122) =>request_signal(122),
+   request(123) =>request_signal(123),
+   request(124) =>request_signal(124),
+   request(125) =>request_signal(125),
+   request(126) =>request_signal(126)
+);
+
+PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port10_in,
+   data_in_en => data_in_en(10),
+   reset => reset,
+   clk =>clk,
+   grant(127) => grant_signal(127),
+   grant(128) => grant_signal(128),
+   grant(129) => grant_signal(129),
+   grant(130) => grant_signal(130),
+   grant(131) => grant_signal(131),
+   grant(132) => grant_signal(132),
+   grant(133) => grant_signal(133),
+   grant(134) => grant_signal(134),
+   grant(135) => grant_signal(135),
+   grant(136) => grant_signal(136),
+   grant(137) => grant_signal(137),
+   grant(138) => grant_signal(138),
+   grant(139) => grant_signal(139),
+   grant(140) => grant_signal(140),
+   fifo_full =>fifo_in_full(10),
+   priority_rotation =>  priority_rotation_signal(10),
+   fifo_empty => fifo_in_empty(10),
+   data_out =>crossbar_in_port10,
+   data_out_pulse =>crossbar_in_pulse10,
+   request(127) =>request_signal(127),
+   request(128) =>request_signal(128),
+   request(129) =>request_signal(129),
+   request(130) =>request_signal(130),
+   request(131) =>request_signal(131),
+   request(132) =>request_signal(132),
+   request(133) =>request_signal(133),
+   request(134) =>request_signal(134),
+   request(135) =>request_signal(135),
+   request(136) =>request_signal(136),
+   request(137) =>request_signal(137),
+   request(138) =>request_signal(138),
+   request(139) =>request_signal(139),
+   request(140) =>request_signal(140)
+);
+
+PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port11_in,
+   data_in_en => data_in_en(11),
+   reset => reset,
+   clk =>clk,
+   grant(141) => grant_signal(141),
+   grant(142) => grant_signal(142),
+   grant(143) => grant_signal(143),
+   grant(144) => grant_signal(144),
+   grant(145) => grant_signal(145),
+   grant(146) => grant_signal(146),
+   grant(147) => grant_signal(147),
+   grant(148) => grant_signal(148),
+   grant(149) => grant_signal(149),
+   grant(150) => grant_signal(150),
+   grant(151) => grant_signal(151),
+   grant(152) => grant_signal(152),
+   grant(153) => grant_signal(153),
+   grant(154) => grant_signal(154),
+   fifo_full =>fifo_in_full(11),
+   priority_rotation =>  priority_rotation_signal(11),
+   fifo_empty => fifo_in_empty(11),
+   data_out =>crossbar_in_port11,
+   data_out_pulse =>crossbar_in_pulse11,
+   request(141) =>request_signal(141),
+   request(142) =>request_signal(142),
+   request(143) =>request_signal(143),
+   request(144) =>request_signal(144),
+   request(145) =>request_signal(145),
+   request(146) =>request_signal(146),
+   request(147) =>request_signal(147),
+   request(148) =>request_signal(148),
+   request(149) =>request_signal(149),
+   request(150) =>request_signal(150),
+   request(151) =>request_signal(151),
+   request(152) =>request_signal(152),
+   request(153) =>request_signal(153),
+   request(154) =>request_signal(154)
+);
+
+PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port12_in,
+   data_in_en => data_in_en(12),
+   reset => reset,
+   clk =>clk,
+   grant(155) => grant_signal(155),
+   grant(156) => grant_signal(156),
+   grant(157) => grant_signal(157),
+   grant(158) => grant_signal(158),
+   grant(159) => grant_signal(159),
+   grant(160) => grant_signal(160),
+   grant(161) => grant_signal(161),
+   grant(162) => grant_signal(162),
+   grant(163) => grant_signal(163),
+   grant(164) => grant_signal(164),
+   grant(165) => grant_signal(165),
+   grant(166) => grant_signal(166),
+   grant(167) => grant_signal(167),
+   grant(168) => grant_signal(168),
+   fifo_full =>fifo_in_full(12),
+   priority_rotation =>  priority_rotation_signal(12),
+   fifo_empty => fifo_in_empty(12),
+   data_out =>crossbar_in_port12,
+   data_out_pulse =>crossbar_in_pulse12,
+   request(155) =>request_signal(155),
+   request(156) =>request_signal(156),
+   request(157) =>request_signal(157),
+   request(158) =>request_signal(158),
+   request(159) =>request_signal(159),
+   request(160) =>request_signal(160),
+   request(161) =>request_signal(161),
+   request(162) =>request_signal(162),
+   request(163) =>request_signal(163),
+   request(164) =>request_signal(164),
+   request(165) =>request_signal(165),
+   request(166) =>request_signal(166),
+   request(167) =>request_signal(167),
+   request(168) =>request_signal(168)
+);
+
+PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port13_in,
+   data_in_en => data_in_en(13),
+   reset => reset,
+   clk =>clk,
+   grant(169) => grant_signal(169),
+   grant(170) => grant_signal(170),
+   grant(171) => grant_signal(171),
+   grant(172) => grant_signal(172),
+   grant(173) => grant_signal(173),
+   grant(174) => grant_signal(174),
+   grant(175) => grant_signal(175),
+   grant(176) => grant_signal(176),
+   grant(177) => grant_signal(177),
+   grant(178) => grant_signal(178),
+   grant(179) => grant_signal(179),
+   grant(180) => grant_signal(180),
+   grant(181) => grant_signal(181),
+   grant(182) => grant_signal(182),
+   fifo_full =>fifo_in_full(13),
+   priority_rotation =>  priority_rotation_signal(13),
+   fifo_empty => fifo_in_empty(13),
+   data_out =>crossbar_in_port13,
+   data_out_pulse =>crossbar_in_pulse13,
+   request(169) =>request_signal(169),
+   request(170) =>request_signal(170),
+   request(171) =>request_signal(171),
+   request(172) =>request_signal(172),
+   request(173) =>request_signal(173),
+   request(174) =>request_signal(174),
+   request(175) =>request_signal(175),
+   request(176) =>request_signal(176),
+   request(177) =>request_signal(177),
+   request(178) =>request_signal(178),
+   request(179) =>request_signal(179),
+   request(180) =>request_signal(180),
+   request(181) =>request_signal(181),
+   request(182) =>request_signal(182)
+);
+
+PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>14)
+PORT MAP(
+   data_in => Port14_in,
+   data_in_en => data_in_en(14),
+   reset => reset,
+   clk =>clk,
+   grant(183) => grant_signal(183),
+   grant(184) => grant_signal(184),
+   grant(185) => grant_signal(185),
+   grant(186) => grant_signal(186),
+   grant(187) => grant_signal(187),
+   grant(188) => grant_signal(188),
+   grant(189) => grant_signal(189),
+   grant(190) => grant_signal(190),
+   grant(191) => grant_signal(191),
+   grant(192) => grant_signal(192),
+   grant(193) => grant_signal(193),
+   grant(194) => grant_signal(194),
+   grant(195) => grant_signal(195),
+   grant(196) => grant_signal(196),
+   fifo_full =>fifo_in_full(14),
+   priority_rotation =>  priority_rotation_signal(14),
+   fifo_empty => fifo_in_empty(14),
+   data_out =>crossbar_in_port14,
+   data_out_pulse =>crossbar_in_pulse14,
+   request(183) =>request_signal(183),
+   request(184) =>request_signal(184),
+   request(185) =>request_signal(185),
+   request(186) =>request_signal(186),
+   request(187) =>request_signal(187),
+   request(188) =>request_signal(188),
+   request(189) =>request_signal(189),
+   request(190) =>request_signal(190),
+   request(191) =>request_signal(191),
+   request(192) =>request_signal(192),
+   request(193) =>request_signal(193),
+   request(194) =>request_signal(194),
+   request(195) =>request_signal(195),
+   request(196) =>request_signal(196)
+);
+
+end generate switch14x14;
+
+
+-- switch 15 ports
+switch15x15 : if number_of_ports = 15 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(16) => grant_signal(16),
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(16) =>request_signal(16),
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32),
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36),
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42),
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   grant(55) => grant_signal(55),
+   grant(56) => grant_signal(56),
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48),
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50),
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52),
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54),
+   request(55) =>request_signal(55),
+   request(56) =>request_signal(56),
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   grant(64) => grant_signal(64),
+   grant(65) => grant_signal(65),
+   grant(66) => grant_signal(66),
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63),
+   request(64) =>request_signal(64),
+   request(65) =>request_signal(65),
+   request(66) =>request_signal(66),
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70),
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72),
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   grant(78) => grant_signal(78),
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   grant(81) => grant_signal(81),
+   grant(82) => grant_signal(82),
+   grant(83) => grant_signal(83),
+   grant(84) => grant_signal(84),
+   grant(85) => grant_signal(85),
+   grant(86) => grant_signal(86),
+   grant(87) => grant_signal(87),
+   grant(88) => grant_signal(88),
+   grant(89) => grant_signal(89),
+   grant(90) => grant_signal(90),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77),
+   request(78) =>request_signal(78),
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80),
+   request(81) =>request_signal(81),
+   request(82) =>request_signal(82),
+   request(83) =>request_signal(83),
+   request(84) =>request_signal(84),
+   request(85) =>request_signal(85),
+   request(86) =>request_signal(86),
+   request(87) =>request_signal(87),
+   request(88) =>request_signal(88),
+   request(89) =>request_signal(89),
+   request(90) =>request_signal(90)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(91) => grant_signal(91),
+   grant(92) => grant_signal(92),
+   grant(93) => grant_signal(93),
+   grant(94) => grant_signal(94),
+   grant(95) => grant_signal(95),
+   grant(96) => grant_signal(96),
+   grant(97) => grant_signal(97),
+   grant(98) => grant_signal(98),
+   grant(99) => grant_signal(99),
+   grant(100) => grant_signal(100),
+   grant(101) => grant_signal(101),
+   grant(102) => grant_signal(102),
+   grant(103) => grant_signal(103),
+   grant(104) => grant_signal(104),
+   grant(105) => grant_signal(105),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(91) =>request_signal(91),
+   request(92) =>request_signal(92),
+   request(93) =>request_signal(93),
+   request(94) =>request_signal(94),
+   request(95) =>request_signal(95),
+   request(96) =>request_signal(96),
+   request(97) =>request_signal(97),
+   request(98) =>request_signal(98),
+   request(99) =>request_signal(99),
+   request(100) =>request_signal(100),
+   request(101) =>request_signal(101),
+   request(102) =>request_signal(102),
+   request(103) =>request_signal(103),
+   request(104) =>request_signal(104),
+   request(105) =>request_signal(105)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(106) => grant_signal(106),
+   grant(107) => grant_signal(107),
+   grant(108) => grant_signal(108),
+   grant(109) => grant_signal(109),
+   grant(110) => grant_signal(110),
+   grant(111) => grant_signal(111),
+   grant(112) => grant_signal(112),
+   grant(113) => grant_signal(113),
+   grant(114) => grant_signal(114),
+   grant(115) => grant_signal(115),
+   grant(116) => grant_signal(116),
+   grant(117) => grant_signal(117),
+   grant(118) => grant_signal(118),
+   grant(119) => grant_signal(119),
+   grant(120) => grant_signal(120),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(106) =>request_signal(106),
+   request(107) =>request_signal(107),
+   request(108) =>request_signal(108),
+   request(109) =>request_signal(109),
+   request(110) =>request_signal(110),
+   request(111) =>request_signal(111),
+   request(112) =>request_signal(112),
+   request(113) =>request_signal(113),
+   request(114) =>request_signal(114),
+   request(115) =>request_signal(115),
+   request(116) =>request_signal(116),
+   request(117) =>request_signal(117),
+   request(118) =>request_signal(118),
+   request(119) =>request_signal(119),
+   request(120) =>request_signal(120)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(121) => grant_signal(121),
+   grant(122) => grant_signal(122),
+   grant(123) => grant_signal(123),
+   grant(124) => grant_signal(124),
+   grant(125) => grant_signal(125),
+   grant(126) => grant_signal(126),
+   grant(127) => grant_signal(127),
+   grant(128) => grant_signal(128),
+   grant(129) => grant_signal(129),
+   grant(130) => grant_signal(130),
+   grant(131) => grant_signal(131),
+   grant(132) => grant_signal(132),
+   grant(133) => grant_signal(133),
+   grant(134) => grant_signal(134),
+   grant(135) => grant_signal(135),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(121) =>request_signal(121),
+   request(122) =>request_signal(122),
+   request(123) =>request_signal(123),
+   request(124) =>request_signal(124),
+   request(125) =>request_signal(125),
+   request(126) =>request_signal(126),
+   request(127) =>request_signal(127),
+   request(128) =>request_signal(128),
+   request(129) =>request_signal(129),
+   request(130) =>request_signal(130),
+   request(131) =>request_signal(131),
+   request(132) =>request_signal(132),
+   request(133) =>request_signal(133),
+   request(134) =>request_signal(134),
+   request(135) =>request_signal(135)
+);
+
+PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port10_in,
+   data_in_en => data_in_en(10),
+   reset => reset,
+   clk =>clk,
+   grant(136) => grant_signal(136),
+   grant(137) => grant_signal(137),
+   grant(138) => grant_signal(138),
+   grant(139) => grant_signal(139),
+   grant(140) => grant_signal(140),
+   grant(141) => grant_signal(141),
+   grant(142) => grant_signal(142),
+   grant(143) => grant_signal(143),
+   grant(144) => grant_signal(144),
+   grant(145) => grant_signal(145),
+   grant(146) => grant_signal(146),
+   grant(147) => grant_signal(147),
+   grant(148) => grant_signal(148),
+   grant(149) => grant_signal(149),
+   grant(150) => grant_signal(150),
+   fifo_full =>fifo_in_full(10),
+   priority_rotation =>  priority_rotation_signal(10),
+   fifo_empty => fifo_in_empty(10),
+   data_out =>crossbar_in_port10,
+   data_out_pulse =>crossbar_in_pulse10,
+   request(136) =>request_signal(136),
+   request(137) =>request_signal(137),
+   request(138) =>request_signal(138),
+   request(139) =>request_signal(139),
+   request(140) =>request_signal(140),
+   request(141) =>request_signal(141),
+   request(142) =>request_signal(142),
+   request(143) =>request_signal(143),
+   request(144) =>request_signal(144),
+   request(145) =>request_signal(145),
+   request(146) =>request_signal(146),
+   request(147) =>request_signal(147),
+   request(148) =>request_signal(148),
+   request(149) =>request_signal(149),
+   request(150) =>request_signal(150)
+);
+
+PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port11_in,
+   data_in_en => data_in_en(11),
+   reset => reset,
+   clk =>clk,
+   grant(151) => grant_signal(151),
+   grant(152) => grant_signal(152),
+   grant(153) => grant_signal(153),
+   grant(154) => grant_signal(154),
+   grant(155) => grant_signal(155),
+   grant(156) => grant_signal(156),
+   grant(157) => grant_signal(157),
+   grant(158) => grant_signal(158),
+   grant(159) => grant_signal(159),
+   grant(160) => grant_signal(160),
+   grant(161) => grant_signal(161),
+   grant(162) => grant_signal(162),
+   grant(163) => grant_signal(163),
+   grant(164) => grant_signal(164),
+   grant(165) => grant_signal(165),
+   fifo_full =>fifo_in_full(11),
+   priority_rotation =>  priority_rotation_signal(11),
+   fifo_empty => fifo_in_empty(11),
+   data_out =>crossbar_in_port11,
+   data_out_pulse =>crossbar_in_pulse11,
+   request(151) =>request_signal(151),
+   request(152) =>request_signal(152),
+   request(153) =>request_signal(153),
+   request(154) =>request_signal(154),
+   request(155) =>request_signal(155),
+   request(156) =>request_signal(156),
+   request(157) =>request_signal(157),
+   request(158) =>request_signal(158),
+   request(159) =>request_signal(159),
+   request(160) =>request_signal(160),
+   request(161) =>request_signal(161),
+   request(162) =>request_signal(162),
+   request(163) =>request_signal(163),
+   request(164) =>request_signal(164),
+   request(165) =>request_signal(165)
+);
+
+PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port12_in,
+   data_in_en => data_in_en(12),
+   reset => reset,
+   clk =>clk,
+   grant(166) => grant_signal(166),
+   grant(167) => grant_signal(167),
+   grant(168) => grant_signal(168),
+   grant(169) => grant_signal(169),
+   grant(170) => grant_signal(170),
+   grant(171) => grant_signal(171),
+   grant(172) => grant_signal(172),
+   grant(173) => grant_signal(173),
+   grant(174) => grant_signal(174),
+   grant(175) => grant_signal(175),
+   grant(176) => grant_signal(176),
+   grant(177) => grant_signal(177),
+   grant(178) => grant_signal(178),
+   grant(179) => grant_signal(179),
+   grant(180) => grant_signal(180),
+   fifo_full =>fifo_in_full(12),
+   priority_rotation =>  priority_rotation_signal(12),
+   fifo_empty => fifo_in_empty(12),
+   data_out =>crossbar_in_port12,
+   data_out_pulse =>crossbar_in_pulse12,
+   request(166) =>request_signal(166),
+   request(167) =>request_signal(167),
+   request(168) =>request_signal(168),
+   request(169) =>request_signal(169),
+   request(170) =>request_signal(170),
+   request(171) =>request_signal(171),
+   request(172) =>request_signal(172),
+   request(173) =>request_signal(173),
+   request(174) =>request_signal(174),
+   request(175) =>request_signal(175),
+   request(176) =>request_signal(176),
+   request(177) =>request_signal(177),
+   request(178) =>request_signal(178),
+   request(179) =>request_signal(179),
+   request(180) =>request_signal(180)
+);
+
+PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port13_in,
+   data_in_en => data_in_en(13),
+   reset => reset,
+   clk =>clk,
+   grant(181) => grant_signal(181),
+   grant(182) => grant_signal(182),
+   grant(183) => grant_signal(183),
+   grant(184) => grant_signal(184),
+   grant(185) => grant_signal(185),
+   grant(186) => grant_signal(186),
+   grant(187) => grant_signal(187),
+   grant(188) => grant_signal(188),
+   grant(189) => grant_signal(189),
+   grant(190) => grant_signal(190),
+   grant(191) => grant_signal(191),
+   grant(192) => grant_signal(192),
+   grant(193) => grant_signal(193),
+   grant(194) => grant_signal(194),
+   grant(195) => grant_signal(195),
+   fifo_full =>fifo_in_full(13),
+   priority_rotation =>  priority_rotation_signal(13),
+   fifo_empty => fifo_in_empty(13),
+   data_out =>crossbar_in_port13,
+   data_out_pulse =>crossbar_in_pulse13,
+   request(181) =>request_signal(181),
+   request(182) =>request_signal(182),
+   request(183) =>request_signal(183),
+   request(184) =>request_signal(184),
+   request(185) =>request_signal(185),
+   request(186) =>request_signal(186),
+   request(187) =>request_signal(187),
+   request(188) =>request_signal(188),
+   request(189) =>request_signal(189),
+   request(190) =>request_signal(190),
+   request(191) =>request_signal(191),
+   request(192) =>request_signal(192),
+   request(193) =>request_signal(193),
+   request(194) =>request_signal(194),
+   request(195) =>request_signal(195)
+);
+
+PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port14_in,
+   data_in_en => data_in_en(14),
+   reset => reset,
+   clk =>clk,
+   grant(196) => grant_signal(196),
+   grant(197) => grant_signal(197),
+   grant(198) => grant_signal(198),
+   grant(199) => grant_signal(199),
+   grant(200) => grant_signal(200),
+   grant(201) => grant_signal(201),
+   grant(202) => grant_signal(202),
+   grant(203) => grant_signal(203),
+   grant(204) => grant_signal(204),
+   grant(205) => grant_signal(205),
+   grant(206) => grant_signal(206),
+   grant(207) => grant_signal(207),
+   grant(208) => grant_signal(208),
+   grant(209) => grant_signal(209),
+   grant(210) => grant_signal(210),
+   fifo_full =>fifo_in_full(14),
+   priority_rotation =>  priority_rotation_signal(14),
+   fifo_empty => fifo_in_empty(14),
+   data_out =>crossbar_in_port14,
+   data_out_pulse =>crossbar_in_pulse14,
+   request(196) =>request_signal(196),
+   request(197) =>request_signal(197),
+   request(198) =>request_signal(198),
+   request(199) =>request_signal(199),
+   request(200) =>request_signal(200),
+   request(201) =>request_signal(201),
+   request(202) =>request_signal(202),
+   request(203) =>request_signal(203),
+   request(204) =>request_signal(204),
+   request(205) =>request_signal(205),
+   request(206) =>request_signal(206),
+   request(207) =>request_signal(207),
+   request(208) =>request_signal(208),
+   request(209) =>request_signal(209),
+   request(210) =>request_signal(210)
+);
+
+PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>15)
+PORT MAP(
+   data_in => Port15_in,
+   data_in_en => data_in_en(15),
+   reset => reset,
+   clk =>clk,
+   grant(211) => grant_signal(211),
+   grant(212) => grant_signal(212),
+   grant(213) => grant_signal(213),
+   grant(214) => grant_signal(214),
+   grant(215) => grant_signal(215),
+   grant(216) => grant_signal(216),
+   grant(217) => grant_signal(217),
+   grant(218) => grant_signal(218),
+   grant(219) => grant_signal(219),
+   grant(220) => grant_signal(220),
+   grant(221) => grant_signal(221),
+   grant(222) => grant_signal(222),
+   grant(223) => grant_signal(223),
+   grant(224) => grant_signal(224),
+   grant(225) => grant_signal(225),
+   fifo_full =>fifo_in_full(15),
+   priority_rotation =>  priority_rotation_signal(15),
+   fifo_empty => fifo_in_empty(15),
+   data_out =>crossbar_in_port15,
+   data_out_pulse =>crossbar_in_pulse15,
+   request(211) =>request_signal(211),
+   request(212) =>request_signal(212),
+   request(213) =>request_signal(213),
+   request(214) =>request_signal(214),
+   request(215) =>request_signal(215),
+   request(216) =>request_signal(216),
+   request(217) =>request_signal(217),
+   request(218) =>request_signal(218),
+   request(219) =>request_signal(219),
+   request(220) =>request_signal(220),
+   request(221) =>request_signal(221),
+   request(222) =>request_signal(222),
+   request(223) =>request_signal(223),
+   request(224) =>request_signal(224),
+   request(225) =>request_signal(225)
+);
+
+end generate switch15x15;
+
+
+-- switch 16 ports
+switch16x16 : if number_of_ports = 16 generate
+
+PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port1_in,
+   data_in_en => data_in_en(1),
+   reset => reset,
+   clk =>clk,
+   grant(1) => grant_signal(1),
+   grant(2) => grant_signal(2),
+   grant(3) => grant_signal(3),
+   grant(4) => grant_signal(4),
+   grant(5) => grant_signal(5),
+   grant(6) => grant_signal(6),
+   grant(7) => grant_signal(7),
+   grant(8) => grant_signal(8),
+   grant(9) => grant_signal(9),
+   grant(10) => grant_signal(10),
+   grant(11) => grant_signal(11),
+   grant(12) => grant_signal(12),
+   grant(13) => grant_signal(13),
+   grant(14) => grant_signal(14),
+   grant(15) => grant_signal(15),
+   grant(16) => grant_signal(16),
+   fifo_full =>fifo_in_full(1),
+   priority_rotation =>  priority_rotation_signal(1),
+   fifo_empty => fifo_in_empty(1),
+   data_out =>crossbar_in_port1,
+   data_out_pulse =>crossbar_in_pulse1,
+   request(1) =>request_signal(1),
+   request(2) =>request_signal(2),
+   request(3) =>request_signal(3),
+   request(4) =>request_signal(4),
+   request(5) =>request_signal(5),
+   request(6) =>request_signal(6),
+   request(7) =>request_signal(7),
+   request(8) =>request_signal(8),
+   request(9) =>request_signal(9),
+   request(10) =>request_signal(10),
+   request(11) =>request_signal(11),
+   request(12) =>request_signal(12),
+   request(13) =>request_signal(13),
+   request(14) =>request_signal(14),
+   request(15) =>request_signal(15),
+   request(16) =>request_signal(16)
+);
+
+PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port2_in,
+   data_in_en => data_in_en(2),
+   reset => reset,
+   clk =>clk,
+   grant(17) => grant_signal(17),
+   grant(18) => grant_signal(18),
+   grant(19) => grant_signal(19),
+   grant(20) => grant_signal(20),
+   grant(21) => grant_signal(21),
+   grant(22) => grant_signal(22),
+   grant(23) => grant_signal(23),
+   grant(24) => grant_signal(24),
+   grant(25) => grant_signal(25),
+   grant(26) => grant_signal(26),
+   grant(27) => grant_signal(27),
+   grant(28) => grant_signal(28),
+   grant(29) => grant_signal(29),
+   grant(30) => grant_signal(30),
+   grant(31) => grant_signal(31),
+   grant(32) => grant_signal(32),
+   fifo_full =>fifo_in_full(2),
+   priority_rotation =>  priority_rotation_signal(2),
+   fifo_empty => fifo_in_empty(2),
+   data_out =>crossbar_in_port2,
+   data_out_pulse =>crossbar_in_pulse2,
+   request(17) =>request_signal(17),
+   request(18) =>request_signal(18),
+   request(19) =>request_signal(19),
+   request(20) =>request_signal(20),
+   request(21) =>request_signal(21),
+   request(22) =>request_signal(22),
+   request(23) =>request_signal(23),
+   request(24) =>request_signal(24),
+   request(25) =>request_signal(25),
+   request(26) =>request_signal(26),
+   request(27) =>request_signal(27),
+   request(28) =>request_signal(28),
+   request(29) =>request_signal(29),
+   request(30) =>request_signal(30),
+   request(31) =>request_signal(31),
+   request(32) =>request_signal(32)
+);
+
+PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port3_in,
+   data_in_en => data_in_en(3),
+   reset => reset,
+   clk =>clk,
+   grant(33) => grant_signal(33),
+   grant(34) => grant_signal(34),
+   grant(35) => grant_signal(35),
+   grant(36) => grant_signal(36),
+   grant(37) => grant_signal(37),
+   grant(38) => grant_signal(38),
+   grant(39) => grant_signal(39),
+   grant(40) => grant_signal(40),
+   grant(41) => grant_signal(41),
+   grant(42) => grant_signal(42),
+   grant(43) => grant_signal(43),
+   grant(44) => grant_signal(44),
+   grant(45) => grant_signal(45),
+   grant(46) => grant_signal(46),
+   grant(47) => grant_signal(47),
+   grant(48) => grant_signal(48),
+   fifo_full =>fifo_in_full(3),
+   priority_rotation =>  priority_rotation_signal(3),
+   fifo_empty => fifo_in_empty(3),
+   data_out =>crossbar_in_port3,
+   data_out_pulse =>crossbar_in_pulse3,
+   request(33) =>request_signal(33),
+   request(34) =>request_signal(34),
+   request(35) =>request_signal(35),
+   request(36) =>request_signal(36),
+   request(37) =>request_signal(37),
+   request(38) =>request_signal(38),
+   request(39) =>request_signal(39),
+   request(40) =>request_signal(40),
+   request(41) =>request_signal(41),
+   request(42) =>request_signal(42),
+   request(43) =>request_signal(43),
+   request(44) =>request_signal(44),
+   request(45) =>request_signal(45),
+   request(46) =>request_signal(46),
+   request(47) =>request_signal(47),
+   request(48) =>request_signal(48)
+);
+
+PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port4_in,
+   data_in_en => data_in_en(4),
+   reset => reset,
+   clk =>clk,
+   grant(49) => grant_signal(49),
+   grant(50) => grant_signal(50),
+   grant(51) => grant_signal(51),
+   grant(52) => grant_signal(52),
+   grant(53) => grant_signal(53),
+   grant(54) => grant_signal(54),
+   grant(55) => grant_signal(55),
+   grant(56) => grant_signal(56),
+   grant(57) => grant_signal(57),
+   grant(58) => grant_signal(58),
+   grant(59) => grant_signal(59),
+   grant(60) => grant_signal(60),
+   grant(61) => grant_signal(61),
+   grant(62) => grant_signal(62),
+   grant(63) => grant_signal(63),
+   grant(64) => grant_signal(64),
+   fifo_full =>fifo_in_full(4),
+   priority_rotation =>  priority_rotation_signal(4),
+   fifo_empty => fifo_in_empty(4),
+   data_out =>crossbar_in_port4,
+   data_out_pulse =>crossbar_in_pulse4,
+   request(49) =>request_signal(49),
+   request(50) =>request_signal(50),
+   request(51) =>request_signal(51),
+   request(52) =>request_signal(52),
+   request(53) =>request_signal(53),
+   request(54) =>request_signal(54),
+   request(55) =>request_signal(55),
+   request(56) =>request_signal(56),
+   request(57) =>request_signal(57),
+   request(58) =>request_signal(58),
+   request(59) =>request_signal(59),
+   request(60) =>request_signal(60),
+   request(61) =>request_signal(61),
+   request(62) =>request_signal(62),
+   request(63) =>request_signal(63),
+   request(64) =>request_signal(64)
+);
+
+PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port5_in,
+   data_in_en => data_in_en(5),
+   reset => reset,
+   clk =>clk,
+   grant(65) => grant_signal(65),
+   grant(66) => grant_signal(66),
+   grant(67) => grant_signal(67),
+   grant(68) => grant_signal(68),
+   grant(69) => grant_signal(69),
+   grant(70) => grant_signal(70),
+   grant(71) => grant_signal(71),
+   grant(72) => grant_signal(72),
+   grant(73) => grant_signal(73),
+   grant(74) => grant_signal(74),
+   grant(75) => grant_signal(75),
+   grant(76) => grant_signal(76),
+   grant(77) => grant_signal(77),
+   grant(78) => grant_signal(78),
+   grant(79) => grant_signal(79),
+   grant(80) => grant_signal(80),
+   fifo_full =>fifo_in_full(5),
+   priority_rotation =>  priority_rotation_signal(5),
+   fifo_empty => fifo_in_empty(5),
+   data_out =>crossbar_in_port5,
+   data_out_pulse =>crossbar_in_pulse5,
+   request(65) =>request_signal(65),
+   request(66) =>request_signal(66),
+   request(67) =>request_signal(67),
+   request(68) =>request_signal(68),
+   request(69) =>request_signal(69),
+   request(70) =>request_signal(70),
+   request(71) =>request_signal(71),
+   request(72) =>request_signal(72),
+   request(73) =>request_signal(73),
+   request(74) =>request_signal(74),
+   request(75) =>request_signal(75),
+   request(76) =>request_signal(76),
+   request(77) =>request_signal(77),
+   request(78) =>request_signal(78),
+   request(79) =>request_signal(79),
+   request(80) =>request_signal(80)
+);
+
+PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port6_in,
+   data_in_en => data_in_en(6),
+   reset => reset,
+   clk =>clk,
+   grant(81) => grant_signal(81),
+   grant(82) => grant_signal(82),
+   grant(83) => grant_signal(83),
+   grant(84) => grant_signal(84),
+   grant(85) => grant_signal(85),
+   grant(86) => grant_signal(86),
+   grant(87) => grant_signal(87),
+   grant(88) => grant_signal(88),
+   grant(89) => grant_signal(89),
+   grant(90) => grant_signal(90),
+   grant(91) => grant_signal(91),
+   grant(92) => grant_signal(92),
+   grant(93) => grant_signal(93),
+   grant(94) => grant_signal(94),
+   grant(95) => grant_signal(95),
+   grant(96) => grant_signal(96),
+   fifo_full =>fifo_in_full(6),
+   priority_rotation =>  priority_rotation_signal(6),
+   fifo_empty => fifo_in_empty(6),
+   data_out =>crossbar_in_port6,
+   data_out_pulse =>crossbar_in_pulse6,
+   request(81) =>request_signal(81),
+   request(82) =>request_signal(82),
+   request(83) =>request_signal(83),
+   request(84) =>request_signal(84),
+   request(85) =>request_signal(85),
+   request(86) =>request_signal(86),
+   request(87) =>request_signal(87),
+   request(88) =>request_signal(88),
+   request(89) =>request_signal(89),
+   request(90) =>request_signal(90),
+   request(91) =>request_signal(91),
+   request(92) =>request_signal(92),
+   request(93) =>request_signal(93),
+   request(94) =>request_signal(94),
+   request(95) =>request_signal(95),
+   request(96) =>request_signal(96)
+);
+
+PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port7_in,
+   data_in_en => data_in_en(7),
+   reset => reset,
+   clk =>clk,
+   grant(97) => grant_signal(97),
+   grant(98) => grant_signal(98),
+   grant(99) => grant_signal(99),
+   grant(100) => grant_signal(100),
+   grant(101) => grant_signal(101),
+   grant(102) => grant_signal(102),
+   grant(103) => grant_signal(103),
+   grant(104) => grant_signal(104),
+   grant(105) => grant_signal(105),
+   grant(106) => grant_signal(106),
+   grant(107) => grant_signal(107),
+   grant(108) => grant_signal(108),
+   grant(109) => grant_signal(109),
+   grant(110) => grant_signal(110),
+   grant(111) => grant_signal(111),
+   grant(112) => grant_signal(112),
+   fifo_full =>fifo_in_full(7),
+   priority_rotation =>  priority_rotation_signal(7),
+   fifo_empty => fifo_in_empty(7),
+   data_out =>crossbar_in_port7,
+   data_out_pulse =>crossbar_in_pulse7,
+   request(97) =>request_signal(97),
+   request(98) =>request_signal(98),
+   request(99) =>request_signal(99),
+   request(100) =>request_signal(100),
+   request(101) =>request_signal(101),
+   request(102) =>request_signal(102),
+   request(103) =>request_signal(103),
+   request(104) =>request_signal(104),
+   request(105) =>request_signal(105),
+   request(106) =>request_signal(106),
+   request(107) =>request_signal(107),
+   request(108) =>request_signal(108),
+   request(109) =>request_signal(109),
+   request(110) =>request_signal(110),
+   request(111) =>request_signal(111),
+   request(112) =>request_signal(112)
+);
+
+PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port8_in,
+   data_in_en => data_in_en(8),
+   reset => reset,
+   clk =>clk,
+   grant(113) => grant_signal(113),
+   grant(114) => grant_signal(114),
+   grant(115) => grant_signal(115),
+   grant(116) => grant_signal(116),
+   grant(117) => grant_signal(117),
+   grant(118) => grant_signal(118),
+   grant(119) => grant_signal(119),
+   grant(120) => grant_signal(120),
+   grant(121) => grant_signal(121),
+   grant(122) => grant_signal(122),
+   grant(123) => grant_signal(123),
+   grant(124) => grant_signal(124),
+   grant(125) => grant_signal(125),
+   grant(126) => grant_signal(126),
+   grant(127) => grant_signal(127),
+   grant(128) => grant_signal(128),
+   fifo_full =>fifo_in_full(8),
+   priority_rotation =>  priority_rotation_signal(8),
+   fifo_empty => fifo_in_empty(8),
+   data_out =>crossbar_in_port8,
+   data_out_pulse =>crossbar_in_pulse8,
+   request(113) =>request_signal(113),
+   request(114) =>request_signal(114),
+   request(115) =>request_signal(115),
+   request(116) =>request_signal(116),
+   request(117) =>request_signal(117),
+   request(118) =>request_signal(118),
+   request(119) =>request_signal(119),
+   request(120) =>request_signal(120),
+   request(121) =>request_signal(121),
+   request(122) =>request_signal(122),
+   request(123) =>request_signal(123),
+   request(124) =>request_signal(124),
+   request(125) =>request_signal(125),
+   request(126) =>request_signal(126),
+   request(127) =>request_signal(127),
+   request(128) =>request_signal(128)
+);
+
+PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port9_in,
+   data_in_en => data_in_en(9),
+   reset => reset,
+   clk =>clk,
+   grant(129) => grant_signal(129),
+   grant(130) => grant_signal(130),
+   grant(131) => grant_signal(131),
+   grant(132) => grant_signal(132),
+   grant(133) => grant_signal(133),
+   grant(134) => grant_signal(134),
+   grant(135) => grant_signal(135),
+   grant(136) => grant_signal(136),
+   grant(137) => grant_signal(137),
+   grant(138) => grant_signal(138),
+   grant(139) => grant_signal(139),
+   grant(140) => grant_signal(140),
+   grant(141) => grant_signal(141),
+   grant(142) => grant_signal(142),
+   grant(143) => grant_signal(143),
+   grant(144) => grant_signal(144),
+   fifo_full =>fifo_in_full(9),
+   priority_rotation =>  priority_rotation_signal(9),
+   fifo_empty => fifo_in_empty(9),
+   data_out =>crossbar_in_port9,
+   data_out_pulse =>crossbar_in_pulse9,
+   request(129) =>request_signal(129),
+   request(130) =>request_signal(130),
+   request(131) =>request_signal(131),
+   request(132) =>request_signal(132),
+   request(133) =>request_signal(133),
+   request(134) =>request_signal(134),
+   request(135) =>request_signal(135),
+   request(136) =>request_signal(136),
+   request(137) =>request_signal(137),
+   request(138) =>request_signal(138),
+   request(139) =>request_signal(139),
+   request(140) =>request_signal(140),
+   request(141) =>request_signal(141),
+   request(142) =>request_signal(142),
+   request(143) =>request_signal(143),
+   request(144) =>request_signal(144)
+);
+
+PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port10_in,
+   data_in_en => data_in_en(10),
+   reset => reset,
+   clk =>clk,
+   grant(145) => grant_signal(145),
+   grant(146) => grant_signal(146),
+   grant(147) => grant_signal(147),
+   grant(148) => grant_signal(148),
+   grant(149) => grant_signal(149),
+   grant(150) => grant_signal(150),
+   grant(151) => grant_signal(151),
+   grant(152) => grant_signal(152),
+   grant(153) => grant_signal(153),
+   grant(154) => grant_signal(154),
+   grant(155) => grant_signal(155),
+   grant(156) => grant_signal(156),
+   grant(157) => grant_signal(157),
+   grant(158) => grant_signal(158),
+   grant(159) => grant_signal(159),
+   grant(160) => grant_signal(160),
+   fifo_full =>fifo_in_full(10),
+   priority_rotation =>  priority_rotation_signal(10),
+   fifo_empty => fifo_in_empty(10),
+   data_out =>crossbar_in_port10,
+   data_out_pulse =>crossbar_in_pulse10,
+   request(145) =>request_signal(145),
+   request(146) =>request_signal(146),
+   request(147) =>request_signal(147),
+   request(148) =>request_signal(148),
+   request(149) =>request_signal(149),
+   request(150) =>request_signal(150),
+   request(151) =>request_signal(151),
+   request(152) =>request_signal(152),
+   request(153) =>request_signal(153),
+   request(154) =>request_signal(154),
+   request(155) =>request_signal(155),
+   request(156) =>request_signal(156),
+   request(157) =>request_signal(157),
+   request(158) =>request_signal(158),
+   request(159) =>request_signal(159),
+   request(160) =>request_signal(160)
+);
+
+PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port11_in,
+   data_in_en => data_in_en(11),
+   reset => reset,
+   clk =>clk,
+   grant(161) => grant_signal(161),
+   grant(162) => grant_signal(162),
+   grant(163) => grant_signal(163),
+   grant(164) => grant_signal(164),
+   grant(165) => grant_signal(165),
+   grant(166) => grant_signal(166),
+   grant(167) => grant_signal(167),
+   grant(168) => grant_signal(168),
+   grant(169) => grant_signal(169),
+   grant(170) => grant_signal(170),
+   grant(171) => grant_signal(171),
+   grant(172) => grant_signal(172),
+   grant(173) => grant_signal(173),
+   grant(174) => grant_signal(174),
+   grant(175) => grant_signal(175),
+   grant(176) => grant_signal(176),
+   fifo_full =>fifo_in_full(11),
+   priority_rotation =>  priority_rotation_signal(11),
+   fifo_empty => fifo_in_empty(11),
+   data_out =>crossbar_in_port11,
+   data_out_pulse =>crossbar_in_pulse11,
+   request(161) =>request_signal(161),
+   request(162) =>request_signal(162),
+   request(163) =>request_signal(163),
+   request(164) =>request_signal(164),
+   request(165) =>request_signal(165),
+   request(166) =>request_signal(166),
+   request(167) =>request_signal(167),
+   request(168) =>request_signal(168),
+   request(169) =>request_signal(169),
+   request(170) =>request_signal(170),
+   request(171) =>request_signal(171),
+   request(172) =>request_signal(172),
+   request(173) =>request_signal(173),
+   request(174) =>request_signal(174),
+   request(175) =>request_signal(175),
+   request(176) =>request_signal(176)
+);
+
+PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port12_in,
+   data_in_en => data_in_en(12),
+   reset => reset,
+   clk =>clk,
+   grant(177) => grant_signal(177),
+   grant(178) => grant_signal(178),
+   grant(179) => grant_signal(179),
+   grant(180) => grant_signal(180),
+   grant(181) => grant_signal(181),
+   grant(182) => grant_signal(182),
+   grant(183) => grant_signal(183),
+   grant(184) => grant_signal(184),
+   grant(185) => grant_signal(185),
+   grant(186) => grant_signal(186),
+   grant(187) => grant_signal(187),
+   grant(188) => grant_signal(188),
+   grant(189) => grant_signal(189),
+   grant(190) => grant_signal(190),
+   grant(191) => grant_signal(191),
+   grant(192) => grant_signal(192),
+   fifo_full =>fifo_in_full(12),
+   priority_rotation =>  priority_rotation_signal(12),
+   fifo_empty => fifo_in_empty(12),
+   data_out =>crossbar_in_port12,
+   data_out_pulse =>crossbar_in_pulse12,
+   request(177) =>request_signal(177),
+   request(178) =>request_signal(178),
+   request(179) =>request_signal(179),
+   request(180) =>request_signal(180),
+   request(181) =>request_signal(181),
+   request(182) =>request_signal(182),
+   request(183) =>request_signal(183),
+   request(184) =>request_signal(184),
+   request(185) =>request_signal(185),
+   request(186) =>request_signal(186),
+   request(187) =>request_signal(187),
+   request(188) =>request_signal(188),
+   request(189) =>request_signal(189),
+   request(190) =>request_signal(190),
+   request(191) =>request_signal(191),
+   request(192) =>request_signal(192)
+);
+
+PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port13_in,
+   data_in_en => data_in_en(13),
+   reset => reset,
+   clk =>clk,
+   grant(193) => grant_signal(193),
+   grant(194) => grant_signal(194),
+   grant(195) => grant_signal(195),
+   grant(196) => grant_signal(196),
+   grant(197) => grant_signal(197),
+   grant(198) => grant_signal(198),
+   grant(199) => grant_signal(199),
+   grant(200) => grant_signal(200),
+   grant(201) => grant_signal(201),
+   grant(202) => grant_signal(202),
+   grant(203) => grant_signal(203),
+   grant(204) => grant_signal(204),
+   grant(205) => grant_signal(205),
+   grant(206) => grant_signal(206),
+   grant(207) => grant_signal(207),
+   grant(208) => grant_signal(208),
+   fifo_full =>fifo_in_full(13),
+   priority_rotation =>  priority_rotation_signal(13),
+   fifo_empty => fifo_in_empty(13),
+   data_out =>crossbar_in_port13,
+   data_out_pulse =>crossbar_in_pulse13,
+   request(193) =>request_signal(193),
+   request(194) =>request_signal(194),
+   request(195) =>request_signal(195),
+   request(196) =>request_signal(196),
+   request(197) =>request_signal(197),
+   request(198) =>request_signal(198),
+   request(199) =>request_signal(199),
+   request(200) =>request_signal(200),
+   request(201) =>request_signal(201),
+   request(202) =>request_signal(202),
+   request(203) =>request_signal(203),
+   request(204) =>request_signal(204),
+   request(205) =>request_signal(205),
+   request(206) =>request_signal(206),
+   request(207) =>request_signal(207),
+   request(208) =>request_signal(208)
+);
+
+PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port14_in,
+   data_in_en => data_in_en(14),
+   reset => reset,
+   clk =>clk,
+   grant(209) => grant_signal(209),
+   grant(210) => grant_signal(210),
+   grant(211) => grant_signal(211),
+   grant(212) => grant_signal(212),
+   grant(213) => grant_signal(213),
+   grant(214) => grant_signal(214),
+   grant(215) => grant_signal(215),
+   grant(216) => grant_signal(216),
+   grant(217) => grant_signal(217),
+   grant(218) => grant_signal(218),
+   grant(219) => grant_signal(219),
+   grant(220) => grant_signal(220),
+   grant(221) => grant_signal(221),
+   grant(222) => grant_signal(222),
+   grant(223) => grant_signal(223),
+   grant(224) => grant_signal(224),
+   fifo_full =>fifo_in_full(14),
+   priority_rotation =>  priority_rotation_signal(14),
+   fifo_empty => fifo_in_empty(14),
+   data_out =>crossbar_in_port14,
+   data_out_pulse =>crossbar_in_pulse14,
+   request(209) =>request_signal(209),
+   request(210) =>request_signal(210),
+   request(211) =>request_signal(211),
+   request(212) =>request_signal(212),
+   request(213) =>request_signal(213),
+   request(214) =>request_signal(214),
+   request(215) =>request_signal(215),
+   request(216) =>request_signal(216),
+   request(217) =>request_signal(217),
+   request(218) =>request_signal(218),
+   request(219) =>request_signal(219),
+   request(220) =>request_signal(220),
+   request(221) =>request_signal(221),
+   request(222) =>request_signal(222),
+   request(223) =>request_signal(223),
+   request(224) =>request_signal(224)
+);
+
+PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port15_in,
+   data_in_en => data_in_en(15),
+   reset => reset,
+   clk =>clk,
+   grant(225) => grant_signal(225),
+   grant(226) => grant_signal(226),
+   grant(227) => grant_signal(227),
+   grant(228) => grant_signal(228),
+   grant(229) => grant_signal(229),
+   grant(230) => grant_signal(230),
+   grant(231) => grant_signal(231),
+   grant(232) => grant_signal(232),
+   grant(233) => grant_signal(233),
+   grant(234) => grant_signal(234),
+   grant(235) => grant_signal(235),
+   grant(236) => grant_signal(236),
+   grant(237) => grant_signal(237),
+   grant(238) => grant_signal(238),
+   grant(239) => grant_signal(239),
+   grant(240) => grant_signal(240),
+   fifo_full =>fifo_in_full(15),
+   priority_rotation =>  priority_rotation_signal(15),
+   fifo_empty => fifo_in_empty(15),
+   data_out =>crossbar_in_port15,
+   data_out_pulse =>crossbar_in_pulse15,
+   request(225) =>request_signal(225),
+   request(226) =>request_signal(226),
+   request(227) =>request_signal(227),
+   request(228) =>request_signal(228),
+   request(229) =>request_signal(229),
+   request(230) =>request_signal(230),
+   request(231) =>request_signal(231),
+   request(232) =>request_signal(232),
+   request(233) =>request_signal(233),
+   request(234) =>request_signal(234),
+   request(235) =>request_signal(235),
+   request(236) =>request_signal(236),
+   request(237) =>request_signal(237),
+   request(238) =>request_signal(238),
+   request(239) =>request_signal(239),
+   request(240) =>request_signal(240)
+);
+
+PORT16_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
+GENERIC MAP(number_of_ports =>16)
+PORT MAP(
+   data_in => Port16_in,
+   data_in_en => data_in_en(16),
+   reset => reset,
+   clk =>clk,
+   grant(241) => grant_signal(241),
+   grant(242) => grant_signal(242),
+   grant(243) => grant_signal(243),
+   grant(244) => grant_signal(244),
+   grant(245) => grant_signal(245),
+   grant(246) => grant_signal(246),
+   grant(247) => grant_signal(247),
+   grant(248) => grant_signal(248),
+   grant(249) => grant_signal(249),
+   grant(250) => grant_signal(250),
+   grant(251) => grant_signal(251),
+   grant(252) => grant_signal(252),
+   grant(253) => grant_signal(253),
+   grant(254) => grant_signal(254),
+   grant(255) => grant_signal(255),
+   grant(256) => grant_signal(256),
+   fifo_full =>fifo_in_full(16),
+   priority_rotation =>  priority_rotation_signal(16),
+   fifo_empty => fifo_in_empty(16),
+   data_out =>crossbar_in_port16,
+   data_out_pulse =>crossbar_in_pulse16,
+   request(241) =>request_signal(241),
+   request(242) =>request_signal(242),
+   request(243) =>request_signal(243),
+   request(244) =>request_signal(244),
+   request(245) =>request_signal(245),
+   request(246) =>request_signal(246),
+   request(247) =>request_signal(247),
+   request(248) =>request_signal(248),
+   request(249) =>request_signal(249),
+   request(250) =>request_signal(250),
+   request(251) =>request_signal(251),
+   request(252) =>request_signal(252),
+   request(253) =>request_signal(253),
+   request(254) =>request_signal(254),
+   request(255) =>request_signal(255),
+   request(256) =>request_signal(256)
+);
+
+end generate switch16x16;
+-- intstanciation et connexion des modules des ports de sorties fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+port_out_switch2x2 : if number_of_ports = 2 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+end generate port_out_switch2x2;
+
+
+-- switch 3 ports
+port_out_switch3x3 : if number_of_ports = 3 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+end generate port_out_switch3x3;
+
+
+-- switch 4 ports
+port_out_switch4x4 : if number_of_ports = 4 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+end generate port_out_switch4x4;
+
+
+-- switch 5 ports
+port_out_switch5x5 : if number_of_ports = 5 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+end generate port_out_switch5x5;
+
+
+-- switch 6 ports
+port_out_switch6x6 : if number_of_ports = 6 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+end generate port_out_switch6x6;
+
+
+-- switch 7 ports
+port_out_switch7x7 : if number_of_ports = 7 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+end generate port_out_switch7x7;
+
+
+-- switch 8 ports
+port_out_switch8x8 : if number_of_ports = 8 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+end generate port_out_switch8x8;
+
+
+-- switch 9 ports
+port_out_switch9x9 : if number_of_ports = 9 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+end generate port_out_switch9x9;
+
+
+-- switch 10 ports
+port_out_switch10x10 : if number_of_ports = 10 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port10,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse10,
+     data_out =>Port10_out,
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+end generate port_out_switch10x10;
+
+
+-- switch 11 ports
+port_out_switch11x11 : if number_of_ports = 11 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port10,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse10,
+     data_out =>Port10_out,
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port11,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse11,
+     data_out =>Port11_out,
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+end generate port_out_switch11x11;
+
+
+-- switch 12 ports
+port_out_switch12x12 : if number_of_ports = 12 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port10,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse10,
+     data_out =>Port10_out,
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port11,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse11,
+     data_out =>Port11_out,
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port12,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse12,
+     data_out =>Port12_out,
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+end generate port_out_switch12x12;
+
+
+-- switch 13 ports
+port_out_switch13x13 : if number_of_ports = 13 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port10,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse10,
+     data_out =>Port10_out,
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port11,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse11,
+     data_out =>Port11_out,
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port12,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse12,
+     data_out =>Port12_out,
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port13,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse13,
+     data_out =>Port13_out,
+     fifo_full =>fifo_out_full_signal(13),
+     data_avalaible => data_available(13),
+     rd_out_en => data_out_en(13)
+    );
+
+end generate port_out_switch13x13;
+
+
+-- switch 14 ports
+port_out_switch14x14 : if number_of_ports = 14 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port10,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse10,
+     data_out =>Port10_out,
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port11,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse11,
+     data_out =>Port11_out,
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port12,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse12,
+     data_out =>Port12_out,
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port13,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse13,
+     data_out =>Port13_out,
+     fifo_full =>fifo_out_full_signal(13),
+     data_avalaible => data_available(13),
+     rd_out_en => data_out_en(13)
+    );
+
+PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port14,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse14,
+     data_out =>Port14_out,
+     fifo_full =>fifo_out_full_signal(14),
+     data_avalaible => data_available(14),
+     rd_out_en => data_out_en(14)
+    );
+
+end generate port_out_switch14x14;
+
+
+-- switch 15 ports
+port_out_switch15x15 : if number_of_ports = 15 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port10,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse10,
+     data_out =>Port10_out,
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port11,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse11,
+     data_out =>Port11_out,
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port12,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse12,
+     data_out =>Port12_out,
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port13,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse13,
+     data_out =>Port13_out,
+     fifo_full =>fifo_out_full_signal(13),
+     data_avalaible => data_available(13),
+     rd_out_en => data_out_en(13)
+    );
+
+PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port14,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse14,
+     data_out =>Port14_out,
+     fifo_full =>fifo_out_full_signal(14),
+     data_avalaible => data_available(14),
+     rd_out_en => data_out_en(14)
+    );
+
+PORT15_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port15,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse15,
+     data_out =>Port15_out,
+     fifo_full =>fifo_out_full_signal(15),
+     data_avalaible => data_available(15),
+     rd_out_en => data_out_en(15)
+    );
+
+end generate port_out_switch15x15;
+
+
+-- switch 16 ports
+port_out_switch16x16 : if number_of_ports = 16 generate
+
+PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port1,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse1,
+     data_out =>Port1_out,
+     fifo_full =>fifo_out_full_signal(1),
+     data_avalaible => data_available(1),
+     rd_out_en => data_out_en(1)
+    );
+
+PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port2,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse2,
+     data_out =>Port2_out,
+     fifo_full =>fifo_out_full_signal(2),
+     data_avalaible => data_available(2),
+     rd_out_en => data_out_en(2)
+    );
+
+PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port3,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse3,
+     data_out =>Port3_out,
+     fifo_full =>fifo_out_full_signal(3),
+     data_avalaible => data_available(3),
+     rd_out_en => data_out_en(3)
+    );
+
+PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port4,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse4,
+     data_out =>Port4_out,
+     fifo_full =>fifo_out_full_signal(4),
+     data_avalaible => data_available(4),
+     rd_out_en => data_out_en(4)
+    );
+
+PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port5,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse5,
+     data_out =>Port5_out,
+     fifo_full =>fifo_out_full_signal(5),
+     data_avalaible => data_available(5),
+     rd_out_en => data_out_en(5)
+    );
+
+PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port6,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse6,
+     data_out =>Port6_out,
+     fifo_full =>fifo_out_full_signal(6),
+     data_avalaible => data_available(6),
+     rd_out_en => data_out_en(6)
+    );
+
+PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port7,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse7,
+     data_out =>Port7_out,
+     fifo_full =>fifo_out_full_signal(7),
+     data_avalaible => data_available(7),
+     rd_out_en => data_out_en(7)
+    );
+
+PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port8,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse8,
+     data_out =>Port8_out,
+     fifo_full =>fifo_out_full_signal(8),
+     data_avalaible => data_available(8),
+     rd_out_en => data_out_en(8)
+    );
+
+PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port9,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse9,
+     data_out =>Port9_out,
+     fifo_full =>fifo_out_full_signal(9),
+     data_avalaible => data_available(9),
+     rd_out_en => data_out_en(9)
+    );
+
+PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port10,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse10,
+     data_out =>Port10_out,
+     fifo_full =>fifo_out_full_signal(10),
+     data_avalaible => data_available(10),
+     rd_out_en => data_out_en(10)
+    );
+
+PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port11,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse11,
+     data_out =>Port11_out,
+     fifo_full =>fifo_out_full_signal(11),
+     data_avalaible => data_available(11),
+     rd_out_en => data_out_en(11)
+    );
+
+PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port12,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse12,
+     data_out =>Port12_out,
+     fifo_full =>fifo_out_full_signal(12),
+     data_avalaible => data_available(12),
+     rd_out_en => data_out_en(12)
+    );
+
+PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port13,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse13,
+     data_out =>Port13_out,
+     fifo_full =>fifo_out_full_signal(13),
+     data_avalaible => data_available(13),
+     rd_out_en => data_out_en(13)
+    );
+
+PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port14,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse14,
+     data_out =>Port14_out,
+     fifo_full =>fifo_out_full_signal(14),
+     data_avalaible => data_available(14),
+     rd_out_en => data_out_en(14)
+    );
+
+PORT15_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port15,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse15,
+     data_out =>Port15_out,
+     fifo_full =>fifo_out_full_signal(15),
+     data_avalaible => data_available(15),
+     rd_out_en => data_out_en(15)
+    );
+
+PORT16_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE 
+   PORT MAP(
+     data_in => crossbar_out_port16,
+     reset => reset,
+     clk => clk,
+     wr_en =>crossbar_out_pulse16,
+     data_out =>Port16_out,
+     fifo_full =>fifo_out_full_signal(16),
+     data_avalaible => data_available(16),
+     rd_out_en => data_out_en(16)
+    );
+
+end generate port_out_switch16x16;
+
+-- intstanciation et connexion des crossbars du  switch en fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+crossbar_switch2x2 : if number_of_ports = 2 generate
+
+Switch_Crossbar2_2: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>2)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => "00000000",
+   Port4_in => "00000000",
+   Port5_in => "00000000",
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in =>'0' ,
+   Port4_pulse_in =>'0' ,
+   Port5_pulse_in =>'0' ,
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+   Ctrl => Grant_signal);
+end generate crossbar_switch2x2;
+
+
+-- switch 3 ports
+crossbar_switch3x3 : if number_of_ports = 3 generate
+
+Switch_Crossbar3_3: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>3)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => "00000000",
+   Port5_in => "00000000",
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in =>'0' ,
+   Port5_pulse_in =>'0' ,
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+   Ctrl => Grant_signal);
+end generate crossbar_switch3x3;
+
+
+-- switch 4 ports
+crossbar_switch4x4 : if number_of_ports = 4 generate
+
+Switch_Crossbar4_4: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>4)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => "00000000",
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in =>'0' ,
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+   Ctrl => Grant_signal);
+end generate crossbar_switch4x4;
+
+
+-- switch 5 ports
+crossbar_switch5x5 : if number_of_ports = 5 generate
+
+Switch_Crossbar5_5: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>5)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => "00000000",
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in =>'0' ,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+   Ctrl => Grant_signal);
+end generate crossbar_switch5x5;
+
+
+-- switch 6 ports
+crossbar_switch6x6 : if number_of_ports = 6 generate
+
+Switch_Crossbar6_6: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>6)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => "00000000",
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in =>'0' ,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+   Ctrl => Grant_signal);
+end generate crossbar_switch6x6;
+
+
+-- switch 7 ports
+crossbar_switch7x7 : if number_of_ports = 7 generate
+
+Switch_Crossbar7_7: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>7)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => "00000000",
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in =>'0' ,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+   Ctrl => Grant_signal);
+end generate crossbar_switch7x7;
+
+
+-- switch 8 ports
+crossbar_switch8x8 : if number_of_ports = 8 generate
+
+Switch_Crossbar8_8: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>8)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => "00000000",
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in =>'0' ,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+   Ctrl => Grant_signal);
+end generate crossbar_switch8x8;
+
+
+-- switch 9 ports
+crossbar_switch9x9 : if number_of_ports = 9 generate
+
+Switch_Crossbar9_9: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>9)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => "00000000",
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in =>'0' ,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+   Ctrl => Grant_signal);
+end generate crossbar_switch9x9;
+
+
+-- switch 10 ports
+crossbar_switch10x10 : if number_of_ports = 10 generate
+
+Switch_Crossbar10_10: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>10)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => crossbar_in_port10,
+   Port11_in => "00000000",
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in => crossbar_in_pulse10,
+   Port11_pulse_in =>'0' ,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+   Port10_pulse_out => crossbar_out_pulse10,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+  Port10_out => crossbar_out_port10,
+   Ctrl => Grant_signal);
+end generate crossbar_switch10x10;
+
+
+-- switch 11 ports
+crossbar_switch11x11 : if number_of_ports = 11 generate
+
+Switch_Crossbar11_11: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>11)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => crossbar_in_port10,
+   Port11_in => crossbar_in_port11,
+   Port12_in => "00000000",
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in => crossbar_in_pulse10,
+   Port11_pulse_in => crossbar_in_pulse11,
+   Port12_pulse_in =>'0' ,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+   Port10_pulse_out => crossbar_out_pulse10,
+   Port11_pulse_out => crossbar_out_pulse11,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+  Port10_out => crossbar_out_port10,
+  Port11_out => crossbar_out_port11,
+   Ctrl => Grant_signal);
+end generate crossbar_switch11x11;
+
+
+-- switch 12 ports
+crossbar_switch12x12 : if number_of_ports = 12 generate
+
+Switch_Crossbar12_12: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>12)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => crossbar_in_port10,
+   Port11_in => crossbar_in_port11,
+   Port12_in => crossbar_in_port12,
+   Port13_in => "00000000",
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in => crossbar_in_pulse10,
+   Port11_pulse_in => crossbar_in_pulse11,
+   Port12_pulse_in => crossbar_in_pulse12,
+   Port13_pulse_in =>'0' ,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+   Port10_pulse_out => crossbar_out_pulse10,
+   Port11_pulse_out => crossbar_out_pulse11,
+   Port12_pulse_out => crossbar_out_pulse12,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+  Port10_out => crossbar_out_port10,
+  Port11_out => crossbar_out_port11,
+  Port12_out => crossbar_out_port12,
+   Ctrl => Grant_signal);
+end generate crossbar_switch12x12;
+
+
+-- switch 13 ports
+crossbar_switch13x13 : if number_of_ports = 13 generate
+
+Switch_Crossbar13_13: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>13)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => crossbar_in_port10,
+   Port11_in => crossbar_in_port11,
+   Port12_in => crossbar_in_port12,
+   Port13_in => crossbar_in_port13,
+   Port14_in => "00000000",
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in => crossbar_in_pulse10,
+   Port11_pulse_in => crossbar_in_pulse11,
+   Port12_pulse_in => crossbar_in_pulse12,
+   Port13_pulse_in => crossbar_in_pulse13,
+   Port14_pulse_in =>'0' ,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+   Port10_pulse_out => crossbar_out_pulse10,
+   Port11_pulse_out => crossbar_out_pulse11,
+   Port12_pulse_out => crossbar_out_pulse12,
+   Port13_pulse_out => crossbar_out_pulse13,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+  Port10_out => crossbar_out_port10,
+  Port11_out => crossbar_out_port11,
+  Port12_out => crossbar_out_port12,
+  Port13_out => crossbar_out_port13,
+   Ctrl => Grant_signal);
+end generate crossbar_switch13x13;
+
+
+-- switch 14 ports
+crossbar_switch14x14 : if number_of_ports = 14 generate
+
+Switch_Crossbar14_14: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>14)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => crossbar_in_port10,
+   Port11_in => crossbar_in_port11,
+   Port12_in => crossbar_in_port12,
+   Port13_in => crossbar_in_port13,
+   Port14_in => crossbar_in_port14,
+   Port15_in => "00000000",
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in => crossbar_in_pulse10,
+   Port11_pulse_in => crossbar_in_pulse11,
+   Port12_pulse_in => crossbar_in_pulse12,
+   Port13_pulse_in => crossbar_in_pulse13,
+   Port14_pulse_in => crossbar_in_pulse14,
+   Port15_pulse_in =>'0' ,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+   Port10_pulse_out => crossbar_out_pulse10,
+   Port11_pulse_out => crossbar_out_pulse11,
+   Port12_pulse_out => crossbar_out_pulse12,
+   Port13_pulse_out => crossbar_out_pulse13,
+   Port14_pulse_out => crossbar_out_pulse14,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+  Port10_out => crossbar_out_port10,
+  Port11_out => crossbar_out_port11,
+  Port12_out => crossbar_out_port12,
+  Port13_out => crossbar_out_port13,
+  Port14_out => crossbar_out_port14,
+   Ctrl => Grant_signal);
+end generate crossbar_switch14x14;
+
+
+-- switch 15 ports
+crossbar_switch15x15 : if number_of_ports = 15 generate
+
+Switch_Crossbar15_15: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>15)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => crossbar_in_port10,
+   Port11_in => crossbar_in_port11,
+   Port12_in => crossbar_in_port12,
+   Port13_in => crossbar_in_port13,
+   Port14_in => crossbar_in_port14,
+   Port15_in => crossbar_in_port15,
+   Port16_in => "00000000",
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in => crossbar_in_pulse10,
+   Port11_pulse_in => crossbar_in_pulse11,
+   Port12_pulse_in => crossbar_in_pulse12,
+   Port13_pulse_in => crossbar_in_pulse13,
+   Port14_pulse_in => crossbar_in_pulse14,
+   Port15_pulse_in => crossbar_in_pulse15,
+   Port16_pulse_in =>'0' ,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+   Port10_pulse_out => crossbar_out_pulse10,
+   Port11_pulse_out => crossbar_out_pulse11,
+   Port12_pulse_out => crossbar_out_pulse12,
+   Port13_pulse_out => crossbar_out_pulse13,
+   Port14_pulse_out => crossbar_out_pulse14,
+   Port15_pulse_out => crossbar_out_pulse15,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+  Port10_out => crossbar_out_port10,
+  Port11_out => crossbar_out_port11,
+  Port12_out => crossbar_out_port12,
+  Port13_out => crossbar_out_port13,
+  Port14_out => crossbar_out_port14,
+  Port15_out => crossbar_out_port15,
+   Ctrl => Grant_signal);
+end generate crossbar_switch15x15;
+
+
+-- switch 16 ports
+crossbar_switch16x16 : if number_of_ports = 16 generate
+
+Switch_Crossbar16_16: Crossbar 
+GENERIC MAP(number_of_crossbar_ports =>16)
+  PORT MAP(
+   Port1_in => crossbar_in_port1,
+   Port2_in => crossbar_in_port2,
+   Port3_in => crossbar_in_port3,
+   Port4_in => crossbar_in_port4,
+   Port5_in => crossbar_in_port5,
+   Port6_in => crossbar_in_port6,
+   Port7_in => crossbar_in_port7,
+   Port8_in => crossbar_in_port8,
+   Port9_in => crossbar_in_port9,
+   Port10_in => crossbar_in_port10,
+   Port11_in => crossbar_in_port11,
+   Port12_in => crossbar_in_port12,
+   Port13_in => crossbar_in_port13,
+   Port14_in => crossbar_in_port14,
+   Port15_in => crossbar_in_port15,
+   Port16_in => crossbar_in_port16,
+   Port1_pulse_in => crossbar_in_pulse1,
+   Port2_pulse_in => crossbar_in_pulse2,
+   Port3_pulse_in => crossbar_in_pulse3,
+   Port4_pulse_in => crossbar_in_pulse4,
+   Port5_pulse_in => crossbar_in_pulse5,
+   Port6_pulse_in => crossbar_in_pulse6,
+   Port7_pulse_in => crossbar_in_pulse7,
+   Port8_pulse_in => crossbar_in_pulse8,
+   Port9_pulse_in => crossbar_in_pulse9,
+   Port10_pulse_in => crossbar_in_pulse10,
+   Port11_pulse_in => crossbar_in_pulse11,
+   Port12_pulse_in => crossbar_in_pulse12,
+   Port13_pulse_in => crossbar_in_pulse13,
+   Port14_pulse_in => crossbar_in_pulse14,
+   Port15_pulse_in => crossbar_in_pulse15,
+   Port16_pulse_in => crossbar_in_pulse16,
+   Port1_pulse_out => crossbar_out_pulse1,
+   Port2_pulse_out => crossbar_out_pulse2,
+   Port3_pulse_out => crossbar_out_pulse3,
+   Port4_pulse_out => crossbar_out_pulse4,
+   Port5_pulse_out => crossbar_out_pulse5,
+   Port6_pulse_out => crossbar_out_pulse6,
+   Port7_pulse_out => crossbar_out_pulse7,
+   Port8_pulse_out => crossbar_out_pulse8,
+   Port9_pulse_out => crossbar_out_pulse9,
+   Port10_pulse_out => crossbar_out_pulse10,
+   Port11_pulse_out => crossbar_out_pulse11,
+   Port12_pulse_out => crossbar_out_pulse12,
+   Port13_pulse_out => crossbar_out_pulse13,
+   Port14_pulse_out => crossbar_out_pulse14,
+   Port15_pulse_out => crossbar_out_pulse15,
+   Port16_pulse_out => crossbar_out_pulse16,
+  Port1_out => crossbar_out_port1,
+  Port2_out => crossbar_out_port2,
+  Port3_out => crossbar_out_port3,
+  Port4_out => crossbar_out_port4,
+  Port5_out => crossbar_out_port5,
+  Port6_out => crossbar_out_port6,
+  Port7_out => crossbar_out_port7,
+  Port8_out => crossbar_out_port8,
+  Port9_out => crossbar_out_port9,
+  Port10_out => crossbar_out_port10,
+  Port11_out => crossbar_out_port11,
+  Port12_out => crossbar_out_port12,
+  Port13_out => crossbar_out_port13,
+  Port14_out => crossbar_out_port14,
+  Port15_out => crossbar_out_port15,
+  Port16_out => crossbar_out_port16,
+   Ctrl => Grant_signal);
+end generate crossbar_switch16x16;
+-- intstanciation et connexion du scheduler en fonction du nombre de ports
+-- le circuit genere depend du parametre generique nombre de ports
+-- switch 2 ports
+scheduler_switch2x2 : if number_of_ports = 2 generate
+
+Scheduler2_2: Scheduler 
+   GENERIC MAP(number_of_ports => 2 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch2x2;
+
+
+-- switch 3 ports
+scheduler_switch3x3 : if number_of_ports = 3 generate
+
+Scheduler3_3: Scheduler 
+   GENERIC MAP(number_of_ports => 3 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch3x3;
+
+
+-- switch 4 ports
+scheduler_switch4x4 : if number_of_ports = 4 generate
+
+Scheduler4_4: Scheduler 
+   GENERIC MAP(number_of_ports => 4 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch4x4;
+
+
+-- switch 5 ports
+scheduler_switch5x5 : if number_of_ports = 5 generate
+
+Scheduler5_5: Scheduler 
+   GENERIC MAP(number_of_ports => 5 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch5x5;
+
+
+-- switch 6 ports
+scheduler_switch6x6 : if number_of_ports = 6 generate
+
+Scheduler6_6: Scheduler 
+   GENERIC MAP(number_of_ports => 6 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch6x6;
+
+
+-- switch 7 ports
+scheduler_switch7x7 : if number_of_ports = 7 generate
+
+Scheduler7_7: Scheduler 
+   GENERIC MAP(number_of_ports => 7 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch7x7;
+
+
+-- switch 8 ports
+scheduler_switch8x8 : if number_of_ports = 8 generate
+
+Scheduler8_8: Scheduler 
+   GENERIC MAP(number_of_ports => 8 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch8x8;
+
+
+-- switch 9 ports
+scheduler_switch9x9 : if number_of_ports = 9 generate
+
+Scheduler9_9: Scheduler 
+   GENERIC MAP(number_of_ports => 9 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch9x9;
+
+
+-- switch 10 ports
+scheduler_switch10x10 : if number_of_ports = 10 generate
+
+Scheduler10_10: Scheduler 
+   GENERIC MAP(number_of_ports => 10 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch10x10;
+
+
+-- switch 11 ports
+scheduler_switch11x11 : if number_of_ports = 11 generate
+
+Scheduler11_11: Scheduler 
+   GENERIC MAP(number_of_ports => 11 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch11x11;
+
+
+-- switch 12 ports
+scheduler_switch12x12 : if number_of_ports = 12 generate
+
+Scheduler12_12: Scheduler 
+   GENERIC MAP(number_of_ports => 12 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch12x12;
+
+
+-- switch 13 ports
+scheduler_switch13x13 : if number_of_ports = 13 generate
+
+Scheduler13_13: Scheduler 
+   GENERIC MAP(number_of_ports => 13 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch13x13;
+
+
+-- switch 14 ports
+scheduler_switch14x14 : if number_of_ports = 14 generate
+
+Scheduler14_14: Scheduler 
+   GENERIC MAP(number_of_ports => 14 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch14x14;
+
+
+-- switch 15 ports
+scheduler_switch15x15 : if number_of_ports = 15 generate
+
+Scheduler15_15: Scheduler 
+   GENERIC MAP(number_of_ports => 15 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch15x15;
+
+
+-- switch 16 ports
+scheduler_switch16x16 : if number_of_ports = 16 generate
+
+Scheduler16_16: Scheduler 
+   GENERIC MAP(number_of_ports => 16 ) 
+   PORT MAP(
+     Request => Request_signal,
+     Fifo_full => fifo_out_full_signal,
+     clk => clk,
+     priority_rotation =>priority_rotation_signal,
+     reset => reset,
+     port_grant => grant_signal
+    );
+
+end generate scheduler_switch16x16;
+
+
+
+
+
+
+
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GENERIQUE_guide.ncd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GENERIQUE_guide.ncd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GENERIQUE_guide.ncd	(revision 20)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
+###3472:XlxV32DM    3f97     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NFgKZCenPpNpU8RgC6is9Z6E0bz/Ymhc3MS3iW8S3wA+DbmGbxKLQGF5u8WazYBRwV1iB642y+mgh9STUmv/3EAHquUo6/VDpTSPXgKA8618iCrG8NPCPl4YNh/K8VsVetBNT+Fk8Wp+vg1eCCxIZ392ME+VcrjH0jGCqb6k8E1ODdwIZz54BmpvUWcbV+xLXdZ6iR6woIfNeP1mdTYLPbxjLag+o5FysO9HURvUX3YDFnTMPt60ZiqX3iFeXbTm/4H0ANTqv327vcdoT0/trAah07QzxvoUvYfRyuyu5eC1CEX8I2OnjIMyLsho0mb0bg12cZmMmzKK6nt20zTJNiSLlIyQ5li29+ypt9Hb6ycmI8t8unsmY4SMkTIOyOgVMy2ZvhRxQETbqJ5oXVC8bWOEiPZtYMtMxEgRt4mo112T9aVg7Lq2GvBzy2mx0FV0zgfvKjJIuooAbYekq8ihdhukXUUOndu6QdJV5FAdDklXkUOXU9OuIodOJDVIuooMkq4ioyZdRYDAn3QVOcRR6SpyiKPSVQRoOiRdRQ5xVLqKHJouuXQVGYAx6SpyALikq8ihCOrSVeTQGNDYTS1GjEpXkUMTOpGuIocidCJdRYBeaOx+AMUI3XV8k64i11gDf9JV5BprgRBGI3ZAu4pcY9gf7SpyjT3gXq6HrrHnJuSj0lVkwOPYpKvIgAw+BtcNYpWuIoc2uJSuIocKeJOuIoc2pJauIkATGlsYla4i11jGqHQVucZgHdpV5Bp7b0LgT7qKHOKodBU5xFHpKgIEm5WuIoc4Kl1FDnWXXLqKDMDYgoMu+udzI5d5YHfarON6go61WQej9KxCa8uEFjQrzTr+DZ6gLTq+UwN2PBZHx4cDYJG01KHMb/MDga405jgWrNDGHOADXUkynb9ZCdFCJr0QvqpJnEOJkWkwgnFXpM0Ga8GLVOuxlvjSZ5S+jHikfQtuUwnfwkOuNqMpLE6bD1zKh1G3YN8SPViaCvwbNSRNBW6FlDdxP6SpwO0RcUrTa7dl7oKk/9A91gZ800In6BIzpQzUgdQ83dI7PEwaCNzSG2xeGghccp4tcqg6Po7K8y90ADk68cmN3KHx+QauItdKA4G5TOE0mkuDCWmzABigaImBgis6DyN5YvO1DQFfmgUgGla8kaGaCm8MwVKscgjhS5sFnPmbSkNQ0AKWz2uL+BDwYifdmikH4kihHi9E9MZTXdoB3KoCBaefSDsAGJ3EAmXsm/bVaVWJa2OnaLRcKEjbAYAvcv+IOXBjuKfSDiCQPBre26822pShyY12LtjvYAkVIYEss9cuBZsn7/h6yREsclWQq82wq80oXq7xe0rFPaX6PUUztcQf3+yeUnk9eXk9eXk9megdMaIJybqxOcnmIJsv2bRy1YMLe0I9akXn/HwLfrWx0QuYrWkhPV4ZXN52b10VB5K1z/KbjUQeu8VoCYm/gvm3ZJmpLIk3NP94TVK76/VKYvMiOeBazZJNykXZNO1/tQApab+pXglLy7SqSDu0rID7XFjMe0To/rwg6bwPSiOSGkEefHgquCjpg54tTTdeZfR3q9vFIGCvkj2BJa2A6n2m4uctk7FBHjO9e/Pfvk6dab3xI+OgjAsy+u8v8es51O4RKmPZkHFTxk0ZB2UclDFSsgjJAGz+XWeMiGT64muSDUrWKdmmZBclIzTtGb9uu9qoiEmvkQPqEVntpojHJpf15S7eEMygii4ZZaoGMjXAlM27N/RUO0rDa8BEl6DWWoA28aq6FdLgsKY/U2kmYf6nXTfrRfut+t/QeqPUPQzLJpZJLINYJrFMYlFtLHMI/eFWn1rCW1AJ8d939ccf+71wNzzSrOTQvb1ysqcV1U9oYAuGMmTvRRNtRUvLTZmjFxi3BqOJpyOBzH30ncFiw9KeqsTFN8vBzTMfiw1yBqCCPLJXPUL7JmfFQSWc2VAdqDv5RW/jgdFUp/soJ5NXBLT73HiFzxukzwJrcxSvRtahrarcFyKH4rYaQvBvti14jNr4KVa/PPiL8XkdGPjP6vFfCy/7wfJYxP+DGG/S###7244:XlxV32DM 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1360eNqtmk2S5LgNhS/jA4gi+KfaTNgbL7yww74ASUnLiZiFvanou/t7yMyu7Gl541FMDAoSSUAEgQeA2W0rrXz8u6a6rR/ffu1zLduyhc9fa2oMjfehFr+G1vjDSH4bSe8j/X1NeBvZ4/mm6HwfsfE1Un9Yk5a3kbcvGOsIXyOz97ehuNT3HZ3vQ2F9H9rfhtL70J7th6H8PvS23ZHXt+3G+MPIfBt5X9Ni+xoZ7wP2dhTv3zaP4/0DyvvQmd6H8tvQ3t8+O59vdh1HfvuE/MOOjvz23aV8fca3//wr7W5Z/ls+/2lL2NKR+J9Xcd3P5dxibiF//DXt/eO3tB8fYyxdszes9Mnr/eNPac9bnAzNffrQ8jY0tmjza863EUYNl7PG+6w1tUtZ+N/XrMcG2v+5gfDzBkYel0qTmAljP2j/9u2XX/7yuee6bEc+15kCL/78GdtnTe5EhMu2h9G3OWOC21fI0bd9XeDWIC6KM3FZXBHXxHVxU9wu7oSLfPoeVzjTCtMK0wrTCtMK0wrTCtOKpBVJK1IUl8RlcVVcEzfWj99qSh/fPqt5QG+Hf3YVySILpJ+QqV3MKKIpuwbmIaLJs+jdLjJEmnargUNSDk3eJeWUlFNSziBbaOCUlFOTz6J3u8gQabJUFckii94hZV2TSBSRlKiB9RDR5FVSoqRESYmSYhowSTFNjpKSJCVJSpKUrIEkKUmTk6RkScmSkiWlaKBIStHkLClVUqqkVElpGqiSUjW5SkqTlCYpTVK6BrqkdE1ukjIkZUjKkJSpgSEpOop1SMqUlCkpU1J2DeySoqNYp6QcknJIio5xPTVwSIqOYj0k5ZSUU1LOJq+qIllEk0+kxJBEokiQzy3iDhFNDkXvdpEh0uSRVSSLMNlkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1WddkXZN1TdY1Wddk3STrJlk3ybom6yZZN8m6SdZNsm6SdZOsm2TdJOsmWTfJuilqIEqKHD2tkmKSYpJikpI0YJKio0gmKUlSkqQomaSsgSwpOoqUJKVISpGUIilVA0VSdBSpSEqVlCopVVKaBpqk6ChSlZQuKV1SuqQIMlKXFB1F6pIyJGVIyiDBH6G9YGdkge66xbCRjcDzvhH6C1lr3xbyJKBE2C+YalFKx25LMP4nTyqPY64Fuy2BlUDqElgbWBxYjVGXwHosvAATC0i4KMGvrAdAlpX1KpfAjAU7LyvrMfqiVM8JLADKgq0XjL7weQtovUTWR9YD6QsnskTWx/rxp5EjKWJhQ2m3B/wrtZftVPopb+/D2TVSSU51KkP1LRa8Ixa+IRbTYz4ggHQs+HEsQ+9wr1j5pFgLaakC9bHii7FhgtjKDmmMNpw0dkwU+yoO8ItdK/rQ49QjGSL2g3dD8wbuFQd1QhySMji5OAbJc+yIH7h6nPhTnARqnPrmOcRNcQcrJvgdd04n7pgk4jcQbXDvTNk5+rjvSNnZeTw41HgU9B4EWzwOFJ1YOJ64azxxw3h2PRKe8SRgTOdvC7BgC3nYAo5hgbO1wLYs8H224jW26t1aDYJDmkDS1r1sFjkwiwSMxYQUDAgBAixqrbE3M8LEbOoR+5mdzEucrSlqwCpEJU7BEqFtGQezbHxGrszLjXkZVwe1WFs4IyvYACTTO60tBJEVkr9VohXo4rFyWlbHCsHOVk8+soGU1kjq1sA4axwy+JW3VNkMAdcheDhByLtGAiX0JgS4TB0YTH0aRAODTRNr55amlk0iPU0tm3xumuTsNA+ETg6FsobRHaBLBxkzqWhMB6ZLB/CWTqk88f50EqzpBHnTKcknLpAVAnnp65Z1MlknkwNhkwOpIAd2lMNgnrJyVnWTlYJyxPVyRFuOVDI5YqYca4eAIdkAgMzpQSLyjNIl29AjFUdOOHVOHQEJv8oJ/8toUunLvJxVBGPEnLs4Tjpn/DSXhRWFrEL0RUjTI66Sy8wbhRxTakRvBbEoHBHVSGS5VXES1UgKuR3itIWON6GC0U6Y5gFG5VEQMIjVPLXBCZ7kaUyZKs0nB5VpbyD4Wp7kjTzx8UxZA8ks23HqvONNeaf+yvuud9RG+QBh8qHtn9r+qe2fBGI+qSzzyVcVIWFZCNOygCplIZLLQjlWAnmoBA65BFyqqEoqK1stK3kD3CkQTV41WSVBiYBrieSXEnHlEgmrEvnmQnhvxYDVYhpVHi+GXwFc4sinxSj+ilJfUatVlH2IBxQlSUkdHWo9Sjr1jsMrmaRVMpbkdOAKBiuFVFUKHlYqDlwqTlgqrlIqrlKqNlhJ5qUeekeQlAa4FwVOaZwqzS9rdVqlyy4dnyy9ipPyTl1aBk5ThgwxCOcyhh5BpDKJHryCd5MwLVOipj6Xkg2CU5ddBtupC8p+MnqAUuWg6CxHYi09AQS3KAeFRVH0lLOqU+56BAqqAqcuQD2eR/ILHEoNfH1VZVxX8nNVfVhVxVUhV416NMoJUGSHJKSoBKpG2NN2rBBNUSzUjK0qzgbBxJVDgvBVpA8ISiBESq04f61soTYSYm1sujYqoqokUpVEaifr1Z71CALXQY6qA7vUwUmTiVg2KQTqPBjdo4ged40eHEo9igi9Qz2DCE5TTwk4aQeaEmlbwMS2gLEEHu8CPk5mKxD2xslWSDkh+F9TG9TIkBA204xYbYZ7N6PRaCqVmiqTlhcEgAUQTqsRIBCJFyq3AmICthqgt2mVXTZ2DQETm9r31sDn1nFlPIopncKndbJuk9O00Xg3OY829fUTl2pKgW3XPnbM3g5OtR3ASJNbtEOfe4KE7aSkAkWOrS9AeF9wvR6ofLB6g3BufeUA+prFAX0cApPJ9BA8opvmGR/Ula16wvW6Aqyrbe3ALQQj9kyd1jPZpRfcoqu26IVurdcgwsn0CkT2Bv71xkf2hlP3zof3Ti3YO2jWdeZ9SPkgdfRJkuuTbfVJ2Pcp8VSEEAzWD+3jwF8oMsLWz0UEZ+0nk8dCsTMWkH8sIPBYiIURSJVDXeJQLzdWyoBBT70NnfSInMwQDo0oAZHSZZgEGMc4VJsPFcVDeXok4HBkUsfIkgIYb6MAzUM7B57hKh8+KsXuUBIelZTPUbKsgU2jkyZG53NH7+JIgQNNEGKLwggysf3QrdnYFz5N91pjp+wdQgHQv/2+6KN8BN3bFnAbdbAroBU5cnUxKtHzKqgWqijIitySc2UP5IVBtzwJ0p3uRpn5JIjDUtYtBJJ6UE8aqBG3QIWxhaQblowfhEKeCZWkHlRChEHVEpSKwo6x6c2ZfA7jc0CQNbDfdcVqq/pAmue4rWqiVtl0Je1unAnfXc51WysnQydbN5rYsdG1Hts6Q/j9pof2TMkX2WRUmRXVCsXEaus4n03yvR2kUroeao9IYKWc8pec9FVJH++V9Nt7yke67dfQUOOwUVy6pUNXNa/iHGufziwquz/+NkDX9fNvEWyOn79Ry378OuhNF/7oLu3j2/8aCrr7Qc3+VOOHWY4rNeOPq1Fn81Ajf0nhSs3xx9X4rafUuEt6e/R7NSXcoOZ4qpHX21mu1NgfV6OWzNUosNLsV2rKDWpeZ6PYpTS8UtNvUNOeahweynKlZr9BTX+pEQJZvPK0dIOa8VTjIKcG/mc16w3h+fI04ahKwJ/VpPMGNedTjaCaxHilZt6AAstTjWeDel6paTeoCS81Sjh5vVKTb1CzPtV4TtM9ys9q4g1qXpjmaVO/If2sZrlBjT3VKDMf52Xc3GG09FSj5H+el3FzhwvkV/b0+mI5ryIn3+HSL4x+1DDhvIqdfEOIhhd8Puok3W9fAOgNkBP698LDa7HlKn7KDRAaXhD6rPeWqwgqN9Q44Xsp9agpL2Oo3FHlvIqpZ916nRbuwIRXWnjWxvHS6+5AhVdieNbf12B6Q9peX6nhUePreuNC0Q1lyPpKDo8+QpfEF4puKKvWV3p49Cpzv6pG0w1l4vpC7kc/pMvpC0V3lL0v7H72XOtVDWd3lPHf0fvR162X2eiOMyrfux/1jst1PrrD6773P96fhnmZj+6Io1eaePTAa7tChnIDMqyvNPHss/NlProB69bxXZH38naZj24oTdZXmnjeF4TLfHRDcbJ+77n9TiIdl/nohuJkfaH3494jj8tbhDs61Rd6P+9W6uU9wg0QFMN3RX5/k69uEtINEBRf6P28I4qX6H1DzRBf5f3zHmq5uk1IN1RB8ZUmHndd+u30QtEdrfErTTzu00a/ulFIN1Sq8ZUmdGcHqZf56A/X3t9++eXvn//AWsvHP/Sj/Mdv6mMX/gR/2nPJW/W/++MvH3L63/D8a7rFc061zXCuKd84N3Tx5tyh+zFx7ZGyxflllnN+peVc1c2Tc133T87tuiZyTj+VdnH6LXN1yfqNre3OFV3AOKd/R7c4N3Vb4tyhOxNxI+hqw7moCw7nsu4hnNOPAc25oUsD5/zqQNzUzbdLnqv6fOeS2nHnippy5/RvylzynOqgnTvV6Irbg9pd50xdqXNZvalzTS2kc0ONpHOH93ti9W/n6PqcfTRnzj5aNGerd1LOdu+nnN297XH29OZHLFCjHsVZ807F2eINhbPN2wpnp1f/zh7eA8DqykulurPRC3Zns9fVzlavrp0dXgQ7u3spLBafU8Xq7Op1q7PJy0tnixeZznavBZ2dXhE6e3rhJnYNXr45a15lOZu91nK2eUnk7PDCyNnD6xexIL6qGGcfxYazyUsOZ6tXBs52rw+c3T2NO3t6MhdLSlfOddY88zpbPEE6+0iTzk7PZs4entPEpuCpx9noCcjZ7HnC2erZwtnhoO7s7tAuFqwQAju7Og47mxwunS0Oms52xzZnpyOcs+fjxwPY8oCjD6Djv7UfTts=
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN_bitgen.xwbt
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN_bitgen.xwbt	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN_bitgen.xwbt	(revision 20)
@@ -0,0 +1,8 @@
+INTSTYLE=ise
+INFILE=C:\Core MPI\SWITCH_GENERIC_16_16\SWITCH_GEN.ncd
+OUTFILE=C:\Core MPI\SWITCH_GENERIC_16_16\SWITCH_GEN.bit
+FAMILY=Spartan3E
+PART=xc3s1200e-4ft256
+WORKINGDIR=C:\Core MPI\SWITCH_GENERIC_16_16
+LICENSE=ISE
+USER_INFO=No user information available.
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN_envsettings.html
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN_envsettings.html	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN_envsettings.html	(revision 20)
@@ -0,0 +1,382 @@
+<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<center><big><big><b>System Settings</b></big></big></center><br>
+<A NAME="Environment Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Environment Variable</b></td>
+<td><b>xst</b></td>
+<td><b>ngdbuild</b></td>
+<td><b>map</b></td>
+<td><b>par</b></td>
+</tr>
+<tr>
+<td>PATHEXT</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>Path</td>
+<td>d:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>D:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>D:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Windows Live\Shared;<br>C:\Program Files (x86)\CMake 2.8\bin;<br>C:\qtsdk\mingw\bin;<br>C:\qtsdk\qtcreator\bin;<br>C:\Program Files (x86)\Graphviz 2.28\bin;<br>C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;<br>C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;<br>C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;<br>c:\altera\90sp1\quartus\bin;<br>C:\Program Files\Oracle\VirtualBox</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>XILINX</td>
+<td>d:\Xilinx\12.3\ISE_DS\ISE\</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>XILINX_DSP</td>
+<td>D:\Xilinx\12.3\ISE_DS\ISE</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>XILINX_EDK</td>
+<td>D:\Xilinx\12.3\ISE_DS\EDK</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>XILINX_PLANAHEAD</td>
+<td>D:\Xilinx\12.3\ISE_DS\PlanAhead</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+</TABLE>
+<A NAME="Synthesis Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-ifn</td>
+<td>&nbsp;</td>
+<td>SWITCH_GEN.prj</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ifmt</td>
+<td>&nbsp;</td>
+<td>mixed</td>
+<td>MIXED</td>
+</tr>
+<tr>
+<td>-ofn</td>
+<td>&nbsp;</td>
+<td>SWITCH_GEN</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ofmt</td>
+<td>&nbsp;</td>
+<td>NGC</td>
+<td>NGC</td>
+</tr>
+<tr>
+<td>-p</td>
+<td>&nbsp;</td>
+<td>xc3s1200e-4-ft256</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-top</td>
+<td>&nbsp;</td>
+<td>SWITCH_GEN</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-opt_mode</td>
+<td>Optimization Goal</td>
+<td>Speed</td>
+<td>Speed</td>
+</tr>
+<tr>
+<td>-opt_level</td>
+<td>Optimization Effort</td>
+<td>1</td>
+<td>1</td>
+</tr>
+<tr>
+<td>-iuc</td>
+<td>Use synthesis Constraints File</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-keep_hierarchy</td>
+<td>Keep Hierarchy</td>
+<td>No</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-netlist_hierarchy</td>
+<td>Netlist Hierarchy</td>
+<td>As_Optimized</td>
+<td>As_Optimized</td>
+</tr>
+<tr>
+<td>-rtlview</td>
+<td>Generate RTL Schematic</td>
+<td>Yes</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-glob_opt</td>
+<td>Global Optimization Goal</td>
+<td>AllClockNets</td>
+<td>AllClockNets</td>
+</tr>
+<tr>
+<td>-read_cores</td>
+<td>Read Cores</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-write_timing_constraints</td>
+<td>Write Timing Constraints</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-cross_clock_analysis</td>
+<td>Cross Clock Analysis</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-bus_delimiter</td>
+<td>Bus Delimiter</td>
+<td>&lt;&gt;</td>
+<td>&lt;&gt;</td>
+</tr>
+<tr>
+<td>-slice_utilization_ratio</td>
+<td>Slice Utilization Ratio</td>
+<td>100</td>
+<td>100%</td>
+</tr>
+<tr>
+<td>-bram_utilization_ratio</td>
+<td>BRAM Utilization Ratio</td>
+<td>100</td>
+<td>100%</td>
+</tr>
+<tr>
+<td>-verilog2001</td>
+<td>Verilog 2001</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-fsm_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-fsm_encoding</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-safe_implementation</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-fsm_style</td>
+<td>&nbsp;</td>
+<td>LUT</td>
+<td>LUT</td>
+</tr>
+<tr>
+<td>-ram_extract</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-ram_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-rom_extract</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-shreg_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-rom_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-auto_bram_packing</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-resource_sharing</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-async_to_sync</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-mult_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-iobuf</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-max_fanout</td>
+<td>&nbsp;</td>
+<td>100000</td>
+<td>500</td>
+</tr>
+<tr>
+<td>-bufg</td>
+<td>&nbsp;</td>
+<td>24</td>
+<td>24</td>
+</tr>
+<tr>
+<td>-register_duplication</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-register_balancing</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-optimize_primitives</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>NO</td>
+</tr>
+<tr>
+<td>-use_clock_enable</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-use_sync_set</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-use_sync_reset</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-iob</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>AUTO</td>
+</tr>
+<tr>
+<td>-equivalent_register_removal</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>YES</td>
+</tr>
+<tr>
+<td>-slice_utilization_ratio_maxmargin</td>
+<td>&nbsp;</td>
+<td>5</td>
+<td>0%</td>
+</tr>
+</TABLE>
+<A NAME="Operating System Information"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Operating System Information</b></td>
+<td><b>xst</b></td>
+<td><b>ngdbuild</b></td>
+<td><b>map</b></td>
+<td><b>par</b></td>
+</tr>
+<tr>
+<td>CPU Architecture/Speed</td>
+<td>Intel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHz</td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>Host</td>
+<td>GAMOM-PC</td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>OS Name</td>
+<td>Microsoft </td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>OS Release</td>
+<td>Service Pack 1  (build 7601)</td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+</tr>
+</TABLE>
+</BODY> </HTML>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN_guide.ncd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN_guide.ncd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/SWITCH_GEN_guide.ncd	(revision 20)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
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Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Scheduler.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Scheduler.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Scheduler.vhd	(revision 20)
@@ -0,0 +1,432 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: KIEGAING EMMANUEL GEL EN 5
+-- 
+-- Create Date:    19:56:34 05/06/2011 
+-- Design Name: 
+-- Module Name:    Sheduler - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: Module de l'ordonnanceur du switch crossbar
+-- l'algorithme utilisé est le DPA (diagonal propagation arbiter)
+-- intencie un scheduler particulier en fonction du nombre de port
+-- Dependencies: 
+--
+-- Revision: 1.0
+-- reconstruction du dpa
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use Work.Sheduler_package.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Scheduler is
+   generic(number_of_ports : positive := 4);
+    Port ( Request : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
+			  Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1);
+           clk : in  STD_LOGIC;
+	        reset : in  STD_LOGIC;
+			  priority_rotation : in  STD_LOGIC_VECTOR (number_of_ports downto 1);
+           port_grant : out  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1));
+      end Scheduler;
+		
+architecture Behavioral of Scheduler is
+-- composants du scheduler
+
+-- composants du scheduler
+
+
+COMPONENT Scheduler2_2
+   PORT(
+      Request : IN std_logic_vector(4 downto 1);
+      Fifo_full : IN std_logic_vector(2 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(4 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (2 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler3_3
+   PORT(
+      Request : IN std_logic_vector(9 downto 1);
+      Fifo_full : IN std_logic_vector(3 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(9 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (3 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler4_4
+   PORT(
+      Request : IN std_logic_vector(16 downto 1);
+      Fifo_full : IN std_logic_vector(4 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(16 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (4 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler5_5
+   PORT(
+      Request : IN std_logic_vector(25 downto 1);
+      Fifo_full : IN std_logic_vector(5 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(25 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (5 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler6_6
+   PORT(
+      Request : IN std_logic_vector(36 downto 1);
+      Fifo_full : IN std_logic_vector(6 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(36 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (6 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler7_7
+   PORT(
+      Request : IN std_logic_vector(49 downto 1);
+      Fifo_full : IN std_logic_vector(7 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(49 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (7 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler8_8
+   PORT(
+      Request : IN std_logic_vector(64 downto 1);
+      Fifo_full : IN std_logic_vector(8 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(64 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (8 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler9_9
+   PORT(
+      Request : IN std_logic_vector(81 downto 1);
+      Fifo_full : IN std_logic_vector(9 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(81 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (9 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler10_10
+   PORT(
+      Request : IN std_logic_vector(100 downto 1);
+      Fifo_full : IN std_logic_vector(10 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(100 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (10 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler11_11
+   PORT(
+      Request : IN std_logic_vector(121 downto 1);
+      Fifo_full : IN std_logic_vector(11 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(121 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (11 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler12_12
+   PORT(
+      Request : IN std_logic_vector(144 downto 1);
+      Fifo_full : IN std_logic_vector(12 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(144 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (12 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler13_13
+   PORT(
+      Request : IN std_logic_vector(169 downto 1);
+      Fifo_full : IN std_logic_vector(13 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(169 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (13 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler14_14
+   PORT(
+      Request : IN std_logic_vector(196 downto 1);
+      Fifo_full : IN std_logic_vector(14 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(196 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (14 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler15_15
+   PORT(
+      Request : IN std_logic_vector(225 downto 1);
+      Fifo_full : IN std_logic_vector(15 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(225 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (15 downto 1)
+   );
+ END COMPONENT;
+
+COMPONENT Scheduler16_16
+   PORT(
+      Request : IN std_logic_vector(256 downto 1);
+      Fifo_full : IN std_logic_vector(16 downto 1);
+      clk : IN std_logic;
+      reset : IN std_logic;
+      port_grant : OUT std_logic_vector(256 downto 1);
+      priority_rotation : in  STD_LOGIC_VECTOR (16 downto 1)
+   );
+ END COMPONENT;
+
+
+-- instanciation des scheduler
+--======================scheduler 2 ports=======================
+
+begin
+
+-- instanciation des scheduler
+--======================scheduler 2 ports=======================
+
+scheduler2x2 : if number_of_ports = 2 generate
+
+  Inst_Scheduler2_2 : Scheduler2_2
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler2x2; 
+
+--======================scheduler 3 ports=======================
+
+scheduler3x3 : if number_of_ports = 3 generate
+
+  Inst_Scheduler3_3 : Scheduler3_3
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler3x3; 
+
+--======================scheduler 4 ports=======================
+
+scheduler4x4 : if number_of_ports = 4 generate
+
+  Inst_Scheduler4_4 : Scheduler4_4
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler4x4; 
+
+--======================scheduler 5 ports=======================
+
+scheduler5x5 : if number_of_ports = 5 generate
+
+  Inst_Scheduler5_5 : Scheduler5_5
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler5x5; 
+
+--======================scheduler 6 ports=======================
+
+scheduler6x6 : if number_of_ports = 6 generate
+
+  Inst_Scheduler6_6 : Scheduler6_6
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler6x6; 
+
+--======================scheduler 7 ports=======================
+
+scheduler7x7 : if number_of_ports = 7 generate
+
+  Inst_Scheduler7_7 : Scheduler7_7
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler7x7; 
+
+--======================scheduler 8 ports=======================
+
+scheduler8x8 : if number_of_ports = 8 generate
+
+  Inst_Scheduler8_8 : Scheduler8_8
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler8x8; 
+
+--======================scheduler 9 ports=======================
+
+scheduler9x9 : if number_of_ports = 9 generate
+
+  Inst_Scheduler9_9 : Scheduler9_9
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler9x9; 
+
+--======================scheduler 10 ports=======================
+
+scheduler10x10 : if number_of_ports = 10 generate
+
+  Inst_Scheduler10_10 : Scheduler10_10
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler10x10; 
+
+--======================scheduler 11 ports=======================
+
+scheduler11x11 : if number_of_ports = 11 generate
+
+  Inst_Scheduler11_11 : Scheduler11_11
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler11x11; 
+
+--======================scheduler 12 ports=======================
+
+scheduler12x12 : if number_of_ports = 12 generate
+
+  Inst_Scheduler12_12 : Scheduler12_12
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler12x12; 
+
+--======================scheduler 13 ports=======================
+
+scheduler13x13 : if number_of_ports = 13 generate
+
+  Inst_Scheduler13_13 : Scheduler13_13
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler13x13; 
+
+--======================scheduler 14 ports=======================
+
+scheduler14x14 : if number_of_ports = 14 generate
+
+  Inst_Scheduler14_14 : Scheduler14_14
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler14x14; 
+
+--======================scheduler 15 ports=======================
+
+scheduler15x15 : if number_of_ports = 15 generate
+
+  Inst_Scheduler15_15 : Scheduler15_15
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler15x15; 
+
+--======================scheduler 16 ports=======================
+
+scheduler16x16 : if number_of_ports = 16 generate
+
+  Inst_Scheduler16_16 : Scheduler16_16
+   PORT MAP(
+     Request => Request, 
+     Fifo_full => Fifo_full,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation,
+     port_grant =>port_grant);
+end generate scheduler16x16; 
+
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Scheduler4_4.vhi
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Scheduler4_4.vhi	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Scheduler4_4.vhi	(revision 20)
@@ -0,0 +1,29 @@
+
+-- VHDL Instantiation Created from source file Scheduler4_4.vhd -- 13:38:35 06/19/2011
+--
+-- Notes: 
+-- 1) This instantiation template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the instantiated module
+-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
+
+	COMPONENT Scheduler4_4
+	PORT(
+		Request : IN std_logic_vector(16 downto 1);
+		Fifo_full : IN std_logic_vector(4 downto 1);
+		clk : IN std_logic;
+		reset : IN std_logic;
+		priority_rotation : IN std_logic_vector(4 downto 1);          
+		port_grant : OUT std_logic_vector(16 downto 1)
+		);
+	END COMPONENT;
+
+	Inst_Scheduler4_4: Scheduler4_4 PORT MAP(
+		Request => ,
+		Fifo_full => ,
+		clk => ,
+		reset => ,
+		priority_rotation => ,
+		port_grant => 
+	);
+
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Scheduler_summary.html
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Scheduler_summary.html	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Scheduler_summary.html	(revision 20)
@@ -0,0 +1,73 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>GENERIC_16_16 Project Status</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>GENERIC_16_16.ise</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>New</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>Scheduler</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc3s1200e-4fg320</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 11.1</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD>Xilinx Default (unlocked)</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 06/19/2011 - 14:29:40</center>
+</BODY></HTML>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Test_fifo.wcfg
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Test_fifo.wcfg	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/Test_fifo.wcfg	(revision 20)
@@ -0,0 +1,98 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="C:/Core MPI/SWITCH_GENERIC_16_16/testbench_isim_beh.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="coretypes" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="testbench" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="20" />
+   <wvobject fp_name="/testbench/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/fifo_empty" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">fifo_empty</obj_property>
+      <obj_property name="ObjectShortName">fifo_empty</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/pipo" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">pipo</obj_property>
+      <obj_property name="ObjectShortName">pipo</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/fifo_full" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">fifo_full</obj_property>
+      <obj_property name="ObjectShortName">fifo_full</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/push" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">push</obj_property>
+      <obj_property name="ObjectShortName">push</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/pop" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">pop</obj_property>
+      <obj_property name="ObjectShortName">pop</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/data_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_in[7:0]</obj_property>
+      <obj_property name="ObjectShortName">data_in[7:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/data_out" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_out[7:0]</obj_property>
+      <obj_property name="ObjectShortName">data_out[7:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/rec_pro/etrec" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">etrec</obj_property>
+      <obj_property name="ObjectShortName">etrec</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/uut/rd_en_signal" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rd_en_signal</obj_property>
+      <obj_property name="ObjectShortName">rd_en_signal</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/rec_pro/pop" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">pop</obj_property>
+      <obj_property name="ObjectShortName">pop</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/ron" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ron</obj_property>
+      <obj_property name="ObjectShortName">ron</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/rdone" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rdone</obj_property>
+      <obj_property name="ObjectShortName">rdone</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/rack" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rack</obj_property>
+      <obj_property name="ObjectShortName">rack</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/son" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">son</obj_property>
+      <obj_property name="ObjectShortName">son</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/sdone" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sdone</obj_property>
+      <obj_property name="ObjectShortName">sdone</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/sack" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sack</obj_property>
+      <obj_property name="ObjectShortName">sack</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/clk_period" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_period</obj_property>
+      <obj_property name="ObjectShortName">clk_period</obj_property>
+   </wvobject>
+   <wvobject fp_name="/testbench/msize" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">msize</obj_property>
+      <obj_property name="ObjectShortName">msize</obj_property>
+   </wvobject>
+</wave_config>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/_xmsgs/ibiswriter.xmsgs
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/_xmsgs/ibiswriter.xmsgs	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/_xmsgs/ibiswriter.xmsgs	(revision 20)
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="PostProcessors" num="123" delta="new" >Uppercase letters not recommended in file names.  Refer to the IBIS Specification (http://www.eigroup.org/ibis/ibis.htm) for allowed characters.  
+</msg>
+
+</messages>
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/_xmsgs/netgen.xmsgs
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/_xmsgs/netgen.xmsgs	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/_xmsgs/netgen.xmsgs	(revision 20)
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="NetListWriters" num="635" delta="old" >The generated VHDL netlist contains Xilinx <arg fmt="%s" index="1">SIMPRIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">SIMPRIM</arg> library for correct compilation and simulation. 
+</msg>
+
+<msg type="info" file="NetListWriters" num="0" delta="new" >Xilinx recommends running separate simulations to check for setup by specifying the MAX field in the SDF file and for hold by specifying the MIN field in the SDF file. Please refer to Simulator documentation for more details on specifying MIN and MAX field in the SDF.
+</msg>
+
+<msg type="info" file="NetListWriters" num="665" delta="old" >For more information on how to pass the SDF switches to the simulator, see your Simulator tool documentation.
+</msg>
+
+</messages>
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/compxlib.cfg
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/compxlib.cfg	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/compxlib.cfg	(revision 20)
@@ -0,0 +1,216 @@
+#*****************************************************************
+#   d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe configuration file - compxlib.cfg
+#   Fri Oct 07 10:37:42 2011
+#                                                                
+#   Important :-                                                 
+#       All options/variables must start from first column       
+#                                                                
+#*****************************************************************
+
+#
+RELEASE_VERSION:12.3
+#
+RELEASE_BUILD:M.70d
+#
+# set current simulator name
+SIMULATOR_NAME:mti_pe
+#
+# set current language name
+LANGUAGE_NAME:vhdl
+#
+# set compilation execution mode
+EXECUTE:on
+#
+# print compilation command template in log file
+LOG_CMD_TEMPLATE:off
+#
+# Hierarchical Output Directories
+HIER_OUT_DIR:off
+#
+# print Pre-Compiled library info
+PRECOMPILED_INFO:on
+#
+# create backup copy of setup files
+BACKUP_SETUP_FILES:on
+#
+# use enhanced compilation techniques for faster library compilation
+# (applicable to selected libraries only)
+FAST_COMPILE:on
+#
+# save compilation results to log file with the name specified with -log option
+ADD_COMPILATION_RESULTS_TO_LOG:on
+#
+# abort compilation process if errors are detected in the library
+ABORT_ON_ERROR:off
+#
+# compile library in the directory specified by the environment variable if the
+# -dir option is not specified
+OUTPUT_DIR_ENV:
+#
+#///////////////////////////////////////////////////////////////////////
+# Setup file name: ModelSim SE
+SET:mti_se:MODELSIM=modelsim.ini
+#
+# ModelSim SE options for VHDL Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vcom -work <library> <OPTION> <file_name>
+#
+OPTION:mti_se:vhdl:u:-source -93 -novopt -explicit
+OPTION:mti_se:vhdl:s:-source -93 -novopt -explicit
+OPTION:mti_se:vhdl:c:-source -93 -novopt -explicit
+OPTION:mti_se:vhdl:r:-source -93 -novopt -explicit
+OPTION:mti_se:vhdl:i:-source -93 -novopt -explicit
+OPTION:mti_se:vhdl:e:-93 -novopt -quiet -explicit
+#
+# ModelSim SE options for VERILOG Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vlog -work <library> <OPTION> <file_name>
+#
+OPTION:mti_se:verilog:u:-source -novopt
+OPTION:mti_se:verilog:s:-source -novopt
+OPTION:mti_se:verilog:n:-source -novopt
+OPTION:mti_se:verilog:c:-source -novopt
+OPTION:mti_se:verilog:r:-source -novopt
+OPTION:mti_se:verilog:i:-source -novopt
+OPTION:mti_se:verilog:e:-novopt -quiet
+#
+#///////////////////////////////////////////////////////////////////////
+# Setup file name: ModelSim PE
+SET:mti_pe:MODELSIM=modelsim.ini
+#
+# ModelSim PE options for VHDL Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vcom -work <library> <OPTION> <file_name>
+#
+OPTION:mti_pe:vhdl:u:-source -93 -explicit
+OPTION:mti_pe:vhdl:s:-source -93 -explicit
+OPTION:mti_pe:vhdl:c:-source -93 -explicit
+OPTION:mti_pe:vhdl:r:-source -93 -explicit
+OPTION:mti_pe:vhdl:i:-source -93 -explicit
+OPTION:mti_pe:vhdl:e:-93 -novopt -quiet -explicit
+#
+# ModelSim PE options for VERILOG Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vlog -work <library> <OPTION> <file_name>
+#
+OPTION:mti_pe:verilog:u:-source
+OPTION:mti_pe:verilog:s:-source
+OPTION:mti_pe:verilog:n:-source
+OPTION:mti_pe:verilog:c:-source
+OPTION:mti_pe:verilog:r:-source
+OPTION:mti_pe:verilog:i:-source
+OPTION:mti_pe:verilog:e:-novopt -quiet
+#
+#///////////////////////////////////////////////////////////////////////
+# Setup file name: ModelSim DE
+SET:mti_de:MODELSIM=modelsim.ini
+#
+# ModelSim DE options for VHDL Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vcom -work <library> <OPTION> <file_name>
+#
+OPTION:mti_de:vhdl:u:-source -93 -novopt -explicit
+OPTION:mti_de:vhdl:s:-source -93 -novopt -explicit
+OPTION:mti_de:vhdl:c:-source -93 -novopt -explicit
+OPTION:mti_de:vhdl:r:-source -93 -novopt -explicit
+OPTION:mti_de:vhdl:i:-source -93 -novopt -explicit
+OPTION:mti_de:vhdl:e:-93 -novopt -quiet -explicit
+#
+# ModelSim DE options for VERILOG Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vlog -work <library> <OPTION> <file_name>
+#
+OPTION:mti_de:verilog:u:-source -novopt
+OPTION:mti_de:verilog:s:-source -novopt
+OPTION:mti_de:verilog:n:-source -novopt
+OPTION:mti_de:verilog:c:-source -novopt
+OPTION:mti_de:verilog:r:-source -novopt
+OPTION:mti_de:verilog:i:-source -novopt
+OPTION:mti_de:verilog:e:-novopt -quiet
+#
+#///////////////////////////////////////////////////////////////////////
+# Setup file name: QuestaSim
+SET:questa:MODELSIM=modelsim.ini
+#
+# QuestaSim options for VHDL Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vcom -work <library> <OPTION> <file_name>
+#
+OPTION:questa:vhdl:u:-source -93 -novopt -explicit
+OPTION:questa:vhdl:s:-source -93 -novopt -explicit
+OPTION:questa:vhdl:c:-source -93 -novopt -explicit
+OPTION:questa:vhdl:r:-source -93 -novopt -explicit
+OPTION:questa:vhdl:i:-source -93 -novopt -explicit
+OPTION:questa:vhdl:e:-93 -novopt -quiet -explicit
+#
+# QuestaSim options for VERILOG Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vlog -work <library> <OPTION> <file_name>
+#
+OPTION:questa:verilog:u:-source -novopt
+OPTION:questa:verilog:s:-source -novopt
+OPTION:questa:verilog:n:-source -novopt
+OPTION:questa:verilog:c:-source -novopt
+OPTION:questa:verilog:r:-source -novopt
+OPTION:questa:verilog:i:-source -novopt
+OPTION:questa:verilog:e:-novopt -quiet
+#
+#///////////////////////////////////////////////////////////////////////
+# Setup file name: Aldec
+SET:riviera:LIBRARY=library.cfg
+#
+# Aldec options for VHDL Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vcom -work <library> <OPTION> <file_name>
+#
+OPTION:riviera:vhdl:u:-93 -quiet -nowarn ELAB1_0026
+OPTION:riviera:vhdl:s:-93 -quiet -nowarn ELAB1_0026
+OPTION:riviera:vhdl:c:-93 -quiet -nowarn ELAB1_0026
+OPTION:riviera:vhdl:r:-93 -quiet -nowarn ELAB1_0026
+OPTION:riviera:vhdl:i:-93 -quiet -nowarn ELAB1_0026
+OPTION:riviera:vhdl:e:-93 -quiet -nowarn ELAB1_0026
+#
+# Aldec options for VERILOG Libraries
+# Syntax:-
+# OPTION:<simulator_name>:<language>:<library>:<options>
+# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
+#              r (coolrunner)
+# vlog -work <library> <OPTION> <file_name>
+#
+OPTION:riviera:verilog:u:-v2k5 -quiet -msg 0
+OPTION:riviera:verilog:s:-v2k5 -quiet -msg 0
+OPTION:riviera:verilog:n:-v2k5 -quiet -msg 0
+OPTION:riviera:verilog:c:-v2k5 -quiet -msg 0
+OPTION:riviera:verilog:r:-v2k5 -quiet -msg 0
+OPTION:riviera:verilog:i:-v2k5 -quiet -msg 0
+OPTION:riviera:verilog:e:-v2k5 -quiet -msg 0
+#///////////////////////////////////////////////////////////////////////
+# End
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/compxlib.log.bak
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/compxlib.log.bak	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/compxlib.log.bak	(revision 20)
@@ -0,0 +1,47 @@
+    ____  ____
+   /   /\/   /
+  /___/  \  /    VENDOR      : Xilinx Inc.
+  \   \   \/     VERSION     : 12.3 (M.70d)
+   \   \         APPLICATION : d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe
+   /   /         CONTENTS    : Compilation Log
+  /___/   /\     FILENAME    : compxlib.log
+  \   \  /  \    
+   \___\/\___\
+
+Release 12.3 - d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe 12.3 (nt64)
+Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
+
+Processing command line ...
+Reading the compxlib configuration file - 'compxlib.cfg' ...
+WARNING:Compxlib - The legacy option '-exclude_deprecated' will be obsolete in version 13.1. Please use the option '-exclude_superseded' for the same.
+Library Source Paths => 'D:/Xilinx/12.3/ISE_DS/ISE d:/Xilinx/12.3/ISE_DS/ISE'
+Current Working Directory => 'C:\Core MPI\SWITCH_GENERIC_16_16'
+Compilation Mode = FAST
+Execute Mode = ON
+Scheduling library installation & compilation for architectures: virtex5
+
+Scheduling library installation & compilation for libraries: simprim unisim xilinxcorelib edk
+
+Signature:-
+------------------------------------------------------------------------------
+d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe -s mti_pe -l vhdl -source_lib D:/Xilinx/12.3/ISE_DS/ISE -arch virtex5 -lib unisim -lib simprim -lib xilinxcorelib -lib edk -exclude_deprecated -intstyle ise 
+------------------------------------------------------------------------------
+ERROR:Compxlib - COMPXLIB[sim]: Unable to automatically find executables for simulator 'mti_pe' from the following paths:
+    d:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64
+   d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64
+   D:\Xilinx\12.3\ISE_DS\PlanAhead\bin
+   D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64
+   D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64
+   D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64
+   D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64
+   D:\Xilinx\12.3\ISE_DS\common\bin\nt64
+   D:\Xilinx\12.3\ISE_DS\common\lib\nt64
+   C:\Program Files\Common Files\Microsoft Shared\Windows Live
+   C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live
+   C:\Windows\system32
+   C:\Windows
+   C:\Windows\System32\Wbem
+   C:\Windows\System32\WindowsPowerShell\v1.0\
+   C:\Program Files (x86)\Windows Live\Shared
+   C:\Program Files\Trend Micro\AMSP.
+Simulator 'mti_pe' is ignored.
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/conv.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/conv.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/conv.vhd	(revision 20)
@@ -0,0 +1,72 @@
+--	Package File Template
+--
+--	Purpose: This package defines supplemental types, subtypes, 
+--		 constants, and functions 
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package conversions is
+
+  
+ -- type <new_type> is
+  --  record
+    --    <type_name>        : std_logic_vector( 7 downto 0);
+      --  <type_name>        : std_logic;
+    --end record;
+
+-- Declare constants
+
+  --constant <constant_name>		: time := <time_unit> ns;
+  --constant <constant_name>		: integer := <value>;
+ 
+-- Declare functions and procedure
+
+  function to_uint ( a: in std_ulogic_vector) return integer;
+  function to_vector (size: integer; val: integer) return std_ulogic_vector;
+  
+end conversions;
+
+
+package body conversions is
+  
+    -- Convert a std_ulogic_vector to an unsigned integer
+    --
+    function to_uint (a: std_ulogic_vector) return integer is
+        alias av: std_ulogic_vector (1 to a'length) is a;
+        variable val: integer := 0;
+        variable b: integer := 1;
+    begin
+        for i in a'length downto 1 loop
+            if (av(i) = '1') then    -- if LSB is '1',
+                val := val + b;       -- add value for current bit position
+            end if;
+            b := b * 2;    -- Shift left 1 bit
+        end loop;
+ 
+        return val;
+    end to_uint;
+ 
+-------------------------------------------------------- 
+    -- Convert an integer to a std_ulogic_vector
+    --
+    function to_vector (size: integer; val: integer) return std_ulogic_vector is
+        variable vec: std_ulogic_vector (1 to size);
+        variable a: integer;
+    begin
+        a := val;
+        for i in size downto 1 loop
+            if ((a mod 2) = 1) then
+                vec(i) := '1';
+            else 
+                vec(i) := '0';
+            end if;
+            a := a / 2;
+        end loop;
+        return vec;
+    end to_vector;
+ 
+
+ 
+end conversions;
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/conversions_vhdl.prj
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/conversions_vhdl.prj	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/conversions_vhdl.prj	(revision 20)
@@ -0,0 +1,1 @@
+vhdl work "C:\Core MPI\SWITCH_GENERIC_16_16\conv.vhd"
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/FIFO_256_FWFT.xreport
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/FIFO_256_FWFT.xreport	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/FIFO_256_FWFT.xreport	(revision 20)
@@ -0,0 +1,217 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+  <DateModified>2012-10-24T11:30:47</DateModified>
+  <ModuleName>testbench</ModuleName>
+  <SummaryTimeStamp>2012-10-24T11:26:11</SummaryTimeStamp>
+  <SavedFilePath>C:/Core MPI/SWITCH_GENERIC_16_16/iseconfig/FIFO_256_FWFT.xreport</SavedFilePath>
+  <ImplementationReportsDirectory>C:/Core MPI/SWITCH_GENERIC_16_16</ImplementationReportsDirectory>
+  <DateInitialized>2012-10-24T11:30:47</DateInitialized>
+  <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+  <viewgroup label="Design Overview" >
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="testbench_summary.html" label="Summary" >
+    <toc-item title="Design Overview" target="Design Overview" />
+    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+    <toc-item title="Performance Summary" target="Performance Summary" />
+    <toc-item title="Failing Constraints" target="Failing Constraints" />
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="testbench_envsettings.html" label="System Settings" />
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="testbench_map.xrpt" label="IOB Properties" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="testbench_map.xrpt" label="Control Set Information" />
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="testbench_map.xrpt" label="Module Level Utilization" />
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="testbench.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="testbench_par.xrpt" label="Pinout Report" />
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="testbench_par.xrpt" label="Clock Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="testbench.twx" label="Static Timing" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="testbench_html/fit/report.htm" label="CPLD Fitter Report" />
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="testbench_html/tim/report.htm" label="CPLD Timing Report" />
+  </viewgroup>
+  <viewgroup label="XPS Errors and Warnings" >
+   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+   <view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" />
+   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+  </viewgroup>
+  <viewgroup label="XPS Reports" >
+   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+   <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
+   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="testbench.log" label="System Log File" />
+  </viewgroup>
+  <viewgroup label="Errors and Warnings" >
+   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
+   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
+  </viewgroup>
+  <viewgroup label="Detailed Reports" >
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="testbench.syr" label="Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
+    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
+    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
+    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
+    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
+    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
+    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
+    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
+    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
+    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
+    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
+    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
+    <toc-item title="Partition Report" target="   Partition Report     " />
+    <toc-item title="Final Report" target="   Final Report   " />
+    <toc-item title="Design Summary" target="   Design Summary   " />
+    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
+    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
+    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
+    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
+    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
+    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
+    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
+    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
+    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
+   </view>
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.srr" label="Synplify Report" />
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.prec_log" label="Precision Report" />
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="testbench.bld" label="Translation Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Command Line" target="Command Line:" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+   </view>
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="testbench_map.mrp" label="Map Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
+    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
+    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
+    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
+    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
+    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
+    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
+    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
+    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
+    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
+    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
+    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
+    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="testbench.par" label="Place and Route Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+    <toc-item title="Router Information" target="Starting Router" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Clock Report" target="Generating Clock Report" />
+    <toc-item title="Timing Results" target="Timing Score:" />
+    <toc-item title="Final Summary" target="Peak Memory Usage:" />
+   </view>
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="testbench.twr" label="Post-PAR Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.rpt" label="CPLD Fitter Report (Text)" >
+    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
+    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
+    <toc-item title="Pin Resources" target="** Pin Resources **" />
+    <toc-item title="Global Resources" target="** Global Control Resources **" />
+   </view>
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.tim" label="CPLD Timing Report (Text)" >
+    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
+    <toc-item title="Performance Summary" target="Performance Summary:" />
+   </view>
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="testbench.pwr" label="Power Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Power summary" target="Power summary" />
+    <toc-item title="Thermal summary" target="Thermal summary" />
+   </view>
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="testbench.bgn" label="Bitgen Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+    <toc-item title="Final Summary" target="DRC detected" />
+   </view>
+  </viewgroup>
+  <viewgroup label="Secondary Reports" >
+   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/testbench_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/testbench_translate.nlf" label="Post-Translate Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="testbench_map.map" label="Map Log File" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Design Information" target="Design Information" />
+    <toc-item title="Design Summary" target="Design Summary" />
+   </view>
+   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_preroute.twr" label="Post-Map Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/testbench_map.nlf" label="Post-Map Simulation Model Report" />
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_map.psr" label="Physical Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="testbench_pad.txt" label="Pad Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="testbench.unroutes" label="Unroutes Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_preroute.tsi" label="Post-Map Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.grf" label="Guide Results Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.dly" label="Asynchronous Delay Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.clk_rgn" label="Clock Region Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.tsi" label="Post-Place and Route Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/testbench_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_sta.nlf" label="Primetime Netlist Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="testbench.ibs" label="IBIS Model" >
+    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
+    <toc-item title="Component" target="Component " />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.lck" label="Back-annotate Pin Report" >
+    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
+    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.lpc" label="Locked Pin Constraints" >
+    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
+    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+   </view>
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/testbench_timesim.nlf" label="Post-Fit Simulation Model Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+  </viewgroup>
+ </body>
+</report-views>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/GENERIC_16_16.projectmgr
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/GENERIC_16_16.projectmgr	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/GENERIC_16_16.projectmgr	(revision 20)
@@ -0,0 +1,691 @@
+<?xml version='1.0' encoding='utf-8'?>
+<!--This is an ISE project configuration file.-->
+<!--It holds project specific layout data for the projectmgr plugin.-->
+<!--Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.-->
+<Project version="2" owner="projectmgr" name="GENERIC_16_16" >
+   <!--This is an ISE project configuration file.-->
+   <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
+      <ClosedNodes>
+         <ClosedNodesVersion>2</ClosedNodesVersion>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT11_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT12_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT13_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT14_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT14_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT15_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT15_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT1_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description/OUTPUT_PORT_FIFO - FIFO_256_FWFT - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT2_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT2_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT3_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT3_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT4_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT5_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT5_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT6_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT6_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT7_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT7_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT8_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORT9_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORTx16_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORTx16_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORTx4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORTx8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/PORTx9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler10_10 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler11_11 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler12_12 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler13_13 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler14_14 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler15_15 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler16_16 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler3_3 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler4_4 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler5_5 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler6_6 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler7_7 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler8_8 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler9_9 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar10_10 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar11_11 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar12_12 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar13_13 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar14_14 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar15_15 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar16_16 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar2_2 - Crossbar - Behavioral</ClosedNode>
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+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler16_16 - Scheduler16_16 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler10_10 - Scheduler10_10 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler11_11 - Scheduler11_11 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler12_12 - Scheduler12_12 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler13_13 - Scheduler13_13 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler14_14 - Scheduler14_14 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler15_15 - Scheduler15_15 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler16_16 - Scheduler16_16 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler2_2 - Scheduler2_2 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler3_3 - Scheduler3_3 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler4_4 - Scheduler4_4 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler5_5 - Scheduler5_5 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler6_6 - Scheduler6_6 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler7_7 - Scheduler7_7 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler8_8 - Scheduler8_8 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler9_9 - Scheduler9_9 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler3_3 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler4_4 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler5_5 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler6_6 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler7_7 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler8_8 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Scheduler9_9 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar10_10 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar11_11 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar12_12 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar13_13 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar14_14 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar15_15 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar16_16 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar2_2 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar3_3 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar4_4 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar5_5 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar6_6 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar7_7 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar8_8 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar9_9 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT11_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT12_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT13_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT14_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT14_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT15_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT15_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT16_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT16_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT1_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT2_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT2_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT3_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT3_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT4_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT5_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT5_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT6_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT6_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT7_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT7_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT8_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT9_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler10_10 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler11_11 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler12_12 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler13_13 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler14_14 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler15_15 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler16_16 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler10_10 - Scheduler10_10 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler11_11 - Scheduler11_11 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler12_12 - Scheduler12_12 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler13_13 - Scheduler13_13 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler14_14 - Scheduler14_14 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler15_15 - Scheduler15_15 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler16_16 - Scheduler16_16 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler2_2 - Scheduler2_2 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler3_3 - Scheduler3_3 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler4_4 - Scheduler4_4 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler5_5 - Scheduler5_5 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler6_6 - Scheduler6_6 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler7_7 - Scheduler7_7 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler8_8 - Scheduler8_8 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler9_9 - Scheduler9_9 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler3_3 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler10_10 - Scheduler10_10 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler11_11 - Scheduler11_11 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler12_12 - Scheduler12_12 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler13_13 - Scheduler13_13 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler14_14 - Scheduler14_14 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler15_15 - Scheduler15_15 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler16_16 - Scheduler16_16 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler2_2 - Scheduler2_2 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler3_3 - Scheduler3_3 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler4_4 - Scheduler4_4 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler5_5 - Scheduler5_5 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler6_6 - Scheduler6_6 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler7_7 - Scheduler7_7 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler8_8 - Scheduler8_8 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler4_4 - Scheduler - Behavioral/Inst_Scheduler9_9 - Scheduler9_9 - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler5_5 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler6_6 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler7_7 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler8_8 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler9_9 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar10_10 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar11_11 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar12_12 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar13_13 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar14_14 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar15_15 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar16_16 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar2_2 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar3_3 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar4_4 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar5_5 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar6_6 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar7_7 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar8_8 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Switch_Crossbar9_9 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Xilinx|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd</ClosedNode>
+         <ClosedNode>/conversions C:|Core MPI|SWITCH_GENERIC_16_16|conv.vhd</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT14_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT15_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT1_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT2_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT2_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT3_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT3_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT4_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT5_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT6_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT7_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT8_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORT9_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORTx16_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORTx16_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORTx4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORTx8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/PORTx9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler10_10 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler11_11 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler12_12 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler13_13 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler14_14 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler15_15 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler10_10 - Scheduler10_10 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler11_11 - Scheduler11_11 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler12_12 - Scheduler12_12 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler13_13 - Scheduler13_13 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler14_14 - Scheduler14_14 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler15_15 - Scheduler15_15 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler16_16 - Scheduler16_16 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler2_2 - Scheduler2_2 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler3_3 - Scheduler3_3 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler4_4 - Scheduler4_4 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler5_5 - Scheduler5_5 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler6_6 - Scheduler6_6 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler7_7 - Scheduler7_7 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler8_8 - Scheduler8_8 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral/Inst_Scheduler9_9 - Scheduler9_9 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler2_2 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler3_3 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler4_4 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler5_5 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler6_6 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler7_7 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler10_10 - Scheduler10_10 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler11_11 - Scheduler11_11 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler12_12 - Scheduler12_12 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler13_13 - Scheduler13_13 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler14_14 - Scheduler14_14 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler15_15 - Scheduler15_15 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler16_16 - Scheduler16_16 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler2_2 - Scheduler2_2 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler3_3 - Scheduler3_3 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler4_4 - Scheduler4_4 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler5_5 - Scheduler5_5 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler6_6 - Scheduler6_6 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler7_7 - Scheduler7_7 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler8_8 - Scheduler8_8 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral/Inst_Scheduler9_9 - Scheduler9_9 - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Scheduler9_9 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar10_10 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar11_11 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar12_12 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar13_13 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar14_14 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar15_15 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar16_16 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar2_2 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar3_3 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar4_4 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar5_5 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar6_6 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar7_7 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar8_8 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar9_9 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT11_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT12_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT13_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT14_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
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+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Scheduler7_7 - Scheduler - Behavioral</ClosedNode>
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+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Scheduler9_9 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar10_10 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar11_11 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar12_12 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar13_13 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar14_14 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar15_15 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar16_16 - Crossbar - Behavioral</ClosedNode>
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+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar6_6 - Crossbar - Behavioral</ClosedNode>
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+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/Switch_Crossbar9_9 - Crossbar - Behavioral</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Documents and Settings|user|Mes documents|These|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral</ClosedNode>
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+         <ClosedNodesVersion>1</ClosedNodesVersion>
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+         <SelectedItem>Simulate Behavioral Model</SelectedItem>
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+      </ClosedNodes>
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+      </SelectedItems>
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+   </ItemView>
+   <ItemView engineview="PostTransSim" guiview="Source" compilemode="AutoCompile" >
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+         <ClosedNodesVersion>2</ClosedNodesVersion>
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+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem>Unassigned User Library Modules</SelectedItem>
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+         <ClosedNodesVersion>1</ClosedNodesVersion>
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+         <SelectedItem>Compile HDL Simulation Libraries</SelectedItem>
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+   </ItemView>
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+   <ItemView engineview="PostMapSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
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+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem/>
+   </ItemView>
+</Project>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/SWITCH_GEN.xreport
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/SWITCH_GEN.xreport	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/SWITCH_GEN.xreport	(revision 20)
@@ -0,0 +1,217 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+  <DateModified>2012-10-22T15:05:29</DateModified>
+  <ModuleName>FIFO_256_FWFT</ModuleName>
+  <SummaryTimeStamp>2012-07-18T16:27:43</SummaryTimeStamp>
+  <SavedFilePath>C:/Core MPI/SWITCH_GENERIC_16_16/iseconfig/SWITCH_GEN.xreport</SavedFilePath>
+  <ImplementationReportsDirectory>C:/Core MPI/SWITCH_GENERIC_16_16\</ImplementationReportsDirectory>
+  <DateInitialized>2012-10-22T15:05:29</DateInitialized>
+  <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+  <viewgroup label="Design Overview" >
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="FIFO_256_FWFT_summary.html" label="Summary" >
+    <toc-item title="Design Overview" target="Design Overview" />
+    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+    <toc-item title="Performance Summary" target="Performance Summary" />
+    <toc-item title="Failing Constraints" target="Failing Constraints" />
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="FIFO_256_FWFT_envsettings.html" label="System Settings" />
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="FIFO_256_FWFT_map.xrpt" showConstraints="0" label="IOB Properties" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="FIFO_256_FWFT_map.xrpt" label="Control Set Information" />
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="FIFO_256_FWFT_map.xrpt" label="Module Level Utilization" />
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="FIFO_256_FWFT.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="FIFO_256_FWFT_par.xrpt" label="Pinout Report" />
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="FIFO_256_FWFT_par.xrpt" label="Clock Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="FIFO_256_FWFT.twx" label="Static Timing" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="FIFO_256_FWFT_html/fit/report.htm" label="CPLD Fitter Report" />
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="FIFO_256_FWFT_html/tim/report.htm" label="CPLD Timing Report" />
+  </viewgroup>
+  <viewgroup label="XPS Errors and Warnings" >
+   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+   <view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" />
+   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+  </viewgroup>
+  <viewgroup label="XPS Reports" >
+   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+   <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
+   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="FIFO_256_FWFT.log" label="System Log File" />
+  </viewgroup>
+  <viewgroup label="Errors and Warnings" >
+   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
+   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
+  </viewgroup>
+  <viewgroup label="Detailed Reports" >
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="FIFO_256_FWFT.syr" label="Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
+    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
+    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
+    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
+    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
+    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
+    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
+    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
+    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
+    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
+    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
+    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
+    <toc-item title="Partition Report" target="   Partition Report     " />
+    <toc-item title="Final Report" target="   Final Report   " />
+    <toc-item title="Design Summary" target="   Design Summary   " />
+    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
+    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
+    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
+    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
+    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
+    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
+    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
+    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
+    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
+   </view>
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="FIFO_256_FWFT.srr" label="Synplify Report" />
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="FIFO_256_FWFT.prec_log" label="Precision Report" />
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="FIFO_256_FWFT.bld" label="Translation Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Command Line" target="Command Line:" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+   </view>
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="FIFO_256_FWFT_map.mrp" label="Map Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
+    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
+    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
+    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
+    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
+    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
+    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
+    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
+    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
+    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
+    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
+    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
+    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="FIFO_256_FWFT.par" label="Place and Route Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+    <toc-item title="Router Information" target="Starting Router" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Clock Report" target="Generating Clock Report" />
+    <toc-item title="Timing Results" target="Timing Score:" />
+    <toc-item title="Final Summary" target="Peak Memory Usage:" />
+   </view>
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="FIFO_256_FWFT.twr" label="Post-PAR Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="FIFO_256_FWFT.rpt" label="CPLD Fitter Report (Text)" >
+    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
+    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
+    <toc-item title="Pin Resources" target="** Pin Resources **" />
+    <toc-item title="Global Resources" target="** Global Control Resources **" />
+   </view>
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="FIFO_256_FWFT.tim" label="CPLD Timing Report (Text)" >
+    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
+    <toc-item title="Performance Summary" target="Performance Summary:" />
+   </view>
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="FIFO_256_FWFT.pwr" label="Power Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Power summary" target="Power summary" />
+    <toc-item title="Thermal summary" target="Thermal summary" />
+   </view>
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="FIFO_256_FWFT.bgn" label="Bitgen Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+    <toc-item title="Final Summary" target="DRC detected" />
+   </view>
+  </viewgroup>
+  <viewgroup label="Secondary Reports" >
+   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/FIFO_256_FWFT_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/FIFO_256_FWFT_translate.nlf" label="Post-Translate Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="FIFO_256_FWFT_map.map" label="Map Log File" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Design Information" target="Design Information" />
+    <toc-item title="Design Summary" target="Design Summary" />
+   </view>
+   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT_preroute.twr" label="Post-Map Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/FIFO_256_FWFT_map.nlf" label="Post-Map Simulation Model Report" />
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT_map.psr" label="Physical Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="FIFO_256_FWFT_pad.txt" label="Pad Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="FIFO_256_FWFT.unroutes" label="Unroutes Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT_preroute.tsi" label="Post-Map Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT.grf" label="Guide Results Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT.dly" label="Asynchronous Delay Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT.clk_rgn" label="Clock Region Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT.tsi" label="Post-Place and Route Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/FIFO_256_FWFT_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT_sta.nlf" label="Primetime Netlist Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT.ibs" label="IBIS Model" >
+    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
+    <toc-item title="Component" target="Component " />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT.lck" label="Back-annotate Pin Report" >
+    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
+    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FIFO_256_FWFT.lpc" label="Locked Pin Constraints" >
+    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
+    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+   </view>
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/FIFO_256_FWFT_timesim.nlf" label="Post-Fit Simulation Model Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+  </viewgroup>
+ </body>
+</report-views>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/SWITCH_GENERIQUE.xreport
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/SWITCH_GENERIQUE.xreport	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/SWITCH_GENERIQUE.xreport	(revision 20)
@@ -0,0 +1,181 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="1.7" >
+ <header>
+  <DateModified>2011-11-19T23:52:40</DateModified>
+  <ModuleName>SWITCH_GEN</ModuleName>
+  <SummaryTimeStamp>2011-11-19T23:36:21</SummaryTimeStamp>
+  <DateInitialized>2011-11-19T23:52:40</DateInitialized>
+  <ImplementationReportsDirectory>C:/Core MPI/SWITCH_GENERIC_16_16\</ImplementationReportsDirectory>
+  <SavedFilePath>C:/Core MPI/SWITCH_GENERIC_16_16/iseconfig/SWITCH_GENERIQUE.xreport</SavedFilePath>
+  <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+  <viewgroup label="Design Overview" >
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="SWITCH_GEN_summary.html" label="Summary" >
+    <toc-item title="Design Overview" target="Design Overview" />
+    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+    <toc-item title="Performance Summary" target="Performance Summary" />
+    <toc-item title="Failing Constraints" target="Failing Constraints" />
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY,EDK_OFF" hidden="true" type="HTML" file="SWITCH_GEN_partitions.html" label="Partition Report" >
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="SWITCH_GEN_map.xrpt" label="IOB Properties" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="SWITCH_GEN_map.xrpt" label="Control Set Information" />
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="SWITCH_GEN_map.xrpt" label="Module Level Utilization" />
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="SWITCH_GEN.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="SWITCH_GEN_par.xrpt" label="Pinout Report" />
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="SWITCH_GEN_par.xrpt" label="Clock Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="SWITCH_GEN.twx" label="Static Timing" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/fit/report.htm" label="CPLD Fitter Report" />
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/tim/report.htm" label="CPLD Timing Report" />
+  </viewgroup>
+  <viewgroup label="XPS Errors and Warnings" >
+   <view program="platgen" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+   <view program="libgen" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/libgen.xmsgs" label="Libgen Messages" />
+   <view program="simgen" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+   <view program="bitinit" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+  </viewgroup>
+  <viewgroup label="XPS Reports" >
+   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="../platgen.log" label="Platgen Log File" />
+   <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="../libgen.log" label="Libgen Log File" />
+   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="../simgen.log" label="Simgen Log File" />
+   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="../bitinit.log" label="BitInit Log File" />
+  </viewgroup>
+  <viewgroup label="Errors and Warnings" >
+   <view inputState="Unknown" program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+   <view inputState="Synthesized" program="ngdbuild" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+   <view inputState="Current" program="implementation" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Current Messages" />
+   <view inputState="Current" program="fitting" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Current Messages (CPLD)" />
+  </viewgroup>
+  <viewgroup label="Detailed Reports" >
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="SWITCH_GEN.syr" label="Synthesis Report" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
+    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
+    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
+    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
+    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
+    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " />
+    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
+    <toc-item title="Partition Report" target="   Partition Report     " />
+    <toc-item title="Final Report" target="   Final Report   " />
+   </view>
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.srr" label="Synplify Report" />
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.prec_log" label="Precision Report" />
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="SWITCH_GEN.bld" label="Translation Report" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Command Line" target="Command Line:" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+   </view>
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN_map.mrp" label="Map Report" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Section 1: Errors" target="Section 1 - " />
+    <toc-item title="Section 2: Warnings" target="Section 2 - " />
+    <toc-item title="Section 3: Infos" target="Section 3 - " />
+    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 - " />
+    <toc-item title="Section 5: Removed Logic" target="Section 5 - " />
+    <toc-item title="Section 6: IOB Properties" target="Section 6 - " />
+    <toc-item title="Section 7: RPMs" target="Section 7 - " />
+    <toc-item title="Section 8: Guide Report" target="Section 8 - " />
+    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 - " />
+    <toc-item title="Section 10: Modular Design Summary" target="Section 10 - " />
+    <toc-item title="Section 11: Timing Report" target="Section 11 - " />
+    <toc-item title="Section 12: Configuration String Details" target="Section 12 - " />
+    <toc-item title="Section 13: Control Set Information" target="Section 13 - " />
+    <toc-item title="Section 14: Utilization by Hierarchy" target="Section 14 - " />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.par" label="Place and Route Report" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+    <toc-item title="Router Information" target="Starting Router" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Clock Report" target="Generating Clock Report" />
+    <toc-item title="Timing Results" target="Timing Score:" />
+    <toc-item title="Final Summary" target="Peak Memory Usage:" />
+   </view>
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.twr" label="Post-PAR Static Timing Report" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Data Sheet Report" target="Data Sheet" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+   </view>
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.rpt" label="CPLD Fitter Report (Text)" >
+    <toc-item title="Top of Report" target="cpldfit:" />
+    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
+    <toc-item title="Pin Resources" target="** Pin Resources **" />
+    <toc-item title="Global Resources" target="** Global Control Resources **" />
+   </view>
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.tim" label="CPLD Timing Report (Text)" >
+    <toc-item title="Top of Report" target="Performance Summary Report" />
+    <toc-item title="Performance Summary" target="Performance Summary:" />
+   </view>
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="SWITCH_GEN.pwr" label="Power Report" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Power summary" target="Power summary" />
+    <toc-item title="Thermal summary" target="Thermal summary" />
+   </view>
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.bgn" label="Bitgen Report" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+    <toc-item title="Final Summary" target="DRC detected" />
+   </view>
+  </viewgroup>
+  <viewgroup label="Secondary Reports" >
+   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/SWITCH_GEN_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/SWITCH_GEN_translate.nlf" label="Post-Translate Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN_map.map" label="Map Log File" >
+    <toc-item title="Top of Report" target="Release" />
+    <toc-item title="Design Information" target="Design Information" />
+    <toc-item title="Design Summary" target="Design Summary" />
+   </view>
+   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.twr" label="Post-Map Static Timing Report" />
+   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/SWITCH_GEN_map.nlf" label="Post-Map Simulation Model Report" />
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_map.psr" label="Physical Synthesis Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="SWITCH_GEN_pad.txt" label="Pad Report" >
+    <toc-item title="Top of Report" target="Release" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN.unroutes" label="Unroutes Report" >
+    <toc-item title="Top of Report" target="Release" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.grf" label="Guide Results Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.dly" label="Asynchronous Delay Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.clk_rgn" label="Clock Region Report" />
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/SWITCH_GEN_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_sta.nlf" label="Primetime Netlist Report" >
+    <toc-item title="Top of Report" target="Release" />
+   </view>
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.ibs" label="IBIS Model" >
+    <toc-item title="Top of Report" target="IBIS Models for" />
+    <toc-item title="Component" target="Component " />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lck" label="Back-annotate Pin Report" >
+    <toc-item title="Top of Report" target="pin2ucf Report File" />
+    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lpc" label="Locked Pin Constraints" >
+    <toc-item title="Top of Report" target="top.lpc" />
+    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+   </view>
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/SWITCH_GEN_timesim.nlf" label="Post-Fit Simulation Model Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+  </viewgroup>
+ </body>
+</report-views>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/testbench.xreport
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/testbench.xreport	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/testbench.xreport	(revision 20)
@@ -0,0 +1,217 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+  <DateModified>2012-11-29T18:08:12</DateModified>
+  <ModuleName>testbench</ModuleName>
+  <SummaryTimeStamp>Unknown</SummaryTimeStamp>
+  <SavedFilePath>C:/Core MPI/SWITCH_GENERIC_16_16/iseconfig/testbench.xreport</SavedFilePath>
+  <ImplementationReportsDirectory>C:/Core MPI/SWITCH_GENERIC_16_16\</ImplementationReportsDirectory>
+  <DateInitialized>2012-10-24T12:13:41</DateInitialized>
+  <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+  <viewgroup label="Design Overview" >
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="testbench_summary.html" label="Summary" >
+    <toc-item title="Design Overview" target="Design Overview" />
+    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+    <toc-item title="Performance Summary" target="Performance Summary" />
+    <toc-item title="Failing Constraints" target="Failing Constraints" />
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="testbench_envsettings.html" label="System Settings" />
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="testbench_map.xrpt" label="IOB Properties" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="testbench_map.xrpt" label="Control Set Information" />
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="testbench_map.xrpt" label="Module Level Utilization" />
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="testbench.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="testbench_par.xrpt" label="Pinout Report" />
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="testbench_par.xrpt" label="Clock Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="testbench.twx" label="Static Timing" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="testbench_html/fit/report.htm" label="CPLD Fitter Report" />
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="testbench_html/tim/report.htm" label="CPLD Timing Report" />
+  </viewgroup>
+  <viewgroup label="XPS Errors and Warnings" >
+   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+   <view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" />
+   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+  </viewgroup>
+  <viewgroup label="XPS Reports" >
+   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+   <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
+   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="testbench.log" label="System Log File" />
+  </viewgroup>
+  <viewgroup label="Errors and Warnings" >
+   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
+   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
+  </viewgroup>
+  <viewgroup label="Detailed Reports" >
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="testbench.syr" label="Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
+    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
+    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
+    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
+    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
+    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
+    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
+    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
+    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
+    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
+    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
+    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
+    <toc-item title="Partition Report" target="   Partition Report     " />
+    <toc-item title="Final Report" target="   Final Report   " />
+    <toc-item title="Design Summary" target="   Design Summary   " />
+    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
+    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
+    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
+    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
+    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
+    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
+    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
+    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
+    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
+   </view>
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.srr" label="Synplify Report" />
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.prec_log" label="Precision Report" />
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="testbench.bld" label="Translation Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Command Line" target="Command Line:" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+   </view>
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="testbench_map.mrp" label="Map Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
+    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
+    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
+    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
+    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
+    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
+    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
+    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
+    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
+    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
+    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
+    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
+    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="testbench.par" label="Place and Route Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+    <toc-item title="Router Information" target="Starting Router" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Clock Report" target="Generating Clock Report" />
+    <toc-item title="Timing Results" target="Timing Score:" />
+    <toc-item title="Final Summary" target="Peak Memory Usage:" />
+   </view>
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="testbench.twr" label="Post-PAR Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.rpt" label="CPLD Fitter Report (Text)" >
+    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
+    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
+    <toc-item title="Pin Resources" target="** Pin Resources **" />
+    <toc-item title="Global Resources" target="** Global Control Resources **" />
+   </view>
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="testbench.tim" label="CPLD Timing Report (Text)" >
+    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
+    <toc-item title="Performance Summary" target="Performance Summary:" />
+   </view>
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="testbench.pwr" label="Power Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Power summary" target="Power summary" />
+    <toc-item title="Thermal summary" target="Thermal summary" />
+   </view>
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="testbench.bgn" label="Bitgen Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+    <toc-item title="Final Summary" target="DRC detected" />
+   </view>
+  </viewgroup>
+  <viewgroup label="Secondary Reports" >
+   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/testbench_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/testbench_translate.nlf" label="Post-Translate Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="testbench_map.map" label="Map Log File" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Design Information" target="Design Information" />
+    <toc-item title="Design Summary" target="Design Summary" />
+   </view>
+   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_preroute.twr" label="Post-Map Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/testbench_map.nlf" label="Post-Map Simulation Model Report" />
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_map.psr" label="Physical Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="testbench_pad.txt" label="Pad Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="testbench.unroutes" label="Unroutes Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench_preroute.tsi" label="Post-Map Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.grf" label="Guide Results Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.dly" label="Asynchronous Delay Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.clk_rgn" label="Clock Region Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.tsi" label="Post-Place and Route Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/testbench_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="testbench_sta.nlf" label="Primetime Netlist Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="testbench.ibs" label="IBIS Model" >
+    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
+    <toc-item title="Component" target="Component " />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.lck" label="Back-annotate Pin Report" >
+    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
+    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="testbench.lpc" label="Locked Pin Constraints" >
+    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
+    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+   </view>
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/testbench_timesim.nlf" label="Post-Fit Simulation Model Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+  </viewgroup>
+ </body>
+</report-views>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/pepExtractor.prj
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/pepExtractor.prj	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/pepExtractor.prj	(revision 20)
@@ -0,0 +1,1 @@
+work	"C:/Core MPI/SWITCH_GENERIC_16_16//OUTPUT_PORT_MODULE.vhd"
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/pinlock.rpt
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/pinlock.rpt	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/pinlock.rpt	(revision 20)
@@ -0,0 +1,53 @@
+
+		pin2ucf Report File
+Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
+	   Created : Fri Feb 10 18:11:10 2012
+
+
+
+Constraint Conflicts Information
+================================
+
+   This section provides information on the constraint conflicts 
+   if pin2ucf were to write a ucf file using the provided design and
+   the existing ucf file. There are 2 types of conflicts that can
+   occur.
+
+   1. Multiple pins could be constrained on the same net
+   2. Same pin could have multiple nets 
+
+   pin2ucf provides a list each for both.
+
+   Note:- "New NET" and "New PIN" indicates the Net and Pin
+   locations found suitable by pin2ucf for pin locking, while
+   "Old Net" and "Old PIN" indicates the Net and Pin locations
+   already set by the user in the ucf file, which were left 
+   untouched by pin2ucf.
+
+
+Net name conflicts on the pins
+-------------------------------
+
+
+----------------------------------------------------------------------
+PIN Location                           New NET              Old NET
+
+----------------------------------------------------------------------
+
+"No net name conflicts were found on pins"
+
+
+Pin name conflicts on the nets
+-------------------------------
+
+
+----------------------------------------------------------------------
+NET Name                               New PIN              Old PIN
+
+----------------------------------------------------------------------
+
+"No pin name conflicts were found on nets"
+
+
+PinLocking Successful. Constraints written to UCF File
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/proto_send.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/proto_send.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/proto_send.vhd	(revision 20)
@@ -0,0 +1,125 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    18:01:21 10/23/2012 
+-- Design Name: 
+-- Module Name:    proto_send - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use work.CoreTypes.all;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity proto_send is
+generic (sizemem : natural := 64);
+ port (
+ clk,reset : in std_logic;
+ fifo_empty,fifo_full : in std_logic;
+  push : out std_logic:='0';
+ fifo_in : out std_logic_vector(Word-1 downto 0);
+ snd_start : in std_logic; --début de la réception
+ snd_ack :in std_logic;   -- acquittement de la réception
+ snd_comp : out std_logic; -- fin de la réception
+ mem :in memory(0 to sizemem-1));
+
+end proto_send;
+
+architecture Behavioral of proto_send is
+type typ_send is (s_head,s_len,s_len2,s_data,s_pulse,s_end);
+ signal etsnd : typ_send;
+ signal sfifo_in : std_logic_vector(Word-1 downto 0);
+ signal spush : std_logic:='0';
+begin
+
+proc_send : process (clk,reset)
+variable dlen,i: natural range 0 to 255 :=0;
+	begin
+	if reset='1' then 
+				 etsnd<=s_head;
+				 
+				else  
+						if rising_edge(clk) then -- le process s'exécute sur chaque front 
+															-- montant de l'horloge
+						case etsnd is
+						when s_head  =>
+							sfifo_in<=mem(0);
+							snd_comp<='0';
+							i:=0;
+							
+							if fifo_empty='1' and snd_start='1' then
+							spush<='1';
+							snd_comp<='0';
+							etsnd<=s_len;
+							end if;
+						when s_pulse =>
+							spush<='1';
+							etsnd<=s_len;
+						when s_len  =>
+							sfifo_in<=mem(1); --8 données
+							i:=i+1;
+							dlen:=to_integer(unsigned(mem(i)));
+							spush<='1';
+							snd_comp<='0';
+							etsnd<=s_data;
+						when s_len2 =>
+							snd_comp<='0';
+								etsnd<=s_data;
+								
+						when s_data  =>
+								if fifo_full='0' then
+								i:=i+1;
+								sfifo_in<=mem(i);
+									if i=dlen-2 then
+										etsnd<=s_end;
+										snd_comp<='1';
+										spush<='1';
+									else
+										spush<='1';
+									end if;
+									
+								else
+								spush<='0';
+								end if;
+						
+						when s_end  =>
+								spush<='0';
+								etsnd<=s_head;
+								sfifo_in<=(others=>'-');
+								if snd_ack='1' then
+									etsnd<=s_head;
+								end if;
+						when others =>
+								spush<='0';
+								etsnd<=s_head;
+								sfifo_in<=(others=>'0');
+						end case;
+						end if;
+				end if;
+	end process;
+	
+	-- affectation concurentes
+	
+	push<=spush;
+	fifo_in<=sfifo_in;
+end Behavioral;
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/scheduler2_2.stx
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/scheduler2_2.stx	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/scheduler2_2.stx	(revision 20)
@@ -0,0 +1,36 @@
+Release 11.1 - xst L.33 (nt)
+Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
+--> Parameter TMPDIR set to C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 1.00 secs
+Total CPU time to Xst completion: 0.18 secs
+ 
+--> Parameter xsthdpdir set to C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst
+
+
+Total REAL time to Xst completion: 1.00 secs
+Total CPU time to Xst completion: 0.18 secs
+ 
+--> 
+=========================================================================
+*                          HDL Compilation                              *
+=========================================================================
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/Arbiter.vhd" in Library work.
+Architecture behavioral of Entity arbiter is up to date.
+Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/scheduler2_2.vhd" in Library work.
+Entity <scheduler2_2> compiled.
+Entity <scheduler2_2> (Architecture <behavioral>) compiled.
+
+
+Total REAL time to Xst completion: 1.00 secs
+Total CPU time to Xst completion: 0.34 secs
+ 
+--> 
+
+Total memory usage is 119772 kilobytes
+
+Number of errors   :    0 (   0 filtered)
+Number of warnings :    0 (   0 filtered)
+Number of infos    :    0 (   0 filtered)
+
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/scheduler2_2.xst
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/scheduler2_2.xst	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/scheduler2_2.xst	(revision 20)
@@ -0,0 +1,5 @@
+set -tmpdir "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst/projnav.tmp"
+set -xsthdpdir "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/xst"
+elaborate
+-ifn scheduler2_2.prj
+-ifmt mixed
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/stimuli1.v
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/stimuli1.v	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/stimuli1.v	(revision 20)
@@ -0,0 +1,50 @@
+-- GENERATEUR DE STIMILUS POUR LE TEST DU SWITCH CROSSBAR
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+
+entity stimuli45 is 
+port (clk : in std_logic;
+      reset : in std_logic;
+       wr_en : out std_logic;
+      data : out std_logic_vector(7 downto 0));
+end stimuli45;
+
+architecture behavioral of stimuli45 is
+type rom_type is array (69 downto 0) of std_logic_vector (7 downto 0);
+signal ROM : rom_type:= (
+						X"01", X"28", X"00" ,X"01" ,X"02" ,X"03" ,
+						X"04" ,X"05" ,X"06" ,X"07" ,X"08" ,X"09" ,
+						X"0a" ,X"0b" ,X"0c" ,X"0d" ,X"0e" ,X"0f" ,
+						X"10" ,X"11" ,X"12" ,X"13" ,X"14" ,X"15" ,
+						X"16" ,X"17" ,X"18" ,X"19" ,X"1a" ,X"1b" ,
+						X"1c" ,X"1d" ,X"1e" ,X"1f" ,X"20" ,X"21" ,
+						X"22" ,X"23" ,X"24" ,X"25" ,X"02", X"1e", 
+						X"00" ,X"01" ,X"02" ,X"03" ,X"04" ,X"05" ,
+						X"06" ,X"07" ,X"08" ,X"09" ,X"0a" ,X"0b" ,
+						X"0c" ,X"0d" ,X"0e" ,X"0f" ,X"10" ,X"11" ,
+						X"12" ,X"13" ,X"14" ,X"15" ,X"16" ,X"17" ,
+						X"18" ,X"19" ,X"1a" ,X"1b" );
+
+constant max_address : std_logic_vector(6 downto 0) :="1000101";
+signal address_counter : std_logic_vector(6 downto 0) := (others => '0');
+begin
+
+data <= ROM(conv_integer(address_counter));
+process (clk)
+  begin
+     if rising_edge(clk) then
+        if reset = '1' then
+            wr_en <='1';
+            address_counter <= (others=>'0');
+        elsif address_counter < max_address then
+             wr_en <='1';
+              address_counter <= address_counter +1;
+             else
+             wr_en <='0';
+             end if;
+    end if;
+  end process;
+end behavioral;
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/stimuli1.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/stimuli1.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/stimuli1.vhd	(revision 20)
@@ -0,0 +1,50 @@
+-- GENERATEUR DE STIMILUS POUR LE TEST DU SWITCH CROSSBAR
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+
+entity stimuli45 is 
+port (clk : in std_logic;
+      reset : in std_logic;
+       wr_en : out std_logic;
+      data : out std_logic_vector(7 downto 0));
+end stimuli45;
+
+architecture behavioral of stimuli45 is
+type rom_type is array (0 to 69) of std_logic_vector (7 downto 0);
+signal ROM : rom_type:= (
+						X"55", X"28", X"00" ,X"01" ,X"02" ,X"03" ,
+						X"04" ,X"05" ,X"06" ,X"07" ,X"08" ,X"09" ,
+						X"0a" ,X"0b" ,X"0c" ,X"0d" ,X"0e" ,X"0f" ,
+						X"10" ,X"11" ,X"12" ,X"13" ,X"14" ,X"15" ,
+						X"16" ,X"17" ,X"18" ,X"19" ,X"1a" ,X"1b" ,
+						X"1c" ,X"1d" ,X"1e" ,X"1f" ,X"20" ,X"21" ,
+						X"22" ,X"23" ,X"24" ,X"25" ,X"52", X"1e", 
+						X"00" ,X"01" ,X"02" ,X"03" ,X"04" ,X"05" ,
+						X"06" ,X"07" ,X"08" ,X"09" ,X"0a" ,X"0b" ,
+						X"0c" ,X"0d" ,X"0e" ,X"0f" ,X"10" ,X"11" ,
+						X"12" ,X"13" ,X"14" ,X"15" ,X"16" ,X"17" ,
+						X"18" ,X"19" ,X"1a" ,X"1b" );
+
+constant max_address : std_logic_vector(6 downto 0) :="1000101";
+signal address_counter : std_logic_vector(6 downto 0) := (others => '0');
+begin
+
+data <= ROM(conv_integer(address_counter));
+process (clk)
+  begin
+     if rising_edge(clk) then
+        if reset = '1' then
+            wr_en <='1';
+            address_counter <= (others=>'0');
+        elsif address_counter < max_address then
+             wr_en <='1';
+              address_counter <= address_counter +1;
+             else
+             wr_en <='0';
+             end if;
+    end if;
+  end process;
+end behavioral;
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_16x16_map.prj
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_16x16_map.prj	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_16x16_map.prj	(revision 20)
@@ -0,0 +1,2 @@
+vhdl work "netgen/map/SWITCH_GEN_map.vhd"
+vhdl work "test_xbar_8x8.vhd"
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_16x16_translate.prj
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_16x16_translate.prj	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_16x16_translate.prj	(revision 20)
@@ -0,0 +1,2 @@
+vhdl work "netgen/translate/SWITCH_GEN_translate.vhd"
+vhdl work "test_xbar_8x8.vhd"
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_8x8.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_8x8.vhd	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_8x8.vhd	(revision 20)
@@ -0,0 +1,716 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:	GAMOM NGOUNOU
+--
+-- Create Date:   19:03:05 07/11/2011
+-- Design Name:   
+-- Module Name:   C:/Xilinx/SWITCH_GENERIC_16_16/test_xbar_8x8.vhd
+-- Project Name:  GENERIC_16_16
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: SWITCH_GENERIQUE
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+--use IEEE.std_logic_textio.ALL;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+use work.Coretypes.all;
+
+
+ENTITY test_xbar_8x8 IS
+END test_xbar_8x8;
+ 
+ARCHITECTURE behavior OF test_xbar_8x8 IS 
+ CONSTANT MAXPORT :natural:=8; 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT SWITCH_GEN
+	 GENERIC (number_of_ports : positive := MAXPORT);
+    PORT(
+	      clk : IN  std_logic;
+			reset : IN  std_logic;
+			
+			Port_in : in typ_portIO(1 to MAXPORT) ;
+			Port_out : out  typ_portIO(1 to MAXPORT);
+
+         cmd_in_en : IN  std_logic_vector(MAXPORT downto 1);
+			data_in_en : IN  std_logic_vector(MAXPORT downto 1);
+			data_out_en : IN  std_logic_vector(MAXPORT downto 1);
+         fifo_in_full : OUT  std_logic_vector(MAXPORT downto 1);
+         fifo_in_empty : OUT  std_logic_vector(MAXPORT downto 1);
+         data_available : OUT  std_logic_vector(MAXPORT downto 1)
+         
+        );
+    END COMPONENT;
+    COMPONENT Stimport5
+	 port (
+			 clk : in std_logic;
+			 reset : in std_logic;
+			 clk_en : in std_logic;
+			 wr_en : out std_logic;
+			 data : out std_logic_vector (7 downto 0)
+			 );
+	 
+	 END COMPONENT;
+	type naturel is array (natural range <>) of natural  range 0 to 511; 
+	type typ_send is (s_head,s_len,s_len2,s_data,s_end);
+	type typ_receiv is (r_wait,r_head,r_dlen,r_glen,r_start,r_end);
+	type typ_cmd is (cmdstart,cmdpost,cmdpostidle,cmdread,cmdlen,cmdglen,cmddata,cmdend,cmdtimeout);
+
+		signal etsnd1,etsnd2,etsnd3 : typ_send;
+		signal etrec:typ_receiv;   --pour la machine à état de réception
+		signal etcmd :typ_cmd;     --pour la machine à état de commande
+   --Inputs
+  signal PortIn : Typ_portio (1 to MAXPORT);  
+  --Outputs
+	signal portOut : Typ_portio(1 to maxport);
+	
+   signal data_in_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
+	signal cmd_in_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
+   signal data_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
+	signal rdata_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
+	signal rcount : naturel(1 to MAXPORT) ;
+	
+	signal cdata_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
+   signal clk : std_logic := '0';
+   signal reset : std_logic := '0';
+	signal din1,din2,din3,din4: std_logic_vector(MAXPORT downto 1):= (others => '0');
+ 	--signaux utiliser pour la mise à jour des MAE
+	signal sdestport,rdestport,rorigport:natural range 0 to 15;
+	signal csend1,csend2,csend3,csend4:natural;
+	signal sorigport :natural range 0 to 15:=1;
+	
+
+   signal fifo_in_full : std_logic_vector(MAXPORT downto 1);
+   signal fifo_in_empty : std_logic_vector(MAXPORT downto 1);
+   signal data_available : std_logic_vector(MAXPORT downto 1);
+
+   -- Clock period definitions
+   constant clk_period : time := 10 ns;
+   -- autres signaux de simulation
+	-- ici nous mettons les signaux permettant de gérer le processus de simulation
+	signal time_out:std_logic_vector(8 downto 1);
+	signal header : std_logic_vector(7 downto 0);
+	signal tosend1,tosend2,tosend3,tosend4 : std_logic_vector(7 downto 0);
+	
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: SWITCH_GEN generic map (MAXPORT) PORT MAP (
+          Port_In  => PortIn,
+			 Port_Out =>PortOut,
+
+          --signaux de contrôle de la lecture des ports
+			 data_in_en => data_in_en,
+			 cmd_in_en =>cmd_in_en,
+          data_out_en => data_out_en,
+          fifo_in_full => fifo_in_full,
+          fifo_in_empty => fifo_in_empty,
+          data_available => data_available,
+          clk => clk,
+          reset => reset
+        );
+--Utilisation de la ROM pour envoyer des stimulis
+--stimport: stimport5 port map (clk,reset,not (fifo_in_full(5)),din3(5),port5_in);
+data_in_en<=din1 or din2 or din3 or din4;
+data_out_en<=rdata_out_en or cdata_out_en;					
+ -- Clock process definitions
+   clk_process :process
+   begin
+		clk <= '0';
+		wait for clk_period/2;
+		clk <= '1';
+		wait for clk_period/2;
+   end process;
+
+ init_process:process (reset)
+ 
+ variable i: natural range 0 to 15;
+ begin
+ if reset='1' then
+ for i in 1 to maxport
+	loop
+	--Portin(i)<=(others=>'0');
+end loop	;
+end if ;
+end process init_process;
+		psend1:process(clk,reset)
+		--génération des paquets à partir du premier port
+		variable pactype :natural range 0 to 15;
+		variable origport,destport : natural range 0 to 15;
+		variable datalen,i,i_pair : natural range 0 to 255;
+		
+		
+		
+				begin
+				if reset='1' then 
+				 etsnd1<=s_head;
+				 
+				else  --reset ='0'
+						origport:=6;
+						if rising_edge(clk) then -- le process s'exécute sur chaque front 
+															-- montant de l'horloge
+						case etsnd1 is
+						when s_head  =>    -- construction et envoie de l'en-tête
+						pactype:=5;-- fonction put
+						destport:=6; -- le port de destination
+						datalen :=4;
+						header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4));
+						 tosend1<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
+						 din1(origport)<='1';   -- en fait data_in_en(origport)
+						 i:=1;i_pair:=i /2;
+						 etsnd1<=s_len;  -- passer à l'état suivant
+						 --port1_in<=tosend1;
+						when s_len => 
+							--tosend1<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
+							tosend1<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
+						
+							din1(origport)<='1';
+
+							--port1_in<=tosend1; --copie directe sur le port 
+							etsnd1<=s_len2;
+						when s_len2 => 
+							tosend1<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
+							din1(origport)<='1';
+
+							--port1_in<=tosend1; --copie directe sur le port 
+							etsnd1<=s_data;	
+						when s_data =>
+							
+							if (fifo_in_full(origport)='0') then
+								din1(origport)<='1';
+								i_pair:=i_pair *2;
+								if i=i_pair then        -- modulo
+									tosend1<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
+									--port1_in<="00001101";  --origport=1
+								else
+									--tosend1<="00001111";
+									tosend1<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
+									--port1_in<="00001111";   --origport=1
+								end if;
+								i:=i+1;i_pair:=i / 2;
+								if i>datalen then
+									etsnd1<=s_end;
+									din1(origport)<='0';
+								end if;
+							else
+								din1(origport)<='1';
+							end if;
+						when s_end  =>
+						tosend1<="--------";
+							din1(origport)<='0';
+							if fifo_in_empty(origport)='1' then
+								etsnd1<=s_head;
+							else
+								etsnd1<=s_end;
+							end if;
+						end case;	
+						
+						end if;
+					 
+					
+						
+					end if; --reset='1'
+		end process psend1;
+		
+		Portin(6)<=tosend1 when reset='0';
+		Portin(2)<=tosend2 when reset='0';
+		Portin(4)<=tosend3 when reset='0';
+		Portin(1)<=tosend4 when reset='0';
+		psend2:process(clk,reset)
+		--génération des paquets à partir du premier port
+		variable pactype :natural range 0 to 15;
+		variable origport,destport : natural range 0 to 15;
+		variable datalen,i,i_pair : natural range 0 to 255;
+		
+		
+		
+				begin
+				if reset='1' then 
+				 etsnd2<=s_head;
+				 
+				else  --reset ='0'
+						origport:=2;
+						if rising_edge(clk) then -- le process s'exécute sur chaque front 
+															-- montant de l'horloge
+						case etsnd2 is
+						when s_head  =>    -- construction et envoie de l'en-tête
+						pactype:=5;-- fonction put
+						destport:=2; -- le port de destination
+						datalen :=9;
+						header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4));
+						 tosend2<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
+						 din2(origport)<='1';
+						 i:=1;i_pair:=i /2;
+						 etsnd2<=s_len;  -- passer à l'état suivant
+						 
+						when s_len => 
+							--tosend2<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
+							tosend2<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
+						
+							din2(origport)<='1';
+
+							--port2_in<=tosend2; --copie directe sur le port 
+							etsnd2<=s_len2;
+						when s_len2 => 
+							tosend2<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
+							din2(origport)<='1';
+
+							--port1_in<=tosend1; --copie directe sur le port 
+							etsnd2<=s_data;
+						when s_data =>
+							
+							if (fifo_in_full(origport)='0') then
+								din2(origport)<='1';
+								i_pair:=i_pair * 2;
+								if i=i_pair then        -- modulo
+									--tosend2<="00000001";
+									tosend2<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
+									--port2_in<="00000001";  --origport=1
+								else
+									--tosend2<="00000010";
+									tosend2<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
+									--port2_in<="00000001";   --origport=1
+								end if;
+								i:=i+1;i_pair:=i / 2;
+								if i>datalen then
+									etsnd2<=s_end;
+									din2(origport)<='0';
+								else
+									din2(origport)<='1';
+								end if;
+							else
+								din2(origport)<='0';
+							end if;
+						when s_end  =>
+							tosend2<="--------";
+							din2(origport)<='0';
+							if fifo_in_empty(origport)='1' then
+								etsnd2<=s_head;
+							else
+								etsnd2<=s_end;
+							end if;
+						end case;	
+						
+						end if;
+					 
+					
+						
+					end if; --reset='1'
+		end process psend2;
+
+		psend3:process(clk,reset)
+		--génération des paquets à partir du premier port
+		variable pactype :natural range 0 to 15;
+		variable origport,destport : natural range 0 to 15;
+		variable datalen,i,i_pair : natural range 0 to 255;
+		
+		
+		
+				begin
+				if reset='1' then 
+				 etsnd3<=s_head;
+				 
+				else  --reset ='0'
+						origport:=4; --attention à régler  tosend3 =Portin(....) !!!!!!!
+						if rising_edge(clk) then -- le process s'exécute sur chaque front 
+															-- montant de l'horloge
+						case etsnd3 is
+						when s_head  =>    -- construction et envoie de l'en-tête
+						pactype:=5;-- fonction put
+						destport:=MAXPORT; -- le port de destination
+						datalen :=4;
+						--header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4));
+						 tosend3<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
+						 din3(origport)<='1';   -- en fait data_in_en(origport)
+						 i:=1;i_pair:=i /2;
+						 etsnd3<=s_len;  -- passer à l'état suivant
+						 --port1_in<=tosend1;
+						when s_len => 
+							--tosend3<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
+							din3(origport)<='1';
+							tosend3<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
+						
+							--port1_in<=tosend1; --copie directe sur le port 
+							etsnd3<=s_len2;
+						when s_len2 => 
+							tosend3<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
+							din3(origport)<='1';
+
+							--port1_in<=tosend1; --copie directe sur le port 
+							etsnd3<=s_data;	
+						when s_data =>
+							
+							if (fifo_in_full(origport)='0') then
+								din3(origport)<='1';
+								i_pair:=i_pair * 2;
+								if i=i_pair then        -- modulo
+									tosend3<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
+									--tosend3<="00001100";
+									--port1_in<="00001101";  --origport=1
+								else
+									tosend3<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
+									--tosend3<="00000110";
+									--port1_in<="00001111";   --origport=1
+								end if;
+								i:=i+1;i_pair:=i / 2;
+								if i>datalen then
+									din3(origport)<='0';
+									etsnd3<=s_end;
+								else
+									din3(origport)<='1';
+								end if;
+							else
+								din3(origport)<='0';
+							end if;
+						when s_end  =>
+						tosend3<="--------";
+							din3(origport)<='0';
+							if fifo_in_empty(origport)='1' then
+								etsnd3<=s_head;
+							else
+								etsnd3<=s_end;
+							end if;
+						end case;	
+						
+						end if;				
+						
+					end if; --reset='1'
+		end process psend3;		
+
+	preceiv:process(clk,reset)
+	
+	variable origport,ptype : natural range 0 to 15;
+	variable datalen,dcount ,timeout:natural range 0 to 255;
+	variable destport  : natural range 0 to 15:=1;
+	begin
+	
+	if reset='1' then
+		etrec<=r_wait;
+		destport:=1;
+		timeout:=0;
+	elsif rising_edge(clk) then
+			case  etrec is
+			when r_wait =>
+				if destport=0 then 
+					destport:=1;
+				end if;
+				timeout:=0;
+				time_out(destport)<='0';
+				if data_available(destport)='1' and cmd_in_en(destport)='0' then 
+				rdata_out_en(destport)<='1';
+				 etrec<=r_head;
+				else
+					if destport>=MAXPORT then 
+					destport:=1;
+					else 
+						destport:=destport+1;
+					end if;
+				etrec<=r_wait;
+				end if;
+			when r_head =>
+			
+				ptype:=to_integer(unsigned(portout(destport)(7 downto 4)));
+				origport:=to_integer(unsigned(portout(destport)(3 downto 0)));
+				rdata_out_en(destport)<='1';
+				if ptype=5 then 
+						etrec<=r_Dlen; --identification de la signature d'en tête valide
+					else
+						etrec<=r_wait;
+				end if;
+			
+
+			
+			
+			
+			when r_Dlen =>   --positionnement du mot de longueur des données
+			if data_available(destport)='1' then 
+			
+			rdata_out_en(destport)<='1';
+			etrec<=r_glen;
+			timeout:=0;
+			else
+				timeout:=timeout+1;
+					if timeout>=30 then 
+					time_out(destport)<='1';
+						etrec<=r_end;             -- données pas prêtes
+					end if;
+			
+			
+			end if;
+			when r_glen =>   --lecture effective de la longueur des données
+			if data_available(destport)='1' then 
+			datalen:=to_integer(unsigned(portout(destport)(7 downto 0)))-3;
+			rdata_out_en(destport)<='1';
+			etrec<=r_start;
+			dcount:=1;  -- initialisation du compteur de reception
+			else
+				timeout:=timeout+1;
+					if timeout>=30 then 
+					time_out(destport)<='1';
+						etrec<=r_end;             -- données pas prêtes
+					end if;
+			
+			end if;
+			
+			when r_start =>
+			if data_available(destport)='1'  then 
+				
+					dcount:=dcount+1;
+					assert true report "Donnée lue :"; --& string(unsigned(port4_out(7 downto 0)))
+					rdata_out_en(destport)<='1';
+					
+					--severity note;
+					if datalen<=dcount then 
+						etrec<=r_end;
+						
+					elsif dcount=255 then   --dépassement de la capacité
+						etrec<=r_end;
+					end if;
+			else
+					timeout:=timeout+1;
+					if timeout>=30 then 
+					   time_out(destport)<='1';
+						etrec<=r_end;             -- données pas prêtes
+					end if;
+				
+					
+			end if;
+			when r_end =>
+			
+			
+			rdata_out_en(destport)<='0';
+			rcount(destport)<=rcount(destport)+1;
+			etrec<=r_wait;
+			if destport>=MAXPORT then -- provoquer le passage au prochain port de réception
+					destport:=1;
+					else 
+						destport:=destport+1;
+					end if;
+			end case;
+		end if;   --reset='1'
+  end process preceiv;	
+	
+	pcmd:process(clk,reset)
+	
+	variable origport,destport,pid,mport : natural range 0 to 15;
+	variable datalen,dcount ,timeout:natural range 0 to 255;
+	begin
+	
+	if reset='1' then
+		etcmd<=cmdstart;
+		destport:=0;
+		timeout:=0;
+		origport:=1;
+		sorigport<=origport;
+	elsif rising_edge(clk) then
+			case  etcmd is
+			when cmdstart =>
+				if fifo_in_empty(origport)='1' then 
+					
+				
+				
+				
+				etcmd<=cmdpost;
+				end if;
+		 when cmdpost =>
+			if fifo_in_empty(origport)='1' then 
+			---assignations de l'état
+				--din4(origport)<='1';
+				--tosend4<="00000001"; ---code pour getportid
+				etcmd<=cmdpostidle;
+			end if;
+		when cmdpostidle  =>   --permet juste la prise en compte de la commande
+				if data_available(origport)='1' then 
+						etcmd<=cmdread;
+				end if;
+		 when cmdread =>
+				
+				
+				timeout:=0;
+				--time_out(destport)<='0';
+			if data_available(origport)='1' then 
+				mport:=to_integer(unsigned(portout(origport)(7 downto 4)));
+				pid:=to_integer(unsigned(portout(origport)(3 downto 0)))+1;
+				--cdata_out_en(origport)<='1';
+				if pid=origport then --le port a été bien identifié
+						etcmd<=cmdglen; --
+					else
+					etcmd<=cmdtimeout;
+				end if;
+			else
+--				if destport>=MAXPORT then 
+--					destport:=1;
+--					else 
+--						destport:=destport+1;
+--					end if;
+				etcmd<=cmdread;
+			end if;
+			
+			
+			when cmdlen =>   --positionnement du mot de longueur des données
+			if data_available(origport)='1' then 
+			
+			--cdata_out_en(origport)<='1';
+			etcmd<=cmdglen;
+			timeout:=0;
+			else
+				timeout:=timeout+1;
+					if timeout>=30 then 
+					--time_out(destport)<='1';
+						etcmd<=cmdtimeout;             -- données pas prêtes
+					end if;
+			
+			
+			end if;
+			when cmdglen =>   --lecture effective de la longueur des données
+			if data_available(origport)='1' then 
+			datalen:=to_integer(unsigned(portout(origport)(7 downto 0)))-3;
+			
+			etcmd<=cmddata;
+			dcount:=0;  -- initialisation du compteur de reception
+			else
+				timeout:=timeout+1;
+					if timeout>=30 then 
+					--time_out(destport)<='1';
+						etcmd<=cmdtimeout;             -- données pas prêtes
+					end if;
+			
+			end if;
+			
+			when cmddata =>
+			if data_available(origport)='1' and timeout<30 then 
+					
+					--cdata_out_en(origport)<='1';
+					mport:=to_integer(unsigned(portout(origport)(7 downto 4)));
+					--attention les ports sont numérotés à partir de 0
+					pid:=to_integer(unsigned(portout(origport)(3 downto 0)))+1;
+					
+					--severity note;
+					if Pid=origport then 
+						etcmd<=cmdend;
+						
+					else   --dépassement de la capacité
+						
+						timeout:=timeout+1;
+						if timeout>=30 then 
+							etcmd<=cmdtimeout;
+						end if;
+						
+					end if;
+			else
+					
+					if timeout>=30 then 
+					   time_out(origport)<='1';
+						etcmd<=cmdtimeout;             -- données pas prêtes
+					end if;
+				   timeout:=timeout+1;
+					
+			end if;
+			when cmdend =>
+			
+			
+			--cdata_out_en(origport)<='0';
+			
+--					if origport>=mport then -- provoquer le passage au prochain port de réception
+--						origport:=1;
+--					else 
+--						origport:=origport+1;
+--					end if;
+					etcmd<=cmdstart;
+					--cmd_in_en(origport)<='0';
+			when cmdtimeout =>
+			  etcmd<=cmdtimeout;
+			  --cmd_in_en(origport)<='0';
+			  etcmd<=cmdstart;
+			end case;
+		sorigport<=origport;	
+		end if;   --reset='1'
+		
+  end process pcmd;	
+
+majetcmd:process (etcmd)
+variable origport : natural:=1;-- =sorigport ;
+	begin
+			case  etcmd is
+			when cmdstart =>
+			
+				cmd_in_en(origport)<='1';
+
+		 when cmdpost  =>
+				din4(origport)<='1';
+				tosend4<="00000001"; ---code pour getportid
+				cmd_in_en(origport)<='1';
+				cdata_out_en(origport)<='0';
+		 when cmdpostidle =>
+				din4(origport)<='0';
+				cdata_out_en(origport)<=data_available(origport);
+				cmd_in_en(origport)<='1';
+	
+		 when cmdread =>
+				din4(origport)<='0';
+				cdata_out_en(origport)<=data_available(origport);
+				cmd_in_en(origport)<='1';
+	
+			when cmdlen |cmdglen =>   --positionnement du mot de longueur des données
+	
+					din4(origport)<='0';
+					cdata_out_en(origport)<=data_available(origport);
+					cmd_in_en(origport)<='1';
+
+			when cmddata =>
+			
+					din4(origport)<='0';
+					cdata_out_en(origport)<=data_available(origport);
+					cmd_in_en(origport)<='1';
+						
+			
+			when cmdend =>
+			
+				din4(origport)<='0';
+				cdata_out_en(origport)<='0';
+				cmd_in_en(origport)<='0';
+			
+			when cmdtimeout =>
+				  din4(origport)<='0';
+				  cdata_out_en(origport)<='0';
+				  cmd_in_en(origport)<='0';
+			 
+			end case;
+		
+end process majetcmd ; 
+   -- Stimulus process
+   stim_proc: process 
+   begin		
+      -- hold reset state for 100 ns.
+      reset<='1';
+		wait for 1 ns;	
+		reset<='1';
+      wait for clk_period*10;
+		reset<='0';
+		wait;
+      -- insert stimulus here 
+	
+      
+		
+		
+	end process;
+
+END;
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_8x8.wcfg
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_8x8.wcfg	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_8x8.wcfg	(revision 20)
@@ -0,0 +1,132 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="C:/Core MPI/SWITCH_GENERIC_16_16/test_xbar_16x16_isim_beh.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="coretypes" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="test_xbar_16x16" />
+            <top_module name="textio" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="14" />
+   <wave_markers>
+      <marker time="890107000" label="" />
+      <marker time="885107000" label="" />
+      <marker time="110000000" label="" />
+      <marker time="105000000" label="" />
+      <marker time="100000000" label="" />
+      <marker time="95000000" label="" />
+      <marker time="1137027000" label="" />
+      <marker time="97800000" label="" />
+   </wave_markers>
+   <wvobject fp_name="/test_xbar_16x16/etsnd1" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">etsnd1</obj_property>
+      <obj_property name="ObjectShortName">etsnd1</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/etsnd2" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">etsnd2</obj_property>
+      <obj_property name="ObjectShortName">etsnd2</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/etsnd3" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">etsnd3</obj_property>
+      <obj_property name="ObjectShortName">etsnd3</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/data_in_en" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_in_en[8:1]</obj_property>
+      <obj_property name="ObjectShortName">data_in_en[8:1]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/fifo_in_empty" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">fifo_in_empty[8:1]</obj_property>
+      <obj_property name="ObjectShortName">fifo_in_empty[8:1]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/portin" type="array" db_ref_id="1">
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="ElementShortName">portin[1:8]</obj_property>
+      <obj_property name="ObjectShortName">portin[1:8]</obj_property>
+      <obj_property name="label">portin[1:8]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/rcount" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rcount[1:8]</obj_property>
+      <obj_property name="ObjectShortName">rcount[1:8]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/reset" type="logic" db_ref_id="1">
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+      <obj_property name="label">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/etcmd" type="other" db_ref_id="1">
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="ElementShortName">etcmd</obj_property>
+      <obj_property name="ObjectShortName">etcmd</obj_property>
+      <obj_property name="label">etcmd</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/data_available" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_available[8:1]</obj_property>
+      <obj_property name="ObjectShortName">data_available[8:1]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/etrec" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">etrec</obj_property>
+      <obj_property name="ObjectShortName">etrec</obj_property>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/portout" type="array" db_ref_id="1">
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="ElementShortName">portout[1:8]</obj_property>
+      <obj_property name="ObjectShortName">portout[1:8]</obj_property>
+      <obj_property name="label">portout[1:4]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/test_xbar_16x16/portout[1]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[1]</obj_property>
+         <obj_property name="ObjectShortName">portout[1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/test_xbar_16x16/portout[2]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[2]</obj_property>
+         <obj_property name="ObjectShortName">portout[2]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/test_xbar_16x16/portout[3]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[3]</obj_property>
+         <obj_property name="ObjectShortName">portout[3]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/test_xbar_16x16/portout[4]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[4]</obj_property>
+         <obj_property name="ObjectShortName">portout[4]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/test_xbar_16x16/portout[5]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[5]</obj_property>
+         <obj_property name="ObjectShortName">portout[5]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/test_xbar_16x16/portout[6]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[6]</obj_property>
+         <obj_property name="ObjectShortName">portout[6]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/test_xbar_16x16/portout[7]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[7]</obj_property>
+         <obj_property name="ObjectShortName">portout[7]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/test_xbar_16x16/portout[8]" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">[8]</obj_property>
+         <obj_property name="ObjectShortName">portout[8]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="/test_xbar_16x16/data_out_en" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_out_en[8:1]</obj_property>
+      <obj_property name="ObjectShortName">data_out_en[8:1]</obj_property>
+   </wvobject>
+</wave_config>
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_8x8_beh.prj
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_8x8_beh.prj	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_8x8_beh.prj	(revision 20)
@@ -0,0 +1,26 @@
+vhdl work "CoreTypes.vhd"
+vhdl work "RAM_256.vhd"
+vhdl work "Arbiter.vhd"
+vhdl work "SCHEDULER9_9.VHD"
+vhdl work "SCHEDULER8_8.VHD"
+vhdl work "SCHEDULER7_7.VHD"
+vhdl work "SCHEDULER6_6.VHD"
+vhdl work "SCHEDULER5_5.VHD"
+vhdl work "SCHEDULER4_4.VHD"
+vhdl work "SCHEDULER3_3.VHD"
+vhdl work "SCHEDULER2_2.VHD"
+vhdl work "SCHEDULER16_16.VHD"
+vhdl work "SCHEDULER15_15.VHD"
+vhdl work "SCHEDULER14_14.VHD"
+vhdl work "SCHEDULER13_13.VHD"
+vhdl work "SCHEDULER12_12.VHD"
+vhdl work "SCHEDULER11_11.VHD"
+vhdl work "SCHEDULER10_10.VHD"
+vhdl work "FIFO_256_FWFT.vhd"
+vhdl work "Crossbit.vhd"
+vhdl work "Scheduler.vhd"
+vhdl work "OUTPUT_PORT_MODULE.vhd"
+vhdl work "INPUT_PORT_MODULE.vhd"
+vhdl work "Crossbar.vhd"
+vhdl work "SWITCH_GEN.vhd"
+vhdl work "test_xbar_8x8.vhd"
Index: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/testbench_summary.html
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/testbench_summary.html	(revision 20)
+++ PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/testbench_summary.html	(revision 20)
@@ -0,0 +1,78 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>testbench Project Status</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>GENERIC_16_16.xise</TD>
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>testbench</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>New</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc3s1200e-4ft256</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
+<TD>&nbsp;</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 11/29/2012 - 18:08:12</center>
+</BODY></HTML>
