Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Backup_prj.bat =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Backup_prj.bat (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Backup_prj.bat (revision 29) @@ -0,0 +1,34 @@ +@Echo off +rem Fichier permettant de copier l'ensemble des +rem sources du projet vers une autre destination +rem +Echo donner le chemin de destination des fichiers à copier svp (defaut=D:\Core_MPI) +set Dest= +set /P Dest="Defaut D:\SCORE_MPI" + +if "%Dest%" == "" goto defaut +if "%Dest%" == " " goto defaut + goto normal +:defaut +set dest=D:\SCORE_MPI +:normal +echo la destination est +echo "%Dest%" + +If exist %Dest% goto lancecopie +Echo Attention la destination n'existe pas +Echo nous tentons de la créer +MD %Dest% +If exist %Dest%\nul goto lancecopie +Echo Création impossible du dossier. +Echo le dossier parent n'existe pas ou le chemin est invalide +Echo vous devez le faire vous-même ou donner un chemin valide. +goto fin +:lancecopie +copy *.vhd %Dest%\ +copy *.wcfg %Dest%\ +copy *.prj %Dest%\ +copy *.ucf %Dest%\ +:fin +pause +Echo fin de la copie Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/CORE_MPI.udo =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/CORE_MPI.udo (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/CORE_MPI.udo (revision 29) @@ -0,0 +1,10 @@ +###################################################################### +## +## Filename: CORE_MPI.udo +## Created on: Sat Jul 02 09:11:34 Paris, Madrid (heure d'été) 2011 +## +## Auto generated by Project Navigator for Post-Behavioral Simulation +## +## You may want to edit this file to control your simulation. +## +###################################################################### Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/CORE_MPI.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/CORE_MPI.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/CORE_MPI.vhd (revision 29) @@ -0,0 +1,720 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM NGOUNOU +-- +-- Create Date: 05:52:25 06/21/2011 +-- Design Name: +-- Module Name: CORE_MPI - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +Library NocLib; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity CORE_MPI is + Port ( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + clkout : out std_logic; + instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + instruction_en : in STD_LOGIC; --valide l'instruction + instruction_fifo_full : out STD_LOGIC; + ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + barrier_completed : out STD_LOGIC; + packet_received : out STD_LOGIC; + packet_ack : in std_logic; + PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); --le resultat de l'exécution + ram_we : out STD_LOGIC; + ram_en : out STD_LOGIC; + ram_address_rd : out STD_LOGIC_VECTOR (15 downto 0); + ram_address_wr : out STD_LOGIC_VECTOR (15 downto 0); + ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + switch_port_in_cmd_en : out std_logic; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_in_wr_en : out STD_LOGIC; + switch_port_in_full : in STD_LOGIC; + switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_out_rd_en : out STD_LOGIC; + switch_port_in_empty : in STD_LOGIC; + switch_port_out_data_vailaible : in STD_LOGIC + + + ); + +end CORE_MPI; + +architecture Structural of CORE_MPI is +--déclaration des types +type Type_Noc is +record + port_in_cmd_en : std_logic; + port_out_data : STD_LOGIC_VECTOR (Word-1 downto 0); + port_in_wr_en : STD_LOGIC; + port_in_empty : STD_LOGIC; + port_in_full : STD_LOGIC; + port_in_data : STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_rd_en : STD_LOGIC; + port_out_data_available : STD_LOGIC; +end record; +-- déclaration des composants MPI + +COMPONENT FIFO_64_FWFT + PORT( + clk : IN std_logic; + din : IN std_logic_vector(Word-1 downto 0); + rd_en : IN std_logic; + srst : IN std_logic; + wr_en : IN std_logic; + dout : OUT std_logic_vector(Word-1 downto 0); + empty : OUT std_logic; + full : OUT std_logic + ); +END COMPONENT; +COMPONENT load_instr + Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + instruction_ack : out STD_LOGIC; + fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_wr :out std_logic; + fifo_full : in STD_LOGIC; + copying : out std_logic; + Ram_rd_en : out STD_LOGIC; + ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0)); +end component; +COMPONENT DMA_ARBITER + PORT( + + clk : IN std_logic; + reset : IN std_logic; + dma_rd_request : IN std_logic_vector(3 downto 0); + data_wr_in : IN std_logic_vector(Word-1 downto 0); + data_rd_out : out std_logic_vector(Word-1 downto 0); + address_rd : IN std_logic_vector(15 downto 0); + address_wr : IN std_logic_vector(15 downto 0); + + dma_wr_request : IN std_logic_vector(3 downto 0); + address_out_rd : OUT std_logic_vector(15 downto 0); + address_out_wr : OUT std_logic_vector(15 downto 0); + ram_en : OUT std_logic; + ram_we : OUT std_logic; + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + data_wr_mem : OUT std_logic_vector(Word-1 downto 0); + data_rd_mem : IN std_logic_vector(Word-1 downto 0); + dma_wr_grant : OUT std_logic_vector(3 downto 0); + dma_rd_grant : OUT std_logic_vector(3 downto 0) + ); +END COMPONENT; + +COMPONENT EX1_FSM + PORT( + clk : IN std_logic; + reset : IN std_logic; + + pid : in std_logic_vector (3 downto 0); --port id + nprocs : in std_logic_vector (3 downto 0); -- la taille du Noc + instruction_en : in std_logic; + fifo_empty : IN std_logic; + fifo_data_out : IN std_logic_vector(Word-1 downto 0); + fifo_rd_en : OUT std_logic; + ram_data_in : IN std_logic_vector(Word-1 downto 0); + ram_data_out : out std_logic_vector(Word-1 downto 0); + dma_rd_grant : IN std_logic; + dma_wr_grant : IN std_logic; + dma_wr_request : OUT std_logic; + dma_rd_request : OUT std_logic; + ram_address : OUT std_logic_vector(15 downto 0); + ram_rd,ram_wr : out std_logic; + + priority_rotation : OUT std_logic; + + switch_port_in_data : OUT std_logic_vector(Word-1 downto 0); + switch_port_in_wr_en : OUT std_logic; + switch_port_in_full : IN std_logic; + Result :out std_logic_vector(Word-1 downto 0); + AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic -- état de la Lib + ); + END COMPONENT; + +COMPONENT EX2_FSM + PORT( + clk : IN std_logic; + reset : IN std_logic; + + instruction_en: in std_logic; + Initialized : in std_logic; + + switch_port_out_rd_en : OUT std_logic ; + switch_data_available : IN std_logic; + switch_port_out_data : IN std_logic_vector(Word-1 downto 0); + AppRank : in STD_LOGIC_VECTOR; + AppSize : in STD_LOGIC_VECTOR; + dma_wr_grant : IN std_logic; + dma_wr_request : OUT std_logic; + dma_rd_grant : IN std_logic; + dma_rd_request : OUT std_logic; + ram_address : OUT std_logic_vector(15 downto 0); + ram_rd,ram_wr : out std_logic; + Ram_data_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_full : IN std_logic; + fifo_data : OUT std_logic_vector(Word-1 downto 0); + fifo_wr_en : OUT std_logic; + --fifo_out : out std_logic_vector; + + packet_received : OUT std_logic; + packet_ack : IN std_logic; + barrier_completed : OUT std_logic; + Ready : Out std_logic; + AppInitAck : in std_logic; + AppInitReq : out std_logic + ); + END COMPONENT; + + + COMPONENT EX3_FSM + PORT( + instruction : IN std_logic_vector(Word-1 downto 0); + clk : IN std_logic; + reset : IN std_logic; + Ismain :in std_logic; + ResOut : OUT std_logic_vector(Word-1 downto 0) + + ); + END COMPONENT; + + COMPONENT EX4_FSM + PORT( + Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); --permet de lire le FIFO + Instruction_En : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + ResultOut : out STD_LOGIC_VECTOR (Word-1 downto 0); + Result_En : out STD_LOGIC; + NocSize : out STD_LOGIC_VECTOR; + AppRank : out STD_LOGIC_VECTOR; + AppSize : out STD_LOGIC_VECTOR; + IsMain : out STD_LOGIC; + Initialized : out STD_LOGIC; + dma_wr_req : out std_logic; + dma_wr_grant : in std_logic; + AdrRam : out STD_LOGIC_VECTOR (15 downto 0); --accès au stockage + WeRam : out STD_LOGIC; --activation de l'écriture en RAM + DataRam : out STD_LOGIC_VECTOR (Word-1 downto 0);--données des ports + AppAck : in STD_LOGIC; + AppReq : in STD_LOGIC; + PortId : out STD_LOGIC_VECTOR(3 downto 0); + port_in_cmd_en : out STD_LOGIC; + port_in_wr_en : out STD_LOGIC; + port_in_empty : in STD_LOGIC; + port_in_full : in STD_LOGIC; + port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_rd_en : out STD_LOGIC; + port_out_data_available : in STD_LOGIC); + END COMPONENT; + + COMPONENT EX0_FSM + PORT( + clk : in STD_LOGIC; + reset : in STD_LOGIC; + + Initialized : in STD_LOGIC; + Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + instruction_en: in STD_LOGIC; + + ClkRate : in STD_LOGIC_VECTOR ; + uTimeResult : out STD_LOGIC_VECTOR; + TickResult : out STD_LOGIC_VECTOR + ); + END COMPONENT; + + +COMPONENT MPI_CORE_SCHEDULER + PORT( + clk : IN std_logic; + reset : IN std_logic; + priority_rotation : IN std_logic; + instruction_fifo_empty : IN std_logic; + instruction_fifo_rd_en : OUT std_logic; + instruction_fifo_data : IN std_logic_vector(Word-1 downto 0); + instruction_available : OUT std_logic; + + get_request_fifo_empty : IN std_logic; + get_request_fifo_rd_en : OUT std_logic; + get_request_fifo_data : IN std_logic_vector(Word-1 downto 0); + + fifo_rd_en : IN std_logic; + fifo_empty : OUT std_logic; + fifo_selected : OUT std_logic; + + data_out : OUT std_logic_vector(Word-1 downto 0) + + + ); + END COMPONENT; + +-- declaration des signaux d'interconnexion entre les modules du coresignal fifo_sel: std_logic; -- indique l'un des deux fifos d'instructions qui sont prêts +signal fifo_instr : std_logic; -- une instruction est prête dans les fifos d'instruction + + +signal scheduler_fifo_empty : std_logic; +signal scheduler_data_out : std_logic_vector(Word-1 downto 0); +signal dma_arbiter_data_rd_out : std_logic_vector(Word-1 downto 0); + +signal scheduler_priority_rotation : std_logic; +signal scheduler_rd_en : std_logic; + +signal dma_data_rd,dma_data_wr : std_logic_vector(Word-1 downto 0); -- bus à 3 états +signal dma_rd_address,dma_rd_address1,dma_rd_address2 : std_logic_vector(15 downto 0); -- ces bus doivent être gérés en logique 3 états! +signal dma_rd_address3 : std_logic_vector(15 downto 0); +signal dma_wr_address1,dma_wr_address3 : std_logic_vector(15 downto 0); +signal dma_wr_address2,dma_wr_address4 : std_logic_vector(15 downto 0); +signal dma_wr_address : std_logic_vector(15 downto 0); +signal switch_port_in_data_signal : std_logic_vector(Word-1 downto 0); +signal ram_data_out_signal : std_logic_vector(Word-1 downto 0); +signal weram,rdram,ram_wev,ram_env :std_logic:='0'; + +signal instruction_fifo2_signal : std_logic_vector(Word-1 downto 0); +signal Ex_EN : std_logic_vector(4 downto 1):=(others=>'0'); --active les sous MAE permettant de décoder les instructions MPI +signal Ex1_RDY,Ex2_RDY,EX3_RDY,EX4_RDY : std_logic; -- indique la fin de l'exécution de la MAE +signal ex1_ram_rd,ex2_ram_rd,ex4_ram_rd ,Exi_ram_rd: std_logic ; -- validation lecture des données en RAM +signal ex1_ram_wr,ex2_ram_wr,ex4_ram_wr,Exi_ram_wr : std_logic ; -- validation écriture des données en RAM +signal Exi_busy : std_logic; +signal Ex1_Result,Ex4_result : std_logic_vector(Word-1 downto 0); + +--================interface DMA avec les modules ====================================== +signal dma_data_in,Dma_data_in1,dma_data_in2,dma_data_in4 : std_logic_vector(Word-1 downto 0); +signal dma_data_out : std_logic_vector(Word-1 downto 0); +signal dma_rd_request :std_logic_vector(4 downto 1):=(others=>'0'); +signal dma_wr_request :std_logic_vector(4 downto 1):=(others=>'0'); +signal dma_wr_grant,dma_rd_grant:std_logic_vector(4 downto 1); +-- +--====================================================================================== +--connexion au switch + +signal Noc1,NOC2,NOC3 : Type_Noc; -- regroupement des signaux qui vont au Noc + +--================================================================ +--déclaration des signaux d'état du Core +signal IsMain,SizeSet,RankSet,Initialized,AppReq,AppAck:std_logic; +signal InitReq,InitReq1,InitReq2 :std_logic; -- demande d'initialisation +signal InitAck,IAck,Ilatch : std_logic; +signal MPISize,MyRank : std_logic_vector(3 downto 0); +signal LibState: std_logic_vector(Word-1 downto 0); --ready,receiving,sending,spawning,rwaiting,swaiting,... +signal NocSize :std_logic_vector(3 downto 0); +Signal PortId : std_logic_vector(3 downto 0); +Signal uClkRate : std_logic_vector(Word-1 downto 0):="00011010"; --50 Mhz +signal uTimeCount :std_logic_vector(31 downto 0); +signal TickCount : std_logic_vector(31 downto 0); +signal RankSize: std_logic_vector(Word-1 downto 0); +--======================================================== +--déclaration des signaux permettant d'activer le module +signal AdrSelect : std_logic_vector(ADRLEN-1 downto 0); +--======================================================== +--signal PushOut_d,RankSize,TickUsOut:std_logic_vector; --résultat de l'execution des commandes mpi +--======================================================== +--connexion avec les FIFO instructions +signal fifo1_wr : std_logic; +signal fifo1_din : std_logic_vector (Word-1 downto 0); +signal fifo_sel : std_logic; --permet d'arbitrer la priorité de lecture entre les deux fifos +signal instruction_fifo1_rd_en : std_logic; +signal fifo1_full : std_logic; +signal instruction_fifo1_empty : std_logic; +signal instruction_fifo1_data_out : std_logic_vector(Word-1 downto 0); +signal instruction_fifo2_rd_en : std_logic; +signal instruction_fifo2_data_out : std_logic_vector(Word-1 downto 0); +signal instruction_fifo2_data_in : std_logic_vector(Word-1 downto 0); +signal instruction_fifo2_wr_en : std_logic; +signal instruction_fifo2_empty : std_logic; +signal instruction_fifo2_full : std_logic; + +--=========================================================== + +begin +--switch_port_in_data_signal <= ; +--switch_port_out_data_signal <= ; +-- istanciation des composants du core MPI +Instruction_Fifo1: FIFO_64_FWFT PORT MAP( + clk =>clk, + din =>fifo1_din, + rd_en => instruction_fifo1_rd_en, + srst => reset, + wr_en => fifo1_wr, + dout =>instruction_fifo1_data_out, + empty => instruction_fifo1_empty, + full => fifo1_full + ); + +Instruction_Fifo2: FIFO_64_FWFT PORT MAP( + clk =>clk, + din => instruction_fifo2_data_in , + rd_en =>instruction_fifo2_rd_en, + srst =>reset, + wr_en =>instruction_fifo2_wr_en, + dout =>instruction_fifo2_data_out, + empty =>instruction_fifo2_empty, + full => instruction_fifo2_full + ); +LD_instr:load_instr PORT MAP ( + + Instruction =>Instruction, + Instruction_en =>Instruction_en, + clk =>clk, + reset =>reset, + dma_rd_grant =>dma_rd_grant(3), + dma_rd_request =>dma_rd_request(3), + copying=> Exi_busy, + instruction_ack =>iack, --indique la fin de la copie d'une instruction dans le FIFO + fifo_din => fifo1_din, + fifo_wr => fifo1_wr, + fifo_full =>fifo1_full, + Ram_rd_en=> Exi_ram_rd, + ram_address_rd => dma_rd_address3, + ram_data =>dma_data_out --sortie DMA +); + +pushout(0)<=ILatch; +pushout(1)<=IsMain; +pushout(2)<=SizeSet; +pushout(3)<=RankSet; +pushout(4)<=Initialized; +pushout(5)<=Ex1_result(1); -- + + +MPI_CORE_EX0_FSM: EX0_FSM PORT MAP( + instruction => instruction_fifo1_data_out, + instruction_en=> '1', + uTimeResult => uTimeCount, + TickResult => TickCount, + Initialized => Initialized, -- indique si la l'appel à init a été concluant + ClkRate => uClkRate, + clk =>clk , + reset => reset + ); +MPI_CORE_EX1_FSM: EX1_FSM PORT MAP( + clk =>clk , + reset =>reset, + pid => MyRank, --port Id + nprocs=>MPISize, -- à revoir dans certains cas ou tous les PEs ne sont pas connectés + fifo_empty => scheduler_fifo_empty , + fifo_data_out =>scheduler_data_out, + fifo_rd_en =>scheduler_rd_en, + priority_rotation => scheduler_priority_rotation, + + instruction_en=>Ex_en(1), --active le module + + switch_port_in_full =>Noc1.port_in_full, --ces signaux doivent être contrôlés en 3 state logic + switch_port_in_data =>Noc1.port_in_data, + switch_port_in_wr_en =>Noc1.Port_in_wr_en , + + Ram_rd => ex1_ram_rd, + Ram_wr =>ex1_ram_wr, + ram_data_in =>dma_data_out, + Ram_data_out =>dma_data_in1, + ram_address=>dma_wr_address1, + --ram_address =>dma_rd_address2, --la même adresse sert pour la lecture ou l'écriture + dma_rd_request =>dma_rd_request(1), + dma_wr_request =>dma_wr_request(1), + dma_rd_grant =>dma_rd_grant(1) , + dma_wr_grant =>dma_wr_grant(1) , + + AppInitReq => InitReq1, -- requête d'initialisation de l'application + AppInitAck =>Ex4_rdy , -- Acquitement d'initialisation + Initialized=>Initialized, -- état de la Lib + Result => Ex1_Result -- le résultat de l'exécution + ); +instruction_fifo_full<=fifo1_full; +dma_rd_address1<=dma_wr_address1; --la même adresse sert pour la lecture ou l'écriture en RAM + +-- détermination de l'activation des module +--scheduler_priority_rotation<=not(Ex1_rdy); +Instr_Rdy:process(Iack,fifo_instr,fifo_sel)--A qoui sert encore ce processus (26/10/12) ???? +begin + case fifo_sel is + when '0' => + + if rising_edge(Iack) then + Ex_en(1)<= fifo_instr; + + end if; + --Ex_en(2)<='0'; + + when '1' => + Ex_en(1)<=fifo_instr; + --Ex_en(2)<= fifo_instr; + when others => + Ex_en(1)<='0'; + --Ex_en(2)<= '0'; + + end case; +end process; + +Active_proc:Process(Ex1_Result) --active la réception lorsqu' Put ou un Get ou un Init a été effectué +begin + if Ex1_result(0)='1' or Ex1_result(1)='1' or Ex1_result(2)='1' then + Ex_en(2)<='1'; + else + --Ex_en(2)<='0'; + end if; + +end process; + +Latch_instr:process (clk,Iack,Exi_busy) +begin + if rising_edge(clk) then + + Ilatch<=IAck; + + end if; + +end process; +--Ex_en(2)<=Initialized; --- Me pose des soucis en ce moment ??? +Ex_en(3)<='0'; +Ex_en(4)<= '1' when InitReq='1' else '0'; +Appreq<=Ex_en(4); --signal d'activation de la MAE Init +InitReq<=(not(Initialized) and InitReq1) or InitReq2; -- deux cas permettent d'activer l'initialisation +AppAck<=Ex1_result(0); -- signal init completed +-- soit une requête du PE soit une requête du Core + + +MPI_CORE_EX2_FSM: EX2_FSM PORT MAP( + + clk =>clk, + reset =>reset, + instruction_en=>Ex_en(2), + Ready =>Ex2_rdy, --signale que le module est disponible + fifo_full =>instruction_fifo2_full, + + fifo_wr_en => instruction_fifo2_wr_en, + fifo_data => instruction_fifo2_data_in, + + switch_port_out_rd_en => Noc2.port_out_rd_en, + switch_data_available =>Noc2.port_out_data_available, + switch_port_out_data =>Noc2.port_out_data , + -- il manque un signal pour valider l'accès à la RAM + dma_wr_request =>dma_wr_request(2), + dma_wr_grant =>dma_wr_grant(2), + dma_rd_request =>dma_rd_request(2), + dma_rd_grant =>dma_rd_grant(2), + ram_address =>dma_wr_address2, + Ram_rd => ex2_ram_rd, + Ram_wr =>ex2_ram_wr, + Ram_data_out=> Dma_data_in2, + Ram_data_in => Dma_data_out, + packet_received =>packet_received, + packet_ack => packet_ack, + barrier_completed =>barrier_completed, + AppRank =>MyRank, + AppSize =>MPISize, + AppInitReq => InitReq2, -- requête d'initialisation de l'application + AppInitAck =>Ex4_rdy , -- Acquitement d'initialisation + Initialized=>Initialized + + ); +Dma_rd_address2<=Dma_wr_address2; +ICI_MPI_CORE_EX3_FSM: EX3_FSM PORT MAP( + instruction => instruction, + ResOut => RankSize, + clk =>clk , + IsMain=>IsMain, + reset => reset + ); +MPI_CORE_EX4_FSM :EX4_FSM PORT MAP ( + Instruction => Instruction, --STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_En =>Ex_en(4), -- ='1' lorsque ce module est sollicité + clk =>clk, + reset =>reset, + ResultOut =>Ex4_Result, --STD_LOGIC_VECTOR (Word-1 downto 0); + Result_En =>Ex4_Rdy, -- ='1' lorsque fin de l'exécution du module + NocSize =>NocSize, + AppRank =>MyRank, + AppSize =>MPISize, + IsMain =>IsMain, + Initialized =>Initialized, + AdrRam =>dma_wr_Address4, --accès au stockage + WeRam =>Ex4_Ram_wr, --activation de l'écriture en RAM + DataRam =>Dma_data_in4, --données à écrire en RAM + DMA_wr_Req => dma_wr_request(4), + DMA_wr_grant => dma_wr_grant(4), + AppAck =>AppAck, + AppReq =>AppReq, + PortId=>PortId, + port_in_cmd_en => Noc3.port_in_cmd_en, + port_in_wr_en =>Noc3.port_in_wr_en, + port_in_empty =>Noc3.port_in_empty, + port_in_full =>Noc3.port_in_full, + port_in_data =>Noc3.port_in_data, + port_out_data =>Noc3.port_out_data, + port_out_rd_en =>Noc3.port_out_rd_en, + port_out_data_available =>Noc3.port_out_data_available + + +); +--=============Mux des signaux d'accès à la RAM========= +ram_we<='1' when (weram='1' and ram_wev ='1') else '0'; -- le contrôleur DMA contrôle directement +Ram_en<= '1' when (rdram ='1' or weram='1') else '0'; -- les signaux qui vont vers la RAM + + --dma_data_in <=dma_data_in1 or dma_data_in2; + --dma_data_out <=dma_data_out1 or dma_data_out2; + mux_ad_ram_rd:process (dma_rd_grant,dma_rd_address1,dma_rd_address2,dma_rd_address3, + ex1_ram_rd, Ex2_ram_rd, Exi_ram_rd ) +begin + case dma_rd_grant is + when "0001" => dma_rd_address <= dma_rd_address1; + rdram<= ex1_ram_rd; + when "0010" => dma_rd_address <= dma_rd_address2; + rdram<= ex2_ram_rd; + when "0100" => dma_rd_address <= dma_rd_address3; + rdram<= exi_ram_rd; +-- when "1000" => dma_rd_address <= ; + when others => dma_rd_address <= (others =>'Z'); + rdram<='0'; + end case; +end process; + mux_ad_ram_wr:process (dma_wr_grant,dma_wr_address1,dma_wr_address2,dma_wr_address4,Dma_data_in1,Dma_data_in2,Dma_data_in4,ex2_ram_wr,ex4_ram_wr) +begin + case dma_wr_grant is + + when "0001" => dma_wr_address <= dma_wr_address1; + weram<=ex1_ram_wr ; + Dma_data_in<=Dma_data_in1; + when "0010" => dma_wr_address <= dma_wr_address2; + weram<=ex2_ram_wr ; + Dma_data_in<=Dma_data_in2; + when "1000" => dma_wr_address <= dma_wr_address4; + weram<=ex4_ram_wr; + Dma_data_in<=Dma_data_in4; +-- when "0100" => dma_rd_address <= ; +-- when "1000" => dma_rd_address <= ; + when others => dma_wr_address <= (others =>'Z'); + weram<='0'; + end case; +end process; +--====================================================== + +--=================Mux des signaux qui vont au switch============ + clkout<=clk; -- permettra le lien avec le module du switch + + NOC1.port_out_data<=switch_port_out_data; + NOC1.port_out_data_available<=switch_port_out_data_vailaible; + NOC1.port_in_empty<=switch_port_in_empty; + NOC1.port_in_full<=switch_port_in_full; + + NOC2.port_out_data<=switch_port_out_data; + NOC2.port_out_data_available<=switch_port_out_data_vailaible; + NOC2.port_in_empty<=switch_port_in_empty; + NOC2.port_in_full<=switch_port_in_full; + + NOC3.port_out_data<=switch_port_out_data; + NOC3.port_out_data_available<=switch_port_out_data_vailaible; + NOC3.port_in_empty<=switch_port_in_empty; + NOC3.port_in_full<=switch_port_in_full; + mux_Noc:process (Ex_en,Noc1,Noc2,Noc3) + +begin + + case Ex_en is + + when"0001" => + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC2.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + when "0010" => + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC2.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + when"0011" => + switch_port_in_data <=Noc1.port_in_data; + switch_port_out_rd_en<=NOC2.port_out_rd_en; + switch_port_in_wr_en <=NOC1.port_in_wr_en; + switch_port_in_cmd_en <='0'; + when "1001" | "1010" => --ca où un appel à init est effectué + switch_port_in_data <=Noc3.port_in_data; + switch_port_out_rd_en<=NOC3.port_out_rd_en; + switch_port_in_wr_en <=NOC3.port_in_wr_en; + switch_port_in_cmd_en <=NOC3.port_in_cmd_en; + + when others => + switch_port_in_data <=(others=>'0'); + switch_port_out_rd_en<='0'; + switch_port_in_wr_en <='0'; + switch_port_in_cmd_en <='0'; + end case; + end process; + + +--=============================================================== +MPI_CORE_DMA_ARBITER: DMA_ARBITER PORT MAP( + clk =>clk, + reset =>reset, + + data_wr_mem => ram_data_in, --vers RAM + + data_rd_mem => Ram_data_out, --- Vers RAM + address_rd =>dma_rd_address, + address_wr =>dma_wr_address, + address_out_rd =>ram_address_rd, + address_out_wr =>ram_address_wr, + ram_en => ram_env, --validation lecture + ram_we =>ram_wev, --validation écriture + hold_req=>hold_req,--demande de bus à l'application + hold_ack=>hold_ack, -- libération du bus RAM par l'application + + data_rd_out => Dma_data_out, --vers périphérique + data_wr_in =>Dma_data_in, --vers périphérique + dma_wr_grant =>dma_wr_grant, + dma_rd_request => dma_rd_request, + dma_rd_grant => dma_rd_grant, + dma_wr_request => dma_wr_request + ); + + +CORE_SCHEDULER: MPI_CORE_SCHEDULER PORT MAP( -- permet de sélectionner la source de l'instruction + -- qui sera exécutée par la MAE EX1 + clk => clk, + reset => reset, + priority_rotation =>scheduler_priority_rotation, + instruction_fifo_empty =>instruction_fifo1_empty, + get_request_fifo_empty => instruction_fifo2_empty, + instruction_fifo_rd_en =>instruction_fifo1_rd_en, + get_request_fifo_rd_en =>instruction_fifo2_rd_en , + instruction_fifo_data =>instruction_fifo1_data_out, + get_request_fifo_data =>instruction_fifo2_data_out, + fifo_selected =>fifo_sel, + instruction_available => fifo_instr, + fifo_empty => scheduler_fifo_empty, + fifo_rd_en =>scheduler_rd_en, + data_out => scheduler_data_out + ); + +end structural; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/CORE_MPI_wave.fdo =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/CORE_MPI_wave.fdo (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/CORE_MPI_wave.fdo (revision 29) @@ -0,0 +1,11 @@ +###################################################################### +## +## Filename: CORE_MPI_wave.fdo +## Created on: Sat Jul 02 09:25:40 Paris, Madrid (heure d'été) 2011 +## +## Auto generated by Project Navigator for Post-Behavioral Simulation +## +## You may want to edit this file to control your simulation windows. +## +###################################################################### +add wave * Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DEMUX1.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DEMUX1.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DEMUX1.vhd (revision 29) @@ -0,0 +1,54 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:35:09 06/13/2011 +-- Design Name: +-- Module Name: DEMUX1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity DEMUX1 is + Port ( di : in STD_LOGIC; + sel : in STD_LOGIC; + do1 : out STD_LOGIC; + do2 : out STD_LOGIC); +end DEMUX1; + +architecture Behavioral of DEMUX1 is + +begin + +demux_process : process(di, sel) +begin + if sel = '0' then + do1 <= di; + do2 <= '0'; + else + do2 <= di; + do1 <='0'; + end if; +end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DEMUX1.vhi =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DEMUX1.vhi (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DEMUX1.vhi (revision 29) @@ -0,0 +1,25 @@ + +-- VHDL Instantiation Created from source file DEMUX1.vhd -- 12:17:42 06/13/2011 +-- +-- Notes: +-- 1) This instantiation template has been automatically generated using types +-- std_logic and std_logic_vector for the ports of the instantiated module +-- 2) To use this template to instantiate this entity, cut-and-paste and then edit + + COMPONENT DEMUX1 + PORT( + di : IN std_logic; + sel : IN std_logic; + do1 : OUT std_logic; + do2 : OUT std_logic + ); + END COMPONENT; + + Inst_DEMUX1: DEMUX1 PORT MAP( + di => , + sel => , + do1 => , + do2 => + ); + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DEMUX1_summary.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DEMUX1_summary.html (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DEMUX1_summary.html (revision 29) @@ -0,0 +1,73 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MPI_CORE_COMPONENTS Project Status
Project File:MPI_CORE_COMPONENTS.iseImplementation State:New
Module Name:DEMUX1
  • Errors:
 
Target Device:xc3s1200e-4fg320
  • Warnings:
 
Product Version:ISE 11.1
  • Routing Results:
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Design Goal:Balanced
  • Timing Constraints:
 
Design Strategy:Xilinx Default (unlocked)
  • Final Timing Score:
  
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Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
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Secondary Reports [-]
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Date Generated: 06/13/2011 - 12:45:39
+ Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DMA_ARBITER.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DMA_ARBITER.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DMA_ARBITER.vhd (revision 29) @@ -0,0 +1,369 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL +-- GAMOM ROLAND CHRISTIAN +-- +-- Create Date: 04:39:43 05/21/2011 +-- Design Name: +-- Module Name: DMA_ARBITER - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- gestionnaire DMA pour le port secodaire de la RAM true dual port des mémoire +-- privée de chaque noeud +-- Dependencies: +-- +-- Revision: 09/07/2012 +-- Revision 1.01 - File Created +-- Additional Comments: Ce module pourra être optimisé pour générer les adresses automatiquement +-- par le controleur DMA lorsqu'il est sollicité par la périphérie +-- +---------------------------------------------------------------------------------- +library IEEE; +library NocLib; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.numeric_std.all; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity DMA_ARBITER is + Port ( dma_rd_request : in STD_LOGIC_VEctor (3 downto 0):=(others=>'0'); + data_wr_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + data_rd_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + address_rd : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); --adresse pour lecture + address_wr : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); -- adresse pour écriture + address_out_wr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); -- adresse de sortie du DMA Arbiter + address_out_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_en : out STD_LOGIC; -- + ram_we : out STD_LOGIC; + data_wr_mem : out STD_LOGIC_VECTOR (Word-1 downto 0); -- donnée en sortie écriture + data_rd_mem : in STD_LOGIC_VECTOR (Word-1 downto 0); -- données en sortie lecture + dma_wr_grant : out STD_LOGIC_vector(3 downto 0):=(others=>'0'); -- autorisation d'écriture + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + clk : in std_logic; + reset : in std_logic; + dma_rd_grant : out STD_LOGIC_vector(3 downto 0):=(others=>'0'); -- autorisation de lecture + dma_wr_request : in STD_LOGIC_vector(3 downto 0):=(others=>'0')); -- demande de lecture +end DMA_ARBITER; + +architecture Behavioral of DMA_ARBITER is +type fsm_states is (idle,wait_ack,arbiter_ack, writing,ReadWrite,reading);-- definition du type etat pour le codage des etats des fsm +signal dmac_state : fsm_states; + +signal prio_rd,prio_wr:std_logic_vector(3 downto 0);--vecteur de bits de priorité +signal pri_rd,pri_wr : natural range 0 to 3; -- stocke le numéro du module qui a la priorité +signal dma_rd_logic : std_logic_vector(3 downto 0):=(others=>'0'); +signal dma_wr_logic : std_logic_vector(3 downto 0):=(others=>'0'); +signal dma_req_wr, dma_req_rd : std_logic; +signal tmp :std_logic_vector(3 downto 0):="0000"; + +begin +--========================================================================== +---le MUX qui contrôle les adresses est géré à l'extérieur du contrôleur DMA +data_rd_out<=data_rd_mem ; +data_wr_mem <= data_wr_in; +address_out_rd <= address_rd; +address_out_wr <= address_wr; +--========================================================================== + +--Déterminer si une requête HOLD doit être émise vers l'application pour la libération du +--bus mémoire +tmp<=(others =>'0'); + +--for i in 0 to 3 loop +--dma_req_wr<=dma_req_wr or dma_wr_request(i); +--loop; + +--for i in 0 to 3 loop +-- dma_req_rd<=dma_req_rd or dma_rd_request(i); -- construire le signal request vers l'extérieur +--loop; +hold_req<=dma_req_rd or dma_req_wr; --envoyer un Hold vers l'application + + +-- machine à etat du DMAC +dmac_process : process(clk) +--variable tmp : natural range 0 to 15; +variable tmp_rd,tmp_wr: std_logic_vector(3 downto 0); +variable req_rd,req_wr : std_logic:='0' ; + +begin + if rising_edge(clk) then + if reset = '1' then + dmac_state<= idle; + + prio_rd <="0001"; -- au debut priorité lecture au premier module + prio_wr <="0010"; -- au debut priorité ecriture au deuxième module + pri_rd<=0;--index de la priorité + pri_wr<=1; + req_rd:='0'; + req_wr:='0'; + else + if req_wr='0' or dma_wr_request="0000" then --tant que le Ctrl DMA est libre alors faire bouger la priorité en écriture + case dma_wr_request is + when "0001" => pri_wr<=0; + prio_wr<="0001"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="0001"; + when "0010" => pri_wr<=1; + prio_wr<="0010"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="0010"; + when "0100" => pri_wr<=2; + prio_wr<="0100"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="0100"; + when "1000" => pri_wr<=3; + prio_wr<="1000"; + req_wr:='1'; + dma_req_wr<= '1'; + dma_wr_logic <="1000"; + + when others => tmp_wr:= (dma_wr_request and prio_wr) ; + dma_wr_logic <=tmp_wr; + req_wr:= not(All_zeros(tmp_wr)); + dma_req_wr<= not(All_zeros(tmp_wr)); + -- la priorité est circulaire et décale à chaque coup d'horloge + prio_wr<=rol_vec(prio_wr); + if pri_wr=3 then + pri_wr<=0; + Prio_wr<="0001"; + else + pri_wr<=pri_wr+1; + end if; + end case; + + end if; + + if req_rd='0' or dma_rd_request="0000" then --tant que le Ctrl DMA est libre alors faire bouger la priorité + case dma_rd_request is + when "0001" => pri_rd<=0; + prio_rd<="0001"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="0001"; + when "0010" => pri_rd<=1; + prio_rd<="0010"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="0010"; + + when "0100" => pri_rd<=2; + prio_rd<="0100"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="0100"; + + when "1000" => pri_rd<=3; + prio_rd<="1000"; + req_rd:='1'; + dma_req_rd<= '1'; + dma_rd_logic<="1000"; + + when others => + + tmp_rd:= (dma_rd_request and prio_rd) ; + dma_rd_logic<=tmp_rd; + dma_req_rd<= not (All_Zeros(tmp_rd)); + req_rd:= not (All_Zeros(tmp_rd)); + + -- la priorité est circulaire et décale à chaque coup d'horloge + prio_rd<=rol_vec(prio_rd); + if pri_rd =3 then + pri_rd<=0; + prio_rd<="0001"; + else + + pri_rd<=pri_rd+1; + end if; + end case; + + end if; + + case dmac_state is + when idle => if req_rd='1' or req_wr='1' then + dmac_state<=wait_ack; + else -- initialiser la priorité + + + req_rd:='0'; + dma_req_rd<= '0'; + dma_rd_logic <="0000"; + + + req_wr:='0'; + dma_req_wr<= '0'; + dma_wr_logic <="0000"; + + end if; + when wait_ack => -- l'application doit autoriser l'utilisation de la RAM par le Core + if dma_wr_request(pri_wr) ='1' or dma_rd_request(pri_rd) ='1' then + if hold_ack='1' then + dmac_state<=arbiter_ack; + end if; + else + + if dma_wr_request(pri_wr) ='0' then + req_wr:='0';-- forcer une nouvelle recherche de priorité + end if; + + if dma_rd_request(pri_rd) ='0' then + req_rd:='0'; + end if; + dmac_state<=Idle; + end if; + + + when arbiter_ack => if dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='1' then -- + dmac_state <= Readwrite; + elsif dma_wr_request(pri_wr) ='0' and dma_rd_request(pri_rd) ='1' then + dmac_state <= Reading; + elsif dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='0' then + dmac_state <= Writing; + else + dmac_state<=Idle; + end if; + + when Writing => if dma_wr_request(pri_wr) ='1' then + if hold_ack='1' then + -- on reste dans cet état + if dma_rd_request(pri_rd)='1' then + dmac_state<=ReadWrite; + else + req_rd:='0'; + end if; + else + dmac_state<=wait_ack; + end if; + elsif dma_rd_request(pri_rd) ='1' then + dmac_state <= Reading; + else + dmac_state <= idle; + end if; + + + when ReadWrite => if hold_ack='1' then + if dma_wr_request(pri_wr)='1' and dma_rd_request(pri_rd)='1' then + dmac_state <= ReadWrite; + elsif dma_wr_request(pri_wr)='1' and dma_rd_request(pri_rd)='0' then + dmac_state <= Writing; + req_rd:='0'; + elsif dma_wr_request(pri_wr)='0' and dma_rd_request(pri_rd)='1' then + dmac_state <= Reading; + req_wr:='0'; + else + dmac_state <= Idle; + req_rd:='0';req_wr:='0'; + end if; + else + if (dma_wr_request(pri_wr)='1') or (dma_rd_request(pri_rd)='1') then + dmac_state <= Wait_ack; + else + dmac_state <= Idle; + end if; + end if; + when Reading => + if dma_rd_request(pri_rd) ='1' then + if hold_ack='1' then + -- on reste dans cet état + if dma_wr_request(pri_wr)='1' then + dmac_state<=ReadWrite; + else + req_wr:='0'; + end if; + else + dmac_state<=wait_ack; + end if; + elsif dma_wr_request(pri_wr) ='1' then + dmac_state<=writing; + else + dmac_state <= idle; + end if; + when others => dmac_state <= idle; + end case; + end if; + end if; +end process; +-- action_asociées +ol: process(dmac_state, address_rd, address_wr,pri_wr,pri_rd,prio_wr,prio_rd,dma_wr_request,dma_rd_request) + +begin +--tester les requêtes DMA en lecture ou en écriture + +case dmac_state is + when idle => + ram_en <='0'; + ram_we <='0'; + dma_wr_grant <=(others=>'0'); + dma_rd_grant <=(others=>'0'); + --address_out_rd <= address_rd; + --hold_req<='0'; + when wait_ack => + ram_en <='0'; + ram_we <='0'; + dma_wr_grant<=(others=>'0'); + dma_rd_grant<=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= (others=>'Z'); + --hold_req<='1'; + when arbiter_ack => --à optimiser pour gagner un cycle + ram_en <='1'; + ram_we <='0'; + dma_wr_grant<=(others=>'0'); + dma_rd_grant<=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= (others=>'Z'); + when writing => -- ecriture dans la ram + ram_en <='1'; + ram_we <='1'; + dma_wr_grant<=(others=>'0'); + dma_wr_grant(pri_wr) <='1'; + dma_rd_grant <=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= address_wr; + --hold_req<='1'; + + when ReadWrite => -- Lecture et écriture simultannée dans la Dual Port RAM + ram_en <='1'; + ram_we <='1'; + dma_wr_grant<=(others=>'0'); + dma_wr_grant(pri_wr) <='1'; + dma_rd_grant<=(others=>'0'); + dma_rd_grant(pri_rd)<='1'; + + --address_out_rd <= address_rd; + --address_out_wr <= address_wr; + --hold_req<='1'; + when Reading => -- lecture dans la ram + ram_en <='1'; + ram_we <='0'; + dma_wr_grant<=(others=>'0'); + dma_rd_grant<=(others=>'0'); + dma_rd_grant(pri_rd)<='1'; + + --address_out_rd <= address_rd; + --address_out_wr <= (others=>'Z'); + --hold_req<='1'; + when others => + ram_en <='0'; + ram_we <='0'; + dma_wr_grant <=(others=>'0'); + dma_rd_grant <=(others=>'0'); + --address_out_rd <= (others=>'Z'); + --address_out_wr <= (others=>'Z'); + --hold_req<='0'; + end case; +end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DMA_ARBITER.vhi =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DMA_ARBITER.vhi (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DMA_ARBITER.vhi (revision 29) @@ -0,0 +1,47 @@ + +-- VHDL Instantiation Created from source file DMA_ARBITER.vhd -- 05:54:04 06/21/2011 +-- +-- Notes: +-- 1) This instantiation template has been automatically generated using types +-- std_logic and std_logic_vector for the ports of the instantiated module +-- 2) To use this template to instantiate this entity, cut-and-paste and then edit + + COMPONENT DMA_ARBITER + PORT( + dma_rd_request : IN std_logic; + data_wr_in : IN std_logic_vector(7 downto 0); + data_rd_in : IN std_logic_vector(7 downto 0); + address_rd : IN std_logic_vector(15 downto 0); + address_wr : IN std_logic_vector(15 downto 0); + clk : IN std_logic; + reset : IN std_logic; + dma_wr_request : IN std_logic; + address_out : OUT std_logic_vector(15 downto 0); + ram_en : OUT std_logic; + ram_we : OUT std_logic; + data_wr_out : OUT std_logic_vector(7 downto 0); + data_rd_out : OUT std_logic_vector(7 downto 0); + dma_wr_grant : OUT std_logic; + dma_rd_grant : OUT std_logic + ); + END COMPONENT; + + Inst_DMA_ARBITER: DMA_ARBITER PORT MAP( + dma_rd_request => , + data_wr_in => , + data_rd_in => , + address_rd => , + address_wr => , + address_out => , + ram_en => , + ram_we => , + data_wr_out => , + data_rd_out => , + dma_wr_grant => , + clk => , + reset => , + dma_rd_grant => , + dma_wr_request => + ); + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DMA_ARBITER_envsettings.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DMA_ARBITER_envsettings.html (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DMA_ARBITER_envsettings.html (revision 29) @@ -0,0 +1,496 @@ +Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuildmappar
PATHEXT.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
Pathd:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
D:\Xilinx\12.3\ISE_DS\common\bin\nt64;
D:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\CMake 2.8\bin;
C:\qtsdk\mingw\bin;
C:\qtsdk\qtcreator\bin;
C:\Program Files (x86)\Graphviz 2.28\bin;
C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox		d:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
D:\Xilinx\12.3\ISE_DS\common\bin\nt64;
D:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\CMake 2.8\bin;
C:\qtsdk\mingw\bin;
C:\qtsdk\qtcreator\bin;
C:\Program Files (x86)\Graphviz 2.28\bin;
C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox		d:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
D:\Xilinx\12.3\ISE_DS\common\bin\nt64;
D:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\CMake 2.8\bin;
C:\qtsdk\mingw\bin;
C:\qtsdk\qtcreator\bin;
C:\Program Files (x86)\Graphviz 2.28\bin;
C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox		d:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
D:\Xilinx\12.3\ISE_DS\common\bin\nt64;
D:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\CMake 2.8\bin;
C:\qtsdk\mingw\bin;
C:\qtsdk\qtcreator\bin;
C:\Program Files (x86)\Graphviz 2.28\bin;
C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox
XILINXd:\Xilinx\12.3\ISE_DS\ISE\d:\Xilinx\12.3\ISE_DS\ISE\d:\Xilinx\12.3\ISE_DS\ISE\d:\Xilinx\12.3\ISE_DS\ISE\
XILINX_DSPD:\Xilinx\12.3\ISE_DS\ISED:\Xilinx\12.3\ISE_DS\ISED:\Xilinx\12.3\ISE_DS\ISED:\Xilinx\12.3\ISE_DS\ISE
XILINX_EDKD:\Xilinx\12.3\ISE_DS\EDKD:\Xilinx\12.3\ISE_DS\EDKD:\Xilinx\12.3\ISE_DS\EDKD:\Xilinx\12.3\ISE_DS\EDK
XILINX_PLANAHEADD:\Xilinx\12.3\ISE_DS\PlanAheadD:\Xilinx\12.3\ISE_DS\PlanAheadD:\Xilinx\12.3\ISE_DS\PlanAheadD:\Xilinx\12.3\ISE_DS\PlanAhead
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn DMA_ARBITER.prj 
-ifmt mixedMIXED
-ofn DMA_ARBITER 
-ofmt NGCNGC
-p xc3s1200e-5-ft256 
-top DMA_ARBITER 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-iucUse synthesis Constraints FileNONO
-keep_hierarchyKeep HierarchySoftNO
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNO
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYES
-write_timing_constraintsWrite Timing ConstraintsNONO
-cross_clock_analysisCross Clock AnalysisNONO
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100%
-bram_utilization_ratioBRAM Utilization Ratio100100%
-verilog2001Verilog 2001YESYES
-fsm_extract YESYES
-fsm_encoding AutoAUTO
-safe_implementation NoNO
-fsm_style LUTLUT
-ram_extract YesYES
-ram_style AutoAUTO
-rom_extract YesYES
-shreg_extract YESYES
-rom_style AutoAUTO
-auto_bram_packing NONO
-resource_sharing YESYES
-async_to_sync NONO
-mult_style LUTAUTO
-iobuf YESYES
-max_fanout 100000500
-bufg 2424
-register_duplication YESYES
-register_balancing NoNO
-optimize_primitives NONO
-use_clock_enable YesYES
-use_sync_set YesYES
-use_sync_reset YesYES
-iob AutoAUTO
-equivalent_register_removal YESYES
-slice_utilization_ratio_maxmargin 50%
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Translation Property Settings
Switch NameProperty NameValueDefault Value
-intstyle iseNone
-dd _ngoNone
-p xc3s1200e-ft256-5None
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Map Property Settings
Switch NameProperty NameValueDefault Value
-irUse RLOC ConstraintsOFFOFF
-cmOptimization Strategy (Cover Mode)areaarea
-intstyle iseNone
-o DMA_ARBITER_map.ncdNone
-prPack I/O Registers/Latches into IOBsoffoff
-p xc3s1200e-ft256-5None
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Place and Route Property Settings
Switch NameProperty NameValueDefault Value
-t 11
-intstyle ise 
-olPlace & Route Effort Level (Overall)highstd
-w truefalse
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHzIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHzIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHzIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHz
HostGAMOM-PCGAMOM-PCGAMOM-PCGAMOM-PC
OS NameMicrosoft Microsoft Microsoft Microsoft
OS ReleaseService Pack 1 (build 7601)Service Pack 1 (build 7601)Service Pack 1 (build 7601)Service Pack 1 (build 7601)
+ Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX1_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX1_FSM.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX1_FSM.vhd (revision 29) @@ -0,0 +1,685 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer:GAMOM /KIEGAING +-- +-- Create Date: 08:12:29 06/16/2011 +-- Design Name: +-- Module Name: EX1_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Ce module est chargé de recevoir les instructions du programme MPI et +-- de les exécuter (PUT) il coopère avec EX2 qui reçoit les instructions venant du NoC +-- (GET) +-- +-- Dependencies: +-- +-- Revision: 09/07/2012 +-- Revision 0.03 - File updated +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +--use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library NocLib ; +use Work.Packet_type.ALL; +USE ieee.numeric_std.ALL; + + +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX1_FSM is + -- parametres generiques du module : + + + Port ( + --instruction_available : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + + instruction_en : in std_logic:='0'; -- active le module instruction + pid : in std_logic_vector(3 downto 0) ; -- id du processeur + nprocs : in std_logic_vector(3 downto 0);-- nombre de processeur du MPSOC - 1 + Result : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module + AppInitReq :out STD_LOGIC:='0'; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic ; -- état de la Lib + -- Accès au Fifo d'instructions + priority_rotation : out STD_LOGIC:='0'; + fifo_rd_en : out STD_LOGIC:='0'; + fifo_empty : in STD_LOGIC; + fifo_data_out : in STD_LOGIC_VECTOR (7 downto 0); + + -- Accès au réseau sur puce + switch_port_in_full : in std_logic; + switch_port_in_data : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'Z'); + switch_port_in_wr_en : out STD_LOGIC:='0'; + -- Accès à la mémoire RAM du PE + ram_data_in : in std_logic_vector(7 downto 0); + ram_data_out : out std_logic_vector(7 downto 0):=(others=>'0'); + ram_rd,ram_wr : out std_logic:='0'; + ram_address : out std_logic_vector(15 downto 0):=(others=>'Z'); + + dma_wr_request : OUT std_logic:='0'; + dma_rd_request : OUT std_logic:='0'; + dma_wr_grant : in STD_LOGIC; + dma_rd_grant : in STD_LOGIC); +end EX1_FSM; + +architecture Behavioral of EX1_FSM is +-- definition du type etat pour le codage des etats des fsm +type fsm_states is (fifo_select, fetch_packet_type, decode_packet_type, fetch_addresses, + decode_packet_type2, read_status1,read_status2,execute_barrier1, execute_barrier2, execute_barrier3, execute_barrier4, + execute_get1, execute_get2,execute_get3,execute_get4, execute_put1, execute_put2, execute_put3, execute_put4,execute_put5, + execute_init1,execute_init2,execute_init3); +-- machine a etat du module +signal ex1_state_mach : fsm_states; + +-- les variables utilisées dans la fsm + +signal data_to_send : std_logic_vector(Word-1 downto 0); +signal packet_type : std_logic_vector(3 downto 0); +--signal dpid : std_logic_vector(3 downto 0); +signal pid_counter : std_logic_vector(3 downto 0); +signal packet_length : std_logic_vector(Word-1 downto 0); +signal src_address : std_logic_vector(ADRLEN-1 downto 0); +signal Wr_ok,rd_ok:std_logic:='0'; +--signal res_address : std_logic_vector(15 downto 0); +signal dest_address : std_logic_vector(ADRLEN-1 downto 0); +signal n : std_logic_vector(3 downto 0); +signal len : std_logic_vector(Word-1 downto 0); + +begin +-- connection des signaux avec les ports +ram_address <= src_address; + +-- processus de transistion entre les etats +fsm_nst_logic : process(clk) +variable tempval : std_logic_vector(Word-1 downto 0); +begin + if rising_edge(clk) then + if reset = '1' then + ex1_state_mach <= fifo_select; + else + case ex1_state_mach is + when fifo_select => if instruction_en='1' and fifo_empty ='0' then + ex1_state_mach <= fetch_packet_type; + else + ex1_state_mach <= fifo_select; + end if; + --lecture du registre status de la mib MPI + when read_status1 => if dma_rd_grant = '1' then -- fin du mpi_put + ex1_state_mach <= read_status2; + else + ex1_state_mach <= read_status1; + end if; + src_address<=std_logic_vector(to_unsigned(core_base_adr,16)); + when read_status2 => + ex1_state_mach <= fifo_select; + when fetch_packet_type => if fifo_empty ='1' then + ex1_state_mach <= fifo_select; + else + packet_type <= fifo_data_out(7 downto 4); + data_to_send <= fifo_data_out; + ex1_state_mach <= decode_packet_type; + end if; + when decode_packet_type => + if packet_type = MPI_PUT then + packet_length <= fifo_data_out + 4; + n <= "0000"; + ex1_state_mach <= fetch_addresses; + elsif packet_type = MPI_GET then + len <= fifo_data_out; + n <= "0000"; + ex1_state_mach <= fetch_addresses; + elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then + packet_length <= "00000011"; -- = 3 + pid_counter <= "0000"; + ex1_state_mach <= execute_barrier1; + elsif packet_type = MPI_INIT then + ex1_state_mach<=execute_init1; + else -- packet non reconnu + if fifo_empty = '1' then + ex1_state_mach <= fifo_select; + else + packet_type <= fifo_data_out(7 downto 4); --lire le prochain paquet + data_to_send <= fifo_data_out; + ex1_state_mach <= decode_packet_type;-- pas necessaire mais plus sure + end if; + end if; + + when fetch_addresses => if fifo_empty = '0' and n = 0 then + src_address(15 downto 8) <= fifo_data_out; + n <= n + 1; + ex1_state_mach <= fetch_addresses; + elsif fifo_empty = '0' and n = 1 then + src_address(7 downto 0) <= fifo_data_out; + n <= n + 1; + ex1_state_mach <= fetch_addresses; + elsif fifo_empty = '0' and n = 2 then + dest_address(15 downto 8) <= fifo_data_out; + n <= n + 1; + ex1_state_mach <= fetch_addresses; + elsif fifo_empty = '0' and n = 3 then + dest_address(7 downto 0) <= fifo_data_out; + n <= "0000"; + ex1_state_mach <= decode_packet_type2; + elsif fifo_empty='1' then + ex1_state_mach <= fetch_addresses; --attendre les données manquantes + else + ex1_state_mach <= fifo_select; + end if; + when decode_packet_type2 => if packet_type = MPI_PUT then + ex1_state_mach <= execute_put1; + elsif packet_type = MPI_GET then + ex1_state_mach <= execute_get1; + end if; + -- execution du mpi put + when execute_put1 => if dma_rd_grant = '1' then + ex1_state_mach <= execute_put2; + else + ex1_state_mach <= execute_put1; + end if; + Wr_ok<='0'; + when execute_put2 => if switch_port_in_full = '0' and n = 0 then + data_to_send <= packet_length; + n <= n + 1; + ex1_state_mach <= execute_put2; + elsif switch_port_in_full = '0' and n = 1 then + data_to_send <= dest_address(15 downto 8); + n <= n + 1; + ex1_state_mach <= execute_put2; + elsif switch_port_in_full = '0' and n = 2 then + data_to_send <= dest_address(7 downto 0); + n <= n +1; + ex1_state_mach <= execute_put2; + elsif switch_port_in_full = '0' and n = 3 then + packet_length <= packet_length - 4; + ex1_state_mach <= execute_put3; + Wr_ok<='0'; + else + ex1_state_mach <= execute_put2; + end if; + when execute_put3 => if unsigned(packet_length)>0 then + if switch_port_in_full = '0' then + packet_length <= packet_length - 1; + src_address <= src_address + 1; + ex1_state_mach <= execute_put3; + Wr_Ok<='1'; + else + Wr_Ok<='0'; + end if; + else + ex1_state_mach <= execute_put4; + end if; + when execute_put4 => if dma_wr_grant = '1' then -- fin du mpi_put + ex1_state_mach <= execute_put5; + n<="0000"; + data_to_send<="00000001"; + rd_ok<='1'; + wr_ok<='0'; + else + ex1_state_mach <= execute_put4; + end if; + src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when execute_put5 => + if n=0 then + if dma_rd_grant='1' then + n<=n+1; + tempval:=Ram_data_in; + src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + tempval(5):='1'; -- SET du bit DSENT + data_to_send<=tempval; + + end if; + rd_ok<='1'; + wr_ok<='0'; + elsif n=1 then + if dma_wr_grant = '1' then + n<=n+1; + + src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + end if; + rd_ok<='0'; + wr_ok<='1'; + elsif n=2 then + if dma_wr_grant = '1' then + n<=n+1; + + src_address<=std_logic_vector(to_unsigned(core_put_adr+6,16)); + + end if; + rd_ok<='0'; + wr_ok<='1'; + elsif n=3 then + if dma_wr_grant = '1' then + n<=n+1; + + -- SET du bit DSENT + data_to_send<="00000001"; + end if; + rd_ok<='0'; + wr_ok<='1'; + elsif n=4 then + n<="0000"; + ex1_state_mach <= fifo_select; + rd_ok<='0'; + wr_ok<='0'; + end if; + + + when execute_get1 => if switch_port_in_full = '0' and n = 0 then -- execution du mpi get + data_to_send <= "00001000"; -- longueur du paquet sur le réseau ? + n <= n + 1; + ex1_state_mach <= execute_get1; + elsif switch_port_in_full = '0' and n = 1 then + data_to_send <= "0000"&pid; -- Rang source + n <= n + 1; + ex1_state_mach <= execute_get1; + elsif switch_port_in_full = '0' and n = 2 then + data_to_send <= len; + n <= n + 1; + ex1_state_mach <= execute_get1; + elsif switch_port_in_full = '0' and n = 3 then + data_to_send <= src_address(15 downto 8); + n <= n + 1; + ex1_state_mach <= execute_get1; + elsif switch_port_in_full = '0' and n = 4 then + data_to_send <= src_address(7 downto 0); + n <= n + 1; + ex1_state_mach <= execute_get1; + elsif switch_port_in_full = '0' and n = 5 then + data_to_send <= dest_address(15 downto 8); + n <= n + 1; + ex1_state_mach <= execute_get1; + elsif switch_port_in_full = '0' and n = 6 then + data_to_send <= dest_address(7 downto 0); + n <= n + 1; + ex1_state_mach <= execute_get2; + else + ex1_state_mach <= execute_get1; + end if; + when execute_get2 => if switch_port_in_full = '0' then + ex1_state_mach <= execute_get3; + else + ex1_state_mach <= execute_get2; + end if; + when execute_get3 => if dma_wr_grant = '1' then -- fin du post de mpi_get + ex1_state_mach <= execute_get4; + n<="0000"; + data_to_send<="00000001"; + else + ex1_state_mach <= execute_get3; + end if; + src_address<=std_logic_vector(to_unsigned(core_get_adr+6,16)); + when execute_get4 => + if n=0 then + if dma_rd_grant='1' then + n<=n+1; + tempval:=Ram_data_in; + src_address<=std_logic_vector(to_unsigned(core_get_adr+6,16)); + end if; + elsif n=1 then + n<=n+1; + src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + elsif n=2 then + if dma_wr_grant = '1' then + n<=n+1; + + tempval(4):='0'; --RESET du bit DReceived + tempval(1):='1'; -- SET du bit DReceiving + data_to_send<=tempval; + end if; + elsif n=3 then + n<="0000"; + ex1_state_mach <= fifo_select; + end if; + + -- execution du barrier + when execute_barrier1 => if switch_port_in_full = '0' then + ex1_state_mach <= execute_barrier2; + else + ex1_state_mach <= execute_barrier1; + end if; + when execute_barrier2 => if switch_port_in_full = '0' then + ex1_state_mach <= execute_barrier3; + else + ex1_state_mach <= execute_barrier2; + end if; + when execute_barrier3 => if switch_port_in_full = '0' then + ex1_state_mach <= execute_barrier4; + else + ex1_state_mach <= execute_barrier3; + end if; + when execute_barrier4 => if packet_type = MPI_BARRIER_COMPLETED and pid_counter < nprocs then + pid_counter <= pid_counter + 1; + ex1_state_mach <= execute_barrier1; + else + ex1_state_mach <= fifo_select; + end if; + when execute_init1 => if Initialized='1' then + ex1_state_mach<=execute_init2; + end if; + + when execute_init2 => if dma_wr_grant = '1' then -- fin du mpi_init + ex1_state_mach <= execute_init3; + else + ex1_state_mach <= execute_init2; + end if; + -- écriture dans le registre status reg. + src_address<=std_logic_vector(to_unsigned(core_base_adr,16)); + when execute_init3 =>if AppInitAck='1' then + ex1_state_mach <= fifo_select; + end if; + when others => ex1_state_mach <= fifo_select; + end case; + end if; + end if; + end process; + + -- sortie de la machine à etat + ex1_fsm_action : process(ex1_state_mach, fifo_empty, switch_port_in_full, packet_length,pid, + pid_counter, ram_data_in,AppInitAck, data_to_send, packet_type, wr_ok) + variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0'); + begin +-- code fonctionnel + case ex1_state_mach is + when fifo_select => priority_rotation <='1'; -- on peut changer la priorité + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'Z'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result <=(others=>'0'); + when read_status1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'Z'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result <=(others=>'0'); + when read_status2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'Z'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + status_reg:=Ram_data_in; + Result <=(others=>'0'); + when fetch_packet_type => priority_rotation <='0'; + fifo_rd_en <= not(fifo_empty); + switch_port_in_data <= (others =>'Z'); + AppInitReq<='0'; + switch_port_in_wr_en <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result <=(others=>'0'); + + when decode_packet_type => priority_rotation <='0'; + fifo_rd_en <= not(fifo_empty); + switch_port_in_data <= (others =>'Z'); + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result <=(others=>'0'); + + when fetch_addresses => priority_rotation <='0'; + fifo_rd_en <= not(fifo_empty); + switch_port_in_data <= (others =>'Z'); + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result <=(others=>'0'); + + when decode_packet_type2 =>priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result <=(others=>'0'); + + when execute_barrier1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= packet_type & pid_counter; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result <=(others=>'0'); + + when execute_barrier2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= packet_length; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result <=(others=>'0'); + + when execute_barrier3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= "0000" & pid; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result <=(others=>'0'); + + when execute_barrier4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= "0000" & pid; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result <=(others=>'0'); + + when execute_get1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result <=(others=>'0'); + + when execute_get2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='0'; + Ram_wr<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result <=(others=>'0'); + + + when execute_get3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_data_in;---??? + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<='1'; + Ram_data_out<=data_to_send; -- le résultat de l'exécution + --result(1)<='1'; + Result <=(2=>'1',others=>'0');--Get completed + when execute_get4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '1'; + Ram_rd<='1'; + Ram_wr<='1'; + Ram_data_out<=data_to_send; --"00000001"; + Result <=(2=>'1',others=>'0'); --get completed + when execute_put1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result <=(others=>'0'); + + + when execute_put2 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= data_to_send; + switch_port_in_wr_en <= not(switch_port_in_full); + AppInitReq<='0'; + Ram_rd<='1'; + Ram_wr<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_data_out<=(others=>'0'); + Result <=(others=>'0'); + + when execute_put3 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_data_in; + switch_port_in_wr_en <= not(switch_port_in_full) and wr_ok; + AppInitReq<='0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + Ram_rd<='1'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + Result <=(others=>'0'); + + when execute_put4 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_data_in;---??? + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<='1'; + Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution + --result(1)<='1'; + Result <=(1=>'1',others=>'0');--put completed + when execute_put5 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='0'; + dma_rd_request <= rd_ok; + dma_wr_request <= wr_ok; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=data_to_send; --"00000001"; + Result <=(1=>'1',others=>'0'); --put completed + when execute_init1 => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'Z'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='1'; + Result <=(others=>'0'); + + when execute_init2=> priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'Z'); + switch_port_in_wr_en <= '0'; + AppInitReq<='1'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<='1'; + Ram_data_out<="00010000"; -- le résultat de l'exécution + -- dans le registre status + Result <=(others=>'0');-- + when execute_init3=> priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= ram_Data_in; + switch_port_in_wr_en <= '0'; + AppInitReq<='1'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + Ram_rd<='0'; + Ram_wr<='1'; + Ram_data_out<="00010000"; + Result<=(0=>'1',others=>'0'); --le résultat de l'initialisation est écrit + + when others => priority_rotation <='0'; + fifo_rd_en <= '0'; + switch_port_in_data <= (others =>'Z'); + switch_port_in_wr_en <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'0'); + AppInitReq<='0'; + Result <=(others=>'0'); + end case; + + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX1_FSM.vhi =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX1_FSM.vhi (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX1_FSM.vhi (revision 29) @@ -0,0 +1,43 @@ + +-- VHDL Instantiation Created from source file EX1_FSM.vhd -- 05:54:42 06/21/2011 +-- +-- Notes: +-- 1) This instantiation template has been automatically generated using types +-- std_logic and std_logic_vector for the ports of the instantiated module +-- 2) To use this template to instantiate this entity, cut-and-paste and then edit + + COMPONENT EX1_FSM + PORT( + clk : IN std_logic; + reset : IN std_logic; + fifo_empty : IN std_logic; + fifo_data_out : IN std_logic_vector(7 downto 0); + switch_port_in_full : IN std_logic; + ram_data : IN std_logic_vector(7 downto 0); + dma_grant : IN std_logic; + ram_address : OUT std_logic_vector(15 downto 0); + priority_rotation : OUT std_logic; + fifo_rd_en : OUT std_logic; + switch_port_in_data : OUT std_logic_vector(7 downto 0); + switch_port_in_wr_en : OUT std_logic; + dma_request : OUT std_logic + ); + END COMPONENT; + + Inst_EX1_FSM: EX1_FSM PORT MAP( + clk => , + reset => , + fifo_empty => , + fifo_data_out => , + switch_port_in_full => , + ram_data => , + ram_address => , + priority_rotation => , + fifo_rd_en => , + switch_port_in_data => , + switch_port_in_wr_en => , + dma_request => , + dma_grant => + ); + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX2_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX2_FSM.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX2_FSM.vhd (revision 29) @@ -0,0 +1,662 @@ +---------------------------------------------------------------------------------- +-- Company: GRIIA - ETIS +-- Engineer: GAMOM, KIEGAING +-- +-- Create Date: 01:02:10 06/17/2011 +-- Design Name: +-- Module Name: EX2_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- machine a etat qui execute la reception des packet dans le core mpi +-- Dependencies: +--ss +-- Revision: 26/01/2012 +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +library NocLib ; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.Numeric_std.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use Work.Packet_type.ALL; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX2_FSM is + + generic ( + pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur + nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1 + ); + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + + Instruction_en : in std_logic; + + dma_wr_grant : in STD_LOGIC; + dma_wr_request : out STD_LOGIC; + dma_rd_grant : in STD_LOGIC; + dma_rd_request : out STD_LOGIC; + ram_rd : out std_logic; + ram_wr : out std_logic; + ram_address : out std_logic_vector(ADRLEN-1 downto 0); + Ram_data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + Ram_data_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + + fifo_data : out STD_LOGIC_VECTOR (Word-1 downto 0); + fifo_wr_en : out STD_LOGIC; + fifo_full : in STD_LOGIC; + + AppRank : in STD_LOGIC_VECTOR(3 downto 0); + AppSize : in STD_LOGIC_VECTOR(3 downto 0); + packet_received : out STD_LOGIC; + packet_ack : in STD_LOGIC; + barrier_completed : out STD_LOGIC; + Ready : Out std_logic; + AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application + AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation + Initialized:in std_logic ; -- état de la Lib + + switch_data_available : in STD_LOGIC; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_out_rd_en : out STD_LOGIC + + + + ); +end EX2_FSM; + +architecture Behavioral of EX2_FSM is +-- définition du type etat de la machine à etat +type fsm_states is (fetch_packet_type, decode_packet_type, decode_packet_type2, +fetch_addresses,execute_spawn,execute_put1,execute_put2,execute_put3 ,execute_put4, +execute_put5,execute_get1, execute_get2,execute_get3,execute_get4, + execute_barrier1, execute_barrier2, execute_barrier3, execute_barrier4, + execute_barrier5, execute_barrier6, execute_barrier7,execute_init1,execute_init2); +signal ex2_state_mach :fsm_states; +-- machine a etat du module +signal packet_type : std_logic_vector(3 downto 0); +signal packet_length : std_logic_vector(Word-1 downto 0); +signal barrier_counter : std_logic_vector(3 downto 0); +signal pading_data,data_to_ram : std_logic_vector(Word-1 downto 0):=(others=>'0'); +signal n : std_logic_vector(3 downto 0); +signal dest_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'Z'); +signal data_to_write_fifo : std_logic_vector(Word-1 downto 0); +signal Ex2_on : std_logic:='0'; +signal rd_ok ,wr_ok:std_logic:='0'; + +begin +ram_address <= dest_address; +fifo_data <= data_to_write_fifo; + +-- processus de transistion entre les etats +fsm_nst_logic : process(clk) +variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée +variable tempval : std_logic_vector(Word-1 downto 0); +begin + if rising_edge(clk) then + if reset = '1' then + ex2_state_mach <= fetch_packet_type; + Ex2_on<='0'; + barrier_counter <= "0000"; + else + Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non + case ex2_state_mach is + when fetch_packet_type => if switch_data_available ='1' and Ex2_on='1' then --and initialized ='1' + ex2_state_mach <= decode_packet_type; + packet_type<=switch_port_out_data(7 downto 4); + else + ex2_state_mach <= fetch_packet_type; + end if; + when decode_packet_type => if switch_data_available ='0' then + ex2_state_mach <= decode_packet_type; + else + if packet_type = MPI_PUT then + packet_length <= switch_port_out_data - 2; + n <="0000"; + ex2_state_mach <= decode_packet_type2; + elsif packet_type = MPI_GET then + packet_length <=switch_port_out_data-2; + ex2_state_mach <= decode_packet_type2; + elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then + packet_length <= switch_port_out_data; + n <= "0000"; + ex2_state_mach <= execute_barrier1; + elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then + ex2_state_mach <= execute_init1; + else + ex2_state_mach <= decode_packet_type; + end if; + end if; + when decode_packet_type2 => if packet_type = MPI_PUT then + ex2_state_mach <= fetch_addresses; + else + ex2_state_mach <= execute_get1; + end if; + when fetch_addresses => if switch_data_available = '1' and n = 0 then + dest_address(15 downto 8) <= switch_port_out_data; + n <= n + 1; + ex2_state_mach <= fetch_addresses; + elsif switch_data_available = '1' and n = 1 then + dest_address(Word-1 downto 0) <= switch_port_out_data; + packet_length <= packet_length - 2; + ex2_state_mach <= execute_put1; + else + ex2_state_mach <= fetch_addresses; + end if; + -- execution du mpi Init + when execute_init1 =>if Initialized='1' then + ex2_state_mach<=execute_init2; + end if; + when execute_init2=> if AppInitAck='1' then + ex2_state_mach<=fetch_packet_type; + end if; + when execute_put1 => if dma_wr_grant = '1' then + ex2_state_mach <= execute_put2; + data_to_ram<=switch_port_out_data; + rd_ok<='1'; + n<="0000"; + delai:=0; + else + ex2_state_mach <= execute_put1; + end if; + when execute_put2 => if unsigned( packet_length) > 1 then + if switch_data_available = '1' and dma_wr_grant='1' then + -- n<=n+1; + --if delai=0 then + packet_length <= packet_length - 1; + dest_address <= dest_address + 1; + ex2_state_mach <= execute_put2; + rd_ok<='1'; + data_to_ram<=switch_port_out_data; + --else + -- delai:=0; + -- end if; + else + if switch_data_available = '1' and dma_wr_grant='0'then + if delai=0 then + data_to_ram<=switch_port_out_data; + end if; + delai:=1;--indique qu'un temps supplémentaire est + --nécessaire pour écrire la donnée en RAM + end if; + ex2_state_mach <= execute_put2; + rd_ok<='0'; + end if; + else + if switch_data_available = '1' then + --la dernière donnée à écrire en RAM + data_to_ram<=switch_port_out_data; + end if; + rd_ok<='0'; + + if dma_wr_grant='1' then + + ex2_state_mach <= execute_put3; + + + end if; + end if; + + when execute_put3 => if dma_rd_grant='1' then + dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + ex2_state_mach <= execute_put4; + n<="0000"; + rd_ok<='1'; + wr_ok<='0'; + end if; + + when execute_put4 => if n=0 then + if dma_rd_grant='1' then + n<=n+1; + tempval:=Ram_data_in; + tempval(4):='1'; --SET du bit DReceived + data_to_ram<=tempval; + + end if; + rd_ok<='1'; + wr_ok<='0'; + elsif n=1 then + rd_ok<='0'; + wr_ok<='1'; + n<=n+1; + elsif n=2 then + if dma_wr_grant='1' then + rd_ok<='0'; + wr_ok<='1'; + ex2_state_mach <= execute_put5; + n<="0000"; + end if; + end if; + + + + dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction + when execute_put5 => + ex2_state_mach <= fetch_packet_type; -- fin du mpi_put + + + when execute_get1 => if switch_data_available = '1' then -- conversion du get en put en empilement dans le fifo + data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0); + packet_length <= packet_length - 1; + ex2_state_mach <= execute_get2; + wr_ok<='1'; + end if; + when execute_get2 => if fifo_full = '0'and switch_data_available ='1' and packet_length > 0 then + data_to_write_fifo <= switch_port_out_data; + packet_length <= packet_length - 1; + ex2_state_mach <= execute_get2; + wr_ok<='1'; + elsif packet_length = 0 and switch_data_available ='1' then-- + ex2_state_mach <= fetch_packet_type; + wr_ok<='0'; + else + ex2_state_mach <= execute_get3; + wr_ok<='0'; + end if; + when execute_get3 => if dma_rd_grant='1' then -- fin du mpi_put + ex2_state_mach <= execute_get4; + n<="0000"; + --activer le bit sending du registre de transfert + else + ex2_state_mach <= execute_get3; + end if; + + dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + when execute_get4 => + if n=0 then + if dma_rd_grant='1' then + n<=n+1; + tempval:=Ram_data_in; + tempval(2):='1'; --mise à 1 du Bit Dreceiving + tempval(5):='0'; --Mise à 0 du Bit Sent + data_to_ram<=tempval; + end if; + rd_ok<='1'; + wr_ok<='0'; + elsif n=1 then + n<=n+1; + elsif n=2 then + n<=n+1; + rd_ok<='0'; + wr_ok<='1'; + elsif n=3 then + if dma_wr_grant = '1' then + n<="0000"; + ex2_state_mach <= fetch_packet_type; -- fin du mpi_get + end if; + rd_ok<='0'; + wr_ok<='1'; + end if; + + + dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16)); + -- execution du barrier + when execute_barrier1 => if switch_data_available = '1' then + pading_data <= switch_port_out_data; + ex2_state_mach <= execute_barrier2; + else + ex2_state_mach <= execute_barrier1; + end if; + when execute_barrier2 => if packet_type = MPI_BARRIER_REACHED then + barrier_counter <= barrier_counter + 1; + ex2_state_mach <= execute_barrier4; + else + ex2_state_mach <= execute_barrier3; + end if; + when execute_barrier3 => if n < 10 then + n <= n + 1; + ex2_state_mach <= execute_barrier3; + else + ex2_state_mach <= fetch_packet_type; + end if; + when execute_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED + data_to_write_fifo <= MPI_BARRIER_COMPLETED & "0000"; + ex2_state_mach <= execute_barrier5; + else + ex2_state_mach <= fetch_packet_type; + end if; + when execute_barrier5 => if fifo_full = '0' then -- taille du packet MPI_BARRIER_COMPLETED + data_to_write_fifo <= "00000011"; + ex2_state_mach <= execute_barrier6; + else + ex2_state_mach <= execute_barrier5; + end if; + when execute_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED + data_to_write_fifo <= "00000000"; + ex2_state_mach <= execute_barrier7; + else + ex2_state_mach <= execute_barrier6; + end if; + when execute_barrier7 => if fifo_full = '0' then + barrier_counter <= "0000"; + ex2_state_mach <= fetch_packet_type; + else + ex2_state_mach <= execute_barrier7; + end if; + + when others => ex2_state_mach <= fetch_packet_type; + end case; + end if; + end if; + end process; + + -- sortie de la machine à etat +-- + ex2_fsm_action : process(ex2_state_mach, fifo_full, packet_length, data_to_write_fifo, packet_type, + switch_data_available,switch_port_out_data,Ram_data_in,rd_ok) + variable transact : std_logic_vector(Word-1 downto 0); + begin +-- code fonctionnel + case ex2_state_mach is + + when fetch_packet_type => fifo_wr_en <= '0'; + switch_port_out_rd_en <= switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_out<=(others=>'Z'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='1'; + AppInitReq<='0'; + + + when decode_packet_type => fifo_wr_en <= '0'; + switch_port_out_rd_en <= switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'Z'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when decode_packet_type2 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'Z'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + when fetch_addresses => fifo_wr_en <= '0'; + switch_port_out_rd_en <= switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'Z'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when execute_put1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '1'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'Z'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when execute_put2 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <=rd_ok; + + if rd_ok = '1' then + + Ram_data_out<=switch_port_out_data; + else + Ram_data_out<=data_to_ram; + end if; + Ram_wr<='1'; + Ram_rd<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + when execute_put3 => Ready<='0'; + fifo_wr_en <= '0'; + switch_port_out_rd_en <=rd_ok; + --ne pas corrompre le contenu de la RAM + Ram_data_out<=data_to_ram; + Ram_wr<='0'; + Ram_rd<='1'; + packet_received <= '0'; + dma_rd_request <= '1'; + dma_wr_request <= '0'; + AppInitReq<='0'; + barrier_completed <= '0'; + + + when execute_put4 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <= '0'; + packet_received <= '1'; + dma_rd_request <= rd_ok; + dma_wr_request <=wr_ok; + Ram_wr<=wr_ok; + Ram_rd<=rd_ok; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_out<=Ram_data_in or "00000010"; -- le résultat de l'exécution + + when execute_put5 => + Ready<='0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '1'; + AppInitReq<='0'; + barrier_completed <= '0'; + dma_rd_request <= rd_ok; + dma_wr_request <= wr_ok; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=ram_data_in or "00000010"; + --Result <=(1=>'1',others=>'0'); --put completed + + when execute_get1=> fifo_wr_en <= '0'; + switch_port_out_rd_en <= switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'Z'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when execute_get2 => if fifo_full = '0' and switch_data_available = '1' and packet_length > 0 then + + switch_port_out_rd_en <='1'; + else + + switch_port_out_rd_en <='0'; + end if; + + fifo_wr_en <= Wr_ok; + Ready<='0'; + packet_received <= '0'; + dma_rd_request <= '0'; + dma_wr_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'Z'); + barrier_completed <= '0'; + AppInitReq<='0'; + + when execute_get3 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <= '0'; + packet_received <= '1'; + dma_rd_request <= '1'; + dma_wr_request <='0'; + Ram_wr<='0'; + Ram_rd<='1'; + AppInitReq<='0'; + barrier_completed <= '0'; + Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending + + when execute_get4 => + Ready<='0'; + barrier_completed <= '0'; + switch_port_out_rd_en<='0'; + fifo_wr_en <= '0'; + packet_received <= '1'; + AppInitReq<='0'; + dma_rd_request <= rd_ok; + dma_wr_request <= wr_ok; + Ram_rd<=rd_ok; + Ram_wr<=wr_ok; + Ram_data_out<=ram_data_in or "00000010"; --activer le bit DSending + + + when execute_barrier1 => fifo_wr_en <= '0'; + switch_port_out_rd_en <= switch_data_available; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'Z'); + barrier_completed <= '0'; + Ready<='0'; + AppInitReq<='0'; + + when execute_barrier2 => fifo_wr_en <= '0'; + Ready<='0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'Z'); + barrier_completed <= '0'; + AppInitReq<='0'; + + when execute_barrier3 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + Ready<='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'Z'); + barrier_completed <= '1'; + AppInitReq<='0'; + + when execute_barrier4 => fifo_wr_en <= '0'; + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'Z'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + + when execute_barrier5 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <='0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'Z'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when execute_barrier6 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'Z'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + when execute_barrier7 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + Ram_data_out<=(others=>'Z'); + barrier_completed <= '0'; + AppInitReq<='0'; + Ready<='0'; + + + when execute_init1 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ready<='0'; + Ram_data_out<=(others =>'Z'); + AppInitReq<='1'; + + + when execute_init2 => fifo_wr_en <= not(fifo_full); + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + Ram_rd<='0'; + Ram_wr<='0'; + barrier_completed <= '0'; + Ram_data_out<=(others =>'Z'); + AppInitReq<='1'; + Ready<='0'; + + when others => Ready<='1'; -- le module est à nouveau libre + fifo_wr_en <= '0'; + switch_port_out_rd_en <= '0'; + packet_received <= '0'; + dma_wr_request <= '0'; + dma_rd_request <= '0'; + barrier_completed <= '0'; + Ram_data_out<=(others=>'Z'); + Ram_rd<='0'; + Ram_wr<='0'; + Ready<='1'; + AppInitReq<='0'; + end case; + + end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX2_FSM.vhi =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX2_FSM.vhi (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX2_FSM.vhi (revision 29) @@ -0,0 +1,45 @@ + +-- VHDL Instantiation Created from source file EX2_FSM.vhd -- 05:55:35 06/21/2011 +-- +-- Notes: +-- 1) This instantiation template has been automatically generated using types +-- std_logic and std_logic_vector for the ports of the instantiated module +-- 2) To use this template to instantiate this entity, cut-and-paste and then edit + + COMPONENT EX2_FSM + PORT( + dma_grant : IN std_logic; + fifo_full : IN std_logic; + switch_data_available : IN std_logic; + switch_port_out_data : IN std_logic_vector(7 downto 0); + packet_ack : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + dma_request : OUT std_logic; + ram_address : OUT std_logic_vector(15 downto 0); + fifo_data : OUT std_logic_vector(7 downto 0); + fifo_wr_en : OUT std_logic; + packet_received : OUT std_logic; + barrier_completed : OUT std_logic; + switch_port_out_rd_en : OUT std_logic + ); + END COMPONENT; + + Inst_EX2_FSM: EX2_FSM PORT MAP( + dma_grant => , + fifo_full => , + switch_data_available => , + switch_port_out_data => , + dma_request => , + ram_address => , + fifo_data => , + fifo_wr_en => , + packet_received => , + packet_ack => , + barrier_completed => , + clk => , + reset => , + switch_port_out_rd_en => + ); + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX3_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX3_FSM.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX3_FSM.vhd (revision 29) @@ -0,0 +1,75 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM / KIEGAING +-- +-- Create Date: 09:22:58 05/20/2011 +-- Design Name: +-- Module Name: EX3_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- module du core mpi chargé d'exécuter les fonctions mpi_get_size et mpi_get_rank +-- Dependencies: +-- +-- Revision: 23/02/2012 +-- Revision 0.02 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +--package Packet_type +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use Work.Packet_type.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX3_FSM is + generic ( + pid : unsigned(Word-1 downto 0) := "00000001"; -- id du processeur + nprocs : unsigned(Word-1 downto 0):="00000011"-- nombre de processeur du MPSOC + ); + Port ( instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + ResOut : out STD_LOGIC_VECTOR (Word-1 downto 0); + pid_nprocs: out STD_LOGIC_VECTOR (Word-1 downto 0); + clk : in STD_LOGIC; + IsMain: in STD_LOGIC; + reset : in STD_LOGIC); +end EX3_FSM; + + +architecture Behavioral of EX3_FSM is + +signal instruction_signal : std_logic_vector(3 downto 0); +signal rank : unsigned(Word-1 downto 0) := pid; +signal size : unsigned(Word-1 downto 0) := nprocs; +begin +instruction_signal <= instruction(3 downto 0); +ex3_fsm_process : process(clk) +begin + + +if rising_edge(clk) then + if reset ='1' then + ResOut <= (others=>'0'); + else + if instruction_signal = MPI_GET_RANK then + ResOut <= std_logic_vector(rank); + elsif instruction_signal = MPI_GET_SIZE then + ResOut <= std_logic_vector(size); + elsif instruction_signal=MPI_INIT then + if IsMain='1' then --master est associé à la bibliothèque de rang 0 + rank<=rank+1; -- elle est responsable d'affecter de nouveaux rangs + end if; + end if; + end if; +end if; +end process; +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX3_FSM.vhi =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX3_FSM.vhi (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX3_FSM.vhi (revision 29) @@ -0,0 +1,25 @@ + +-- VHDL Instantiation Created from source file EX3_FSM.vhd -- 05:56:26 06/21/2011 +-- +-- Notes: +-- 1) This instantiation template has been automatically generated using types +-- std_logic and std_logic_vector for the ports of the instantiated module +-- 2) To use this template to instantiate this entity, cut-and-paste and then edit + + COMPONENT EX3_FSM + PORT( + instruction : IN std_logic_vector(7 downto 0); + clk : IN std_logic; + reset : IN std_logic; + pid_nprocs : OUT std_logic_vector(3 downto 0) + ); + END COMPONENT; + + Inst_EX3_FSM: EX3_FSM PORT MAP( + instruction => , + pid_nprocs => , + clk => , + reset => + ); + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX4_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX4_FSM.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX4_FSM.vhd (revision 29) @@ -0,0 +1,1095 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM +-- +-- Create Date: 14:44:36 03/07/2012 +-- Design Name: +-- Module Name: EX4_FSM - Behavioral +-- Project Name: MPI_CORE_COMPONENTS +-- Target Devices: SPARTAN 3E xc3s1200e +-- Tool versions: +-- Description: Ce module renferme les fonctions permettant d'initialiser la +-- bibliothèque matériel MPI +-- Dependencies: +-- +-- Revision: 25/juin/2012 au 24/Octobre/2012 +-- Revision 0.03 - File updated +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; + +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; +Library NocLib; +use NoCLib.CoreTypes.all; +use work.packet_type.all; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity EX4_FSM is + Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_En : in STD_LOGIC; + clk : in STD_LOGIC; + reset : in STD_LOGIC; + ResultOut : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); + Result_En : out STD_LOGIC:='0'; + NocSize : out STD_LOGIC_VECTOR(3 downto 0); + PortId : out STD_LOGIC_VECTOR(3 downto 0):=(others=>'0'); + AppRank : out STD_LOGIC_VECTOR(3 downto 0):=(others=>'0'); + AppSize : out STD_LOGIC_VECTOR(3 downto 0):=(others=>'0'); + IsMain : out STD_LOGIC:='0'; + Initialized : out STD_LOGIC:='0'; + dma_wr_req : out std_logic:='0'; + dma_wr_grant : in std_logic; + AdrRam : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); --accès au stockage + WeRam : out STD_LOGIC:='0'; --activation de l'écriture en RAM + DataRam : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'Z');--données des ports + AppAck : in STD_LOGIC; + AppReq : in STD_LOGIC; + port_in_cmd_en : out STD_LOGIC:='0'; + port_in_wr_en : out STD_LOGIC:='0'; + port_in_empty : in STD_LOGIC; + port_in_full : in STD_LOGIC; + port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'Z'); + port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); + port_out_rd_en : out STD_LOGIC:='0'; + port_out_data_available : in STD_LOGIC); +end EX4_FSM; + +architecture Behavioral of EX4_FSM is + + +Type Ar_MPIPort_In is array (positive range <>) of Typ_MPIPort_in; +Type Ar_MPIPort_out is array (positive range <>) of Typ_MPIPort_out; + + --MAE pour emission de init + --type init1_type is (init,NocSize,InitToNoc,NextPort,EndBCast); + -- MAE pour affectation des rangs aux différentes librairies MPI + type init2_type is (init,GetPortNum,DecodeData,IsPortZero,SeekMain1,SeekMain2,StoreMain,SetMainFlag,GetMainReq,StoreRank,NewRank,SendRank,RegRank,SendApp,EndInit); + -- MAE pour réception de init depuis le réseau; + type init3_type is (init,GetNocSize,ReadInitHead,StorePort,EndInit); + type typ_send is (s_init,s_head,s_len,s_len2,s_data,s_end); + type typ_receiv is (r_wait,r_dlen,r_drop,r_glen,r_data,r_pulse,r_end); + type typ_cmd is (cmdstart,cmdpost,cmdpostidle,cmdread,cmdlen,cmdglen,cmddata,cmdend,cmdtimeout); + + signal etsnd : typ_send; + signal etrec:typ_receiv; --pour la machine à état de réception + signal etcmd :typ_cmd; --pour la machine à état de commande +-- signal stInit1, next_stInit1 : init1_type; + signal stInit2, next_stInit2 : init2_type; + --signal stInit3, next_stInit3 : init3_type; + --signaux pour l'interface avec les ports + signal cport_in_wr_en,sport_in_wr_en:std_logic; + signal cport_out_rd_en,rport_out_rd_en:std_logic; + signal tosend,tosend4 :std_logic_vector(Word-1 downto 0); + signal selector : std_logic_vector (2 downto 0); -- pour le MUX des signaux vers le port + --signaux pour les états des MAE + signal NocSizeOk,PortCountFlag : std_logic; + signal PortNumFlag,EquFlag,MainResp,RankAsked,RankSent:std_logic; + + signal RTS_cmd,RTS_dat,CTR,BCast,Send_Ack,DS_Ack,CM_Ack:std_logic:='0'; + signal Rcv_On,Snd_On,Cmd_On : std_logic:='0'; --status des MAE d'envoie et de réception + signal DS_RDY ,BCast_Rdy,Send_RDY,CM_RDY:std_logic:='0'; + signal ExecTime_out:std_logic; + --signaux de gestion de la RAM + signal Ram_NextAdress : std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_BASE_ADR+CORE_Rank2port_BASE,16)); + signal Ram_NExtAdress_i :std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_BASE_ADR+CORE_Rank2port_BASE,16)); + --Signaux des résultats et de l'état + signal PortNum_i,MyPort : std_logic_vector(3 downto 0); -- + signal NocMax : std_logic_vector(3 downto 0); -- Nombre de ports du réseau -1 ? + signal MyRank : std_logic_vector(3 downto 0) ; --rang du PE + signal MainPort : std_logic_vector(3 downto 0) ; --Port de la lib main + signal NextRank : std_logic_vector(3 downto 0):=(others=>'0'); --utiliser pour gérer les affectations de rangs MPI + signal DataToSend : Typ_PortIo(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); -- permet d'empiler les données à envoyer + signal CmdReceived,DataReceived : Typ_PortIO(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); + signal Datalen : natural range 0 to 3 :=0; --indique la longueur des données + --other outputs + signal RankAsked_i,EquFlag_i,MainResp_i,RankSent_i,IsMain_i,Result_i:std_logic; + --signal BCast_Rdy_i : std_logic; + signal cdlen,dcount,timeout,timeout_i : natural range 0 to 255:=0; --longueur du paquet reçu par le process pcmd +begin +--======================================================================================= +--fonctions du module +--======================================================================================= +--======================================================================================= + + + + -- Gestion de l'initialisation du Core MPI + sync_Init2 : process (clk,reset) + begin + if reset='1' then + stinit2<=init; + elsif rising_edge(clk) then + stinit2<=next_stinit2; + --ajout des autres affectations ici + Ram_NextAdress<=Ram_NextAdress_i ; + MyPort<=PortNum_i; + RankAsked<=RankAsked_i; + RankSent<=RankSent_i; + AppRank<=MyRank; + timeout<=timeout_i; + + end if; +end process; + + Init2_DECODE: process (stinit2, CmdReceived, EquFlag, MyPort, DS_RDY, MainResp, DataReceived, Ram_NextAdress) + variable nextr,nextadr : natural :=to_integer(unsigned(Ram_NextAdress)); + begin + + Case stInit2 is + When Init => + RTS_cmd<='0'; + RTS_dat<='0'; + BCast<='0'; + Result_En<='0'; + Initialized<='0'; + CM_Ack <='0'; + CTR<='0' ; + DS_ACK<='0'; + Send_Ack<='0'; + WeRam<='0'; + ResultOut<=(others=>'0'); + PortNum_i<=(others=>'Z'); + IsMain<='0'; + EquFlag<='0'; + RankAsked_i<='0'; + dma_wr_req<='0'; + When GetPortNum => + RTS_cmd<='1'; + RTS_dat<='0'; + Result_En<='0'; + Initialized<='0'; + BCast<='0'; --réalise un envoie non collectif + CM_Ack<='0'; -- les données sont maintenant attendues + CTR<='0' ; + DataToSend(0)<=X"0" & GETPORTID; + DS_ACK<='0'; + Send_Ack<='0'; + WeRam<='0'; + IsMain<='0'; + ResultOut<=(others=>'0'); + PortNum_i<=(others=>'Z'); + RankAsked_i<='0'; + dma_wr_req<='0'; + When DecodeData => + EquFlag<=(All_zeros(Cmdreceived(2)(3 downto 0))); + RTS_cmd<='0'; + RTS_dat<='0'; + BCast<='0'; + IsMain<='0'; + Result_En<='0'; + Initialized<='0'; + CM_Ack <='1'; --les données ont été reçues + PortNum_i<=Cmdreceived(2)(3 downto 0); --récupère les valeurs de port + NocMax<=Cmdreceived(2)(7 downto 4); -- et la taille du réseau + PortNumFlag<='1'; -- le numéro du port est maintenant connu + CTR<='0' ; + DS_ACK<='0'; + Send_Ack<='0'; + WeRam<='0'; + RankAsked_i<='0'; + ResultOut<=(others=>'0'); + dma_wr_req<='0'; + When IsPortZero => --Ce port est-il le n° 0 du NoC ? + BCast<='0'; + Result_En<='0'; + Initialized<='0'; + RTS_cmd<='0'; + RTS_dat<='0'; + NextRank<="0001"; -- le prochain rang à affecter sera le n° 1 + nextr:=1; + IsMain<=EquFlag; + MyRank<="0000"; + MainPort<="0000"; + --MainAdr<="0000"; -- le port 0 est le main Lib par défaut; + CTR<='0' ; + DS_ACK<='0'; + WeRam<='0'; + RankAsked_i<='0'; + ResultOut<=(others=>'0'); + dma_wr_req<='0'; + When SeekMain1 => -- recherche de la lib main + RTS_cmd<='0'; + RTS_DAT<='1'; + CTR<='1' ; -- prêt à recevoir les données Clear To Receive + DS_ACK<='0'; --les données sont attendus + Send_Ack<=BCast_rdy; + DataToSend(0)<=INIT_SEEKMAIN & MyPort ; + DataToSend(1)<="00000011"; -- la longueur du packet =3 + DataToSend(2)<="0000" & MyPort; --propose sa propre adresse + DataLen<=3; + BCast<='1'; + IsMain<='0'; + Result_En<='0'; + Initialized<='0'; + WeRam<='0'; + ResultOut<=(others=>'0'); + EquFlag<='0'; + RankAsked_i<='0'; + dma_wr_req<='0'; + When SeekMain2 => -- recherche de la lib main + RTS_cmd<='0'; + RTS_DAT<='0'; + CTR<='1' ; -- prêt à recevoir les données Clear To Receive + DS_ACK<='0'; --les données sont attendus + Send_Ack<=BCast_rdy; +-- DataToSend(0)<=INIT_SEEKMAIN & MyPort ; +-- DataToSend(1)<="00000011"; -- la longueur du packet =3 +-- DataToSend(2)<="0000" & MyPort; --propose sa propre adresse +-- DataLen<=3; + BCast<='0'; + IsMain<='0'; + Result_En<='0'; + Initialized<='0'; + WeRam<='0'; + ResultOut<=(others=>'0'); + EquFlag<='0'; + RankAsked_i<='0'; + dma_wr_req<='0'; + When StoreMain => -- la Main Lib est une autre + BCAST<='0'; + Result_En<='0'; + IsMain<='0'; + Initialized<='0'; + DS_ACK<=DS_RDY; + Send_Ack<='0'; + RTS_cmd<='0'; + RTS_DAT<='0'; + CTR<=not(MainResp); -- essayer de recevoir tant que le main n'a pas répondu + WeRam<='1'; + ResultOut<=(others=>'0'); + RankAsked_i<='0'; + EquFlag<='0'; + AdrRam<= STD_logic_vector(to_unsigned(Core_init_adr+1,16)); + DataRam<=DataReceived(0)(3 downto 0)& DataReceived(2)(3 downto 0); --MainPort & MyRank + dma_wr_req<= '0'; ---pas très sûr + When SetMainFlag => -- Cette Lib est la Main Lib + if (Datareceived(0)(7 downto 4) = INIT_SEEKMAIN) then + RankAsked_i<='1'; + else + RankAsked_i<='0'; + end if; + RTS_cmd<='0'; + Initialized<='0'; + RTS_DAT<='0'; + BCast<='0'; + IsMain<='0'; + Result_En<='0'; + MyRank<="0000"; + MainPort<="0000"; + CTR<='1'; + DS_ACK<='0'; + WeRam<='1'; + ResultOut<=(others=>'0'); + EquFlag<='1'; + AdrRam<= STD_logic_vector(to_unsigned(Core_init_adr+1,16)); + DataRam<=(others =>'0'); -- le port vaut 0 et la mainlib est aussi à 0 + dma_wr_req<='1'; + When GetMainReq => + RankAsked_i<='1'; + WeRam<='0'; -- pas + BCast<='0'; + DS_ACK<='0'; + IsMain<='0'; + Result_En<='0'; + Initialized<='0'; + RTS_cmd<='0'; + RTS_DAT<='0'; + CTR<='1'; + ResultOut<=(others=>'0'); + PortNum_i<=DataReceived(0)(3 downto 0); -- le port qui demande un rang; + EquFlag<='1'; + dma_wr_req<='0'; + When NewRank => + nextr:=nextr+1; + NextAdr:=NextAdr+1; + --NextRank<=incr_vec(NextRank,'1'); + NextRank<=STD_logic_vector(to_unsigned(nextr,4)); + DataToSend(0)<=INIT_SETRANK & PortNum_i ; + DataToSend(1)<="00000011"; + DataToSend(2)<="0000" & NextRank; --ici c'est la valeur avant incrémentation ! + DataLen<=3; + BCast<='0'; + DS_ACK<='0'; + Result_En<='0'; + Initialized<='0'; + EquFlag<='1'; + RTS_cmd<='0'; + Rts_DAT<='1'; + IsMain<='0'; + CTR<='0' ; + WeRam<='0'; + RankAsked_i<='1'; + ResultOut<=(others=>'0'); + dma_wr_req<='0'; + When SendRank => + BCast<='0'; + Result_En<='0'; + EquFlag<='1'; + Rts_DAT<='1'; + RTS_cmd<='0'; + DS_ACK<='0'; + Send_Ack<=Send_Rdy; + IsMain<='0'; + CTR<='0' ; + WeRam<='0'; + ResultOut<=(others=>'0'); + RankAsked_i<='1'; + Initialized<='0'; + dma_wr_req<='0'; + When RegRank => + if (Datareceived(0)(7 downto 4) = INIT_SEEKMAIN) then + RankAsked_i<='1'; + else + RankAsked_i<='0'; + end if; + CTR<='0' ; + Result_En<='0'; + Initialized<='0'; + RTS_cmd<='0'; + DS_ACK<='0'; + Send_Ack<='0'; + IsMain<='0'; + Rts_Dat<='0'; + BCast<='0'; + EquFlag<='1'; + WeRam<='1'; + + Ram_NextAdress_i<= STD_logic_vector(to_unsigned(NextAdr,16)); --incr_vec(Ram_NextAdress,'1'); + AdrRam<=Ram_NextAdress; -- le rang qui a été envoyé; + DataRam<=DataToSend(2)(3 downto 0) & MyPort; + ResultOut<=(others=>'0'); + dma_wr_req<='1'; + When StoreRank => --le processus qui écoute le Port et qui + --stoke les adresses des autres bib va gérer le stockage du rang + BCAST<='0'; + DS_ACK<='1'; + Send_Ack<='0'; + RTS_cmd<='0'; + EquFlag<='0'; + RTS_DAT<='0'; + CTR<='0'; + Result_En<='0'; + Initialized<='0'; + IsMain<='0'; + + if ExecTime_out='1' then + MainPort<="0000"; + MyRank<=MyPort; + else + MainPort<=DataReceived(0)(3 downto 0); + MyRank<=DataReceived(2)(3 downto 0); + + end if; + WeRam<='1'; + --AdrRam<=DataReceived(2); -- le rang qui a été envoyé; + AdrRam<= STD_logic_vector(to_unsigned(Core_init_adr+1,16)); + DataRam<=DataReceived(0)(3 downto 0)& DataReceived(2)(3 downto 0); --MainPort & MyRank + ResultOut<=(others=>'0'); + RankAsked_i<='0'; + dma_wr_req<='1'; + When SendApp => --ajouter du code pour recevoir l'adr du reg status + Initialized<='1'; + ResultOut<="00000001"; -- Init Ok + Result_En<='1'; + IsMain<='0'; + PortId<=MyPort; + BCAST<='0'; + DS_ACK<='1'; + Send_Ack<='0'; + RTS_cmd<='0'; + RTS_DAT<='0'; + CTR<='0'; + WeRam<='0'; + RankAsked_i<='0'; + dma_wr_req<='0'; + When EndInit=> + RTS_cmd<='0'; + RTS_DAT<='0'; + Result_En<='0'; + IsMain<='0'; + Initialized<='0'; + DS_ACK<='0'; + Send_Ack<='0'; + BCAST<='0'; + CTR<='0'; + WeRam<='0'; + RankAsked_i<='0'; + ResultOut<=(others=>'0'); + dma_wr_req<='0'; + end case; + end process; + + NEXT_STInit2_DECODE: process (stInit2,AppReq, AppAck,PortNumFlag,EquFlag,MainResp,RankAsked,RankSent,CM_RDY, CmdReceived, BCast_Rdy, DS_RDY, DataReceived, Send_RDY,TimeOut,Dma_wr_grant) + variable InitTimeOut :natural:=0; + variable nulvect : std_logic_vector(3 downto 0):="0000"; + begin + --declare default state for next_state to avoid latches + next_stInit2 <= stInit2; --default is to stay in current state + --insert statements to decode next_state + --below is a simple example + case (stInit2) is + + + When Init =>If AppReq='1' then + If PortNumFlag='1' and RankAsked='1' then + Next_stInit2 <=GetMainReq; + else + Next_stInit2 <=GetPortNum; + end if; + TimeOut_i<=0; + end if; + + When GetPortNum => -- récupérer le numéro du port + + if CM_RDY='1' then + Next_stInit2 <=DecodeData; + end if; + + When DecodeData => -- cet état permet de lire les données reçues du port + --if CM_RDY='1' then + if ((Cmdreceived(2)(3 downto 0) or nulvect)=nulvect) then -- teste si le n° du port est zero + --EquFlag<='1'; + else + --EquFlag<='0'; + end if; + + Next_stInit2 <=IsPortZero; + --end if; + When IsPortZero => + if PortNumFlag='1' then + + End if; + if EquFlag='0' then --tester le numéro de port obtenu + Next_stInit2 <=SeekMain1; -- chercher le numéro de port sur le réseau + else + Next_stInit2<=SetMainFlag; -- enregistrer le numéro de port + End If; + TimeOut_i<=0; + + When SeekMain1 =>If BCast_RDY='1' then -- si tous les envois ont été postés + Next_stInit2<=SeekMain2; + End if; + When SeekMain2 => + If DS_RDY='1' then -- Si un jeu de données a été reçu + Next_stInit2 <=StoreMain; -- de la librairie pricipale + elsif ExecTime_Out='1' then + -- le Noc ne répond pas + -- affecter un numéro en raport avec le port + Next_stInit2 <=StoreMain; + else + Timeout_i<=TimeOut+1; + End if; + + if (Datareceived(0)(7 downto 4) = INIT_SETRANK) then + MainResp<='1'; + else + MainResp<='0'; + end if; + + When StoreMain => + if DataReceived(0)(7 downto 4)= MPI_INIT then + --ignorer le message + Next_stInit2 <=StoreMain; --essayer de recevoir le rang + elsif Datareceived(0)(7 downto 4) = INIT_SEEKMAIN then + -- ignorer ce message + Next_stInit2 <=StoreMain; --essayer de recevoir le rang + elsif Datareceived(0)(7 downto 4) = INIT_SETRANK then --ok le rang a été reçu + -- enregistrer le Main Adresse et les adresses des autres processus + -- dans la variable prévue à cet effet + --if dma_wr_grant='1' then + Next_stInit2 <=StoreRank; + --end if; + + end if; + + When StoreRank => + --il faut prévoir du code pour s'assurer que la RAM a bien enregistrer + -- la donnée ... + if dma_wr_grant = '1' then + Next_stInit2 <=SendApp; + else + Next_stInit2 <=StoreRank; + end if; + + When SetMainFlag => + if dma_wr_grant='1' then + if DS_RDY='1' then + + + Next_stInit2 <=GetMainReq; + elsif Timeout=240 then + Next_stInit2 <=SendApp; + else + TimeOut_i<=TimeOut+1; + end if; -- il est envisagée de terminer le programme à ce point + end if; + When GetMainReq => + + if RankAsked='1' then + Next_stInit2 <=NewRank; + else + Next_stInit2 <=SendApp; + end if; + When NewRank => + Next_stInit2 <=SendRank; + When SendRank => + if Send_RDY='1' then --RankSent + Next_stInit2 <=RegRank; + RankSent_i<='1'; -- le rang a été envoyé + TimeOut_i<=0; -- prépare le traitement de la prochaine requête + -- d'attente des ports + end if; + When RegRank => + --il faut prévoir du code pour s'assurer que la RAM a bien enregistrer + -- la donnée ... + if dma_wr_grant = '1' then + + + if DS_RDY='1' then + RankSent_i<='0'; + Next_stInit2 <=GetMainReq; + elsif Timeout=10 then + Next_stInit2 <=SendApp; + else + TimeOut_i<=TimeOut+1; + end if; -- il est envisagée + + end if; + When SendApp => -- envoyer au programme un signal + -- et attendre un acquittement et l'adresse de base + If AppAck='1' then + Next_stInit2 <=EndInit; + end if; + + + When EndInit=> + + + Next_stInit2<=Init; + end case; + end process; + +--================================================ +--sauvegarde du rang et du main port à l'adresse de retour de la fonction Init +--================================================== + +--==================================================== +--envoie des données sur le port +--=================================================== +selector<=(Rcv_on,Cmd_on,Snd_on); + +process (selector,Rport_out_rd_en,cport_out_rd_en,sPort_in_wr_en ,cPort_in_wr_en, + tosend ,tosend4) +begin + case selector is + + when "000" => port_in_data<=(others=>'Z'); + Port_in_wr_en<='0'; + Port_out_rd_en<='0'; + + when "001" => port_in_data<=tosend; --envoie de données + Port_in_wr_en<=sPort_in_wr_en ; + Port_out_rd_en<='0'; + when "101" => port_in_data<=tosend; --envoie de données + Port_in_wr_en<=sPort_in_wr_en ; + Port_out_rd_en<=Rport_out_rd_en ; + when "010" | "110" | "011" | "111" => + port_in_data<=tosend4; --envoie de commande GetPort + Port_in_wr_en<=cPort_in_wr_en; + Port_out_rd_en<=cport_out_rd_en; + + when "100" => port_in_data<=(others=>'Z'); -- réception de données + Port_in_wr_en<='0'; + Port_out_rd_en<=Rport_out_rd_en ; + + when others => port_in_data<=(others=>'Z'); + Port_in_wr_en<='0'; + Port_out_rd_en<='0'; + end case; +end process; + +--================================================== + + --=============================================================== + --processus d'accès au réseau + --=============================================================== + + + + + + preceiv:process(clk,reset) + + variable origport,destport : natural range 0 to 15; + variable dcount,dlen ,rtimeout:natural range 0 to 255; + variable ptype : std_logic_vector(3 downto 0); + begin +-- + if rising_edge(clk) then + if reset='1' then + etrec<=r_wait; + destport:=1; + rtimeout:=0; + else + case etrec is + when r_wait => + + rtimeout:=0; + + if Port_out_data_available='1' and CTR='1' then + ptype:=port_out_data(7 downto 4); + origport:=to_integer(unsigned(port_out_data(3 downto 0))); + + if ptype=MPI_INIT or ptype=INIT_SETRANK or ptype=INIT_SEEKMAIN then + etrec<=r_dlen; --identification de la signature d'en tête valide + Datareceived(0)<=Port_out_data; --stocker l'entête + else + --une donnée non attendue est présente sur le port + etrec<=r_drop; + end if; + --elsif Port_out_data_available='1' and CTR='0' then + -- etrec<=r_drop; + else + + etrec<=r_wait; + end if; + + When r_drop => -- ignorer les messages qui arrivent à ce noeud tant que + --l'application n'a pas été initialisée + if port_out_data_available='0' then + etrec<=r_end; + end if; + --Rport_out_rd_en<='1'; --lire les données qui sont dans le tampon de sortie + --DS_RDY<='0'; + when r_Dlen => --positionnement du mot de longueur des données + if Port_out_data_available ='1' then + + --Rport_out_rd_en<='1'; + etrec<=r_glen; + rtimeout:=0; + else + rtimeout:=rtimeout+1; + if rtimeout>=30 then + Exectime_out<='1'; --read Noc time out + etrec<=r_end; -- données pas prêtes + end if; + + + end if; + --DS_RDY<='0'; + -- + when r_glen => --lecture effective de la longueur des données + if port_out_data_available='1' then + dlen:=to_integer(unsigned(port_out_data(Word-1 downto 0))); + Datareceived(1)<=Port_out_data; + --RPort_out_rd_en<='0'; + etrec<=r_data; + dcount:=2; -- initialisation du compteur de reception (il y a + -- déjà deux mots reçues + else + rtimeout:=rtimeout+1; + if rtimeout>=30 then + ExecTime_out<='1'; + etrec<=r_end; -- données pas prêtes + end if; + + end if; + --DS_RDY<='0'; + when r_data => -- lecture des données + if port_out_data_available='1' then + + --Rport_out_rd_en<='1'; --autoriser la lecture + DataReceived(dcount)<=Port_out_data; --récupération des données + --assert true report "Donnée lue :"; --& string(unsigned(port4_out(Word-1 downto 0))) + --DS_RDY<='0'; + dcount:=dcount+1; + --severity note; + if dlen <=dcount then -- ce doit être égale ici et non <= ??? + etrec<=r_end; + --DS_RDY<='1'; -- jeu de données disponibles + elsif dcount=255 then --dépassement de la capacité + --DS_RDY<='0'; + etrec<=r_end; + end if; + else + rtimeout:=rtimeout+1; + if rtimeout>=30 then + ExecTime_out<='1'; + etrec<=r_end; -- données pas prêtes + end if; + --DS_RDY<='0'; + + end if; + when r_pulse => + etrec<=r_end; + when r_end => + + + + --rPort_out_rd_en <='0'; + + if DS_ACK='1' or rtimeout> 30 or CTR='0' then + --DS_RDY<='0'; + etrec<=r_wait; + end if; + + + + end case; + end if;--reset='1' + end if; + end process preceiv; + + val_preceiv: process (etrec) + begin + case etrec is + when r_wait => + DS_RDY<='0'; + + Rport_out_rd_en <='0'; + when r_dlen => + DS_RDY<='0'; + Rport_out_rd_en <='1'; + rcv_On<='1'; + when r_drop => + DS_RDY<='0'; + Rport_out_rd_en <='1'; + rcv_On<='1'; + when r_glen => + Rport_out_rd_en <='1'; + DS_RDY<='0'; + rcv_On<='1'; + when r_data => + Rport_out_rd_en <='1'; + DS_RDY<='0'; + rcv_On<='1'; + when r_pulse => + Rport_out_rd_en <='0'; + rcv_On<='1'; + DS_RDY<='1'; + when r_end => + Rport_out_rd_en <='0'; + DS_RDY<='1'; + rcv_On<='0'; + when others => + Rport_out_rd_en <='0'; + DS_RDY<='0'; + rcv_On<='0'; + end case; + end process; + + psend:process(clk,reset) + --génération des paquets à partir du port courant + variable pactype :natural range 0 to 15; + variable destport : natural range 0 to 15:=0; + variable realdlen, i,i_pair : natural range 0 to 255; + variable MaxPort : natural :=to_integer(unsigned(NOCMAX)); -- en fait ne doit pas être 0 + + + begin + if rising_edge(clk) then + if reset='1' then + etsnd<=s_init; + + + + else -- le process s'exécute sur chaque front + -- montant de l'horloge + case etsnd is + when s_init => tosend<=(others=>'Z'); + MaxPort :=to_integer(unsigned(NOCMAX)); + sPort_in_wr_en<='0'; + if port_in_full='0' and Rts_dat='1' then --on peut aussi tester si le port est vide + BCast_RDY<='0'; -- pas la fin de du Broadcasting + Send_RDY<='0'; + Snd_on<='1'; + if Bcast='1' then -- envoyer à tous les ports le même message ? + DestPort :=0; + else + DestPort:=to_integer(unsigned(DataToSend(0)(3 downto 0))); + end if; + etsnd<=s_head; + end if; + when s_head => -- construction et envoie de l'en-tête + Send_RDY<='0'; --l'envoi commence + BCast_RDY<='0'; + Snd_on<='1'; + --pactype:=to_integer(MPI_INIT);-- + pactype:=to_integer(unsigned(DataToSend(0)(7 downto 4))); + --realdlen:=to_integer(unsigned(Datalen)); + --? destport:=MAXPORT; -- le port de destination + + tosend <=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4)); + sPort_in_wr_en<='1'; -- + + i:=1; + etsnd<=s_len2; -- passer à l'état suivant + + when s_len => + BCast_RDY<='0'; + Send_RDY<='0'; + Snd_on<='1'; + --tosend<=(STD_LOGIC_VECTOR(to_unsigned(Realdlen,8))); + tosend<=DataToSend(1); + sPort_in_wr_en <='1'; + + + --port1_in<=tosend1; --copie directe sur le port + etsnd<=s_len2; + when s_len2 => + --tosend<=(STD_LOGIC_VECTOR(to_unsigned(realdlen,8))); + sPort_in_wr_en<='1'; + tosend<=DataToSend(1); + + --port1_in<=tosend1; --copie directe sur le port + etsnd<=s_data; + BCast_RDY<='0'; + Send_RDY<='0'; + Snd_on<='1'; + i:=i+1; + when s_data => + Snd_on<='1'; + if Port_in_full='0'and RTS_dat='1' then + sPort_in_wr_en<='1'; + + --envoie des données sur le port + tosend<=DataToSend(i); + + + if i+1>=datalen then + etsnd<=s_end; + Send_RDY<='1'; --l'envoi est terminé + if BCast='1' and destport=MAXPort then + BCAST_RDY<='1'; --l'envoi collectif aussi + else + BCast_RDY<='0'; + + end if; + else + BCast_RDY<='0'; + Send_RDY<='0'; + i:=i+1; + end if; + else + sPort_in_wr_en<='0'; + BCast_RDY<='0'; + Send_RDY<='0'; + end if; + when s_end => + tosend<=(others=>'Z'); + Send_RDY<='1'; + sPort_in_wr_en<='0'; + Snd_on<='0'; + if Bcast='1' then + DestPort:=Destport+1; + if DestPort<=MaxPort then + etsnd<=s_head; + else + BCast_RDY<='1' ; -- BroadCast End=Ok + if Send_ack='1' then + etsnd<=s_init; + end if; + end if; + else + BCast_RDY<='0'; + if Send_ack='1' then + etsnd<=s_init; + end if; + + end if; + end case; + + + end if; --reset ='1' + end if; --rising_edge... + end process psend; + +-- envoi des commandes +pcmd:process(clk,reset) + + variable origport,destport,pid,mport : natural range 0 to 15; + variable ctimeout:natural range 0 to 255; + begin + + if rising_edge(clk) then + if reset='1' then + etcmd<=cmdstart; + destport:=0; + ctimeout:=0; + origport:=1; + -- sorigport<=origport; + else + case etcmd is + when cmdstart => + if Port_in_empty='1' and RTS_Cmd='1' then + etcmd<=cmdpost; + + end if; + when cmdpost => + if Port_in_empty='1' then + etcmd<=cmdread; + end if; + + when cmdpostidle => --permet juste la prise en compte de la commande + etcmd<=cmdread; + dcount<=0;-- initialisation du compteur de reception + when cmdread => + + + ctimeout:=0; + + if Port_out_data_available='1' then + mport:=to_integer(unsigned(port_out_data(7 downto 4))); + pid:=to_integer(unsigned(port_out_data(3 downto 0)))+1; + CmdReceived(dcount)<=port_out_data; + --cdata_out_en(origport)<='1'; +-- if pid=origport then --le port a été bien identifié + etcmd<=cmdglen; -- + dcount<=dcount+1; +-- else +-- etcmd<=cmdtimeout; +-- end if; + else + + etcmd<=cmdread; + end if; + + + when cmdlen => --positionnement du mot de longueur des données + if Port_out_data_available='1' then + + etcmd<=cmdglen; + ctimeout:=0; + else + ctimeout:=ctimeout+1; + if ctimeout>=30 then + etcmd<=cmdtimeout; -- données pas prêtes + end if; + + + end if; + when cmdglen => --lecture effective de la longueur des données + if Port_out_data_available='1' then + cdlen<=to_integer(unsigned(port_out_data(Word-1 downto 0))); + CmdReceived(dcount)<=port_out_data; + etcmd<=cmddata; + dcount<=dcount+1; + else + ctimeout:=ctimeout+1; + if ctimeout>=30 then + --time_out(destport)<='1'; + etcmd<=cmdtimeout; -- données pas prêtes + end if; + + end if; + + when cmddata => + if (port_out_data_available='1' and ctimeout<30) then + + --cdata_out_en(origport)<='1'; + mport:=to_integer(unsigned(port_out_data(7 downto 4))); + --attention les ports sont numérotés à partir de 0 + pid:=to_integer(unsigned(port_out_data(3 downto 0)))+1; + CmdReceived(dcount)<=port_out_data; + if (dcount>=cdlen-1 ) then--attention le compteur de données commence à 0 + etcmd<=cmdend; + --CM_RDY<='1'; + else + dcount<=dcount+1; + end if; + Else + + if ctimeout>=30 then + --time_out(destport)<='1'; + etcmd<=cmdtimeout; -- données pas prêtes + else + ctimeout:=ctimeout+1; + etcmd<=cmdend; + end if; + end if; + when cmdend => + + etcmd<=cmdstart; + + when cmdtimeout => + + etcmd<=cmdstart; + end case; + --sorigport<=origport; + end if; --reset='1' + end if; + end process pcmd; + +majetcmd: process (etcmd,DataToSend, port_out_data_available, dcount,port_out_data) +variable origport : natural; +variable i:natural:=0; + begin + case etcmd is + when cmdstart => + i:=0; + Port_in_cmd_en<='0'; + tosend4<=(others=>'Z'); + cport_out_rd_en<='0'; + cport_in_wr_en<='0'; + CM_RDY<='0'; + Cmd_on<='0'; + when cmdpost | cmdpostidle => + cport_in_wr_en<='1'; + tosend4<=DataToSend(0); ---code pour getportid + Port_in_cmd_en<='1'; + cport_out_rd_en<='0'; + CM_RDY<='0'; + Cmd_on<='1'; + when cmdread => + tosend4<=(others=>'Z'); + cPort_in_wr_en<='0'; + cport_out_rd_en<=port_out_data_available; + --CmdReceived(dcount)<=port_out_data; --mettre les données dans le tampon + Port_in_cmd_en<='1'; + CM_RDY<='0'; + Cmd_on<='1'; + when cmdlen |cmdglen => --positionnement du mot de longueur des données + tosend4<=(others=>'Z'); + cport_in_wr_en<='0'; + cport_out_rd_en<=port_out_data_available; + Port_in_cmd_en<='1'; + --CmdReceived(dcount)<= port_out_data; + CM_RDY<='0'; + Cmd_on<='1'; + when cmddata => + tosend4<=(others=>'Z'); + cport_in_wr_en<='0'; + cport_out_rd_en<=Port_out_data_available; + Port_in_cmd_en<='1'; + --CmdReceived(dcount)<=port_out_data; --mettre les données dans le tampon + i:=i+1; + CM_RDY<='0'; + Cmd_on<='1'; + when cmdend => + tosend4<=(others=>'Z'); + cport_in_wr_en<='0'; + cport_out_rd_en<='0'; + --CmdReceived(dcount)<=port_out_data; + Port_in_cmd_en<='0'; + CM_RDY<='1'; + Cmd_on<='0'; + when cmdtimeout => + tosend4<=(others=>'Z'); + cport_in_wr_en<='0'; + cport_out_rd_en<='0'; + Port_in_cmd_en<='0'; + Cmd_on<='1'; + end case; + +end process majetcmd ; +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Ex0_FSM.v =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Ex0_FSM.v (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Ex0_FSM.v (revision 29) @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 05:17:03 03/06/2012 +// Design Name: +// Module Name: Ex0_FSM +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Ex0_FSM( + ); + + +endmodule Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Ex0_Fsm.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Ex0_Fsm.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Ex0_Fsm.vhd (revision 29) @@ -0,0 +1,206 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM +-- +-- Create Date: 05:37:34 03/06/2012 +-- Design Name: +-- Module Name: Ex0_Fsm - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Fournit le temps en µs depuis l'initialisation de la bibliothèque +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library NocLib ; + +--use NocLib.CoreTypes.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Ex0_Fsm is + Port ( Initialized : in STD_LOGIC; + + Instruction : in STD_LOGIC_VECTOR (7 downto 0); + instruction_en: in STD_LOGIC; --ceci n'est pas nécessaire dans ce module + -- car le module fonctionne en permanence. + clk : in STD_LOGIC; + reset : in STD_LOGIC; + ClkRate : in STD_LOGIC_VECTOR; --la fréquence de l'horloge en Mhz + uTimeResult : out STD_LOGIC_VECTOR; + TickResult : out STD_LOGIC_VECTOR; + OvFus : out STD_Logic:='0' + ); +end Ex0_Fsm; + +architecture Behavioral of Ex0_Fsm is + + --Use descriptive names for the states, like st1_reset, st2_search + type state_type is (Init,COunt,UsOut,OverFlow); + signal state, next_state : state_type; + --Declare internal signals for all outputs of the state-machine + signal Tick_Count: std_logic_vector(31 downto 0):=(others=>'0'); + signal Time_Ucount :std_logic_vector(31 downto 0):=(others=>'0'); + signal OvF,Ovf_us,ovF_i,zero :std_logic; -- overflow flag + signal ClkR_Count : std_logic_vector(ClkRate'high downto ClkRate'low):=(others=>'0'); + signal en : std_logic:='1'; + --other outputs +begin +utime_PROC: process (clk) + begin + if (rising_edge(clk)) then + if (reset = '1') or Initialized='0' then + state <= init; + -- Time_UCount<= (others=>'0'); + -- Tick_Count <=(others=>'0'); + else + state <= next_state; + TickResult<= Tick_Count; + uTimeResult <=Time_ucount; + OvF<=OvF_i; + OvfUs<=Ovf_us; + -- <= _i; + -- assign other outputs to internal signals + end if; + end if; + end process; + + --MOORE State-Machine - Outputs based on state only + OUTPUT_DECODE: process (state) + FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is + --this function increments a std_logic_vector type by '1' + VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE tb : std_logic_vector(s1'high downto s1'low); + BEGIN + tb(s1'low) := en; + V := s1; + for i in (V'low + 1) to V'high loop + tb(i) := V(i - 1) and tb(i -1); + end loop; + for i in V'low to V'high loop + if(tb(i) = '1') then + V(i) := not(V(i)); + end if; + end loop; + return V; + end incr_vec; -- end function + + +FUNCTION dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is + --this function decrements a std_logic_vector type by '1' + VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE tb : std_logic_vector(s1'high downto s1'low); + BEGIN + tb(s1'low) := not(en); + V := s1; + for i in (V'low + 1) to V'high loop + tb(i) := V(i - 1) or tb(i -1); + end loop; + for i in V'low to V'high loop + if(tb(i) = '0') then + V(i) := not(V(i)); + end if; + end loop; + return V; + end dcr_vec; -- end function +FUNCTION all_ones(s1:std_logic_vector) return std_logic is + --this function tells if all bits of a vector are '1' + --return value Z is '1', then vector has all 1 bits + --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE Z : std_logic; + BEGIN + Z := s1(s1'low); + FOR i IN (s1'low+1) to s1'high LOOP + Z := Z AND s1(i); + END LOOP; + RETURN Z; + END all_ones; -- end function +FUNCTION all_zeros(s1:std_logic_vector) return std_logic is + --this function tells if all bits of a vector are '0' + --return value Z if '1', then vector has all 0 bits + --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; + VARIABLE Z : std_logic; + BEGIN + Z := '0'; + FOR i IN (s1'low) to s1'high LOOP + Z := Z OR s1(i); + END LOOP; + RETURN not(Z); + END all_zeros; -- end function + + begin + --insert statements to decode internal output signals + --below is simple example + case state is + When Init => + Clkr_Count<=ClkRate; --initialiser le décompte + Time_uCount<=( others =>'0'); -- mettre à 0 le compteur des µS + Tick_Count<=(others =>'0'); --mettre à 0 les ticks + When Count => + Tick_count<=incr_vec(Tick_Count,en); + ClkR_Count<=dcr_vec(Clkr_Count,en); --compteur de µs + zero<=all_zeros(ClkR_Count); -- + OvF_i<=All_ones(Tick_count); -- + when UsOut => + Time_Ucount<=incr_vec(time_ucount,en); + Clkr_Count<=ClkRate; + Tick_count<=incr_vec(Tick_Count,en); + OvF_i<=All_ones(Tick_count); + zero<='0'; + OvF_us<=All_ones(Time_Ucount); + when OverFlow => + Tick_count<=incr_vec(Tick_Count,en); --compteur de tick + ClkR_Count<=dcr_vec(Clkr_Count,en); + OvF_us<=All_ones(Time_Ucount); + OvF_i<=All_ones(Tick_count); + end case; + end process; + + NEXT_STATE_DECODE: process (state, Initialized, zero, OvF) + begin + --declare default state for next_state to avoid latches + next_state <= state; --default is to stay in current state + --insert statements to decode next_state + --below is a simple example + case (state) is + when Init => + if Initialized = '1' then + + next_state <= count; + end if; + when Count => + if Zero = '0' then + next_state <= Count; + elsif Zero = '1' then + next_state <=Usout; + + end if; + when UsOut => + If OvF='0' then + next_state <= count; + elsif OvF='1' then + next_state <= OverFlow; + end if; + When OverFlow => + next_state<=Count; +-- when others => +-- next_state <= Init; + end case; + end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIFO_64_FWFT.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIFO_64_FWFT.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIFO_64_FWFT.vhd (revision 29) @@ -0,0 +1,223 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL/GAMOM +-- +-- Create Date: 19:51:54 04/19/2011 +-- Design Name: +-- Module Name: FIFO_64 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +--FIFO 64 Octets utisé pour les modules d'entrée +-- ce fifo est de type fwft first word falls throught ce qui +-- signifie que l'on a toujours la donnée au sommet de la pile en +-- sortie du fifo. +-- Dependencies: RAM_64.vhd +-- +-- Revision: 08-11-2012 +-- Revision 0.01 - File Created +-- Additional Comments: suppression du signal counter_en dans les expressions +-- 08/11/12 : prise en compte du retard de propagation des infos dans la FIFO. +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FIFO_64_FWFT is + Port ( clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR (Word-1 downto 0); + rd_en : in STD_LOGIC; + srst : in STD_LOGIC; + wr_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR (Word-1 downto 0); + empty : out STD_LOGIC; + full : out STD_LOGIC); +end FIFO_64_FWFT; + +architecture Behavioral of FIFO_64_FWFT is +-- declaration de la ram 64 octets +COMPONENT RAM_64 + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector(5 downto 0); + addrb : IN std_logic_vector(5 downto 0); + dia : IN std_logic_vector(Word-1 downto 0); + --doa : OUT std_logic_vector(Word-1 downto 0); + dob : OUT std_logic_vector(Word-1 downto 0) + ); + END COMPONENT; +type fsm_states is (state0, state1, state2);-- definition du type etat pour le codage des etats des fsm +signal fwft_fsm_state : fsm_states; +type ram_type is array (63 downto 0) of std_logic_vector (Word-1 downto 0); + signal RAM: ram_type; +-- declaration des signeaux des compteurs +signal push_address_counter : std_logic_vector(5 downto 0); +signal pop_address_counter : std_logic_vector(5 downto 0); +signal fifo_counter : std_logic_vector(5 downto 0); +--autre signaux +signal rd_ready : std_logic:='0'; +signal empty_signal : std_logic; +signal full_signal : std_logic; +signal wr_en_signal : std_logic; +signal rd_en_signal : std_logic; +signal clk_signal : std_logic; +signal dob_signal : std_logic_vector(Word-1 downto 0); +signal dout_signal : std_logic_vector(Word-1 downto 0); +signal doa_signal : std_logic_vector(Word-1 downto 0); +signal counter_en : std_logic; + +begin + +-- ram instantiation de la ram 64 octets du FIFO +--fifo_RAM_64: RAM_64 PORT MAP( +-- clka => clk_signal, +-- clkb => clk_signal, +-- wea => wr_en_signal, +-- ena => wr_en_signal, +-- enb => rd_en_signal, +-- addra => push_address_counter, +-- addrb => pop_address_counter, +-- dia => din, +-- --doa => doa_signal, +-- dob => dob_signal +-- ); +-- circuiterie des signaux de validation et d'etat du fifo +wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein +rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide +full_signal <= '1' when fifo_counter = "111111" else + '0'; +empty_signal <= '1' when rd_ready='0' or unsigned(fifo_counter) = 0 else + '0'; +clk_signal <= clk; +full <= full_signal; +empty <= empty_signal; + +-- sortie du fifo fwft +dout <= dout_signal; + +-- le processus des transistion +fwft_fsm_nsl : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + fwft_fsm_state <= state0; + else + case fwft_fsm_state is + when state0 => if wr_en_signal = '1' then --tampon vide seule l'écriture est possible + fwft_fsm_state <= state1; + end if; + + + when state1 => --if rd_en_signal = '1' and wr_en_signal='1' then --écriture seule dans le tampon + + fwft_fsm_state <= state2; + --end if; + + when state2 => if rd_en_signal = '1' and wr_en_signal='1' then + fwft_fsm_state <= state2; + elsif rd_en_signal='1' and wr_en_signal='0' and unsigned(fifo_counter) = 1 then --lecture avec écriture + fwft_fsm_state <= state0; + elsif unsigned(fifo_counter) = 0 then + fwft_fsm_state <= state0; + end if; + + when others => fwft_fsm_state <= state0; + end case; + end if; + end if; + end process; + -- actions associées à la fsm + -- mux qui oriente les sortie doa et dob vers out + val_fwft:process (fwft_fsm_state,dob_signal) + + begin + case fwft_fsm_state is + when state0 => + + dout_signal <= dob_signal; + counter_en <= '0'; + rd_ready <='0'; + when state1 => + + dout_signal <= dob_signal; + counter_en <= '1'; + rd_ready <='0'; + when state2 => + + dout_signal <= dob_signal; + counter_en <= '1'; + rd_ready <='1'; + when others => + dout_signal <= dob_signal; + counter_en <= '0'; + rd_ready <='0'; + end case; +end process; +doa_latch_process : process(clk) +begin + if rising_edge(clk) then + if wr_en_signal ='1' then + doa_signal <= din; + end if; + end if; +end process; + +-- processus de comptage des adresses d'empilement +push_process : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + push_address_counter <= (others =>'0'); + elsif wr_en_signal ='1' then + RAM(conv_integer(push_address_counter)) <=din; + push_address_counter <= push_address_counter +1; + end if; + end if; +end process; + + -- processus de comptage des adresses depilement du fifo +pop_process : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + pop_address_counter <= (others =>'0'); + elsif rd_en_signal ='1' then + pop_address_counter <= pop_address_counter +1; + end if; + end if; + end process; + dob_signal<=RAM(conv_integer(pop_address_counter)); + -- processus de comptage des octets dans le fifo + fifo_counter_process : process(clk) + variable count : std_logic_vector(5 downto 0):= (others=>'0'); +begin + if rising_edge(clk) then + if srst = '1' then + fifo_counter <= (others =>'0'); + count:=(others =>'0'); + else + if wr_en_signal ='1' and rd_en_signal ='0' then + count:=count+1; + end if; + if rd_en_signal ='1' and wr_en_signal ='0' and counter_en='1' then + count:=count-1; + end if; + fifo_counter<=count; + end if; + end if; +end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIFO_64_FWFT.vhi =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIFO_64_FWFT.vhi (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIFO_64_FWFT.vhi (revision 29) @@ -0,0 +1,33 @@ + +-- VHDL Instantiation Created from source file FIFO_64_FWFT.vhd -- 05:59:41 06/21/2011 +-- +-- Notes: +-- 1) This instantiation template has been automatically generated using types +-- std_logic and std_logic_vector for the ports of the instantiated module +-- 2) To use this template to instantiate this entity, cut-and-paste and then edit + + COMPONENT FIFO_64_FWFT + PORT( + clk : IN std_logic; + din : IN std_logic_vector(7 downto 0); + rd_en : IN std_logic; + srst : IN std_logic; + wr_en : IN std_logic; + dout : OUT std_logic_vector(7 downto 0); + empty : OUT std_logic; + full : OUT std_logic + ); + END COMPONENT; + + Inst_FIFO_64_FWFT: FIFO_64_FWFT PORT MAP( + clk => , + din => , + rd_en => , + srst => , + wr_en => , + dout => , + empty => , + full => + ); + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIFO_64_FWFT_new.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIFO_64_FWFT_new.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIFO_64_FWFT_new.vhd (revision 29) @@ -0,0 +1,212 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL/GAMOM +-- +-- Create Date: 19:51:54 04/19/2011 +-- Design Name: +-- Module Name: FIFO_64 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +--FIFO 64 Octets utisé pour les modules d'entrée +-- ce fifo est de type fwft first word falls throught ce qui +-- signifie que l'on a toujours la donnée au sommet de la pile en +-- sortie du fifo. +-- Dependencies: RAM_64.vhd +-- +-- Revision: 30-07-2012 +-- Revision 0.01 - File Created +-- Additional Comments: suppression du signal counter_en dans les expressions +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FIFO_64_FWFT is + Port ( clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR (Word-1 downto 0); + rd_en : in STD_LOGIC; + srst : in STD_LOGIC; + wr_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR (Word-1 downto 0); + empty : out STD_LOGIC; + full : out STD_LOGIC); +end FIFO_64_FWFT; + +architecture Behavioral of FIFO_64_FWFT is +-- declaration de la ram 64 octets +COMPONENT RAM_64 + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector(5 downto 0); + addrb : IN std_logic_vector(5 downto 0); + dia : IN std_logic_vector(Word-1 downto 0); + --doa : OUT std_logic_vector(Word-1 downto 0); + dob : OUT std_logic_vector(Word-1 downto 0) + ); + END COMPONENT; +type fsm_states is (state0, state1, state2);-- definition du type etat pour le codage des etats des fsm +signal fwft_fsm_state : fsm_states; +-- declaration des signeaux des compteurs +signal push_address_counter : std_logic_vector(5 downto 0); +signal pop_address_counter : std_logic_vector(5 downto 0); +signal fifo_counter : std_logic_vector(5 downto 0); +--autre signaux +signal rd_ready : std_logic:='0'; +signal empty_signal : std_logic; +signal full_signal : std_logic; +signal wr_en_signal : std_logic; +signal rd_en_signal : std_logic; +signal clk_signal : std_logic; +signal dob_signal : std_logic_vector(Word-1 downto 0); +signal dout_signal : std_logic_vector(Word-1 downto 0); +signal doa_signal : std_logic_vector(Word-1 downto 0); +signal counter_en : std_logic; + +begin + +-- ram instantiation de la ram 64 octets du FIFO +fifo_RAM_64: RAM_64 PORT MAP( + clka => clk_signal, + clkb => clk_signal, + wea => wr_en_signal, + ena => wr_en_signal, + enb => rd_en_signal, + addra => push_address_counter, + addrb => pop_address_counter, + dia => din, + --doa => doa_signal, + dob => dob_signal + ); +-- circuiterie des signaux de validation et d'etat du fifo +wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein +rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide +full_signal <= '1' when fifo_counter = "111111" else + '0'; +empty_signal <= '1' when rd_ready='0' and unsigned(fifo_counter) = 0 else + '0'; +clk_signal <= clk; +full <= full_signal; +empty <= empty_signal; + +-- sortie du fifo fwft +dout <= dout_signal; + +-- le processus des transistion +fwft_fsm_nsl : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + fwft_fsm_state <= state0; + else + case fwft_fsm_state is + when state0 => if wr_en_signal = '1' then --tampon vide seule l'écriture est possible + fwft_fsm_state <= state1; + end if; + + + when state1 => --if rd_en_signal = '1' and wr_en_signal='1' then --écriture seule dans le tampon + + fwft_fsm_state <= state2; + --end if; + + when state2 => if rd_en_signal = '1' and wr_en_signal='1' then + fwft_fsm_state <= state2; + elsif rd_en_signal='1' and wr_en_signal='0' and fifo_counter = "000001" then --lecture avec écriture + fwft_fsm_state <= state0; + elsif unsigned(fifo_counter) = 0 then + fwft_fsm_state <= state0; + end if; + + when others => fwft_fsm_state <= state0; + end case; + end if; + end if; + end process; + -- actions associées à la fsm + -- mux qui oriente les sortie doa et dob vers out + with fwft_fsm_state select + dout_signal <= dob_signal when state0, + doa_signal when state1, + dob_signal when state2, + doa_signal when others; + -- counter_en + with fwft_fsm_state select + counter_en <= '0' when state0, + '1' when state1, + '1' when state2, + '0' when others; + +with fwft_fsm_state select + rd_ready <= '0' when state0, + '0' when state1, + '1' when state2, + '0' when others; +doa_latch_process : process(clk) +begin + if rising_edge(clk) then + if wr_en_signal ='1' then + doa_signal <= din; + end if; + end if; +end process; + +-- processus de comptage des adresses d'empilement +push_process : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + push_address_counter <= (others =>'0'); + elsif wr_en_signal ='1' then + push_address_counter <= push_address_counter +1; + end if; + end if; +end process; + + -- processus de comptage des adresses depilement du fifo +pop_process : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + pop_address_counter <= (others =>'0'); + elsif rd_en_signal ='1' then + pop_address_counter <= pop_address_counter +1; + end if; + end if; + end process; + + -- processus de comptage des octets dans le fifo + fifo_counter_process : process(clk) + variable count : std_logic_vector(word-1 downto 0):= (others=>'0'); +begin + if rising_edge(clk) then + if srst = '1' then + fifo_counter <= (others =>'0'); + count:=(others =>'0'); + else + if wr_en_signal ='1' and rd_en_signal ='0' then + count:=count+1; + end if; + if rd_en_signal ='1' and wr_en_signal ='0' and counter_en='1' then + count:=count-1; + end if; + fifo_counter<=count; + end if; + end if; +end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIFO_64_FWFT_old.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIFO_64_FWFT_old.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIFO_64_FWFT_old.vhd (revision 29) @@ -0,0 +1,196 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL/GAMOM +-- +-- Create Date: 19:51:54 04/19/2011 +-- Design Name: +-- Module Name: FIFO_64 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +--FIFO 64 Octets utisé pour les modules d'entrée +-- ce fifo est de type fwft first word falls throught ce qui +-- signifie que l'on a toujours la donnée au sommet de la pile en +-- sortie du fifo. +-- Dependencies: RAM_64.vhd +-- +-- Revision: 30-07-2012 +-- Revision 0.01 - File Created +-- Additional Comments: suppression du signal counter_en dans les expressions +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FIFO_64_FWFT is + Port ( clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR (Word-1 downto 0); + rd_en : in STD_LOGIC; + srst : in STD_LOGIC; + wr_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR (Word-1 downto 0); + empty : out STD_LOGIC; + full : out STD_LOGIC); +end FIFO_64_FWFT; + +architecture Behavioral of FIFO_64_FWFT is +-- declaration de la ram 64 octets +COMPONENT RAM_64 + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector(5 downto 0); + addrb : IN std_logic_vector(5 downto 0); + dia : IN std_logic_vector(Word-1 downto 0); + --doa : OUT std_logic_vector(Word-1 downto 0); + dob : OUT std_logic_vector(Word-1 downto 0) + ); + END COMPONENT; +type fsm_states is (state0, state1, state2);-- definition du type etat pour le codage des etats des fsm +signal fwft_fsm_state : fsm_states; +-- declaration des signeaux des compteurs +signal push_address_counter : std_logic_vector(5 downto 0); +signal pop_address_counter : std_logic_vector(5 downto 0); +signal fifo_counter : std_logic_vector(5 downto 0); +--autre signaux +signal empty_signal : std_logic; +signal full_signal : std_logic; +signal wr_en_signal : std_logic; +signal rd_en_signal : std_logic; +signal clk_signal : std_logic; +signal dob_signal : std_logic_vector(Word-1 downto 0); +signal dout_signal : std_logic_vector(Word-1 downto 0); +signal doa_signal : std_logic_vector(Word-1 downto 0); +signal counter_en : std_logic; + +begin + +-- ram instantiation de la ram 64 octets du FIFO +fifo_RAM_64: RAM_64 PORT MAP( + clka => clk_signal, + clkb => clk_signal, + wea => wr_en_signal, + ena => wr_en_signal, + enb => rd_en_signal, + addra => push_address_counter, + addrb => pop_address_counter, + dia => din, + --doa => doa_signal, + dob => dob_signal + ); +-- circuiterie des signaux de validation et d'etat du fifo +wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein +rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide +full_signal <= '1' when fifo_counter = "111111" else + '0'; +empty_signal <= '1' when fifo_counter = "000000" else + '0'; +clk_signal <= clk; +full <= full_signal; +empty <= empty_signal; + +-- sortie du fifo fwft +dout <= dout_signal; + +-- le processus des transistion +fwft_fsm_nsl : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + fwft_fsm_state <= state0; + else + case fwft_fsm_state is + when state0 => if wr_en_signal = '1' then + fwft_fsm_state <= state1; + end if; + when state1 => if rd_en_signal = '1' then + fwft_fsm_state <= state2; + end if; + when state2 => if rd_en_signal='1' and fifo_counter = "000001" then --lecture avec écriture + fwft_fsm_state <= state0; + elsif fifo_counter = "000000" then + fwft_fsm_state <= state0; + end if; + + when others => fwft_fsm_state <= state0; + end case; + end if; + end if; + end process; + -- actions associées à la fsm + -- mux qui oriente les sortie doa et dob vers out + with fwft_fsm_state select + dout_signal <= dob_signal when state0, + doa_signal when state1, + dob_signal when state2, + doa_signal when others; + -- counter_en + with fwft_fsm_state select + counter_en <= '0' when state0, + '1' when state1, + '1' when state2, + '0' when others; +doa_latch_process : process(clk) +begin + if rising_edge(clk) then + if wr_en_signal ='1' then + doa_signal <= din; + end if; + end if; +end process; + +-- processus de comptage des adresses d'empilement +push_process : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + push_address_counter <= (others =>'0'); + elsif wr_en_signal ='1' then + push_address_counter <= push_address_counter +1; + end if; + end if; +end process; + + -- processus de comptage des adresses depilement du fifo +pop_process : process(clk) + begin + if rising_edge(clk) then + if srst = '1' then + pop_address_counter <= (others =>'0'); + elsif rd_en_signal ='1' then + pop_address_counter <= pop_address_counter +1; + end if; + end if; + end process; + + -- processus de comptage des octets dans le fifo + fifo_counter_process : process(clk) +begin + if rising_edge(clk) then + if srst = '1' then + fifo_counter <= (others =>'0'); + else + if wr_en_signal ='1' and rd_en_signal ='0' then --and counter_en='1' ??? + fifo_counter <= fifo_counter +1; + end if; + if rd_en_signal ='1' and wr_en_signal ='0' then + fifo_counter <= fifo_counter - 1; + end if; + end if; + end if; +end process; + +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIfo_mem.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIfo_mem.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIfo_mem.vhd (revision 29) @@ -0,0 +1,91 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04:35:05 10/15/2012 +-- Design Name: +-- Module Name: FIfo_mem - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +entity FIFO is + generic (N: integer := 6; -- number of address bits for 2**N address locations +M: integer := 8); -- number of data bits to/from FIFO + port (CLK, PUSH, POP, INIT: in std_logic; + DIN: in std_logic_vector(N-1 downto 0); +DOUT: out std_logic_vector(N-1 downto 0); + FULL, EMPTY, NOPUSH, NOPOP: out std_logic; + clk: IN std_logic; + + rd_en: IN std_logic; + srst: IN std_logic; + wr_en: IN std_logic; + + empty: OUT std_logic; + full: OUT std_logic); +end entity FIFO; +architecture TOP_HIER of FIFO is +signal WE: std_logic; +signal A: std_logic_vector(N-1 downto 0); +signal PUSH, POP, INIT: std_logic; + +signal NOPUSH, NOPOP: std_logic; + +component FIFO_LOGIC is + generic (N: integer); -- number of address bits + port (CLK, PUSH, POP, INIT: in std_logic; + ADD: out std_logic_vector(N-1 downto 0); + FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic); +end component FIFO_LOGIC; + +COMPONENT RAM_256 + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector(Word-1 downto 0); + addrb : IN std_logic_vector(Word-1 downto 0); + dia : IN std_logic_vector(Word-1 downto 0); + dob : OUT std_logic_vector(Word-1 downto 0) + ); +END COMPONENT; +begin +-- example of component instantiation using positional notation +FL: FIFO_LOGIC generic map (N) + port map (CLK, PUSH, POP, INIT, A, FULL, EMPTY, WE, NOPUSH, NOPOP); +Push<=wr_en; +pop<=rd_en; +nopush<=nopush; +nopop<=nopop; +init<=srst; +-- example of component instantiation using keyword notation +--R: RAM generic map (W => N, K => M) +-- port map (DIN => DIN, ADDR => A, WR => WE, DOUT => DOUT); +R: RAM_256 PORT MAP( + clka => clk, + clkb => clk, + wea => we, + ena => '1', + enb => '1', + addra => A, + addrb => A, + dia => din, + dob => dout + ); +end architecture TOP_HIER; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIfo_proc.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIfo_proc.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/FIfo_proc.vhd (revision 29) @@ -0,0 +1,102 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 04:35:05 10/15/2012 +-- Design Name: +-- Module Name: FIfo_mem - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +entity FIFO_LOGIC is + generic (N: integer := 3); + port (CLK, PUSH, POP, INIT: in std_logic; + ADD: out std_logic_vector(N-1 downto 0); + FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic); +end entity FIFO_LOGIC; +architecture RTL of FIFO_LOGIC is +signal WPTR, RPTR: std_logic_vector(N-1 downto 0); +signal LASTOP: std_logic; +begin +SYNC: process (CLK) begin + if (CLK'event and CLK = '1') then + if (INIT = '1') then -- initialization -- + WPTR <= (others => '0'); + RPTR <= (others => '0'); + LASTOP <= '0'; + elsif (POP = '1' and EMPTY = '0') then -- pop -- + RPTR <= RPTR + 1; + LASTOP <= '0'; + elsif (PUSH = '1' and FULL = '0') then -- push -- + WPTR <= WPTR + 1; + LASTOP <= '1'; + end if; -- otherwise all Fs hold their value -- + end if; +end process SYNC; +COMB: process (PUSH, POP, WPTR, RPTR, LASTOP, FULL, EMPTY) begin +-- full and empty flags -- + if (RPTR = WPTR) then + if (LASTOP = '1') then + FULL <= '1'; + EMPTY <= '0'; + else + FULL <= '0'; + EMPTY <= '1'; + end if; + else + FULL <= '0'; + EMPTY <= '0'; + end if; +-- address, write enable and nopush/nopop logic -- + if (POP = '0' and PUSH = '0') then -- no operation -- + ADD <= RPTR; + WE <= '0'; + NOPUSH <= '0'; + NOPOP <= '0'; + elsif (POP = '0' and PUSH = '1') then -- push only -- + ADD <= WPTR; + NOPOP <= '0'; + if (FULL = '0') then -- valid write condition -- + WE <= '1'; + NOPUSH <= '0'; + else -- no write condition -- + WE <= '0'; + NOPUSH <= '1'; + end if; + elsif (POP = '1' and PUSH = '0') then -- pop only -- + ADD <= RPTR; + NOPUSH <= '0'; + WE <= '0'; + if (EMPTY = '0') then -- valid read condition -- + NOPOP <= '0'; + else + NOPOP <= '1'; -- no red condition -- + end if; + else -- push and pop at same time - + if (EMPTY = '0') then -- valid pop -- + ADD <= RPTR; + WE <= '0'; + NOPUSH <= '1'; + NOPOP <= '0'; + else + ADD <= wptr; + WE <= '1'; + NOPUSH <= '0'; + NOPOP <= '1'; + end if; + end if; +end process COMB; +end architecture RTL; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPICORETEST.udo =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPICORETEST.udo (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPICORETEST.udo (revision 29) @@ -0,0 +1,10 @@ +###################################################################### +## +## Filename: MPICORETEST.udo +## Created on: Mon Oct 01 18:34:07 Paris, Madrid (heure d’été) 2012 +## +## Auto generated by Project Navigator for Post-Behavioral Simulation +## +## You may want to edit this file to control your simulation. +## +###################################################################### Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPICORETEST.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPICORETEST.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPICORETEST.vhd (revision 29) @@ -0,0 +1,702 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 01:27:32 04/20/2012 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/MPICORETEST.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: MPI_NOC +-- +-- Dependencies: +-- +-- Revision: 11 Juillet 2012 +-- Revision 0.01 - File Created +-- Additional Comments:Permet de tester le composant MPI +-- en simulant deux PE qui s'échangent des données. +-- Notes: +-- +-- +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +library NocLib ; +--use IEEE.STD_LOGIC_ARITH.ALL; +--use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +use work.MPI_RMA.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +USE ieee.numeric_std.ALL; + +ENTITY MPICORETEST IS +--port (clkm : in std_logic; +--reset : in std_logic; +--result : out std_logic_vector(Word-1 downto 0)); +END MPICORETEST; + +ARCHITECTURE behavior OF MPICORETEST IS +--constant WORD :positive:=8; +constant MEMSIZE:positive:=65535; + -- Components declaration + COMPONENT RAM_v + generic (width : positive;size :positive); + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector; + addrb : IN std_logic_vector; + dia : IN std_logic_vector; + dob : OUT std_logic_vector + ); + END COMPONENT; + + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT MPI_NOC + generic (NPROC : positive:=2); + PORT( + MPI_Node_in : IN Ar_MPIPort_in(1 to 2); + MPI_Node_Out : OUT Ar_MPIPort_out(1 to 2) + ); + END COMPONENT; + + constant clk_period : time := 10 ns; + +--===================signaux pour l'horloge ============================== +signal reset,clkm : std_logic := '0'; +--======================================================================== + --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0'; + signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic; + signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal PE_Instr_en : std_logic:='0'; + signal sram : typ_dpram; + signal pe_hold_ack,pe_hold_req : std_logic; + --signal pe_putadr:std_logic_vector(MEMSIZE-1 downto 0);-- adresse du bloc pour Put + --signal pe_getadr:std_logic_vector(MEMSIZE-1 downto 0);-- adresse du bloc pour get + signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée + signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO + signal Lib_Init : std_logic; -- l'initialisation est terminée + + --données du programme PE + signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0); + signal dpid,dpid_i : natural range 0 to 15:=1; + --Inputs + signal MPI_Node_in : Ar_MPIPort_in(1 to 2) ; +-- Port details +-- instruction : STD_LOGIC_VECTOR (Word -1 downto 0); +-- instruction_en : STD_LOGIC; +-- packet_ack : std_logic; +-- ram_data_in : STD_LOGIC_VECTOR (Word-1 downto 0); +-- clk : STD_LOGIC; +-- reset : STD_LOGIC; + --Outputs + signal MPI_Node_Out : Ar_MPIPort_out(1 to 2); +-- détails des champs de Typ_MPIPORT_Out +-- +-- +-- ram_we : STD_LOGIC; +-- ram_en : STD_LOGIC; +-- packet_received : STD_LOGIC; +-- barrier_completed : STD_LOGIC; +-- instruction_fifo_full : STD_LOGIC; +-- PushOut : STD_LOGIC_VECTOR (WORD-1 downto 0); +-- ram_data_out : STD_LOGIC_VECTOR (WORD-1 downto 0); +-- ram_address : STD_LOGIC_VECTOR (ADRLEN-1 downto 0); +-- +--end record; + -- + -- a + + + --signaux pour la gestion de la MAE + type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, + putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); +signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées +signal count,count_i : natural range 0 to 15:=0; + +--signal adresse,adresse_rd :natural range 0 to 65536; + + signal etPutGet : typ_mae; + signal Ram_busy :std_logic:='0'; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: MPI_NOC GENERIC MAP (NPROC=>2) + PORT MAP ( + MPI_Node_in => MPI_Node_in, + MPI_Node_Out => MPI_Node_Out + ); +Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN) + PORT MAP( + clka =>clkm, + clkb => clkm, + wea => ram_we, + ena => ram_ena, + enb => ram_enb, + addra => ram_addra, + addrb =>ram_addrb, + dia => ram_din, + dob => ram_do + ); + + --MUX de la RAM + + ram_addrb <= MPI_Node_out(1).ram_address_rd WHEN ramsel ='1' ELSE + pe_ram_addrb; + ram_addra <= MPI_Node_out(1).ram_address_wr WHEN ramsel ='1' ELSE + pe_ram_addra; + + +ram_ena <= MPI_Node_out(1).ram_en WHEN ramsel ='1' ELSE + pe_ram_ena; +ram_enb <= MPI_Node_out(1).ram_en WHEN ramsel ='1' ELSE + pe_ram_enb; +ram_ena <= MPI_Node_out(1).ram_en WHEN ramsel ='1' ELSE + pe_ram_ena; + +ram_we<= MPI_Node_out(1).ram_we WHEN ramsel ='1' ELSE + pe_ram_we; + +ram_din <= MPI_Node_out(1).ram_data_in WHEN ramsel ='1' ELSE + pe_ram_din; + + +MPI_Node_in(1).ram_data_out<=ram_do when ramsel='1' else (others=>'Z'); +pe_ram_do<=ram_do when ramsel='0' else (others=>'Z'); + + +pe_hold_req<=MPI_Node_out(1).hold_req; +MPI_Node_in(1).hold_ack<=pe_hold_ack; +MPI_Node_in(1).reset<=reset; +MPI_Node_in(1).clk<=clkm; +MPI_Node_in(1).instruction_en<=PE_instr_en; +MPI_Node_in(1).instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8)); + +Lib_Instr_ack<=MPI_Node_out(1).Pushout(0); --l'instruction a été copié +Lib_init<=MPI_Node_out(1).Pushout(4); -- Initialized +--============================================================= + -- Clock process definitions +--============================================================= + clk_process :process + begin + clkm <= '0' ; + wait for 10 ns;--clk_period/2; + clkm <= '1' ; + wait for 10 ns;--clk_period/2; + end process; + stim_proc: process + begin + -- hold reset state for 100 ns. + reset<='0'; + wait for 1 ns; + reset<='1'; + wait for clk_period*10; + reset<='0'; + wait; + + + end process; +--================================================================ +dpid<=dpid_i; + pPutGet:process(clkm) + + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout,dlen,ct : natural range 0 to 255; + variable adrToset : std_logic_vector(ADRLEN-1 downto 0); + variable iack : std_logic:='0'; + variable adresse,adresse_rd :natural range 0 to 65536; + + begin + + if (clkm'event and clkm='1') then + if reset='1' then + etputget<=start; + + + dcount<=0; + + else + + case etputget is + when start => + if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide + etputget<=Fillmem; + end if; + Ram_busy<='0'; + PE_Instr_En<='0'; + iack:='0'; + adresse:=256; + adresse_rd:=0; + timeout:=0; + dcount<=0; + when Fillmem => + if mpi_node_out(1).hold_req='0' then + + + + PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f"; + PE_Instr_En<='0'; + dcount<=dcount+1; + + if dcount=50 then + bfill:=bfill+1; + + if bfill=4 then + etputget<=InitApp; + else + etputget<=nextfill; + end if; + else + adresse:=adresse+1; + etputget<=Fillmem; + end if; + else -- attente de la libéraion de la mémoire + timeout:=timeout+1; + if timeout=100 then + etputget<=st_timeout; + end if; + + end if; + when nextfill => --prépare le prochain bloc mémoire qui sera rempli + adresse:=100*bfill; + dcount<=0; + etputget<=Fillmem; + PE_Instr_En<='0'; + when InitApp => + --code pour Init ici + --mettre mpi_init à l'adresse mpi + + PE_Ram_din<=MPI_INIT & x"0" ; + adresse:=core_init_adr; + + PE_Instr_En<='0'; + fsrc:=1; + adrToSet:=std_logic_vector(to_unsigned(core_init_adr,ADRLEN)); + if ret/=fsrc then + dcount<=0; + etputget<=writeptr; + adresse:=core_base_adr+2; + PE_Instr_En<='0'; + else + if Lib_instr_ack='1' then -- attente de la prise en compte de l'instruction + etputget<=InitCompleted; + PE_instr_en<='0'; + + else + PE_Instr_en<='1'; + end if; + + end if; + + when writeptr => + PE_Instr_En<='0'; + if PE_Hold_req = '0' then --s'assurer que le bus est disponible + + if dcount=0 then + PE_RAM_Din<=AdrToSet(Word-1 downto 0); + dcount <=dcount+1; + --adresse:=adresse+1; --prépare la prochaine écriture + elsif dcount=1 then + dcount <=dcount+1; + adresse:=adresse+1; --prépare la prochaine écriture + PE_RAM_Din<=AdrToSet(15 downto 8); + elsif dcount=2 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + ret:=fsrc; + dcount<=0; + timeout:=0; + + if fsrc=1 then + etputget <= InitApp; + elsif fsrc=2 then + etputget <= putdata; + elsif fsrc=3 then + etputget <= getdata; + else + etputget <= start; + end if; + + end if; + + end if; + When InstrCopy => + if Lib_instr_ack='1' then + etputget<=Writeptr; + PE_instr_en<='0'; + iack:='1'; + + else + PE_Instr_en<='1'; + end if; + + when InitCompleted => + + if Lib_Init='1' then + etputget<=putdata; + PE_Instr_En<='0'; + else + PE_Instr_En<='0'; + end if; + when putdata => --construire le packet pour le Put + DestRank:=1; + adresse_rd:=core_base_adr+Core_Rank2port_base+DestRank; + + PE_Instr_En<='0'; + timeout:=0; + dcount<=0; + fsrc:=2; + adrToSet:=std_logic_vector(to_unsigned(core_put_adr,ADRLEN)); + if ret/=fsrc then + adresse:=core_base_adr+2; + etputget<=writeptr; + ret:=0; + else + if Lib_instr_ack/='1' then + etputget<= putdata2; + end if; + end if; + + when putdata2 => + + if ramsel = '0' then --si le PE a accès à la RAM + dlen:=to_integer(unsigned(datalen)); + pMPI_put(clkm,destrank,SrcAdr1 & Srcadr0,DestAdr1 & DestAdr0,Dlen,sram,ct); + adresse:=to_integer(unsigned(sram.addr_wr)); + PE_ram_din<=sram.data_in; + dcount<=ct; + if dcount<=6 then +-- +-- PE_Instr_En<='0'; +-- if dcount=0 then +-- adresse:=core_put_adr; +-- PE_Ram_din<=MPI_PUT & std_logic_vector(to_unsigned(Dpid,4)); +-- elsif dcount=1 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=Datalen ; +-- elsif dcount=2 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=SrcAdr1 ; +-- elsif dcount=3 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=SrcAdr0 ; +-- elsif dcount=4 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=DestAdr1 ; +-- elsif dcount=5 then +-- adresse:=core_put_adr+dcount; +-- PE_Ram_din<=DestAdr0 ; + elsif dcount=7 then --juste après la valeur 6 en fait +-- adresse:=core_base_adr+1; +-- adresse_rd:=core_base_adr; +-- PE_Ram_din<=x"01"; --instruction pulse enable; + PE_Instr_En<='1'; +-- + end if; +-- dcount<=dcount+1; +-- end if; + elsif PE_instr_En='0' then + timeout:=timeout+1; + if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire + ram_busy<='1'; + timeout:=0; + PE_Instr_En<='0'; + end if; + end if; + if dcount >=6 then + Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI + if Lib_instr_ack='1' then -- Instruction ack + PE_Instr_En<='0'; + if Ramsel='0' then + adresse:=core_base_adr+1; + PE_Ram_din<=x"00"; --ramener le IPulse à 0; + Ram_busy<='0'; + etPutGet<=putcompleted; + else + + Ram_busy<='1'; --force la prise du bus + end if; + else + + timeout:=timeout+1; + if timeout=150 then + etputget<=st_timeout; + end if; + end if; + end if; + + + when putcompleted => + adresse_rd:=core_put_adr+6; + if PE_Ram_do(0)='1' then --Put completed + etPutGet<=GetData; + end if; + PE_Instr_En<='0'; + when getdata => --positionnement du mot de longueur des données + + DestRank:=1; + timeout:=0; + dcount<=0; + fsrc:=3; + adrToSet:=std_logic_vector(to_unsigned(core_get_adr,ADRLEN)); + if ret/=fsrc then + adresse:=core_base_adr+2; + etputget<=writeptr; + ret:=0; + else + adresse:=core_get_adr; + etputget<= getdata2; + end if; + PE_Instr_En<='0'; + when getdata2 => + + if ramsel='0' then + + pMPI_get(clkm,destrank,SrcAdr1 & Srcadr0,DestAdr1 & DestAdr0,Dlen,sram,ct); + adresse:=to_integer(unsigned(sram.addr_wr)); + PE_ram_din<=sram.data_in; + dcount<=ct; + if dcount<=6 then + +-- if dcount<=0 then +-- adresse:=core_get_adr; +-- PE_Ram_din<=MPI_GET & std_logic_vector(to_unsigned(Dpid,4)); +-- elsif dcount=1 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=Datalen ; +-- elsif dcount=2 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=SrcAdr1 ; +-- elsif dcount=3 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=SrcAdr0 ; +-- elsif dcount=4 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=DestAdr1 ; +-- elsif dcount=5 then +-- adresse:=core_get_adr+dcount; +-- PE_Ram_din<=DestAdr0 ; + + elsif dcount=7 then +-- adresse:=core_base_adr+1; + adresse_rd:=core_base_adr; + PE_Instr_En<='1'; +-- PE_Ram_din<=x"01"; --instruction pulse enable; + timeout:=0; + end if; +-- dcount<=dcount+1; +-- end if; + elsif PE_Instr_En='0'then + timeout:=timeout+1; + if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire + ram_busy<='1'; + timeout:=0; + PE_Instr_En<='0'; + end if; + end if; + + if dcount >=6 then + Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI + if Lib_instr_ack='1' then -- Instruction ack + PE_Instr_En<='0'; + if Ramsel='0' then + adresse:=core_base_adr+1; + PE_Ram_din<=x"00"; --ramener le IPulse à 0; + Ram_busy<='0'; + etPutGet<=getcompleted; + else + + Ram_busy<='1'; --force la prise du bus + end if; + else + + timeout:=timeout+1; + if timeout=150 then + etputget<=st_timeout; + end if; + end if; + + + end if; + + + + when getcompleted => + adresse_rd:=core_get_adr+6; + PE_Instr_En<='0'; + if PE_Ram_do(0)='1' then --Put completed + if Ramsel='0' then + adresse:=core_base_adr+1; + PE_Ram_din<=x"00"; --ramener le IPulse à 0; + etPutGet<=Terminate; + else + timeout:=timeout+1; + end if; + end if; + + + when terminate => + + + etputget<=start; + + when st_timeout => + + --if ram_busy='1' then + etputget<=start; + --end if + + etputget<=start; + end case; + pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,ADRLEN)); + pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,ADRLEN)); + end if; --reset='1' + end if; + end process pPutGet; + +majPutGet:process (etputget) + + begin + case etputget is + when start => + + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + when fillmem => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + when nextfill => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + when InitApp => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + when Initcompleted => + --PE_Instr_En<='1'; + when writeptr => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + -- dcount<=dcount+1; + + --PE_Instr_En<='0'; + when InstrCopy => --instruction copy + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + + + when putdata => --positionnement du mot de longueur des données + --dcount<=0; + srcadr0<=X"00"; + srcadr1<=X"01"; + destadr0<=X"00"; + destadr1<=X"02"; + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + --lecture du n° de port de destination + PE_Ram_enb<='1'; + datalen<=std_logic_vector(to_unsigned(50,8)); + dpid_i<=to_integer(unsigned(PE_ram_do(3 downto 0))); --le port est situé ur les 4 bits de poids faible + --PE_Instr_En<='0'; + when putdata2 => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + -- dcount<=dcount+1; + if dcount>=5 then + --PE_Instr_En<='1'; + else + --PE_Instr_En<='0'; + end if; + when putcompleted => + PE_Ram_we <='1'; + PE_Ram_ena <='1'; + -- lecture du résultat + PE_Ram_enb <='1'; + --PE_Instr_En<='1'; + when getdata => + --dcount<=0; + srcadr0<=X"00"; + srcadr1<=X"02"; + destadr0<=X"00"; + destadr1<=X"03"; + datalen<=std_logic_vector(to_unsigned(50,8)); + --PE_Instr_En<='0'; + when getdata2 => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + --dcount<=dcount+1; + if dcount=5 then + --PE_Instr_En<='1'; + else + --PE_Instr_En<='0'; + end if; + when getcompleted => + PE_Ram_we <='1'; + PE_Ram_ena <='1'; + -- lecture du résultat + PE_Ram_enb <='1'; + --PE_Instr_En<='1'; + when terminate => + + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + when st_timeout => + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + end case; + +end process majPutGet ; + + hold:process (pe_hold_req,clkm,reset) + begin + if rising_edge(clkm) then + if reset='1' then + pe_hold_ack<='0'; + else + if pe_hold_req='1' then + ramsel<=not(ram_busy); + pe_hold_ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération + else + pe_hold_ack<='0'; + ramsel<='0'; + end if; + end if; + end if; + end process hold; +END; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPICORETEST_envsettings.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPICORETEST_envsettings.html (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPICORETEST_envsettings.html (revision 29) @@ -0,0 +1,382 @@ +Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuildmappar
PATHEXT.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		< data not available >< data not available >< data not available >
Pathd:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
D:\Xilinx\12.3\ISE_DS\common\bin\nt64;
D:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\CMake 2.8\bin;
C:\qtsdk\mingw\bin;
C:\qtsdk\qtcreator\bin;
C:\Program Files (x86)\Graphviz 2.28\bin;
C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox		< data not available >< data not available >< data not available >
XILINXd:\Xilinx\12.3\ISE_DS\ISE\< data not available >< data not available >< data not available >
XILINX_DSPD:\Xilinx\12.3\ISE_DS\ISE< data not available >< data not available >< data not available >
XILINX_EDKD:\Xilinx\12.3\ISE_DS\EDK< data not available >< data not available >< data not available >
XILINX_PLANAHEADD:\Xilinx\12.3\ISE_DS\PlanAhead< data not available >< data not available >< data not available >
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn MPICORETEST.prj 
-ifmt mixedMIXED
-ofn MPICORETEST 
-ofmt NGCNGC
-p xc3s1200e-5-ft256 
-top MPICORETEST 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-iucUse synthesis Constraints FileNONO
-keep_hierarchyKeep HierarchySoftNO
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNO
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYES
-write_timing_constraintsWrite Timing ConstraintsNONO
-cross_clock_analysisCross Clock AnalysisNONO
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100%
-bram_utilization_ratioBRAM Utilization Ratio100100%
-verilog2001Verilog 2001YESYES
-fsm_extract YESYES
-fsm_encoding AutoAUTO
-safe_implementation NoNO
-fsm_style LUTLUT
-ram_extract YesYES
-ram_style AutoAUTO
-rom_extract YesYES
-shreg_extract YESYES
-rom_style AutoAUTO
-auto_bram_packing NONO
-resource_sharing YESYES
-async_to_sync NONO
-mult_style LUTAUTO
-iobuf YESYES
-max_fanout 100000500
-bufg 2424
-register_duplication YESYES
-register_balancing NoNO
-optimize_primitives NONO
-use_clock_enable YesYES
-use_sync_set YesYES
-use_sync_reset YesYES
-iob AutoAUTO
-equivalent_register_removal YESYES
-slice_utilization_ratio_maxmargin 50%
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHz<  data not available  ><  data not available  ><  data not available  >
HostGAMOM-PC<  data not available  ><  data not available  ><  data not available  >
OS NameMicrosoft <  data not available  ><  data not available  ><  data not available  >
OS ReleaseService Pack 1 (build 7601)<  data not available  ><  data not available  ><  data not available  >
+ Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPICORETEST_wave.fdo =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPICORETEST_wave.fdo (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPICORETEST_wave.fdo (revision 29) @@ -0,0 +1,11 @@ +###################################################################### +## +## Filename: MPICORETEST_wave.fdo +## Created on: Mon Oct 01 19:00:26 Paris, Madrid (heure d’été) 2012 +## +## Auto generated by Project Navigator for Post-Behavioral Simulation +## +## You may want to edit this file to control your simulation windows. +## +###################################################################### +add wave * Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_COMPONENTS.gise =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_COMPONENTS.gise (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_COMPONENTS.gise (revision 29) @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_COMPONENTS.xise =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_COMPONENTS.xise (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_COMPONENTS.xise (revision 29) @@ -0,0 +1,679 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER.vhd (revision 29) @@ -0,0 +1,135 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:16:03 06/13/2011 +-- Design Name: +-- Module Name: MPI_CORE_SCHEDULER - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity MPI_CORE_SCHEDULER is + Port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + priority_rotation : in STD_LOGIC; + instruction_fifo_empty : in STD_LOGIC; + instruction_fifo_data : in STD_LOGIC_VECTOR (7 downto 0); + instruction_available : out STD_LOGIC; + + get_request_fifo_data : in STD_LOGIC_VECTOR (7 downto 0); + get_request_fifo_empty : in STD_LOGIC; + instruction_fifo_rd_en : out STD_LOGIC; + get_request_fifo_rd_en : out STD_LOGIC; + + fifo_selected : out STD_LOGIC; + fifo_empty : out STD_LOGIC; + fifo_rd_en : in STD_LOGIC; + data_out : out STD_LOGIC_VECTOR (7 downto 0) + ); +end MPI_CORE_SCHEDULER; + +architecture Behavioral of MPI_CORE_SCHEDULER is + +signal sel_signal : std_logic; +-- declaration des composants du scheduler +COMPONENT DEMUX1 + PORT( + di : IN std_logic; + sel : IN std_logic; + do1 : OUT std_logic; + do2 : OUT std_logic + ); + END COMPONENT; + +COMPONENT MUX1 + PORT( + di1 : IN std_logic; + di2 : IN std_logic; + sel : IN std_logic; + do : OUT std_logic + ); + END COMPONENT; + +COMPONENT MUX8 + PORT( + di1 : IN std_logic_vector(7 downto 0); + di2 : IN std_logic_vector(7 downto 0); + sel : IN std_logic; + do : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + +COMPONENT round_robbin_machine + PORT( + get_request_fifo_empty : IN std_logic; + instruction_fifo_empty : IN std_logic; + priority_rotation : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + fifo_selected : OUT std_logic; + instruction_available : OUT std_logic; + mux_sel : OUT std_logic + ); +END COMPONENT; +begin +-- instances des composants + + +mpi_core_rr_machine: round_robbin_machine PORT MAP( + get_request_fifo_empty => get_request_fifo_empty, + instruction_fifo_empty => instruction_fifo_empty, + priority_rotation => priority_rotation , + clk => clk, + fifo_selected => fifo_selected, + instruction_available => instruction_available , + reset => reset, + mux_sel => sel_signal + ); + + +Fifo_empty_MUX: MUX1 PORT MAP( + di1 => instruction_fifo_empty , + di2 => get_request_fifo_empty, + do => fifo_empty, + sel => sel_signal + ); + + + +rd_en_demux: DEMUX1 PORT MAP( + di => fifo_rd_en , + sel => sel_signal, + do1 => instruction_fifo_rd_en, + do2 => get_request_fifo_rd_en + ); + +data_MUX8: MUX8 PORT MAP( + di1 => instruction_fifo_data , + di2 => get_request_fifo_data, + sel => sel_signal, + do => data_out + ); + + + +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER.vhi =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER.vhi (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER.vhi (revision 29) @@ -0,0 +1,45 @@ + +-- VHDL Instantiation Created from source file MPI_CORE_SCHEDULER.vhd -- 06:00:01 06/21/2011 +-- +-- Notes: +-- 1) This instantiation template has been automatically generated using types +-- std_logic and std_logic_vector for the ports of the instantiated module +-- 2) To use this template to instantiate this entity, cut-and-paste and then edit + + COMPONENT MPI_CORE_SCHEDULER + PORT( + clk : IN std_logic; + reset : IN std_logic; + priority_rotation : IN std_logic; + instruction_fifo_empty : IN std_logic; + get_request_fifo_empty : IN std_logic; + instruction_fifo_data : IN std_logic_vector(7 downto 0); + get_request_fifo_data : IN std_logic_vector(7 downto 0); + fifo_rd_en : IN std_logic; + instruction_fifo_rd_en : OUT std_logic; + get_request_fifo_rd_en : OUT std_logic; + fifo_selected : OUT std_logic; + instruction_available : OUT std_logic; + fifo_empty : OUT std_logic; + data_out : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + Inst_MPI_CORE_SCHEDULER: MPI_CORE_SCHEDULER PORT MAP( + clk => , + reset => , + priority_rotation => , + instruction_fifo_empty => , + get_request_fifo_empty => , + instruction_fifo_rd_en => , + get_request_fifo_rd_en => , + instruction_fifo_data => , + get_request_fifo_data => , + fifo_selected => , + instruction_available => , + fifo_empty => , + fifo_rd_en => , + data_out => + ); + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER_summary.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER_summary.html (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER_summary.html (revision 29) @@ -0,0 +1,73 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MPI_CORE_COMPONENTS Project Status
Project File:MPI_CORE_COMPONENTS.iseImplementation State:New
Module Name:MPI_CORE_SCHEDULER
  • Errors:
 
Target Device:xc3s1200e-4fg320
  • Warnings:
 
Product Version:ISE 11.1
  • Routing Results:
 + 
Design Goal:Balanced
  • Timing Constraints:
 
Design Strategy:Xilinx Default (unlocked)
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 06/16/2011 - 20:05:57
+ Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC.sym =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC.sym (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC.sym (revision 29) @@ -0,0 +1,17 @@ + + + BLOCK + 2012-7-12T10:22:56 + + + + + + + + + + + + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC.vhd (revision 29) @@ -0,0 +1,172 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:05:07 11/19/2011 +-- Design Name: +-- Module Name: MPI_NOC - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library NocLib ; + +use NocLib.CoreTypes.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity MPI_NOC is +generic (NPROC : positive:=2); + port( + + MPI_Node_in : in Ar_MPIPort_in(1 to NPROC); + MPI_Node_Out : out Ar_MPIPort_out(1 to NPROC) + ); +end MPI_NOC; + +architecture structural of MPI_NOC is +-- Declare signals for interconnections + +--constant NPROC : positive :=8 ; + --Inputs + signal noc_portOut :typ_portio(1 to NPROC); + signal noc_portIn :typ_portio(1 to NPROC); + + signal noc_fifo_in_full : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_data_available : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_fifo_in_empty : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_data_in_en : std_logic_vector(NPROC downto 1) := (others => '0'); + signal noc_cmd_in_en : std_logic_vector(NPROC downto 1) := (others => '0'); + signal noc_data_out_en : std_logic_vector(NPROC downto 1) := (others => '0'); + -- signal noc_clk : std_logic := '0'; + --signal noc_reset : std_logic := '0'; + +-- Declare components +COMPONENT SWITCH_GEN + GENERIC (number_of_ports : positive := NPROC); + PORT( + Port_in : IN typ_PortIO(1 to number_of_ports); + Port_out : OUT typ_PortIO(1 to number_of_ports); + data_in_en : IN std_logic_vector(NPROC downto 1); + cmd_in_en : IN std_logic_vector(NPROC downto 1); + data_out_en : IN std_logic_vector(NPROC downto 1); + fifo_in_full : OUT std_logic_vector(NPROC downto 1); + fifo_in_empty : OUT std_logic_vector(NPROC downto 1); + data_available : OUT std_logic_vector(NPROC downto 1); + clk : IN std_logic; + reset : IN std_logic + ); + END COMPONENT; + COMPONENT CORE_MPI is + Port ( instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + instruction_en : in STD_LOGIC; + + barrier_completed : out STD_LOGIC; + packet_received : out STD_LOGIC; + packet_ack : in std_logic; + PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); + ram_we : out STD_LOGIC; + hold_req : out STD_Logic; --requete vers application + hold_ack : in STD_Logic; --autorisation par l'application + ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_address_wr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); + ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_in_wr_en : out STD_LOGIC; -- OK (au switch) pour lire les données + switch_port_in_empty : in STD_LOGIC; + switch_port_in_cmd_en : out STD_LOGIC; + switch_port_in_full : in STD_LOGIC; -- port d'entréendu switch saturé + switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); -- port de donées d'entrée + switch_port_out_rd_en : out STD_LOGIC; -- OK (au switch) pour écrire les données + switch_port_out_data_vailaible : in STD_LOGIC; -- Donnée disponible à la sortie (du switch) + clk : in STD_LOGIC; + clkout : out std_logic; + reset : in STD_LOGIC; + ram_en : out STD_LOGIC; + instruction_fifo_full : out STD_LOGIC; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0)); + end COMPONENT; +-- cette fonction met en place l'architecture d'exécution de l'environnement +-- elle permet de construire le Noc et de connecter les différents core MPI +-- chaque core reçoit un ID qui sera son Rank lors de l'appel à MPI_GET_Rank +-- faut il créer une petite mémoire chargée de stocker les IDs ? +-- Oui car cette mémoire sera consultée par la fonction MPI_Init pour associer +-- un communicateur au MPI Core + + + + begin +Socsyst: if nproc > 1 generate --nproc + -- instancier le switch et connecter les différents ports + +switch_gen1: SWITCH_GEN generic map (NPROC) + PORT MAP ( + Port_in => Noc_PortIn, + + Port_out => noc_Portout, + + --signaux de contrôle de la lecture des ports + data_in_en => noc_data_in_en, + cmd_in_en => noc_cmd_in_en, + data_out_en => noc_data_out_en, + fifo_in_full => noc_fifo_in_full, + fifo_in_empty => noc_fifo_in_empty, + data_available => noc_data_available, + clk => MPI_Node_in(1).clk, + reset => MPI_Node_in(1).reset + ); + end generate; + connect_core: for i in 1 to nproc generate -- nproc + hardmpi:core_mpi port map ( + + + PushOut=>MPI_Node_out(i).PushOut, + ram_we=> MPI_Node_out(i).ram_we, + ram_en=>MPI_Node_out(i).ram_en , + hold_req=>MPI_NODE_out(i).hold_req, + packet_received=>MPI_Node_out(i).packet_received , + packet_ack=>MPI_Node_in(i).packet_ack, + hold_ack=>MPI_NODE_in(i).hold_ack, + ram_address_rd => MPI_Node_out(i).ram_address_rd , + ram_address_wr => MPI_Node_out(i).ram_address_wr , + ram_data_in=>MPI_Node_out(i).ram_data_in , + ram_data_out=>MPI_Node_in(i).ram_data_out, + barrier_completed =>MPI_Node_out(i).barrier_completed, + instruction => MPI_Node_in(i).instruction, + instruction_en => MPI_Node_in(i).instruction_en, + instruction_fifo_full =>MPI_Node_Out(i).instruction_fifo_full, + switch_port_in_wr_en => noc_data_in_en(i), + switch_port_in_cmd_en=>noc_cmd_in_en(i), + switch_port_in_full => noc_fifo_in_full(i), + switch_port_in_empty => noc_fifo_in_empty(i), + switch_port_in_data => noc_PortIn(i), + switch_port_out_rd_en => noc_data_out_en(i), + switch_port_out_data_vailaible => noc_data_available(i), + switch_port_out_data => noc_PortOut(i), + clk =>MPI_Node_in(1).clk, + reset =>MPI_Node_in(1).reset + + ); + end generate; + + + + +end Structural; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC_bitgen.xwbt =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC_bitgen.xwbt (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC_bitgen.xwbt (revision 29) @@ -0,0 +1,8 @@ +INTSTYLE=ise +INFILE=C:\Core MPI\CORE_MPI\MPI_NOC.ncd +OUTFILE=C:\Core MPI\CORE_MPI\MPI_NOC.bit +FAMILY=Spartan3E +PART=xc3s1200e-5ft256 +WORKINGDIR=C:\Core MPI\CORE_MPI +LICENSE=ISE +USER_INFO=No user information available. Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC_bld.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC_bld.html (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC_bld.html (revision 29) @@ -0,0 +1,1 @@ +Translation Report
Translation Report
Wed 25. Jul 19:31:37 2012


Release 12.3 ngdbuild M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

Command Line: d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -i -p xc3s1200e-ft256-5 MPI_NOC.ngc
MPI_NOC.ngd

Reading NGO file "C:/Core MPI/CORE_MPI/MPI_NOC.ngc" ...
Gathering constraint information from source properties...
Done.

Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'connect_core[2].hardmpi/MyRank<0>' has no
   driver
WARNING:NgdBuild:452 - logical net 'connect_core[2].hardmpi/MyRank<1>' has no
   driver
WARNING:NgdBuild:452 - logical net 'connect_core[2].hardmpi/MyRank<2>' has no
   driver
WARNING:NgdBuild:452 - logical net 'connect_core[2].hardmpi/MyRank<3>' has no
   driver
WARNING:NgdBuild:452 - logical net
   'connect_core[2].hardmpi/instruction_fifo2_full' has no driver
WARNING:NgdBuild:452 - logical net 'connect_core[2].hardmpi/packet_ack' has no
   driver
WARNING:NgdBuild:452 - logical net 'connect_core[1].hardmpi/MyRank<0>' has no
   driver
WARNING:NgdBuild:452 - logical net 'connect_core[1].hardmpi/MyRank<1>' has no
   driver
WARNING:NgdBuild:452 - logical net 'connect_core[1].hardmpi/MyRank<2>' has no
   driver
WARNING:NgdBuild:452 - logical net 'connect_core[1].hardmpi/MyRank<3>' has no
   driver
WARNING:NgdBuild:452 - logical net
   'connect_core[1].hardmpi/instruction_fifo2_full' has no driver
WARNING:NgdBuild:452 - logical net 'connect_core[1].hardmpi/packet_ack' has no
   driver

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  12

Total memory usage is 152844 kilobytes

Writing NGD file "MPI_NOC.ngd" ...
Total REAL time to NGDBUILD completion:  3 sec
Total CPU time to NGDBUILD completion:   2 sec

Writing NGDBUILD log file "MPI_NOC.bld"...
Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC_envsettings.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC_envsettings.html (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC_envsettings.html (revision 29) @@ -0,0 +1,382 @@ +Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuildmappar
PATHEXT.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		< data not available >< data not available >< data not available >
Pathd:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;
d:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;
D:\Xilinx\12.3\ISE_DS\PlanAhead\bin;
D:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;
D:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;
D:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;
D:\Xilinx\12.3\ISE_DS\common\bin\nt64;
D:\Xilinx\12.3\ISE_DS\common\lib\nt64;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files (x86)\Windows Live\Shared;
C:\Program Files (x86)\CMake 2.8\bin;
C:\qtsdk\mingw\bin;
C:\qtsdk\qtcreator\bin;
C:\Program Files (x86)\Graphviz 2.28\bin;
C:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
c:\altera\90sp1\quartus\bin;
C:\Program Files\Oracle\VirtualBox		< data not available >< data not available >< data not available >
XILINXd:\Xilinx\12.3\ISE_DS\ISE\< data not available >< data not available >< data not available >
XILINX_DSPD:\Xilinx\12.3\ISE_DS\ISE< data not available >< data not available >< data not available >
XILINX_EDKD:\Xilinx\12.3\ISE_DS\EDK< data not available >< data not available >< data not available >
XILINX_PLANAHEADD:\Xilinx\12.3\ISE_DS\PlanAhead< data not available >< data not available >< data not available >
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn MPI_NOC.prj 
-ifmt mixedMIXED
-ofn MPI_NOC 
-ofmt NGCNGC
-p xc3s1200e-5-ft256 
-top MPI_NOC 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-iucUse synthesis Constraints FileNONO
-keep_hierarchyKeep HierarchySoftNO
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNO
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYES
-write_timing_constraintsWrite Timing ConstraintsNONO
-cross_clock_analysisCross Clock AnalysisNONO
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100%
-bram_utilization_ratioBRAM Utilization Ratio100100%
-verilog2001Verilog 2001YESYES
-fsm_extract YESYES
-fsm_encoding AutoAUTO
-safe_implementation NoNO
-fsm_style LUTLUT
-ram_extract YesYES
-ram_style AutoAUTO
-rom_extract YesYES
-shreg_extract YESYES
-rom_style AutoAUTO
-auto_bram_packing NONO
-resource_sharing YESYES
-async_to_sync NONO
-mult_style LUTAUTO
-iobuf YESYES
-max_fanout 100000500
-bufg 2424
-register_duplication YESYES
-register_balancing NoNO
-optimize_primitives NONO
-use_clock_enable YesYES
-use_sync_set YesYES
-use_sync_reset YesYES
-iob AutoAUTO
-equivalent_register_removal YESYES
-slice_utilization_ratio_maxmargin 50%
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHz<  data not available  ><  data not available  ><  data not available  >
HostGAMOM-PC<  data not available  ><  data not available  ><  data not available  >
OS NameMicrosoft <  data not available  ><  data not available  ><  data not available  >
OS ReleaseService Pack 1 (build 7601)<  data not available  ><  data not available  ><  data not available  >
+ Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_PKG.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_PKG.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_PKG.vhd (revision 29) @@ -0,0 +1,127 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +Library NocLib; +use NocLib.CoreTypes.all; +package mpi_pkg is +-- Declare constants + +-- constant : time := ns; + constant NPROC : positive:= 8; + +-- type declaration +type portio is array(1 to NPROC) of std_logic_vector (Word-1 downto 0); +-- type is +-- record +-- : std_logic_vector( Word-1 downto 0); +-- : std_logic; +-- end record; + + +-- Declare signals for interconnections + + + --Inputs + signal noc_portOut :portio; + signal noc_portIn :portio; + + signal noc_fifo_in_full : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_data_available : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_fifo_in_empty : std_logic_vector(NPROC downto 1):= (others => '0'); + signal noc_data_in_en : std_logic_vector(NPROC downto 1) := (others => '0'); + signal noc_data_out_en : std_logic_vector(NPROC downto 1) := (others => '0'); + signal noc_clk : std_logic := '0'; + signal noc_reset : std_logic := '0'; + +-- Declare components +COMPONENT SWITCH_GENERIQUE + GENERIC (number_of_ports : positive := 8); + PORT( + Port1_in : IN std_logic_vector(Word-1 downto 0); + Port2_in : IN std_logic_vector(Word-1 downto 0); + Port3_in : IN std_logic_vector(Word-1 downto 0); + Port4_in : IN std_logic_vector(Word-1 downto 0); + Port5_in : IN std_logic_vector(Word-1 downto 0); + Port6_in : IN std_logic_vector(Word-1 downto 0); + Port7_in : IN std_logic_vector(Word-1 downto 0); + Port8_in : IN std_logic_vector(Word-1 downto 0); + Port9_in : IN std_logic_vector(Word-1 downto 0); + Port10_in : IN std_logic_vector(Word-1 downto 0); + Port11_in : IN std_logic_vector(Word-1 downto 0); + Port12_in : IN std_logic_vector(Word-1 downto 0); + Port13_in : IN std_logic_vector(Word-1 downto 0); + Port14_in : IN std_logic_vector(Word-1 downto 0); + Port15_in : IN std_logic_vector(Word-1 downto 0); + Port16_in : IN std_logic_vector(Word-1 downto 0); + Port1_out : OUT std_logic_vector(Word-1 downto 0); + Port2_out : OUT std_logic_vector(Word-1 downto 0); + Port3_out : OUT std_logic_vector(Word-1 downto 0); + Port4_out : OUT std_logic_vector(Word-1 downto 0); + Port5_out : OUT std_logic_vector(Word-1 downto 0); + Port6_out : OUT std_logic_vector(Word-1 downto 0); + Port7_out : OUT std_logic_vector(Word-1 downto 0); + Port8_out : OUT std_logic_vector(Word-1 downto 0); + Port9_out : OUT std_logic_vector(Word-1 downto 0); + Port10_out : OUT std_logic_vector(Word-1 downto 0); + Port11_out : OUT std_logic_vector(Word-1 downto 0); + Port12_out : OUT std_logic_vector(Word-1 downto 0); + Port13_out : OUT std_logic_vector(Word-1 downto 0); + Port14_out : OUT std_logic_vector(Word-1 downto 0); + Port15_out : OUT std_logic_vector(Word-1 downto 0); + Port16_out : OUT std_logic_vector(Word-1 downto 0); + data_in_en : IN std_logic_vector(8 downto 1); + data_out_en : IN std_logic_vector(8 downto 1); + fifo_in_full : OUT std_logic_vector(8 downto 1); + fifo_in_empty : OUT std_logic_vector(8 downto 1); + data_available : OUT std_logic_vector(8 downto 1); + clk : IN std_logic; + reset : IN std_logic + ); + END COMPONENT; + COMPONENT CORE_MPI is + Port ( instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); + instruction_en : in STD_LOGIC; + ram_data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); + barrier_completed : out STD_LOGIC; + packet_received : out STD_LOGIC; + packet_ack : in std_logic; + PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); + ram_we : out STD_LOGIC; + ram_address : out STD_LOGIC_VECTOR (15 downto 0); + ram_data_out : out STD_LOGIC_VECTOR (Word-1 downto 0); + switch_port_in_wr_en : out STD_LOGIC; -- OK (au switch) pour lire les données + switch_port_in_full : in STD_LOGIC; -- port d'entréendu switch saturé + switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0); -- port de donées d'entrée + switch_port_out_rd_en : out STD_LOGIC; -- OK (au switch) pour écrire les données + switch_port_out_data_vailaible : in STD_LOGIC; -- Donnée disponible à la sortie (du switch) + clk : in STD_LOGIC; + reset : in STD_LOGIC; + ram_en : out STD_LOGIC; + instruction_fifo_full : out STD_LOGIC; + switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0)); + end COMPONENT; +-- declare functions and procedure + +end MPI_PKG; + + +package body MPI_PKG is + +-- Example 1 + + + +-- cette fonction met en place l'architecture d'exécution de l'environnement +-- elle permet de construire le Noc et de connecter les différents core MPI +-- chaque core reçoit un ID qui sera son Rank lors de l'appel à MPI_GET_Rank +-- faut il créer une petite mémoire chargée de stocker les IDs ? +-- Oui car cette mémoire sera consultée par la fonction MPI_Init pour associer +-- un communicateur au MPI Core + + +end MPI_PKG; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_RMA.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_RMA.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_RMA.vhd (revision 29) @@ -0,0 +1,825 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +Library NocLib; +use NocLib.CoreTypes.all; +use work.PACKET_TYPE.all; + +package Mpi_Rma is +procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural; signal clkin:std_logic;signal SysRam :out typ_dpram); +procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram); +procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural); + +procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural); +procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector ); + +procedure pMPI_Win_create(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; + info:natural; comm:Mpi_Comm; Win: inout MPI_Win ); +-- declare functions and procedure + procedure ReadMem(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; data: out std_logic_vector); +procedure WriteMem(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; Data:in std_logic_vector); +end MPI_Rma; + + +package body MPI_Rma is +----int MPI_Put( +-- void *origin_addr, +-- int origin_count, +-- MPI_Datatype origin_datatype, +-- int target_rank, +-- MPI_Aint target_disp, +-- int target_count, +-- MPI_Datatype target_datatype, +-- MPI_Win win +--); +-- Example 1 +procedure pMPI_PUT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural) is +variable i,dcount : natural:=0; +variable adresse :natural; +variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr; +variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp; +variable put_adr : std_logic_vector (ADRLEN-1 downto 0); +variable config_reg: std_logic_vector (Word-1 downto 0); +constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0'); + begin + put_adr:=Std_logic_vector(to_unsigned(Core_put_adr,ADRLEN)); + + addr1:=Orig_Addr; + addr2:=Target_Disp; + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + end if; +-- + + if rising_edge(clkin) then + if dcount>=0 and dcount <=3 then + if interf.ramsel='0' then + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='0'; + WritePtr (put_adr,dcount,clkin,SysRam); + if dcount =4 then + -- fin de l'écriture du pointeur en mémoire + end if; + end if; + + elsif dcount=4 then + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='0'; + adresse:=core_put_adr; + sysRam.Data_in<=MPI_PUT & std_logic_vector(to_unsigned(Target_Rank,4)); --code fonction + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + elsif dcount=5 then + adresse:=core_put_adr+1; + sysRam.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + elsif dcount=6 then + adresse:=core_put_adr+2; + sysRam.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + elsif dcount=7 then + adresse:=core_put_adr+3; + sysRam.Data_in<=Addr1(Word-1 downto 0); --source Bas + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + elsif dcount=8 then + adresse:=core_put_adr+4; + sysRam.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + elsif dcount=9 then + adresse:=core_put_adr+5; + sysRam.Data_in<=Addr2(Word-1 downto 0); -- destination bas + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + elsif dcount=10 then + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='1'; + adresse:=core_base_adr+1; + SysRam.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + sysRam.Data_in<=x"01"; --instruction pulse enable via la mémoire; + Interf.Instr_En<='1'; --active la prise en compte de l'instruction + dcount:=dcount+1; + elsif dcount=11 then + if Interf.Instr_ack='1' then -- le Core a reçu l'instruction ? + Interf.Instr_En<='0'; --désactiver la prise en compte de l'instruction + dcount:=dcount+1; + config_reg:=SysRam.data_out and x"f6"; + SysRam.Data_in<=config_reg ; --ramener le IPulse à 0; + end if; + adresse:=core_base_adr+1; + SysRam.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + --SysRam.Ram_busy<='0'; --?? + SysRam.we<='0'; + SysRam.ena<='0'; -- préparer la lecture du résultat du Put + SysRam.enb<='1'; + elsif dcount=12 then + adresse:=core_base_adr+1; + SysRam.we<='1'; + SysRam.ena<='1'; -- préparer l'écriture du résultat du Put + SysRam.enb<='1'; + config_reg:=SysRam.data_out and x"f6"; + SysRam.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + SysRam.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=13 then + SysRam.we<='1'; + SysRam.ena<='1'; -- préparer l'écriture du résultat du Put + SysRam.enb<='0'; + config_reg:=SysRam.data_out and x"f6"; + SysRam.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + adresse:=core_base_adr+1; + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=14 then + SysRam.we<='0'; + SysRam.ena<='0'; + SysRam.enb<='1'; + if Interf.RamSel='0' then + SysRam.addr_rd<=Std_logic_vector(to_unsigned(Core_put_adr+6,Adrlen)); + if SysRam.Data_out(0)='1' then --fin du MPI PUT ici pour l'envoie ! + dcount:=dcount+1; + end if; + end if; + elsif dcount=15 then + dcount:=0; --fin normale de la fonction + end if; + + + NExtCtx:=dcount; + end if; + end procedure; + +procedure pMPI_GET(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram; + Orig_Addr: std_logic_vector;Orig_Count : natural; Orig_DataType: natural; + Target_Rank : natural; Target_disp : std_logic_vector; Target_Count : natural; + Target_Datatype :natural; Win : natural) is +variable i,dcount : natural:=0; +variable adresse :natural; +variable addr1 :std_logic_vector(Orig_Addr'length-1 downto 0):=Orig_Addr; +variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp; +variable get_adr : std_logic_vector (ADRLEN-1 downto 0); +variable config_reg: std_logic_vector (Word-1 downto 0); +constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0'); + begin + get_adr:=Std_logic_vector(to_unsigned(Core_get_adr,ADRLEN)); + + addr1:=Orig_Addr; + addr2:=Target_Disp; + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + end if; +-- + + if rising_edge(clkin) then + if dcount>=0 and dcount <=3 then + if interf.ramsel='0' then + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='0'; + WritePtr (get_adr,dcount,clkin,SysRam); + if dcount =4 then + -- fin de l'écriture du pointeur en mémoire + end if; + end if; + + elsif dcount=4 then + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='0'; + adresse:=core_get_adr; + sysRam.Data_in<=MPI_GET & std_logic_vector(to_unsigned(Target_Rank,4)); --code fonction + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + elsif dcount=5 then + adresse:=core_get_adr+1; + sysRam.Data_in<=std_logic_vector(to_unsigned(Orig_Count,8)) ;--la longueur + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + elsif dcount=6 then + adresse:=core_get_adr+2; + sysRam.Data_in<= Addr1(ADRLEN-1 downto Word) ; --source Haut + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + elsif dcount=7 then + adresse:=core_get_adr+3; + sysRam.Data_in<=Addr1(Word-1 downto 0); --source Bas + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + elsif dcount=8 then + adresse:=core_get_adr+4; + sysRam.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + elsif dcount=9 then + adresse:=core_get_adr+5; + sysRam.Data_in<=Addr2(Word-1 downto 0); -- destination bas + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + dcount:=dcount+1; + elsif dcount=10 then + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='1'; + adresse:=core_base_adr+1; + SysRam.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + sysRam.Data_in<=x"01"; --instruction pulse enable via la mémoire; + Interf.Instr_En<='1'; --active la prise en compte de l'instruction + dcount:=dcount+1; + elsif dcount=11 then + if Interf.Instr_ack='1' then -- le Core a reçu l'instruction ? + Interf.Instr_En<='0'; --désactiver la prise en compte de l'instruction + dcount:=dcount+1; + config_reg:=SysRam.data_out and x"f6"; + SysRam.Data_in<=config_reg ; --ramener le IPulse à 0; + end if; + adresse:=core_base_adr+1; + SysRam.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + SysRam.addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + --SysRam.Ram_busy<='0'; --?? + SysRam.we<='0'; + SysRam.ena<='0'; -- préparer la lecture du résultat du get + SysRam.enb<='1'; + elsif dcount=12 then + adresse:=core_base_adr+1; + SysRam.we<='1'; + SysRam.ena<='1'; -- préparer l'écriture du résultat du get + SysRam.enb<='1'; + config_reg:=SysRam.data_out and x"f6"; + SysRam.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + SysRam.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=13 then + SysRam.we<='1'; + SysRam.ena<='1'; -- préparer l'écriture du résultat du GET + SysRam.enb<='0'; + config_reg:=SysRam.data_out and x"f6"; + SysRam.Data_in<=config_reg ; --ramener le IPulse à 0; + dcount:=dcount+1; + adresse:=core_base_adr+1; + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=14 then + SysRam.we<='0'; + SysRam.ena<='0'; + SysRam.enb<='1'; + if Interf.RamSel='0' then + SysRam.addr_rd<=Std_logic_vector(to_unsigned(Core_get_adr+6,Adrlen)); + if SysRam.Data_out(0)='1' then --fin du MPI get ici pour l'envoie ! + dcount:=dcount+1; + end if; + end if; + elsif dcount=15 then + dcount:=0; --fin normale de la fonction + end if; + + + NExtCtx:=dcount; + end if; + end procedure; +Procedure pMPI_Comm_group(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; COMM :in MPI_Comm; signal grp : out Mpi_group ) is +Begin +--cette procédure permet de récupérer le groupe qui est associé à un communicateur +--dans notre cas c'est la récupération du groupe associé à COMM_WORLD +end procedure; +--int MPI_Group_incl(MPI_Group group, int n, int *ranks, +-- MPI_Group *newgroup) +Procedure pMPI_group_incl(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam : inout typ_dpram; + GRP: Mpi_group; n:natural;ranks :natural; newgroup: out Mpi_group) is +Begin +-- cette procedure a pour algo de parcourir les rangs qui sont dans la mémoire pointée par ranks +-- et d'activer l'un des bits de position de newgroup. +-- +-- +end procedure; + +procedure pMPI_Comm_Rank(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; COMM :in natural; signal Rank : out std_logic_vector ) is +variable adresse_rd : natural range 0 to 2**ADRLEN-1; + +begin + + if NextCtx =0 then + SysRam.we<='0'; + SysRam.ena<='0'; + SysRam.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + sysRam.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if Interf.Ramsel='0' then + NextCtx:=1; + end if; + elsif NextCtx=1 then + SysRam.we<='0'; + SysRam.ena<='0'; + SysRam.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + sysRam.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if Interf.Ramsel='0' then + Rank<=SysRam.Data_out(3 downto 0); + NextCtx:=2; + end if; + elsif NextCtx=2 then + SysRam.we<='0'; + SysRam.ena<='0'; + SysRam.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + sysRam.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if Interf.Ramsel='0' then + Rank<=SysRam.Data_out(3 downto 0); + NextCtx:=3; + end if; + elsif NextCtx=3 then + SysRam.we<='0'; + SysRam.ena<='0'; + SysRam.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + sysRam.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.ramsel='0' then + Rank<=SysRam.Data_out(3 downto 0); + NextCtx:=0; + end if; + end if; +end procedure; + +--int MPI_Win_create( +-- void *base, +-- MPI_Aint size, +-- int disp_unit, +-- MPI_Info info, +-- MPI_Comm comm, +-- MPI_Win *win +--); +procedure pMPI_Win_create(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; + info:natural; comm:Mpi_Comm; Win: inout MPI_Win ) is + -- parcours de la liste des fenêtres existantes à la recherche d'un emplacement libre + -- si fenêtre libre trouvée, et + -- mise à 1 du Bit WCreate du registre status + type wtype is array (1 to 4 ) of natural range 0 to 255; + variable AdrWin: std_logic_vector(ADRLEN-1 downto 0); + variable wcreate_adr : std_logic_vector(ADRLEN-1 downto 0):=std_logic_vector(to_unsigned(Core_wcreate_adr,ADRLEN)); + variable w0 : std_logic_vector(Word-1 downto 0); + variable count : natural range 0 to 255; + variable wdisp :wtype:=(4,14,24,34); --stocke l'adresse de la prochaine Win libre +begin +-- création d'une fenêtre il s'agit d'affecter l'objet Win et de retourner +-- le pointeur qui permet de le décrire + + +If NextCtx=0 then + NExtCtx:=NextCtx+1; + count:=0; + Interf.Intstate1<=count; +elsif NextCtx>=1 and NextCtx <= 4 then + count:=Interf.IntState1; + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(NextCtx),16)); + readmem(count,interf,sysRam,AdrWin,w0); + if count=0 then + if w0(0)/='1' then -- cette fenêtre est libre + NextCtx:=6; --étape de la création de la fenêtre + Win.addr:=base; --l'adresse de la fenêtre + Win.id:=NextCtx; -- la référence provisoire de la fenêtre + Win.size:=Size; -- la taille de la fenêtre + + else + NextCtx:=NextCtx+1; + end if; + end if; + Interf.intstate1<=count;--sauvegarde du statut de la sous-procédure + +elsif NextCtx=5 then + -- Plus de fenêtre disponible erreur + NextCtx:=1; -- boucle sans fin :) + Win.id:=0; + Win.addr:=x"0000"; +elsif NextCtx=6 then + --Affectation de l'objet Windows car une place est disponible + count<=Interf.intstate1; + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + Writemem(count,interf,SysRam,AdrWin,x"01"); --signal status pour created + Interf.intstate1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + +elsif NextCtx=8 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + interf.winid<=interf.winid+1; + count<=Interf.intstate1; + Writemem(count,interf,SysRam,AdrWin+1,interf.winid); --win id de la fenêtre + Interf.intstate1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=9 then + + + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + count<=Interf.intstate1; + Writemem(count,interf,SysRam,AdrWin+2,base(7 downto 0)); --adresse basse + Interf.intstate1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=10 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + count<=Interf.intstate1; + Writemem(count,interf,SysRam,AdrWin+3,base(15 downto 8)); --adresse haute + Interf.intstate1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=11 then + AdrWin:=std_logic_vector(to_unsigned(Core_base_adr+Wdisp(Win.id),16)); + sizewin:=std_logic_vector(to_unsigned(size,8)); + count<=Interf.intstate1; + Writemem(count,interf,SysRam,AdrWin+4,sizewin); -- taille de la fenêtre + Interf.intstate1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; +elsif NextCtx=12 then + --cette étape consiste à envoyer le message WINCREATE Sur le réseau et à récupérer + -- les informations donnant le numéro de la fenêtre + W0:=MPI_WCREATE & std_logic_vector(to_unsigned(0,4)); --code fonction + count<=Interf.intstate1; + Writemem(count,interf,SysRam,wcreate_adr,w0); + Interf.intstate1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + + elsif NextCtx=13 then + w0:=Win.Id; -- id proposé pour la fenêtre en création + count<=Interf.intstate1; + Writemem(count,interf,SysRam,wcreate_adr+1,w0); + Interf.intstate1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + elsif NextCtx=14 then + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='0'; + count<=Interf.intstate1; + if interf.Ramsel='0' then + WritePtr (wcreate_adr,count,clkin,SysRam); --écriture du pointeur d'instruction + Interf.intstate1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + end if; + elsif NextCtx=15 then + -- il faut mettre instruction_en à 1 + SysRam.we<='0'; + SysRam.ena<='0'; + SysRam.enb<='1'; + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='1'; + adresse:=stdlv(core_base_adr+1); + SysRam.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + sysRam.Data_in<=x"01"; --instruction pulse enable via la mémoire; + Writemem(count,interf,SysRam,adresse,x"01"); + Interf.intstate1<=count; + if count=0 then + NextCtx:=NextCtx+1; + end if; + Interf.Instr_En<='1'; + sysRam.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen)); + NextCtx:=NextCtx+1; + elsif NextCtx=16 then --acquittement de la copie des données dans le tampon de la lib + if Interf.Instr_ack='1' then + Interf.Instr_En<='0'; + NextCtx:=NextCtx+1; + end if; + SysRam.we<='0'; + SysRam.ena<='0'; + SysRam.enb<='1'; + elsif NextCtx=17 then + -- lecture du résultat de l'instruction + + +else + +end if; +end procedure; +--int MPI_Win_start( +-- MPI_Group group, +-- int assert, +-- MPI_Win win +--); +procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is +--cette fonction active les bits WStart pour chaque processus avec lequel +-- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à +--chacune de ces cibles + begin + + -- retour de l'adresse de de la fenêtre dans la structure Win + -- initialisation des bits concernant + + + + end procedure; +procedure pMPI_Win_complete( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is +begin + +end procedure; +procedure pMPI_Win_post( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win) is +--cette fonction active les bits WStart pour chaque processus avec lequel +-- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à +--chacune de ces cibles + begin + + end procedure; + + procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win) is +--permet de synchroniser la fin des opérations sur une fenêtre +begin + +end procedure; + + + Procedure pMPI_Finalize(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram) is + begin + + end procedure; + + +procedure pMPI_INIT(NextCtx : inout natural;signal Interf:inout Core_io;signal clkin:std_logic;signal SysRam :inout typ_dpram) is +variable i,dcount : natural:=0; +variable adresse :natural; +variable init_adr : std_logic_vector(adrlen-1 downto 0):=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN)); +begin + init_adr:=Std_logic_vector(to_unsigned(Core_init_adr,ADRLEN)); + if NextCtx =0 then + + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='0'; + if interf.ramsel='0' then + NextCtx:=1; + adresse:=core_init_adr; + sysRam.Data_in<=MPI_INIT & x"0" ; + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + + + Interf.Instr_En<='0'; + end if; + elsif NextCtx=1 then + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='0'; + if interf.ramsel='0' then + NextCtx:=2; + adresse:=core_init_adr; + sysRam.Data_in<=MPI_INIT & x"0" ; + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + Interf.Instr_En<='0'; + end if; + + elsif NextCtx=2 then + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='0'; + + sysRam.Data_in<=MPI_INIT & x"0" ; + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + NextCtx:=3; + elsif NextCtx=3 then + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='0'; + dcount:=1; + if interf.ramsel='0' then + sysRam.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,ADRLEN)); + WritePtr (init_adr,dcount,clkin,SysRam); + Interf.Instr_En<='0'; + --if dcount =0 then + NextCtx:=4; + --end if; + end if; + elsif NextCtx>=4 and NextCtx<=7 then + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='1'; + if interf.ramsel='0' then + dcount:=NextCtx-3; + WritePtr (init_adr,dcount,clkin,SysRam); + NextCtx:=NextCtx+1; + if dcount =4 then + NextCtx:=8; + end if; + end if; + elsif NextCtx=8 then --fin de la fonction + SysRam.we<='0'; + SysRam.ena<='0'; + SysRam.enb<='1'; + dcount:=0; + Interf.Instr_En<='1'; + sysRam.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen)); + NextCtx:=9; + elsif NextCtx=9 then --acquittement de la copie des données dans le tampon + if Interf.Instr_ack='1' then + Interf.Instr_En<='0'; + NextCtx:=10; + end if; + SysRam.we<='0'; + SysRam.ena<='0'; + SysRam.enb<='1'; + + elsif NextCtx=10 then --lecture de la fin de l'initialisation + SysRam.we<='0'; + SysRam.ena<='0'; + SysRam.enb<='1'; + if Interf.RamSel='0' then + SysRam.addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,Adrlen)); + if SysRam.Data_out(4)='1' then + NextCtx:=11; + end if; + end if; + elsif NextCtx =11 then + Interf.Instr_En<='0'; + SysRam.we<='0'; + SysRam.ena<='0'; + SysRam.enb<='0'; + NextCtx:=0; + end if; + + +end procedure; + + +procedure WriteMem(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; Data:in std_logic_vector) is +--cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + + if dcount=0 then + if Interf.RamSel='0' then + dcount :=dcount+1; + end if; + sysRam.Data_in<=AdrToSet(Word-1 downto 0); + sysRam.Addr_wr<=adrToSet; + elsif dcount=1 then + if Interf.RamSel='0' then + + dcount :=dcount+1; + end if; + sysRam.Data_in<=data; + sysRam.Addr_wr<=adrToSet; + elsif dcount=2 then + sysRam.Data_in<=data; + dcount :=dcount+1; + sysRam.Addr_wr<=AdrToSet; + elsif dcount=3 then + + dcount :=dcount+1; + sysRam.Addr_wr<=adrToSet; + sysRam.Data_in<=data; + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + sysRam.Addr_wr<=AdrToSet; + end if; + + NextCtx:=dcount; +end procedure; + +-- écriture dans la mémoire +procedure ReadMem(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; + AdrVect:in std_logic_vector; data: out std_logic_vector) is +--cette procédure permet d'écrire un mot dans la mémoire du PE(tâche matérielle) +--en ayant vérifié que le bus est bien disponible pour l'écriture + variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; + +begin + if NextCtx /=0 then --préserver la valeur de count entre les appels + dcount:=NextCtx; + else + + + end if; + + if dcount=0 then + if Interf.RamSel='0' then + dcount :=dcount+1; + end if; + + sysRam.Addr_rd<=adrToSet; + elsif dcount=1 then + data:=sysRam.Data_out; + dcount :=dcount+1; + sysRam.Addr_rd<=adrToSet; + elsif dcount=2 then + data:=sysRam.Data_out; + dcount :=dcount+1; + sysRam.Addr_rd<=adrToSet; + elsif dcount=3 then + if Interf.RamSel='0' then + dcount :=dcount+1; + sysRam.Addr_rd<=adrToSet; + data:=sysRam.Data_out; + end if; + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + + end if; + + NextCtx:=dcount; +end procedure; + + + + + + + + + + + + + + + + + +procedure WritePtr(AdrVect:in std_logic_vector; count: inout natural; signal clkin:std_logic;signal SysRam :out typ_dpram) is +--cette procédure permet d'écrire dans la mémoire du PE(tâche matérielle) +--les données de l'appel de la procédure +variable i,dcount : natural:=0; +variable adresse :natural; +variable AdrToSet :std_logic_vector(AdrVect'length-1 downto 0):=AdrVect; +begin + if count /=0 then --préserver la valeur de count entre les appels + dcount:=count; + else + + + end if; + adresse:=Core_base_adr+2; + + if dcount=0 then + sysRam.Data_in<=AdrToSet(Word-1 downto 0); + dcount :=dcount+1; + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=1 then + sysRam.Data_in<=AdrToSet(Word-1 downto 0); + dcount :=dcount+1; + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); + elsif dcount=2 then + sysRam.Data_in<=AdrToSet(ADRLEN-1 downto Word); + dcount :=dcount+1; + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + elsif dcount=3 then + dcount :=dcount+1; + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + sysRam.Data_in<=AdrToSet(ADRLEN-1 downto Word); + elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + dcount:=0; + sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse+1,ADRLEN)); + end if; + + count:=dcount; +end procedure; +end MPI_Rma; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPIenv.jhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPIenv.jhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPIenv.jhd (revision 29) @@ -0,0 +1,1 @@ +MODULE MPIenv Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPIenv.sch =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPIenv.sch (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPIenv.sch (revision 29) @@ -0,0 +1,12 @@ + + + + + + + + + + + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX1.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX1.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX1.vhd (revision 29) @@ -0,0 +1,46 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:18:52 06/13/2011 +-- Design Name: +-- Module Name: MUX1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity MUX1 is + Port ( di1 : in STD_LOGIC; + di2 : in STD_LOGIC; + do : out STD_LOGIC; + sel : in STD_LOGIC); +end MUX1; + +architecture Behavioral of MUX1 is + +begin + --modelisation d'un multiplexeur 1 bit + with sel select + do <= di1 when '0', + di2 when '1', + di1 when others; +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX1.vhi =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX1.vhi (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX1.vhi (revision 29) @@ -0,0 +1,25 @@ + +-- VHDL Instantiation Created from source file MUX1.vhd -- 12:17:39 06/13/2011 +-- +-- Notes: +-- 1) This instantiation template has been automatically generated using types +-- std_logic and std_logic_vector for the ports of the instantiated module +-- 2) To use this template to instantiate this entity, cut-and-paste and then edit + + COMPONENT MUX1 + PORT( + di1 : IN std_logic; + di2 : IN std_logic; + sel : IN std_logic; + do : OUT std_logic + ); + END COMPONENT; + + Inst_MUX1: MUX1 PORT MAP( + di1 => , + di2 => , + do => , + sel => + ); + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX1_summary.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX1_summary.html (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX1_summary.html (revision 29) @@ -0,0 +1,73 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MPI_CORE_COMPONENTS Project Status
Project File:MPI_CORE_COMPONENTS.iseImplementation State:New
Module Name:MUX1
  • Errors:
 
Target Device:xc3s1200e-4fg320
  • Warnings:
 
Product Version:ISE 11.1
  • Routing Results:
 + 
Design Goal:Balanced
  • Timing Constraints:
 
Design Strategy:Xilinx Default (unlocked)
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 06/13/2011 - 11:54:24
+ Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX8.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX8.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX8.vhd (revision 29) @@ -0,0 +1,45 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:30:26 06/13/2011 +-- Design Name: +-- Module Name: MUX8 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity MUX8 is + Port ( di1 : in STD_LOGIC_VECTOR (7 downto 0); + di2 : in STD_LOGIC_VECTOR (7 downto 0); + sel : in STD_LOGIC; + do : out STD_LOGIC_VECTOR (7 downto 0)); +end MUX8; + +architecture Behavioral of MUX8 is + +begin + with sel select + do <= di1 when '0', + di2 when '1', + di1 when others; +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX8.vhi =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX8.vhi (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX8.vhi (revision 29) @@ -0,0 +1,25 @@ + +-- VHDL Instantiation Created from source file MUX8.vhd -- 12:18:04 06/13/2011 +-- +-- Notes: +-- 1) This instantiation template has been automatically generated using types +-- std_logic and std_logic_vector for the ports of the instantiated module +-- 2) To use this template to instantiate this entity, cut-and-paste and then edit + + COMPONENT MUX8 + PORT( + di1 : IN std_logic_vector(7 downto 0); + di2 : IN std_logic_vector(7 downto 0); + sel : IN std_logic; + do : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + Inst_MUX8: MUX8 PORT MAP( + di1 => , + di2 => , + sel => , + do => + ); + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX8_summary.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX8_summary.html (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX8_summary.html (revision 29) @@ -0,0 +1,73 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MPI_CORE_COMPONENTS Project Status
Project File:MPI_CORE_COMPONENTS.iseImplementation State:New
Module Name:MUX8
  • Errors:
 
Target Device:xc3s1200e-4fg320
  • Warnings:
 
Product Version:ISE 11.1
  • Routing Results:
 + 
Design Goal:Balanced
  • Timing Constraints:
 
Design Strategy:Xilinx Default (unlocked)
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 06/13/2011 - 11:54:29
+ Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest.vhd (revision 29) @@ -0,0 +1,156 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM Roland Christian +-- +-- Create Date: 16:44:13 08/01/2012 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/MultiMPITest.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: MPI_NOC +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- +-- +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +library NocLib ; + +use NocLib.CoreTypes.all; +use work.Packet_type.all; + +USE ieee.numeric_std.ALL; + +ENTITY MultiMPITest IS +--port (clkm : in std_logic; +--reset : in std_logic; +--result : out std_logic_vector(Word-1 downto 0)); +END MultiMPITest; + +ARCHITECTURE behavior OF MultiMPITest IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT MPI_NOC + generic (NPROC: natural:=2); + PORT( + MPI_Node_in : IN Ar_MPIPort_in(1 to NPROC); + MPI_Node_Out : OUT Ar_MPIPort_out(1 to NPROC) + ); + END COMPONENT; + Component PE + generic(destid : natural); + Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : out STD_LOGIC; + Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_WE : in STD_LOGIC; + Core_RAM_EN : in STD_LOGIC; + --Core_RAM_ENB : in STD_LOGIC; + Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_Hold_req : in STD_LOGIC; + Core_Hold_Ack : out STD_LOGIC); +end Component; + + constant clk_period : time := 10 ns; + constant PROC : positive :=4; +--===================signaux pour l'horloge ============================== +signal reset,clkm : std_logic := '0'; +--======================================================================== + --signaux pour la gestion de la MAE + type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, + putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); +signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées +signal count,count_i : natural range 0 to 15:=0; + +signal MPI_Node_in : Ar_MPIPort_in(1 to PROC) ; +signal MPI_Node_Out : Ar_MPIPort_out(1 to PROC); + + + + +BEGIN + uut: MPI_NOC GENERIC MAP (NPROC=>PROC) + PORT MAP ( + MPI_Node_in => MPI_Node_in, + MPI_Node_Out => MPI_Node_Out + ); + +PE1: PE generic map (DestId=>1) +Port Map ( +Instruction => MPi_Node_in(1).Instruction, + Instruction_en => MPi_Node_in(1).Instruction_en, + Core_PushOut => MPi_Node_out(1).PushOut, + clk =>clkm, + reset =>reset, + Core_RAM_Data_Out =>MPi_Node_in(1).Ram_Data_out, + Core_RAM_Data_IN => MPI_Node_out(1).ram_data_in, + Core_RAM_WE => MPI_Node_out(1).ram_we, + Core_RAM_EN => MPI_Node_out(1).ram_en, + -- Core_RAM_ENB => MPI_Node_out(1).ram_en, + Core_RAM_Address_Wr => MPI_Node_out(1).ram_address_wr, + Core_RAM_Address_Rd => MPI_Node_out(1).ram_address_rd, + Core_Hold_req => MPI_Node_out(1).hold_req, + Core_Hold_Ack => MPI_Node_in(1).hold_ack +); + +PE2: PE Generic map (DestId=>0) + Port Map ( + Instruction => MPi_Node_in(2).Instruction, + Instruction_en => MPi_Node_in(2).Instruction_en, + Core_PushOut => MPi_Node_out(2).PushOut, + clk =>clkm, + reset =>reset, + Core_RAM_Data_Out =>MPi_Node_in(2).Ram_Data_out, + Core_RAM_Data_IN => MPI_Node_out(2).ram_data_in, + Core_RAM_WE => MPI_Node_out(2).ram_we, + Core_RAM_EN => MPI_Node_out(2).ram_en, + --Core_RAM_ENB => MPI_Node_out(2).ram_en, + Core_RAM_Address_Wr => MPI_Node_out(2).ram_address_wr, + Core_RAM_Address_Rd => MPI_Node_out(2).ram_address_rd, + Core_Hold_req => MPI_Node_out(2).hold_req, + Core_Hold_Ack => MPI_Node_in(2).hold_ack +); +MPI_Node_in(1).reset<=reset; +MPI_Node_in(1).clk<=clkm; +MPI_Node_in(2).reset<=reset; +MPI_Node_in(2).clk<=clkm; +--Result<=MPi_Node_out(1).PushOut; +--============================================================= + -- Clock process definitions +--============================================================= + clk_process :process + begin + clkm <= '0' ; + wait for clk_period/2; + clkm <= '1' ; + wait for clk_period/2; + end process; + stim_proc: process + begin + -- hold reset state for 100 ns. + reset<='0'; + wait for 1 ns; + reset<='1'; + wait for clk_period*10; + reset<='0'; + wait; + + + end process; +--================================================================ +END; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest_summary.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest_summary.html (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest_summary.html (revision 29) @@ -0,0 +1,91 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MultiMPITest Project Status
Project File:MPI_CORE_COMPONENTS.xiseParser Errors:X 2 Errors
Module Name:MultiMPITestImplementation State:New
Target Device:xc6slx100-3fgg484
  • Errors:
 
Product Version:ISE 12.3
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
+ + + + 
+ + +
Current Warnings [-]
No Warnings Found
+ + + + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + + + + +
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentTue 27. Nov 11:49:23 2012
WebTalk ReportCurrentFri 17. Aug 16:33:25 2012
WebTalk Log FileCurrentFri 17. Aug 16:33:28 2012
+ + +
Date Generated: 11/29/2012 - 18:29:00
+ Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiTest.wcfg =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiTest.wcfg (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiTest.wcfg (revision 29) @@ -0,0 +1,316 @@ + + + + + + + + + + + + + + + + + + + + + reset + reset + + + mpi_node_in[1:4] + mpi_node_in[1:4] + HEXRADIX + + + mpi_node_out[1:4] + mpi_node_out[1:4] + HEXRADIX + + + cm_rdy + cm_rdy + + + core_ram_address_rd[15:0] + core_ram_address_rd[15:0] + + + ram_din[7:0] + ram_din[7:0] + + + ram_addra[15:0] + ram_addra[15:0] + + + ram_addrb[15:0] + ram_addrb[15:0] + + + pe_ram_do[7:0] + pe_ram_do[7:0] + + + etcmd + etcmd + + + cm_rdy + cm_rdy + + + stinit2 + stinit2 + + + stinit2 + stinit2 + + + ds_rdy + ds_rdy + + + runstate + runstate + + + runstate + runstate + + + ram_address_rd[15:0] + ram_address_rd[15:0] + + + ram_data[7:0] + ram_data[7:0] + + + fifo_wr_i + fifo_wr_i + + + count + count + + + count + count + + + fifo_din_i[7:0] + fifo_din_i[7:0] + + + fifo_wr_i + fifo_wr_i + + + ram_address_i[15:0] + ram_address_i[15:0] + + + ram_data[7:0] + ram_data[7:0] + + + port_in_data[7:0] + port_in_data[7:0] + + + pe_ram_addra[15:0] + pe_ram_addra[15:0] + + + pe_ram_din[7:0] + pe_ram_din[7:0] + + + pe_ram_din[7:0] + pe_ram_din[7:0] + + + tosend[7:0] + tosend[7:0] + + + clkm + clkm + + + port_out_data[7:0] + port_out_data[7:0] + + + etrec + etrec + + + empty_signal + empty_signal + + + pop_state + pop_state + + + etcmd + etcmd + + + switch_port_in_wr_en + switch_port_in_wr_en + + + switch_port_in_data[7:0] + switch_port_in_data[7:0] + + + ram_data_in[7:0] + ram_data_in[7:0] + + + ram_data_out[7:0] + ram_data_out[7:0] + + + ram_address[15:0] + ram_address[15:0] + + + switch_port_out_data[7:0] + switch_port_out_data[7:0] + + + ram_address[15:0] + ram_address[15:0] + + + data_to_send[7:0] + data_to_send[7:0] + + + packet_length[7:0] + packet_length[7:0] + + + ex1_state_mach + ex1_state_mach + + + label + ex2_state_mach + ex2_state_mach + ex2_state_mach + + + switch_port_out_data[7:0] + switch_port_out_data[7:0] + + + switch_port_out_rd_en + switch_port_out_rd_en + + + ram_wr + ram_wr + + + ram_data_out[7:0] + ram_data_out[7:0] + + + packet_length[7:0] + packet_length[7:0] + + + ex1_state_mach + ex1_state_mach + + + ex2_state_mach + ex2_state_mach + + + switch_port_out_data[7:0] + switch_port_out_data[7:0] + + + switch_port_out_rd_en + switch_port_out_rd_en + + + ram_data_out[7:0] + ram_data_out[7:0] + + + ram_data_in[7:0] + ram_data_in[7:0] + + + ram_wr + ram_wr + + + ram_address[15:0] + ram_address[15:0] + + + dest_address[15:0] + dest_address[15:0] + + + packet_length[7:0] + packet_length[7:0] + + + port_out_data_available + port_out_data_available + + + etrec + etrec + + + etsnd + etsnd + + + rd_en_signal + rd_en_signal + + + rd_ready + rd_ready + + + empty + empty + + + fifo_counter[5:0] + fifo_counter[5:0] + + + fwft_fsm_state + fwft_fsm_state + + + rd_en + rd_en + + + wr_en + wr_en + + + initialized + initialized + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE.vhd (revision 29) @@ -0,0 +1,498 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:20:54 07/16/2012 +-- Design Name: +-- Module Name: PE - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library NocLib ; +--use IEEE.STD_LOGIC_ARITH.ALL; +--use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +use work.MPI_RMA.all; +use IEEE.NUMERIC_STD.ALL; + + +entity PE is + Generic (DestId : natural ); + Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : out STD_LOGIC; + Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_WE : in STD_LOGIC; + Core_RAM_EN : in STD_LOGIC; + --Core_RAM_ENB : in STD_LOGIC; + Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_Hold_req : in STD_LOGIC; + Core_Hold_Ack : out STD_LOGIC); +end PE; + +architecture Behavioral of PE is +COMPONENT RAM_v + generic (width : positive;size :positive); + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector; + addrb : IN std_logic_vector; + dia : IN std_logic_vector; + dob : OUT std_logic_vector + ); + END COMPONENT; +--données du programme PE + --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0'; + signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic; + signal pe_instr_en,pe_hold_ack: std_logic:='0'; + signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal sram : typ_dpram; + + signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0); + signal dpid,dpid_i : natural range 0 to 15:=DestId; + signal MyRank :std_logic_vector(3 downto 0); + signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque + signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée + signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO + signal Lib_Init : std_logic; -- l'initialisation est terminée + --signaux pour la gestion de la MAE + type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,GetRank1,GetRank2,GetRank3,writeptr,InstrCopy, + putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); +signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées +signal count,count_i : natural range 0 to 15:=0; + + + signal RunState : typ_mae; + signal Ram_busy :std_logic:='0'; +begin +Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN) + PORT MAP( + clka =>clk, + clkb => clk, + wea => ram_we, + ena => ram_ena, + enb => ram_enb, + addra => ram_addra, + addrb =>ram_addrb, + dia => ram_din, + dob => ram_do + ); +--================================================================ + --MUX de la RAM + +Ram_mux: process (ramsel,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr, + Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do, + Pe_ram_din,Pe_ram_we ) + begin + case ramsel is + + when '1' => + ram_addra <= Core_ram_address_wr ; + ram_addrb <= Core_ram_address_rd ; + ram_ena <= Core_ram_en; + ram_enb <= Core_ram_en; + ram_we<= Core_ram_we; + ram_din <= Core_ram_data_in; + pe_ram_do<=(others=>'Z'); + Core_ram_data_out<=ram_do; + + when others => + ram_addra <= pe_ram_addra; + ram_addrb <= pe_ram_addrb; + ram_ena <= pe_ram_ena; + ram_enb <= pe_ram_enb; + ram_we<= pe_ram_we; + ram_din <=pe_ram_din; + Core_ram_data_out<=(others=>'Z'); + pe_ram_do<=ram_do; +end case ; +end process ; + + + +Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --********A changer ********** +--=== !!!!! attention la suppression de la ligne ci-dessous empêche ce +-- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!! +instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8)); + +dpid<=dpid_i; + +Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié +Lib_init<=Core_Pushout(4); -- Initialized +-- pe_hold_req<=Core_hold_req; +--Core_hold_ack<=pe_hold_ack; + + hold:process (Core_Hold_Req,clk,reset) + begin + if rising_edge(clk) then + if reset='1' then + Core_Hold_Ack<='0'; + else + if Core_Hold_Req='1' then + + ramsel<=not(ram_busy); + Core_Hold_Ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération + Pe_hold_ack<=not(ram_busy); + else + Core_Hold_Ack<='0'; + ramsel<='0'; + Pe_hold_ack<='0'; + + end if; + end if; + end if; + end process hold; +--======================================================================= + + + +--======================================================================= +--MAE du PE +--======================================================================= + + pPutGet:process(clk,Core_Pushout,Core_Hold_req,PE_hold_Ack,RamSel,PE_Ram_do) + + constant DATAPTR : natural :=256; + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout,ct,dlen : natural range 0 to 255; + variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0); + variable iack : std_logic:='0'; + variable adresse,adresse_rd :natural range 0 to 65536; + variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0'); + begin + --=== Partie combinatoire du process =================================== + Libr.Instr_ack<=Core_pushout(0); + Libr.InitOk<=Core_pushout(4); + Libr.Hold_Req<=Core_Hold_req; + Libr.Hold_Ack<=Pe_Hold_Ack; + Libr.RamSel<=RamSel; + sram.data_out<=PE_ram_do; + --=== Fin de la partie combinatoire du process ========================== + if (clk'event and clk='1') then + if reset='1' then + RunState<=start; + + else + + Libr.Instr_ack<=Core_pushout(0); + Libr.InitOk<=Core_pushout(4); + Libr.Hold_Req<=Core_Hold_req; + Libr.Hold_Ack<=Pe_Hold_Ack; + Libr.RamSel<=RamSel; + sram.data_out<=PE_ram_do; + case RunState is + when start => + Dcount<=0; + if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide + RunState<=Fillmem; + end if; + Ram_busy<='0'; + PE_Instr_En<='0'; + iack:='0'; + adresse:=DATAPTR; + + adresse_rd:=0; + timeout:=0; + dcount<=0; + when Fillmem => + if Ramsel='0' then + + + + PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f"; + PE_Instr_En<='0'; + dcount<=dcount+1; + + if dcount=50 then + bfill:=bfill+1; + + if bfill=4 then + RunState<=InitApp; + else + RunState<=nextfill; + end if; + else + adresse:=adresse+1; + RunState<=Fillmem; + end if; + else -- attente de la libéraion de la mémoire + timeout:=timeout+1; + if timeout=100 then + RunState<=st_timeout; + end if; + + end if; + when nextfill => --prépare le prochain bloc mémoire qui sera rempli + adresse:=100*bfill; + dcount<=0; + ct:=0; + RunState<=Fillmem; + PE_Instr_En<='0'; + when InitApp => + --code pour Init + + pMPI_Init(ct,Libr,Clk,SRam); + PE_Instr_EN<=Libr.instr_en; + adresse:=to_integer(unsigned(sram.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.addr_rd)); + PE_ram_din<=sram.data_in; + + --if Libr.InitOk='1' then + if ct=0 then + RunState<=GetRank1; + end if; + + + when writeptr => + + When InstrCopy => + + + when InitCompleted => + + when GetRank1 => + + pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); + if ct=0 then + RunState<=PutData2; + end if; + adresse_rd:=to_integer(unsigned(sram.addr_rd)); + + when GetRank2 => + adresse_rd:=CORE_INIT_ADR+1; + if ramsel='0' then + RunState<=Getrank3; + end if; + when GetRank3=> + adresse_rd:=CORE_INIT_ADR+1; + if ramsel='0' then + RunState<=putdata2; + end if; + when putdata => --construire le packet pour le Put + + + when putdata2 => + + if unsigned(MyRank) = 0 then + Destrank:=1; + else + DestRank:=0; + end if; + dlen:=10; --- to_integer(unsigned(datalen)); + SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); + DestAdr:=X"2000"; + + pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr1 & DestAdr,Dlen,Mpi_int,Default_win); + adresse:=to_integer(unsigned(sram.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.addr_rd)); + PE_Instr_EN<=Libr.instr_en; + PE_ram_din<=sram.data_in; + dcount<=ct; + + if ct=0 then + RunState<=GetData; + end if; + + + when putcompleted => + + when getdata => --positionnement du mot de longueur des données + + dlen:=10; --- to_integer(unsigned(datalen)); + SrcAdr:=X"0150"; + DestAdr:=X"0300"; + + pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr1 & DestAdr,Dlen,Mpi_int,Default_win); + adresse:=to_integer(unsigned(sram.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.addr_rd)); + PE_Instr_EN<=Libr.instr_en; + PE_ram_din<=sram.data_in; + dcount<=ct; + + if ct=0 then + RunState<=terminate; + end if; + when getdata2 => + + + + + when getcompleted => + + + + when terminate => + + + RunState<=start; + + when st_timeout => + + --if ram_busy='1' then + RunState<=start; + --end if + + RunState<=start; + end case; + pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,16)); + pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16)); + end if; + end if; + + end process pPutGet; + +majPutGet:process (RunState,pe_ram_do,sram,Lib_Init) + + begin + case RunState is + when start => + + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + when fillmem => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + when nextfill => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + PE_Ram_enb<='0'; + + when InitApp => +-- PE_Ram_we<='1'; +-- PE_Ram_ena<='1'; +-- PE_Ram_enb<='0'; + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; + + when Initcompleted => + + PE_Ram_ena<=Lib_Init; + PE_Ram_we<='1'; + PE_Ram_enb<='1'; + + when GetRank1 => + + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; + when GetRank2 => + PE_Ram_ena<='0'; + --lecture effective du rang + PE_Ram_enb<='1'; + --MyRank<=PE_ram_do(3 downto 0); + when GetRank3 => + PE_Ram_ena<='0'; + --lecture effective du rang + PE_Ram_enb<='1'; + --MyRank<=PE_ram_do(3 downto 0); + when writeptr => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + -- dcount<=dcount+1; + + --PE_Instr_En<='0'; + when InstrCopy => --instruction copy + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + + + when putdata => --positionnement du mot de longueur des données + --dcount<=0; + srcadr0<=X"00"; + srcadr1<=X"01"; + destadr0<=X"00"; + destadr1<=X"02"; + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + + PE_Ram_enb<='1'; + + when putdata2 => +-- PE_Ram_we <='1'; --écriture dans la RAM +-- PE_Ram_ena <='1'; +-- PE_Ram_enb <='0'; + srcadr0<=X"00"; + srcadr1<=X"01"; + destadr0<=X"00"; + destadr1<=X"02"; + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; + + when putcompleted => + PE_Ram_we <='1'; + PE_Ram_ena <='1'; + -- lecture du résultat + PE_Ram_enb <='1'; + --PE_Instr_En<='1'; + when getdata => + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; + + + when getdata2 => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + + when getcompleted => + PE_Ram_we <='1'; + PE_Ram_ena <='1'; + + PE_Ram_enb <='1'; + + when terminate => + + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + + + when st_timeout => + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + + + end case; + +end process majPutGet ; +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE101.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE101.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE101.vhd (revision 29) @@ -0,0 +1,498 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:20:54 07/16/2012 +-- Design Name: +-- Module Name: PE - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library NocLib ; +--use IEEE.STD_LOGIC_ARITH.ALL; +--use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +use work.MPI_RMA.all; +use IEEE.NUMERIC_STD.ALL; + + +entity PE is + Generic (DestId : natural ); + Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : out STD_LOGIC; + Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_WE : in STD_LOGIC; + Core_RAM_EN : in STD_LOGIC; + --Core_RAM_ENB : in STD_LOGIC; + Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_Hold_req : in STD_LOGIC; + Core_Hold_Ack : out STD_LOGIC); +end PE; + +architecture Behavioral of PE is +COMPONENT RAM_v + generic (width : positive;size :positive); + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector; + addrb : IN std_logic_vector; + dia : IN std_logic_vector; + dob : OUT std_logic_vector + ); + END COMPONENT; +--données du programme PE + --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0'; + signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic; + signal pe_instr_en,pe_hold_ack: std_logic:='0'; + signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal sram : typ_dpram; + + signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0); + signal dpid,dpid_i : natural range 0 to 15:=DestId; + signal MyRank :std_logic_vector(3 downto 0); + signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque + signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée + signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO + signal Lib_Init : std_logic; -- l'initialisation est terminée + --signaux pour la gestion de la MAE + type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,GetRank1,GetRank2,GetRank3,writeptr,InstrCopy, + putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); +signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées +signal count,count_i : natural range 0 to 15:=0; + + + signal RunState : typ_mae; + signal Ram_busy :std_logic:='0'; +begin +Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN) + PORT MAP( + clka =>clk, + clkb => clk, + wea => ram_we, + ena => ram_ena, + enb => ram_enb, + addra => ram_addra, + addrb =>ram_addrb, + dia => ram_din, + dob => ram_do + ); +--================================================================ + --MUX de la RAM + +Ram_mux: process (ramsel,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr, + Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do, + Pe_ram_din,Pe_ram_we ) + begin + case ramsel is + + when '1' => + ram_addra <= Core_ram_address_wr ; + ram_addrb <= Core_ram_address_rd ; + ram_ena <= Core_ram_en; + ram_enb <= Core_ram_en; + ram_we<= Core_ram_we; + ram_din <= Core_ram_data_in; + pe_ram_do<=(others=>'Z'); + Core_ram_data_out<=ram_do; + + when others => + ram_addra <= pe_ram_addra; + ram_addrb <= pe_ram_addrb; + ram_ena <= pe_ram_ena; + ram_enb <= pe_ram_enb; + ram_we<= pe_ram_we; + ram_din <=pe_ram_din; + Core_ram_data_out<=(others=>'Z'); + pe_ram_do<=ram_do; +end case ; +end process ; + + + +Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --********A changer ********** +--=== !!!!! attention la suppression de la ligne ci-dessous empêche ce +-- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!! +instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8)); + +dpid<=dpid_i; + +Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié +Lib_init<=Core_Pushout(4); -- Initialized +-- pe_hold_req<=Core_hold_req; +--Core_hold_ack<=pe_hold_ack; + + hold:process (Core_Hold_Req,clk,reset) + begin + if rising_edge(clk) then + if reset='1' then + Core_Hold_Ack<='0'; + else + if Core_Hold_Req='1' then + + ramsel<=not(ram_busy); + Core_Hold_Ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération + Pe_hold_ack<=not(ram_busy); + else + Core_Hold_Ack<='0'; + ramsel<='0'; + Pe_hold_ack<='0'; + + end if; + end if; + end if; + end process hold; +--======================================================================= + + + +--======================================================================= +--MAE du PE +--======================================================================= + + pPutGet:process(clk,Core_Pushout,Core_Hold_req,PE_hold_Ack,RamSel,PE_Ram_do) + + constant DATAPTR : natural :=256; + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout,ct,dlen : natural range 0 to 255; + variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0); + variable iack : std_logic:='0'; + variable adresse,adresse_rd :natural range 0 to 65536; + variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0'); + begin + --=== Partie combinatoire du process =================================== + Libr.Instr_ack<=Core_pushout(0); + Libr.InitOk<=Core_pushout(4); + Libr.Hold_Req<=Core_Hold_req; + Libr.Hold_Ack<=Pe_Hold_Ack; + Libr.RamSel<=RamSel; + sram.data_out<=PE_ram_do; + --=== Fin de la partie combinatoire du process ========================== + if (clk'event and clk='1') then + if reset='1' then + RunState<=start; + + else + + Libr.Instr_ack<=Core_pushout(0); + Libr.InitOk<=Core_pushout(4); + Libr.Hold_Req<=Core_Hold_req; + Libr.Hold_Ack<=Pe_Hold_Ack; + Libr.RamSel<=RamSel; + sram.data_out<=PE_ram_do; + case RunState is + when start => + Dcount<=0; + if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide + RunState<=Fillmem; + end if; + Ram_busy<='0'; + PE_Instr_En<='0'; + iack:='0'; + adresse:=DATAPTR; + + adresse_rd:=0; + timeout:=0; + dcount<=0; + when Fillmem => + if Ramsel='0' then + + + + PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f"; + PE_Instr_En<='0'; + dcount<=dcount+1; + + if dcount=50 then + bfill:=bfill+1; + + if bfill=4 then + RunState<=InitApp; + else + RunState<=nextfill; + end if; + else + adresse:=adresse+1; + RunState<=Fillmem; + end if; + else -- attente de la libéraion de la mémoire + timeout:=timeout+1; + if timeout=100 then + RunState<=st_timeout; + end if; + + end if; + when nextfill => --prépare le prochain bloc mémoire qui sera rempli + adresse:=100*bfill; + dcount<=0; + ct:=0; + RunState<=Fillmem; + PE_Instr_En<='0'; + when InitApp => + --code pour Init + + pMPI_Init(ct,Libr,Clk,SRam); + PE_Instr_EN<=Libr.instr_en; + adresse:=to_integer(unsigned(sram.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.addr_rd)); + PE_ram_din<=sram.data_in; + + --if Libr.InitOk='1' then + if ct=0 then + RunState<=GetRank1; + end if; + + + when writeptr => + + When InstrCopy => + + + when InitCompleted => + + when GetRank1 => + + pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); + if ct=0 then + RunState<=PutData2; + end if; + adresse_rd:=to_integer(unsigned(sram.addr_rd)); + + when GetRank2 => + adresse_rd:=CORE_INIT_ADR+1; + if ramsel='0' then + RunState<=Getrank3; + end if; + when GetRank3=> + adresse_rd:=CORE_INIT_ADR+1; + if ramsel='0' then + RunState<=putdata2; + end if; + when putdata => --construire le packet pour le Put + + + when putdata2 => + + if unsigned(MyRank) = 0 then + Destrank:=1; + else + DestRank:=0; + end if; + dlen:=10; --- to_integer(unsigned(datalen)); + SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); + DestAdr:=X"2000"; + + pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr1 & DestAdr,Dlen,Mpi_int,Default_win); + adresse:=to_integer(unsigned(sram.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.addr_rd)); + PE_Instr_EN<=Libr.instr_en; + PE_ram_din<=sram.data_in; + dcount<=ct; + + if ct=0 then + RunState<=GetData; + end if; + + + when putcompleted => + + when getdata => --positionnement du mot de longueur des données + + dlen:=10; --- to_integer(unsigned(datalen)); + SrcAdr:=X"0150"; + DestAdr:=X"0300"; + + pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr1 & DestAdr,Dlen,Mpi_int,Default_win); + adresse:=to_integer(unsigned(sram.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.addr_rd)); + PE_Instr_EN<=Libr.instr_en; + PE_ram_din<=sram.data_in; + dcount<=ct; + + if ct=0 then + RunState<=terminate; + end if; + when getdata2 => + + + + + when getcompleted => + + + + when terminate => + + + RunState<=start; + + when st_timeout => + + --if ram_busy='1' then + RunState<=start; + --end if + + RunState<=start; + end case; + pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,16)); + pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16)); + end if; + end if; + + end process pPutGet; + +majPutGet:process (RunState,pe_ram_do,sram,Lib_Init) + + begin + case RunState is + when start => + + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + when fillmem => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + when nextfill => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + PE_Ram_enb<='0'; + + when InitApp => +-- PE_Ram_we<='1'; +-- PE_Ram_ena<='1'; +-- PE_Ram_enb<='0'; + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; + + when Initcompleted => + + PE_Ram_ena<=Lib_Init; + PE_Ram_we<='1'; + PE_Ram_enb<='1'; + + when GetRank1 => + + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; + when GetRank2 => + PE_Ram_ena<='0'; + --lecture effective du rang + PE_Ram_enb<='1'; + --MyRank<=PE_ram_do(3 downto 0); + when GetRank3 => + PE_Ram_ena<='0'; + --lecture effective du rang + PE_Ram_enb<='1'; + --MyRank<=PE_ram_do(3 downto 0); + when writeptr => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + -- dcount<=dcount+1; + + --PE_Instr_En<='0'; + when InstrCopy => --instruction copy + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + + + when putdata => --positionnement du mot de longueur des données + --dcount<=0; + srcadr0<=X"00"; + srcadr1<=X"01"; + destadr0<=X"00"; + destadr1<=X"02"; + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + + PE_Ram_enb<='1'; + + when putdata2 => +-- PE_Ram_we <='1'; --écriture dans la RAM +-- PE_Ram_ena <='1'; +-- PE_Ram_enb <='0'; + srcadr0<=X"00"; + srcadr1<=X"01"; + destadr0<=X"00"; + destadr1<=X"02"; + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; + + when putcompleted => + PE_Ram_we <='1'; + PE_Ram_ena <='1'; + -- lecture du résultat + PE_Ram_enb <='1'; + --PE_Instr_En<='1'; + when getdata => + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; + + + when getdata2 => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + + when getcompleted => + PE_Ram_we <='1'; + PE_Ram_ena <='1'; + + PE_Ram_enb <='1'; + + when terminate => + + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + + + when st_timeout => + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + + + end case; + +end process majPutGet ; +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE_100.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE_100.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE_100.vhd (revision 29) @@ -0,0 +1,704 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:20:54 07/16/2012 +-- Design Name: +-- Module Name: PE - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library NocLib ; +--use IEEE.STD_LOGIC_ARITH.ALL; +--use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +use work.MPI_RMA.all; +use IEEE.NUMERIC_STD.ALL; + + +entity PE is + Generic (DestId : natural ); + Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : out STD_LOGIC; + Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_WE : in STD_LOGIC; + Core_RAM_EN : in STD_LOGIC; + --Core_RAM_ENB : in STD_LOGIC; + Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_Hold_req : in STD_LOGIC; + Core_Hold_Ack : out STD_LOGIC); +end PE; + +architecture Behavioral of PE is +COMPONENT RAM_v + generic (width : positive;size :positive); + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector; + addrb : IN std_logic_vector; + dia : IN std_logic_vector; + dob : OUT std_logic_vector + ); + END COMPONENT; +--données du programme PE + --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0'; + signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic; + signal pe_instr_en,pe_hold_ack: std_logic:='0'; + signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal sram : typ_dpram; + + signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0); + signal dpid,dpid_i : natural range 0 to 15:=DestId; + signal MyRank :std_logic_vector(3 downto 0); + signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque + signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée + signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO + signal Lib_Init : std_logic; -- l'initialisation est terminée + --signaux pour la gestion de la MAE + type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,GetRank1,GetRank2,GetRank3,writeptr,InstrCopy, + putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); +signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées +signal count,count_i : natural range 0 to 15:=0; + + + signal RunState : typ_mae; + signal Ram_busy :std_logic:='0'; +begin +Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN) + PORT MAP( + clka =>clk, + clkb => clk, + wea => ram_we, + ena => ram_ena, + enb => ram_enb, + addra => ram_addra, + addrb =>ram_addrb, + dia => ram_din, + dob => ram_do + ); +--================================================================ + --MUX de la RAM + +Ram_mux: process (ramsel,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr, + Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do, + Pe_ram_din,Pe_ram_we ) + begin + case ramsel is + + when '1' => + ram_addra <= Core_ram_address_wr ; + ram_addrb <= Core_ram_address_rd ; + ram_ena <= Core_ram_en; + ram_enb <= Core_ram_en; + ram_we<= Core_ram_we; + ram_din <= Core_ram_data_in; + pe_ram_do<=(others=>'Z'); + Core_ram_data_out<=ram_do; + + when others => + ram_addra <= pe_ram_addra; + ram_addrb <= pe_ram_addrb; + ram_ena <= pe_ram_ena; + ram_enb <= pe_ram_enb; + ram_we<= pe_ram_we; + ram_din <=pe_ram_din; + Core_ram_data_out<=(others=>'Z'); + pe_ram_do<=ram_do; +end case ; +end process ; + + + +Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --********A changer ********** +--=== !!!!! attention la suppression de la ligne ci-dessous empêche ce +-- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!! +instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8)); + +dpid<=dpid_i; + +Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié +Lib_init<=Core_Pushout(4); -- Initialized +-- pe_hold_req<=Core_hold_req; +--Core_hold_ack<=pe_hold_ack; + + hold:process (Core_Hold_Req,clk,reset) + begin + if rising_edge(clk) then + if reset='1' then + Core_Hold_Ack<='0'; + else + if Core_Hold_Req='1' then + + ramsel<=not(ram_busy); + Core_Hold_Ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération + Pe_hold_ack<=not(ram_busy); + else + Core_Hold_Ack<='0'; + ramsel<='0'; + Pe_hold_ack<='0'; + + end if; + end if; + end if; + end process hold; +--======================================================================= + + + +--======================================================================= +--MAE du PE +--======================================================================= + + pPutGet:process(clk,Core_Pushout,Core_Hold_req,PE_hold_Ack,RamSel,PE_Ram_do) + + constant DATAPTR : natural :=256; + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout,ct,dlen : natural range 0 to 255; + variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0); + variable iack : std_logic:='0'; + variable adresse,adresse_rd :natural range 0 to 65536; + variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0'); + begin + --=== Partie combinatoire du process =================================== + Libr.Instr_ack<=Core_pushout(0); + Libr.InitOk<=Core_pushout(4); + Libr.Hold_Req<=Core_Hold_req; + Libr.Hold_Ack<=Pe_Hold_Ack; + Libr.RamSel<=RamSel; + sram.data_out<=PE_ram_do; + --=== Fin de la partie combinatoire du process ========================== + if (clk'event and clk='1') then + if reset='1' then + RunState<=start; + + else + + Libr.Instr_ack<=Core_pushout(0); + Libr.InitOk<=Core_pushout(4); + Libr.Hold_Req<=Core_Hold_req; + Libr.Hold_Ack<=Pe_Hold_Ack; + Libr.RamSel<=RamSel; + sram.data_out<=PE_ram_do; + case RunState is + when start => + Dcount<=0; + if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide + RunState<=Fillmem; + end if; + Ram_busy<='0'; + PE_Instr_En<='0'; + iack:='0'; + adresse:=DATAPTR; + + adresse_rd:=0; + timeout:=0; + dcount<=0; + when Fillmem => + if Ramsel='0' then + + + + PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f"; + PE_Instr_En<='0'; + dcount<=dcount+1; + + if dcount=50 then + bfill:=bfill+1; + + if bfill=4 then + RunState<=InitApp; + else + RunState<=nextfill; + end if; + else + adresse:=adresse+1; + RunState<=Fillmem; + end if; + else -- attente de la libéraion de la mémoire + timeout:=timeout+1; + if timeout=100 then + RunState<=st_timeout; + end if; + + end if; + when nextfill => --prépare le prochain bloc mémoire qui sera rempli + adresse:=100*bfill; + dcount<=0; + ct:=0; + RunState<=Fillmem; + PE_Instr_En<='0'; + when InitApp => + --code pour Init + + pMPI_Init(ct,Libr,Clk,SRam); + PE_Instr_EN<=Libr.instr_en; + adresse:=to_integer(unsigned(sram.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.addr_rd)); + PE_ram_din<=sram.data_in; + + --if Libr.InitOk='1' then + if ct=0 then + RunState<=GetRank1; + end if; + + + when writeptr => + PE_Instr_En<='0'; + if Ramsel= '0' then --s'assurer que le bus est disponible + + if dcount=0 then + PE_RAM_Din<=AdrToSet(Word-1 downto 0); + dcount <=dcount+1; + --adresse:=adresse+1; --prépare la prochaine écriture + elsif dcount=1 then + dcount <=dcount+1; + adresse:=adresse+1; --prépare la prochaine écriture + PE_RAM_Din<=AdrToSet(15 downto 8); + elsif dcount=2 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + ret:=fsrc; + dcount<=0; + timeout:=0; + + if fsrc=1 then + RunState <= InitApp; + elsif fsrc=2 then + RunState <= putdata; + elsif fsrc=3 then + RunState <= getdata; + else + RunState <= start; + end if; + + end if; + + end if; + When InstrCopy => + if Lib_instr_ack='1' then + RunState<=Writeptr; + PE_instr_en<='0'; + iack:='1'; + + else + PE_Instr_en<='1'; + end if; + + when InitCompleted => + adresse:=CORE_BASE_ADR; + + status_reg:=status_reg or x"10"; + PE_Ram_din<=status_reg ; + if Lib_Init='1' then + RunState<=GetRank1; + PE_Instr_En<='0'; + --instruction(5)<='1'; + else + PE_Instr_En<='0'; + end if; + when GetRank1 => + + pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); + if ct=0 then + RunState<=PutData2; + end if; + adresse_rd:=to_integer(unsigned(sram.addr_rd)); +-- adresse_rd:=CORE_INIT_ADR+1; +-- if ramsel='0' then +-- RunState<=getrank2; +-- end if; + when GetRank2 => + adresse_rd:=CORE_INIT_ADR+1; + if ramsel='0' then + RunState<=Getrank3; + end if; + when GetRank3=> + adresse_rd:=CORE_INIT_ADR+1; + if ramsel='0' then + RunState<=putdata2; + end if; + when putdata => --construire le packet pour le Put + if unsigned(MyRank) = 0 then + Destrank:=1; + else + DestRank:=0; + end if; + adresse_rd:=core_base_adr+Core_Rank2port_base+DestRank; + + PE_Instr_En<='0'; + timeout:=0; + dcount<=0; + fsrc:=2; + adrToSet:=std_logic_vector(to_unsigned(core_put_adr,16)); + if ret/=fsrc then + adresse:=core_base_adr+2; + RunState<=writeptr; + ret:=0; + else + if Lib_instr_ack/='1' then + RunState<= putdata2; + end if; + end if; + + when putdata2 => + + if unsigned(MyRank) = 0 then + Destrank:=1; + else + DestRank:=0; + end if; + dlen:=10; --- to_integer(unsigned(datalen)); + SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); + DestAdr:=X"2000"; + + pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr1 & DestAdr,Dlen,Mpi_int,Default_win); + adresse:=to_integer(unsigned(sram.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.addr_rd)); + PE_Instr_EN<=Libr.instr_en; + PE_ram_din<=sram.data_in; + dcount<=ct; + + if ct=0 then + RunState<=GetData; + end if; + +-- if dcount<=6 then +-- +-- elsif dcount=7 then +-- +-- PE_Instr_En<='1'; +-- +-- end if; + +-- elsif PE_instr_En='0' then +-- timeout:=timeout+1; +-- if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire +-- ram_busy<='1'; +-- timeout:=0; +-- PE_Instr_En<='0'; +-- end if; +-- end if; +-- if dcount >=6 then +-- Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI +-- if Lib_instr_ack='1' then -- Instruction ack +-- PE_Instr_En<='0'; +-- if Ramsel='0' then +-- adresse:=core_base_adr+1; +-- config_reg:=config_reg and x"f6"; +-- PE_Ram_din<=config_reg ; --ramener le IPulse à 0; +-- Ram_busy<='0'; +-- RunState<=putcompleted; +-- else +-- +-- Ram_busy<='1'; --force la prise du bus +-- end if; +-- else +-- +-- timeout:=timeout+1; +-- if timeout=150 then +-- RunState<=st_timeout; +-- end if; +-- end if; +-- end if; + + + when putcompleted => + adresse_rd:=core_put_adr+6; + if PE_Ram_do(0)='1' then --Put completed + RunState<=GetData; + end if; + PE_Instr_En<='0'; + when getdata => --positionnement du mot de longueur des données + + --DestRank:=1; + timeout:=0; + dcount<=0; + fsrc:=3; + adrToSet:=std_logic_vector(to_unsigned(core_get_adr,16)); + if ret/=fsrc then + adresse:=core_base_adr+2; + RunState<=writeptr; + ret:=0; + else + adresse:=core_get_adr; + RunState<= getdata2; + end if; + PE_Instr_En<='0'; + when getdata2 => + + if ramsel='0' then + if dcount<=6 then + + if dcount=0 then + adresse:=core_get_adr; + PE_Ram_din<=MPI_GET & std_logic_vector(to_unsigned(DestRank,4)); + elsif dcount=1 then + adresse:=core_get_adr+dcount; + PE_Ram_din<=Datalen ; + elsif dcount=2 then + adresse:=core_get_adr+dcount; + PE_Ram_din<=SrcAdr1 ; + elsif dcount=3 then + adresse:=core_get_adr+dcount; + PE_Ram_din<=SrcAdr0 ; + elsif dcount=4 then + adresse:=core_get_adr+dcount; + PE_Ram_din<=DestAdr1 ; + elsif dcount=5 then + adresse:=core_get_adr+dcount; + PE_Ram_din<=DestAdr0 ; + + elsif dcount=6 then + adresse:=core_base_adr+1; + adresse_rd:=core_base_adr; + PE_Instr_En<='1'; + config_reg:=config_reg or x"01"; + PE_Ram_din<=config_reg ; --instruction pulse enable; + + timeout:=0; + end if; + dcount<=dcount+1; + end if; + elsif PE_Instr_En='0'then + timeout:=timeout+1; + if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire + ram_busy<='1'; + timeout:=0; + PE_Instr_En<='0'; + end if; + end if; + + if dcount >=6 then + Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI + if Lib_instr_ack='1' then -- Instruction ack + PE_Instr_En<='0'; + if Ramsel='0' then + adresse:=core_base_adr+1; + config_reg:=config_reg and x"f6"; + PE_Ram_din<=config_reg ; --ramener le IPulse à 0; + + Ram_busy<='0'; + RunState<=getcompleted; + else + + Ram_busy<='1'; --force la prise du bus + end if; + else + + timeout:=timeout+1; + if timeout=150 then + RunState<=st_timeout; + end if; + end if; + + + end if; + + + + when getcompleted => + adresse_rd:=core_get_adr+6; + PE_Instr_En<='0'; + if PE_Ram_do(0)='1' then --get completed + if Ramsel='0' then + adresse:=core_base_adr+1; + config_reg:=config_reg and x"f6"; + PE_Ram_din<=config_reg ; --ramener le IPulse à 0; + + RunState<=Terminate; + else + timeout:=timeout+1; + end if; + end if; + + + when terminate => + + + RunState<=start; + + when st_timeout => + + --if ram_busy='1' then + RunState<=start; + --end if + + RunState<=start; + end case; + pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,16)); + pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16)); + end if; + end if; + + end process pPutGet; + +majPutGet:process (RunState,pe_ram_do,sram,Lib_Init) + + begin + case RunState is + when start => + + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + when fillmem => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + when nextfill => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + PE_Ram_enb<='0'; + + when InitApp => +-- PE_Ram_we<='1'; +-- PE_Ram_ena<='1'; +-- PE_Ram_enb<='0'; + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; + + when Initcompleted => + + PE_Ram_ena<=Lib_Init; + PE_Ram_we<='1'; + PE_Ram_enb<='1'; + + when GetRank1 => +-- PE_Ram_ena<='0'; +-- --lecture du rang positionnement de l'adresse +-- PE_Ram_enb<='1'; +-- --MyRank<=PE_ram_do(3 downto 0); + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; + when GetRank2 => + PE_Ram_ena<='0'; + --lecture effective du rang + PE_Ram_enb<='1'; + --MyRank<=PE_ram_do(3 downto 0); + when GetRank3 => + PE_Ram_ena<='0'; + --lecture effective du rang + PE_Ram_enb<='1'; + --MyRank<=PE_ram_do(3 downto 0); + when writeptr => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + -- dcount<=dcount+1; + + --PE_Instr_En<='0'; + when InstrCopy => --instruction copy + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + + + when putdata => --positionnement du mot de longueur des données + --dcount<=0; + srcadr0<=X"00"; + srcadr1<=X"01"; + destadr0<=X"00"; + destadr1<=X"02"; + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + --lecture du n° de port de destination + PE_Ram_enb<='1'; + datalen<=std_logic_vector(to_unsigned(10,8)); + dpid_i<=to_integer(unsigned(PE_ram_do(3 downto 0))); --le port est situé ur les 4 bits de poids faible + --PE_Instr_En<='0'; + when putdata2 => +-- PE_Ram_we <='1'; --écriture dans la RAM +-- PE_Ram_ena <='1'; +-- PE_Ram_enb <='0'; + srcadr0<=X"00"; + srcadr1<=X"01"; + destadr0<=X"00"; + destadr1<=X"02"; + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; + + when putcompleted => + PE_Ram_we <='1'; + PE_Ram_ena <='1'; + -- lecture du résultat + PE_Ram_enb <='1'; + --PE_Instr_En<='1'; + when getdata => + --dcount<=0; + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + PE_Ram_enb<='0'; + + srcadr0<=X"50"; + srcadr1<=X"01"; + destadr0<=X"00"; + destadr1<=X"03"; + datalen<=std_logic_vector(to_unsigned(10,8)); + --PE_Instr_En<='0'; + when getdata2 => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + --dcount<=dcount+1; + if dcount=5 then + --PE_Instr_En<='1'; + else + --PE_Instr_En<='0'; + end if; + when getcompleted => + PE_Ram_we <='1'; + PE_Ram_ena <='1'; + -- lecture du résultat + PE_Ram_enb <='1'; + --PE_Instr_En<='1'; + when terminate => + + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + when st_timeout => + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + end case; + +end process majPutGet ; +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE_beh.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE_beh.prj (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE_beh.prj (revision 29) @@ -0,0 +1,5 @@ +vhdl NocLib "../SWITCH_GENERIC_16_16/CoreTypes.vhd" +vhdl work "Packet_type.vhd" +vhdl work "RAM_32_32.vhd" +vhdl work "MPI_RMA.vhd" +vhdl work "PE.vhd" Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE_new.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE_new.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE_new.vhd (revision 29) @@ -0,0 +1,704 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:20:54 07/16/2012 +-- Design Name: +-- Module Name: PE - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library NocLib ; +--use IEEE.STD_LOGIC_ARITH.ALL; +--use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +use work.MPI_RMA.all; +use IEEE.NUMERIC_STD.ALL; + + +entity PE is + Generic (DestId : natural ); + Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); + Instruction_en : out STD_LOGIC; + Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); + clk : in STD_LOGIC; + reset : in STD_LOGIC; + Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); + Core_RAM_WE : in STD_LOGIC; + Core_RAM_EN : in STD_LOGIC; + --Core_RAM_ENB : in STD_LOGIC; + Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); + Core_Hold_req : in STD_LOGIC; + Core_Hold_Ack : out STD_LOGIC); +end PE; + +architecture Behavioral of PE is +COMPONENT RAM_v + generic (width : positive;size :positive); + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector; + addrb : IN std_logic_vector; + dia : IN std_logic_vector; + dob : OUT std_logic_vector + ); + END COMPONENT; +--données du programme PE + --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_we ,ram_ena,ram_enb,ramsel: std_logic:='0'; + signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic; + signal pe_instr_en,pe_hold_ack: std_logic:='0'; + signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); + signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); + signal sram : typ_dpram; + + signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0); + signal dpid,dpid_i : natural range 0 to 15:=DestId; + signal MyRank :std_logic_vector(3 downto 0); + signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque + signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée + signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO + signal Lib_Init : std_logic; -- l'initialisation est terminée + --signaux pour la gestion de la MAE + type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,GetRank1,GetRank2,GetRank3,writeptr,InstrCopy, + putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); +signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées +signal count,count_i : natural range 0 to 15:=0; + + + signal RunState : typ_mae; + signal Ram_busy :std_logic:='0'; +begin +Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN) + PORT MAP( + clka =>clk, + clkb => clk, + wea => ram_we, + ena => ram_ena, + enb => ram_enb, + addra => ram_addra, + addrb =>ram_addrb, + dia => ram_din, + dob => ram_do + ); +--================================================================ + --MUX de la RAM + +Ram_mux: process (ramsel,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr, + Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do, + Pe_ram_din,Pe_ram_we ) + begin + case ramsel is + + when '1' => + ram_addra <= Core_ram_address_wr ; + ram_addrb <= Core_ram_address_rd ; + ram_ena <= Core_ram_en; + ram_enb <= Core_ram_en; + ram_we<= Core_ram_we; + ram_din <= Core_ram_data_in; + pe_ram_do<=(others=>'Z'); + Core_ram_data_out<=ram_do; + + when others => + ram_addra <= pe_ram_addra; + ram_addrb <= pe_ram_addrb; + ram_ena <= pe_ram_ena; + ram_enb <= pe_ram_enb; + ram_we<= pe_ram_we; + ram_din <=pe_ram_din; + Core_ram_data_out<=(others=>'Z'); + pe_ram_do<=ram_do; +end case ; +end process ; + + + +Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --********A changer ********** +--=== !!!!! attention la suppression de la ligne ci-dessous empêche ce +-- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!! +instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8)); + +dpid<=dpid_i; + +Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié +Lib_init<=Core_Pushout(4); -- Initialized +-- pe_hold_req<=Core_hold_req; +--Core_hold_ack<=pe_hold_ack; + + hold:process (Core_Hold_Req,clk,reset) + begin + if rising_edge(clk) then + if reset='1' then + Core_Hold_Ack<='0'; + else + if Core_Hold_Req='1' then + + ramsel<=not(ram_busy); + Core_Hold_Ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération + Pe_hold_ack<=not(ram_busy); + else + Core_Hold_Ack<='0'; + ramsel<='0'; + Pe_hold_ack<='0'; + + end if; + end if; + end if; + end process hold; +--======================================================================= + + + +--======================================================================= +--MAE du PE +--======================================================================= + + pPutGet:process(clk,Core_Pushout,Core_Hold_req,PE_hold_Ack,RamSel,PE_Ram_do) + + constant DATAPTR : natural :=256; + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout,ct,dlen : natural range 0 to 255; + variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0); + variable iack : std_logic:='0'; + variable adresse,adresse_rd :natural range 0 to 65536; + variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0'); + begin + --=== Partie combinatoire du process =================================== + Libr.Instr_ack<=Core_pushout(0); + Libr.InitOk<=Core_pushout(4); + Libr.Hold_Req<=Core_Hold_req; + Libr.Hold_Ack<=Pe_Hold_Ack; + Libr.RamSel<=RamSel; + sram.data_out<=PE_ram_do; + --=== Fin de la partie combinatoire du process ========================== + if (clk'event and clk='1') then + if reset='1' then + RunState<=start; + + else + + Libr.Instr_ack<=Core_pushout(0); + Libr.InitOk<=Core_pushout(4); + Libr.Hold_Req<=Core_Hold_req; + Libr.Hold_Ack<=Pe_Hold_Ack; + Libr.RamSel<=RamSel; + sram.data_out<=PE_ram_do; + case RunState is + when start => + Dcount<=0; + if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide + RunState<=Fillmem; + end if; + Ram_busy<='0'; + PE_Instr_En<='0'; + iack:='0'; + adresse:=DATAPTR; + + adresse_rd:=0; + timeout:=0; + dcount<=0; + when Fillmem => + if Ramsel='0' then + + + + PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f"; + PE_Instr_En<='0'; + dcount<=dcount+1; + + if dcount=50 then + bfill:=bfill+1; + + if bfill=4 then + RunState<=InitApp; + else + RunState<=nextfill; + end if; + else + adresse:=adresse+1; + RunState<=Fillmem; + end if; + else -- attente de la libéraion de la mémoire + timeout:=timeout+1; + if timeout=100 then + RunState<=st_timeout; + end if; + + end if; + when nextfill => --prépare le prochain bloc mémoire qui sera rempli + adresse:=100*bfill; + dcount<=0; + ct:=0; + RunState<=Fillmem; + PE_Instr_En<='0'; + when InitApp => + --code pour Init + + pMPI_Init(ct,Libr,Clk,SRam); + PE_Instr_EN<=Libr.instr_en; + adresse:=to_integer(unsigned(sram.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.addr_rd)); + PE_ram_din<=sram.data_in; + + --if Libr.InitOk='1' then + if ct=0 then + RunState<=GetRank1; + end if; + + + when writeptr => + PE_Instr_En<='0'; + if Ramsel= '0' then --s'assurer que le bus est disponible + + if dcount=0 then + PE_RAM_Din<=AdrToSet(Word-1 downto 0); + dcount <=dcount+1; + --adresse:=adresse+1; --prépare la prochaine écriture + elsif dcount=1 then + dcount <=dcount+1; + adresse:=adresse+1; --prépare la prochaine écriture + PE_RAM_Din<=AdrToSet(15 downto 8); + elsif dcount=2 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + ret:=fsrc; + dcount<=0; + timeout:=0; + + if fsrc=1 then + RunState <= InitApp; + elsif fsrc=2 then + RunState <= putdata; + elsif fsrc=3 then + RunState <= getdata; + else + RunState <= start; + end if; + + end if; + + end if; + When InstrCopy => + if Lib_instr_ack='1' then + RunState<=Writeptr; + PE_instr_en<='0'; + iack:='1'; + + else + PE_Instr_en<='1'; + end if; + + when InitCompleted => + adresse:=CORE_BASE_ADR; + + status_reg:=status_reg or x"10"; + PE_Ram_din<=status_reg ; + if Lib_Init='1' then + RunState<=GetRank1; + PE_Instr_En<='0'; + --instruction(5)<='1'; + else + PE_Instr_En<='0'; + end if; + when GetRank1 => + + pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); + if ct=0 then + RunState<=PutData2; + end if; + adresse_rd:=to_integer(unsigned(sram.addr_rd)); +-- adresse_rd:=CORE_INIT_ADR+1; +-- if ramsel='0' then +-- RunState<=getrank2; +-- end if; + when GetRank2 => + adresse_rd:=CORE_INIT_ADR+1; + if ramsel='0' then + RunState<=Getrank3; + end if; + when GetRank3=> + adresse_rd:=CORE_INIT_ADR+1; + if ramsel='0' then + RunState<=putdata2; + end if; + when putdata => --construire le packet pour le Put + if unsigned(MyRank) = 0 then + Destrank:=1; + else + DestRank:=0; + end if; + adresse_rd:=core_base_adr+Core_Rank2port_base+DestRank; + + PE_Instr_En<='0'; + timeout:=0; + dcount<=0; + fsrc:=2; + adrToSet:=std_logic_vector(to_unsigned(core_put_adr,16)); + if ret/=fsrc then + adresse:=core_base_adr+2; + RunState<=writeptr; + ret:=0; + else + if Lib_instr_ack/='1' then + RunState<= putdata2; + end if; + end if; + + when putdata2 => + + if unsigned(MyRank) = 0 then + Destrank:=1; + else + DestRank:=0; + end if; + dlen:=10; --- to_integer(unsigned(datalen)); + SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); + DestAdr:=X"2000"; + + pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr1 & DestAdr,Dlen,Mpi_int,Default_win); + adresse:=to_integer(unsigned(sram.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.addr_rd)); + PE_Instr_EN<=Libr.instr_en; + PE_ram_din<=sram.data_in; + dcount<=ct; + + if ct=0 then + RunState<=GetData; + end if; + +-- if dcount<=6 then +-- +-- elsif dcount=7 then +-- +-- PE_Instr_En<='1'; +-- +-- end if; + +-- elsif PE_instr_En='0' then +-- timeout:=timeout+1; +-- if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire +-- ram_busy<='1'; +-- timeout:=0; +-- PE_Instr_En<='0'; +-- end if; +-- end if; +-- if dcount >=6 then +-- Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI +-- if Lib_instr_ack='1' then -- Instruction ack +-- PE_Instr_En<='0'; +-- if Ramsel='0' then +-- adresse:=core_base_adr+1; +-- config_reg:=config_reg and x"f6"; +-- PE_Ram_din<=config_reg ; --ramener le IPulse à 0; +-- Ram_busy<='0'; +-- RunState<=putcompleted; +-- else +-- +-- Ram_busy<='1'; --force la prise du bus +-- end if; +-- else +-- +-- timeout:=timeout+1; +-- if timeout=150 then +-- RunState<=st_timeout; +-- end if; +-- end if; +-- end if; + + + when putcompleted => + adresse_rd:=core_put_adr+6; + if PE_Ram_do(0)='1' then --Put completed + RunState<=GetData; + end if; + PE_Instr_En<='0'; + when getdata => --positionnement du mot de longueur des données + + DestRank:=1; + timeout:=0; + dcount<=0; + fsrc:=3; + adrToSet:=std_logic_vector(to_unsigned(core_get_adr,16)); + if ret/=fsrc then + adresse:=core_base_adr+2; + RunState<=writeptr; + ret:=0; + else + adresse:=core_get_adr; + RunState<= getdata2; + end if; + PE_Instr_En<='0'; + when getdata2 => + + if ramsel='0' then + if dcount<=6 then + + if dcount=0 then + adresse:=core_get_adr; + PE_Ram_din<=MPI_GET & std_logic_vector(to_unsigned(Dpid,4)); + elsif dcount=1 then + adresse:=core_get_adr+dcount; + PE_Ram_din<=Datalen ; + elsif dcount=2 then + adresse:=core_get_adr+dcount; + PE_Ram_din<=SrcAdr1 ; + elsif dcount=3 then + adresse:=core_get_adr+dcount; + PE_Ram_din<=SrcAdr0 ; + elsif dcount=4 then + adresse:=core_get_adr+dcount; + PE_Ram_din<=DestAdr1 ; + elsif dcount=5 then + adresse:=core_get_adr+dcount; + PE_Ram_din<=DestAdr0 ; + + elsif dcount=6 then + adresse:=core_base_adr+1; + adresse_rd:=core_base_adr; + PE_Instr_En<='1'; + config_reg:=config_reg or x"01"; + PE_Ram_din<=config_reg ; --instruction pulse enable; + + timeout:=0; + end if; + dcount<=dcount+1; + end if; + elsif PE_Instr_En='0'then + timeout:=timeout+1; + if timeout>=10 then -- reprendre le contrôle du Bus de force si nécessaire + ram_busy<='1'; + timeout:=0; + PE_Instr_En<='0'; + end if; + end if; + + if dcount >=6 then + Ram_busy<='0';--libérer le bus et attendre la réponse du Core MPI + if Lib_instr_ack='1' then -- Instruction ack + PE_Instr_En<='0'; + if Ramsel='0' then + adresse:=core_base_adr+1; + config_reg:=config_reg and x"f6"; + PE_Ram_din<=config_reg ; --ramener le IPulse à 0; + + Ram_busy<='0'; + RunState<=getcompleted; + else + + Ram_busy<='1'; --force la prise du bus + end if; + else + + timeout:=timeout+1; + if timeout=150 then + RunState<=st_timeout; + end if; + end if; + + + end if; + + + + when getcompleted => + adresse_rd:=core_get_adr+6; + PE_Instr_En<='0'; + if PE_Ram_do(0)='1' then --get completed + if Ramsel='0' then + adresse:=core_base_adr+1; + config_reg:=config_reg and x"f6"; + PE_Ram_din<=config_reg ; --ramener le IPulse à 0; + + RunState<=Terminate; + else + timeout:=timeout+1; + end if; + end if; + + + when terminate => + + + RunState<=start; + + when st_timeout => + + --if ram_busy='1' then + RunState<=start; + --end if + + RunState<=start; + end case; + pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,16)); + pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16)); + end if; + end if; + + end process pPutGet; + +majPutGet:process (RunState,pe_ram_do,sram,Lib_Init) + + begin + case RunState is + when start => + + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + when fillmem => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + when nextfill => + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + PE_Ram_enb<='0'; + + when InitApp => +-- PE_Ram_we<='1'; +-- PE_Ram_ena<='1'; +-- PE_Ram_enb<='0'; + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; + + when Initcompleted => + + PE_Ram_ena<=Lib_Init; + PE_Ram_we<='1'; + PE_Ram_enb<='1'; + + when GetRank1 => +-- PE_Ram_ena<='0'; +-- --lecture du rang positionnement de l'adresse +-- PE_Ram_enb<='1'; +-- --MyRank<=PE_ram_do(3 downto 0); + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; + when GetRank2 => + PE_Ram_ena<='0'; + --lecture effective du rang + PE_Ram_enb<='1'; + --MyRank<=PE_ram_do(3 downto 0); + when GetRank3 => + PE_Ram_ena<='0'; + --lecture effective du rang + PE_Ram_enb<='1'; + --MyRank<=PE_ram_do(3 downto 0); + when writeptr => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + -- dcount<=dcount+1; + + --PE_Instr_En<='0'; + when InstrCopy => --instruction copy + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + + + when putdata => --positionnement du mot de longueur des données + --dcount<=0; + srcadr0<=X"00"; + srcadr1<=X"01"; + destadr0<=X"00"; + destadr1<=X"02"; + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + --lecture du n° de port de destination + PE_Ram_enb<='1'; + datalen<=std_logic_vector(to_unsigned(10,8)); + dpid_i<=to_integer(unsigned(PE_ram_do(3 downto 0))); --le port est situé ur les 4 bits de poids faible + --PE_Instr_En<='0'; + when putdata2 => +-- PE_Ram_we <='1'; --écriture dans la RAM +-- PE_Ram_ena <='1'; +-- PE_Ram_enb <='0'; + srcadr0<=X"00"; + srcadr1<=X"01"; + destadr0<=X"00"; + destadr1<=X"02"; + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; + + when putcompleted => + PE_Ram_we <='1'; + PE_Ram_ena <='1'; + -- lecture du résultat + PE_Ram_enb <='1'; + --PE_Instr_En<='1'; + when getdata => + --dcount<=0; + PE_Ram_we<='1'; + PE_Ram_ena<='1'; + PE_Ram_enb<='0'; + + srcadr0<=X"00"; + srcadr1<=X"02"; + destadr0<=X"00"; + destadr1<=X"03"; + datalen<=std_logic_vector(to_unsigned(10,8)); + --PE_Instr_En<='0'; + when getdata2 => + PE_Ram_we <='1'; --écriture dans la RAM + PE_Ram_ena <='1'; + + PE_Ram_enb <='0'; + --dcount<=dcount+1; + if dcount=5 then + --PE_Instr_En<='1'; + else + --PE_Instr_En<='0'; + end if; + when getcompleted => + PE_Ram_we <='1'; + PE_Ram_ena <='1'; + -- lecture du résultat + PE_Ram_enb <='1'; + --PE_Instr_En<='1'; + when terminate => + + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + when st_timeout => + PE_Ram_we<='0'; + PE_Ram_ena<='0'; + PE_Ram_enb<='0'; + --PE_Instr_En<='0'; + + end case; + +end process majPutGet ; +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Packet_type.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Packet_type.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Packet_type.vhd (revision 29) @@ -0,0 +1,79 @@ +-- Package File Template +-- +-- Purpose: This package defines supplemental types, subtypes, +-- constants, and functions +-- package definissant le codage des fonctions MPI +-- dans le champs packet type des instructions MPI + +-- Ce fichier définit les trames des instruction MPI qui sont utilisables +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package Packet_type is + constant MPI_COMM_WORLD :natural:=1; + constant MPI_DEFAULT :natural:=0; + constant MPI_INT :natural:=1; + constant MPI_INFO_NULL :natural:=0; + constant Default_Win :natural:=1; + constant MPI_GET_RANK : std_logic_vector(3 downto 0) := "0000"; + constant MPI_GET_SIZE : std_logic_vector(3 downto 0) := "0001"; + constant MPI_BARRIER : std_logic_vector(3 downto 0) := "0010"; + constant MPI_BARRIER_REACHED : std_logic_vector(3 downto 0) := "0011"; + constant MPI_BARRIER_COMPLETED : std_logic_vector(3 downto 0) := "0100"; + constant MPI_PUT : std_logic_vector(3 downto 0) := "0101"; + constant MPI_GET : std_logic_vector(3 downto 0) := "0110"; + constant MPI_BROADCAST : std_logic_vector(3 downto 0) := "0111"; + constant MPI_INIT : std_logic_vector(3 downto 0) := "1000"; + constant MPI_SPWAN : std_logic_vector(3 downto 0) := "1001"; + + constant MPI_WINCREATE : std_logic_vector(3 downto 0) := "1010"; + constant MPI_WINCOMPLETE : std_logic_vector(3 downto 0) := "1011"; + constant MPI_WINPOST : std_logic_vector(3 downto 0) := "1100"; + constant MPI_WINWAIT : std_logic_vector(3 downto 0) := "1101"; + + + + constant MPI_WTIME + constantMPI_WTICK + constant MPI_CONFIG : std_logic_vector(3 downto 0) := "1101"; + --paramètres des commandes + Constant INIT_SEEKMAIN : std_logic_vector(3 downto 0) := "0001"; + Constant INIT_SETRANK : std_logic_vector(3 downto 0) := "0010"; + Constant INIT_REGISTER : std_logic_vector(3 downto 0) := "0011"; +-- constantes pour le NoC + Constant NOC_GETPORTID : std_logic_vector(7 downto 0) := "00000001"; + + +Type MPI_Datatype is (MPI_BYTE,MPI_INTEGER,MPI_REAL,MPI_PACKET, MPI_pointer); +SUBType MPI_COMM is natural range 0 to 2**ADRLEN-1 ; --pointeur sur la structure du communicateur +subType Mpi_AInt is natural range 0 to 2**ADRLEN-1 ; + +Type MPI_COMM_struc is record + id : natural range 0 to 3; -- id du communicateur + grp : std_logic_vector(15 downto 0); --groupe associé au communicateur + nproc : natural range 0 to 15; -- nombre de membres du groupe de ce communicateur + AddrLib : std_logic_vector(15 downto 0); -- adresse dans la mémoire de la Lib + -- des registres GStart et GPost + C_open,C_close : std_logic; -- état du communciateur (Inistialisé ou finalisé) +end record; + +Type Mpi_Win is record + status : std_logic_vector(7 downto 0); --état de la fenêtre (create,Start,Complete,Post,WaitSync, etc.) + id : natural range 0 to 15 ; -- numéro de la fenêtre + + Addr : std_logic_vector(15 downto 0); -- adresse dans la mémoire locale du PE + Size : natural range 0 to 65535; -- taille de la fenêtre en octets + + comm : MPI_COMM; -- communicateur associé à la fenêtre +end record; +Type Mpi_group is record + grp : std_logic_vector(15 downto 0); --( vecteur de la liste des processus du groupe) + nb : natural range 0 to 15; -- nombre de membres(processus du groupe) + comm_id : natural range 0 to 3; -- reférence du communicateur +end record; +end Packet_type; + +package body Packet_type is + + +end Packet_type; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Processing_node.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Processing_node.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Processing_node.vhd (revision 29) @@ -0,0 +1,397 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 01:27:32 04/20/2012 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/MPICORETEST.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: MPI_NOC +-- +-- Dependencies: +-- +-- Revision: 11 Juillet 2012 +-- Revision 0.01 - File Created +-- Additional Comments : entité de test de l'environement MPSOC il est constitué d'une +--MAE simulant le processeur +-- Notes: +-- +-- +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +library NocLib ; +--use IEEE.STD_LOGIC_ARITH.ALL; +--use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +USE ieee.numeric_std.ALL; + +ENTITY PROCESSING_ELEMENT IS +-- entité du processeur du MPI +port ( clk : in std_logic; + reset : in std_logic; + ram_we : in std_logic; + ram_ena : in std_logic; + ram_enb : in std_logic; + ram_do : out std_logic_vector( downto ); --word - 1 downto 0 + ram_din : in std_logic_vector(word - 1 downto 0);--word - 1 downto 0 + ram_addra : out std_logic_vector(ADRLEN - 1 downto 0);-- ADRLEN - 1 downto 0 + ram_addrb : out std_logic_vector(ADRLEN - 1 downto 0);-- ADRLEN - 1 downto 0 + instruction_en : out std_logic; + hold_request : in std_logic; + hold_ack : out std_logic; + ram_sel : out std_logic; + lib_ready : in std_logic; + lib_initialized : in std_logic; + ); +END PROCESSING_ELEMENT; + +ARCHITECTURE behavior OF PROCESSING_ELEMENT IS + + --données du programme PE + signal SrcAdr0, SrcAdr1, destAdr0, destAdr1, Datalen : std_logic_vector(word - 1downto 0);-- + signal dpid,dpid_i : natural range 0 to 15; + --signaux pour la gestion de la MAE + type typ_mae is (InitApp,InitCompleted,writeptr, putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); + signal dcount : natural range 0 to 255:= 0; --permet de compter le packet de données envoyées + signal count,count_i : natural range 0 to 15:=0; +--signal adresse,adresse_rd :natural range 0 to 65536; + signal etPutGet : typ_mae; + signal Ram_busy :std_logic:='0'; + --constant pour la construction du fichier + -- ces lignes devront être commentées lors de l'assemblage final +BEGIN + + +dpid<=dpid_i; + pPutGet : process(clk) + + variable bfill,destrank,pid,mport : natural range 0 to 15; + variable fsrc,ret : natural range 0 to 15:=0; + variable timeout : natural range 0 to 255; + variable adrToset : std_logic_vector(15 downto 0); + variable adresse,adresse_rd :natural range 0 to 65536; + begin + if (clk'event and clk ='1') then + if reset='1' then + etputget<= InitApp; + adresse:=0; + adresse_rd:=0; + timeout:=0; + dcount<=0; + else + case etputget is + + when InitApp => + --code pour Init ici + --mettre mpi_init à l'adresse mpi + --initialisation du module mpi du pn + ram_do <=MPI_INIT & x"0" ; + fsrc:=1; + adrToSet:=std_logic_vector(to_unsigned(core_init_adr,16)); + if ret/=fsrc then + dcount<=0; + etputget<=writeptr; + adresse:=core_base_adr+2; + else + adresse:=core_init_adr; + etputget<= InitCompleted; + end if; + + when writeptr => + + if PE_Hold_req = '0' then --s'assurer que le bus est disponible + if dcount=0 then + ram_do <=AdrToSet(7 downto 0); + dcount <=dcount+1; + --adresse:=adresse+1; --prépare la prochaine écriture + elsif dcount=1 then + dcount <=dcount+1; + adresse:=adresse+1; --prépare la prochaine écriture + ram_do <=AdrToSet(15 downto 8); + elsif dcount=2 then -- ce cycle permet juste de vider le tampon d'écriture en RAM + ret:=fsrc; + dcount<=0; + timeout:=0; + if fsrc=1 then + etputget <= InitApp; + elsif fsrc=2 then + etputget <= putdata; + elsif fsrc=3 then + etputget <= getdata; + else + etputget <= start; + end if; + + end if; + + end if; + when InitCompleted => + if Lib_Init='1' then + etputget <= putdata; + end if; + when putdata => --construire le packet pour le Put + DestRank:=1; + adresse_rd:=core_base_adr+Core_Rank2port_base+DestRank; + timeout:=0; + dcount<=0; + fsrc:=2; + adrToSet:=std_logic_vector(to_unsigned(core_put_adr,16)); + if ret/=fsrc then + etputget<=writeptr; + ret:=0; + else + etputget<= putdata2; + end if; + + when putdata2 => + if dcount<5 then + dcount<=dcount+1; + if dcount=0 then + adresse:=core_put_adr; + ram_do <=MPI_PUT & std_logic_vector(to_unsigned(Dpid,4)); + elsif dcount=1 then + adresse:=core_put_adr+dcount; + ram_do <=SrcAdr1 ; + elsif dcount=2 then + adresse:=core_put_adr+dcount; + ram_do <=SrcAdr0 ; + elsif dcount=3 then + adresse:=core_put_adr+dcount; + ram_do <=DestAdr1 ; + elsif dcount=4 then + adresse:=core_put_adr+dcount; + ram_do <=DestAdr0 ; + elsif dcount=5 then + adresse:=core_put_adr+dcount; + ram_do <=Datalen ; + end if; + else + adresse:=core_base_adr+1; + adresse_rd:=core_base_adr; + ram_do <=x"01"; --instruction pulse enable; + if ram_din(1)='1' then -- Instruction ack + if PE_Hold_Req='0' then + adresse:=core_base_adr+1; + ram_do <=x"00"; --ramener le IPulse à 0; + etPutGet<=putcompleted; + else + + end if; + end if; + end if; + + when putcompleted => + adresse_rd:=core_put_adr+6; + if ram_din(0)='1' then --Put completed + etPutGet<=GetData; + end if; + when getdata => --positionnement du mot de longueur des données + adresse:=core_get_adr; + DestRank:=1; + timeout:=0; + dcount<=0; + fsrc:=3; + adrToSet:=std_logic_vector(to_unsigned(core_get_adr,16)); + if ret/=fsrc then + + etputget<=writeptr; + ret:=0; + else + etputget<= getdata2; + end if; + + when getdata2 => + if dcount<5 then + dcount<=dcount+1; + if dcount=0 then + adresse:=core_get_adr; + ram_do <=MPI_GET & std_logic_vector(to_unsigned(Dpid,4)); + adresse:=core_get_adr+dcount; + ram_do <=SrcAdr1 ; + elsif dcount=2 then + adresse:=core_get_adr+dcount; + ram_do <=SrcAdr0 ; + elsif dcount=3 then + adresse:=core_get_adr+dcount; + ram_do <=DestAdr1 ; + elsif dcount=4 then + adresse:=core_get_adr+dcount; + ram_do <=DestAdr0 ; + elsif dcount=5 then + adresse:=core_get_adr+dcount; + ram_do <=Datalen; + end if; + else + adresse:=core_base_adr+1; + adresse_rd:=core_base_adr; + ram_do <=x"01"; --instruction pulse enable; + if ram_din(1)='1' then -- Instruction ack + etPutGet<=getcompleted; + else + + end if; + end if; + + when getcompleted => + adresse_rd:=core_get_adr+6; + if ram_din(0)='1' then --Put completed + if PE_Hold_Req='0' then + adresse:=core_base_adr+1; + ram_do <=x"00"; --ramener le IPulse à 0; + etPutGet<=Terminate; + else + timeout:=timeout+1; + end if; + end if; + + + when terminate => + + + etputget<=start; + + when st_timeout => + + --if ram_busy='1' then + etputget<=start; + --end if + etputget<=start; + end case; + ram_addra <=STD_LOGIC_VECTOR(to_unsigned(adresse,16)); + ram_addrb <=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16)); + end if; --reset='1' + end if; + end process pPutGet; + +majPutGet:process (etputget) + + begin + case etputget is + when start => + ram_we <='0'; + ram_ena<='0'; + ram_enb<='0'; + instruction_en<='0'; + + when fillmem => + ram_we <='1'; + ram_ena<='1'; + + ram_enb<='0'; + instruction_en<='0'; + when nextfill => + ram_we <='1'; + ram_ena<='1'; + ram_enb<='0'; + instruction_en<='0'; + when InitApp => + ram_we <='1'; + ram_ena<='1'; + ram_enb<='0'; + instruction_en<='0'; + when Initcompleted => + instruction_en<='1'; + when writeptr => + ram_we <='1'; --écriture dans la RAM + ram_ena <='1'; + + ram_enb <='0'; + -- dcount<=dcount+1; + + instruction_en<='0'; + + when putdata => --positionnement du mot de longueur des données + --dcount<=0; + srcadr0<=X"00"; + srcadr1<=X"01"; + destadr0<=X"00"; + destadr1<=X"02"; + ram_we <='0'; + ram_ena<='0'; + --lecture du n° de port de destination + ram_enb<='1'; + datalen<=std_logic_vector(to_unsigned(50,8)); + dpid_i<=to_integer(unsigned(ram_din(3 downto 0))); --le port est situé ur les 4 bits de poids faible + instruction_en<='0'; + when putdata2 => + ram_we <='1'; --écriture dans la RAM + ram_ena <='1'; + + ram_enb <='0'; + -- dcount<=dcount+1; + if dcount=5 then + instruction_en<='1'; + else + instruction_en<='0'; + end if; + when putcompleted => + ram_we <='1'; + ram_ena <='1'; + -- lecture du résultat + ram_enb <='1'; + instruction_en<='1'; + when getdata => + --dcount<=0; + srcadr0<=X"00"; + srcadr1<=X"02"; + destadr0<=X"00"; + destadr1<=X"03"; + datalen<=std_logic_vector(to_unsigned(50,8)); + instruction_en<='0'; + when getdata2 => + ram_we <='1'; --écriture dans la RAM + ram_ena <='1'; + + ram_enb <='0'; + --dcount<=dcount+1; + if dcount=5 then + instruction_en<='1'; + else + instruction_en<='0'; + end if; + when getcompleted => + ram_we <='1'; + ram_ena <='1'; + -- lecture du résultat + ram_enb <='1'; + instruction_en<='1'; + when terminate => + + ram_we <='0'; + ram_ena<='0'; + ram_enb<='0'; + instruction_en<='0'; + + when st_timeout => + ram_we <='0'; + ram_ena<='0'; + ram_enb<='0'; + instruction_en <='0'; + end case; +end process majPutGet ; + + hold:process (clk) + begin + if rising_edge(clk) then + if reset='1' then + hold_ack<='0'; + else + if hold_request ='1' then + ramsel<='1'; + pe_hold_ack<= '1';--not(ram_busy); --si la mémoire est occupé, forcé une libération + else + pe_hold_ack<='0'; + ramsel<='0'; + end if; + end if; + end if; + end process hold; +END; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/RAM_32_32.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/RAM_32_32.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/RAM_32_32.vhd (revision 29) @@ -0,0 +1,92 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM NGOUNOU +-- +-- Create Date: 18:33:31 03/05/2012 +-- Design Name: +-- Module Name: RAM_32_32 - Behavioral +-- Project Name: MPI_Core +-- Target Devices: +-- Tool versions: +-- Description: permet de stocker les données locales de la librairie MPI +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RAM_v is +generic(width : positive:=32; Size:positive:=16); +Port ( clka, clkb : in std_logic; + wea : in std_logic; + ena, enb : in std_logic; + addra, addrb : in std_logic_vector(size-1 downto 0); --cinq lignes d'adresse + dia : in std_logic_vector(width-1 downto 0); + dob : out std_logic_vector(width-1 downto 0)); +end RAM_v; + +architecture Behavioral of RAM_v is + signal Lra,Lrb :std_logic:='0'; + signal sel : std_logic_vector(1 downto 0); + signal doa,dout : std_logic_vector(width-1 downto 0); + type ram_type is array (2**size-1 downto 0) of std_logic_vector (width-1 downto 0); + signal RAM: ram_type; +begin + process (clka) + begin + if clka'event and clka = '1' then + if ena = '1' then + if wea = '1' then + RAM(conv_integer(addra)) <= dia; + end if; + + doa<=RAM(conv_integer(addrb)); + Lra<='1'; + else + if lrb='1' then + Lra<='0'; + end if; + end if; + end if; + end process; + + + process (clkb) + begin + if clkb'event and clkb = '1' then + if enb = '1' then + Lrb<='1'; + dout <= RAM(conv_integer(addrb)) ; + else + if Lra='1' then + Lrb<='0'; + end if; + end if; + end if; + end process; + + sel<=(Lra,Lrb); + With sel select + dob <=dout when "11", + doa when "10", + dout when "01", + dout when "00", + dout when others; + +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/RAM_64.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/RAM_64.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/RAM_64.vhd (revision 29) @@ -0,0 +1,67 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: KIEGAING EMMANUEL GEL EN 5 +-- +-- Create Date: 18:54:08 04/19/2011 +-- Design Name: +-- Module Name: RAM_64 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: SYNTHESE d'une RAM 64 octet par inferation +-- la ram possède un port d'écriture et un port de lecture +-- le port primaire est à lecture et ecrite et le port secondaire à lecture seule +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +Library NocLib; +use NocLib.CoreTypes.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RAM_64 is + Port ( clka, clkb : in std_logic; + wea : in std_logic; + ena, enb : in std_logic; + addra, addrb : in std_logic_vector(5 downto 0); + dia : in std_logic_vector(Word-1 downto 0); + dob : out std_logic_vector(Word-1 downto 0)); +end RAM_64; + +architecture Behavioral of RAM_64 is + type ram_type is array (63 downto 0) of std_logic_vector (Word-1 downto 0); + signal RAM: ram_type; +begin + process (clka) + begin + if clka'event and clka = '1' then + if ena = '1' then + if wea = '1' then + RAM(conv_integer(addra)) <= dia; + end if; + end if; + end if; + end process; + + process (clkb) + begin + if clkb'event and clkb = '1' then + if enb = '1' then + --dob <= RAM(conv_integer(addrb)) ; + end if; + end if; + end process; + dob <= RAM(conv_integer(addrb)) ; +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/RAM_MUX.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/RAM_MUX.vhd (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/RAM_MUX.vhd (revision 29) @@ -0,0 +1,96 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:45:28 07/26/2012 +-- Design Name: +-- Module Name: RAM_MUX - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- Multiplexeur de la memoire du noeud +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +library NocLib ; +--use IEEE.STD_LOGIC_ARITH.ALL; +--use IEEE.STD_LOGIC_UNSIGNED.ALL; +use NocLib.CoreTypes.all; +use work.Packet_type.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +USE ieee.numeric_std.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RAM_MUX is + Port ( ram_ena_in : in STD_LOGIC_VECTOR (1 downto 0); + ram_enb_in : in STD_LOGIC_VECTOR (1 downto 0); + ram_we_in : in STD_LOGIC_VECTOR (1 downto 0); + ram_dina_in_0 : in STD_LOGIC_VECTOR (word - 1 downto 0); + ram_dina_in_1 : in STD_LOGIC_VECTOR (word - 1 downto 0); + ram_addra_in_0 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_addra_in_1 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_addrb_in_0 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_addrb_in_1 : in STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_dob_in : in STD_LOGIC_VECTOR (word - 1 downto 0); + + + ram_ena_out : out STD_LOGIC; + ram_enb_out : out STD_LOGIC; + ram_we_out : out STD_LOGIC; + ram_dina_out : out STD_LOGIC_VECTOR (word - 1 downto 0); + ram_addra_out : out STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_addrb_out : out STD_LOGIC_VECTOR (ADRLEN - 1 downto 0); + ram_dob_out_0 : out STD_LOGIC_VECTOR (word - 1 downto 0); + ram_dob_out_1 : out STD_LOGIC_VECTOR (word - 1 downto 0); + sel : in std_logic + ); +end RAM_MUX; + +architecture Behavioral of RAM_MUX is + +begin + +mux : process(sel,ram_ena_in,ram_enb_in ,ram_we_in,ram_dina_in_0, ram_dina_in_1,ram_addra_in_0,ram_addra_in_1, ram_addrb_in_0, ram_addrb_in_1, ram_dob_in) + begin + + if sel = '1' then + -- si sel est à 1 les entrées 1 sont sur les sorties correspondantes + ram_ena_out <= ram_ena_in(1); + ram_enb_out <= ram_enb_in(1); + ram_we_out <= ram_we_in(1); + ram_dina_out <= ram_dina_in_1; + ram_addra_out <= ram_addra_in_1; + ram_addrb_out <= ram_addrb_in_1 ; + ram_dob_out_1 <= ram_dob_in; + ram_dob_out_0 <= (others => '0'); + else + -- si est à 0 les entrées 0 sont sur les sorties correspondantes + ram_ena_out <= ram_ena_in(0); + ram_enb_out <= ram_enb_in(0); + ram_we_out <= ram_we_in(0); + ram_dina_out <= ram_dina_in_0; + ram_addra_out <= ram_addra_in_0; + ram_addrb_out <= ram_addrb_in_0 ; + ram_dob_out_0 <= ram_dob_in; + ram_dob_out_1 <= (others => '0'); + + end if; + + + end process; + + +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/TestPutGet.wcfg =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/TestPutGet.wcfg (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/TestPutGet.wcfg (revision 29) @@ -0,0 +1,166 @@ + + + + + + + + + + + + + + + + + + + + reset + reset + + + ram_we + ram_we + + + ram_ena + ram_ena + + + ram_enb + ram_enb + + + ramsel + ramsel + + + pe_instr_en + pe_instr_en + + + pe_ram_we + pe_ram_we + + + pe_ram_ena + pe_ram_ena + + + pe_ram_enb + pe_ram_enb + + + clkm + clkm + + + etputget + etputget + + + ram_din[7:0] + ram_din[7:0] + HEXRADIX + + + ram_addra[15:0] + ram_addra[15:0] + HEXRADIX + + + ram_addrb[15:0] + ram_addrb[15:0] + HEXRADIX + + + ram_do[7:0] + ram_do[7:0] + HEXRADIX + + + pe_ram_do[7:0] + pe_ram_do[7:0] + HEXRADIX + + + pe_ram_din[7:0] + pe_ram_din[7:0] + HEXRADIX + + + pe_ram_addra[15:0] + pe_ram_addra[15:0] + HEXRADIX + + + pe_ram_addrb[15:0] + pe_ram_addrb[15:0] + HEXRADIX + + + etloadinst + etloadinst + + + ilatch + ilatch + + + iack + iack + + + fifo_wr + fifo_wr + + + fifo_din[7:0] + fifo_din[7:0] + HEXRADIX + + + pe_hold_ack + pe_hold_ack + + + pe_hold_req + pe_hold_req + + + lib_ready + lib_ready + + + lib_init + lib_init + + + mpi_node_in[1:2] + mpi_node_in[1:2] + HEXRADIX + + + mpi_node_out[1:2] + mpi_node_out[1:2] + HEXRADIX + + + ex1_state_mach + ex1_state_mach + + + fifo_data_out[7:0] + fifo_data_out[7:0] + + + instruction_ack_i + instruction_ack_i + + + instruction_ack + instruction_ack + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Test_Du_NOc.wcfg =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Test_Du_NOc.wcfg (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/Test_Du_NOc.wcfg (revision 29) @@ -0,0 +1,422 @@ + + + + + + + + + + + + + + + + + + + etsnd1 + etsnd1 + + + etsnd2 + etsnd2 + + + etsnd3 + etsnd3 + + + etrec + etrec + + + etcmd + etcmd + + + portin[1:8] + portin[1:8] + + + pipeline_latch[7:0] + pipeline_latch[7:0] + + + cmd_data_signal[7:0] + cmd_data_signal[7:0] + + + cmdstate + cmdstate + + + rdata_out_en[8:1] + rdata_out_en[8:1] + + + data_out_en[8:1] + data_out_en[8:1] + + + dat_data_out_pulse + dat_data_out_pulse + + + data_out_pulse + data_out_pulse + + + fifo_read_signal + fifo_read_signal + + + fifo_read_signal + fifo_read_signal + + + pop_state + pop_state + + + fifo_read_signal + fifo_read_signal + + + etrec + etrec + + + etcmd + etcmd + + + data_available[8:1] + data_available[8:1] + + + cdata_out_en[8:1] + cdata_out_en[8:1] + + + din4[8:1] + din4[8:1] + + + portout[1:8] + portout[1:8] + + + clk + clk + + + fifo_out_signal[7:0] + fifo_out_signal[7:0] + + + fifo_out_signal[7:0] + fifo_out_signal[7:0] + + + fifo_out_signal[7:0] + fifo_out_signal[7:0] + + + pop_state + pop_state + + + cmd_in_en + cmd_in_en + + + wr_en_signal + wr_en_signal + + + rd_en_signal + rd_en_signal + + + clk_signal + clk_signal + + + doa_signal[7:0] + doa_signal[7:0] + + + din[7:0] + din[7:0] + + + fifo_counter[7:0] + fifo_counter[7:0] + + + fifo_counter[7:0] + fifo_counter[7:0] + + + data_in_en[8:1] + data_in_en[8:1] + + + cmd_in_en[8:1] + cmd_in_en[8:1] + + + grant[8:1] + grant[8:1] + + + grant[8:1] + grant[8:1] + + + fifo_read_signal + fifo_read_signal + + + data_counter[7:0] + data_counter[7:0] + + + data_counter[7:0] + data_counter[7:0] + + + data_counter[7:0] + data_counter[7:0] + + + data_counter[7:0] + data_counter[7:0] + + + rdata_out_en[8:1] + rdata_out_en[8:1] + + + rcount[1:8] + rcount[1:8] + + + cdata_out_en[8:1] + cdata_out_en[8:1] + + + reset + reset + + + din1[8:1] + din1[8:1] + + + din2[8:1] + din2[8:1] + + + din3[8:1] + din3[8:1] + + + din4[8:1] + din4[8:1] + + + fifo_in_full[8:1] + fifo_in_full[8:1] + + + fifo_in_empty[8:1] + fifo_in_empty[8:1] + + + data_available[8:1] + data_available[8:1] + + + time_out[8:1] + time_out[8:1] + + + header[7:0] + header[7:0] + + + fwft_fsm_state + fwft_fsm_state + + + empty + empty + + + fwft_fsm_state + fwft_fsm_state + + + push_address_counter[7:0] + push_address_counter[7:0] + + + pop_address_counter[7:0] + pop_address_counter[7:0] + + + doa_signal[7:0] + doa_signal[7:0] + + + wr_en_signal + wr_en_signal + + + din[7:0] + din[7:0] + + + empty_signal + empty_signal + + + rd_ready[1:0] + rd_ready[1:0] + + + dob_signal[7:0] + dob_signal[7:0] + + + dout_signal[7:0] + dout_signal[7:0] + + + full_signal + full_signal + + + wr_en_signal + wr_en_signal + + + rd_en_signal + rd_en_signal + + + clk_signal + clk_signal + + + din[7:0] + din[7:0] + + + doa_signal[7:0] + doa_signal[7:0] + + + counter_en + counter_en + + + push_address_counter[7:0] + push_address_counter[7:0] + + + pop_address_counter[7:0] + pop_address_counter[7:0] + + + dout[7:0] + dout[7:0] + + + fwft_fsm_state + fwft_fsm_state + + + fifo_out_signal[7:0] + fifo_out_signal[7:0] + + + wr_en_signal + wr_en_signal + + + rd_en_signal + rd_en_signal + + + din[7:0] + din[7:0] + + + push_address_counter[7:0] + push_address_counter[7:0] + + + pop_address_counter[7:0] + pop_address_counter[7:0] + + + fifo_counter[7:0] + fifo_counter[7:0] + + + dout[7:0] + dout[7:0] + + + empty_signal + empty_signal + + + doa_signal[7:0] + doa_signal[7:0] + + + dob_signal[7:0] + dob_signal[7:0] + + + empty + empty + + + fwft_fsm_state + fwft_fsm_state + + + din[7:0] + din[7:0] + + + rd_en_signal + rd_en_signal + + + counter_en + counter_en + + + dob_signal[7:0] + dob_signal[7:0] + + + doa_signal[7:0] + doa_signal[7:0] + + + dout[7:0] + dout[7:0] + + + wr_en_signal + wr_en_signal + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/_xmsgs/netgen.xmsgs =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/_xmsgs/netgen.xmsgs (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/_xmsgs/netgen.xmsgs (revision 29) @@ -0,0 +1,12 @@ + + + +The generated VHDL netlist contains Xilinx UNISIM simulation primitives and has to be used with UNISIM library for correct compilation and simulation. + + + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/compxlib.cfg =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/compxlib.cfg (revision 29) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/compxlib.cfg (revision 29) @@ -0,0 +1,216 @@ +#***************************************************************** +# d:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe configuration file - compxlib.cfg +# Mon Oct 01 18:11:12 2012 +# +# Important :- +# All options/variables must start from first column +# +#***************************************************************** + +# +RELEASE_VERSION:12.3 +# +RELEASE_BUILD:M.70d +# +# set current simulator name +SIMULATOR_NAME:mti_se +# +# set current language name +LANGUAGE_NAME:vhdl +# +# set compilation execution mode +EXECUTE:on +# +# print compilation command template in log file +LOG_CMD_TEMPLATE:off +# +# Hierarchical Output Directories +HIER_OUT_DIR:off +# +# print Pre-Compiled library info +PRECOMPILED_INFO:on +# +# create backup copy of setup files +BACKUP_SETUP_FILES:on +# +# use enhanced compilation techniques for faster library compilation +# (applicable to selected libraries only) +FAST_COMPILE:on +# +# save compilation results to log file with the name specified with -log option +ADD_COMPILATION_RESULTS_TO_LOG:on +# +# abort compilation process if errors are detected in the library +ABORT_ON_ERROR:off +# +# compile library in the directory specified by the environment variable if the +# -dir option is not specified +OUTPUT_DIR_ENV: +# +#/////////////////////////////////////////////////////////////////////// +# Setup file name: ModelSim SE +SET:mti_se:MODELSIM=modelsim.ini +# +# ModelSim SE options for VHDL Libraries +# Syntax:- +# OPTION:::: +# :- u (unisim) s (simprim) c (xilinxcorelib) +# r (coolrunner) +# vcom -work