| MPI_CORE_COMPONENTS Project Status | |||
| Project File: | MPI_CORE_COMPONENTS.ise | Implementation State: | Synthesized |
| Module Name: | CORE_MPI |
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No Errors |
| Target Device: | xc3s1200e-4fg320 |
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151 Warnings |
| Product Version: | ISE 11.1 |
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| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slices | 213 | 8672 | 2% | |
| Number of Slice Flip Flops | 137 | 17344 | 0% | |
| Number of 4 input LUTs | 470 | 17344 | 2% | |
| Number of bonded IOBs | 63 | 250 | 25% | |
| Number of GCLKs | 1 | 24 | 4% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | mar. 21. juin 10:30:03 2011 | 0 | 151 Warnings | 37 Infos | |
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |