Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX1_FSM.vhd
===================================================================
--- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX1_FSM.vhd	(revision 35)
+++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX1_FSM.vhd	(revision 39)
@@ -56,4 +56,5 @@
 			  fifo_empty : in  STD_LOGIC;
            fifo_data_out : in  STD_LOGIC_VECTOR (7 downto 0);
+			  fifo_src :      in STD_LOGIC; --permet de désigner le fifo qui est en service
 
 												-- Accès au réseau sur puce
@@ -90,5 +91,5 @@
 signal packet_length : std_logic_vector(Word-1 downto 0);
 signal src_address : std_logic_vector(ADRLEN-1 downto 0);
-signal Wr_ok,rd_ok:std_logic:='0';
+signal dma_rd,dma_wr,Wr_ok,rd_ok:std_logic:='0';
 --signal res_address : std_logic_vector(15 downto 0);
 signal dest_address : std_logic_vector(ADRLEN-1 downto 0);
@@ -217,30 +218,69 @@
 												end if;
 										 else
+												Wr_Ok<='0';
 											ex1_state_mach <= execute_put4;
 										end if;	
-			when execute_put4 => if dma_wr_grant = '1' then -- fin du mpi_put
+			when execute_put4 => if dma_rd_grant = '1' then -- fin du mpi_put
 										   ex1_state_mach <= execute_put5;
 											n<="0000";
 											data_to_send<="00000001";
-											rd_ok<='1';
-											wr_ok<='0';
 										  else
 											ex1_state_mach <= execute_put4;
 								      end if;
+										rd_ok<='1';
+										wr_ok<='0';
 										src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-			when execute_put5 => 
-											if n=0 then
+	
+			when execute_put5 =>  if n <6 then     
+			
+												dma_wr<='1';  --demander un accès exclusif au bus
+												dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
+											else
+												dma_wr<='0';										
+												dma_rd<='0';
+											end if;
+										
+										if n=0 then
 												if dma_rd_grant='1' then
-													n<=n+1;
-													tempval:=Ram_data_in;
-													src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-													tempval(5):='1';			-- SET du bit DSENT
-													data_to_send<=tempval;
-													
+												n<=n+1;
+												
 												end if;
 												rd_ok<='1';
 												wr_ok<='0';
+												dma_wr<='1';										
+												dma_rd<='1';
 											elsif n=1 then
-												if dma_wr_grant = '1'  then
+												if dma_rd_grant='1' then
+													n<=n+1;
+													dma_wr<='1';
+													end if;
+													rd_ok<='1';
+													wr_ok<='0';
+																							
+													dma_rd<='1';
+											elsif n=2 then
+												if dma_rd_grant='1' and dma_wr_grant='1' then
+													n<=n+1;
+													tempval:=Ram_data_in;
+													src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
+													if fifo_src='0' then -- c'est un put qui est exécuté
+														tempval(5):='1';			-- SET du bit DSENT
+													else  -- c'est un Get qui est exécuté
+														tempval(2):='0';  --annuler le sending après un GET
+													end if;
+													data_to_send<=tempval;
+													rd_ok<='0';
+													wr_ok<='1';
+													dma_wr<='1';										
+													dma_rd<='1';
+												else
+												rd_ok<='1';
+												wr_ok<='0';
+												dma_rd<='0'; --libérer le bus et revenir en arrière
+												dma_wr<='0';
+												n<=n-1;
+												end if;
+											elsif n=3 then
+												if dma_wr_grant = '1' and dma_rd_grant='1' then
 													n<=n+1;
 													
@@ -249,6 +289,8 @@
 													rd_ok<='0';
 													wr_ok<='1';
-											elsif n=2 then
-												if dma_wr_grant = '1'  then
+													dma_wr<='1';										
+													dma_rd<='1';
+											elsif n=4 then
+												if dma_wr_grant = '1' and dma_rd_grant='1' then
 													n<=n+1;
 																								
@@ -258,5 +300,7 @@
 													rd_ok<='0';
 													wr_ok<='1';	
-											elsif n=3 then
+													dma_wr<='1';										
+													dma_rd<='0';
+											elsif n=5 then
 													if dma_wr_grant = '1'  then
 														n<=n+1;
@@ -267,9 +311,13 @@
 														rd_ok<='0';
 														wr_ok<='1';
-											elsif n=4 then
+														dma_wr<='1';										
+														dma_rd<='0';
+											elsif n=6 then
 														n<="0000";
 														ex1_state_mach <= fifo_select;
 														rd_ok<='0';
 														wr_ok<='0';
+														dma_wr<='0';										
+														dma_rd<='0';
 											end if;
 										 
@@ -302,42 +350,90 @@
 											   data_to_send <= dest_address(7 downto 0);
 												n <= n + 1;
+												ex1_state_mach <= execute_get1;
+											 elsif switch_port_in_full = '0' and n = 7 then
 												ex1_state_mach <= execute_get2;
+												n<="0000";
 												 else
 												  ex1_state_mach <= execute_get1;
 								      end if;	
-			when execute_get2 => if switch_port_in_full = '0' then
+			when execute_get2 => if dma_wr_grant = '1'  then
 										 ex1_state_mach <= execute_get3;
+										 src_address<=std_logic_vector(to_unsigned(core_get_adr+6,16));
+										data_to_send<="00000001";
 										else
 										 ex1_state_mach <= execute_get2;
-								end if;	
+										 wr_ok<='1';
+										end if;
+										
 			when execute_get3 => if dma_wr_grant = '1' then -- fin du post de mpi_get
 										   ex1_state_mach <= execute_get4;
 											n<="0000";
 											data_to_send<="00000001";
+											wr_ok<='0';
+											rd_ok<='1';
 										  else
 											ex1_state_mach <= execute_get3;
 								      end if;
 										src_address<=std_logic_vector(to_unsigned(core_get_adr+6,16));
-			when execute_get4 => 
-											if n=0 then
-												if  dma_rd_grant='1' then
-													n<=n+1;
-													tempval:=Ram_data_in;
+			when execute_get4 => 	if n=0 then
+											
+												if dma_rd_grant='1' then
+													n<=n+1;
+													
+													end if;
+													rd_ok<='1';
+													wr_ok<='0';
+													dma_wr<='1';										
+													dma_rd<='1';
+											elsif n=1 then
+												src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
+												if dma_rd_grant='1' then
+													n<=n+1;
+													
+													end if;
+													rd_ok<='1';
+													wr_ok<='0';
+													dma_wr<='1';										
+													dma_rd<='1';
+											elsif n=2 then
+												if  dma_rd_grant='1'  then
+													n<=n+1;
+													
 													src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
 												end if;
-												elsif n=1 then
-													n<=n+1;
+													dma_wr<='1';										
+													dma_rd<='1';
+											elsif n=3 then
+													if  dma_rd_grant='1' and dma_wr_grant='1' then
+													n<=n+1;
+													tempval:=Ram_data_in;
+													rd_ok<='0';
+													wr_ok<='1';
+													dma_wr<='1';										
+													dma_rd<='1';
+													else 
+														dma_wr<='0';										
+														dma_rd<='0';
+														n<=n-1;
+													end if;
 													src_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-												elsif n=2 then
-													if dma_wr_grant = '1'  then
+												elsif n=4 then
+													if dma_wr_grant = '1' and dma_rd_grant='1' then
 													n<=n+1;
 													
-													tempval(4):='0';			--RESET du bit DReceived
+													--tempval(4):='0';			--RESET du bit DReceived
 													tempval(1):='1';			-- SET du bit DReceiving
 													data_to_send<=tempval;
+													else
+													rd_ok<='0';
+													wr_ok<='1';
 													end if;
-												elsif n=3 then
+													dma_wr<='1';										
+													dma_rd<='1';
+												elsif n=5 then
 													n<="0000";
 												ex1_state_mach <= fifo_select;
+												dma_wr<='0';										
+												dma_rd<='0';
 												end if;
 										
@@ -536,10 +632,10 @@
 										  fifo_rd_en <= '0';
 								        switch_port_in_data <= data_to_send;
-								        switch_port_in_wr_en <= not(switch_port_in_full);
+								        switch_port_in_wr_en <='0';
 								        AppInitReq<='0';
 								        Ram_rd<='0';
 										Ram_wr<='0';
 								        dma_rd_request <= '0';
-										  dma_wr_request <= '0';
+										  dma_wr_request <= Wr_ok;
 										  Ram_rd<='0';
 										  Ram_wr<='0';
@@ -565,8 +661,8 @@
 								        switch_port_in_wr_en <= '0';
 								        AppInitReq<='0';
-								        dma_rd_request <= '1';
-										  dma_wr_request <= '1';
-											Ram_rd<='1';
-											Ram_wr<='1';
+								        dma_rd_request <= dma_rd;
+										  dma_wr_request <= dma_wr;
+											Ram_rd<=rd_ok;
+											Ram_wr<=wr_ok;
 											Ram_data_out<=data_to_send; --"00000001";
 											Result <=(2=>'1',others=>'0'); --get completed
@@ -613,8 +709,8 @@
 								        switch_port_in_wr_en <= '0';
 								        AppInitReq<='0';
-								        dma_rd_request <= '0';
-										  dma_wr_request <= '1';
-											Ram_rd<='0';
-											Ram_wr<='1';
+								        dma_rd_request <= rd_ok;
+										  dma_wr_request <= wr_ok;
+											Ram_rd<=rd_ok;
+											Ram_wr<=wr_ok;
 											Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution 
 											--result(1)<='1'; 
@@ -625,6 +721,6 @@
 								        switch_port_in_wr_en <= '0';
 								        AppInitReq<='0';
-								        dma_rd_request <= rd_ok;
-										  dma_wr_request <= wr_ok;
+								        dma_rd_request <= dma_rd;
+										  dma_wr_request <= dma_wr;
 											Ram_rd<=rd_ok;
 											Ram_wr<=wr_ok;
