Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX2_FSM.vhd
===================================================================
--- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX2_FSM.vhd	(revision 29)
+++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/EX2_FSM.vhd	(revision 39)
@@ -91,5 +91,5 @@
 signal data_to_write_fifo :  std_logic_vector(Word-1 downto 0);
 signal Ex2_on : std_logic:='0';
-signal rd_ok ,wr_ok:std_logic:='0';
+signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0';
 
 begin
@@ -169,19 +169,17 @@
 								      end if;	
 			when execute_put2 =>	if unsigned( packet_length) > 1  then 
+												
 											if switch_data_available = '1' and dma_wr_grant='1'  then
-													-- n<=n+1;
-													 --if delai=0 then 
+													 
 														 packet_length <= packet_length - 1;
 														 dest_address <= dest_address + 1;
 														 ex2_state_mach <= execute_put2;
 														 rd_ok<='1';
+														 wr_ok<='1';
 														 data_to_ram<=switch_port_out_data;
-													--else
-													--  delai:=0;
-													-- end if;
-												 else
-													if switch_data_available = '1' and dma_wr_grant='0'then
+											else
+													if switch_data_available = '1' and dma_wr_grant='0' then
 														if delai=0 then 
-														data_to_ram<=switch_port_out_data;
+														data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch
 														end if;
 														delai:=1;--indique qu'un temps supplémentaire est
@@ -189,17 +187,20 @@
 													end if;
 													ex2_state_mach <= execute_put2;
-													rd_ok<='0';
-												end if;
+													rd_ok<='0'; --bloaque la lecture du switch pour ne pas perdre les données
+											end if;
 										else 
 											if switch_data_available = '1' then 
 												--la dernière donnée à écrire en RAM
 												data_to_ram<=switch_port_out_data;
+												rd_ok<='0';
+												wr_ok<='1';
+											else
+												rd_ok<='1';
+												wr_ok<='0';
 											end if;
-											rd_ok<='0';
-											 
 											if dma_wr_grant='1' then 
 
 												 ex2_state_mach <= execute_put3;
-
+												Wr_ok<='0';
 												 
 											 end if;
@@ -214,19 +215,46 @@
 												end if;
 			
-			when execute_put4 => if n=0 then
+			when execute_put4 => if n <=4 then     
+			
+												dma_wr<='1';  --demander un accès exclusif au bus
+												dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
+											else
+												dma_wr<='0';										
+												dma_rd<='0';
+											end if;
+										if n=0 then
 											if dma_rd_grant='1' then 
 												n<=n+1;
-												tempval:=Ram_data_in;
-												tempval(4):='1';			--SET du bit DReceived
-												data_to_ram<=tempval;
-												
+											else
+											rd_ok<='1';
+											wr_ok<='0';
 											end if;
+											elsif n=1 then
+												if dma_rd_grant='1' then 
+													n<=n+1;
+												else
 												rd_ok<='1';
 												wr_ok<='0';
-											elsif n=1 then
-												rd_ok<='0';
-												wr_ok<='1';
-												n<=n+1;
+												end if;
 											elsif n=2 then
+												if dma_rd_grant='1' then 
+													n<=n+1;
+													tempval:=Ram_data_in;
+													tempval(4):='1';			--SET du bit DReceived
+													data_to_ram<=tempval;
+													rd_ok<='0';
+													wr_ok<='1';
+												else
+												rd_ok<='1';
+												wr_ok<='0';
+												n<=n-1;
+												end if;
+											elsif n=3 then
+												if dma_wr_grant='1' then
+													rd_ok<='0';
+													wr_ok<='1';
+													n<=n+1;
+												end if;
+											elsif n=4 then
 												if dma_wr_grant='1' then
 													rd_ok<='0';
@@ -250,5 +278,5 @@
 											  wr_ok<='1';
 								      end if;	
-			when execute_get2 => if fifo_full = '0'and switch_data_available ='1' and packet_length > 0 then
+			when execute_get2 => if fifo_full = '0' and switch_data_available ='1' and packet_length > 0 then
 										   data_to_write_fifo <= switch_port_out_data;
 											packet_length <= packet_length - 1;
@@ -271,28 +299,56 @@
 											
 										dest_address<=std_logic_vector(to_unsigned(core_base_adr+4,16));
-			when execute_get4 => 
+			when execute_get4 => if n <4 then     
+			
+												dma_wr<='1';  --demander un accès exclusif au bus
+												dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
+											else
+												dma_wr<='0';										
+												dma_rd<='0';
+											end if;
 											if n=0 then
-													if dma_rd_grant='1' then
+												if dma_rd_grant='1' then
+												n<=n+1;
+												
+												end if;
+												rd_ok<='1';
+												wr_ok<='0';
+											elsif n=1 then
+												if dma_rd_grant='1' then
+													n<=n+1;
+													
+													end if;
+													rd_ok<='1';
+													wr_ok<='0';
+												
+											elsif n=2 then
+													if dma_rd_grant='1' and dma_wr_grant='1' then
 														n<=n+1;
 														tempval:=Ram_data_in;
 														tempval(2):='1';  	--mise à 1 du Bit Dreceiving
-														tempval(5):='0'; 		--Mise à 0 du Bit Sent
+														--tempval(5):='0'; 		--Mise à 0 du Bit Sent
 														data_to_ram<=tempval;
-													end if;
+														rd_ok<='0';
+														wr_ok<='1';
+													else
 													rd_ok<='1';
 													wr_ok<='0';
-											elsif n=1 then
-												n<=n+1;
-											elsif n=2 then
+												end if;
+											
+											elsif n=3 then
+												if dma_wr_grant = '1' then
 												n<=n+1;
 												rd_ok<='0';
 												wr_ok<='1';
-											elsif n=3 then
+												end if;
+											elsif n=4 then
 											  if dma_wr_grant = '1' then
 													n<="0000";
 													ex2_state_mach <= fetch_packet_type; -- fin du mpi_get
-											  end if;
-											   rd_ok<='0';
-												wr_ok<='1';
+											  else
+													rd_ok<='0';
+													wr_ok<='1';
+													--n<=n-1;
+											 end if;
 											end if;
 										   
@@ -439,5 +495,5 @@
 									   switch_port_out_rd_en <=rd_ok;	
 										--ne pas corrompre le contenu de la RAM
-										Ram_data_out<=data_to_ram; 					
+										--Ram_data_out<=data_to_ram; 					
 										Ram_wr<='0';
 										Ram_rd<='1';
@@ -453,11 +509,11 @@
 										switch_port_out_rd_en <= '0';
 										 packet_received <= '1'; 
-										 dma_rd_request <= rd_ok;
-										 dma_wr_request <=wr_ok;
+										 dma_rd_request <= dma_rd;
+										 dma_wr_request <=dma_wr;
 										 Ram_wr<=wr_ok;
 										 Ram_rd<=rd_ok;
 										 AppInitReq<='0';	 
 										 barrier_completed <= '0';	
-										 Ram_data_out<=Ram_data_in or "00000010"; -- le résultat de l'exécution 
+										 Ram_data_out<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution 
 											
 		when execute_put5 =>		  
@@ -468,9 +524,9 @@
 								        AppInitReq<='0';
 								        barrier_completed <= '0';
-								        dma_rd_request <= rd_ok;
-										dma_wr_request <= wr_ok;
+								        dma_rd_request <= dma_rd;
+										dma_wr_request <= dma_wr;
 										Ram_rd<=rd_ok;
 										Ram_wr<=wr_ok;
-										Ram_data_out<=ram_data_in or "00000010";
+										Ram_data_out<=data_to_ram;
 										--Result <=(1=>'1',others=>'0'); --put completed								  
 		
@@ -516,5 +572,5 @@
 										  AppInitReq<='0';	
 										  barrier_completed <= '0';	
-										 Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending
+										 --Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending
 											
 		when execute_get4 =>		  
@@ -525,9 +581,9 @@
 								        packet_received <= '1';
 								        AppInitReq<='0';
-								        dma_rd_request <= rd_ok;
-										dma_wr_request <= wr_ok;
+								        dma_rd_request <= dma_rd;
+										dma_wr_request <= dma_wr;
 										Ram_rd<=rd_ok;
 										Ram_wr<=wr_ok;
-										Ram_data_out<=ram_data_in or "00000010"; --activer le bit DSending
+										Ram_data_out<=data_to_ram; --activer le bit DSending
 		
 		
