Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER_summary.html
===================================================================
--- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER_summary.html	(revision 29)
+++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER_summary.html	(revision 41)
@@ -3,25 +3,31 @@
 <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>MPI_CORE_COMPONENTS Project Status</B></TD></TR>
+<TD ALIGN=CENTER COLSPAN='4'><B>MultiMPITest Project Status (12/09/2012 - 19:46:00)</B></TD></TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
-<TD>MPI_CORE_COMPONENTS.ise</TD>
-<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
-<TD>New</TD>
+<TD>MPI_CORE_COMPONENTS.xise</TD>
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+<TD> No Errors </TD>
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
 <TD>MPI_CORE_SCHEDULER</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>Placed and Routed</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc6slx45-3csg324</TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
 <TD>&nbsp;</TD>
 </TR>
 <TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
-<TD>xc3s1200e-4fg320</TD>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
 <TD>&nbsp;</TD>
 </TR>
 <TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 11.1</TD>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
 <TD>
@@ -29,12 +35,15 @@
 </TR>
 <TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
-<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
 <TD>&nbsp;</TD>
 </TR>
 <TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
-<TD>Xilinx Default (unlocked)</TD>
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
+<TD>
+<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_envsettings.html'>
+System Settings</A>
+</TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
 <TD>&nbsp;&nbsp;</TD>
@@ -44,9 +53,292 @@
 
 
-
-
-
-
-
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
+<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
+<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>4,800</TD>
+<TD ALIGN=RIGHT>1%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latch-thrus</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as AND/OR logics</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
+<TD ALIGN=RIGHT>9</TD>
+<TD ALIGN=RIGHT>2,400</TD>
+<TD ALIGN=RIGHT>1%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
+<TD ALIGN=RIGHT>9</TD>
+<TD ALIGN=RIGHT>2,400</TD>
+<TD ALIGN=RIGHT>1%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
+<TD ALIGN=RIGHT>5</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1,200</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
+<TD ALIGN=RIGHT>5</TD>
+<TD ALIGN=RIGHT>600</TD>
+<TD ALIGN=RIGHT>1%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
+<TD ALIGN=RIGHT>9</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
+<TD ALIGN=RIGHT>7</TD>
+<TD ALIGN=RIGHT>9</TD>
+<TD ALIGN=RIGHT>77%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>9</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>9</TD>
+<TD ALIGN=RIGHT>22%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
+<TD ALIGN=RIGHT>14</TD>
+<TD ALIGN=RIGHT>4,800</TD>
+<TD ALIGN=RIGHT>1%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
+<TD ALIGN=RIGHT>35</TD>
+<TD ALIGN=RIGHT>102</TD>
+<TD ALIGN=RIGHT>34%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>12</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>24</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>32</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>32</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>16</TD>
+<TD ALIGN=RIGHT>6%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGMUX</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>200</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>200</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>200</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>128</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>8</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>8</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
+<TD ALIGN=RIGHT>1.39</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
+<TD>0 (Setup: 0, Hold: 0)</TD>
+<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
+<TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
+<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.unroutes'>All Signals Completely Routed</A></TD>
+<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
+<TD COLSPAN='2'><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
+<TD>
+<A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
+<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TABLE>
 
 
@@ -56,10 +348,11 @@
 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
 <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:05 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:09 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:27 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:38 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 <TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\MPI_CORE_SCHEDULER.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sat 8. Dec 00:53:43 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 <TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 </TABLE>
@@ -67,7 +360,10 @@
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
-</TABLE>
-
-
-<br><center><b>Date Generated:</b> 06/16/2011 - 20:05:57</center>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri 7. Dec 14:52:37 2012</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat 8. Dec 15:45:26 2012</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Core MPI/CORE_MPI\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat 8. Dec 15:45:32 2012</TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 12/09/2012 - 19:46:00</center>
 </BODY></HTML>
