Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DEMUX1.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DEMUX1.vhd (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DEMUX1.vhd (revision 41) @@ -28,12 +28,12 @@ --use UNISIM.VComponents.all; -entity DEMUX1 is +entity CDEMUX1 is Port ( di : in STD_LOGIC; sel : in STD_LOGIC; do1 : out STD_LOGIC; do2 : out STD_LOGIC); -end DEMUX1; +end CDEMUX1; -architecture Behavioral of DEMUX1 is +architecture Behavioral of CDEMUX1 is begin Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DMA_ARBITER.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DMA_ARBITER.vhd (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/DMA_ARBITER.vhd (revision 41) @@ -135,6 +135,14 @@ pri_wr<=pri_rd; req_wr:='1'; - prio_wr<=(pri_rd=>'1',others=>'0'); - dma_rd_logic<=(pri_rd=>'1',others=>'0'); + for i in 0 to 3 loop + if i=pri_rd then + prio_wr(i)<='1'; + dma_wr_logic(i)<='1'; + else + prio_wr(i)<='0'; + dma_wr_logic(i)<='0'; + end if; + end loop; + end if; @@ -193,6 +201,14 @@ pri_rd<=pri_wr; req_rd:='1'; - prio_rd<=(pri_wr=>'1',others=>'0'); - dma_rd_logic<=(pri_wr=>'1',others=>'0'); + for i in 0 to 3 loop + if i=pri_wr then + prio_rd(i)<='1'; + dma_rd_logic(i)<='1'; + else + prio_rd(i)<='0'; + dma_rd_logic(i)<='0'; + end if; + end loop; + end if; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_COMPONENTS.gise =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_COMPONENTS.gise (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_COMPONENTS.gise (revision 41) @@ -23,23 +23,147 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -47,206 +171,144 @@ + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_COMPONENTS.xise =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_COMPONENTS.xise (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_COMPONENTS.xise (revision 41) @@ -18,7 +18,5 @@ - - - + @@ -342,5 +340,5 @@ - + @@ -493,5 +491,5 @@ - + @@ -521,5 +519,5 @@ - + @@ -628,5 +626,5 @@ - + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER.vhd (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER.vhd (revision 41) @@ -52,5 +52,5 @@ signal sel_signal : std_logic; -- declaration des composants du scheduler -COMPONENT DEMUX1 +COMPONENT CDEMUX1 PORT( di : IN std_logic; @@ -61,5 +61,5 @@ END COMPONENT; -COMPONENT MUX1 +COMPONENT CMUXP1 PORT( di1 : IN std_logic; @@ -70,5 +70,5 @@ END COMPONENT; -COMPONENT MUX8 +COMPONENT CMUX8 PORT( di1 : IN std_logic_vector(7 downto 0); @@ -107,5 +107,5 @@ -Fifo_empty_MUX: MUX1 PORT MAP( +Fifo_empty_MUX: CMUXP1 PORT MAP( di1 => instruction_fifo_empty , di2 => get_request_fifo_empty, @@ -116,5 +116,5 @@ -rd_en_demux: DEMUX1 PORT MAP( +rd_en_demux: CDEMUX1 PORT MAP( di => fifo_rd_en , sel => sel_signal, @@ -123,5 +123,5 @@ ); -data_MUX8: MUX8 PORT MAP( +data_MUX8: CMUX8 PORT MAP( di1 => instruction_fifo_data , di2 => get_request_fifo_data, Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER_summary.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER_summary.html (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_CORE_SCHEDULER_summary.html (revision 41) @@ -3,25 +3,31 @@ - + - - - + + + + + + + + + - - + - + + - - + + - - + + @@ -44,9 +53,292 @@ - - - - - + 
MPI_CORE_COMPONENTS Project Status
MultiMPITest Project Status (12/09/2012 - 19:46:00)
Project File:MPI_CORE_COMPONENTS.iseImplementation State:NewMPI_CORE_COMPONENTS.xiseParser Errors: No Errors
Module Name: MPI_CORE_SCHEDULERImplementation State:Placed and Routed
Target Device:xc6slx45-3csg324
  • Errors:
  
Target Device:xc3s1200e-4fg320Product Version:ISE 12.3
  • Warnings:
  
Product Version:ISE 11.1Design Goal:Balanced
  • Routing Results:
 @@ -29,12 +35,15 @@
Design Goal:BalancedDesign Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
  
Design Strategy:Xilinx Default (unlocked)Environment: + +System Settings +
  • Final Timing Score:
   
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers24,8001% 
    Number used as Flip Flops2   
    Number used as Latches0   
    Number used as Latch-thrus0   
    Number used as AND/OR logics0   
Number of Slice LUTs92,4001% 
    Number used as logic92,4001% 
        Number using O6 output only4   
        Number using O5 output only0   
        Number using O5 and O65   
        Number used as ROM0   
    Number used as Memory01,2000% 
Number of occupied Slices56001% 
Number of LUT Flip Flop pairs used9   
    Number with an unused Flip Flop7977% 
    Number with an unused LUT090% 
    Number of fully used LUT-FF pairs2922% 
    Number of unique control sets2   
    Number of slice register sites lost
        to control set restrictions		144,8001% 
Number of bonded IOBs3510234% 
Number of RAMB16BWERs0120% 
Number of RAMB8BWERs0240% 
Number of BUFIO2/BUFIO2_2CLKs0320% 
Number of BUFIO2FB/BUFIO2FB_2CLKs0320% 
Number of BUFG/BUFGMUXs1166% 
    Number used as BUFGs1   
    Number used as BUFGMUX0   
Number of DCM/DCM_CLKGENs040% 
Number of ILOGIC2/ISERDES2s02000% 
Number of IODELAY2/IODRP2/IODRP2_MCBs02000% 
Number of OLOGIC2/OSERDES2s02000% 
Number of BSCANs040% 
Number of BUFHs01280% 
Number of BUFPLLs080% 
Number of BUFPLL_MCBs040% 
Number of DSP48A1s080% 
Number of ICAPs010% 
Number of PCILOGICSEs020% 
Number of PLL_ADVs020% 
Number of PMVs010% 
Number of STARTUPs010% 
Number of SUSPEND_SYNCs010% 
Average Fanout of Non-Clock Nets1.39   
+ + + + 
+ + + + + + + + + + + + + + + + + +
Performance Summary [-]
Final Timing Score:0 (Setup: 0, Hold: 0)Pinout Data:Pinout Report
Routing Results: +All Signals Completely RoutedClock Data:Clock Report
Timing Constraints: +All Constraints Met  
@@ -56,10 +348,11 @@ Report NameStatusGenerated ErrorsWarningsInfos -Synthesis Report      -Translation Report      -Map Report      -Place and Route Report      +Synthesis ReportCurrentSat 8. Dec 00:53:05 2012    +Translation ReportCurrentSat 8. Dec 00:53:09 2012    +Map ReportCurrentSat 8. Dec 00:53:27 2012    +Place and Route ReportCurrentSat 8. Dec 00:53:38 2012    +CPLD Fitter Report (Text)      Power Report      -Post-PAR Static Timing Report      +Post-PAR Static Timing ReportCurrentSat 8. Dec 00:53:43 2012    Bitgen Report      @@ -67,7 +360,10 @@ Secondary Reports [-] Report NameStatusGenerated - - - -
Date Generated: 06/16/2011 - 20:05:57
+ISIM Simulator LogOut of DateFri 7. Dec 14:52:37 2012 +WebTalk ReportOut of DateSat 8. Dec 15:45:26 2012 +WebTalk Log FileOut of DateSat 8. Dec 15:45:32 2012 + + + +
Date Generated: 12/09/2012 - 19:46:00
Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC.sym =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC.sym (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC.sym (revision 41) @@ -2,14 +2,14 @@ BLOCK - 2012-7-12T10:22:56 + 2012-12-9T10:59:12 - + + - Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC.vhd (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MPI_NOC.vhd (revision 41) @@ -33,5 +33,5 @@ entity MPI_NOC is -generic (NPROC : positive:=2); +generic (NPROC : positive:=4); port( Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX1.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX1.vhd (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX1.vhd (revision 41) @@ -28,12 +28,12 @@ --use UNISIM.VComponents.all; -entity MUX1 is +entity CMUXP1 is Port ( di1 : in STD_LOGIC; di2 : in STD_LOGIC; do : out STD_LOGIC; sel : in STD_LOGIC); -end MUX1; +end CMUXP1; -architecture Behavioral of MUX1 is +architecture Behavioral of CMUXP1 is begin Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX8.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX8.vhd (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MUX8.vhd (revision 41) @@ -28,12 +28,12 @@ --use UNISIM.VComponents.all; -entity MUX8 is +entity CMUX8 is Port ( di1 : in STD_LOGIC_VECTOR (7 downto 0); di2 : in STD_LOGIC_VECTOR (7 downto 0); sel : in STD_LOGIC; do : out STD_LOGIC_VECTOR (7 downto 0)); -end MUX8; +end CMUX8; -architecture Behavioral of MUX8 is +architecture Behavioral of CMUX8 is begin Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest.ucf =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest.ucf (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest.ucf (revision 41) @@ -0,0 +1,4 @@ + +#Created by Constraints Editor (xc6slx45-csg324-3) - 2012/12/19 +NET "clkm" TNM_NET = clkm; +TIMESPEC TS_clkm = PERIOD "clkm" 10 ns HIGH 50%; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest.vhd (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest.vhd (revision 41) @@ -33,7 +33,9 @@ ENTITY MultiMPITest IS ---port (clkm : in std_logic; ---reset : in std_logic; ---result : out std_logic_vector(Word-1 downto 0)); +--simulation translate_off +port (clkm : in std_logic; +reset : in std_logic; +result : out std_logic_vector(Word-1 downto 0)); +--simulation translate_on END MultiMPITest; @@ -68,8 +70,10 @@ constant clk_period : time := 10 ns; - constant PROC : positive :=4; + constant PROC : positive :=8; +-- synthesis translate_off --===================signaux pour l'horloge ============================== signal reset,clkm : std_logic := '0'; --======================================================================== +-- synthesis translate_on --signaux pour la gestion de la MAE type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, @@ -85,5 +89,5 @@ BEGIN - uut: MPI_NOC GENERIC MAP (NPROC=>PROC) + Xbar: MPI_NOC GENERIC MAP (NPROC=>PROC) PORT MAP ( MPI_Node_in => MPI_Node_in, @@ -126,13 +130,53 @@ Core_Hold_Ack => MPI_Node_in(2).hold_ack ); +PE3: PE generic map (DestId=>2) +Port Map ( +Instruction => MPi_Node_in(3).Instruction, + Instruction_en => MPi_Node_in(3).Instruction_en, + Core_PushOut => MPi_Node_out(3).PushOut, + clk =>clkm, + reset =>reset, + Core_RAM_Data_Out =>MPi_Node_in(3).Ram_Data_out, + Core_RAM_Data_IN => MPI_Node_out(3).ram_data_in, + Core_RAM_WE => MPI_Node_out(3).ram_we, + Core_RAM_EN => MPI_Node_out(3).ram_en, + -- Core_RAM_ENB => MPI_Node_out(1).ram_en, + Core_RAM_Address_Wr => MPI_Node_out(3).ram_address_wr, + Core_RAM_Address_Rd => MPI_Node_out(3).ram_address_rd, + Core_Hold_req => MPI_Node_out(3).hold_req, + Core_Hold_Ack => MPI_Node_in(3).hold_ack +); + +--PE4: PE Generic map (DestId=>3) +-- Port Map ( +-- Instruction => MPi_Node_in(4).Instruction, +-- Instruction_en => MPi_Node_in(4).Instruction_en, +-- Core_PushOut => MPi_Node_out(4).PushOut, +-- clk =>clkm, +-- reset =>reset, +-- Core_RAM_Data_Out =>MPi_Node_in(4).Ram_Data_out, +-- Core_RAM_Data_IN => MPI_Node_out(4).ram_data_in, +-- Core_RAM_WE => MPI_Node_out(4).ram_we, +-- Core_RAM_EN => MPI_Node_out(4).ram_en, +-- --Core_RAM_ENB => MPI_Node_out(2).ram_en, +-- Core_RAM_Address_Wr => MPI_Node_out(4).ram_address_wr, +-- Core_RAM_Address_Rd => MPI_Node_out(4).ram_address_rd, +-- Core_Hold_req => MPI_Node_out(4).hold_req, +-- Core_Hold_Ack => MPI_Node_in(4).hold_ack +--); MPI_Node_in(1).reset<=reset; MPI_Node_in(1).clk<=clkm; MPI_Node_in(2).reset<=reset; MPI_Node_in(2).clk<=clkm; ---Result<=MPi_Node_out(1).PushOut; +MPI_Node_in(3).reset<=reset; +MPI_Node_in(3).clk<=clkm; +MPI_Node_in(4).reset<=reset; +MPI_Node_in(4).clk<=clkm; +Result<=MPi_Node_out(1).PushOut; --============================================================= -- Clock process definitions --============================================================= - clk_process :process +-- synthesis translate_off + clk_process :process begin clkm <= '0' ; @@ -153,4 +197,5 @@ end process; +-- synthesis translate_on --================================================================ END; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest_summary.html =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest_summary.html (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/MultiMPITest_summary.html (revision 41) @@ -3,5 +3,5 @@ - + @@ -14,18 +14,17 @@ - + - + +No Errors - + @@ -34,5 +33,5 @@ +All Signals Completely Routed @@ -40,5 +39,7 @@ - + @@ -49,5 +50,5 @@ - +
MultiMPITest Project Status (12/05/2012 - 14:37:41)
SWITCH_GEN Project Status (12/17/2012 - 14:30:15)
Project File:MultiMPITest Implementation State:Synthesized (Failed)Placed and Routed
Target Device:xc6slx100-3fgg484xc6slx45-3csg324
  • Errors:
 -X -3 Errors (3 new)
Product Version:ISE 12.3
  • Warnings:
71 Warnings (71 new)3183 Warnings (2171 new)
  • Routing Results:
 - 
Xilinx Default (unlocked)
  • Timing Constraints:
  +X +10 Failing Constraints
  • Final Timing Score:
  2511  (Timing Report)
@@ -56,67 +57,376 @@  
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current Warnings [-]
Synthesis Warnings (Only the first 50 listed)New
WARNING:HDLCompiler:871: - "\Core MPI\CORE_MPI\../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" Line 114: Using initial value ('0','0','1','1','0','0','0','0') for port_id since it is never assignedNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" Line 587: port_id should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" Line 596: port_id should be on the sensitivity list of the processNew
WARNING:HDLCompiler:871: - "\Core MPI\CORE_MPI\CORE_MPI.vhd" Line 333: Using initial value "00011010" for uclkrate since it is never assignedNew
WARNING:HDLCompiler:1127: - "\Core MPI\CORE_MPI\FIFO_64_FWFT.vhd" Line 103: Assignment to clk_signal ignored, since the identifier is never usedNew
WARNING:HDLCompiler:1127: - "\Core MPI\CORE_MPI\FIFO_64_FWFT.vhd" Line 168: Assignment to doa_signal ignored, since the identifier is never usedNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\load_instr.vhd" Line 187: base_adr should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\load_instr.vhd" Line 215: ram_address_i should be on the sensitivity list of the processNew
WARNING:HDLCompiler:871: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 59: Using initial value '1' for en since it is never assignedNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 149: clkrate should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 153: tick_count should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 154: clkr_count should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 155: clkr_count should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 156: tick_count should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 158: time_ucount should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 159: clkrate should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 160: tick_count should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 161: tick_count should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 163: time_ucount should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 165: tick_count should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 166: clkr_count should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 167: time_ucount should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\Ex0_Fsm.vhd" Line 168: tick_count should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX1_FSM.vhd" Line 665: rd_ok should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX1_FSM.vhd" Line 667: rd_ok should be on the sensitivity list of the processNew
WARNING:HDLCompiler:1127: - "\Core MPI\CORE_MPI\EX2_FSM.vhd" Line 100: Assignment to pading_data ignored, since the identifier is never usedNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX2_FSM.vhd" Line 468: data_to_ram should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX2_FSM.vhd" Line 481: data_to_ram should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX2_FSM.vhd" Line 496: wr_ok should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX2_FSM.vhd" Line 497: wr_ok should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX2_FSM.vhd" Line 501: data_to_ram should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX2_FSM.vhd" Line 511: wr_ok should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX2_FSM.vhd" Line 513: wr_ok should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX2_FSM.vhd" Line 514: data_to_ram should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX2_FSM.vhd" Line 537: wr_ok should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX2_FSM.vhd" Line 568: wr_ok should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX2_FSM.vhd" Line 570: wr_ok should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX2_FSM.vhd" Line 571: data_to_ram should be on the sensitivity list of the processNew
WARNING:HDLCompiler:871: - "\Core MPI\CORE_MPI\EX3_FSM.vhd" Line 51: Using initial value "00000011" for size since it is never assignedNew
WARNING:HDLCompiler:1127: - "\Core MPI\CORE_MPI\EX4_FSM.vhd" Line 126: Assignment to ranksent ignored, since the identifier is never usedNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX4_FSM.vhd" Line 224: bcast_rdy should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX4_FSM.vhd" Line 243: bcast_rdy should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX4_FSM.vhd" Line 316: portnum_i should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX4_FSM.vhd" Line 318: nextrank should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX4_FSM.vhd" Line 340: send_rdy should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX4_FSM.vhd" Line 368: datatosend should be on the sensitivity list of the processNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX4_FSM.vhd" Line 384: exectime_out should be on the sensitivity list of the processNew
WARNING:HDLCompiler:1127: - "\Core MPI\CORE_MPI\EX4_FSM.vhd" Line 143: Assignment to cm_ack ignored, since the identifier is never usedNew
WARNING:HDLCompiler:871: - "\Core MPI\CORE_MPI\EX4_FSM.vhd" Line 433: Using initial value "0000" for nulvect since it is never assignedNew
WARNING:HDLCompiler:92: - "\Core MPI\CORE_MPI\EX4_FSM.vhd" Line 484: exectime_out should be on the sensitivity list of the processNew
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers2,78754,5765% 
    Number used as Flip Flops2,177   
    Number used as Latches610   
    Number used as Latch-thrus0   
    Number used as AND/OR logics0   
Number of Slice LUTs12,10727,28844% 
    Number used as logic6,96227,28825% 
        Number using O6 output only5,563   
        Number using O5 output only409   
        Number using O5 and O6990   
        Number used as ROM0   
    Number used as Memory5,0886,40879% 
        Number used as Dual Port RAM5,080   
            Number using O6 output only5,080   
            Number using O5 output only0   
            Number using O5 and O60   
        Number used as Single Port RAM8   
            Number using O6 output only8   
            Number using O5 output only0   
            Number using O5 and O60   
        Number used as Shift Register0   
    Number used exclusively as route-thrus57   
        Number with same-slice register load9   
        Number with same-slice carry load48   
        Number with other load0   
Number of occupied Slices3,9486,82257% 
Number of LUT Flip Flop pairs used12,444   
    Number with an unused Flip Flop9,82012,44478% 
    Number with an unused LUT33712,4442% 
    Number of fully used LUT-FF pairs2,28712,44418% 
    Number of unique control sets858   
    Number of slice register sites lost
        to control set restrictions		3,34154,5766% 
Number of bonded IOBs102184% 
Number of RAMB16BWERs01160% 
Number of RAMB8BWERs02320% 
Number of BUFIO2/BUFIO2_2CLKs0320% 
Number of BUFIO2FB/BUFIO2FB_2CLKs0320% 
Number of BUFG/BUFGMUXs41625% 
    Number used as BUFGs4   
    Number used as BUFGMUX0   
Number of DCM/DCM_CLKGENs080% 
Number of ILOGIC2/ISERDES2s03760% 
Number of IODELAY2/IODRP2/IODRP2_MCBs03760% 
Number of OLOGIC2/OSERDES2s03760% 
Number of BSCANs040% 
Number of BUFHs02560% 
Number of BUFPLLs080% 
Number of BUFPLL_MCBs040% 
Number of DSP48A1s0580% 
Number of ICAPs010% 
Number of MCBs020% 
Number of PCILOGICSEs020% 
Number of PLL_ADVs040% 
Number of PMVs010% 
Number of STARTUPs010% 
Number of SUSPEND_SYNCs010% 
Average Fanout of Non-Clock Nets5.70   
- - - - - - - + 
+ + + + + + + + + + + + + + + + + +
Performance Summary [-]
Final Timing Score:2511 (Setup: 2511, Hold: 0)Pinout Data:Pinout Report
Routing Results: +All Signals Completely RoutedClock Data:Clock Report
Timing Constraints: +X +10 Failing Constraints  
@@ -126,21 +436,21 @@ Report NameStatusGenerated ErrorsWarningsInfos -Synthesis ReportCurrentWed 5. Dec 14:37:20 2012X 3 Errors (3 new)71 Warnings (71 new)0 -Translation Report      -Map Report      -Place and Route Report      +Synthesis ReportCurrentMon 17. Dec 14:18:41 201201257 Warnings (277 new)428 Infos (8 new) +Translation ReportCurrentMon 17. Dec 14:18:50 20120102 Warnings (70 new)0 +Map ReportCurrentMon 17. Dec 14:26:12 20120974 Warnings (974 new)8 Infos (2 new) +Place and Route ReportCurrentMon 17. Dec 14:29:38 20120850 Warnings (850 new)4 Infos (0 new) Power Report      -Post-PAR Static Timing Report      -Bitgen Report      +Post-PAR Static Timing ReportCurrentMon 17. Dec 14:30:13 2012003 Infos (0 new) +Bitgen ReportOut of DateSat 8. Dec 15:41:28 20120693 Warnings (693 new)0  
- - - + + +
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateWed 5. Dec 14:35:53 2012
WebTalk ReportOut of DateFri 17. Aug 16:33:25 2012
WebTalk Log FileOut of DateFri 17. Aug 16:33:28 2012
ISIM Simulator LogOut of DateFri 7. Dec 14:52:37 2012
WebTalk ReportOut of DateSat 8. Dec 15:45:26 2012
WebTalk Log FileOut of DateSat 8. Dec 15:45:32 2012
-
Date Generated: 12/05/2012 - 14:39:46
+
Date Generated: 12/17/2012 - 14:30:15
Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE.vhd (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/PE.vhd (revision 41) @@ -27,10 +27,12 @@ use work.Packet_type.all; use work.MPI_RMA.all; +-- synthesis translate_off use std.textio.all; +-- synthesis translate_on use IEEE.NUMERIC_STD.ALL; entity PE is - Generic (DestId : natural ); + Generic (DestId : natural:=0 ); Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); Instruction_en : out STD_LOGIC; @@ -189,4 +191,5 @@ --======================================================= --variables pour la création du fichier de résultats + -- synthesis translate_off type char_file is file of character; file f: text; @@ -196,7 +199,16 @@ variable L: line; variable fopened: std_logic:='0'; + -- synthesis translate_on --====================================================== begin --=== Partie combinatoire du process =================================== + + --=== Fin de la partie combinatoire du process ========================== + + + + --end loop; + + if (clk'event and clk='1') then Libr.Instr_ack<=Core_pushout(0); Libr.InitOk<=Core_pushout(4); @@ -205,11 +217,5 @@ Libr.RamSel<=RamSel; sram.data_out<=PE_ram_do; - --=== Fin de la partie combinatoire du process ========================== - - - - --end loop; - - if (clk'event and clk='1') then + if reset='1' then RunState<=start; @@ -237,4 +243,5 @@ timeout:=0; dcount<=0; + -- synthesis translate_off if fopened='0' then file_open(status,f, integer'image(destid) & "test_file0.txt", APPEND_MODE); @@ -247,5 +254,5 @@ fopened:='1'; end if; - + -- synthesis translate_on when Fillmem => if Ramsel='0' then @@ -284,10 +291,12 @@ when InitApp => --code pour Init - dlen:=1; + dlen:=251; if ct=0 then - write (l,string'("Dlen; ;INIT of Process n°; " & image(MyRank) & "; started at ; " & time'image(now))); + -- synthesis translate_off + write (l,string'("Dlen; ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & time'image(now))); report l.all; writeline (f, l) ; + -- synthesis translate_on end if; pMPI_Init(ct,Libr,Clk,SRam); @@ -300,7 +309,9 @@ if ct=0 then RunState<=GetRank; - write (l,string'("Dlen; ;INIT;" & "; ended at ; " & time'image(now))); + -- synthesis translate_off + write (l,string'("Dlen; ;INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now))); report l.all; writeline (f, l) ; + -- synthesis translate_on end if; @@ -309,8 +320,9 @@ when GetRank => if ct=0 then - - write (l,string'("Dlen; ; Rank ; " & "; started ; " & time'image(now))); + -- synthesis translate_off + write (l,string'("Dlen; ;Rank1 " & integer'image(Dlen) & "; ; started ; " & time'image(now))); report l.all; writeline (f, l) ; + -- synthesis translate_on end if; pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); @@ -318,7 +330,9 @@ if ct=0 then RunState<=PutData; - write (l,string'("Dlen; ; Rank ; " & "; ended at ; " & time'image(now))); + -- synthesis translate_off + write (l,string'("Dlen; ;Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now))); report l.all; - writeline (f, l) ; + writeline (f, l) ; + -- synthesis translate_on end if; @@ -331,10 +345,19 @@ --dlen:=251; --- if ct=0 then - write (l,string'("Dlen;" & integer'image(dlen) & ";Put of Pr n°; " & image(MyRank) & "; started at ; " & time'image(now))); + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now))); report l.all; writeline (f, l) ; + -- synthesis translate_on end if; if unsigned(MyRank) = 0 then + Destrank:=2; + + elsif unsigned(MyRank) = 1 then + Destrank:=0; + elsif unsigned(MyRank) = 2 then Destrank:=1; + elsif unsigned(MyRank) = 3 then + Destrank:=2; else DestRank:=0; @@ -343,6 +366,6 @@ SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); DestAdr:=X"2000"; - pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + adresse:=to_integer(unsigned(sram.addr_wr)); adresse_rd:=to_integer(unsigned(sram.addr_rd)); @@ -353,8 +376,10 @@ if ct=0 then RunState<=GetData; + -- synthesis translate_off report "Put of Process n°; " & image(MyRank) & "; ended at ; " & time'image(now); - write (l,string'("Dlen;" & integer'image(dlen) & ";Put of Pr n°; " & image(MyRank) & "; ended at time ; " & time'image(now))); + write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & time'image(now))); report l.all; - writeline (f, l) ; + writeline (f, l) ; + -- synthesis translate_on end if; @@ -363,13 +388,18 @@ --dlen:=251; --- if ct=0 then - write (l,string'("Dlen;" & integer'image(dlen) & ";GET of Process n°; " & image(MyRank) & "; started at ; " & time'image(now))); + -- synthesis translate_off + write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & time'image(now))); report l.all; writeline (f, l) ; + -- synthesis translate_on end if; SrcAdr:=X"0120"; DestAdr:=X"4000"; - - pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + if unsigned(MyRank) /= 2 then + pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); + else + RunState<=wincompleted; + end if; adresse:=to_integer(unsigned(sram.addr_wr)); adresse_rd:=to_integer(unsigned(sram.addr_rd)); @@ -380,17 +410,21 @@ if ct=0 then RunState<=wincompleted; + -- synthesis translate_off assert ct/=0 report "GET_END " & integer'image(destrank) severity Warning ; - write (l,string'("Dlen ;" & integer'image(dlen) & ";GET of Proc n°; " & image(MyRank) & "; ended at ; " & time'image(now))); + write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now))); report l.all; - writeline (f, l) ; + writeline (f, l) ; + -- synthesis translate_on end if; when WinCompleted => if ct=0 then - write (l,string'("Dlen ;" & integer'image(dlen) & ";Wait of Proc n°; " & image(MyRank) & "; started at ; " & time'image(now))); + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now))); report l.all; writeline (f, l) ; + -- synthesis translate_on end if; pMPI_Win_wait(ct,Libr,sram,MyWin ); @@ -399,7 +433,9 @@ if ct=0 then RunState<=finalize; - write (l,string'("Dlen ;" & integer'image(dlen) & ";Wait of Proc n°; " & image(MyRank) & "; ended at ; " & time'image(now))); + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now))); report l.all; writeline (f, l) ; + -- synthesis translate_on end if; @@ -408,15 +444,19 @@ when finalize => if ct=0 then - write (l,string'("Dlen ;" & integer'image(dlen) & ";Finalize of Proc n°; " & image(MyRank) & "; started at ; " & time'image(now))); + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now))); report l.all; writeline (f, l) ; + -- synthesis translate_on end if; if ct=0 then RunState<=start; - write (l,string'("Dlen ;" & integer'image(dlen) & ";Finalize of Proc n°; " & image(MyRank) & "; ended at ; " & time'image(now))); + -- synthesis translate_off + write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now))); report l.all; writeline (f, l) ; file_close(f); + -- synthesis translate_on end if; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/RAM_32_32.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/RAM_32_32.vhd (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/RAM_32_32.vhd (revision 41) @@ -45,5 +45,5 @@ signal sel : std_logic_vector(1 downto 0); signal doa,dout : std_logic_vector(width-1 downto 0); - type ram_type is array (2**size-1 downto 0) of std_logic_vector (width-1 downto 0); + type ram_type is array (2**(size-3)-1 downto 0) of std_logic_vector (width-1 downto 0); signal RAM: ram_type; begin Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/iseconfig/MPI_CORE_COMPONENTS.projectmgr =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/iseconfig/MPI_CORE_COMPONENTS.projectmgr (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/iseconfig/MPI_CORE_COMPONENTS.projectmgr (revision 41) @@ -11,8 +11,8 @@ /CORE_MPI - Behavioral C:|Documents and Settings|Administrateur.SWEET-918992B6D|Bureau|MPSOC_MEMOIRE_FIN|MPI_CORE_COMPONENTS|CORE_MPI.vhd/Instruction_Fifo1 - FIFO_64_FWFT - Behavioral /CORE_MPI - Behavioral C:|Documents and Settings|Administrateur.SWEET-918992B6D|Bureau|MPSOC_MEMOIRE_FIN|MPI_CORE_COMPONENTS|CORE_MPI.vhd/Instruction_Fifo2 - FIFO_64_FWFT - Behavioral + /FIFO - TOP_HIER C:|Core MPI|CORE_MPI|FIfo_mem.vhd /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/Inst_RAM_v - RAM_v - Behavioral/MPI_PKG/mpi_pkg /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/MPI_PKG - /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural - /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/CORE_SCHEDULER - MPI_CORE_SCHEDULER - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo1 - FIFO_64_FWFT - Behavioral /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo2 - FIFO_64_FWFT - Behavioral @@ -71,4 +71,57 @@ /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen - SWITCH_GEN - Behavioral/Switch_Crossbar9_9 - Crossbar - Behavioral /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT14_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT15_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT1_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT2_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT2_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT3_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT3_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT4_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT5_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT6_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT7_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT8_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT9_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx16_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx16_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler10_10 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler11_11 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler12_12 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler13_13 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler14_14 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler15_15 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler2_2 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler3_3 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler4_4 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler5_5 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler6_6 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler7_7 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler9_9 - Scheduler - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar10_10 - Crossbar - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar11_11 - Crossbar - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar12_12 - Crossbar - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar13_13 - Crossbar - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar14_14 - Crossbar - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar15_15 - Crossbar - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar16_16 - Crossbar - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar2_2 - Crossbar - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar3_3 - Crossbar - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar4_4 - Crossbar - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar5_5 - Crossbar - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar6_6 - Crossbar - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar7_7 - Crossbar - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar8_8 - Crossbar - Behavioral + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar9_9 - Crossbar - Behavioral /MPI_NOC - structural C:|Core MPI|CORE_MPI|MPI_NOC.vhd/MPI_PKG /MPI_NOC - structural C:|Core MPI|CORE_MPI|MPI_NOC.vhd/hardmpi - CORE_MPI - Structural/Instruction_Fifo1 - FIFO_64_FWFT - Behavioral @@ -128,12 +181,18 @@ /MPI_NOC - structural C:|Core MPI|CORE_MPI|MPI_NOC.vhd/switch_gen - SWITCH_GEN - Behavioral/Switch_Crossbar8_8 - Crossbar - Behavioral /MPI_NOC - structural C:|Core MPI|CORE_MPI|MPI_NOC.vhd/switch_gen - SWITCH_GEN - Behavioral/Switch_Crossbar9_9 - Crossbar - Behavioral - /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Image_Pkg + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/MPI_PKG + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/PE1 - PE - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/CORE_SCHEDULER - MPI_CORE_SCHEDULER - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral + /Unassigned User Library Modules MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd) - 0 - 0 - 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002ca000000020000000000000000000000000000000064ffffffff000000810000000000000002000002ca0000000100000000000000000000000100000000 + 9 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002f3000000020000000000000000000000000000000064ffffffff000000810000000000000002000002f30000000100000000000000000000000100000000 false MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd) @@ -143,58 +202,57 @@ 1 Configure Target Device - Design Utilities + Implement Design Implement Design/Place & Route/Back-annotate Pin Locations Implement Design/Place & Route/Generate IBIS Model Implement Design/Place & Route/Generate Post-Place & Route Static Timing Implement Design/Translate - User Constraints - - - + + + Synthesize - XST + + 8 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f70000000100000000 + false + Synthesize - XST + + + + 1 + + + C:\Core MPI\SWITCH_GENERIC_16_16\INPUT_PORT_MODULE.vhd + + 23 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000307000000040101000100000000000000000000000064ffffffff000000810000000000000004000001f90000000100000000000000440000000100000000000000660000000100000000000000640000000100000000 + false + C:\Core MPI\SWITCH_GENERIC_16_16\INPUT_PORT_MODULE.vhd + + + + 1 + work + + + C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER4_4.VHD + + 7 + 0 + 000000ff000000000000000100000000000000000100000000000000000000000000000000000000f7000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f70000000100000000 + false + C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER4_4.VHD + + + + 1 + Design Utilities + + + 0 0 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000 - false - - - - - 1 - - - C:\Core MPI\SWITCH_GENERIC_16_16\CoreTypes.vhd - - 15 - 0 - 000000ff00000000000000010000000000000000010000000000000000000000000000000000000307000000040101000100000000000000000000000064ffffffff000000810000000000000004000001f90000000100000000000000440000000100000000000000660000000100000000000000640000000100000000 - false - C:\Core MPI\SWITCH_GENERIC_16_16\CoreTypes.vhd - - - - 1 - work - - - C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER4_4.VHD - - 7 - 0 - 000000ff00000000000000010000000000000000010000000000000000000000000000000000000103000000010001000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000 - false - C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER4_4.VHD - - - - 1 - Design Utilities - - - - - 0 - 0 - 000000ff000000000000000100000001000000000000000000000000000000000000000000000001b0000000010000000100000000000000000000000064ffffffff000000810000000000000001000001b00000000100000000 false @@ -243,11 +301,11 @@ - xc6slx100-3fgg484 - - 0 + MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd) + + 6 0 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002c1000000020000000000000000000000000000000064ffffffff000000810000000000000002000002c10000000100000000000000000000000100000000 false - xc6slx100-3fgg484 + MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd) @@ -257,11 +315,11 @@ - - - 0 - 0 - 000000ff0000000000000001000000010000000000000000000000000000000000000000000000010d000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010d0000000100000000 - false - + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000132000000010000000100000000000000000000000064ffffffff000000810000000000000001000001320000000100000000 + false + @@ -270,14 +328,14 @@ - - - 0 - 0 - 000000ff0000000000000001000000010000000000000000000000000000000000000000000000010d000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010d0000000100000000 - false - - - 000000ff0000000000000002000000db000000a801000000050100000002 - Behavioral Simulation + ISim Simulator + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000132000000010000000100000000000000000000000064ffffffff000000810000000000000001000001320000000100000000 + false + ISim Simulator + + 000000ff0000000000000002000000d1000000d101000000050100000002 + Implementation Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/iseconfig/MultiMPITest.xreport =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/iseconfig/MultiMPITest.xreport (revision 40) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.01/iseconfig/MultiMPITest.xreport (revision 41) @@ -2,15 +2,15 @@
- 2012-12-05T03:48:30 - MultiMPITest - 2012-11-05T16:48:15 + 2012-12-20T15:14:17 + SWITCH_GEN + 2012-12-19T17:00:46 C:/Core MPI/CORE_MPI/iseconfig/MultiMPITest.xreport C:/Core MPI/CORE_MPI\ - 2012-11-05T16:59:29 + 2012-12-09T12:18:32 false
- + @@ -18,15 +18,19 @@ - - @@ -41,5 +45,5 @@ @@ -57,5 +61,5 @@ -