SWITCH_GEN Project Status (12/17/2012 - 14:30:15)
Project File: | MPI_CORE_COMPONENTS.xise | Parser Errors: | No Errors
Module Name: | MultiMPITest | Implementation State: | Placed and Routed
Target Device: | xc6slx45-3csg324 | Errors: | No Errors
Product Version: | ISE 12.3 | Warnings: | 3183 Warnings (2171 new)
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: | X 10 Failing Constraints
Environment: | System Settings | Final Timing Score: | 2511 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 2,787 | 54,576 | 5% |
Number used as Flip Flops | 2,177 |  |  |
Number used as Latches | 610 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 0 |  |  |
Number of Slice LUTs | 12,107 | 27,288 | 44% |
Number used as logic | 6,962 | 27,288 | 25% |
Number using O6 output only | 5,563 |  |  |
Number using O5 output only | 409 |  |  |
Number using O5 and O6 | 990 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 5,088 | 6,408 | 79% |
Number used as Dual Port RAM | 5,080 |  |  |
Number using O6 output only | 5,080 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 0 |  |  |
Number used as Single Port RAM | 8 |  |  |
Number using O6 output only | 8 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 0 |  |  |
Number used as Shift Register | 0 |  |  |
Number used exclusively as route-thrus | 57 |  |  |
Number with same-slice register load | 9 |  |  |
Number with same-slice carry load | 48 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 3,948 | 6,822 | 57% |
Number of LUT Flip Flop pairs used | 12,444 |  |  |
Number with an unused Flip Flop | 9,820 | 12,444 | 78% |
Number with an unused LUT | 337 | 12,444 | 2% |
Number of fully used LUT-FF pairs | 2,287 | 12,444 | 18% |
Number of unique control sets | 858 |  |  |
Number of slice register sites lost to control set restrictions | 3,341 | 54,576 | 6% |
Number of bonded IOBs | 10 | 218 | 4% |
Number of RAMB16BWERs | 0 | 116 | 0% |
Number of RAMB8BWERs | 0 | 232 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 4 | 16 | 25% |
Number used as BUFGs | 4 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 8 | 0% |
Number of ILOGIC2/ISERDES2s | 0 | 376 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 376 | 0% |
Number of OLOGIC2/OSERDES2s | 0 | 376 | 0% |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 256 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 0 | 58 | 0% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 0 | 4 | 0% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 5.70 |  |  |

Performance Summary | [-]
Final Timing Score: | 2511 (Setup: 2511, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | X 10 Failing Constraints |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Mon 17. Dec 14:18:41 2012 | 0 | 1257 Warnings (277 new) | 428 Infos (8 new)
Translation Report | Current | Mon 17. Dec 14:18:50 2012 | 0 | 102 Warnings (70 new) | 0
Map Report | Current | Mon 17. Dec 14:26:12 2012 | 0 | 974 Warnings (974 new) | 8 Infos (2 new)
Place and Route Report | Current | Mon 17. Dec 14:29:38 2012 | 0 | 850 Warnings (850 new) | 4 Infos (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | Mon 17. Dec 14:30:13 2012 | 0 | 0 | 3 Infos (0 new)
Bitgen Report | Out of Date | Sat 8. Dec 15:41:28 2012 | 0 | 693 Warnings (693 new) | 0

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | Fri 7. Dec 14:52:37 2012
WebTalk Report | Out of Date | Sat 8. Dec 15:45:26 2012
WebTalk Log File | Out of Date | Sat 8. Dec 15:45:32 2012

Date Generated: 12/17/2012 - 14:30:15