Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/DMA_ARBITER.vhd =================================================================== --- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/DMA_ARBITER.vhd (revision 45) +++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/DMA_ARBITER.vhd (revision 64) @@ -17,4 +17,7 @@ -- Revision: 09/07/2012 -- Revision 1.01 - File Created +-- Revision 1.2 - 19/03/2013 +-- Correction de bugs et optimisation du nombre de cycles +-- Création d'un testbench -- Additional Comments: Ce module pourra être optimisé pour générer les adresses automatiquement -- par le controleur DMA lorsqu'il est sollicité par la périphérie @@ -62,5 +65,7 @@ signal dma_rd_logic : std_logic_vector(3 downto 0):=(others=>'0'); signal dma_wr_logic : std_logic_vector(3 downto 0):=(others=>'0'); +signal dma_rd_latch,dma_wr_latch: std_logic_vector(3 downto 0):=(others=>'0'); signal dma_req_wr, dma_req_rd : std_logic; +signal last_grant_rd,last_grant_wr : STD_LOGIC_vector(3 downto 0):=(others=>'0'); signal tmp :std_logic_vector(3 downto 0):="0000"; @@ -68,8 +73,16 @@ --========================================================================== ---le MUX qui contrôle les adresses est géré à l'extérieur du contrôleur DMA +dma_sync: process (clk) +begin data_rd_out<=data_rd_mem ; data_wr_mem <= data_wr_in; address_out_rd <= address_rd; address_out_wr <= address_wr; + +end process; +--dma_rd_grant<= dma_rd_logic; +--dma_wr_grant<= dma_wr_logic; +dma_rd_grant<= dma_rd_latch; +dma_wr_grant<= dma_wr_latch; --========================================================================== @@ -85,9 +98,9 @@ -- dma_req_rd<=dma_req_rd or dma_rd_request(i); -- construire le signal request vers l'extérieur --loop; -hold_req<=dma_req_rd or dma_req_wr; --envoyer un Hold vers l'application +hold_req<='1' when dma_req_rd='1' or dma_req_wr='1' else '0'; --envoyer un Hold vers l'application -- machine à etat du DMAC -dmac_process : process(clk) +dmac_process : process(clk,reset) --variable tmp : natural range 0 to 15; variable tmp_rd,tmp_wr: std_logic_vector(3 downto 0); @@ -106,5 +119,5 @@ req_wr:='0'; else - if req_wr='0' or dma_wr_request="0000" then --tant que le Ctrl DMA est libre alors faire bouger la priorité en écriture + if req_wr='0' then --tant que le Ctrl DMA est libre alors faire bouger la priorité en écriture case dma_wr_request is when "0001" => pri_wr<=0; @@ -130,5 +143,5 @@ when others => - if req_rd='1' then + if req_rd='1' then --demande simultané de lecture et d'écriture if dma_rd_request(pri_rd)='1' then @@ -148,5 +161,5 @@ end if; - else + else --on affecte l'accè à la mémoire suivant le round robbin tmp_wr:= (dma_wr_request and prio_wr) ; dma_wr_logic <=tmp_wr; @@ -166,8 +179,27 @@ end if; end case; - + else --req_wr='1' + + --demande simultané de lecture et d'écriture + + if dma_rd_request(pri_wr)='1' then + pri_rd<=pri_wr; + req_rd:='1'; + prio_rd<=prio_wr; +-- for i in 0 to 3 loop +-- if i=pri_rd then +-- prio_wr(i)<='1'; +-- dma_wr_logic(i)<='1'; +-- else +-- prio_wr(i)<='0'; +-- dma_wr_logic(i)<='0'; +-- end if; +-- end loop; + + end if; + end if; - if req_rd='0' or dma_rd_request="0000" then --tant que le Ctrl DMA est libre alors faire bouger la priorité + if req_rd='0' then --tant que le Ctrl DMA est libre alors faire bouger la priorité case dma_rd_request is when "0001" => pri_rd<=0; @@ -243,31 +275,20 @@ req_rd:='0'; dma_req_rd<= '0'; - dma_rd_logic <="0000"; + req_wr:='0'; dma_req_wr<= '0'; - dma_wr_logic <="0000"; + + dma_wr_logic <="0000"; --aucun accès mémoire n'est accrédité + dma_rd_logic <="0000"; end if; + when wait_ack => -- l'application doit autoriser l'utilisation de la RAM par le Core if dma_wr_request(pri_wr) ='1' or dma_rd_request(pri_rd) ='1' then if hold_ack='1' then - dmac_state<=arbiter_ack; - end if; - else - - if dma_wr_request(pri_wr) ='0' then - req_wr:='0';-- forcer une nouvelle recherche de priorité - end if; - - if dma_rd_request(pri_rd) ='0' then - req_rd:='0'; - end if; - dmac_state<=Idle; - end if; - - - when arbiter_ack => if dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='1' then -- + --dmac_state<=arbiter_ack; + if dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='1' then -- dmac_state <= Readwrite; elsif dma_wr_request(pri_wr) ='0' and dma_rd_request(pri_rd) ='1' then @@ -278,5 +299,29 @@ dmac_state<=Idle; end if; - + end if; + else + + if dma_wr_request(pri_wr) ='0' then + req_wr:='0';-- forcer une nouvelle recherche de priorité + end if; + + if dma_rd_request(pri_rd) ='0' then + req_rd:='0'; + end if; + dmac_state<=Idle; + end if; + + + when arbiter_ack => +-- if dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='1' then -- +-- dmac_state <= Readwrite; +-- elsif dma_wr_request(pri_wr) ='0' and dma_rd_request(pri_rd) ='1' then +-- dmac_state <= Reading; +-- elsif dma_wr_request(pri_wr) ='1' and dma_rd_request(pri_rd) ='0' then +-- dmac_state <= Writing; +-- else + dmac_state<=Idle; +-- end if; + -- cet état a été combiné au précédent pour gagner un cycle when Writing => if dma_wr_request(pri_wr) ='1' then if hold_ack='1' then @@ -292,6 +337,8 @@ elsif dma_rd_request(pri_rd) ='1' then dmac_state <= Reading; + req_wr:='0'; else dmac_state <= idle; + req_wr:='0'; end if; @@ -331,6 +378,8 @@ elsif dma_wr_request(pri_wr) ='1' then dmac_state<=writing; + req_rd:='0'; else dmac_state <= idle; + req_rd:='0'; end if; when others => dmac_state <= idle; @@ -349,6 +398,6 @@ ram_en <='0'; ram_we <='0'; - dma_wr_grant <=(others=>'0'); - dma_rd_grant <=(others=>'0'); + dma_wr_latch <=(others=>'0'); + dma_rd_latch <=(others=>'0'); --address_out_rd <= address_rd; --hold_req<='0'; @@ -356,14 +405,14 @@ ram_en <='0'; ram_we <='0'; - dma_wr_grant<=(others=>'0'); - dma_rd_grant<=(others=>'0'); + dma_wr_latch<=(others=>'0'); + dma_rd_latch<=(others=>'0'); --address_out_rd <= (others=>'Z'); --address_out_wr <= (others=>'Z'); --hold_req<='1'; when arbiter_ack => --à optimiser pour gagner un cycle - ram_en <='1'; + ram_en <='0'; ram_we <='0'; - dma_wr_grant<=(others=>'0'); - dma_rd_grant<=(others=>'0'); + dma_wr_latch<=(others=>'0'); + dma_rd_latch<=(others=>'0'); --address_out_rd <= (others=>'Z'); --address_out_wr <= (others=>'Z'); @@ -371,7 +420,7 @@ ram_en <='1'; ram_we <='1'; - dma_wr_grant<=(others=>'0'); - dma_wr_grant(pri_wr) <='1'; - dma_rd_grant <=(others=>'0'); + dma_wr_latch<=(others=>'0'); + dma_wr_latch(pri_wr) <='1'; + dma_rd_latch <=(others=>'0'); --address_out_rd <= (others=>'Z'); --address_out_wr <= address_wr; @@ -381,8 +430,8 @@ ram_en <='1'; ram_we <='1'; - dma_wr_grant<=(others=>'0'); - dma_wr_grant(pri_wr) <='1'; - dma_rd_grant<=(others=>'0'); - dma_rd_grant(pri_rd)<='1'; + dma_wr_latch<=(others=>'0'); + dma_wr_latch(pri_wr) <='1'; + dma_rd_latch<=(others=>'0'); + dma_rd_latch(pri_rd)<='1'; --address_out_rd <= address_rd; @@ -392,7 +441,7 @@ ram_en <='1'; ram_we <='0'; - dma_wr_grant<=(others=>'0'); - dma_rd_grant<=(others=>'0'); - dma_rd_grant(pri_rd)<='1'; + dma_wr_latch<=(others=>'0'); + dma_rd_latch<=(others=>'0'); + dma_rd_latch(pri_rd)<='1'; --address_out_rd <= address_rd; @@ -402,6 +451,6 @@ ram_en <='0'; ram_we <='0'; - dma_wr_grant <=(others=>'0'); - dma_rd_grant <=(others=>'0'); + dma_wr_latch <=(others=>'0'); + dma_rd_latch <=(others=>'0'); --address_out_rd <= (others=>'Z'); --address_out_wr <= (others=>'Z'); Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/DMA_ARBITER_envsettings.html =================================================================== --- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/DMA_ARBITER_envsettings.html (revision 45) +++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/DMA_ARBITER_envsettings.html (revision 64) @@ -17,42 +17,42 @@ PATHEXT .COM;
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D:\SDT\testSpawn\release XILINX d:\Xilinx\12.3\ISE_DS\ISE\ +< data not available > d:\Xilinx\12.3\ISE_DS\ISE\ -d:\Xilinx\12.3\ISE_DS\ISE\ -d:\Xilinx\12.3\ISE_DS\ISE\ +d:\Xilinx\12.3\ISE_DS\ISE\ XILINX_DSP D:\Xilinx\12.3\ISE_DS\ISE +< data not available > D:\Xilinx\12.3\ISE_DS\ISE -D:\Xilinx\12.3\ISE_DS\ISE -D:\Xilinx\12.3\ISE_DS\ISE +D:\Xilinx\12.3\ISE_DS\ISE XILINX_EDK D:\Xilinx\12.3\ISE_DS\EDK +< data not available > D:\Xilinx\12.3\ISE_DS\EDK -D:\Xilinx\12.3\ISE_DS\EDK -D:\Xilinx\12.3\ISE_DS\EDK +D:\Xilinx\12.3\ISE_DS\EDK XILINX_PLANAHEAD D:\Xilinx\12.3\ISE_DS\PlanAhead +< data not available > D:\Xilinx\12.3\ISE_DS\PlanAhead -D:\Xilinx\12.3\ISE_DS\PlanAhead -D:\Xilinx\12.3\ISE_DS\PlanAhead +D:\Xilinx\12.3\ISE_DS\PlanAhead @@ -78,5 +78,5 @@   mixed -MIXED +Mixed @@ -95,5 +95,5 @@ -p   -xc3s1200e-5-ft256 +xc6slx45-3-csg324   @@ -117,8 +117,14 @@ +-power +Power Reduction +NO +No + + -iuc Use synthesis Constraints File NO -NO +No @@ -126,5 +132,5 @@ Keep Hierarchy Soft -NO +No @@ -138,5 +144,5 @@ Generate RTL Schematic Yes -NO +No @@ -150,5 +156,5 @@ Read Cores YES -YES +Yes @@ -156,5 +162,5 @@ Write Timing Constraints NO -NO +No @@ -162,5 +168,5 @@ Cross Clock Analysis NO -NO +No @@ -174,5 +180,5 @@ Slice Utilization Ratio 100 -100% +100 @@ -180,11 +186,17 @@ BRAM Utilization Ratio 100 -100% - - --verilog2001 -Verilog 2001 -YES -YES +100 + + +-dsp_utilization_ratio +DSP Utilization Ratio +100 +100 + + +-reduce_control_sets +  +Auto +Auto @@ -192,5 +204,5 @@   YES -YES +Yes @@ -198,5 +210,5 @@   Auto -AUTO +Auto @@ -204,5 +216,5 @@   No -NO +No @@ -216,11 +228,11 @@   Yes -YES +Yes -ram_style   -Auto -AUTO +Block +Auto @@ -228,5 +240,5 @@   Yes -YES +Yes @@ -234,5 +246,5 @@   YES -YES +Yes @@ -240,5 +252,5 @@   Auto -AUTO +Auto @@ -246,5 +258,5 @@   NO -NO +No @@ -252,5 +264,5 @@   YES -YES +Yes @@ -258,11 +270,11 @@   NO -NO - - --mult_style -  -LUT -AUTO +No + + +-use_dsp48 +  +Auto +Auto @@ -270,5 +282,5 @@   YES -YES +Yes @@ -276,11 +288,11 @@   100000 -500 +100000 -bufg   -24 -24 +16 +16 @@ -288,5 +300,5 @@   YES -YES +Yes @@ -294,5 +306,5 @@   No -NO +No @@ -300,23 +312,23 @@   NO -NO +No -use_clock_enable   -Yes -YES +Auto +Auto -use_sync_set   -Yes -YES +Auto +Auto -use_sync_reset   -Yes -YES +Auto +Auto @@ -324,5 +336,5 @@   Auto -AUTO +Auto @@ -330,5 +342,5 @@   YES -YES +Yes @@ -336,11 +348,11 @@   5 -0% +0 - +  
- + @@ -351,4 +363,28 @@ + + + + + + + + + + + + + + + + + + + + + + + + @@ -357,20 +393,38 @@ - - - + + + + + + + + + + + + + + + + + + + + + - +
Translation Property Settings Map Property Settings
-olPlace & Route Effort Level (Overall)highhigh
-xtExtra Cost Tables00
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-tStarting Placer Cost Table (1-100) Map10
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-w truefalse
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-p  xc3s1200e-ft256-5xc6slx45-csg324-3 None
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Map Property Settings Place and Route Property Settings
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-cmOptimization Strategy (Cover Mode)areaarea
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-p xc3s1200e-ft256-5None
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + +
Place and Route Property Settings
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-olPlace & Route Effort Level (Overall)highstd
-w truefalse
@@ -468,28 +474,28 @@ CPU Architecture/Speed Intel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHz +<  data not available  > Intel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHz -Intel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHz -Intel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHz +Intel(R) Core(TM) i7-2670QM CPU @ 2.20GHz/2195 MHz Host GAMOM-PC +<  data not available  > GAMOM-PC -GAMOM-PC -GAMOM-PC +GAMOM-PC OS Name Microsoft +<  data not available  > Microsoft -Microsoft -Microsoft +Microsoft OS Release Service Pack 1 (build 7601) +<  data not available  > Service Pack 1 (build 7601) -Service Pack 1 (build 7601) -Service Pack 1 (build 7601) +Service Pack 1 (build 7601) Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/EX2_FSM.vhd =================================================================== --- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/EX2_FSM.vhd (revision 45) +++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/EX2_FSM.vhd (revision 64) @@ -242,4 +242,5 @@ tempval:=Ram_data_in; tempval(4):='1'; --SET du bit DReceived + tempval(1):='0'; --reset du bit DRING !! data_to_ram<=tempval; rd_ok<='0'; Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/EX4_FSM.vhd =================================================================== --- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/EX4_FSM.vhd (revision 45) +++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/EX4_FSM.vhd (revision 64) @@ -73,5 +73,5 @@ --type init1_type is (init,NocSize,InitToNoc,NextPort,EndBCast); -- MAE pour affectation des rangs aux différentes librairies MPI - type init2_type is (init,GetPortNum,DecodeData,IsPortZero,SeekMain1,SeekMain2,StoreMain,SetMainFlag,GetMainReq,StoreRank,NewRank,SendRank,RegRank,SendApp,EndInit); + type init2_type is (init,GetPortNum,DecodeData,IsPortZero,SeekMain1,SeekMain2,StoreMain,SetMainFlag,ReadNoc,GetMainReq,StoreRank,NewRank,SendRank,RegRank,SendPeerStat,GetPeerStat,SendApp,EndInit); -- MAE pour réception de init depuis le réseau; type init3_type is (init,GetNocSize,ReadInitHead,StorePort,EndInit); @@ -90,4 +90,5 @@ signal cport_out_rd_en,rport_out_rd_en:std_logic; signal tosend,tosend4 :std_logic_vector(Word-1 downto 0); + signal PeerStat : std_logic_vector(15 downto 0):=(others=>'0'); --état des autres Lib initialisées signal selector : std_logic_vector (2 downto 0); -- pour le MUX des signaux vers le port --signaux pour les états des MAE @@ -107,5 +108,5 @@ signal MyRank : std_logic_vector(3 downto 0) ; --rang du PE signal MainPort : std_logic_vector(3 downto 0) ; --Port de la lib main - signal NextRank : std_logic_vector(3 downto 0):=(others=>'0'); --utiliser pour gérer les affectations de rangs MPI + signal NextRank,NextRank_i : std_logic_vector(3 downto 0):=(others=>'0'); --utiliser pour gérer les affectations de rangs MPI signal DataToSend : Typ_PortIo(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); -- permet d'empiler les données à envoyer signal CmdReceived,DataReceived : Typ_PortIO(0 to 3):=((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0')); @@ -115,4 +116,9 @@ --signal BCast_Rdy_i : std_logic; signal cdlen,dcount,timeout,timeout_i : natural range 0 to 255:=0; --longueur du paquet reçu par le process pcmd + signal PortStat : std_logic_vector(3 downto 0):=(others=>'0'); + signal PeerPort : natural range 0 to 15:=0; -- désigne le port qui emet une requête + signal PeerRTS,PeerCTR:std_logic:='0'; + signal cpt,cpt_peer : natural range 0 to 15:=0; --compteur pour le nombre de HT initialisés + signal clk_cyl,clk_cyl_i : natural range 0 to 15:=0; begin --======================================================================================= @@ -132,15 +138,18 @@ --ajout des autres affectations ici Ram_NextAdress<=Ram_NextAdress_i ; - MyPort<=PortNum_i; + RankAsked<=RankAsked_i; RankSent<=RankSent_i; AppRank<=MyRank; timeout<=timeout_i; - + cpt<=cpt_peer; + clk_cyl<=clk_cyl_i; + NextRank<=NextRank_i; end if; end process; - Init2_DECODE: process (stinit2, CmdReceived, EquFlag, MyPort, DS_RDY, MainResp, DataReceived, Ram_NextAdress) + Init2_DECODE: process (stinit2, CmdReceived, EquFlag, MyPort, DS_RDY, MainResp, DataReceived, Ram_NextAdress,PeerRTS) variable nextr,nextadr : natural :=to_integer(unsigned(Ram_NextAdress)); + variable nport : natural range 0 to 15:=0; begin @@ -163,4 +172,5 @@ RankAsked_i<='0'; dma_wr_req<='0'; + When GetPortNum => RTS_cmd<='1'; @@ -189,5 +199,7 @@ Initialized<='0'; CM_Ack <='1'; --les données ont été reçues + MyPort<=Cmdreceived(2)(3 downto 0); PortNum_i<=Cmdreceived(2)(3 downto 0); --récupère les valeurs de port + PeerPort<=To_integer(unsigned(Cmdreceived(2)(3 downto 0))); NocMax<=Cmdreceived(2)(7 downto 4); -- et la taille du réseau PortNumFlag<='1'; -- le numéro du port est maintenant connu @@ -205,5 +217,5 @@ RTS_cmd<='0'; RTS_dat<='0'; - NextRank<="0001"; -- le prochain rang à affecter sera le n° 1 + NextRank_i<="0001"; -- le prochain rang à affecter sera le n° 1 nextr:=1; IsMain<=EquFlag; @@ -240,5 +252,5 @@ RTS_DAT<='0'; CTR<='1' ; -- prêt à recevoir les données Clear To Receive - DS_ACK<='0'; --les données sont attendus + DS_ACK<= DS_RDY; --les données sont acquittées aussitôt reçues Send_Ack<=BCast_rdy; -- DataToSend(0)<=INIT_SEEKMAIN & MyPort ; @@ -269,4 +281,5 @@ RankAsked_i<='0'; EquFlag<='0'; + MainPort<=DataReceived(0)(3 downto 0); AdrRam<= STD_logic_vector(to_unsigned(Core_init_adr+1,16)); DataRam<=DataReceived(0)(3 downto 0)& DataReceived(2)(3 downto 0); --MainPort & MyRank @@ -286,4 +299,5 @@ MyRank<="0000"; MainPort<="0000"; + PeerStat(0)<='1'; --la main lib est initialisée CTR<='1'; DS_ACK<='0'; @@ -294,9 +308,29 @@ DataRam<=(others =>'0'); -- le port vaut 0 et la mainlib est aussi à 0 dma_wr_req<='1'; + When ReadNoc => + if (Datareceived(0)(7 downto 4) = INIT_SEEKMAIN) then + RankAsked_i<='1' ; + else + RankAsked_i<='0'; + end if; + WeRam<='0'; -- pas d'écriture en RAM + BCast<='0'; + DS_ACK<='0'; + --IsMain<='0'; + Result_En<='0'; + Initialized<='0'; + RTS_cmd<='0'; + RTS_DAT<='0'; + CTR<='1'; + ResultOut<=(others=>'0'); + PortNum_i<=DataReceived(2)(3 downto 0); -- le port qui demande un rang; + PeerPort<= To_integer(unsigned(DataReceived(2)(3 downto 0))); + --EquFlag<='1'; + dma_wr_req<='0'; When GetMainReq => - RankAsked_i<='1'; + --RankAsked_i<='1'; WeRam<='0'; -- pas BCast<='0'; - DS_ACK<='0'; + DS_ACK<='1'; IsMain<='0'; Result_En<='0'; @@ -309,12 +343,31 @@ EquFlag<='1'; dma_wr_req<='0'; + When GetPeerStat => + --RankAsked_i<='1'; + WeRam<='0'; -- pas + BCast<='0'; + DS_ACK<='1'; + IsMain<='0'; + Result_En<='0'; + Initialized<='0'; + RTS_cmd<='0'; + RTS_DAT<='0'; + CTR<='1'; + ResultOut<=(others=>'0'); + PortNum_i<=DataReceived(0)(3 downto 0); --adresse du Main Port + EquFlag<='1'; + dma_wr_req<='0'; When NewRank => - nextr:=nextr+1; + nport:=to_integer(Unsigned(PortNum_i)); --port ayant sollicité le rang + if PeerStat(nport)='0' then -- si le rang n'a pas encore été affecté à ce port + nextrank_i<=incr_vec(nextrank,'1'); NextAdr:=NextAdr+1; + end if; --NextRank<=incr_vec(NextRank,'1'); - NextRank<=STD_logic_vector(to_unsigned(nextr,4)); + nextr:=to_integer(unsigned(nextrank)); DataToSend(0)<=INIT_SETRANK & PortNum_i ; DataToSend(1)<="00000011"; DataToSend(2)<="0000" & NextRank; --ici c'est la valeur avant incrémentation ! + PeerStat(nport)<='1'; -- mise à jour du status DataLen<=3; BCast<='0'; @@ -338,4 +391,47 @@ RTS_cmd<='0'; DS_ACK<='0'; + Send_Ack<='0'; + IsMain<='0'; + CTR<='0' ; + WeRam<='0'; + Ram_NextAdress_i<= STD_logic_vector(to_unsigned(CORE_RANK_ADR+Nextr-1,16)); + ResultOut<=(others=>'0'); + RankAsked_i<='1'; + Initialized<='0'; + dma_wr_req<='0'; + When RegRank => +-- if (Datareceived(0)(7 downto 4) = INIT_SEEKMAIN) then +-- RankAsked_i<='1'; +-- else + RankAsked_i<='0'; +-- end if; + CTR<='1' ; -- continuer à recevoir les données du NoC + Result_En<='0'; + Initialized<='0'; + RTS_cmd<='0'; + DS_ACK<='0'; + Send_Ack<=Send_RDY; + IsMain<='0'; + Rts_Dat<='0'; + BCast<='0'; + EquFlag<='1'; + WeRam<='1'; + + Ram_NextAdress_i<= STD_logic_vector(to_unsigned(CORE_RANK_ADR+Nextr-1,16)); --incr_vec(Ram_NextAdress,'1'); + AdrRam<=Ram_NextAdress; -- le rang qui a été envoyé; + -- "le motif 0001 indique juste que le port est bien activé + DataRam<="0001" & PortNum_i; --enregistrer le port qui a fait la demande en RAM + ResultOut<=(others=>'0'); + dma_wr_req<='1'; + When SendPeerStat => + BCast<='0'; + Result_En<='0'; + EquFlag<='0'; + Rts_DAT<=PeerRTS; + RTS_cmd<='0'; + DS_ACK<='0'; + DataToSend(0)<=INIT_REGISTER & PortStat ; + DataToSend(1)<="00000011"; + DataToSend(2)<=PeerStat(7 downto 0); Send_Ack<=Send_Rdy; IsMain<='0'; @@ -346,27 +442,4 @@ Initialized<='0'; dma_wr_req<='0'; - When RegRank => - if (Datareceived(0)(7 downto 4) = INIT_SEEKMAIN) then - RankAsked_i<='1'; - else - RankAsked_i<='0'; - end if; - CTR<='0' ; - Result_En<='0'; - Initialized<='0'; - RTS_cmd<='0'; - DS_ACK<='0'; - Send_Ack<='0'; - IsMain<='0'; - Rts_Dat<='0'; - BCast<='0'; - EquFlag<='1'; - WeRam<='1'; - - Ram_NextAdress_i<= STD_logic_vector(to_unsigned(NextAdr,16)); --incr_vec(Ram_NextAdress,'1'); - AdrRam<=Ram_NextAdress; -- le rang qui a été envoyé; - DataRam<=DataToSend(2)(3 downto 0) & MyPort; - ResultOut<=(others=>'0'); - dma_wr_req<='1'; When StoreRank => --le processus qui écoute le Port et qui --stoke les adresses des autres bib va gérer le stockage du rang @@ -429,7 +502,9 @@ end process; - NEXT_STInit2_DECODE: process (stInit2,AppReq, AppAck,PortNumFlag,EquFlag,MainResp,RankAsked,RankSent,CM_RDY, CmdReceived, BCast_Rdy, DS_RDY, DataReceived, Send_RDY,TimeOut,Dma_wr_grant) + NEXT_STInit2_DECODE: process (stInit2,AppReq, AppAck,PortNumFlag,EquFlag,MainResp,RankAsked,RankSent,CM_RDY, CmdReceived, + BCast_Rdy, DS_RDY, DataReceived, Send_RDY,TimeOut,Dma_wr_grant,cpt,clk_cyl) variable InitTimeOut :natural:=0; - variable nulvect : std_logic_vector(3 downto 0):="0000"; + variable vPortStat,nulvect : std_logic_vector(3 downto 0):="0000"; + begin --declare default state for next_state to avoid latches @@ -442,9 +517,9 @@ When Init =>If AppReq='1' then If PortNumFlag='1' and RankAsked='1' then - Next_stInit2 <=GetMainReq; + Next_stInit2 <=ReadNoC; else Next_stInit2 <=GetPortNum; end if; - TimeOut_i<=0; + TimeOut_i<=0;PeerRTS<='0'; end if; @@ -480,19 +555,27 @@ End if; When SeekMain2 => - If DS_RDY='1' then -- Si un jeu de données a été reçu - Next_stInit2 <=StoreMain; -- de la librairie pricipale - elsif ExecTime_Out='1' then + If DS_RDY='1' then -- Si un jeu de données a été reçu + if (Datareceived(0)(7 downto 4) = INIT_SETRANK) then + MainResp<='1'; + Next_stInit2 <=StoreMain; -- de la librairie pricipale + else + MainResp<='0'; + Timeout_i<=0; + end if; + + elsif (ExecTime_Out='1') then + -- le Noc ne répond pas -- affecter un numéro en raport avec le port - Next_stInit2 <=StoreMain; - else + Next_stInit2 <=SeekMain2; + elsif TimeOut=150 then + --essayer de redemander l'initialisation + Timeout_i<=0; + Next_stInit2 <=SeekMain2; + else Timeout_i<=TimeOut+1; - End if; + End if; - if (Datareceived(0)(7 downto 4) = INIT_SETRANK) then - MainResp<='1'; - else - MainResp<='0'; - end if; + When StoreMain => @@ -516,28 +599,63 @@ -- la donnée ... if dma_wr_grant = '1' then - Next_stInit2 <=SendApp; + if clk_cyl=2 then --prévoir deux cycle d'horloge pour lire en RAM + Next_stInit2 <=GetPeerStat; + TimeOut_i<=0; + clk_cyl_i<=0; + else + clk_cyl_i<=clk_cyl+1; + end if; else Next_stInit2 <=StoreRank; + TimeOut_i<=0; + clk_cyl_i<=0; end if; + When GetPeerStat => + If DS_RDY='1' then -- Si un jeu de données a été reçu + if (Datareceived(0) = INIT_REGISTER & MainPort ) then + MainResp<='1'; + Next_stInit2 <=SendApp; -- de la librairie pricipale + else + MainResp<='0'; + Timeout_i<=0; + end if; + + elsif (ExecTime_Out='1') then + + + Next_stInit2 <=EndInit; + elsif TimeOut=180 then + --essayer de redemander l'initialisation + + Next_stInit2 <=SeekMain1; + else + Timeout_i<=TimeOut+1; + End if; When SetMainFlag => - if dma_wr_grant='1' then - if DS_RDY='1' then - - - Next_stInit2 <=GetMainReq; - elsif Timeout=240 then + if dma_wr_grant='1' then + TimeOut_i<=0; + Next_stInit2 <=ReadNoc; + elsif Timeout=200 then Next_stInit2 <=SendApp; else TimeOut_i<=TimeOut+1; - end if; -- il est envisagée de terminer le programme à ce point +-- end if; -- il est envisagée de terminer le programme à ce point end if; - When GetMainReq => - - if RankAsked='1' then - Next_stInit2 <=NewRank; - else - Next_stInit2 <=SendApp; - end if; + when ReadNoc => if DS_RDY='1' then + Next_stInit2 <=GetMainReq; + Timeout_i<=0; + elsif Timeout=80 then + Timeout_i<=0; + Next_stInit2 <=SendPeerStat; + else + TimeOut_i<=TimeOut+1; + end if; + + When GetMainReq => if RankAsked='1' and PeerStat(PeerPort)='0' then + Next_stInit2 <=NewRank; -- un nouveau rang est demandé + else + Next_stInit2 <=ReadNoC; -- sinon essayer encore de lire un jeu de données. + end if; When NewRank => Next_stInit2 <=SendRank; @@ -553,15 +671,53 @@ -- la donnée ... if dma_wr_grant = '1' then - - - if DS_RDY='1' then +-- if DS_RDY='1' then RankSent_i<='0'; - Next_stInit2 <=GetMainReq; - elsif Timeout=10 then + if DS_RDY='0' then + Next_stInit2 <=ReadNoc; + end if; + elsif Timeout=150 then Next_stInit2 <=SendApp; else TimeOut_i<=TimeOut+1; - end if; -- il est envisagée +-- end if; -- il est envisagée + end if; + When SendPeerStat => + if cpt<=(unsigned(NoCMax)) then + if peerRts='0' then -- pas encore envoyer les données alors les préparer + PortStat<=std_logic_vector(to_unsigned(cpt,4));--Port à contacter + vPortStat:=std_logic_vector(to_unsigned(cpt,4)); + if (PeerStat(cpt)='1') and not(vPortStat=MyPort) then + PeerRts<='1'; + + end if; + cpt_peer<=cpt+1; + TimeOut_i<=0; + else + if Send_RDY='1' then --RankSent + --Next_stInit2 <= RegRank; + RankSent_i<='1'; -- les stat ont été envoyé + TimeOut_i<=0; -- prépare le traitement de la prochaine requête + PeerRts<='0'; -- d'attente des ports + elsif TimeOut_i=100 then + Next_stInit2 <=EndInit ;-- impossible d'envoyer sur le NoC + else + TimeOut_i<=TimeOut_i+1; + end if; + end if; + elsif PeerRTS='1' then -- le dernier port est il activé ? + if Send_RDY='1' then --RankSent + RankSent_i<='1'; -- les stat ont été envoyé + TimeOut_i<=0; -- prépare le traitement de la prochaine requête + PeerRts<='0'; + Next_stInit2<=SendApp; + + elsif TimeOut_i=100 then + Next_stInit2 <=EndInit; + else + TimeOut_i<=TimeOut_i+1; + end if; + else + Next_stInit2<=SendApp; end if; When SendApp => -- envoyer au programme un signal @@ -633,4 +789,5 @@ variable dcount,dlen ,rtimeout:natural range 0 to 255; variable ptype : std_logic_vector(3 downto 0); + variable bad_paquet :std_logic:='0'; begin -- @@ -640,4 +797,5 @@ destport:=1; rtimeout:=0; + bad_paquet:='0'; else case etrec is @@ -645,15 +803,19 @@ rtimeout:=0; - + bad_paquet:='0'; if Port_out_data_available='1' and CTR='1' then ptype:=port_out_data(7 downto 4); origport:=to_integer(unsigned(port_out_data(3 downto 0))); - if ptype=MPI_INIT or ptype=INIT_SETRANK or ptype=INIT_SEEKMAIN then + if ptype=MPI_INIT or ptype=INIT_SETRANK or ptype=INIT_SEEKMAIN or ptype=INIT_REGISTER then etrec<=r_dlen; --identification de la signature d'en tête valide Datareceived(0)<=Port_out_data; --stocker l'entête + bad_paquet:='0'; else --une donnée non attendue est présente sur le port - etrec<=r_drop; + etrec<=r_dlen; + dcount:=1; + bad_paquet:='1'; + Datareceived(0)<=(others=>'0'); end if; --elsif Port_out_data_available='1' and CTR='0' then @@ -663,12 +825,17 @@ etrec<=r_wait; end if; - + DS_RDY<='0'; When r_drop => -- ignorer les messages qui arrivent à ce noeud tant que --l'application n'a pas été initialisée if port_out_data_available='0' then etrec<=r_end; + dcount:=0; + end if; + + + --Rport_out_rd_en<='1'; --lire les données qui sont dans le tampon de sortie - --DS_RDY<='0'; + DS_RDY<='0'; when r_Dlen => --positionnement du mot de longueur des données if Port_out_data_available ='1' then @@ -686,5 +853,5 @@ end if; - --DS_RDY<='0'; + DS_RDY<='0'; -- when r_glen => --lecture effective de la longueur des données @@ -704,19 +871,24 @@ end if; - --DS_RDY<='0'; + DS_RDY<='0'; when r_data => -- lecture des données if port_out_data_available='1' then --Rport_out_rd_en<='1'; --autoriser la lecture - DataReceived(dcount)<=Port_out_data; --récupération des données + if bad_paquet='0' then + DataReceived(dcount)<=Port_out_data; --récupération des données + else + DataReceived(2)<=(others=>'0'); + --ignorer ces données + end if; --assert true report "Donnée lue :"; --& string(unsigned(port4_out(Word-1 downto 0))) - --DS_RDY<='0'; + DS_RDY<='0'; dcount:=dcount+1; --severity note; if dlen <=dcount then -- ce doit être égale ici et non <= ??? etrec<=r_end; - --DS_RDY<='1'; -- jeu de données disponibles + DS_RDY<='1'; -- jeu de données disponibles elsif dcount=255 then --dépassement de la capacité - --DS_RDY<='0'; + DS_RDY<='0'; etrec<=r_end; end if; @@ -727,18 +899,19 @@ etrec<=r_end; -- données pas prêtes end if; - --DS_RDY<='0'; + DS_RDY<='0'; end if; when r_pulse => etrec<=r_end; + DS_RDY<='1'; when r_end => - - - + --rPort_out_rd_en <='0'; - if DS_ACK='1' or rtimeout> 30 or CTR='0' then - --DS_RDY<='0'; + if DS_ACK='1' or rtimeout> 30 or CTR='0' or bad_paquet='1' then + DS_RDY<='0'; etrec<=r_wait; + else + DS_RDY<=DS_RDY; end if; @@ -754,34 +927,34 @@ case etrec is when r_wait => - DS_RDY<='0'; +-- DS_RDY<='0'; Rport_out_rd_en <='0'; when r_dlen => - DS_RDY<='0'; +-- DS_RDY<='0'; Rport_out_rd_en <='1'; rcv_On<='1'; when r_drop => - DS_RDY<='0'; +-- DS_RDY<='0'; Rport_out_rd_en <='1'; rcv_On<='1'; when r_glen => Rport_out_rd_en <='1'; - DS_RDY<='0'; +-- DS_RDY<='0'; rcv_On<='1'; when r_data => Rport_out_rd_en <='1'; - DS_RDY<='0'; +-- DS_RDY<='0'; rcv_On<='1'; when r_pulse => Rport_out_rd_en <='0'; rcv_On<='1'; - DS_RDY<='1'; +-- DS_RDY<='1'; when r_end => Rport_out_rd_en <='0'; - DS_RDY<='1'; +-- DS_RDY<='0'; rcv_On<='0'; when others => Rport_out_rd_en <='0'; - DS_RDY<='0'; +-- DS_RDY<='0'; rcv_On<='0'; end case; @@ -887,5 +1060,5 @@ when s_end => tosend<=(others=>'Z'); - Send_RDY<='1'; + sPort_in_wr_en<='0'; Snd_on<='0'; @@ -898,4 +1071,5 @@ if Send_ack='1' then etsnd<=s_init; + Send_RDY<='0'; end if; end if; @@ -904,4 +1078,5 @@ if Send_ack='1' then etsnd<=s_init; + Send_RDY<='0'; end if; Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MPI_CORE_COMPONENTS.gise =================================================================== --- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MPI_CORE_COMPONENTS.gise (revision 45) +++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MPI_CORE_COMPONENTS.gise (revision 64) @@ -26,6 +26,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -78,10 +136,8 @@ - - @@ -120,7 +176,7 @@ - + @@ -150,4 +206,13 @@ + + + + + + + + + @@ -155,8 +220,12 @@ + + + + @@ -171,4 +240,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -176,4 +275,7 @@ + + + @@ -185,36 +287,214 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -225,5 +505,4 @@ - @@ -232,15 +511,18 @@ + - - - - - + + + + + + + @@ -249,8 +531,9 @@ - + + @@ -263,8 +546,9 @@ - + + @@ -278,38 +562,12 @@ - - - - - - - - - - - - - - - - - + + + + - - - - - - - - - - - - - Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MPI_CORE_COMPONENTS.xise =================================================================== --- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MPI_CORE_COMPONENTS.xise (revision 45) +++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MPI_CORE_COMPONENTS.xise (revision 64) @@ -69,5 +69,4 @@ - @@ -82,4 +81,6 @@ + + @@ -125,8 +126,10 @@ + + @@ -193,90 +196,110 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + @@ -404,5 +427,5 @@ - + @@ -443,6 +466,6 @@ - - + + @@ -555,10 +578,10 @@ - - - - - - + + + + + + @@ -580,8 +603,8 @@ - - - - + + + + @@ -646,5 +669,5 @@ - + @@ -653,5 +676,5 @@ - + @@ -664,4 +687,6 @@ + + Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MPI_RMA.vhd =================================================================== --- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MPI_RMA.vhd (revision 45) +++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MPI_RMA.vhd (revision 64) @@ -31,4 +31,5 @@ base :std_logic_vector; size : Mpi_Aint;disp_unit:natural; info:natural; comm:Mpi_Comm; Win: inout MPI_Win ); +procedure pMPI_Win_start( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; pgroup:MPI_group;asser : natural; Win :MPI_Win); procedure pMPI_Win_wait( NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram; Win :MPI_Win); -- declare functions and procedure @@ -76,4 +77,5 @@ if dcount>=0 and dcount <=3 then if interf.ramsel='0' then + Interf.membusy<='0'; SysRam.we<='1'; SysRam.ena<='1'; @@ -90,4 +92,5 @@ SysRam.ena<='1'; SysRam.enb<='0'; + Interf.membusy<='1'; adresse:=core_put_adr; sysRam.Data_in<=MPI_PUT & std_logic_vector(to_unsigned(Target_Rank,4)); --code fonction @@ -141,4 +144,5 @@ sysRam.Data_in<=x"01"; --instruction pulse enable via la mémoire; Interf.Instr_En<='1'; --active la prise en compte de l'instruction + Interf.membusy<='0'; dcount:=dcount+1; end if; @@ -166,4 +170,5 @@ SysRam.Data_in<=config_reg ; --ramener le IPulse à 0; dcount:=dcount+1; + Interf.membusy<='1'; end if; SysRam.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); @@ -182,12 +187,15 @@ SysRam.ena<='0'; SysRam.enb<='1'; - if Interf.RamSel='0' then + Interf.membusy<='0'; + if Interf.ramsel='0' then SysRam.addr_rd<=Std_logic_vector(to_unsigned(Core_put_adr+6,Adrlen)); if SysRam.Data_out(0)='1' then --fin du MPI PUT ici pour l'envoie ! dcount:=dcount+1; + end if; end if; elsif dcount=15 then dcount:=0; --fin normale de la fonction + Interf.membusy<='0'; end if; @@ -206,5 +214,5 @@ variable addr2 :std_logic_vector(Target_Disp'length-1 downto 0):=Target_Disp; variable get_adr : std_logic_vector (ADRLEN-1 downto 0); -variable config_reg: std_logic_vector (Word-1 downto 0); +variable config_reg,win_reg: std_logic_vector (Word-1 downto 0); constant LeftZero: std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0'); begin @@ -230,4 +238,5 @@ WritePtr (get_adr,wcount,SysRam); interf.intstate1<=wcount; + Interf.membusy<='1'; if wcount =0 then dcount:=4; @@ -236,16 +245,17 @@ elsif dcount=4 then - if Interf.RamSel='0' then + if Interf.ramsel='0' then SysRam.we<='1'; SysRam.ena<='1'; SysRam.enb<='0'; + adresse:=core_get_adr; sysRam.Data_in<=MPI_GET & std_logic_vector(to_unsigned(Target_Rank,4)); --code fonction sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); - + Interf.membusy<='1'; dcount:=dcount+1; end if; elsif dcount=5 then - if Interf.RamSel='0' then + if Interf.ramsel='0' then SysRam.we<='1'; SysRam.ena<='1'; @@ -257,5 +267,5 @@ end if; elsif dcount=6 then - if Interf.RamSel='0' then + if Interf.ramsel='0' then SysRam.we<='1'; SysRam.ena<='1'; @@ -269,5 +279,5 @@ end if; elsif dcount=7 then - if Interf.RamSel='0' then + if Interf.ramsel='0' then SysRam.we<='1'; SysRam.ena<='1'; @@ -281,5 +291,5 @@ end if; elsif dcount=8 then - if Interf.RamSel='0' then + if Interf.ramsel='0' then SysRam.we<='1'; SysRam.ena<='1'; @@ -287,5 +297,5 @@ sysRam.Data_in<= Addr2(ADRLEN-1 downto Word) ; -- destination haut sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); - + Interf.membusy<='1'; dcount:=dcount+1; else @@ -299,5 +309,5 @@ sysRam.Data_in<=Addr2(Word-1 downto 0); -- destination bas sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); - + Interf.membusy<='0'; dcount:=dcount+1; end if; @@ -328,5 +338,6 @@ SysRam.we<='0'; SysRam.ena<='0'; -- préparer la lecture du résultat du get - SysRam.enb<='1'; + SysRam.enb<='1'; + Interf.membusy<='0'; elsif dcount=12 then @@ -339,4 +350,5 @@ SysRam.Data_in<=config_reg ; --ramener le IPulse à 0; dcount:=dcount+1; + Interf.membusy<='1'; end if; SysRam.addr_rd<=std_logic_vector(to_unsigned(core_base_adr+1,ADRLEN)); @@ -354,5 +366,5 @@ SysRam.Data_in<=config_reg ; --ramener le IPulse à 0; dcount:=dcount+1; - + Interf.membusy<='0'; end if; elsif dcount=14 then @@ -360,12 +372,16 @@ SysRam.ena<='0'; SysRam.enb<='1'; + Interf.membusy<='0'; if Interf.RamSel='0' then SysRam.addr_rd<=Std_logic_vector(to_unsigned(Core_get_adr+6,Adrlen)); if SysRam.Data_out(0)='1' then --fin du MPI get ici pour l'envoie ! dcount:=dcount+1; + end if; end if; + elsif dcount=15 then dcount:=0; --fin normale de la fonction + Interf.membusy<='0'; end if; @@ -413,4 +429,5 @@ Rank<=SysRam.Data_out(3 downto 0); NextCtx:=2; + Interf.membusy<='1'; end if; elsif NextCtx=2 then @@ -423,4 +440,5 @@ Rank<=SysRam.Data_out(3 downto 0); NextCtx:=3; + Interf.membusy<='1'; end if; elsif NextCtx=3 then @@ -432,5 +450,17 @@ if interf.ramsel='0' then Rank<=SysRam.Data_out(3 downto 0); + NextCtx:=4; + Interf.membusy<='1'; + end if; + elsif NextCtx=4 then + SysRam.we<='0'; + SysRam.ena<='0'; + SysRam.enb<='1'; + adresse_rd:=CORE_INIT_ADR+1; + sysRam.Addr_rd<=Std_logic_vector(to_unsigned(adresse_rd,ADRLEN)); + if interf.ramsel='0' then + Rank<=SysRam.Data_out(3 downto 0); NextCtx:=0; + Interf.membusy<='0'; end if; end if; @@ -469,4 +499,5 @@ NExtCtx:=NextCtx+1; count:=0; + Interf.membusy<='0'; Interf.Intstate1<=count; elsif NextCtx>=1 and NextCtx <= 4 then @@ -618,4 +649,6 @@ -- la source veut communiquer et par la suite envoie un message de synchro sur le réseau à --chacune de ces cibles + variable dcount : natural range 0 to 255:=0; + variable cstatus : std_logic_vector(Word-1 downto 0); begin @@ -623,5 +656,33 @@ -- initialisation des bits concernant - + if NextCtx =0 then + NextCtx:=NextCtx+1; + elsif NextCtx=1 then + if interf.ramsel='0' then + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='0'; + SysRam.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+4,Adrlen)); + SysRam.Data_in<=x"01"; --mise à 1 du bit WSTART et remise à zero de tous les autres Bits + + NextCtx:=NextCtx+1; + Interf.membusy<='1'; + + end if; + elsif NextCtx=2 then + if interf.ramsel='0' then + SysRam.we<='1'; + SysRam.ena<='1'; + SysRam.enb<='0'; + SysRam.addr_wr<=Std_logic_vector(to_unsigned(core_base_adr+4,Adrlen)); + SysRam.Data_in<=x"01"; + NextCtx:=NextCtx+1; + Interf.membusy<='0'; + end if; + elsif NextCtx=3 then + NextCtx:=0; + Interf.membusy<='0'; + end if; + end procedure; @@ -655,5 +716,5 @@ SysRam.enb<='1'; SysRam.addr_rd<=Std_logic_vector(to_unsigned(core_base_adr+4,Adrlen)); - if SysRam.Data_out(5)='1' and SysRam.Data_out(4)='1' and SysRam.Data_out(2)='0' then + if (SysRam.Data_out(5)='1' and SysRam.Data_out(4)='1') and SysRam.Data_out(2)='0' and SysRam.Data_out(1)='0' then NextCtx:=NextCtx+1; end if; @@ -691,5 +752,5 @@ sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); - + Interf.membusy<='1'; Interf.Instr_En<='0'; end if; @@ -704,4 +765,5 @@ sysRam.Addr_wr<=Std_logic_vector(to_unsigned(adresse,ADRLEN)); Interf.Instr_En<='0'; + Interf.membusy<='1'; end if; @@ -723,4 +785,5 @@ WritePtr (init_adr,dcount,SysRam); Interf.Instr_En<='0'; + Interf.membusy<='1'; --if dcount =0 then NextCtx:=4; @@ -744,4 +807,5 @@ SysRam.enb<='1'; dcount:=0; + Interf.membusy<='0'; Interf.Instr_En<='1'; sysRam.Addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,AdrLen)); @@ -760,12 +824,14 @@ SysRam.ena<='0'; SysRam.enb<='1'; - if Interf.RamSel='0' then + if Interf.ramsel='0' then SysRam.addr_rd<=Std_logic_vector(to_unsigned(Core_base_adr,Adrlen)); if SysRam.Data_out(4)='1' then NextCtx:=11; end if; + Interf.membusy<='0'; end if; elsif NextCtx =11 then Interf.Instr_En<='0'; + Interf.membusy<='0'; SysRam.we<='0'; SysRam.ena<='0'; @@ -796,12 +862,13 @@ if dcount=0 then - if Interf.RamSel='0' then - dcount :=dcount+1; + if Interf.ramsel='0' then + dcount :=dcount+1; + Interf.membusy<='1'; end if; sysRam.Data_in<=AdrToSet(Word-1 downto 0); sysRam.Addr_wr<=adrToSet; elsif dcount=1 then - if Interf.RamSel='0' then - + if Interf.ramsel='0' then + Interf.membusy<='1'; dcount :=dcount+1; end if; @@ -813,5 +880,5 @@ sysRam.Addr_wr<=AdrToSet; elsif dcount=3 then - + Interf.membusy<='1'; dcount :=dcount+1; sysRam.Addr_wr<=adrToSet; @@ -819,4 +886,5 @@ elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM dcount:=0; + Interf.membusy<='0'; sysRam.Addr_wr<=AdrToSet; end if; @@ -843,6 +911,7 @@ if dcount=0 then - if Interf.RamSel='0' then - dcount :=dcount+1; + if Interf.ramsel='0' then + dcount :=dcount+1; + Interf.membusy<='1'; end if; @@ -857,12 +926,13 @@ sysRam.Addr_rd<=adrToSet; elsif dcount=3 then - if Interf.RamSel='0' then + if Interf.ramsel='0' then dcount :=dcount+1; sysRam.Addr_rd<=adrToSet; data:=sysRam.Data_out; + Interf.membusy<='0'; end if; elsif dcount=4 then -- ce cycle permet juste de vider le tampon d'écriture en RAM dcount:=0; - + Interf.membusy<='0'; end if; Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MultiMPITest.vhd =================================================================== --- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MultiMPITest.vhd (revision 45) +++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MultiMPITest.vhd (revision 64) @@ -70,8 +70,8 @@ constant clk_period : time := 10 ns; - constant PROC : positive :=8; + constant PROC : positive :=16; -- synthesis translate_off --===================signaux pour l'horloge ============================== -signal reset,clkm : std_logic := '0'; +--signal reset,clkm : std_logic := '0'; --======================================================================== -- synthesis translate_on @@ -95,5 +95,5 @@ ); -PE1: PE generic map (DestId=>1) +PE1: PE generic map (DestId=>0) Port Map ( Instruction => MPi_Node_in(1).Instruction, @@ -113,5 +113,5 @@ ); -PE2: PE Generic map (DestId=>0) +PE2: PE Generic map (DestId=>1) Port Map ( Instruction => MPi_Node_in(2).Instruction, @@ -148,21 +148,21 @@ ); ---PE4: PE Generic map (DestId=>3) --- Port Map ( --- Instruction => MPi_Node_in(4).Instruction, --- Instruction_en => MPi_Node_in(4).Instruction_en, --- Core_PushOut => MPi_Node_out(4).PushOut, --- clk =>clkm, --- reset =>reset, --- Core_RAM_Data_Out =>MPi_Node_in(4).Ram_Data_out, --- Core_RAM_Data_IN => MPI_Node_out(4).ram_data_in, --- Core_RAM_WE => MPI_Node_out(4).ram_we, --- Core_RAM_EN => MPI_Node_out(4).ram_en, --- --Core_RAM_ENB => MPI_Node_out(2).ram_en, --- Core_RAM_Address_Wr => MPI_Node_out(4).ram_address_wr, --- Core_RAM_Address_Rd => MPI_Node_out(4).ram_address_rd, --- Core_Hold_req => MPI_Node_out(4).hold_req, --- Core_Hold_Ack => MPI_Node_in(4).hold_ack ---); +PE4: PE Generic map (DestId=>3) + Port Map ( + Instruction => MPi_Node_in(4).Instruction, + Instruction_en => MPi_Node_in(4).Instruction_en, + Core_PushOut => MPi_Node_out(4).PushOut, + clk =>clkm, + reset =>reset, + Core_RAM_Data_Out =>MPi_Node_in(4).Ram_Data_out, + Core_RAM_Data_IN => MPI_Node_out(4).ram_data_in, + Core_RAM_WE => MPI_Node_out(4).ram_we, + Core_RAM_EN => MPI_Node_out(4).ram_en, + --Core_RAM_ENB => MPI_Node_out(2).ram_en, + Core_RAM_Address_Wr => MPI_Node_out(4).ram_address_wr, + Core_RAM_Address_Rd => MPI_Node_out(4).ram_address_rd, + Core_Hold_req => MPI_Node_out(4).hold_req, + Core_Hold_Ack => MPI_Node_in(4).hold_ack +); MPI_Node_in(1).reset<=reset; MPI_Node_in(1).clk<=clkm; @@ -178,23 +178,23 @@ --============================================================= -- synthesis translate_off - clk_process :process - begin - clkm <= '0' ; - wait for clk_period/2; - clkm <= '1' ; - wait for clk_period/2; - end process; - stim_proc: process - begin +-- clk_process :process +-- begin +-- clkm <= '0' ; +-- wait for clk_period/2; +-- clkm <= '1' ; +-- wait for clk_period/2; +-- end process; +-- stim_proc: process +-- begin -- hold reset state for 100 ns. - reset<='0'; - wait for 1 ns; - reset<='1'; - wait for clk_period*10; - reset<='0'; - wait; - - - end process; +-- reset<='0'; +-- wait for 1 ns; +-- reset<='1'; +-- wait for clk_period*10; +-- reset<='0'; +-- wait; +-- +-- +-- end process; -- synthesis translate_on --================================================================ Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MultiMPITest_summary.html =================================================================== --- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MultiMPITest_summary.html (revision 45) +++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MultiMPITest_summary.html (revision 64) @@ -3,5 +3,5 @@ - + @@ -26,5 +26,5 @@ - + @@ -41,5 +41,5 @@ +1 Failing Constraint @@ -50,5 +50,5 @@ - +
SWITCH_GEN Project Status (12/17/2012 - 14:30:15)
DMA_ARBITER Project Status (04/03/2013 - 19:35:29)
Project File:Product Version:ISE 12.3
  • Warnings:
3183 Warnings (2171 new)3132 Warnings (78 new)
X -10 Failing Constraints
  • Final Timing Score:
2511  (Timing Report)3412527  (Timing Report)
@@ -62,5 +62,5 @@ Number of Slice Registers -2,787 +2,815 54,576 5% @@ -68,5 +68,5 @@     Number used as Flip Flops -2,177 +2,208     @@ -74,5 +74,5 @@     Number used as Latches -610 +607     @@ -92,5 +92,5 @@ Number of Slice LUTs -12,107 +12,079 27,288 44% @@ -98,5 +98,5 @@     Number used as logic -6,962 +6,942 27,288 25% @@ -104,5 +104,5 @@         Number using O6 output only -5,563 +5,481     @@ -116,5 +116,5 @@         Number using O5 and O6 -990 +1,052     @@ -188,5 +188,5 @@     Number used exclusively as route-thrus -57 +49     @@ -194,5 +194,5 @@         Number with same-slice register load -9 +1     @@ -212,11 +212,11 @@ Number of occupied Slices -3,948 +3,785 6,822 -57% +55%   Number of LUT Flip Flop pairs used -12,444 +12,380     @@ -224,23 +224,23 @@     Number with an unused Flip Flop -9,820 -12,444 +9,722 +12,380 78%       Number with an unused LUT -337 -12,444 +301 +12,380 2%       Number of fully used LUT-FF pairs -2,287 -12,444 -18% +2,357 +12,380 +19%       Number of unique control sets -858 +855     @@ -248,5 +248,5 @@     Number of slice register sites lost
        to control set restrictions -3,341 +3,313 54,576 6% @@ -266,7 +266,7 @@ Number of RAMB8BWERs -0 +3 232 -0% +1%   @@ -398,5 +398,5 @@ Average Fanout of Non-Clock Nets -5.70 +5.66     @@ -411,5 +411,5 @@ Final Timing Score: -2511 (Setup: 2511, Hold: 0) +3412527 (Setup: 3412527, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report @@ -425,5 +425,5 @@ X -10 Failing Constraints +1 Failing Constraint     @@ -436,21 +436,22 @@ Report NameStatusGenerated ErrorsWarningsInfos -Synthesis ReportCurrentMon 17. Dec 14:18:41 201201257 Warnings (277 new)428 Infos (8 new) -Translation ReportCurrentMon 17. Dec 14:18:50 20120102 Warnings (70 new)0 -Map ReportCurrentMon 17. Dec 14:26:12 20120974 Warnings (974 new)8 Infos (2 new) -Place and Route ReportCurrentMon 17. Dec 14:29:38 20120850 Warnings (850 new)4 Infos (0 new) +Synthesis ReportCurrentWed 3. Apr 19:05:13 201301211 Warnings (3 new)433 Infos (10 new) +Translation ReportCurrentWed 3. Apr 19:05:27 20130102 Warnings (0 new)0 +Map ReportCurrentWed 3. Apr 19:13:28 20130967 Warnings (74 new)8 Infos (0 new) +Place and Route ReportCurrentWed 3. Apr 19:34:53 20130852 Warnings (1 new)0 Power Report      -Post-PAR Static Timing ReportCurrentMon 17. Dec 14:30:13 2012003 Infos (0 new) -Bitgen ReportOut of DateSat 8. Dec 15:41:28 20120693 Warnings (693 new)0 +Post-PAR Static Timing ReportCurrentWed 3. Apr 19:35:24 2013002 Infos (0 new) +Bitgen ReportOut of DateWed 19. Dec 13:42:44 201201106 Warnings (565 new)0  
- - - + + + +
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateFri 7. Dec 14:52:37 2012
WebTalk ReportOut of DateSat 8. Dec 15:45:26 2012
WebTalk Log FileOut of DateSat 8. Dec 15:45:32 2012
ISIM Simulator LogOut of DateWed 3. Apr 19:01:58 2013
Post-Map Static Timing ReportOut of DateWed 19. Dec 17:30:44 2012
WebTalk ReportOut of DateMon 18. Mar 11:20:20 2013
WebTalk Log FileOut of DateMon 18. Mar 11:20:25 2013
-
Date Generated: 12/17/2012 - 14:30:15
+
Date Generated: 04/03/2013 - 19:35:29
Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MultiTest.wcfg =================================================================== --- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MultiTest.wcfg (revision 45) +++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/MultiTest.wcfg (revision 64) @@ -4,9 +4,9 @@ - + - + @@ -18,308 +18,165 @@ - - + + + + + + + reset reset - - mpi_node_in[1:4] - mpi_node_in[1:4] - HEXRADIX + + runstate + runstate - - mpi_node_out[1:4] - mpi_node_out[1:4] - HEXRADIX + + runstate + runstate - - cm_rdy - cm_rdy + + runstate + runstate - - core_ram_address_rd[15:0] - core_ram_address_rd[15:0] + + runstate + runstate - - ram_din[7:0] - ram_din[7:0] + + clk + clk - - ram_addra[15:0] - ram_addra[15:0] + + holdstate + holdstate - - ram_addrb[15:0] - ram_addrb[15:0] + + libr + libr - - pe_ram_do[7:0] - pe_ram_do[7:0] + + sram + sram - + + sram + sram + + + libr + libr + + + sram + sram + + + etrec + etrec + + + etsnd + etsnd + + etcmd etcmd - - cm_rdy - cm_rdy + + appreq + appreq - + + appack + appack + + stinit2 stinit2 - + + etsnd + etsnd + + + port_out_data[7:0] + port_out_data[7:0] + + + port_out_data[7:0] + port_out_data[7:0] + + + port_out_data[7:0] + port_out_data[7:0] + + + port_out_data[7:0] + port_out_data[7:0] + + + port_out_data[7:0] + port_out_data[7:0] + + + port_out_data[7:0] + port_out_data[7:0] + + + port_in_data[7:0] + port_in_data[7:0] + + + port_in_wr_en + port_in_wr_en + + + port_in_empty + port_in_empty + + + port_out_data_available + port_out_data_available + + stinit2 stinit2 - + + etsnd + etsnd + + + port_out_data[7:0] + port_out_data[7:0] + + + stinit2 + stinit2 + + + port_out_data[7:0] + port_out_data[7:0] + + + port_out_rd_en + port_out_rd_en + + + datareceived[0:3] + datareceived[0:3] + + + etrec + etrec + + ds_rdy ds_rdy - - ram_address_rd[15:0] - ram_address_rd[15:0] - - - ram_data[7:0] - ram_data[7:0] - - - fifo_wr_i - fifo_wr_i - - - count - count - - - count - count - - - fifo_din_i[7:0] - fifo_din_i[7:0] - - - fifo_wr_i - fifo_wr_i - - - ram_address_i[15:0] - ram_address_i[15:0] - - - ram_data[7:0] - ram_data[7:0] - - - port_in_data[7:0] - port_in_data[7:0] - - - pe_ram_addra[15:0] - pe_ram_addra[15:0] - - - pe_ram_din[7:0] - pe_ram_din[7:0] - - - pe_ram_din[7:0] - pe_ram_din[7:0] - - - tosend[7:0] - tosend[7:0] - - - clkm - clkm - - - port_out_data[7:0] - port_out_data[7:0] - - - etrec - etrec - - - empty_signal - empty_signal - - - pop_state - pop_state - - + etcmd etcmd - - switch_port_in_wr_en - switch_port_in_wr_en - - - switch_port_in_data[7:0] - switch_port_in_data[7:0] - - - ram_data_in[7:0] - ram_data_in[7:0] - - - ram_data_out[7:0] - ram_data_out[7:0] - - - ram_address[15:0] - ram_address[15:0] - - - switch_port_out_data[7:0] - switch_port_out_data[7:0] - - - ram_address[15:0] - ram_address[15:0] - - - data_to_send[7:0] - data_to_send[7:0] - - - packet_length[7:0] - packet_length[7:0] - - - runstate - runstate - - - ex1_state_mach - ex1_state_mach - - - fifo_empty - fifo_empty - - - fifo_data_out[7:0] - fifo_data_out[7:0] - - - label - ex2_state_mach - ex2_state_mach - ex2_state_mach - - - switch_port_out_data[7:0] - switch_port_out_data[7:0] - - - switch_port_out_rd_en - switch_port_out_rd_en - - - ram_wr - ram_wr - - - ram_data_out[7:0] - ram_data_out[7:0] - - - packet_length[7:0] - packet_length[7:0] - - - runstate - runstate - - - ex1_state_mach - ex1_state_mach - - - ex2_state_mach - ex2_state_mach - - - switch_port_out_data[7:0] - switch_port_out_data[7:0] - - - switch_port_out_rd_en - switch_port_out_rd_en - - - ram_data_out[7:0] - ram_data_out[7:0] - - - ram_data_in[7:0] - ram_data_in[7:0] - - - ram_wr - ram_wr - - - ram_address[15:0] - ram_address[15:0] - - - dest_address[15:0] - dest_address[15:0] - - - packet_length[7:0] - packet_length[7:0] - - - port_out_data_available - port_out_data_available - - - etrec - etrec - - - etsnd - etsnd - - - rd_en_signal - rd_en_signal - - - rd_ready - rd_ready - - - empty - empty - - - fifo_counter[5:0] - fifo_counter[5:0] - - - fwft_fsm_state - fwft_fsm_state - - - rd_en - rd_en - - - wr_en - wr_en - - - initialized - initialized - Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/PE.vhd =================================================================== --- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/PE.vhd (revision 45) +++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/PE.vhd (revision 64) @@ -66,4 +66,12 @@ ); END COMPONENT; +COMPONENT Hold_FSM is + Port ( Hold_Req : in STD_LOGIC; + Ram_busy : in STD_LOGIC; + Clk : in STD_LOGIC; + Reset : in STD_LOGIC; + Ramsel : out STD_LOGIC; + Hold_Ack : out STD_LOGIC); +end COMPONENT Hold_FSM; --données du programme PE --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); @@ -76,5 +84,6 @@ signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); signal sram : typ_dpram; - + signal MyGroup:mpi_group; + signal MyWin : mpi_win; signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0); signal dpid,dpid_i : natural range 0 to 15:=DestId; @@ -84,6 +93,8 @@ signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO signal Lib_Init : std_logic; -- l'initialisation est terminée + signal Hold_Ack : std_logic; --signaux pour la gestion de la MAE - type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate, putdata,getdata,WinCompleted,finalize,st_timeout); + type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinStart, putdata,getdata,WinCompleted,finalize,st_timeout); + type typ_Hld is (Ht_Lock,Core_Lock,Ht_free); signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées signal count,count_i : natural range 0 to 15:=0; @@ -91,4 +102,5 @@ signal RunState : typ_mae; + signal Hld_state :typ_hld; signal Ram_busy :std_logic:='0'; begin @@ -147,29 +159,13 @@ Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié Lib_init<=Core_Pushout(4); -- Initialized --- pe_hold_req<=Core_hold_req; ---Core_hold_ack<=pe_hold_ack; - - hold:process (Core_Hold_Req,clk,reset) - begin - if rising_edge(clk) then - if reset='1' then - Core_Hold_Ack<='0'; - else - if Core_Hold_Req='1' then - - ramsel<=not(ram_busy); - Core_Hold_Ack<=not(ram_busy); --si la mémoire est occupé, forcé une libération - Pe_hold_ack<=not(ram_busy); - else - Core_Hold_Ack<='0'; - ramsel<='0'; - Pe_hold_ack<='0'; - - end if; - end if; - end if; - end process hold; ---======================================================================= - + +Hold1: Hold_fsm port map ( +clk=>clk, +reset =>reset, +Ram_Busy=>Libr.membusy, +Hold_Ack=>Hold_Ack, +Hold_req =>Core_Hold_Req, +RamSel => RamSel); +Core_Hold_Ack<=Hold_Ack; @@ -214,5 +210,5 @@ Libr.InitOk<=Core_pushout(4); Libr.Hold_Req<=Core_Hold_req; - Libr.Hold_Ack<=Pe_Hold_Ack; + Libr.Hold_Ack<=Hold_Ack; Libr.RamSel<=RamSel; sram.data_out<=PE_ram_do; @@ -226,7 +222,8 @@ Libr.InitOk<=Core_pushout(4); Libr.Hold_Req<=Core_Hold_req; - Libr.Hold_Ack<=Pe_Hold_Ack; + Libr.Hold_Ack<=Hold_Ack; Libr.RamSel<=RamSel; sram.data_out<=PE_ram_do; + case RunState is when start => @@ -236,4 +233,5 @@ end if; Ram_busy<='0'; + Libr.MemBusy<='0'; PE_Instr_En<='0'; iack:='0'; @@ -264,5 +262,5 @@ dcount<=dcount+1; - if dcount=200 then + if dcount=100 then bfill:=bfill+1; @@ -284,5 +282,5 @@ end if; when nextfill => --prépare le prochain bloc mémoire qui sera rempli - adresse:=200*bfill; + adresse:=200*bfill+1; dcount<=0; ct:=0; @@ -291,5 +289,5 @@ when InitApp => --code pour Init - dlen:=251; + dlen:=139; if ct=0 then -- synthesis translate_off @@ -305,5 +303,5 @@ adresse_rd:=to_integer(unsigned(sram.addr_rd)); PE_ram_din<=sram.data_in; - + Ram_busy<=Libr.membusy; --if Libr.InitOk='1' then if ct=0 then @@ -328,6 +326,8 @@ pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank); adresse_rd:=to_integer(unsigned(sram.addr_rd)); + Ram_busy<=Libr.membusy; + if ct=0 then - RunState<=PutData; + RunState<=WinStart; -- synthesis translate_off write (l,string'("Dlen; ;Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now))); @@ -337,6 +337,31 @@ end if; - + when Wincreate => + + when WinStart => + if ct=0 then + -- synthesis translate_off + write (l,string'("Dlen; ;WStart1 " & integer'image(Dlen) & "; ; started ; " & time'image(now))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; + pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin); + adresse:=to_integer(unsigned(sram.addr_wr)); + adresse_rd:=to_integer(unsigned(sram.addr_rd)); + --PE_Instr_EN<=Libr.instr_en; + PE_ram_din<=sram.data_in; + Ram_busy<=Libr.membusy; + dcount<=ct; + + if ct=0 then + RunState<=PutData; + -- synthesis translate_off + write (l,string'("Dlen; ;WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now))); + report l.all; + writeline (f, l) ; + -- synthesis translate_on + end if; @@ -365,5 +390,5 @@ SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN)); - DestAdr:=X"2000"; + DestAdr:=X"0340"; pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); @@ -372,4 +397,5 @@ PE_Instr_EN<=Libr.instr_en; PE_ram_din<=sram.data_in; + Ram_busy<=Libr.membusy; dcount<=ct; @@ -396,5 +422,5 @@ SrcAdr:=X"0120"; - DestAdr:=X"4000"; + DestAdr:=X"1400"; if unsigned(MyRank) /= 2 then pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win); @@ -406,4 +432,5 @@ PE_Instr_EN<=Libr.instr_en; PE_ram_din<=sram.data_in; + Ram_busy<=Libr.membusy; dcount<=ct; @@ -431,4 +458,5 @@ adresse:=to_integer(unsigned(sram.addr_wr)); adresse_rd:=to_integer(unsigned(sram.addr_rd)); + Ram_busy<=Libr.membusy; if ct=0 then RunState<=finalize; @@ -518,5 +546,9 @@ PE_Ram_enb<=sram.enb; - + when WinStart => + + PE_Ram_we<=sram.we; + PE_Ram_ena<=sram.ena; + PE_Ram_enb<=sram.enb; --positionnement du mot de longueur des données Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/iseconfig/MPI_CORE_COMPONENTS.projectmgr =================================================================== --- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/iseconfig/MPI_CORE_COMPONENTS.projectmgr (revision 45) +++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/iseconfig/MPI_CORE_COMPONENTS.projectmgr (revision 64) @@ -14,5 +14,5 @@ /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/Inst_RAM_v - RAM_v - Behavioral/MPI_PKG/mpi_pkg /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/MPI_PKG - /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/CORE_SCHEDULER - MPI_CORE_SCHEDULER - Behavioral /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo1 - FIFO_64_FWFT - Behavioral /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/Instruction_Fifo2 - FIFO_64_FWFT - Behavioral @@ -184,15 +184,188 @@ /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/MPI_PKG /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/PE1 - PE - Behavioral - /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/PE2 - PE - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/PE3 - PE - Behavioral /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/CORE_SCHEDULER - MPI_CORE_SCHEDULER - Behavioral /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral - /Unassigned User Library Modules + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT14_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT15_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT1_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT2_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT2_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT3_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT3_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT4_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT5_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT6_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT7_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT8_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT9_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx16_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx16_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler10_10 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler11_11 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler12_12 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler13_13 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler14_14 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler15_15 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler2_2 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler3_3 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler4_4 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler5_5 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler6_6 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler7_7 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler9_9 - Scheduler - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar10_10 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar11_11 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar12_12 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar13_13 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar14_14 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar15_15 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar16_16 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar2_2 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar3_3 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar4_4 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar5_5 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar6_6 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar7_7 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar8_8 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar9_9 - Crossbar - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/conversions + /SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT11_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT12_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT13_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT14_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT14_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT15_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT15_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT16_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT16_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT1_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT2_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT2_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT3_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT3_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT4_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT5_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT5_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT6_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT6_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT7_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT7_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT8_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/PORT9_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler10_10 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler11_11 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler12_12 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler13_13 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler14_14 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler15_15 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler16_16 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler2_2 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler3_3 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler4_4 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler5_5 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler6_6 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler7_7 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler8_8 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Scheduler9_9 - Scheduler - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar10_10 - Crossbar - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar11_11 - Crossbar - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar12_12 - Crossbar - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar13_13 - Crossbar - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar14_14 - Crossbar - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar15_15 - Crossbar - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar16_16 - Crossbar - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar2_2 - Crossbar - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar3_3 - Crossbar - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar4_4 - Crossbar - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar5_5 - Crossbar - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar6_6 - Crossbar - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar7_7 - Crossbar - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar8_8 - Crossbar - Behavioral + /Unassigned User Library Modules/SWITCH_GENERIQUE - Behavioral/Switch_Crossbar9_9 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT14_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT15_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT1_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT2_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT2_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT3_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT3_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT4_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT5_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT6_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT7_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT8_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORT9_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORTx16_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORTx16_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORTx4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORTx8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/PORTx9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler10_10 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler11_11 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler12_12 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler13_13 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler14_14 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler15_15 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler2_2 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler3_3 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler4_4 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler5_5 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler6_6 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler7_7 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Scheduler9_9 - Scheduler - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar10_10 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar11_11 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar12_12 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar13_13 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar14_14 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar15_15 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar16_16 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar2_2 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar3_3 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar4_4 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar5_5 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar6_6 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar7_7 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar8_8 - Crossbar - Behavioral + /Unassigned User Library Modules/test_xbar_8x8 - behavior/uut - SWITCH_GEN - Behavioral/Switch_Crossbar9_9 - Crossbar - Behavioral + /testbench - behavior C:|Core MPI|CORE_MPI|sim_fifo.vhd MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd) - 9 - 0 - 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002f3000000020000000000000000000000000000000064ffffffff000000810000000000000002000002f30000000100000000000000000000000100000000 + 21 + 0 + 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000035b000000020000000000000000000000000000000064ffffffff0000008100000000000000020000035b0000000100000000000000000000000100000000 false MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd) @@ -202,18 +375,19 @@ 1 Configure Target Device - Implement Design + Implement Design/Map + Implement Design/Place & Route Implement Design/Place & Route/Back-annotate Pin Locations Implement Design/Place & Route/Generate IBIS Model Implement Design/Place & Route/Generate Post-Place & Route Static Timing - Implement Design/Translate - - - Synthesize - XST - - 0 - 0 - 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f70000000100000000 - false - Synthesize - XST + User Constraints + + + View RTL Schematic + + 0 + 0 + 000000ff0000000000000001000000010000000000000000000000000000000000000000000000013c000000010000000100000000000000000000000064ffffffff0000008100000000000000010000013c0000000100000000 + false + View RTL Schematic @@ -222,25 +396,24 @@ - C:\Core MPI\SWITCH_GENERIC_16_16\Crossbar.vhd - - 26 - 0 - 000000ff00000000000000010000000000000000010000000000000000000000000000000000000307000000040101000100000000000000000000000064ffffffff000000810000000000000004000001f90000000100000000000000440000000100000000000000660000000100000000000000640000000100000000 - false - C:\Core MPI\SWITCH_GENERIC_16_16\Crossbar.vhd + C:\Core MPI\CORE_MPI\MPI_RMA.vhd + + 0 + 0 + 000000ff00000000000000010000000000000002010000000000000000000000000000000000000307000000040101000100000000000000000000000064ffffffff000000810000000000000004000001f90000000100000000000000440000000100000000000000660000000100000000000000640000000100000000 + false + C:\Core MPI\CORE_MPI\MPI_RMA.vhd 1 - work - - - C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER4_4.VHD - - 7 + + + C:\Core MPI\CORE_MPI\MultiMPITest.vhd + + 48 0 000000ff00000000000000010000000000000000010000000000000000000000000000000000000103000000010001000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000 false - C:\Core MPI\SWITCH_GENERIC_16_16\SCHEDULER4_4.VHD + C:\Core MPI\CORE_MPI\MultiMPITest.vhd @@ -254,5 +427,5 @@ 0 0 - 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000228000000010000000100000000000000000000000064ffffffff000000810000000000000001000002280000000100000000 false @@ -269,4 +442,5 @@ /CORE_MPI - Behavioral C:|Documents and Settings|Administrateur.SWEET-918992B6D|Bureau|MPSOC_MEMOIRE_FIN|MPI_CORE_COMPONENTS|CORE_MPI.vhd/Instruction_Fifo2 - FIFO_64_FWFT - Behavioral /FIFO - TOP_HIER C:|Core MPI|CORE_MPI|FIfo_mem.vhd + /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural /MPICORETEST - behavior C:|Core MPI|CORE_MPI|MPICORETEST.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural/CORE_SCHEDULER - MPI_CORE_SCHEDULER - Behavioral @@ -282,8 +456,9 @@ /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/PE1 - PE - Behavioral /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/PE2 - PE - Behavioral + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural + /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/uut - MPI_NOC - structural /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/uut - MPI_NOC - structural/hardmpi - CORE_MPI - Structural /MultiMPITest - behavior C:|Core MPI|CORE_MPI|MultiMPITest.vhd/uut - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral - /Unassigned User Library Modules /Unassigned User Library Modules/Scheduler12_12 - Behavioral /Unassigned User Library Modules/Scheduler13_13 - Behavioral @@ -296,16 +471,77 @@ /Unassigned User Library Modules/Scheduler6_6 - Behavioral /Unassigned User Library Modules/Scheduler7_7 - Behavioral + /Unassigned User Library Modules/conversions /Unassigned User Library Modules/test_xbar_16x16 - behavior /Unassigned User Library Modules/test_xbar_8x8 - behavior + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/PE1 - PE - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/PE2 - PE - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/PE3 - PE - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/hardmpi - CORE_MPI - Structural + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT11_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT12_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT13_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT14_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT15_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT1_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT1_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT2_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT2_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT3_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT3_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT4_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT5_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT6_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT7_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT8_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORT9_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx16_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx16_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx4_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx8_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/PORTx9_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler10_10 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler11_11 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler12_12 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler13_13 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler14_14 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler15_15 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler16_16 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler2_2 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler3_3 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler4_4 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler5_5 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler6_6 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler7_7 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler8_8 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Scheduler9_9 - Scheduler - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar10_10 - Crossbar - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar11_11 - Crossbar - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar12_12 - Crossbar - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar13_13 - Crossbar - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar14_14 - Crossbar - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar15_15 - Crossbar - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar16_16 - Crossbar - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar2_2 - Crossbar - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar3_3 - Crossbar - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar4_4 - Crossbar - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar5_5 - Crossbar - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar6_6 - Crossbar - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar7_7 - Crossbar - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar8_8 - Crossbar - Behavioral + /mpi_test - behavior C:|Core MPI|CORE_MPI|mpi_test.vhd/uut - MultiMPITest - behavior/Xbar - MPI_NOC - structural/switch_gen1 - SWITCH_GEN - Behavioral/Switch_Crossbar9_9 - Crossbar - Behavioral + /test_DMA - behavior C:|Core MPI|CORE_MPI|test_DMA.vhd /testbench - behavior C:|Core MPI|CORE_MPI|sim_fifo.vhd/uut - FIFO_256_FWFT - Behavioral - MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd) - - 6 + mpi_test - behavior (C:/Core MPI/CORE_MPI/mpi_test.vhd) + + 7 0 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002c1000000020000000000000000000000000000000064ffffffff000000810000000000000002000002c10000000100000000000000000000000100000000 false - MultiMPITest - behavior (C:/Core MPI/CORE_MPI/MultiMPITest.vhd) + mpi_test - behavior (C:/Core MPI/CORE_MPI/mpi_test.vhd) @@ -319,5 +555,5 @@ 0 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000132000000010000000100000000000000000000000064ffffffff000000810000000000000001000001320000000100000000 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000151000000010000000100000000000000000000000064ffffffff000000810000000000000001000001510000000100000000 false @@ -332,10 +568,10 @@ 0 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000132000000010000000100000000000000000000000064ffffffff000000810000000000000001000001320000000100000000 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000151000000010000000100000000000000000000000064ffffffff000000810000000000000001000001510000000100000000 false ISim Simulator 000000ff0000000000000002000000d1000000d101000000050100000002 - Implementation + Behavioral Simulation @@ -408,11 +644,11 @@ - stimuli45 - behavioral (C:/Core MPI/SWITCH_GENERIC_16_16/stimuli1.vhd) - - 0 - 0 - 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000189000000020000000000000000000000000000000064ffffffff000000810000000000000002000001890000000100000000000000000000000100000000 - false - stimuli45 - behavioral (C:/Core MPI/SWITCH_GENERIC_16_16/stimuli1.vhd) + Unassigned User Library Modules + + 1 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000213000000020000000100000000000000000000000064ffffffff000000810000000000000002000002130000000100000000000000000000000100000000 + true + Unassigned User Library Modules @@ -421,15 +657,55 @@ - Compile HDL Simulation Libraries - - 0 - 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000115000000010000000100000000000000000000000064ffffffff000000810000000000000001000001150000000100000000 - false - Compile HDL Simulation Libraries + Design Utilities + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000228000000010000000100000000000000000000000064ffffffff000000810000000000000001000002280000000100000000 + false + Design Utilities 1 + + + Simulate Post-Translate Model + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000228000000010000000100000000000000000000000064ffffffff000000810000000000000001000002280000000100000000 + false + Simulate Post-Translate Model + + + + 2 + + + Unassigned User Library Modules + + 2 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000275000000020000000000000000000000000000000064ffffffff000000810000000000000002000002750000000100000000000000000000000100000000 + false + Unassigned User Library Modules + + + + 1 + Design Utilities + + + + + 0 + 0 + 000000ff0000000000000001000000010000000000000000000000000000000000000000000000010c000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010c0000000100000000 + false + + + + + 1 ISim Simulator @@ -439,5 +715,55 @@ 0 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000115000000010000000100000000000000000000000064ffffffff000000810000000000000001000001150000000100000000 + 000000ff0000000000000001000000010000000000000000000000000000000000000000000000010c000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010c0000000100000000 + false + + + + + 2 + + + Unassigned User Library Modules + + 2 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000275000000020000000000000000000000000000000064ffffffff000000810000000000000002000002750000000100000000000000000000000100000000 + false + Unassigned User Library Modules + + + + 1 + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000228000000010000000100000000000000000000000064ffffffff000000810000000000000001000002280000000100000000 + false + + + + + 1 + + + Simulate Post-Place & Route Model + + 0 + 0 + 000000ff0000000000000001000000010000000000000000000000000000000000000000000000010c000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010c0000000100000000 + false + Simulate Post-Place & Route Model + + + + 1 + + + 0 + 0 + false Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/iseconfig/MultiMPITest.xreport =================================================================== --- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/iseconfig/MultiMPITest.xreport (revision 45) +++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/iseconfig/MultiMPITest.xreport (revision 64) @@ -2,15 +2,15 @@
- 2012-12-20T15:14:17 - SWITCH_GEN - 2012-12-19T17:00:46 + 2013-04-22T08:02:07 + DMA_ARBITER + 2013-04-10T14:49:35 C:/Core MPI/CORE_MPI/iseconfig/MultiMPITest.xreport C:/Core MPI/CORE_MPI\ - 2012-12-09T12:18:32 + 2013-03-19T19:44:50 false
- + @@ -22,15 +22,17 @@ - - @@ -45,5 +47,5 @@ @@ -61,5 +63,5 @@ -