Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SWITCH_GEN.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SWITCH_GEN.vhd	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SWITCH_GEN.vhd	(revision 65)
@@ -32,43 +32,13 @@
 entity SWITCH_GEN is 
  --type portio is array(positive range) of std_logic_vector (7 downto 0);    
- generic(number_of_ports : positive := 4);
+ generic(number_of_ports : positive := 8);
      port(
 	        -- ports d'entree
            Port_in : in typ_portIO(1 to number_of_ports) ;
---			  Port1_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---           Port2_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---           Port3_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---           Port4_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---			  Port5_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---           Port6_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---           Port7_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---           Port8_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---			  Port9_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---           Port10_in : in  STD_LOGIC_VECTOR (7 downto 0);
---           Port11_in : in  STD_LOGIC_VECTOR (7 downto 0);
---           Port12_in : in  STD_LOGIC_VECTOR (7 downto 0);
---			  Port13_in : in  STD_LOGIC_VECTOR (7 downto 0);
---           Port14_in : in  STD_LOGIC_VECTOR (7 downto 0);
---           Port15_in : in  STD_LOGIC_VECTOR (7 downto 0);
---           Port16_in : in  STD_LOGIC_VECTOR (7 downto 0);
+
 			 
 			  -- port de sortie
 			  Port_out : out  typ_portIO(1 to number_of_ports);
---			  Port1_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port2_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port3_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port4_out : out  STD_LOGIC_VECTOR (7 downto 0);
---			  Port5_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port6_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port7_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port8_out : out  STD_LOGIC_VECTOR (7 downto 0);
---			  Port9_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port10_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port11_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port12_out : out  STD_LOGIC_VECTOR (7 downto 0);
---			  Port13_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port14_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port15_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port16_out : out  STD_LOGIC_VECTOR (7 downto 0);
+
 			  -- signaux de controle
 			  data_in_en : in std_logic_vector(number_of_ports downto 1);
@@ -87,5 +57,5 @@
 
 COMPONENT INPUT_PORT_MODULE
-  generic(number_of_ports : positive := 4;
+  generic(number_of_ports : positive := 8;
 			Port_num: natural);
     Port ( data_in : in  STD_LOGIC_VECTOR (7 downto 0);
@@ -125,6 +95,7 @@
 			);
     Port ( 
-	        --Port_in : in Typ_PortIO(1 to number_of_crossbar_ports);
-			  Port1_in : in  STD_LOGIC_VECTOR (7 downto 0);
+	        clk : in  STD_LOGIC;
+			reset : in  STD_LOGIC;
+			Port1_in : in  STD_LOGIC_VECTOR (7 downto 0);
            Port2_in : in  STD_LOGIC_VECTOR (7 downto 0);
            Port3_in : in  STD_LOGIC_VECTOR (7 downto 0);
@@ -213,14 +184,4 @@
 
 --declaration des signaux de connection entre les modules du switch
---type port_connection_type is array(16 downto 1) of std_logic_vector(7 downto 1);
---signal crossbar_port_in_connetion : port_connection_type;
---signal crossbar_port_out_connetion :port_connection_type;
---signal request_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
---signal grant_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
---signal priority_rotation_connection : std_logic_vector(number_of_ports downto 1);
---signal fifo_out_full_connection : std_logic_vector(1 to number_of_ports);
---signal crossbar_in_pulse(_connection : std_logic_vector(number_of_ports downto 1);
---signal crossbar_out_pulse_connection : std_logic_vector(number_of_ports downto 1);
---variable i,j : integer;
 
 Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
@@ -231,74 +192,14 @@
 signal crossbar_in_port :  Typ_PortIO(1 to number_of_ports);
 
---signal crossbar_in_port1 : std_logic_vector(7 downto 0);
---signal crossbar_in_port2 : std_logic_vector(7 downto 0);
---signal crossbar_in_port3 : std_logic_vector(7 downto 0);
---signal crossbar_in_port4 : std_logic_vector(7 downto 0);
---signal crossbar_in_port5 : std_logic_vector(7 downto 0);
---signal crossbar_in_port6 : std_logic_vector(7 downto 0);
---signal crossbar_in_port7 : std_logic_vector(7 downto 0);
---signal crossbar_in_port8 : std_logic_vector(7 downto 0);
---signal crossbar_in_port9 : std_logic_vector(7 downto 0);
---signal crossbar_in_port10 : std_logic_vector(7 downto 0);
---signal crossbar_in_port11 : std_logic_vector(7 downto 0);
---signal crossbar_in_port12 : std_logic_vector(7 downto 0);
---signal crossbar_in_port13 : std_logic_vector(7 downto 0);
---signal crossbar_in_port14 : std_logic_vector(7 downto 0);
---signal crossbar_in_port15 : std_logic_vector(7 downto 0);
---signal crossbar_in_port16 : std_logic_vector(7 downto 0);
+
 
 signal crossbar_out_port  :  Typ_PortIO(1 to number_of_ports);
---signal crossbar_out_port1 : std_logic_vector(7 downto 0);
---signal crossbar_out_port2 : std_logic_vector(7 downto 0);
---signal crossbar_out_port3 : std_logic_vector(7 downto 0);
---signal crossbar_out_port4 : std_logic_vector(7 downto 0);
---signal crossbar_out_port5 : std_logic_vector(7 downto 0);
---signal crossbar_out_port6 : std_logic_vector(7 downto 0);
---signal crossbar_out_port7 : std_logic_vector(7 downto 0);
---signal crossbar_out_port8 : std_logic_vector(7 downto 0);
---signal crossbar_out_port9 : std_logic_vector(7 downto 0);
---signal crossbar_out_port10 : std_logic_vector(7 downto 0);
---signal crossbar_out_port11 : std_logic_vector(7 downto 0);
---signal crossbar_out_port12 : std_logic_vector(7 downto 0);
---signal crossbar_out_port13 : std_logic_vector(7 downto 0);
---signal crossbar_out_port14 : std_logic_vector(7 downto 0);
---signal crossbar_out_port15 : std_logic_vector(7 downto 0);
---signal crossbar_out_port16 : std_logic_vector(7 downto 0);
+
 
 signal crossbar_in_pulse  : std_logic_vector(number_of_ports downto 1);
---signal crossbar_in_pulse1 : std_logic;
---signal crossbar_in_pulse2 : std_logic;
---signal crossbar_in_pulse3 : std_logic;
---signal crossbar_in_pulse4 : std_logic;
---signal crossbar_in_pulse5 : std_logic;
---signal crossbar_in_pulse6 : std_logic;
---signal crossbar_in_pulse7 : std_logic;
---signal crossbar_in_pulse8 : std_logic;
---signal crossbar_in_pulse9 : std_logic;
---signal crossbar_in_pulse10 : std_logic;
---signal crossbar_in_pulse11 : std_logic;
---signal crossbar_in_pulse12 : std_logic;
---signal crossbar_in_pulse13 : std_logic;
---signal crossbar_in_pulse14 : std_logic;
---signal crossbar_in_pulse15 : std_logic;
---signal crossbar_in_pulse16 : std_logic;
+
 
 signal crossbar_out_pulse  : std_logic_vector(number_of_ports downto 1);
---signal crossbar_out_pulse1 : std_logic;
---signal crossbar_out_pulse2 : std_logic;
---signal crossbar_out_pulse3 : std_logic;
---signal crossbar_out_pulse4 : std_logic;
---signal crossbar_out_pulse5 : std_logic;
---signal crossbar_out_pulse6 : std_logic;
---signal crossbar_out_pulse7 : std_logic;
---signal crossbar_out_pulse8 : std_logic;
---signal crossbar_out_pulse9 : std_logic;
---signal crossbar_out_pulse10 : std_logic;
---signal crossbar_out_pulse11 : std_logic;
---signal crossbar_out_pulse12 : std_logic;
---signal crossbar_out_pulse13 : std_logic;
---signal crossbar_out_pulse14 : std_logic;
---signal crossbar_out_pulse15 : std_logic;
---signal crossbar_out_pulse16 : std_logic;
+
 
 
@@ -428,5 +329,5 @@
 --j=number_of_ports*(i-1);
 PORTx4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
-GENERIC MAP(number_of_ports =>4,Port_num=>i)
+GENERIC MAP(number_of_ports =>number_of_ports,Port_num=>i)
 PORT MAP(
    data_in => Port_in(i),
@@ -6281,4 +6182,6 @@
 GENERIC MAP(number_of_crossbar_ports =>2)
   PORT MAP(
+		reset => reset,
+     clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6327,5 +6230,7 @@
 GENERIC MAP(number_of_crossbar_ports =>3)
   PORT MAP(
-   Port1_in => crossbar_in_port(1),
+		reset => reset,
+     clk => clk, 
+	Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
    Port3_in => crossbar_in_port(3),
@@ -6375,4 +6280,6 @@
 GENERIC MAP(number_of_crossbar_ports =>4)
   PORT MAP(
+		reset => reset,
+     clk => clk,  
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6425,4 +6332,6 @@
 GENERIC MAP(number_of_crossbar_ports =>5)
   PORT MAP(
+		reset => reset,
+     clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6477,4 +6386,7 @@
 GENERIC MAP(number_of_crossbar_ports =>6)
   PORT MAP(
+  
+ 		reset => reset,
+     clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6531,4 +6443,6 @@
 GENERIC MAP(number_of_crossbar_ports =>7)
   PORT MAP(
+		reset => reset,
+     clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6587,4 +6501,6 @@
 GENERIC MAP(number_of_crossbar_ports =>8)
   PORT MAP(
+    reset => reset,
+   clk =>clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6645,4 +6561,6 @@
 GENERIC MAP(number_of_crossbar_ports =>9)
   PORT MAP(
+		reset => reset,
+     clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6705,4 +6623,6 @@
 GENERIC MAP(number_of_crossbar_ports =>10)
   PORT MAP(
+	reset => reset,
+   clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6767,4 +6687,6 @@
 GENERIC MAP(number_of_crossbar_ports =>11)
   PORT MAP(
+	reset => reset,
+   clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6831,4 +6753,6 @@
 GENERIC MAP(number_of_crossbar_ports =>12)
   PORT MAP(
+	reset => reset,
+   clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6897,4 +6821,6 @@
 GENERIC MAP(number_of_crossbar_ports =>13)
   PORT MAP(
+	reset => reset,
+   clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6965,4 +6891,6 @@
 GENERIC MAP(number_of_crossbar_ports =>14)
   PORT MAP(
+	reset => reset,
+   clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -7035,4 +6963,6 @@
 GENERIC MAP(number_of_crossbar_ports =>15)
   PORT MAP(
+	reset => reset,
+   clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -7107,4 +7037,6 @@
 GENERIC MAP(number_of_crossbar_ports =>16)
   PORT MAP(
+	reset => reset,
+   clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
