Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Arbiter.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Arbiter.vhd	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Arbiter.vhd	(revision 65)
@@ -46,9 +46,11 @@
 signal grant_signal : STD_LOGIC; 
 --signal not_fifo_full : STD_LOGIC;
-signal Mask : STD_LOGIC;
+signal Mask : STD_LOGIC:='0';
+signal RNW : std_logic:='0';
 begin
 --Grant<=grant_signal; -- Grant n'a pas été déclarée InOut
 Mask <= P AND (not Fifo_full);
-process(Mask, Request, North, West)-- genere de la logique purement combinatoire
+RNW<= Request And North And West;
+process(Mask, RNW, North, West)-- genere de la logique purement combinatoire
 begin
 if Mask ='0' then --cellule inactive
@@ -57,7 +59,7 @@
 East <= '1';
    else
-	Grant <= Request And North And West;
-	South <= (North) And (Not (Request And North And West));	
-	East  <= (West)  And (Not (Request And North And West));
+	Grant <= RNW;
+	South <= (North) And (Not (RNW));	
+	East  <= (West)  And (Not (RNW));
 end if;
 end process;
Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/CoreTypes.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/CoreTypes.vhd	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/CoreTypes.vhd	(revision 65)
@@ -24,4 +24,5 @@
 CONSTANT CORE_WWAIT_ADR : natural := CORE_BASE_ADR+566;
 CONSTANT CORE_Rank2port_BASE :NATURAL:=32;
+CONSTANT CORE_RANK_ADR : NATURAL:=CORE_BASE_ADR+CORE_Rank2Port_Base;
 CONSTANT WIN0_ADR :natural :=4;
 CONSTANT WIN1_ADR :natural :=14;
Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Crossbar.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Crossbar.vhd	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Crossbar.vhd	(revision 65)
@@ -1,5 +1,5 @@
 ----------------------------------------------------------------------------------
 -- Company: 
--- Engineer: KIEGAING EMMANUEL
+-- Engineer: KIEGAING EMMANUEL / GAMOM NGOUNOU
 -- 
 -- Create Date:    11:48:18 06/19/2011 
@@ -16,5 +16,6 @@
 -- a été retiré les signaux inutilisées comme fp, port_source, etc...
 -- Revision 0.01 - File Created
--- Additional Comments: 
+-- Revision 0.02 Ajout des signaux clk et reset
+-- Additional Comments: pour la gestion du pipeline
 --
 ----------------------------------------------------------------------------------
@@ -33,7 +34,9 @@
     generic
 	      (
-			  number_of_crossbar_ports: positive := 4
+			  number_of_crossbar_ports: positive := 8
 			);
-    Port ( Port1_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
+    Port ( clk : in  STD_LOGIC;
+			  reset : in  STD_LOGIC; --pour gérer le pipeline
+			  Port1_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
            Port2_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
            Port3_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
@@ -115,13 +118,19 @@
 			  number_of_ports : positive := 4
 			);
-    Port ( Control : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
+    Port ( clk,reset : in std_logic;
+			  Control : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
            Data_In : in  STD_LOGIC_VECTOR (number_of_ports downto 1);
            Data_out : out  STD_LOGIC_VECTOR (number_of_ports downto 1));
 	END COMPONENT;	
-	
+signal ctrl_buf:	STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1):=(others=>'0');
+--signal ctrl_chg:std_logic:='0';
 begin
 -- La matrice interconnectee
 -- le circuit genere depend du parametre generique nombre de ports
-
+--ctrl_chg<=all_zeros(ctrl_buf xor ctrl); --sur chaque changement du mot de contrôle, mettre à jour ce registre
+--ctrl_proc:process(ctrl)
+--	begin
+	ctrl_buf<=ctrl;
+--	end process;
 --======================crossbar 2 ports=======================
 
@@ -133,6 +142,8 @@
       GENERIC MAP(number_of_ports => 2)
       PORT MAP(
-
-      Control => Ctrl,
+		reset => reset,
+		clk =>clk,
+      
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -146,6 +157,8 @@
       GENERIC MAP(number_of_ports => 2)
       PORT MAP(
-
-      Control => Ctrl,
+		reset => reset,
+		clk =>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -159,6 +172,8 @@
       GENERIC MAP(number_of_ports => 2)
       PORT MAP(
-
-      Control => Ctrl,
+		reset => reset,
+		clk =>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -172,6 +187,8 @@
       GENERIC MAP(number_of_ports => 2)
       PORT MAP(
-
-      Control => Ctrl,
+		reset => reset,
+		clk =>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -186,5 +203,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+		reset => reset,
+		clk =>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -199,5 +219,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -212,5 +234,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -225,5 +249,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -237,6 +263,8 @@
       GENERIC MAP(number_of_ports => 2)
       PORT MAP(
-
-      Control => Ctrl,
+		reset => reset,
+		clk =>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
@@ -258,5 +286,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+		reset => reset,
+		clk =>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -272,6 +303,8 @@
       GENERIC MAP(number_of_ports => 3)
       PORT MAP(
-
-      Control => Ctrl,
+		reset => reset,
+		clk =>clk,
+      
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -288,5 +321,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -302,6 +337,8 @@
       GENERIC MAP(number_of_ports => 3)
       PORT MAP(
-
-      Control => Ctrl,
+		reset => reset,
+		clk =>clk,
+      
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -318,5 +355,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -333,5 +372,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -348,5 +389,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+		reset => reset,
+		clk =>clk,
+      
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -362,6 +406,8 @@
       GENERIC MAP(number_of_ports => 3)
       PORT MAP(
-
-      Control => Ctrl,
+		reset => reset,
+		clk =>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -377,6 +423,8 @@
       GENERIC MAP(number_of_ports => 3)
       PORT MAP(
-
-      Control => Ctrl,
+		reset => reset,
+		clk =>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
@@ -400,5 +448,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -417,5 +467,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -434,5 +486,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -451,5 +505,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -468,5 +524,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -485,5 +543,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -502,5 +562,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -519,5 +581,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -536,5 +600,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
@@ -560,5 +626,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -579,5 +647,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -598,5 +668,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -617,5 +689,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -636,5 +710,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -655,5 +731,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -674,5 +752,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -693,5 +773,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -712,5 +794,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
@@ -738,5 +822,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -759,5 +845,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -780,5 +868,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -801,5 +891,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -822,5 +914,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -843,5 +937,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -864,5 +960,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -885,5 +983,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -906,5 +1006,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
@@ -934,5 +1036,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -957,5 +1061,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -980,5 +1086,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -1003,5 +1111,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -1026,5 +1136,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -1049,5 +1161,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -1072,5 +1186,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -1095,5 +1211,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -1118,5 +1236,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
@@ -1147,6 +1267,8 @@
       GENERIC MAP(number_of_ports => 8)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+    
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -1172,6 +1294,8 @@
       GENERIC MAP(number_of_ports => 8)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+      
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -1197,6 +1321,8 @@
       GENERIC MAP(number_of_ports => 8)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+      
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -1222,6 +1348,8 @@
       GENERIC MAP(number_of_ports => 8)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -1247,6 +1375,8 @@
       GENERIC MAP(number_of_ports => 8)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -1272,6 +1402,8 @@
       GENERIC MAP(number_of_ports => 8)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -1297,6 +1429,8 @@
       GENERIC MAP(number_of_ports => 8)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -1322,6 +1456,8 @@
       GENERIC MAP(number_of_ports => 8)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+ 
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -1347,6 +1483,8 @@
       GENERIC MAP(number_of_ports => 8)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
@@ -1379,6 +1517,8 @@
       GENERIC MAP(number_of_ports => 9)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -1406,6 +1546,8 @@
       GENERIC MAP(number_of_ports => 9)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+    
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -1433,6 +1575,8 @@
       GENERIC MAP(number_of_ports => 9)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -1460,6 +1604,8 @@
       GENERIC MAP(number_of_ports => 9)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+ 
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -1487,6 +1633,8 @@
       GENERIC MAP(number_of_ports => 9)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+ 
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -1514,6 +1662,8 @@
       GENERIC MAP(number_of_ports => 9)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+ 
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -1541,6 +1691,8 @@
       GENERIC MAP(number_of_ports => 9)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+ 
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -1568,6 +1720,8 @@
       GENERIC MAP(number_of_ports => 9)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+     
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -1595,6 +1749,8 @@
       GENERIC MAP(number_of_ports => 9)
       PORT MAP(
-
-      Control => Ctrl,
+		clk =>clk,
+		reset =>reset,
+   
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
@@ -1630,5 +1786,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -1659,5 +1817,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -1688,5 +1848,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -1717,5 +1879,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -1746,5 +1910,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -1775,5 +1941,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -1804,5 +1972,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -1833,5 +2003,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -1862,5 +2034,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
@@ -1898,5 +2072,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -1929,5 +2105,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -1960,5 +2138,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -1991,5 +2171,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ clk=>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -2022,5 +2205,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -2053,5 +2238,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -2084,5 +2272,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -2115,5 +2306,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -2146,5 +2340,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
@@ -2184,5 +2381,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -2217,5 +2417,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -2250,5 +2453,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -2283,5 +2489,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -2316,5 +2525,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -2349,5 +2561,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -2382,5 +2597,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -2415,5 +2633,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -2448,5 +2669,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
@@ -2488,5 +2712,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -2523,5 +2749,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -2558,5 +2787,8 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -2593,5 +2825,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -2628,5 +2862,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -2663,5 +2899,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -2698,5 +2936,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -2733,5 +2973,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -2768,5 +3010,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
@@ -2810,5 +3054,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -2847,5 +3093,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -2884,5 +3132,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -2921,5 +3171,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -2958,5 +3210,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -2995,5 +3249,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -3032,5 +3288,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -3069,5 +3327,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -3106,5 +3366,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
@@ -3150,5 +3412,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -3189,5 +3453,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -3228,5 +3494,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -3267,5 +3535,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -3306,5 +3576,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -3345,5 +3617,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -3384,5 +3658,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -3423,5 +3699,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -3462,5 +3740,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
@@ -3508,5 +3788,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(0),
        Data_In(2) => Port2_in(0),
@@ -3549,5 +3831,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(1),
        Data_In(2) => Port2_in(1),
@@ -3590,5 +3874,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(2),
        Data_In(2) => Port2_in(2),
@@ -3631,5 +3917,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(3),
        Data_In(2) => Port2_in(3),
@@ -3672,5 +3960,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(4),
        Data_In(2) => Port2_in(4),
@@ -3713,5 +4003,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(5),
        Data_In(2) => Port2_in(5),
@@ -3754,5 +4046,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(6),
        Data_In(2) => Port2_in(6),
@@ -3795,5 +4089,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_in(7),
        Data_In(2) => Port2_in(7),
@@ -3836,5 +4132,7 @@
       PORT MAP(
 
-      Control => Ctrl,
+      reset => reset,
+ 	 	 clk=>clk,
+ 	 	 Control => Ctrl_buf,
        Data_In(1) => Port1_pulse_in,
        Data_In(2) => Port2_pulse_in,
Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Crossbit.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Crossbit.vhd	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Crossbit.vhd	(revision 65)
@@ -1,5 +1,5 @@
 ----------------------------------------------------------------------------------
 -- Company: 
--- Engineer: Kiegaing Emmanuel GEL EN 5
+-- Engineer: Kiegaing Emmanuel /GAMOM Roland Christian
 -- 
 -- Create Date:    01:47 05/06/2011
@@ -14,5 +14,6 @@
 -- Dependencies: 
 --
--- Revision: 
+-- Revision: 11-01-2013
+-- AJOUT DU CLK pour créer un pipeline dans l'architecture.
 -- Revision 0.01 - File Created
 -- Additional Comments: 
@@ -34,12 +35,14 @@
 			  number_of_ports: positive := 4
 			);
-    Port ( Control : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
+    Port ( clk,reset : in std_logic;
+				Control : in  STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
 			  Data_In : in  STD_LOGIC_VECTOR (number_of_ports downto 1);
            Data_out : out  STD_LOGIC_VECTOR (number_of_ports downto 1)
+			  
 			  );
 end Crossbit;
 
 architecture Behavioral of Crossbit is
-
+signal dout :STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'0');
 begin
 -- element de commutation utilisee dans la matrice interconnecte
@@ -49,6 +52,6 @@
 crossbit2x2 : if number_of_ports = 2 generate
 
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(3)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(4)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(3)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(4)));
 end generate crossbit2x2;
 
@@ -59,7 +62,7 @@
 
  
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(4)) OR (Data_in(3) And Control(7)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(5)) OR (Data_in(3) And Control(8)));
-  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(9)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(4)) OR (Data_in(3) And Control(7)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(5)) OR (Data_in(3) And Control(8)));
+  Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(9)));
 end generate crossbit3x3;
 
@@ -69,8 +72,8 @@
 crossbit4x4 : if number_of_ports = 4 generate
 
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(5)) OR (Data_in(3) And Control(9)) OR (Data_in(4) And Control(13)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(10)) OR (Data_in(4) And Control(14)));
-  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(11)) OR (Data_in(4) And Control(15)));
-  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(12)) OR (Data_in(4) And Control(16)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(5)) OR (Data_in(3) And Control(9)) OR (Data_in(4) And Control(13)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(10)) OR (Data_in(4) And Control(14)));
+  Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(11)) OR (Data_in(4) And Control(15)));
+  Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(12)) OR (Data_in(4) And Control(16)));
 end generate crossbit4x4;
 
@@ -80,9 +83,9 @@
 crossbit5x5 : if number_of_ports = 5 generate
 
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(11)) OR (Data_in(4) And Control(16)) OR (Data_in(5) And Control(21)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(12)) OR (Data_in(4) And Control(17)) OR (Data_in(5) And Control(22)));
-  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(13)) OR (Data_in(4) And Control(18)) OR (Data_in(5) And Control(23)));
-  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(14)) OR (Data_in(4) And Control(19)) OR (Data_in(5) And Control(24)));
-  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(20)) OR (Data_in(5) And Control(25)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(6)) OR (Data_in(3) And Control(11)) OR (Data_in(4) And Control(16)) OR (Data_in(5) And Control(21)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(12)) OR (Data_in(4) And Control(17)) OR (Data_in(5) And Control(22)));
+  Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(13)) OR (Data_in(4) And Control(18)) OR (Data_in(5) And Control(23)));
+  Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(14)) OR (Data_in(4) And Control(19)) OR (Data_in(5) And Control(24)));
+  Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(20)) OR (Data_in(5) And Control(25)));
 end generate crossbit5x5;
 
@@ -92,10 +95,10 @@
 crossbit6x6 : if number_of_ports = 6 generate
 
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(13)) OR (Data_in(4) And Control(19)) OR (Data_in(5) And Control(25)) OR (Data_in(6) And Control(31)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(14)) OR (Data_in(4) And Control(20)) OR (Data_in(5) And Control(26)) OR (Data_in(6) And Control(32)));
-  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(21)) OR (Data_in(5) And Control(27)) OR (Data_in(6) And Control(33)));
-  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(16)) OR (Data_in(4) And Control(22)) OR (Data_in(5) And Control(28)) OR (Data_in(6) And Control(34)));
-  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(23)) OR (Data_in(5) And Control(29)) OR (Data_in(6) And Control(35)));
-  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(24)) OR (Data_in(5) And Control(30)) OR (Data_in(6) And Control(36)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(7)) OR (Data_in(3) And Control(13)) OR (Data_in(4) And Control(19)) OR (Data_in(5) And Control(25)) OR (Data_in(6) And Control(31)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(14)) OR (Data_in(4) And Control(20)) OR (Data_in(5) And Control(26)) OR (Data_in(6) And Control(32)));
+  Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(21)) OR (Data_in(5) And Control(27)) OR (Data_in(6) And Control(33)));
+  Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(16)) OR (Data_in(4) And Control(22)) OR (Data_in(5) And Control(28)) OR (Data_in(6) And Control(34)));
+  Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(23)) OR (Data_in(5) And Control(29)) OR (Data_in(6) And Control(35)));
+  Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(24)) OR (Data_in(5) And Control(30)) OR (Data_in(6) And Control(36)));
 end generate crossbit6x6;
 
@@ -105,11 +108,11 @@
 crossbit7x7 : if number_of_ports = 7 generate
 
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(22)) OR (Data_in(5) And Control(29)) OR (Data_in(6) And Control(36)) OR (Data_in(7) And Control(43)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(16)) OR (Data_in(4) And Control(23)) OR (Data_in(5) And Control(30)) OR (Data_in(6) And Control(37)) OR (Data_in(7) And Control(44)));
-  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(24)) OR (Data_in(5) And Control(31)) OR (Data_in(6) And Control(38)) OR (Data_in(7) And Control(45)));
-  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(25)) OR (Data_in(5) And Control(32)) OR (Data_in(6) And Control(39)) OR (Data_in(7) And Control(46)));
-  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(26)) OR (Data_in(5) And Control(33)) OR (Data_in(6) And Control(40)) OR (Data_in(7) And Control(47)));
-  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(27)) OR (Data_in(5) And Control(34)) OR (Data_in(6) And Control(41)) OR (Data_in(7) And Control(48)));
-  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(35)) OR (Data_in(6) And Control(42)) OR (Data_in(7) And Control(49)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(8)) OR (Data_in(3) And Control(15)) OR (Data_in(4) And Control(22)) OR (Data_in(5) And Control(29)) OR (Data_in(6) And Control(36)) OR (Data_in(7) And Control(43)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(16)) OR (Data_in(4) And Control(23)) OR (Data_in(5) And Control(30)) OR (Data_in(6) And Control(37)) OR (Data_in(7) And Control(44)));
+  Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(24)) OR (Data_in(5) And Control(31)) OR (Data_in(6) And Control(38)) OR (Data_in(7) And Control(45)));
+  Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(25)) OR (Data_in(5) And Control(32)) OR (Data_in(6) And Control(39)) OR (Data_in(7) And Control(46)));
+  Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(26)) OR (Data_in(5) And Control(33)) OR (Data_in(6) And Control(40)) OR (Data_in(7) And Control(47)));
+  Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(27)) OR (Data_in(5) And Control(34)) OR (Data_in(6) And Control(41)) OR (Data_in(7) And Control(48)));
+  Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(35)) OR (Data_in(6) And Control(42)) OR (Data_in(7) And Control(49)));
 end generate crossbit7x7;
 
@@ -119,12 +122,12 @@
 crossbit8x8 : if number_of_ports = 8 generate
 
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(25)) OR (Data_in(5) And Control(33)) OR (Data_in(6) And Control(41)) OR (Data_in(7) And Control(49)) OR (Data_in(8) And Control(57)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(26)) OR (Data_in(5) And Control(34)) OR (Data_in(6) And Control(42)) OR (Data_in(7) And Control(50)) OR (Data_in(8) And Control(58)));
-  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(27)) OR (Data_in(5) And Control(35)) OR (Data_in(6) And Control(43)) OR (Data_in(7) And Control(51)) OR (Data_in(8) And Control(59)));
-  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(36)) OR (Data_in(6) And Control(44)) OR (Data_in(7) And Control(52)) OR (Data_in(8) And Control(60)));
-  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(29)) OR (Data_in(5) And Control(37)) OR (Data_in(6) And Control(45)) OR (Data_in(7) And Control(53)) OR (Data_in(8) And Control(61)));
-  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(30)) OR (Data_in(5) And Control(38)) OR (Data_in(6) And Control(46)) OR (Data_in(7) And Control(54)) OR (Data_in(8) And Control(62)));
-  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(39)) OR (Data_in(6) And Control(47)) OR (Data_in(7) And Control(55)) OR (Data_in(8) And Control(63)));
-  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(40)) OR (Data_in(6) And Control(48)) OR (Data_in(7) And Control(56)) OR (Data_in(8) And Control(64)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(9)) OR (Data_in(3) And Control(17)) OR (Data_in(4) And Control(25)) OR (Data_in(5) And Control(33)) OR (Data_in(6) And Control(41)) OR (Data_in(7) And Control(49)) OR (Data_in(8) And Control(57)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(18)) OR (Data_in(4) And Control(26)) OR (Data_in(5) And Control(34)) OR (Data_in(6) And Control(42)) OR (Data_in(7) And Control(50)) OR (Data_in(8) And Control(58)));
+  Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(27)) OR (Data_in(5) And Control(35)) OR (Data_in(6) And Control(43)) OR (Data_in(7) And Control(51)) OR (Data_in(8) And Control(59)));
+  Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(36)) OR (Data_in(6) And Control(44)) OR (Data_in(7) And Control(52)) OR (Data_in(8) And Control(60)));
+  Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(29)) OR (Data_in(5) And Control(37)) OR (Data_in(6) And Control(45)) OR (Data_in(7) And Control(53)) OR (Data_in(8) And Control(61)));
+  Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(30)) OR (Data_in(5) And Control(38)) OR (Data_in(6) And Control(46)) OR (Data_in(7) And Control(54)) OR (Data_in(8) And Control(62)));
+  Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(39)) OR (Data_in(6) And Control(47)) OR (Data_in(7) And Control(55)) OR (Data_in(8) And Control(63)));
+  Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(40)) OR (Data_in(6) And Control(48)) OR (Data_in(7) And Control(56)) OR (Data_in(8) And Control(64)));
 end generate crossbit8x8;
 
@@ -134,13 +137,13 @@
 crossbit9x9 : if number_of_ports = 9 generate
 
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(37)) OR (Data_in(6) And Control(46)) OR (Data_in(7) And Control(55)) OR (Data_in(8) And Control(64)) OR (Data_in(9) And Control(73)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(29)) OR (Data_in(5) And Control(38)) OR (Data_in(6) And Control(47)) OR (Data_in(7) And Control(56)) OR (Data_in(8) And Control(65)) OR (Data_in(9) And Control(74)));
-  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(30)) OR (Data_in(5) And Control(39)) OR (Data_in(6) And Control(48)) OR (Data_in(7) And Control(57)) OR (Data_in(8) And Control(66)) OR (Data_in(9) And Control(75)));
-  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(40)) OR (Data_in(6) And Control(49)) OR (Data_in(7) And Control(58)) OR (Data_in(8) And Control(67)) OR (Data_in(9) And Control(76)));
-  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(41)) OR (Data_in(6) And Control(50)) OR (Data_in(7) And Control(59)) OR (Data_in(8) And Control(68)) OR (Data_in(9) And Control(77)));
-  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(33)) OR (Data_in(5) And Control(42)) OR (Data_in(6) And Control(51)) OR (Data_in(7) And Control(60)) OR (Data_in(8) And Control(69)) OR (Data_in(9) And Control(78)));
-  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(43)) OR (Data_in(6) And Control(52)) OR (Data_in(7) And Control(61)) OR (Data_in(8) And Control(70)) OR (Data_in(9) And Control(79)));
-  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(44)) OR (Data_in(6) And Control(53)) OR (Data_in(7) And Control(62)) OR (Data_in(8) And Control(71)) OR (Data_in(9) And Control(80)));
-  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(54)) OR (Data_in(7) And Control(63)) OR (Data_in(8) And Control(72)) OR (Data_in(9) And Control(81)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(10)) OR (Data_in(3) And Control(19)) OR (Data_in(4) And Control(28)) OR (Data_in(5) And Control(37)) OR (Data_in(6) And Control(46)) OR (Data_in(7) And Control(55)) OR (Data_in(8) And Control(64)) OR (Data_in(9) And Control(73)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(20)) OR (Data_in(4) And Control(29)) OR (Data_in(5) And Control(38)) OR (Data_in(6) And Control(47)) OR (Data_in(7) And Control(56)) OR (Data_in(8) And Control(65)) OR (Data_in(9) And Control(74)));
+  Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(30)) OR (Data_in(5) And Control(39)) OR (Data_in(6) And Control(48)) OR (Data_in(7) And Control(57)) OR (Data_in(8) And Control(66)) OR (Data_in(9) And Control(75)));
+  Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(40)) OR (Data_in(6) And Control(49)) OR (Data_in(7) And Control(58)) OR (Data_in(8) And Control(67)) OR (Data_in(9) And Control(76)));
+  Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(41)) OR (Data_in(6) And Control(50)) OR (Data_in(7) And Control(59)) OR (Data_in(8) And Control(68)) OR (Data_in(9) And Control(77)));
+  Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(33)) OR (Data_in(5) And Control(42)) OR (Data_in(6) And Control(51)) OR (Data_in(7) And Control(60)) OR (Data_in(8) And Control(69)) OR (Data_in(9) And Control(78)));
+  Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(43)) OR (Data_in(6) And Control(52)) OR (Data_in(7) And Control(61)) OR (Data_in(8) And Control(70)) OR (Data_in(9) And Control(79)));
+  Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(44)) OR (Data_in(6) And Control(53)) OR (Data_in(7) And Control(62)) OR (Data_in(8) And Control(71)) OR (Data_in(9) And Control(80)));
+  Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(54)) OR (Data_in(7) And Control(63)) OR (Data_in(8) And Control(72)) OR (Data_in(9) And Control(81)));
 end generate crossbit9x9;
 
@@ -150,14 +153,14 @@
 crossbit10x10 : if number_of_ports = 10 generate
 
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(41)) OR (Data_in(6) And Control(51)) OR (Data_in(7) And Control(61)) OR (Data_in(8) And Control(71)) OR (Data_in(9) And Control(81)) OR (Data_in(10) And Control(91)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(42)) OR (Data_in(6) And Control(52)) OR (Data_in(7) And Control(62)) OR (Data_in(8) And Control(72)) OR (Data_in(9) And Control(82)) OR (Data_in(10) And Control(92)));
-  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(33)) OR (Data_in(5) And Control(43)) OR (Data_in(6) And Control(53)) OR (Data_in(7) And Control(63)) OR (Data_in(8) And Control(73)) OR (Data_in(9) And Control(83)) OR (Data_in(10) And Control(93)));
-  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(44)) OR (Data_in(6) And Control(54)) OR (Data_in(7) And Control(64)) OR (Data_in(8) And Control(74)) OR (Data_in(9) And Control(84)) OR (Data_in(10) And Control(94)));
-  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(55)) OR (Data_in(7) And Control(65)) OR (Data_in(8) And Control(75)) OR (Data_in(9) And Control(85)) OR (Data_in(10) And Control(95)));
-  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(46)) OR (Data_in(6) And Control(56)) OR (Data_in(7) And Control(66)) OR (Data_in(8) And Control(76)) OR (Data_in(9) And Control(86)) OR (Data_in(10) And Control(96)));
-  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(47)) OR (Data_in(6) And Control(57)) OR (Data_in(7) And Control(67)) OR (Data_in(8) And Control(77)) OR (Data_in(9) And Control(87)) OR (Data_in(10) And Control(97)));
-  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(48)) OR (Data_in(6) And Control(58)) OR (Data_in(7) And Control(68)) OR (Data_in(8) And Control(78)) OR (Data_in(9) And Control(88)) OR (Data_in(10) And Control(98)));
-  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(59)) OR (Data_in(7) And Control(69)) OR (Data_in(8) And Control(79)) OR (Data_in(9) And Control(89)) OR (Data_in(10) And Control(99)));
-  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(60)) OR (Data_in(7) And Control(70)) OR (Data_in(8) And Control(80)) OR (Data_in(9) And Control(90)) OR (Data_in(10) And Control(100)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(11)) OR (Data_in(3) And Control(21)) OR (Data_in(4) And Control(31)) OR (Data_in(5) And Control(41)) OR (Data_in(6) And Control(51)) OR (Data_in(7) And Control(61)) OR (Data_in(8) And Control(71)) OR (Data_in(9) And Control(81)) OR (Data_in(10) And Control(91)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(22)) OR (Data_in(4) And Control(32)) OR (Data_in(5) And Control(42)) OR (Data_in(6) And Control(52)) OR (Data_in(7) And Control(62)) OR (Data_in(8) And Control(72)) OR (Data_in(9) And Control(82)) OR (Data_in(10) And Control(92)));
+  Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(33)) OR (Data_in(5) And Control(43)) OR (Data_in(6) And Control(53)) OR (Data_in(7) And Control(63)) OR (Data_in(8) And Control(73)) OR (Data_in(9) And Control(83)) OR (Data_in(10) And Control(93)));
+  Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(44)) OR (Data_in(6) And Control(54)) OR (Data_in(7) And Control(64)) OR (Data_in(8) And Control(74)) OR (Data_in(9) And Control(84)) OR (Data_in(10) And Control(94)));
+  Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(55)) OR (Data_in(7) And Control(65)) OR (Data_in(8) And Control(75)) OR (Data_in(9) And Control(85)) OR (Data_in(10) And Control(95)));
+  Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(46)) OR (Data_in(6) And Control(56)) OR (Data_in(7) And Control(66)) OR (Data_in(8) And Control(76)) OR (Data_in(9) And Control(86)) OR (Data_in(10) And Control(96)));
+  Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(47)) OR (Data_in(6) And Control(57)) OR (Data_in(7) And Control(67)) OR (Data_in(8) And Control(77)) OR (Data_in(9) And Control(87)) OR (Data_in(10) And Control(97)));
+  Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(48)) OR (Data_in(6) And Control(58)) OR (Data_in(7) And Control(68)) OR (Data_in(8) And Control(78)) OR (Data_in(9) And Control(88)) OR (Data_in(10) And Control(98)));
+  Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(59)) OR (Data_in(7) And Control(69)) OR (Data_in(8) And Control(79)) OR (Data_in(9) And Control(89)) OR (Data_in(10) And Control(99)));
+  Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(60)) OR (Data_in(7) And Control(70)) OR (Data_in(8) And Control(80)) OR (Data_in(9) And Control(90)) OR (Data_in(10) And Control(100)));
 end generate crossbit10x10;
 
@@ -167,15 +170,15 @@
 crossbit11x11 : if number_of_ports = 11 generate
 
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(56)) OR (Data_in(7) And Control(67)) OR (Data_in(8) And Control(78)) OR (Data_in(9) And Control(89)) OR (Data_in(10) And Control(100)) OR (Data_in(11) And Control(111)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(46)) OR (Data_in(6) And Control(57)) OR (Data_in(7) And Control(68)) OR (Data_in(8) And Control(79)) OR (Data_in(9) And Control(90)) OR (Data_in(10) And Control(101)) OR (Data_in(11) And Control(112)));
-  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(47)) OR (Data_in(6) And Control(58)) OR (Data_in(7) And Control(69)) OR (Data_in(8) And Control(80)) OR (Data_in(9) And Control(91)) OR (Data_in(10) And Control(102)) OR (Data_in(11) And Control(113)));
-  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(48)) OR (Data_in(6) And Control(59)) OR (Data_in(7) And Control(70)) OR (Data_in(8) And Control(81)) OR (Data_in(9) And Control(92)) OR (Data_in(10) And Control(103)) OR (Data_in(11) And Control(114)));
-  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(60)) OR (Data_in(7) And Control(71)) OR (Data_in(8) And Control(82)) OR (Data_in(9) And Control(93)) OR (Data_in(10) And Control(104)) OR (Data_in(11) And Control(115)));
-  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(61)) OR (Data_in(7) And Control(72)) OR (Data_in(8) And Control(83)) OR (Data_in(9) And Control(94)) OR (Data_in(10) And Control(105)) OR (Data_in(11) And Control(116)));
-  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(51)) OR (Data_in(6) And Control(62)) OR (Data_in(7) And Control(73)) OR (Data_in(8) And Control(84)) OR (Data_in(9) And Control(95)) OR (Data_in(10) And Control(106)) OR (Data_in(11) And Control(117)));
-  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(52)) OR (Data_in(6) And Control(63)) OR (Data_in(7) And Control(74)) OR (Data_in(8) And Control(85)) OR (Data_in(9) And Control(96)) OR (Data_in(10) And Control(107)) OR (Data_in(11) And Control(118)));
-  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(64)) OR (Data_in(7) And Control(75)) OR (Data_in(8) And Control(86)) OR (Data_in(9) And Control(97)) OR (Data_in(10) And Control(108)) OR (Data_in(11) And Control(119)));
-  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(65)) OR (Data_in(7) And Control(76)) OR (Data_in(8) And Control(87)) OR (Data_in(9) And Control(98)) OR (Data_in(10) And Control(109)) OR (Data_in(11) And Control(120)));
-  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(77)) OR (Data_in(8) And Control(88)) OR (Data_in(9) And Control(99)) OR (Data_in(10) And Control(110)) OR (Data_in(11) And Control(121)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(12)) OR (Data_in(3) And Control(23)) OR (Data_in(4) And Control(34)) OR (Data_in(5) And Control(45)) OR (Data_in(6) And Control(56)) OR (Data_in(7) And Control(67)) OR (Data_in(8) And Control(78)) OR (Data_in(9) And Control(89)) OR (Data_in(10) And Control(100)) OR (Data_in(11) And Control(111)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(24)) OR (Data_in(4) And Control(35)) OR (Data_in(5) And Control(46)) OR (Data_in(6) And Control(57)) OR (Data_in(7) And Control(68)) OR (Data_in(8) And Control(79)) OR (Data_in(9) And Control(90)) OR (Data_in(10) And Control(101)) OR (Data_in(11) And Control(112)));
+  Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(36)) OR (Data_in(5) And Control(47)) OR (Data_in(6) And Control(58)) OR (Data_in(7) And Control(69)) OR (Data_in(8) And Control(80)) OR (Data_in(9) And Control(91)) OR (Data_in(10) And Control(102)) OR (Data_in(11) And Control(113)));
+  Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(48)) OR (Data_in(6) And Control(59)) OR (Data_in(7) And Control(70)) OR (Data_in(8) And Control(81)) OR (Data_in(9) And Control(92)) OR (Data_in(10) And Control(103)) OR (Data_in(11) And Control(114)));
+  Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(60)) OR (Data_in(7) And Control(71)) OR (Data_in(8) And Control(82)) OR (Data_in(9) And Control(93)) OR (Data_in(10) And Control(104)) OR (Data_in(11) And Control(115)));
+  Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(61)) OR (Data_in(7) And Control(72)) OR (Data_in(8) And Control(83)) OR (Data_in(9) And Control(94)) OR (Data_in(10) And Control(105)) OR (Data_in(11) And Control(116)));
+  Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(51)) OR (Data_in(6) And Control(62)) OR (Data_in(7) And Control(73)) OR (Data_in(8) And Control(84)) OR (Data_in(9) And Control(95)) OR (Data_in(10) And Control(106)) OR (Data_in(11) And Control(117)));
+  Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(52)) OR (Data_in(6) And Control(63)) OR (Data_in(7) And Control(74)) OR (Data_in(8) And Control(85)) OR (Data_in(9) And Control(96)) OR (Data_in(10) And Control(107)) OR (Data_in(11) And Control(118)));
+  Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(64)) OR (Data_in(7) And Control(75)) OR (Data_in(8) And Control(86)) OR (Data_in(9) And Control(97)) OR (Data_in(10) And Control(108)) OR (Data_in(11) And Control(119)));
+  Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(65)) OR (Data_in(7) And Control(76)) OR (Data_in(8) And Control(87)) OR (Data_in(9) And Control(98)) OR (Data_in(10) And Control(109)) OR (Data_in(11) And Control(120)));
+  Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(77)) OR (Data_in(8) And Control(88)) OR (Data_in(9) And Control(99)) OR (Data_in(10) And Control(110)) OR (Data_in(11) And Control(121)));
 end generate crossbit11x11;
 
@@ -185,16 +188,16 @@
 crossbit12x12 : if number_of_ports = 12 generate
 
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(61)) OR (Data_in(7) And Control(73)) OR (Data_in(8) And Control(85)) OR (Data_in(9) And Control(97)) OR (Data_in(10) And Control(109)) OR (Data_in(11) And Control(121)) OR (Data_in(12) And Control(133)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(62)) OR (Data_in(7) And Control(74)) OR (Data_in(8) And Control(86)) OR (Data_in(9) And Control(98)) OR (Data_in(10) And Control(110)) OR (Data_in(11) And Control(122)) OR (Data_in(12) And Control(134)));
-  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(51)) OR (Data_in(6) And Control(63)) OR (Data_in(7) And Control(75)) OR (Data_in(8) And Control(87)) OR (Data_in(9) And Control(99)) OR (Data_in(10) And Control(111)) OR (Data_in(11) And Control(123)) OR (Data_in(12) And Control(135)));
-  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(52)) OR (Data_in(6) And Control(64)) OR (Data_in(7) And Control(76)) OR (Data_in(8) And Control(88)) OR (Data_in(9) And Control(100)) OR (Data_in(10) And Control(112)) OR (Data_in(11) And Control(124)) OR (Data_in(12) And Control(136)));
-  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(65)) OR (Data_in(7) And Control(77)) OR (Data_in(8) And Control(89)) OR (Data_in(9) And Control(101)) OR (Data_in(10) And Control(113)) OR (Data_in(11) And Control(125)) OR (Data_in(12) And Control(137)));
-  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(78)) OR (Data_in(8) And Control(90)) OR (Data_in(9) And Control(102)) OR (Data_in(10) And Control(114)) OR (Data_in(11) And Control(126)) OR (Data_in(12) And Control(138)));
-  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(67)) OR (Data_in(7) And Control(79)) OR (Data_in(8) And Control(91)) OR (Data_in(9) And Control(103)) OR (Data_in(10) And Control(115)) OR (Data_in(11) And Control(127)) OR (Data_in(12) And Control(139)));
-  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(56)) OR (Data_in(6) And Control(68)) OR (Data_in(7) And Control(80)) OR (Data_in(8) And Control(92)) OR (Data_in(9) And Control(104)) OR (Data_in(10) And Control(116)) OR (Data_in(11) And Control(128)) OR (Data_in(12) And Control(140)));
-  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(69)) OR (Data_in(7) And Control(81)) OR (Data_in(8) And Control(93)) OR (Data_in(9) And Control(105)) OR (Data_in(10) And Control(117)) OR (Data_in(11) And Control(129)) OR (Data_in(12) And Control(141)));
-  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(70)) OR (Data_in(7) And Control(82)) OR (Data_in(8) And Control(94)) OR (Data_in(9) And Control(106)) OR (Data_in(10) And Control(118)) OR (Data_in(11) And Control(130)) OR (Data_in(12) And Control(142)));
-  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(83)) OR (Data_in(8) And Control(95)) OR (Data_in(9) And Control(107)) OR (Data_in(10) And Control(119)) OR (Data_in(11) And Control(131)) OR (Data_in(12) And Control(143)));
-  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(84)) OR (Data_in(8) And Control(96)) OR (Data_in(9) And Control(108)) OR (Data_in(10) And Control(120)) OR (Data_in(11) And Control(132)) OR (Data_in(12) And Control(144)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(13)) OR (Data_in(3) And Control(25)) OR (Data_in(4) And Control(37)) OR (Data_in(5) And Control(49)) OR (Data_in(6) And Control(61)) OR (Data_in(7) And Control(73)) OR (Data_in(8) And Control(85)) OR (Data_in(9) And Control(97)) OR (Data_in(10) And Control(109)) OR (Data_in(11) And Control(121)) OR (Data_in(12) And Control(133)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(26)) OR (Data_in(4) And Control(38)) OR (Data_in(5) And Control(50)) OR (Data_in(6) And Control(62)) OR (Data_in(7) And Control(74)) OR (Data_in(8) And Control(86)) OR (Data_in(9) And Control(98)) OR (Data_in(10) And Control(110)) OR (Data_in(11) And Control(122)) OR (Data_in(12) And Control(134)));
+  Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(39)) OR (Data_in(5) And Control(51)) OR (Data_in(6) And Control(63)) OR (Data_in(7) And Control(75)) OR (Data_in(8) And Control(87)) OR (Data_in(9) And Control(99)) OR (Data_in(10) And Control(111)) OR (Data_in(11) And Control(123)) OR (Data_in(12) And Control(135)));
+  Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(52)) OR (Data_in(6) And Control(64)) OR (Data_in(7) And Control(76)) OR (Data_in(8) And Control(88)) OR (Data_in(9) And Control(100)) OR (Data_in(10) And Control(112)) OR (Data_in(11) And Control(124)) OR (Data_in(12) And Control(136)));
+  Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(65)) OR (Data_in(7) And Control(77)) OR (Data_in(8) And Control(89)) OR (Data_in(9) And Control(101)) OR (Data_in(10) And Control(113)) OR (Data_in(11) And Control(125)) OR (Data_in(12) And Control(137)));
+  Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(78)) OR (Data_in(8) And Control(90)) OR (Data_in(9) And Control(102)) OR (Data_in(10) And Control(114)) OR (Data_in(11) And Control(126)) OR (Data_in(12) And Control(138)));
+  Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(67)) OR (Data_in(7) And Control(79)) OR (Data_in(8) And Control(91)) OR (Data_in(9) And Control(103)) OR (Data_in(10) And Control(115)) OR (Data_in(11) And Control(127)) OR (Data_in(12) And Control(139)));
+  Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(56)) OR (Data_in(6) And Control(68)) OR (Data_in(7) And Control(80)) OR (Data_in(8) And Control(92)) OR (Data_in(9) And Control(104)) OR (Data_in(10) And Control(116)) OR (Data_in(11) And Control(128)) OR (Data_in(12) And Control(140)));
+  Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(69)) OR (Data_in(7) And Control(81)) OR (Data_in(8) And Control(93)) OR (Data_in(9) And Control(105)) OR (Data_in(10) And Control(117)) OR (Data_in(11) And Control(129)) OR (Data_in(12) And Control(141)));
+  Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(70)) OR (Data_in(7) And Control(82)) OR (Data_in(8) And Control(94)) OR (Data_in(9) And Control(106)) OR (Data_in(10) And Control(118)) OR (Data_in(11) And Control(130)) OR (Data_in(12) And Control(142)));
+  Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(83)) OR (Data_in(8) And Control(95)) OR (Data_in(9) And Control(107)) OR (Data_in(10) And Control(119)) OR (Data_in(11) And Control(131)) OR (Data_in(12) And Control(143)));
+  Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(84)) OR (Data_in(8) And Control(96)) OR (Data_in(9) And Control(108)) OR (Data_in(10) And Control(120)) OR (Data_in(11) And Control(132)) OR (Data_in(12) And Control(144)));
 end generate crossbit12x12;
 
@@ -204,17 +207,17 @@
 crossbit13x13 : if number_of_ports = 13 generate
 
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(79)) OR (Data_in(8) And Control(92)) OR (Data_in(9) And Control(105)) OR (Data_in(10) And Control(118)) OR (Data_in(11) And Control(131)) OR (Data_in(12) And Control(144)) OR (Data_in(13) And Control(157)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(67)) OR (Data_in(7) And Control(80)) OR (Data_in(8) And Control(93)) OR (Data_in(9) And Control(106)) OR (Data_in(10) And Control(119)) OR (Data_in(11) And Control(132)) OR (Data_in(12) And Control(145)) OR (Data_in(13) And Control(158)));
-  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(68)) OR (Data_in(7) And Control(81)) OR (Data_in(8) And Control(94)) OR (Data_in(9) And Control(107)) OR (Data_in(10) And Control(120)) OR (Data_in(11) And Control(133)) OR (Data_in(12) And Control(146)) OR (Data_in(13) And Control(159)));
-  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(56)) OR (Data_in(6) And Control(69)) OR (Data_in(7) And Control(82)) OR (Data_in(8) And Control(95)) OR (Data_in(9) And Control(108)) OR (Data_in(10) And Control(121)) OR (Data_in(11) And Control(134)) OR (Data_in(12) And Control(147)) OR (Data_in(13) And Control(160)));
-  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(70)) OR (Data_in(7) And Control(83)) OR (Data_in(8) And Control(96)) OR (Data_in(9) And Control(109)) OR (Data_in(10) And Control(122)) OR (Data_in(11) And Control(135)) OR (Data_in(12) And Control(148)) OR (Data_in(13) And Control(161)));
-  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(84)) OR (Data_in(8) And Control(97)) OR (Data_in(9) And Control(110)) OR (Data_in(10) And Control(123)) OR (Data_in(11) And Control(136)) OR (Data_in(12) And Control(149)) OR (Data_in(13) And Control(162)));
-  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(85)) OR (Data_in(8) And Control(98)) OR (Data_in(9) And Control(111)) OR (Data_in(10) And Control(124)) OR (Data_in(11) And Control(137)) OR (Data_in(12) And Control(150)) OR (Data_in(13) And Control(163)));
-  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(73)) OR (Data_in(7) And Control(86)) OR (Data_in(8) And Control(99)) OR (Data_in(9) And Control(112)) OR (Data_in(10) And Control(125)) OR (Data_in(11) And Control(138)) OR (Data_in(12) And Control(151)) OR (Data_in(13) And Control(164)));
-  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(74)) OR (Data_in(7) And Control(87)) OR (Data_in(8) And Control(100)) OR (Data_in(9) And Control(113)) OR (Data_in(10) And Control(126)) OR (Data_in(11) And Control(139)) OR (Data_in(12) And Control(152)) OR (Data_in(13) And Control(165)));
-  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(75)) OR (Data_in(7) And Control(88)) OR (Data_in(8) And Control(101)) OR (Data_in(9) And Control(114)) OR (Data_in(10) And Control(127)) OR (Data_in(11) And Control(140)) OR (Data_in(12) And Control(153)) OR (Data_in(13) And Control(166)));
-  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(89)) OR (Data_in(8) And Control(102)) OR (Data_in(9) And Control(115)) OR (Data_in(10) And Control(128)) OR (Data_in(11) And Control(141)) OR (Data_in(12) And Control(154)) OR (Data_in(13) And Control(167)));
-  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(90)) OR (Data_in(8) And Control(103)) OR (Data_in(9) And Control(116)) OR (Data_in(10) And Control(129)) OR (Data_in(11) And Control(142)) OR (Data_in(12) And Control(155)) OR (Data_in(13) And Control(168)));
-  Data_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(104)) OR (Data_in(9) And Control(117)) OR (Data_in(10) And Control(130)) OR (Data_in(11) And Control(143)) OR (Data_in(12) And Control(156)) OR (Data_in(13) And Control(169)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(14)) OR (Data_in(3) And Control(27)) OR (Data_in(4) And Control(40)) OR (Data_in(5) And Control(53)) OR (Data_in(6) And Control(66)) OR (Data_in(7) And Control(79)) OR (Data_in(8) And Control(92)) OR (Data_in(9) And Control(105)) OR (Data_in(10) And Control(118)) OR (Data_in(11) And Control(131)) OR (Data_in(12) And Control(144)) OR (Data_in(13) And Control(157)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(28)) OR (Data_in(4) And Control(41)) OR (Data_in(5) And Control(54)) OR (Data_in(6) And Control(67)) OR (Data_in(7) And Control(80)) OR (Data_in(8) And Control(93)) OR (Data_in(9) And Control(106)) OR (Data_in(10) And Control(119)) OR (Data_in(11) And Control(132)) OR (Data_in(12) And Control(145)) OR (Data_in(13) And Control(158)));
+  Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(42)) OR (Data_in(5) And Control(55)) OR (Data_in(6) And Control(68)) OR (Data_in(7) And Control(81)) OR (Data_in(8) And Control(94)) OR (Data_in(9) And Control(107)) OR (Data_in(10) And Control(120)) OR (Data_in(11) And Control(133)) OR (Data_in(12) And Control(146)) OR (Data_in(13) And Control(159)));
+  Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(56)) OR (Data_in(6) And Control(69)) OR (Data_in(7) And Control(82)) OR (Data_in(8) And Control(95)) OR (Data_in(9) And Control(108)) OR (Data_in(10) And Control(121)) OR (Data_in(11) And Control(134)) OR (Data_in(12) And Control(147)) OR (Data_in(13) And Control(160)));
+  Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(70)) OR (Data_in(7) And Control(83)) OR (Data_in(8) And Control(96)) OR (Data_in(9) And Control(109)) OR (Data_in(10) And Control(122)) OR (Data_in(11) And Control(135)) OR (Data_in(12) And Control(148)) OR (Data_in(13) And Control(161)));
+  Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(84)) OR (Data_in(8) And Control(97)) OR (Data_in(9) And Control(110)) OR (Data_in(10) And Control(123)) OR (Data_in(11) And Control(136)) OR (Data_in(12) And Control(149)) OR (Data_in(13) And Control(162)));
+  Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(85)) OR (Data_in(8) And Control(98)) OR (Data_in(9) And Control(111)) OR (Data_in(10) And Control(124)) OR (Data_in(11) And Control(137)) OR (Data_in(12) And Control(150)) OR (Data_in(13) And Control(163)));
+  Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(73)) OR (Data_in(7) And Control(86)) OR (Data_in(8) And Control(99)) OR (Data_in(9) And Control(112)) OR (Data_in(10) And Control(125)) OR (Data_in(11) And Control(138)) OR (Data_in(12) And Control(151)) OR (Data_in(13) And Control(164)));
+  Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(74)) OR (Data_in(7) And Control(87)) OR (Data_in(8) And Control(100)) OR (Data_in(9) And Control(113)) OR (Data_in(10) And Control(126)) OR (Data_in(11) And Control(139)) OR (Data_in(12) And Control(152)) OR (Data_in(13) And Control(165)));
+  Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(75)) OR (Data_in(7) And Control(88)) OR (Data_in(8) And Control(101)) OR (Data_in(9) And Control(114)) OR (Data_in(10) And Control(127)) OR (Data_in(11) And Control(140)) OR (Data_in(12) And Control(153)) OR (Data_in(13) And Control(166)));
+  Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(89)) OR (Data_in(8) And Control(102)) OR (Data_in(9) And Control(115)) OR (Data_in(10) And Control(128)) OR (Data_in(11) And Control(141)) OR (Data_in(12) And Control(154)) OR (Data_in(13) And Control(167)));
+  Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(90)) OR (Data_in(8) And Control(103)) OR (Data_in(9) And Control(116)) OR (Data_in(10) And Control(129)) OR (Data_in(11) And Control(142)) OR (Data_in(12) And Control(155)) OR (Data_in(13) And Control(168)));
+  Dout(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(104)) OR (Data_in(9) And Control(117)) OR (Data_in(10) And Control(130)) OR (Data_in(11) And Control(143)) OR (Data_in(12) And Control(156)) OR (Data_in(13) And Control(169)));
 end generate crossbit13x13;
 
@@ -224,18 +227,18 @@
 crossbit14x14 : if number_of_ports = 14 generate
 
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(85)) OR (Data_in(8) And Control(99)) OR (Data_in(9) And Control(113)) OR (Data_in(10) And Control(127)) OR (Data_in(11) And Control(141)) OR (Data_in(12) And Control(155)) OR (Data_in(13) And Control(169)) OR (Data_in(14) And Control(183)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(86)) OR (Data_in(8) And Control(100)) OR (Data_in(9) And Control(114)) OR (Data_in(10) And Control(128)) OR (Data_in(11) And Control(142)) OR (Data_in(12) And Control(156)) OR (Data_in(13) And Control(170)) OR (Data_in(14) And Control(184)));
-  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(73)) OR (Data_in(7) And Control(87)) OR (Data_in(8) And Control(101)) OR (Data_in(9) And Control(115)) OR (Data_in(10) And Control(129)) OR (Data_in(11) And Control(143)) OR (Data_in(12) And Control(157)) OR (Data_in(13) And Control(171)) OR (Data_in(14) And Control(185)));
-  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(74)) OR (Data_in(7) And Control(88)) OR (Data_in(8) And Control(102)) OR (Data_in(9) And Control(116)) OR (Data_in(10) And Control(130)) OR (Data_in(11) And Control(144)) OR (Data_in(12) And Control(158)) OR (Data_in(13) And Control(172)) OR (Data_in(14) And Control(186)));
-  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(75)) OR (Data_in(7) And Control(89)) OR (Data_in(8) And Control(103)) OR (Data_in(9) And Control(117)) OR (Data_in(10) And Control(131)) OR (Data_in(11) And Control(145)) OR (Data_in(12) And Control(159)) OR (Data_in(13) And Control(173)) OR (Data_in(14) And Control(187)));
-  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(90)) OR (Data_in(8) And Control(104)) OR (Data_in(9) And Control(118)) OR (Data_in(10) And Control(132)) OR (Data_in(11) And Control(146)) OR (Data_in(12) And Control(160)) OR (Data_in(13) And Control(174)) OR (Data_in(14) And Control(188)));
-  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(105)) OR (Data_in(9) And Control(119)) OR (Data_in(10) And Control(133)) OR (Data_in(11) And Control(147)) OR (Data_in(12) And Control(161)) OR (Data_in(13) And Control(175)) OR (Data_in(14) And Control(189)));
-  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(92)) OR (Data_in(8) And Control(106)) OR (Data_in(9) And Control(120)) OR (Data_in(10) And Control(134)) OR (Data_in(11) And Control(148)) OR (Data_in(12) And Control(162)) OR (Data_in(13) And Control(176)) OR (Data_in(14) And Control(190)));
-  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(79)) OR (Data_in(7) And Control(93)) OR (Data_in(8) And Control(107)) OR (Data_in(9) And Control(121)) OR (Data_in(10) And Control(135)) OR (Data_in(11) And Control(149)) OR (Data_in(12) And Control(163)) OR (Data_in(13) And Control(177)) OR (Data_in(14) And Control(191)));
-  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(80)) OR (Data_in(7) And Control(94)) OR (Data_in(8) And Control(108)) OR (Data_in(9) And Control(122)) OR (Data_in(10) And Control(136)) OR (Data_in(11) And Control(150)) OR (Data_in(12) And Control(164)) OR (Data_in(13) And Control(178)) OR (Data_in(14) And Control(192)));
-  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(95)) OR (Data_in(8) And Control(109)) OR (Data_in(9) And Control(123)) OR (Data_in(10) And Control(137)) OR (Data_in(11) And Control(151)) OR (Data_in(12) And Control(165)) OR (Data_in(13) And Control(179)) OR (Data_in(14) And Control(193)));
-  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(96)) OR (Data_in(8) And Control(110)) OR (Data_in(9) And Control(124)) OR (Data_in(10) And Control(138)) OR (Data_in(11) And Control(152)) OR (Data_in(12) And Control(166)) OR (Data_in(13) And Control(180)) OR (Data_in(14) And Control(194)));
-  Data_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(111)) OR (Data_in(9) And Control(125)) OR (Data_in(10) And Control(139)) OR (Data_in(11) And Control(153)) OR (Data_in(12) And Control(167)) OR (Data_in(13) And Control(181)) OR (Data_in(14) And Control(195)));
-  Data_out(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(112)) OR (Data_in(9) And Control(126)) OR (Data_in(10) And Control(140)) OR (Data_in(11) And Control(154)) OR (Data_in(12) And Control(168)) OR (Data_in(13) And Control(182)) OR (Data_in(14) And Control(196)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(15)) OR (Data_in(3) And Control(29)) OR (Data_in(4) And Control(43)) OR (Data_in(5) And Control(57)) OR (Data_in(6) And Control(71)) OR (Data_in(7) And Control(85)) OR (Data_in(8) And Control(99)) OR (Data_in(9) And Control(113)) OR (Data_in(10) And Control(127)) OR (Data_in(11) And Control(141)) OR (Data_in(12) And Control(155)) OR (Data_in(13) And Control(169)) OR (Data_in(14) And Control(183)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(30)) OR (Data_in(4) And Control(44)) OR (Data_in(5) And Control(58)) OR (Data_in(6) And Control(72)) OR (Data_in(7) And Control(86)) OR (Data_in(8) And Control(100)) OR (Data_in(9) And Control(114)) OR (Data_in(10) And Control(128)) OR (Data_in(11) And Control(142)) OR (Data_in(12) And Control(156)) OR (Data_in(13) And Control(170)) OR (Data_in(14) And Control(184)));
+  Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(45)) OR (Data_in(5) And Control(59)) OR (Data_in(6) And Control(73)) OR (Data_in(7) And Control(87)) OR (Data_in(8) And Control(101)) OR (Data_in(9) And Control(115)) OR (Data_in(10) And Control(129)) OR (Data_in(11) And Control(143)) OR (Data_in(12) And Control(157)) OR (Data_in(13) And Control(171)) OR (Data_in(14) And Control(185)));
+  Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(60)) OR (Data_in(6) And Control(74)) OR (Data_in(7) And Control(88)) OR (Data_in(8) And Control(102)) OR (Data_in(9) And Control(116)) OR (Data_in(10) And Control(130)) OR (Data_in(11) And Control(144)) OR (Data_in(12) And Control(158)) OR (Data_in(13) And Control(172)) OR (Data_in(14) And Control(186)));
+  Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(75)) OR (Data_in(7) And Control(89)) OR (Data_in(8) And Control(103)) OR (Data_in(9) And Control(117)) OR (Data_in(10) And Control(131)) OR (Data_in(11) And Control(145)) OR (Data_in(12) And Control(159)) OR (Data_in(13) And Control(173)) OR (Data_in(14) And Control(187)));
+  Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(90)) OR (Data_in(8) And Control(104)) OR (Data_in(9) And Control(118)) OR (Data_in(10) And Control(132)) OR (Data_in(11) And Control(146)) OR (Data_in(12) And Control(160)) OR (Data_in(13) And Control(174)) OR (Data_in(14) And Control(188)));
+  Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(105)) OR (Data_in(9) And Control(119)) OR (Data_in(10) And Control(133)) OR (Data_in(11) And Control(147)) OR (Data_in(12) And Control(161)) OR (Data_in(13) And Control(175)) OR (Data_in(14) And Control(189)));
+  Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(92)) OR (Data_in(8) And Control(106)) OR (Data_in(9) And Control(120)) OR (Data_in(10) And Control(134)) OR (Data_in(11) And Control(148)) OR (Data_in(12) And Control(162)) OR (Data_in(13) And Control(176)) OR (Data_in(14) And Control(190)));
+  Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(79)) OR (Data_in(7) And Control(93)) OR (Data_in(8) And Control(107)) OR (Data_in(9) And Control(121)) OR (Data_in(10) And Control(135)) OR (Data_in(11) And Control(149)) OR (Data_in(12) And Control(163)) OR (Data_in(13) And Control(177)) OR (Data_in(14) And Control(191)));
+  Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(80)) OR (Data_in(7) And Control(94)) OR (Data_in(8) And Control(108)) OR (Data_in(9) And Control(122)) OR (Data_in(10) And Control(136)) OR (Data_in(11) And Control(150)) OR (Data_in(12) And Control(164)) OR (Data_in(13) And Control(178)) OR (Data_in(14) And Control(192)));
+  Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(95)) OR (Data_in(8) And Control(109)) OR (Data_in(9) And Control(123)) OR (Data_in(10) And Control(137)) OR (Data_in(11) And Control(151)) OR (Data_in(12) And Control(165)) OR (Data_in(13) And Control(179)) OR (Data_in(14) And Control(193)));
+  Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(96)) OR (Data_in(8) And Control(110)) OR (Data_in(9) And Control(124)) OR (Data_in(10) And Control(138)) OR (Data_in(11) And Control(152)) OR (Data_in(12) And Control(166)) OR (Data_in(13) And Control(180)) OR (Data_in(14) And Control(194)));
+  Dout(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(111)) OR (Data_in(9) And Control(125)) OR (Data_in(10) And Control(139)) OR (Data_in(11) And Control(153)) OR (Data_in(12) And Control(167)) OR (Data_in(13) And Control(181)) OR (Data_in(14) And Control(195)));
+  Dout(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(112)) OR (Data_in(9) And Control(126)) OR (Data_in(10) And Control(140)) OR (Data_in(11) And Control(154)) OR (Data_in(12) And Control(168)) OR (Data_in(13) And Control(182)) OR (Data_in(14) And Control(196)));
 end generate crossbit14x14;
 
@@ -245,19 +248,19 @@
 crossbit15x15 : if number_of_ports = 15 generate
 
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(106)) OR (Data_in(9) And Control(121)) OR (Data_in(10) And Control(136)) OR (Data_in(11) And Control(151)) OR (Data_in(12) And Control(166)) OR (Data_in(13) And Control(181)) OR (Data_in(14) And Control(196)) OR (Data_in(15) And Control(211)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(92)) OR (Data_in(8) And Control(107)) OR (Data_in(9) And Control(122)) OR (Data_in(10) And Control(137)) OR (Data_in(11) And Control(152)) OR (Data_in(12) And Control(167)) OR (Data_in(13) And Control(182)) OR (Data_in(14) And Control(197)) OR (Data_in(15) And Control(212)));
-  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(93)) OR (Data_in(8) And Control(108)) OR (Data_in(9) And Control(123)) OR (Data_in(10) And Control(138)) OR (Data_in(11) And Control(153)) OR (Data_in(12) And Control(168)) OR (Data_in(13) And Control(183)) OR (Data_in(14) And Control(198)) OR (Data_in(15) And Control(213)));
-  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(79)) OR (Data_in(7) And Control(94)) OR (Data_in(8) And Control(109)) OR (Data_in(9) And Control(124)) OR (Data_in(10) And Control(139)) OR (Data_in(11) And Control(154)) OR (Data_in(12) And Control(169)) OR (Data_in(13) And Control(184)) OR (Data_in(14) And Control(199)) OR (Data_in(15) And Control(214)));
-  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(80)) OR (Data_in(7) And Control(95)) OR (Data_in(8) And Control(110)) OR (Data_in(9) And Control(125)) OR (Data_in(10) And Control(140)) OR (Data_in(11) And Control(155)) OR (Data_in(12) And Control(170)) OR (Data_in(13) And Control(185)) OR (Data_in(14) And Control(200)) OR (Data_in(15) And Control(215)));
-  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(96)) OR (Data_in(8) And Control(111)) OR (Data_in(9) And Control(126)) OR (Data_in(10) And Control(141)) OR (Data_in(11) And Control(156)) OR (Data_in(12) And Control(171)) OR (Data_in(13) And Control(186)) OR (Data_in(14) And Control(201)) OR (Data_in(15) And Control(216)));
-  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(112)) OR (Data_in(9) And Control(127)) OR (Data_in(10) And Control(142)) OR (Data_in(11) And Control(157)) OR (Data_in(12) And Control(172)) OR (Data_in(13) And Control(187)) OR (Data_in(14) And Control(202)) OR (Data_in(15) And Control(217)));
-  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(113)) OR (Data_in(9) And Control(128)) OR (Data_in(10) And Control(143)) OR (Data_in(11) And Control(158)) OR (Data_in(12) And Control(173)) OR (Data_in(13) And Control(188)) OR (Data_in(14) And Control(203)) OR (Data_in(15) And Control(218)));
-  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(99)) OR (Data_in(8) And Control(114)) OR (Data_in(9) And Control(129)) OR (Data_in(10) And Control(144)) OR (Data_in(11) And Control(159)) OR (Data_in(12) And Control(174)) OR (Data_in(13) And Control(189)) OR (Data_in(14) And Control(204)) OR (Data_in(15) And Control(219)));
-  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(85)) OR (Data_in(7) And Control(100)) OR (Data_in(8) And Control(115)) OR (Data_in(9) And Control(130)) OR (Data_in(10) And Control(145)) OR (Data_in(11) And Control(160)) OR (Data_in(12) And Control(175)) OR (Data_in(13) And Control(190)) OR (Data_in(14) And Control(205)) OR (Data_in(15) And Control(220)));
-  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(71)) OR (Data_in(6) And Control(86)) OR (Data_in(7) And Control(101)) OR (Data_in(8) And Control(116)) OR (Data_in(9) And Control(131)) OR (Data_in(10) And Control(146)) OR (Data_in(11) And Control(161)) OR (Data_in(12) And Control(176)) OR (Data_in(13) And Control(191)) OR (Data_in(14) And Control(206)) OR (Data_in(15) And Control(221)));
-  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(57)) OR (Data_in(5) And Control(72)) OR (Data_in(6) And Control(87)) OR (Data_in(7) And Control(102)) OR (Data_in(8) And Control(117)) OR (Data_in(9) And Control(132)) OR (Data_in(10) And Control(147)) OR (Data_in(11) And Control(162)) OR (Data_in(12) And Control(177)) OR (Data_in(13) And Control(192)) OR (Data_in(14) And Control(207)) OR (Data_in(15) And Control(222)));
-  Data_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(43)) OR (Data_in(4) And Control(58)) OR (Data_in(5) And Control(73)) OR (Data_in(6) And Control(88)) OR (Data_in(7) And Control(103)) OR (Data_in(8) And Control(118)) OR (Data_in(9) And Control(133)) OR (Data_in(10) And Control(148)) OR (Data_in(11) And Control(163)) OR (Data_in(12) And Control(178)) OR (Data_in(13) And Control(193)) OR (Data_in(14) And Control(208)) OR (Data_in(15) And Control(223)));
-  Data_out(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(29)) OR (Data_in(3) And Control(44)) OR (Data_in(4) And Control(59)) OR (Data_in(5) And Control(74)) OR (Data_in(6) And Control(89)) OR (Data_in(7) And Control(104)) OR (Data_in(8) And Control(119)) OR (Data_in(9) And Control(134)) OR (Data_in(10) And Control(149)) OR (Data_in(11) And Control(164)) OR (Data_in(12) And Control(179)) OR (Data_in(13) And Control(194)) OR (Data_in(14) And Control(209)) OR (Data_in(15) And Control(224)));
-  Data_out(15) <= ((Data_in(1) And Control(15)) OR (Data_in(2) And Control(30)) OR (Data_in(3) And Control(45)) OR (Data_in(4) And Control(60)) OR (Data_in(5) And Control(75)) OR (Data_in(6) And Control(90)) OR (Data_in(7) And Control(105)) OR (Data_in(8) And Control(120)) OR (Data_in(9) And Control(135)) OR (Data_in(10) And Control(150)) OR (Data_in(11) And Control(165)) OR (Data_in(12) And Control(180)) OR (Data_in(13) And Control(195)) OR (Data_in(14) And Control(210)) OR (Data_in(15) And Control(225)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(16)) OR (Data_in(3) And Control(31)) OR (Data_in(4) And Control(46)) OR (Data_in(5) And Control(61)) OR (Data_in(6) And Control(76)) OR (Data_in(7) And Control(91)) OR (Data_in(8) And Control(106)) OR (Data_in(9) And Control(121)) OR (Data_in(10) And Control(136)) OR (Data_in(11) And Control(151)) OR (Data_in(12) And Control(166)) OR (Data_in(13) And Control(181)) OR (Data_in(14) And Control(196)) OR (Data_in(15) And Control(211)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(32)) OR (Data_in(4) And Control(47)) OR (Data_in(5) And Control(62)) OR (Data_in(6) And Control(77)) OR (Data_in(7) And Control(92)) OR (Data_in(8) And Control(107)) OR (Data_in(9) And Control(122)) OR (Data_in(10) And Control(137)) OR (Data_in(11) And Control(152)) OR (Data_in(12) And Control(167)) OR (Data_in(13) And Control(182)) OR (Data_in(14) And Control(197)) OR (Data_in(15) And Control(212)));
+  Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(48)) OR (Data_in(5) And Control(63)) OR (Data_in(6) And Control(78)) OR (Data_in(7) And Control(93)) OR (Data_in(8) And Control(108)) OR (Data_in(9) And Control(123)) OR (Data_in(10) And Control(138)) OR (Data_in(11) And Control(153)) OR (Data_in(12) And Control(168)) OR (Data_in(13) And Control(183)) OR (Data_in(14) And Control(198)) OR (Data_in(15) And Control(213)));
+  Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(64)) OR (Data_in(6) And Control(79)) OR (Data_in(7) And Control(94)) OR (Data_in(8) And Control(109)) OR (Data_in(9) And Control(124)) OR (Data_in(10) And Control(139)) OR (Data_in(11) And Control(154)) OR (Data_in(12) And Control(169)) OR (Data_in(13) And Control(184)) OR (Data_in(14) And Control(199)) OR (Data_in(15) And Control(214)));
+  Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(80)) OR (Data_in(7) And Control(95)) OR (Data_in(8) And Control(110)) OR (Data_in(9) And Control(125)) OR (Data_in(10) And Control(140)) OR (Data_in(11) And Control(155)) OR (Data_in(12) And Control(170)) OR (Data_in(13) And Control(185)) OR (Data_in(14) And Control(200)) OR (Data_in(15) And Control(215)));
+  Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(96)) OR (Data_in(8) And Control(111)) OR (Data_in(9) And Control(126)) OR (Data_in(10) And Control(141)) OR (Data_in(11) And Control(156)) OR (Data_in(12) And Control(171)) OR (Data_in(13) And Control(186)) OR (Data_in(14) And Control(201)) OR (Data_in(15) And Control(216)));
+  Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(112)) OR (Data_in(9) And Control(127)) OR (Data_in(10) And Control(142)) OR (Data_in(11) And Control(157)) OR (Data_in(12) And Control(172)) OR (Data_in(13) And Control(187)) OR (Data_in(14) And Control(202)) OR (Data_in(15) And Control(217)));
+  Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(113)) OR (Data_in(9) And Control(128)) OR (Data_in(10) And Control(143)) OR (Data_in(11) And Control(158)) OR (Data_in(12) And Control(173)) OR (Data_in(13) And Control(188)) OR (Data_in(14) And Control(203)) OR (Data_in(15) And Control(218)));
+  Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(99)) OR (Data_in(8) And Control(114)) OR (Data_in(9) And Control(129)) OR (Data_in(10) And Control(144)) OR (Data_in(11) And Control(159)) OR (Data_in(12) And Control(174)) OR (Data_in(13) And Control(189)) OR (Data_in(14) And Control(204)) OR (Data_in(15) And Control(219)));
+  Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(85)) OR (Data_in(7) And Control(100)) OR (Data_in(8) And Control(115)) OR (Data_in(9) And Control(130)) OR (Data_in(10) And Control(145)) OR (Data_in(11) And Control(160)) OR (Data_in(12) And Control(175)) OR (Data_in(13) And Control(190)) OR (Data_in(14) And Control(205)) OR (Data_in(15) And Control(220)));
+  Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(71)) OR (Data_in(6) And Control(86)) OR (Data_in(7) And Control(101)) OR (Data_in(8) And Control(116)) OR (Data_in(9) And Control(131)) OR (Data_in(10) And Control(146)) OR (Data_in(11) And Control(161)) OR (Data_in(12) And Control(176)) OR (Data_in(13) And Control(191)) OR (Data_in(14) And Control(206)) OR (Data_in(15) And Control(221)));
+  Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(57)) OR (Data_in(5) And Control(72)) OR (Data_in(6) And Control(87)) OR (Data_in(7) And Control(102)) OR (Data_in(8) And Control(117)) OR (Data_in(9) And Control(132)) OR (Data_in(10) And Control(147)) OR (Data_in(11) And Control(162)) OR (Data_in(12) And Control(177)) OR (Data_in(13) And Control(192)) OR (Data_in(14) And Control(207)) OR (Data_in(15) And Control(222)));
+  Dout(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(43)) OR (Data_in(4) And Control(58)) OR (Data_in(5) And Control(73)) OR (Data_in(6) And Control(88)) OR (Data_in(7) And Control(103)) OR (Data_in(8) And Control(118)) OR (Data_in(9) And Control(133)) OR (Data_in(10) And Control(148)) OR (Data_in(11) And Control(163)) OR (Data_in(12) And Control(178)) OR (Data_in(13) And Control(193)) OR (Data_in(14) And Control(208)) OR (Data_in(15) And Control(223)));
+  Dout(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(29)) OR (Data_in(3) And Control(44)) OR (Data_in(4) And Control(59)) OR (Data_in(5) And Control(74)) OR (Data_in(6) And Control(89)) OR (Data_in(7) And Control(104)) OR (Data_in(8) And Control(119)) OR (Data_in(9) And Control(134)) OR (Data_in(10) And Control(149)) OR (Data_in(11) And Control(164)) OR (Data_in(12) And Control(179)) OR (Data_in(13) And Control(194)) OR (Data_in(14) And Control(209)) OR (Data_in(15) And Control(224)));
+  Dout(15) <= ((Data_in(1) And Control(15)) OR (Data_in(2) And Control(30)) OR (Data_in(3) And Control(45)) OR (Data_in(4) And Control(60)) OR (Data_in(5) And Control(75)) OR (Data_in(6) And Control(90)) OR (Data_in(7) And Control(105)) OR (Data_in(8) And Control(120)) OR (Data_in(9) And Control(135)) OR (Data_in(10) And Control(150)) OR (Data_in(11) And Control(165)) OR (Data_in(12) And Control(180)) OR (Data_in(13) And Control(195)) OR (Data_in(14) And Control(210)) OR (Data_in(15) And Control(225)));
 end generate crossbit15x15;
 
@@ -267,22 +270,31 @@
 crossbit16x16 : if number_of_ports = 16 generate
 
-  Data_out(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(113)) OR (Data_in(9) And Control(129)) OR (Data_in(10) And Control(145)) OR (Data_in(11) And Control(161)) OR (Data_in(12) And Control(177)) OR (Data_in(13) And Control(193)) OR (Data_in(14) And Control(209)) OR (Data_in(15) And Control(225)) OR (Data_in(16) And Control(241)));
-  Data_out(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(114)) OR (Data_in(9) And Control(130)) OR (Data_in(10) And Control(146)) OR (Data_in(11) And Control(162)) OR (Data_in(12) And Control(178)) OR (Data_in(13) And Control(194)) OR (Data_in(14) And Control(210)) OR (Data_in(15) And Control(226)) OR (Data_in(16) And Control(242)));
-  Data_out(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(99)) OR (Data_in(8) And Control(115)) OR (Data_in(9) And Control(131)) OR (Data_in(10) And Control(147)) OR (Data_in(11) And Control(163)) OR (Data_in(12) And Control(179)) OR (Data_in(13) And Control(195)) OR (Data_in(14) And Control(211)) OR (Data_in(15) And Control(227)) OR (Data_in(16) And Control(243)));
-  Data_out(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(100)) OR (Data_in(8) And Control(116)) OR (Data_in(9) And Control(132)) OR (Data_in(10) And Control(148)) OR (Data_in(11) And Control(164)) OR (Data_in(12) And Control(180)) OR (Data_in(13) And Control(196)) OR (Data_in(14) And Control(212)) OR (Data_in(15) And Control(228)) OR (Data_in(16) And Control(244)));
-  Data_out(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(85)) OR (Data_in(7) And Control(101)) OR (Data_in(8) And Control(117)) OR (Data_in(9) And Control(133)) OR (Data_in(10) And Control(149)) OR (Data_in(11) And Control(165)) OR (Data_in(12) And Control(181)) OR (Data_in(13) And Control(197)) OR (Data_in(14) And Control(213)) OR (Data_in(15) And Control(229)) OR (Data_in(16) And Control(245)));
-  Data_out(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(86)) OR (Data_in(7) And Control(102)) OR (Data_in(8) And Control(118)) OR (Data_in(9) And Control(134)) OR (Data_in(10) And Control(150)) OR (Data_in(11) And Control(166)) OR (Data_in(12) And Control(182)) OR (Data_in(13) And Control(198)) OR (Data_in(14) And Control(214)) OR (Data_in(15) And Control(230)) OR (Data_in(16) And Control(246)));
-  Data_out(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(71)) OR (Data_in(6) And Control(87)) OR (Data_in(7) And Control(103)) OR (Data_in(8) And Control(119)) OR (Data_in(9) And Control(135)) OR (Data_in(10) And Control(151)) OR (Data_in(11) And Control(167)) OR (Data_in(12) And Control(183)) OR (Data_in(13) And Control(199)) OR (Data_in(14) And Control(215)) OR (Data_in(15) And Control(231)) OR (Data_in(16) And Control(247)));
-  Data_out(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(72)) OR (Data_in(6) And Control(88)) OR (Data_in(7) And Control(104)) OR (Data_in(8) And Control(120)) OR (Data_in(9) And Control(136)) OR (Data_in(10) And Control(152)) OR (Data_in(11) And Control(168)) OR (Data_in(12) And Control(184)) OR (Data_in(13) And Control(200)) OR (Data_in(14) And Control(216)) OR (Data_in(15) And Control(232)) OR (Data_in(16) And Control(248)));
-  Data_out(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(57)) OR (Data_in(5) And Control(73)) OR (Data_in(6) And Control(89)) OR (Data_in(7) And Control(105)) OR (Data_in(8) And Control(121)) OR (Data_in(9) And Control(137)) OR (Data_in(10) And Control(153)) OR (Data_in(11) And Control(169)) OR (Data_in(12) And Control(185)) OR (Data_in(13) And Control(201)) OR (Data_in(14) And Control(217)) OR (Data_in(15) And Control(233)) OR (Data_in(16) And Control(249)));
-  Data_out(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(58)) OR (Data_in(5) And Control(74)) OR (Data_in(6) And Control(90)) OR (Data_in(7) And Control(106)) OR (Data_in(8) And Control(122)) OR (Data_in(9) And Control(138)) OR (Data_in(10) And Control(154)) OR (Data_in(11) And Control(170)) OR (Data_in(12) And Control(186)) OR (Data_in(13) And Control(202)) OR (Data_in(14) And Control(218)) OR (Data_in(15) And Control(234)) OR (Data_in(16) And Control(250)));
-  Data_out(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(43)) OR (Data_in(4) And Control(59)) OR (Data_in(5) And Control(75)) OR (Data_in(6) And Control(91)) OR (Data_in(7) And Control(107)) OR (Data_in(8) And Control(123)) OR (Data_in(9) And Control(139)) OR (Data_in(10) And Control(155)) OR (Data_in(11) And Control(171)) OR (Data_in(12) And Control(187)) OR (Data_in(13) And Control(203)) OR (Data_in(14) And Control(219)) OR (Data_in(15) And Control(235)) OR (Data_in(16) And Control(251)));
-  Data_out(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(44)) OR (Data_in(4) And Control(60)) OR (Data_in(5) And Control(76)) OR (Data_in(6) And Control(92)) OR (Data_in(7) And Control(108)) OR (Data_in(8) And Control(124)) OR (Data_in(9) And Control(140)) OR (Data_in(10) And Control(156)) OR (Data_in(11) And Control(172)) OR (Data_in(12) And Control(188)) OR (Data_in(13) And Control(204)) OR (Data_in(14) And Control(220)) OR (Data_in(15) And Control(236)) OR (Data_in(16) And Control(252)));
-  Data_out(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(29)) OR (Data_in(3) And Control(45)) OR (Data_in(4) And Control(61)) OR (Data_in(5) And Control(77)) OR (Data_in(6) And Control(93)) OR (Data_in(7) And Control(109)) OR (Data_in(8) And Control(125)) OR (Data_in(9) And Control(141)) OR (Data_in(10) And Control(157)) OR (Data_in(11) And Control(173)) OR (Data_in(12) And Control(189)) OR (Data_in(13) And Control(205)) OR (Data_in(14) And Control(221)) OR (Data_in(15) And Control(237)) OR (Data_in(16) And Control(253)));
-  Data_out(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(30)) OR (Data_in(3) And Control(46)) OR (Data_in(4) And Control(62)) OR (Data_in(5) And Control(78)) OR (Data_in(6) And Control(94)) OR (Data_in(7) And Control(110)) OR (Data_in(8) And Control(126)) OR (Data_in(9) And Control(142)) OR (Data_in(10) And Control(158)) OR (Data_in(11) And Control(174)) OR (Data_in(12) And Control(190)) OR (Data_in(13) And Control(206)) OR (Data_in(14) And Control(222)) OR (Data_in(15) And Control(238)) OR (Data_in(16) And Control(254)));
-  Data_out(15) <= ((Data_in(1) And Control(15)) OR (Data_in(2) And Control(31)) OR (Data_in(3) And Control(47)) OR (Data_in(4) And Control(63)) OR (Data_in(5) And Control(79)) OR (Data_in(6) And Control(95)) OR (Data_in(7) And Control(111)) OR (Data_in(8) And Control(127)) OR (Data_in(9) And Control(143)) OR (Data_in(10) And Control(159)) OR (Data_in(11) And Control(175)) OR (Data_in(12) And Control(191)) OR (Data_in(13) And Control(207)) OR (Data_in(14) And Control(223)) OR (Data_in(15) And Control(239)) OR (Data_in(16) And Control(255)));
-  Data_out(16) <= ((Data_in(1) And Control(16)) OR (Data_in(2) And Control(32)) OR (Data_in(3) And Control(48)) OR (Data_in(4) And Control(64)) OR (Data_in(5) And Control(80)) OR (Data_in(6) And Control(96)) OR (Data_in(7) And Control(112)) OR (Data_in(8) And Control(128)) OR (Data_in(9) And Control(144)) OR (Data_in(10) And Control(160)) OR (Data_in(11) And Control(176)) OR (Data_in(12) And Control(192)) OR (Data_in(13) And Control(208)) OR (Data_in(14) And Control(224)) OR (Data_in(15) And Control(240)) OR (Data_in(16) And Control(256)));
+  Dout(1) <= ((Data_in(1) And Control(1)) OR (Data_in(2) And Control(17)) OR (Data_in(3) And Control(33)) OR (Data_in(4) And Control(49)) OR (Data_in(5) And Control(65)) OR (Data_in(6) And Control(81)) OR (Data_in(7) And Control(97)) OR (Data_in(8) And Control(113)) OR (Data_in(9) And Control(129)) OR (Data_in(10) And Control(145)) OR (Data_in(11) And Control(161)) OR (Data_in(12) And Control(177)) OR (Data_in(13) And Control(193)) OR (Data_in(14) And Control(209)) OR (Data_in(15) And Control(225)) OR (Data_in(16) And Control(241)));
+  Dout(2) <= ((Data_in(1) And Control(2)) OR (Data_in(2) And Control(18)) OR (Data_in(3) And Control(34)) OR (Data_in(4) And Control(50)) OR (Data_in(5) And Control(66)) OR (Data_in(6) And Control(82)) OR (Data_in(7) And Control(98)) OR (Data_in(8) And Control(114)) OR (Data_in(9) And Control(130)) OR (Data_in(10) And Control(146)) OR (Data_in(11) And Control(162)) OR (Data_in(12) And Control(178)) OR (Data_in(13) And Control(194)) OR (Data_in(14) And Control(210)) OR (Data_in(15) And Control(226)) OR (Data_in(16) And Control(242)));
+  Dout(3) <= ((Data_in(1) And Control(3)) OR (Data_in(2) And Control(19)) OR (Data_in(3) And Control(35)) OR (Data_in(4) And Control(51)) OR (Data_in(5) And Control(67)) OR (Data_in(6) And Control(83)) OR (Data_in(7) And Control(99)) OR (Data_in(8) And Control(115)) OR (Data_in(9) And Control(131)) OR (Data_in(10) And Control(147)) OR (Data_in(11) And Control(163)) OR (Data_in(12) And Control(179)) OR (Data_in(13) And Control(195)) OR (Data_in(14) And Control(211)) OR (Data_in(15) And Control(227)) OR (Data_in(16) And Control(243)));
+  Dout(4) <= ((Data_in(1) And Control(4)) OR (Data_in(2) And Control(20)) OR (Data_in(3) And Control(36)) OR (Data_in(4) And Control(52)) OR (Data_in(5) And Control(68)) OR (Data_in(6) And Control(84)) OR (Data_in(7) And Control(100)) OR (Data_in(8) And Control(116)) OR (Data_in(9) And Control(132)) OR (Data_in(10) And Control(148)) OR (Data_in(11) And Control(164)) OR (Data_in(12) And Control(180)) OR (Data_in(13) And Control(196)) OR (Data_in(14) And Control(212)) OR (Data_in(15) And Control(228)) OR (Data_in(16) And Control(244)));
+  Dout(5) <= ((Data_in(1) And Control(5)) OR (Data_in(2) And Control(21)) OR (Data_in(3) And Control(37)) OR (Data_in(4) And Control(53)) OR (Data_in(5) And Control(69)) OR (Data_in(6) And Control(85)) OR (Data_in(7) And Control(101)) OR (Data_in(8) And Control(117)) OR (Data_in(9) And Control(133)) OR (Data_in(10) And Control(149)) OR (Data_in(11) And Control(165)) OR (Data_in(12) And Control(181)) OR (Data_in(13) And Control(197)) OR (Data_in(14) And Control(213)) OR (Data_in(15) And Control(229)) OR (Data_in(16) And Control(245)));
+  Dout(6) <= ((Data_in(1) And Control(6)) OR (Data_in(2) And Control(22)) OR (Data_in(3) And Control(38)) OR (Data_in(4) And Control(54)) OR (Data_in(5) And Control(70)) OR (Data_in(6) And Control(86)) OR (Data_in(7) And Control(102)) OR (Data_in(8) And Control(118)) OR (Data_in(9) And Control(134)) OR (Data_in(10) And Control(150)) OR (Data_in(11) And Control(166)) OR (Data_in(12) And Control(182)) OR (Data_in(13) And Control(198)) OR (Data_in(14) And Control(214)) OR (Data_in(15) And Control(230)) OR (Data_in(16) And Control(246)));
+  Dout(7) <= ((Data_in(1) And Control(7)) OR (Data_in(2) And Control(23)) OR (Data_in(3) And Control(39)) OR (Data_in(4) And Control(55)) OR (Data_in(5) And Control(71)) OR (Data_in(6) And Control(87)) OR (Data_in(7) And Control(103)) OR (Data_in(8) And Control(119)) OR (Data_in(9) And Control(135)) OR (Data_in(10) And Control(151)) OR (Data_in(11) And Control(167)) OR (Data_in(12) And Control(183)) OR (Data_in(13) And Control(199)) OR (Data_in(14) And Control(215)) OR (Data_in(15) And Control(231)) OR (Data_in(16) And Control(247)));
+  Dout(8) <= ((Data_in(1) And Control(8)) OR (Data_in(2) And Control(24)) OR (Data_in(3) And Control(40)) OR (Data_in(4) And Control(56)) OR (Data_in(5) And Control(72)) OR (Data_in(6) And Control(88)) OR (Data_in(7) And Control(104)) OR (Data_in(8) And Control(120)) OR (Data_in(9) And Control(136)) OR (Data_in(10) And Control(152)) OR (Data_in(11) And Control(168)) OR (Data_in(12) And Control(184)) OR (Data_in(13) And Control(200)) OR (Data_in(14) And Control(216)) OR (Data_in(15) And Control(232)) OR (Data_in(16) And Control(248)));
+  Dout(9) <= ((Data_in(1) And Control(9)) OR (Data_in(2) And Control(25)) OR (Data_in(3) And Control(41)) OR (Data_in(4) And Control(57)) OR (Data_in(5) And Control(73)) OR (Data_in(6) And Control(89)) OR (Data_in(7) And Control(105)) OR (Data_in(8) And Control(121)) OR (Data_in(9) And Control(137)) OR (Data_in(10) And Control(153)) OR (Data_in(11) And Control(169)) OR (Data_in(12) And Control(185)) OR (Data_in(13) And Control(201)) OR (Data_in(14) And Control(217)) OR (Data_in(15) And Control(233)) OR (Data_in(16) And Control(249)));
+  Dout(10) <= ((Data_in(1) And Control(10)) OR (Data_in(2) And Control(26)) OR (Data_in(3) And Control(42)) OR (Data_in(4) And Control(58)) OR (Data_in(5) And Control(74)) OR (Data_in(6) And Control(90)) OR (Data_in(7) And Control(106)) OR (Data_in(8) And Control(122)) OR (Data_in(9) And Control(138)) OR (Data_in(10) And Control(154)) OR (Data_in(11) And Control(170)) OR (Data_in(12) And Control(186)) OR (Data_in(13) And Control(202)) OR (Data_in(14) And Control(218)) OR (Data_in(15) And Control(234)) OR (Data_in(16) And Control(250)));
+  Dout(11) <= ((Data_in(1) And Control(11)) OR (Data_in(2) And Control(27)) OR (Data_in(3) And Control(43)) OR (Data_in(4) And Control(59)) OR (Data_in(5) And Control(75)) OR (Data_in(6) And Control(91)) OR (Data_in(7) And Control(107)) OR (Data_in(8) And Control(123)) OR (Data_in(9) And Control(139)) OR (Data_in(10) And Control(155)) OR (Data_in(11) And Control(171)) OR (Data_in(12) And Control(187)) OR (Data_in(13) And Control(203)) OR (Data_in(14) And Control(219)) OR (Data_in(15) And Control(235)) OR (Data_in(16) And Control(251)));
+  Dout(12) <= ((Data_in(1) And Control(12)) OR (Data_in(2) And Control(28)) OR (Data_in(3) And Control(44)) OR (Data_in(4) And Control(60)) OR (Data_in(5) And Control(76)) OR (Data_in(6) And Control(92)) OR (Data_in(7) And Control(108)) OR (Data_in(8) And Control(124)) OR (Data_in(9) And Control(140)) OR (Data_in(10) And Control(156)) OR (Data_in(11) And Control(172)) OR (Data_in(12) And Control(188)) OR (Data_in(13) And Control(204)) OR (Data_in(14) And Control(220)) OR (Data_in(15) And Control(236)) OR (Data_in(16) And Control(252)));
+  Dout(13) <= ((Data_in(1) And Control(13)) OR (Data_in(2) And Control(29)) OR (Data_in(3) And Control(45)) OR (Data_in(4) And Control(61)) OR (Data_in(5) And Control(77)) OR (Data_in(6) And Control(93)) OR (Data_in(7) And Control(109)) OR (Data_in(8) And Control(125)) OR (Data_in(9) And Control(141)) OR (Data_in(10) And Control(157)) OR (Data_in(11) And Control(173)) OR (Data_in(12) And Control(189)) OR (Data_in(13) And Control(205)) OR (Data_in(14) And Control(221)) OR (Data_in(15) And Control(237)) OR (Data_in(16) And Control(253)));
+  Dout(14) <= ((Data_in(1) And Control(14)) OR (Data_in(2) And Control(30)) OR (Data_in(3) And Control(46)) OR (Data_in(4) And Control(62)) OR (Data_in(5) And Control(78)) OR (Data_in(6) And Control(94)) OR (Data_in(7) And Control(110)) OR (Data_in(8) And Control(126)) OR (Data_in(9) And Control(142)) OR (Data_in(10) And Control(158)) OR (Data_in(11) And Control(174)) OR (Data_in(12) And Control(190)) OR (Data_in(13) And Control(206)) OR (Data_in(14) And Control(222)) OR (Data_in(15) And Control(238)) OR (Data_in(16) And Control(254)));
+  Dout(15) <= ((Data_in(1) And Control(15)) OR (Data_in(2) And Control(31)) OR (Data_in(3) And Control(47)) OR (Data_in(4) And Control(63)) OR (Data_in(5) And Control(79)) OR (Data_in(6) And Control(95)) OR (Data_in(7) And Control(111)) OR (Data_in(8) And Control(127)) OR (Data_in(9) And Control(143)) OR (Data_in(10) And Control(159)) OR (Data_in(11) And Control(175)) OR (Data_in(12) And Control(191)) OR (Data_in(13) And Control(207)) OR (Data_in(14) And Control(223)) OR (Data_in(15) And Control(239)) OR (Data_in(16) And Control(255)));
+  Dout(16) <= ((Data_in(1) And Control(16)) OR (Data_in(2) And Control(32)) OR (Data_in(3) And Control(48)) OR (Data_in(4) And Control(64)) OR (Data_in(5) And Control(80)) OR (Data_in(6) And Control(96)) OR (Data_in(7) And Control(112)) OR (Data_in(8) And Control(128)) OR (Data_in(9) And Control(144)) OR (Data_in(10) And Control(160)) OR (Data_in(11) And Control(176)) OR (Data_in(12) And Control(192)) OR (Data_in(13) And Control(208)) OR (Data_in(14) And Control(224)) OR (Data_in(15) And Control(240)) OR (Data_in(16) And Control(256)));
 end generate crossbit16x16;
-
+--pcrossbit:process (clk,reset)
+--begin
+--if rising_edge(clk) then
+--	if reset='1' then
+--	data_out<= (others=>'0');
+--	else
+		data_out<=dout;
+--	end if;
+--end if;
+--end process pcrossbit;
 end Behavioral;
 
Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/FIFO_256_FWFT.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/FIFO_256_FWFT.vhd	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/FIFO_256_FWFT.vhd	(revision 65)
@@ -83,15 +83,16 @@
 
 -- ram instantiation de la bloc ram 256 octets du FIFO
-fifo_RAM_256: RAM_256 PORT MAP(
-		clka => clk_signal,
-		clkb => clk_signal,
-		wea => wr_en_signal,
-		ena => '1',
-		enb => '1',
-		addra => push_address_counter,
-		addrb => pop_address_counter,
-		dia => din,
-		dob => doa_signal
-	);
+--fifo_RAM_256: RAM_256 PORT MAP(
+--		clka => clk_signal,
+--		clkb => clk_signal,
+--		wea => wr_en_signal,
+--		ena => '1',
+--		enb => '1',
+--		addra => push_address_counter,
+--		addrb => pop_address_counter,
+--		dia => din,
+--		dob => dob_signal
+--		--dob => doa_signal
+--	);
 		
 -- circuiterie des signaux de validation et d'etat du fifo
@@ -102,5 +103,5 @@
 --empty_signal <= '1' when fifo_counter = "000000"  else
 --					 '0';
-empty_signal <= '1' when rd_ready='0' or unsigned(fifo_counter) = 0  else
+empty_signal <= '1' when (rd_ready='0') else -- or (All_zeros(fifo_counter) = '0')  else
 					 '0';
 clk_signal <= clk;
@@ -143,5 +144,5 @@
 										end if;
 
-					when others => fwft_fsm_state <= state0;
+--					when others => fwft_fsm_state <= state0;
 										
 										
Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/INPUT_PORT_MODULE.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/INPUT_PORT_MODULE.vhd	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/INPUT_PORT_MODULE.vhd	(revision 65)
@@ -44,5 +44,5 @@
     Port ( data_in : in  STD_LOGIC_VECTOR (Word-1 downto 0);
            data_in_en : in  STD_LOGIC; -- signaler la présence des données en entrée
-			  cmd_in_en : STD_LOGIC;    --permet d'identifier les données qui sont dans le tampon
+			  cmd_in_en :in STD_LOGIC;    --permet d'identifier les données qui sont dans le tampon
            reset : in  STD_LOGIC;
 			  clk   : in  STD_LOGIC;
@@ -73,5 +73,5 @@
 
 --definition du type etat pour les fsm
-type fsm_states is (state0, CmdOn, WaitGrant, ReqPort, state1, state2,stpulse, state3);-- definition du type etat pour le codage des etats des fsm
+type fsm_states is (state0, CmdOn, WaitGrant, ReqPort, state1, state2,stpulse,stateErr, state3);-- definition du type etat pour le codage des etats des fsm
 type fsm_states2 is(cmdstart,cmdwait,cmdread,cmdSetDest,cmdSetCount,cmdSetId,cmdpulse,CmdEnd);
 signal pop_state : fsm_states;
@@ -79,9 +79,10 @@
 signal cmd_exec : std_logic:='0';  --indique que le port est en train d'exécuter une commande
 signal dat_exec :std_logic:='0'; -- indique le port est en train de transférer des données
-signal readOk : std_logic:='0'; --indique s'il est possible de lire les données
+signal dat_Err :std_logic:='0'; -- signal une erreur pendant l'exécution 
+signal readOk,CmdReadOk : std_logic:='0'; --indique s'il est possible de lire les données
 -- signaux utilisés dans les fsm
-signal request_decoder : STD_LOGIC_VECTOR(number_of_ports  downto 1);
+signal request_decoder,req_grant : STD_LOGIC_VECTOR(number_of_ports  downto 1);
 signal request_decoder_en : std_logic;
-signal request_latch : STD_LOGIC_VECTOR(4 downto 1);   -- pourquoi pas 3 downto 0 ?
+signal request_latch : STD_LOGIC_VECTOR(4 downto 1):=(others=>'0');   -- pourquoi pas 3 downto 0 ?
 signal request_latch_en : std_logic;
 signal pipeline_latch : std_logic_vector(Word-1 downto 0);
@@ -131,10 +132,11 @@
 
 data_out <= pipeline_latch ;--when cmd_exec='0' else cmd_data_signal;
-fifo_empty <= fifo_empty_signal;
+fifo_empty <= empty_latch;
 reset_signal <= reset;
 grant_proc:process(clk)
 begin
 if rising_edge(clk) then
-	if unsigned(grant)> 0 then
+--	if unsigned(grant)> 0 then
+	if unsigned(req_grant) > 0 then
 		port_granted <= '1';   		--il faut veiller à ce que ce port soit vraiment autorisé
 	else 
@@ -145,4 +147,8 @@
 rd_en_signal <= not(empty_latch) ;
 request <= request_decoder;
+reg_grant:process (request_decoder,grant)
+begin
+req_grant<=request_decoder and grant;
+end process reg_grant;
 request_word <=  request_latch & request_decoder_en;
 clk_signal <= clk;
@@ -499,5 +505,5 @@
 		  case pop_state is
 			when state0 => if cmd_in_en='0'  then --il ne faut pas exécuter les deux MAE ...
-									if fifo_empty_signal  ='0' then -- pile pas vide on doit dépiler									
+									if empty_latch  ='0' then -- pile pas vide on doit dépiler									
 										pop_state <= WaitGrant;
 									end if;
@@ -505,7 +511,14 @@
 									pop_state <= CmdOn;
 								end if;
-			when CmdOn => if fifo_empty_signal='1' then
+			when CmdOn => if empty_latch='1' and cmd_in_en='0' then
 								pop_state <= state0;
+								elsif empty_latch='0' and cmd_in_en='1' then
+								pop_state <= CmdOn;
+								elsif empty_latch='1' and cmd_in_en='1' then
+								pop_state <= state0;
+								else -- empty_latch='0' and cmd_in_en='0'
+								pop_state <= WaitGrant;
 								end if;
+								
 			when WaitGrant => if port_granted = '1' then
 										--
@@ -536,4 +549,8 @@
 										  pop_state <= state2;
 										  ReadOk<='1';
+										else --rd_en_signal='0' fin prématurée de la lecture
+											ReadOk<='0';
+											pop_state<=stateErr;
+											data_counter<=(others => '0');
 										end if;
 									else
@@ -549,5 +566,7 @@
 										data_counter <= data_counter - 1;
 										pop_state <= state0;
-																						
+			when stateErr => 	 
+										data_counter <= data_counter;
+										pop_state <= stateErr;												
 			when others => pop_state <= state0;
 		   end case;
@@ -557,5 +576,5 @@
 
 -- actions associées à chaque etat de la fsm de mealy
-pop_fsm_action : process(pop_state, fifo_out_signal,fifo_empty_signal, rd_en_signal,readok, port_granted )
+pop_fsm_action : process(pop_state, fifo_out_signal,empty_latch, rd_en_signal,readok, port_granted )
   begin   
 -- code fonctionnel	
@@ -568,7 +587,9 @@
 								dat_priority_rotation <= '1';
 								dat_exec<='0';
+								dat_Err<='0';
 								push_dout<=fifo_out_signal;
+								
 		when CmdOn =>		dat_request_latch_en <= '0';  
-								dat_pipeline_latch_en <= rd_en_signal;
+								dat_pipeline_latch_en <= '0';
 								dat_fifo_read_signal <='0';
 								dat_request_decoder_en <= '0';
@@ -576,4 +597,5 @@
 								dat_priority_rotation <= '1';
 								dat_exec<='0';
+								dat_Err<='0';
 								push_dout<=fifo_out_signal;
 		when WaitGrant =>	
@@ -585,13 +607,15 @@
 								dat_priority_rotation <= '0';
 								dat_exec<='1';
+								dat_Err<='0';
 								push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0);
 		when ReqPort =>	
 								dat_request_latch_en <='1'; --autoriser l'identification du port de destination
-								dat_pipeline_latch_en <= Port_granted; --pour le transmettre à travers le réseau
-								dat_fifo_read_signal <= Port_granted;
+								dat_pipeline_latch_en <= '1'; --pour le transmettre à travers le réseau
+								dat_fifo_read_signal <= '1';
 								dat_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
 								dat_data_out_pulse <= '0';     --transmettre le signal pour le dernier mot
 								dat_priority_rotation <= '0';
 								dat_exec<='1';
+								dat_Err<='0';
 								push_dout<=fifo_out_signal(7 downto 4) & PORT_ID(3 downto 0);
 							
@@ -600,7 +624,8 @@
 								dat_fifo_read_signal <= rd_en_signal and port_granted;
 								dat_request_decoder_en <= '1';
-								dat_data_out_pulse <= '1';
+								dat_data_out_pulse <= port_granted;
 								dat_priority_rotation <= '0';
 								dat_exec<='1';
+								dat_Err<='0';
 								push_dout<=fifo_out_signal;
 								
@@ -612,4 +637,5 @@
 								dat_priority_rotation <= '0';
 								dat_exec<='1';
+								dat_Err<='0';
 								push_dout<=fifo_out_signal;
 								
@@ -621,4 +647,5 @@
 								dat_priority_rotation <= '0';
 								dat_exec<='1';
+								dat_Err<='0';
 								push_dout<=fifo_out_signal;
 								
@@ -630,6 +657,15 @@
 								dat_data_out_pulse <= '0';
 								dat_exec<='0';
+								dat_Err<='0';
 								push_dout<=fifo_out_signal;
-		
+		when stateErr =>    dat_request_latch_en <= '0';
+								dat_pipeline_latch_en <= '0';
+								dat_priority_rotation <= '1';    -- libérer la priorité
+								dat_fifo_read_signal <= '0';
+								dat_request_decoder_en <= '0';   --libérer le décodeur
+								dat_data_out_pulse <= '0';
+								dat_exec<='1';
+								dat_Err<='1';
+								push_dout<=fifo_out_signal;
 		when others =>    dat_request_latch_en <= '0';
 								dat_pipeline_latch_en <= '0';
@@ -639,4 +675,5 @@
 								dat_data_out_pulse <= '0';
 								dat_exec<='0';
+								dat_Err<='0';
 								push_dout<=fifo_out_signal;
 										
@@ -655,45 +692,57 @@
 	
 	   when cmdstart  =>
-				if cmd_in_en='1' and dat_exec='0' and fifo_empty_signal='0' then 
-				cmdstate<=cmdwait;
+				if cmd_in_en='1' and dat_exec='0' and empty_latch='0' then 
+				cmdstate<=cmdread;
 				end if;
-		when cmdwait => if fifo_empty_signal='0' and port_granted ='1' then
+				cmdReadOk<='0';
+		when cmdwait => if port_granted='1' then  -- demande du port de sortie
 								
-									cmdstate<=cmdread;
+									cmdstate<=cmdsetdest;
+							elsif cmd_in_en='1' then
+								cmdstate<=cmdwait;
 							else 
 								cmdstate<=cmdstart;
 							end if;
+							cmdReadOk<='0';
 		when cmdread =>
-				if port_granted ='1'then -- ne pas modifier l'état des priorités si on ne l'avait pas
+--				if port_granted ='1'then -- ne pas modifier l'état des priorités si on ne l'avait pas
 					cmdcode:= to_integer(unsigned(fifo_out_signal));
 					if cmdcode=1 then --code de getportid
-							cmdstate<=cmdsetdest;
+							cmdstate<=cmdwait;
+							cmdReadOk<='1';
 					else
-						if port_granted='1' then
-							cmdstate<=cmdend;
-						end if;
+						        --ne pas prendre le code inconnu en compte
+							cmdstate<=cmdend; -- la commande n'a pas été reconnu
+						
+						cmdReadOk<='0';
 					end if;
-				end if;
+--				end if;
 		when cmdsetdest =>
 				if port_granted='1' then
 					cmdstate<=cmdsetcount;
 				end if;
+				cmdReadOk<='0';
 		when cmdsetcount =>
 				if port_granted='1' then
 					cmdstate<=cmdsetID;
+				else
+					cmdstate<=cmdsetdest;
 				end if;
+				cmdReadOk<='0';
 		when cmdsetID=>
 			if port_granted='1' then
 			cmdstate <=cmdpulse;
 			end if;
+			cmdReadOk<='0';
 		when cmdpulse =>
 			if port_granted='1' then
 			cmdstate <=cmdEnd;
 			end if;
+			cmdReadOk<='0';
 		when cmdend  =>
-			
+			if cmd_in_en='0' then --éviter l'exécution en boucle
 				cmdstate<=cmdstart; 
-			
-				
+			end if;
+			cmdReadOk<='0';	
 	  
 	end case;
@@ -715,27 +764,27 @@
 						cmd_data_signal<=(others=>'0');
 						cmd_data_out_pulse <= '0';
-	when cmdwait =>
+
+	when cmdread =>
+						cmd_exec<='1';
+						cmd_pipeline_latch_en <= '0';
+						cmd_fifo_read_signal <= '1'; -- vider le tampon d'entrée
+						cmd_request_latch_en<='1';    --mémoriser l'adresse de destination
+						cmd_request_decoder_en <= '1';                   --demande d'émission
+						cmd_data_out_pulse <= '0';
+						cmd_priority_rotation <= '1';                    --sans priorité
+						cmd_data_signal<=Port_ID;  
+		when cmdwait =>
 						cmd_exec<='1';
 						cmd_pipeline_latch_en <='0';
 						cmd_fifo_read_signal <= '0';
-						cmd_priority_rotation <= '1';    --sans priorité
-						cmd_request_latch_en<='0';
-						cmd_request_decoder_en <= not(fifo_empty_signal);   --demande d'émission
-						cmd_data_signal<=(others=>'0');
-						cmd_data_out_pulse <= '0';
-	when cmdread =>
-						cmd_exec<='1';
-						cmd_pipeline_latch_en <= '1';
-						cmd_fifo_read_signal <= '0';
-						cmd_request_latch_en<='1';    --mémoriser l'adresse de destination
-						cmd_request_decoder_en <= '1';                   --demande d'émission
-						cmd_data_out_pulse <= '0';
-						cmd_priority_rotation <= '0';                    --avec priorité
-						--cmd_data_signal<=(others=>'0');
-						cmd_data_signal<=Port_ID;  
+						cmd_request_latch_en<='1';
+						cmd_priority_rotation <= '0';    --avec priorité
+						cmd_request_decoder_en <= '1';   --demande d'émission
+						cmd_data_signal<=Port_ID;
+						cmd_data_out_pulse <= '0';					
 	when cmdsetdest  =>
 						--cmd_request_decoder_en <= '1';
 						cmd_exec<='1';
-						cmd_pipeline_latch_en <='1';
+						cmd_pipeline_latch_en <='1'; --empiler dans le tampon de sortie la donnée
 						cmd_fifo_read_signal <='0';
 						cmd_request_latch_en<='0';
@@ -744,5 +793,14 @@
 						cmd_priority_rotation <= '0';
 						cmd_data_signal<=Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
-						
+	when cmdsetcount =>
+								 
+						cmd_exec<='1';   
+						cmd_pipeline_latch_en <='1'; -- empiler dans le tampon de sortie les données
+						cmd_fifo_read_signal <='0';
+						cmd_request_latch_en<='0';  --enregistrer l'adresse de destination
+						cmd_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
+						cmd_data_out_pulse <= port_granted;
+						cmd_priority_rotation <= '0';
+						cmd_data_signal<=STD_LOGIC_VECTOR(to_unsigned(3,8));					
 	when cmdSetId =>
 						--cmd_request_decoder_en <= '1';
@@ -750,21 +808,10 @@
 						cmd_pipeline_latch_en <='1';
 						cmd_fifo_read_signal <='0';
-						cmd_request_latch_en<='0';
+						cmd_request_latch_en<='0';			--enregistrer l'adresse de destination
 						cmd_request_decoder_en <= '1';          --autoriser le decodeur à activer le dernier bit de request
-						cmd_data_out_pulse <= '1';
+						cmd_data_out_pulse <= port_granted;
 						cmd_priority_rotation <= '0';
 						cmd_data_signal<=Port_ID;    -- le numéro du port et le nombre total des ports est envoyé
 											
-	when cmdsetcount =>
-								 
-						cmd_exec<='1';   
-						cmd_pipeline_latch_en <='1';
-						cmd_fifo_read_signal <='1';
-						cmd_request_latch_en<='0';
-						cmd_request_decoder_en <= '1';          --autoriser le decodeur activer le dernier bit de request
-						cmd_data_out_pulse <= port_granted;
-						cmd_priority_rotation <= '0';
-						cmd_data_signal<=STD_LOGIC_VECTOR(to_unsigned(3,8));
-	
 	when cmdpulse =>	cmd_exec<='1';
 						cmd_pipeline_latch_en <='0';
Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Proto_receiv.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Proto_receiv.vhd	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Proto_receiv.vhd	(revision 65)
@@ -81,11 +81,15 @@
 								dlen:=to_integer(unsigned(fifo_out));
 								mem(1)<=fifo_out; -- la longueur
-								etrec<=r_data;
 								
+								if dlen>2 then
+									etrec<=r_data;
+								else
+									etrec<=r_end;
+								end if;
 								i:=1;
 								
 						when r_data  =>
 								if fifo_empty='0' then
-									if i<dlen-3 then
+									if i<dlen-2 then
 										i:=i+1;
 										mem(i)<=fifo_out;
Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER12_12.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER12_12.VHD	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER12_12.VHD	(revision 65)
@@ -55,9 +55,10 @@
  signal grant_latch : std_logic_vector(144 downto 1); 
  signal priority_rotation_en : std_logic; 
- signal Grant :  std_logic_vector(144 downto 1);
+ signal Grant,req_grant :  std_logic_vector(144 downto 1);
  begin
 
 --validation de la rotation de priorité lorsque aucun port n'emet 
- priority_rotation_en <= '1' when unsigned(priority_rotation) = 4095 else 	'0'; 
+req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 4095 else 	'0'; 
 --latch servant qui memorise le signal grant pendant a transmission 
 grant_latch_process : process(clk)
@@ -66,10 +67,10 @@
    if reset = '1' then 
  		grant_latch <= (others => '0'); 
- 	 elsif priority_rotation_en = '1' then 
+ 	 elsif  priority_rotation_en = '1' or unsigned(Grant_latch)=0 then 
 	   grant_latch <= Grant; 
    end if; 
    end if; 
  end process; 
- port_grant <= Grant and grant_latch; 
+ port_grant <= grant_latch; 
  Grant(1)  <= Signal_grant(1)(1) or Signal_grant(13)(1); --  Grant(1,1)
 Grant(2)  <= Signal_grant(2)(2) or Signal_grant(14)(2); --  Grant(1,2)
Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER13_13.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER13_13.VHD	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER13_13.VHD	(revision 65)
@@ -55,9 +55,10 @@
  signal grant_latch : std_logic_vector(169 downto 1); 
  signal priority_rotation_en : std_logic; 
- signal Grant :  std_logic_vector(169 downto 1);
+ signal Grant,req_grant :  std_logic_vector(169 downto 1);
  begin
 
 --validation de la rotation de priorité lorsque aucun port n'emet 
- priority_rotation_en <= '1' when unsigned(priority_rotation) = 8191 else 	'0'; 
+req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 8191 else 	'0'; 
 --latch servant qui memorise le signal grant pendant a transmission 
 grant_latch_process : process(clk)
@@ -66,10 +67,10 @@
    if reset = '1' then 
  		grant_latch <= (others => '0'); 
- 	 elsif priority_rotation_en = '1' then 
+ 	 elsif priority_rotation_en = '1' or unsigned(Grant_latch)=0 then 
 	   grant_latch <= Grant; 
    end if; 
    end if; 
  end process; 
- port_grant <= Grant and grant_latch; 
+ port_grant <= grant_latch; 
  Grant(1)  <= Signal_grant(1)(1) or Signal_grant(14)(1); --  Grant(1,1)
 Grant(2)  <= Signal_grant(2)(2) or Signal_grant(15)(2); --  Grant(1,2)
Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER14_14.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER14_14.VHD	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER14_14.VHD	(revision 65)
@@ -55,9 +55,10 @@
  signal grant_latch : std_logic_vector(196 downto 1); 
  signal priority_rotation_en : std_logic; 
- signal Grant :  std_logic_vector(196 downto 1);
+ signal Grant,req_grant :  std_logic_vector(196 downto 1);
  begin
 
 --validation de la rotation de priorité lorsque aucun port n'emet 
- priority_rotation_en <= '1' when unsigned(priority_rotation) = 16383 else 	'0'; 
+req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 16383 else 	'0'; 
 --latch servant qui memorise le signal grant pendant a transmission 
 grant_latch_process : process(clk)
@@ -66,10 +67,10 @@
    if reset = '1' then 
  		grant_latch <= (others => '0'); 
- 	 elsif priority_rotation_en = '1' then 
+ 	 elsif priority_rotation_en = '1' or unsigned(Grant_latch)=0 then 
 	   grant_latch <= Grant; 
    end if; 
    end if; 
  end process; 
- port_grant <= Grant and grant_latch; 
+ port_grant <= grant_latch; 
  Grant(1)  <= Signal_grant(1)(1) or Signal_grant(15)(1); --  Grant(1,1)
 Grant(2)  <= Signal_grant(2)(2) or Signal_grant(16)(2); --  Grant(1,2)
Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER15_15.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER15_15.VHD	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER15_15.VHD	(revision 65)
@@ -55,9 +55,10 @@
  signal grant_latch : std_logic_vector(225 downto 1); 
  signal priority_rotation_en : std_logic; 
- signal Grant :  std_logic_vector(225 downto 1);
+ signal Grant ,req_grant:  std_logic_vector(225 downto 1);
  begin
 
 --validation de la rotation de priorité lorsque aucun port n'emet 
- priority_rotation_en <= '1' when unsigned(priority_rotation) = 32767 else 	'0'; 
+req_grant<=(request and grant_latch);
+ priority_rotation_en <= '1' when unsigned(req_grant)=0 or unsigned(priority_rotation) = 32767 else 	'0'; 
 --latch servant qui memorise le signal grant pendant a transmission 
 grant_latch_process : process(clk)
@@ -66,10 +67,10 @@
    if reset = '1' then 
  		grant_latch <= (others => '0'); 
- 	 elsif priority_rotation_en = '1' then 
+ 	 elsif priority_rotation_en = '1'or unsigned(Grant_latch)=0 then 
 	   grant_latch <= Grant; 
    end if; 
    end if; 
  end process; 
- port_grant <= Grant and grant_latch; 
+ port_grant <= grant_latch; 
  Grant(1)  <= Signal_grant(1)(1) or Signal_grant(16)(1); --  Grant(1,1)
 Grant(2)  <= Signal_grant(2)(2) or Signal_grant(17)(2); --  Grant(1,2)
Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER16_16.VHD
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER16_16.VHD	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER16_16.VHD	(revision 65)
@@ -55,9 +55,10 @@
  signal grant_latch : std_logic_vector(256 downto 1); 
  signal priority_rotation_en : std_logic; 
- signal Grant :  std_logic_vector(256 downto 1);
+ signal Grant,req_grant :  std_logic_vector(256 downto 1);
  begin
 
---validation de la rotation de priorité lorsque aucun port n'emet 
- priority_rotation_en <= '1' when unsigned(priority_rotation) = 65535 else 	'0'; 
+--validation de la rotation de priorité lorsque aucun port n'emet
+req_grant<=(request and grant_latch); 
+ priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 65535 else 	'0'; 
 --latch servant qui memorise le signal grant pendant a transmission 
 grant_latch_process : process(clk)
@@ -66,10 +67,10 @@
    if reset = '1' then 
  		grant_latch <= (others => '0'); 
- 	 elsif priority_rotation_en = '1' then 
+ 	 elsif priority_rotation_en = '1' or unsigned(Grant_latch)=0  then 
 	   grant_latch <= Grant; 
    end if; 
    end if; 
  end process; 
- port_grant <= Grant and grant_latch; 
+ port_grant <= grant_latch; 
  Grant(1)  <= Signal_grant(1)(1) or Signal_grant(17)(1); --  Grant(1,1)
 Grant(2)  <= Signal_grant(2)(2) or Signal_grant(18)(2); --  Grant(1,2)
Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SWITCH_GEN.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SWITCH_GEN.vhd	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SWITCH_GEN.vhd	(revision 65)
@@ -32,43 +32,13 @@
 entity SWITCH_GEN is 
  --type portio is array(positive range) of std_logic_vector (7 downto 0);    
- generic(number_of_ports : positive := 4);
+ generic(number_of_ports : positive := 8);
      port(
 	        -- ports d'entree
            Port_in : in typ_portIO(1 to number_of_ports) ;
---			  Port1_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---           Port2_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---           Port3_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---           Port4_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---			  Port5_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---           Port6_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---           Port7_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---           Port8_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---			  Port9_in : in  STD_LOGIC_VECTOR  (7 downto 0);
---           Port10_in : in  STD_LOGIC_VECTOR (7 downto 0);
---           Port11_in : in  STD_LOGIC_VECTOR (7 downto 0);
---           Port12_in : in  STD_LOGIC_VECTOR (7 downto 0);
---			  Port13_in : in  STD_LOGIC_VECTOR (7 downto 0);
---           Port14_in : in  STD_LOGIC_VECTOR (7 downto 0);
---           Port15_in : in  STD_LOGIC_VECTOR (7 downto 0);
---           Port16_in : in  STD_LOGIC_VECTOR (7 downto 0);
+
 			 
 			  -- port de sortie
 			  Port_out : out  typ_portIO(1 to number_of_ports);
---			  Port1_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port2_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port3_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port4_out : out  STD_LOGIC_VECTOR (7 downto 0);
---			  Port5_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port6_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port7_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port8_out : out  STD_LOGIC_VECTOR (7 downto 0);
---			  Port9_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port10_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port11_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port12_out : out  STD_LOGIC_VECTOR (7 downto 0);
---			  Port13_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port14_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port15_out : out  STD_LOGIC_VECTOR (7 downto 0);
---           Port16_out : out  STD_LOGIC_VECTOR (7 downto 0);
+
 			  -- signaux de controle
 			  data_in_en : in std_logic_vector(number_of_ports downto 1);
@@ -87,5 +57,5 @@
 
 COMPONENT INPUT_PORT_MODULE
-  generic(number_of_ports : positive := 4;
+  generic(number_of_ports : positive := 8;
 			Port_num: natural);
     Port ( data_in : in  STD_LOGIC_VECTOR (7 downto 0);
@@ -125,6 +95,7 @@
 			);
     Port ( 
-	        --Port_in : in Typ_PortIO(1 to number_of_crossbar_ports);
-			  Port1_in : in  STD_LOGIC_VECTOR (7 downto 0);
+	        clk : in  STD_LOGIC;
+			reset : in  STD_LOGIC;
+			Port1_in : in  STD_LOGIC_VECTOR (7 downto 0);
            Port2_in : in  STD_LOGIC_VECTOR (7 downto 0);
            Port3_in : in  STD_LOGIC_VECTOR (7 downto 0);
@@ -213,14 +184,4 @@
 
 --declaration des signaux de connection entre les modules du switch
---type port_connection_type is array(16 downto 1) of std_logic_vector(7 downto 1);
---signal crossbar_port_in_connetion : port_connection_type;
---signal crossbar_port_out_connetion :port_connection_type;
---signal request_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
---signal grant_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
---signal priority_rotation_connection : std_logic_vector(number_of_ports downto 1);
---signal fifo_out_full_connection : std_logic_vector(1 to number_of_ports);
---signal crossbar_in_pulse(_connection : std_logic_vector(number_of_ports downto 1);
---signal crossbar_out_pulse_connection : std_logic_vector(number_of_ports downto 1);
---variable i,j : integer;
 
 Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
@@ -231,74 +192,14 @@
 signal crossbar_in_port :  Typ_PortIO(1 to number_of_ports);
 
---signal crossbar_in_port1 : std_logic_vector(7 downto 0);
---signal crossbar_in_port2 : std_logic_vector(7 downto 0);
---signal crossbar_in_port3 : std_logic_vector(7 downto 0);
---signal crossbar_in_port4 : std_logic_vector(7 downto 0);
---signal crossbar_in_port5 : std_logic_vector(7 downto 0);
---signal crossbar_in_port6 : std_logic_vector(7 downto 0);
---signal crossbar_in_port7 : std_logic_vector(7 downto 0);
---signal crossbar_in_port8 : std_logic_vector(7 downto 0);
---signal crossbar_in_port9 : std_logic_vector(7 downto 0);
---signal crossbar_in_port10 : std_logic_vector(7 downto 0);
---signal crossbar_in_port11 : std_logic_vector(7 downto 0);
---signal crossbar_in_port12 : std_logic_vector(7 downto 0);
---signal crossbar_in_port13 : std_logic_vector(7 downto 0);
---signal crossbar_in_port14 : std_logic_vector(7 downto 0);
---signal crossbar_in_port15 : std_logic_vector(7 downto 0);
---signal crossbar_in_port16 : std_logic_vector(7 downto 0);
+
 
 signal crossbar_out_port  :  Typ_PortIO(1 to number_of_ports);
---signal crossbar_out_port1 : std_logic_vector(7 downto 0);
---signal crossbar_out_port2 : std_logic_vector(7 downto 0);
---signal crossbar_out_port3 : std_logic_vector(7 downto 0);
---signal crossbar_out_port4 : std_logic_vector(7 downto 0);
---signal crossbar_out_port5 : std_logic_vector(7 downto 0);
---signal crossbar_out_port6 : std_logic_vector(7 downto 0);
---signal crossbar_out_port7 : std_logic_vector(7 downto 0);
---signal crossbar_out_port8 : std_logic_vector(7 downto 0);
---signal crossbar_out_port9 : std_logic_vector(7 downto 0);
---signal crossbar_out_port10 : std_logic_vector(7 downto 0);
---signal crossbar_out_port11 : std_logic_vector(7 downto 0);
---signal crossbar_out_port12 : std_logic_vector(7 downto 0);
---signal crossbar_out_port13 : std_logic_vector(7 downto 0);
---signal crossbar_out_port14 : std_logic_vector(7 downto 0);
---signal crossbar_out_port15 : std_logic_vector(7 downto 0);
---signal crossbar_out_port16 : std_logic_vector(7 downto 0);
+
 
 signal crossbar_in_pulse  : std_logic_vector(number_of_ports downto 1);
---signal crossbar_in_pulse1 : std_logic;
---signal crossbar_in_pulse2 : std_logic;
---signal crossbar_in_pulse3 : std_logic;
---signal crossbar_in_pulse4 : std_logic;
---signal crossbar_in_pulse5 : std_logic;
---signal crossbar_in_pulse6 : std_logic;
---signal crossbar_in_pulse7 : std_logic;
---signal crossbar_in_pulse8 : std_logic;
---signal crossbar_in_pulse9 : std_logic;
---signal crossbar_in_pulse10 : std_logic;
---signal crossbar_in_pulse11 : std_logic;
---signal crossbar_in_pulse12 : std_logic;
---signal crossbar_in_pulse13 : std_logic;
---signal crossbar_in_pulse14 : std_logic;
---signal crossbar_in_pulse15 : std_logic;
---signal crossbar_in_pulse16 : std_logic;
+
 
 signal crossbar_out_pulse  : std_logic_vector(number_of_ports downto 1);
---signal crossbar_out_pulse1 : std_logic;
---signal crossbar_out_pulse2 : std_logic;
---signal crossbar_out_pulse3 : std_logic;
---signal crossbar_out_pulse4 : std_logic;
---signal crossbar_out_pulse5 : std_logic;
---signal crossbar_out_pulse6 : std_logic;
---signal crossbar_out_pulse7 : std_logic;
---signal crossbar_out_pulse8 : std_logic;
---signal crossbar_out_pulse9 : std_logic;
---signal crossbar_out_pulse10 : std_logic;
---signal crossbar_out_pulse11 : std_logic;
---signal crossbar_out_pulse12 : std_logic;
---signal crossbar_out_pulse13 : std_logic;
---signal crossbar_out_pulse14 : std_logic;
---signal crossbar_out_pulse15 : std_logic;
---signal crossbar_out_pulse16 : std_logic;
+
 
 
@@ -428,5 +329,5 @@
 --j=number_of_ports*(i-1);
 PORTx4_INPUT_PORT_MODULE: INPUT_PORT_MODULE 
-GENERIC MAP(number_of_ports =>4,Port_num=>i)
+GENERIC MAP(number_of_ports =>number_of_ports,Port_num=>i)
 PORT MAP(
    data_in => Port_in(i),
@@ -6281,4 +6182,6 @@
 GENERIC MAP(number_of_crossbar_ports =>2)
   PORT MAP(
+		reset => reset,
+     clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6327,5 +6230,7 @@
 GENERIC MAP(number_of_crossbar_ports =>3)
   PORT MAP(
-   Port1_in => crossbar_in_port(1),
+		reset => reset,
+     clk => clk, 
+	Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
    Port3_in => crossbar_in_port(3),
@@ -6375,4 +6280,6 @@
 GENERIC MAP(number_of_crossbar_ports =>4)
   PORT MAP(
+		reset => reset,
+     clk => clk,  
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6425,4 +6332,6 @@
 GENERIC MAP(number_of_crossbar_ports =>5)
   PORT MAP(
+		reset => reset,
+     clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6477,4 +6386,7 @@
 GENERIC MAP(number_of_crossbar_ports =>6)
   PORT MAP(
+  
+ 		reset => reset,
+     clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6531,4 +6443,6 @@
 GENERIC MAP(number_of_crossbar_ports =>7)
   PORT MAP(
+		reset => reset,
+     clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6587,4 +6501,6 @@
 GENERIC MAP(number_of_crossbar_ports =>8)
   PORT MAP(
+    reset => reset,
+   clk =>clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6645,4 +6561,6 @@
 GENERIC MAP(number_of_crossbar_ports =>9)
   PORT MAP(
+		reset => reset,
+     clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6705,4 +6623,6 @@
 GENERIC MAP(number_of_crossbar_ports =>10)
   PORT MAP(
+	reset => reset,
+   clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6767,4 +6687,6 @@
 GENERIC MAP(number_of_crossbar_ports =>11)
   PORT MAP(
+	reset => reset,
+   clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6831,4 +6753,6 @@
 GENERIC MAP(number_of_crossbar_ports =>12)
   PORT MAP(
+	reset => reset,
+   clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6897,4 +6821,6 @@
 GENERIC MAP(number_of_crossbar_ports =>13)
   PORT MAP(
+	reset => reset,
+   clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -6965,4 +6891,6 @@
 GENERIC MAP(number_of_crossbar_ports =>14)
   PORT MAP(
+	reset => reset,
+   clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -7035,4 +6963,6 @@
 GENERIC MAP(number_of_crossbar_ports =>15)
   PORT MAP(
+	reset => reset,
+   clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
@@ -7107,4 +7037,6 @@
 GENERIC MAP(number_of_crossbar_ports =>16)
   PORT MAP(
+	reset => reset,
+   clk => clk,
    Port1_in => crossbar_in_port(1),
    Port2_in => crossbar_in_port(2),
Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Scheduler.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Scheduler.vhd	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Scheduler.vhd	(revision 65)
@@ -42,9 +42,10 @@
 		
 architecture Behavioral of Scheduler is
+-- signaux pour le pipeline;
+signal Request_latch :STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1):=(others=>'0');
+signal Fifo_full_latch : STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'0');
+signal priority_rotation_latch : STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'1');
+         
 -- composants du scheduler
-
--- composants du scheduler
-
-
 COMPONENT Scheduler2_2
    PORT(
@@ -225,4 +226,46 @@
   Inst_Scheduler2_2 : Scheduler2_2
    PORT MAP(
+     Request => Request_latch, 
+     Fifo_full => Fifo_full_latch,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation_latch,
+     port_grant =>port_grant);
+end generate scheduler2x2; 
+
+--======================scheduler 3 ports=======================
+
+scheduler3x3 : if number_of_ports = 3 generate
+
+  Inst_Scheduler3_3 : Scheduler3_3
+   PORT MAP(
+     Request => Request_latch, 
+     Fifo_full => Fifo_full_latch,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation_latch,
+     port_grant =>port_grant);
+end generate scheduler3x3; 
+
+--======================scheduler 4 ports=======================
+
+scheduler4x4 : if number_of_ports = 4 generate
+
+  Inst_Scheduler4_4 : Scheduler4_4
+   PORT MAP(
+     Request => Request_latch, 
+     Fifo_full => Fifo_full_latch,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation_latch,
+     port_grant =>port_grant);
+end generate scheduler4x4; 
+
+--======================scheduler 5 ports=======================
+
+scheduler5x5 : if number_of_ports = 5 generate
+
+  Inst_Scheduler5_5 : Scheduler5_5
+   PORT MAP(
      Request => Request, 
      Fifo_full => Fifo_full,
@@ -231,11 +274,67 @@
      priority_rotation =>priority_rotation,
      port_grant =>port_grant);
-end generate scheduler2x2; 
-
---======================scheduler 3 ports=======================
-
-scheduler3x3 : if number_of_ports = 3 generate
-
-  Inst_Scheduler3_3 : Scheduler3_3
+end generate scheduler5x5; 
+
+--======================scheduler 6 ports=======================
+
+scheduler6x6 : if number_of_ports = 6 generate
+
+  Inst_Scheduler6_6 : Scheduler6_6
+   PORT MAP(
+     Request => Request_latch, 
+     Fifo_full => Fifo_full_latch,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation_latch,
+     port_grant =>port_grant);
+end generate scheduler6x6; 
+
+--======================scheduler 7 ports=======================
+
+scheduler7x7 : if number_of_ports = 7 generate
+
+  Inst_Scheduler7_7 : Scheduler7_7
+   PORT MAP(
+     Request => Request_latch, 
+     Fifo_full => Fifo_full_latch,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation_latch,
+     port_grant =>port_grant);
+end generate scheduler7x7; 
+
+--======================scheduler 8 ports=======================
+
+scheduler8x8 : if number_of_ports = 8 generate
+
+  Inst_Scheduler8_8 : Scheduler8_8
+   PORT MAP(
+     Request => Request_latch, 
+     Fifo_full => Fifo_full_latch,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation_latch,
+     port_grant =>port_grant);
+end generate scheduler8x8; 
+
+--======================scheduler 9 ports=======================
+
+scheduler9x9 : if number_of_ports = 9 generate
+
+  Inst_Scheduler9_9 : Scheduler9_9
+   PORT MAP(
+     Request => Request_latch, 
+     Fifo_full => Fifo_full_latch,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation_latch,
+     port_grant =>port_grant);
+end generate scheduler9x9; 
+
+--======================scheduler 10 ports=======================
+
+scheduler10x10 : if number_of_ports = 10 generate
+
+  Inst_Scheduler10_10 : Scheduler10_10
    PORT MAP(
      Request => Request, 
@@ -245,11 +344,11 @@
      priority_rotation =>priority_rotation,
      port_grant =>port_grant);
-end generate scheduler3x3; 
-
---======================scheduler 4 ports=======================
-
-scheduler4x4 : if number_of_ports = 4 generate
-
-  Inst_Scheduler4_4 : Scheduler4_4
+end generate scheduler10x10; 
+
+--======================scheduler 11 ports=======================
+
+scheduler11x11 : if number_of_ports = 11 generate
+
+  Inst_Scheduler11_11 : Scheduler11_11
    PORT MAP(
      Request => Request, 
@@ -259,102 +358,4 @@
      priority_rotation =>priority_rotation,
      port_grant =>port_grant);
-end generate scheduler4x4; 
-
---======================scheduler 5 ports=======================
-
-scheduler5x5 : if number_of_ports = 5 generate
-
-  Inst_Scheduler5_5 : Scheduler5_5
-   PORT MAP(
-     Request => Request, 
-     Fifo_full => Fifo_full,
-     clk => clk ,
-     reset =>reset,
-     priority_rotation =>priority_rotation,
-     port_grant =>port_grant);
-end generate scheduler5x5; 
-
---======================scheduler 6 ports=======================
-
-scheduler6x6 : if number_of_ports = 6 generate
-
-  Inst_Scheduler6_6 : Scheduler6_6
-   PORT MAP(
-     Request => Request, 
-     Fifo_full => Fifo_full,
-     clk => clk ,
-     reset =>reset,
-     priority_rotation =>priority_rotation,
-     port_grant =>port_grant);
-end generate scheduler6x6; 
-
---======================scheduler 7 ports=======================
-
-scheduler7x7 : if number_of_ports = 7 generate
-
-  Inst_Scheduler7_7 : Scheduler7_7
-   PORT MAP(
-     Request => Request, 
-     Fifo_full => Fifo_full,
-     clk => clk ,
-     reset =>reset,
-     priority_rotation =>priority_rotation,
-     port_grant =>port_grant);
-end generate scheduler7x7; 
-
---======================scheduler 8 ports=======================
-
-scheduler8x8 : if number_of_ports = 8 generate
-
-  Inst_Scheduler8_8 : Scheduler8_8
-   PORT MAP(
-     Request => Request, 
-     Fifo_full => Fifo_full,
-     clk => clk ,
-     reset =>reset,
-     priority_rotation =>priority_rotation,
-     port_grant =>port_grant);
-end generate scheduler8x8; 
-
---======================scheduler 9 ports=======================
-
-scheduler9x9 : if number_of_ports = 9 generate
-
-  Inst_Scheduler9_9 : Scheduler9_9
-   PORT MAP(
-     Request => Request, 
-     Fifo_full => Fifo_full,
-     clk => clk ,
-     reset =>reset,
-     priority_rotation =>priority_rotation,
-     port_grant =>port_grant);
-end generate scheduler9x9; 
-
---======================scheduler 10 ports=======================
-
-scheduler10x10 : if number_of_ports = 10 generate
-
-  Inst_Scheduler10_10 : Scheduler10_10
-   PORT MAP(
-     Request => Request, 
-     Fifo_full => Fifo_full,
-     clk => clk ,
-     reset =>reset,
-     priority_rotation =>priority_rotation,
-     port_grant =>port_grant);
-end generate scheduler10x10; 
-
---======================scheduler 11 ports=======================
-
-scheduler11x11 : if number_of_ports = 11 generate
-
-  Inst_Scheduler11_11 : Scheduler11_11
-   PORT MAP(
-     Request => Request, 
-     Fifo_full => Fifo_full,
-     clk => clk ,
-     reset =>reset,
-     priority_rotation =>priority_rotation,
-     port_grant =>port_grant);
 end generate scheduler11x11; 
 
@@ -365,9 +366,9 @@
   Inst_Scheduler12_12 : Scheduler12_12
    PORT MAP(
-     Request => Request, 
-     Fifo_full => Fifo_full,
-     clk => clk ,
-     reset =>reset,
-     priority_rotation =>priority_rotation,
+     Request => Request_latch, 
+     Fifo_full => Fifo_full_latch,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation_latch,
      port_grant =>port_grant);
 end generate scheduler12x12; 
@@ -379,9 +380,9 @@
   Inst_Scheduler13_13 : Scheduler13_13
    PORT MAP(
-     Request => Request, 
-     Fifo_full => Fifo_full,
-     clk => clk ,
-     reset =>reset,
-     priority_rotation =>priority_rotation,
+     Request => Request_latch, 
+     Fifo_full => Fifo_full_latch,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation_latch,
      port_grant =>port_grant);
 end generate scheduler13x13; 
@@ -393,9 +394,9 @@
   Inst_Scheduler14_14 : Scheduler14_14
    PORT MAP(
-     Request => Request, 
-     Fifo_full => Fifo_full,
-     clk => clk ,
-     reset =>reset,
-     priority_rotation =>priority_rotation,
+     Request => Request_latch, 
+     Fifo_full => Fifo_full_latch,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation_latch,
      port_grant =>port_grant);
 end generate scheduler14x14; 
@@ -407,9 +408,9 @@
   Inst_Scheduler15_15 : Scheduler15_15
    PORT MAP(
-     Request => Request, 
-     Fifo_full => Fifo_full,
-     clk => clk ,
-     reset =>reset,
-     priority_rotation =>priority_rotation,
+     Request => Request_latch, 
+     Fifo_full => Fifo_full_latch,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation_latch,
      port_grant =>port_grant);
 end generate scheduler15x15; 
@@ -421,12 +422,25 @@
   Inst_Scheduler16_16 : Scheduler16_16
    PORT MAP(
-     Request => Request, 
-     Fifo_full => Fifo_full,
-     clk => clk ,
-     reset =>reset,
-     priority_rotation =>priority_rotation,
+     Request => Request_latch, 
+     Fifo_full => Fifo_full_latch,
+     clk => clk ,
+     reset =>reset,
+     priority_rotation =>priority_rotation_latch,
      port_grant =>port_grant);
 end generate scheduler16x16; 
-
+Sched:process (clk,reset)
+begin
+if rising_edge(clk) then
+	if reset='1' then
+		request_latch<=(others=>'0');
+		Fifo_full_latch<=(others=>'0');
+		priority_rotation_latch<=(others=>'1');
+	else
+		request_latch<=request;
+		Fifo_full_latch<=fifo_full;
+		priority_rotation_latch<=priority_rotation;
+	end if;
+end if;
+end process sched;
 end Behavioral;
 
Index: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/proto_send.vhd
===================================================================
--- PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/proto_send.vhd	(revision 45)
+++ PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/proto_send.vhd	(revision 65)
@@ -50,4 +50,5 @@
  signal sfifo_in : std_logic_vector(Word-1 downto 0);
  signal spush : std_logic:='0';
+ signal err : std_logic_vector(Word-1 downto 0):=(others =>'0');
 begin
 
@@ -57,5 +58,5 @@
 	if reset='1' then 
 				 etsnd<=s_head;
-				 
+				 err<=(others =>'0');
 				else  
 						if rising_edge(clk) then -- le process s'exécute sur chaque front 
@@ -79,7 +80,14 @@
 							i:=i+1;
 							dlen:=to_integer(unsigned(mem(i)));
-							spush<='1';
-							snd_comp<='0';
-							etsnd<=s_data;
+							if dlen > 2 then
+								spush<='1';
+								snd_comp<='0';
+								etsnd<=s_data;
+							else
+								spush<='1';
+								snd_comp<='1';
+								etsnd<=s_end;
+							
+							end if;
 						when s_len2 =>
 							snd_comp<='0';
@@ -87,8 +95,9 @@
 								
 						when s_data  =>
-								if fifo_full='0' then
+								if (fifo_full='0') and (dlen >2) then 
 								i:=i+1;
 								sfifo_in<=mem(i);
-									if i=dlen-2 then
+									if i>=dlen-1 then --les indices 0 et 1 étant réservés
+															--les données sont comptés à partir de 2
 										etsnd<=s_end;
 										snd_comp<='1';
