Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/DMA_ARBITER.ucf =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/DMA_ARBITER.ucf (revision 66) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/DMA_ARBITER.ucf (revision 66) @@ -0,0 +1,4 @@ + +#Created by Constraints Editor (xc6slx45-csg324-3) - 2013/03/21 +NET "clk" TNM_NET = clk; +TIMESPEC TS_clk = PERIOD "clk" 10 ns HIGH 50%; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/Hold_FSM.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/Hold_FSM.vhd (revision 66) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/Hold_FSM.vhd (revision 66) @@ -0,0 +1,122 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: GAMOM Roland Christian +-- +-- Create Date: 17:38:35 04/20/2013 +-- Design Name: +-- Module Name: Hold_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Hold_FSM is + Port ( Hold_Req : in STD_LOGIC; + ram_busy : in STD_LOGIC; + Clk : in STD_LOGIC; + Reset : in STD_LOGIC; + Ramsel : out STD_LOGIC; + Hold_Ack : out STD_LOGIC); +end Hold_FSM; + +architecture Behavioral of Hold_FSM is +type typ_Hld is (Ht_Lock,Core_Lock,Ht_free); +signal Holdstate,Hold_st :typ_hld; + signal Ram_sel :std_logic:='0'; + signal front_Rbusy,front_hReq:std_logic:='0'; +begin + +hold_sync:process (clk,reset) + begin + if rising_edge(clk) then + + + end if; + end process hold_sync; + Ramsel_state:process(clk,reset)--,HoldState,Hold_Req,ram_Busy,Front_HReq,Front_RBusy) + + begin + + if rising_edge(clk) then + if reset='1' then + HolDState<=Ht_free; + else +-- HolDState<=Hold_St; +-- Hold_St<=HoldState; + case HoldState is + when Ht_free => + if Hold_Req='1' and ram_busy='0' then + HolDState <=Core_lock; + elsif Hold_Req='0' and ram_busy='1' then + HoldState <=HT_lock; + else + HoldState <=HT_free; + end if; + when Ht_lock => + if Hold_Req='0' and ram_busy='0' then + HoldState <=HT_free; + elsif Hold_Req='1' and Ram_busy='0' then + HoldState <=Core_lock; + else + HoldState <=HT_lock; + end if; + + When Core_lock => + If Hold_Req='0' and Ram_busy='0' then + HoldState <=HT_free; + elsif Hold_Req='0' and Ram_busy='1' then + HoldState <=HT_lock; + else + HoldState <=Core_lock; + end if; + end case ; + end if; + end if; + + end process; + + Ramsel_val:process(HoldState,Hold_Req,Ram_Busy) + + begin + case HoldState is + when Ht_free => + ram_sel<='0'; + Hold_Ack<='0'; + when Ht_Lock => + ram_sel<='0'; + Hold_Ack<='0'; + when Core_lock => + Ram_sel <='1'; + Hold_Ack<='1'; + end case; + if Hold_Req= not(front_HReq) then + front_HReq<= not front_HReq; +end if; + +if Ram_busy= not (front_RBusy) then + front_RBusy<= not front_RBusy; +end if; + end process ramsel_val; + Ramsel<=Ram_sel; +--======================================================================= +end Behavioral; + Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/SWITCH_GEN.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/SWITCH_GEN.prj (revision 66) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/SWITCH_GEN.prj (revision 66) @@ -0,0 +1,25 @@ +vhdl NocLib "../SWITCH_GENERIC_16_16/CoreTypes.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/RAM_256.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/Arbiter.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/Crossbit.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/Scheduler.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/Crossbar.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/SWITCH_GEN.vhd" Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/SWITCH_GEN.ucf =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/SWITCH_GEN.ucf (revision 66) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/SWITCH_GEN.ucf (revision 66) @@ -0,0 +1,4 @@ + +#Created by Constraints Editor (xc6slx45-csg324-3) - 2013/01/04 +NET "clk" TNM_NET = clk; +TIMESPEC TS_clk = PERIOD "clk" 10 ns HIGH 50%; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/SWITCH_GENERIQUE.prj =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/SWITCH_GENERIQUE.prj (revision 66) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/SWITCH_GENERIQUE.prj (revision 66) @@ -0,0 +1,25 @@ +vhdl NocLib "../SWITCH_GENERIC_16_16/CoreTypes.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/RAM_256.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/Arbiter.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER9_9.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER8_8.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER7_7.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER6_6.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER5_5.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER4_4.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER3_3.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER2_2.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER16_16.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER15_15.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER14_14.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER13_13.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER12_12.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER11_11.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/SCHEDULER10_10.VHD" +vhdl NocLib "../SWITCH_GENERIC_16_16/FIFO_256_FWFT.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/Crossbit.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/Scheduler.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/OUTPUT_PORT_MODULE.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/INPUT_PORT_MODULE.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/Crossbar.vhd" +vhdl NocLib "../SWITCH_GENERIC_16_16/SWITCH_GENERIQUE.vhd" Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/mpi_test.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/mpi_test.vhd (revision 66) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/mpi_test.vhd (revision 66) @@ -0,0 +1,89 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 07:29:14 03/26/2013 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/mpi_test.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: MultiMPITest +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY mpi_test IS +END mpi_test; + +ARCHITECTURE behavior OF mpi_test IS + signal clk,reset : std_logic:='0'; + signal result : std_logic_vector(7 downto 0); + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT MultiMPITest + + port (clkm : in std_logic; + reset : in std_logic; + result : out std_logic_vector(7 downto 0)); + + END COMPONENT; + + -- No clocks detected in port list. Replace below with + -- appropriate port name + + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: MultiMPITest PORT MAP ( + clkm=>clk, + reset=>reset, + result=>result + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + reset<='1'; + wait for clk_period*10; + reset<='0'; + wait ; + + -- insert stimulus here + + wait; + end process; + +END; Index: /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/test_DMA.vhd =================================================================== --- /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/test_DMA.vhd (revision 66) +++ /PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v0.03/test_DMA.vhd (revision 66) @@ -0,0 +1,295 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 14:37:10 03/18/2013 +-- Design Name: +-- Module Name: C:/Core MPI/CORE_MPI/test_DMA.vhd +-- Project Name: MPI_CORE_COMPONENTS +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: DMA_ARBITER +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY test_DMA IS +END test_DMA; + +ARCHITECTURE behavior OF test_DMA IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT DMA_ARBITER + PORT( + dma_rd_request : IN std_logic_vector(3 downto 0); + data_wr_in : IN std_logic_vector(7 downto 0); + data_rd_out : OUT std_logic_vector(7 downto 0); + address_rd : IN std_logic_vector(15 downto 0); + address_wr : IN std_logic_vector(15 downto 0); + address_out_wr : OUT std_logic_vector(15 downto 0); + address_out_rd : OUT std_logic_vector(15 downto 0); + ram_en : OUT std_logic; + ram_we : OUT std_logic; + data_wr_mem : OUT std_logic_vector(7 downto 0); + data_rd_mem : IN std_logic_vector(7 downto 0); + dma_wr_grant : OUT std_logic_vector(3 downto 0); + hold_req : OUT std_logic; + hold_ack : IN std_logic; + clk : IN std_logic; + reset : IN std_logic; + dma_rd_grant : OUT std_logic_vector(3 downto 0); + dma_wr_request : IN std_logic_vector(3 downto 0) + ); + END COMPONENT; + +COMPONENT RAM_v + generic (width : positive;size :positive); + PORT( + clka : IN std_logic; + clkb : IN std_logic; + wea : IN std_logic; + ena : IN std_logic; + enb : IN std_logic; + addra : IN std_logic_vector; + addrb : IN std_logic_vector; + dia : IN std_logic_vector; + dob : OUT std_logic_vector + ); + END COMPONENT; + --Inputs + signal dma_rd_request : std_logic_vector(3 downto 0) := (others => '0'); + signal data_wr_in : std_logic_vector(7 downto 0) := (others => '0'); + signal address_rd : std_logic_vector(15 downto 0) := (others => '0'); + signal address_wr : std_logic_vector(15 downto 0) := (others => '0'); + signal data_rd_mem : std_logic_vector(7 downto 0) := (others => '0'); + signal hold_ack : std_logic := '0'; + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal dma_wr_request : std_logic_vector(3 downto 0) := (others => '0'); + + --Outputs + signal data_rd_out : std_logic_vector(7 downto 0); + signal address_out_wr : std_logic_vector(15 downto 0); + signal address_out_rd : std_logic_vector(15 downto 0); + signal ram_en : std_logic; + signal ram_we : std_logic; + signal data_wr_mem : std_logic_vector(7 downto 0); + signal dma_wr_grant : std_logic_vector(3 downto 0); + signal hold_req : std_logic; + signal dma_rd_grant : std_logic_vector(3 downto 0); + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: DMA_ARBITER PORT MAP ( + dma_rd_request => dma_rd_request, + data_wr_in => data_wr_in, + data_rd_out => data_rd_out, + address_rd => address_rd, + address_wr => address_wr, + address_out_wr => address_out_wr, + address_out_rd => address_out_rd, + ram_en => ram_en, + ram_we => ram_we, + data_wr_mem => data_wr_mem, + data_rd_mem => data_rd_mem, + dma_wr_grant => dma_wr_grant, + hold_req => hold_req, + hold_ack => hold_ack, + clk => clk, + reset => reset, + dma_rd_grant => dma_rd_grant, + dma_wr_request => dma_wr_request + ); + +Inst_RAM_v: RAM_v generic map(width=>8,size=>16) + PORT MAP( + clka =>clk, + clkb => clk, + wea => ram_we, + ena => ram_en, + enb => ram_en, + addra => address_out_wr, + addrb =>address_out_rd, + dia => data_wr_mem, + dob => data_rd_mem + ); + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + reset_proc: process + begin + -- hold reset state for 100 ns. + reset <='1'; + wait for 100 ns; + reset<='0'; + wait for clk_period*10; + + -- insert stimulus here + + wait; + end process; + + stim_proc: process (clk,reset) + variable i,j,k,l : std_logic_vector(15 downto 0); + variable x: integer ; --indique le temps à partir duquel chaque + --permet de faire des requêtes DMA et de les valider + begin + if rising_edge(clk) then + if reset ='1' then + x:=0; + else + x:=x+1; + if x>=1 and x<=20 then + dma_rd_request<="0001"; + elsif x>=21 and x<=40 then + dma_rd_request<="0011"; + elsif x>=41 and x<=60 then + dma_rd_request<="0010"; + elsif x>=61 and x<=80 then + dma_rd_request<="0110"; + elsif x>=81 and x<=100 then + dma_rd_request<="0100"; + elsif x>=61 and x<=80 then + dma_rd_request<="1100"; + elsif x>=101 and x<=120 then + dma_rd_request<="1101"; + elsif x>=121 and x<=140 then + dma_rd_request<="1001"; + elsif x>=141 and x<=160 then + dma_rd_request<="1000"; + elsif x>=161 and x<=180 then + dma_rd_request<="0000"; + elsif x>=181 and x<=200 then + dma_rd_request<="0111"; + elsif x>=181 and x<=200 then + dma_rd_request<="1111"; + elsif x>=181 and x<=200 then + dma_rd_request<="1110"; + else + x:=0; + + end if; + + end if; + end if; + end process; +stim2_proc: process (clk,reset) + variable i,j,k,l : std_logic_vector(15 downto 0); + variable x: integer ; --indique le temps à partir duquel chaque + --permet de faire des requêtes DMA et de les valider + begin + if rising_edge(clk) then + if reset ='1' then + x:=0; + else + x:=x+1; + if x>=1 and x<=10 then + dma_wr_request<="0001"; + elsif x>=11 and x<=20 then + dma_wr_request<="0011"; + elsif x>=21 and x<=30 then + dma_wr_request<="0010"; + elsif x>=31 and x<=40 then + dma_wr_request<="0110"; + elsif x>=41 and x<=50 then + dma_wr_request<="0100"; + elsif x>=51 and x<=60 then + dma_wr_request<="1100"; + elsif x>=61 and x<=80 then + dma_wr_request<="1101"; + elsif x>=81 and x<=90 then + dma_wr_request<="1001"; + elsif x>=91 and x<=100 then + dma_wr_request<="1000"; + elsif x>=101 and x<=110 then + dma_wr_request<="0000"; + elsif x>=111 and x<=120 then + dma_wr_request<="0111"; + elsif x>=121 and x<=130 then + dma_wr_request<="1111"; + elsif x>=131 and x<=200 then + dma_wr_request<="1110"; + else + x:=0; + + end if; + + end if; + end if; + end process; +liredat:process (dma_rd_grant) +begin + + +if dma_rd_grant="0001" then +address_rd<=x"0000"; +elsif dma_rd_grant="0010" then +address_rd<=x"0002"; +elsif dma_rd_grant="0100" then +address_rd<=x"0004"; +elsif dma_rd_grant="1000" then +address_rd<=x"0006"; +else + + address_rd<=x"0000"; +end if; + +end process; +ecriredat:process (dma_wr_grant) +begin + + +if dma_wr_grant="0001" then +address_wr<=x"0000"; +data_wr_in<=x"0a"; +elsif dma_rd_grant="0010" then +address_wr<=x"0002"; +data_wr_in<=x"20"; +elsif dma_rd_grant="0100" then +address_wr<=x"0004"; +data_wr_in<=x"a0"; +elsif dma_rd_grant="1000" then +address_wr<=x"0006"; +data_wr_in<=x"0F"; +else + + address_wr<=x"0000"; + +end if; + +end process; +Hold_ack<=Hold_req; -- toujours autoriser la gestion de la mémoire par le DMA + +END;