MultiMPITest Project Status (12/09/2012 - 19:46:00)
Project File: | MPI_CORE_COMPONENTS.xise | Parser Errors: | No Errors
Module Name: | MPI_CORE_SCHEDULER | Implementation State: | Placed and Routed
Target Device: | xc6slx45-3csg324 | Errors: |
Product Version: | ISE 12.3 | Warnings: |
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: | System Settings | Final Timing Score: |

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 2 | 4,800 | 1% |
Number used as Flip Flops | 2 |  |  |
Number used as Latches | 0 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 0 |  |  |
Number of Slice LUTs | 9 | 2,400 | 1% |
Number used as logic | 9 | 2,400 | 1% |
Number using O6 output only | 4 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 5 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 0 | 1,200 | 0% |
Number of occupied Slices | 5 | 600 | 1% |
Number of LUT Flip Flop pairs used | 9 |  |  |
Number with an unused Flip Flop | 7 | 9 | 77% |
Number with an unused LUT | 0 | 9 | 0% |
Number of fully used LUT-FF pairs | 2 | 9 | 22% |
Number of unique control sets | 2 |  |  |
Number of slice register sites lost to control set restrictions | 14 | 4,800 | 1% |
Number of bonded IOBs | 35 | 102 | 34% |
Number of RAMB16BWERs | 0 | 12 | 0% |
Number of RAMB8BWERs | 0 | 24 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 1 | 16 | 6% |
Number used as BUFGs | 1 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% |
Number of ILOGIC2/ISERDES2s | 0 | 200 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% |
Number of OLOGIC2/OSERDES2s | 0 | 200 | 0% |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 0 | 8 | 0% |
Number of ICAPs | 0 | 1 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 0 | 2 | 0% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 1.39 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Sat 8. Dec 00:53:05 2012 |  |  |
Translation Report | Current | Sat 8. Dec 00:53:09 2012 |  |  |
Map Report | Current | Sat 8. Dec 00:53:27 2012 |  |  |
Place and Route Report | Current | Sat 8. Dec 00:53:38 2012 |  |  |
CPLD Fitter Report (Text) |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | Sat 8. Dec 00:53:43 2012 |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | Fri 7. Dec 14:52:37 2012
WebTalk Report | Out of Date | Sat 8. Dec 15:45:26 2012
WebTalk Log File | Out of Date | Sat 8. Dec 15:45:32 2012

Date Generated: 12/09/2012 - 19:46:00