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-- Company: 
-- Engineer:
--
-- Create Date:   07:29:14 03/26/2013
-- Design Name:   
-- Module Name:   C:/Core MPI/CORE_MPI/mpi_test.vhd
-- Project Name:  MPI_CORE_COMPONENTS
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: MultiMPITest
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY mpi_test IS
END mpi_test;
 
ARCHITECTURE behavior OF mpi_test IS 
 signal clk,reset : std_logic:='0';
 signal result : std_logic_vector(7 downto 0);
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT MultiMPITest
    
	 port (clkm : in std_logic;
		reset : in std_logic;
		result : out std_logic_vector(7 downto 0));
     
    END COMPONENT;
    
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: MultiMPITest PORT MAP (
		clkm=>clk,
		reset=>reset,
		result=>result
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      reset<='1';
      wait for clk_period*10;
		reset<='0';
      wait ;

      -- insert stimulus here 

      wait;
   end process;

END;
