DMA_ARBITER Project Status (04/03/2013 - 19:35:29)
Project File: | MPI_CORE_COMPONENTS.xise | Parser Errors: | No Errors
Module Name: | MultiMPITest | Implementation State: | Placed and Routed
Target Device: | xc6slx45-3csg324 | Errors: | No Errors
Product Version: | ISE 12.3 | Warnings: | 3132 Warnings (78 new)
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: | X 1 Failing Constraint
Environment: | System Settings | Final Timing Score: | 3412527 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 2,815 | 54,576 | 5% |
Number used as Flip Flops | 2,208 |  |  |
Number used as Latches | 607 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 0 |  |  |
Number of Slice LUTs | 12,079 | 27,288 | 44% |
Number used as logic | 6,942 | 27,288 | 25% |
Number using O6 output only | 5,481 |  |  |
Number using O5 output only | 409 |  |  |
Number using O5 and O6 | 1,052 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 5,088 | 6,408 | 79% |
Number used as Dual Port RAM | 5,080 |  |  |
Number using O6 output only | 5,080 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 0 |  |  |
Number used as Single Port RAM | 8 |  |  |
Number using O6 output only | 8 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 0 |  |  |
Number used as Shift Register | 0 |  |  |
Number used exclusively as route-thrus | 49 |  |  |
Number with same-slice register load | 1 |  |  |
Number with same-slice carry load | 48 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 3,785 | 6,822 | 55% |
Number of LUT Flip Flop pairs used | 12,380 |  |  |
Number with an unused Flip Flop | 9,722 | 12,380 | 78% |
Number with an unused LUT | 301 | 12,380 | 2% |
Number of fully used LUT-FF pairs | 2,357 | 12,380 | 19% |
Number of unique control sets | 855 |  |  |
Number of slice register sites lost to control set restrictions | 3,313 | 54,576 | 6% |
Number of bonded IOBs | 10 | 218 | 4% |
Number of RAMB16BWERs | 0 | 116 | 0% |
Number of RAMB8BWERs | 3 | 232 | 1% |
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 4 | 16 | 25% |
Number used as BUFGs | 4 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 8 | 0% |
Number of ILOGIC2/ISERDES2s | 0 | 376 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 376 | 0% |
Number of OLOGIC2/OSERDES2s | 0 | 376 | 0% |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 256 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 0 | 58 | 0% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 0 | 4 | 0% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 5.66 |  |  |

Performance Summary | [-]
Final Timing Score: | 3412527 (Setup: 3412527, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | X 1 Failing Constraint |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Wed 3. Apr 19:05:13 2013 | 0 | 1211 Warnings (3 new) | 433 Infos (10 new)
Translation Report | Current | Wed 3. Apr 19:05:27 2013 | 0 | 102 Warnings (0 new) | 0
Map Report | Current | Wed 3. Apr 19:13:28 2013 | 0 | 967 Warnings (74 new) | 8 Infos (0 new)
Place and Route Report | Current | Wed 3. Apr 19:34:53 2013 | 0 | 852 Warnings (1 new) | 0
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | Wed 3. Apr 19:35:24 2013 | 0 | 0 | 2 Infos (0 new)
Bitgen Report | Out of Date | Wed 19. Dec 13:42:44 2012 | 0 | 1106 Warnings (565 new) | 0

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | Wed 3. Apr 19:01:58 2013
Post-Map Static Timing Report | Out of Date | Wed 19. Dec 17:30:44 2012
WebTalk Report | Out of Date | Mon 18. Mar 11:20:20 2013
WebTalk Log File | Out of Date | Mon 18. Mar 11:20:25 2013

Date Generated: 04/03/2013 - 19:35:29