Index: /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/CoreTypes.vhd
===================================================================
--- /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/CoreTypes.vhd	(revision 68)
+++ /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/CoreTypes.vhd	(revision 69)
@@ -23,5 +23,6 @@
 CONSTANT CORE_WPOST_ADR : natural := CORE_BASE_ADR+556;
 CONSTANT CORE_WWAIT_ADR : natural := CORE_BASE_ADR+566;
-CONSTANT CORE_Rank2port_BASE :NATURAL:=32;
+CONSTANT CORE_SPAWN_ADR : natural := CORE_BASE_ADR+576;
+CONSTANT CORE_Rank2port_BASE :NATURAL:=52;
 CONSTANT CORE_RANK_ADR : NATURAL:=CORE_BASE_ADR+CORE_Rank2Port_Base;
 CONSTANT WIN0_ADR :natural :=4;
@@ -53,4 +54,5 @@
 		IsMain : std_logic; -- indique si la librairie est principal
 		Rank : natural range 0 to 16; --donne le rang du processus courant
+		Spawned: std_logic; --indique que ce module a été activé par la bibliothèque
 end record;
 
@@ -284,5 +286,5 @@
 
 function image(L: std_logic) return String is
-variable bit_image: String(1 to 1) := std_logic'image(L);
+variable bit_image: String(1 to 3) := std_logic'image(L);
 begin
 return(bit_image(1 to 1));
Index: /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/GENERIC_16_16.gise
===================================================================
--- /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/GENERIC_16_16.gise	(revision 68)
+++ /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/GENERIC_16_16.gise	(revision 69)
@@ -29,5 +29,102 @@
   </files>
 
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1370435746" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1370435746">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1370435746" xil_pn:in_ck="9216248337673135807" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1370435746">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="../CORE_MPI/sim_fifo.vhd"/>
+      <outfile xil_pn:name="Arbiter.vhd"/>
+      <outfile xil_pn:name="C:/RomSwitch/testport5.vhd"/>
+      <outfile xil_pn:name="CoreTypes.vhd"/>
+      <outfile xil_pn:name="Crossbar.vhd"/>
+      <outfile xil_pn:name="Crossbit.vhd"/>
+      <outfile xil_pn:name="FIFO_256_FWFT.vhd"/>
+      <outfile xil_pn:name="FIFO_DP.vhd"/>
+      <outfile xil_pn:name="INPUT_PORT_MODULE.vhd"/>
+      <outfile xil_pn:name="OUTPUT_PORT_MODULE.vhd"/>
+      <outfile xil_pn:name="Proto_receiv.vhd"/>
+      <outfile xil_pn:name="RAM_256.vhd"/>
+      <outfile xil_pn:name="SCHEDULER10_10.VHD"/>
+      <outfile xil_pn:name="SCHEDULER11_11.VHD"/>
+      <outfile xil_pn:name="SCHEDULER12_12.VHD"/>
+      <outfile xil_pn:name="SCHEDULER13_13.VHD"/>
+      <outfile xil_pn:name="SCHEDULER14_14.VHD"/>
+      <outfile xil_pn:name="SCHEDULER15_15.VHD"/>
+      <outfile xil_pn:name="SCHEDULER16_16.VHD"/>
+      <outfile xil_pn:name="SCHEDULER2_2.VHD"/>
+      <outfile xil_pn:name="SCHEDULER3_3.VHD"/>
+      <outfile xil_pn:name="SCHEDULER4_4.VHD"/>
+      <outfile xil_pn:name="SCHEDULER5_5.VHD"/>
+      <outfile xil_pn:name="SCHEDULER6_6.VHD"/>
+      <outfile xil_pn:name="SCHEDULER7_7.VHD"/>
+      <outfile xil_pn:name="SCHEDULER8_8.VHD"/>
+      <outfile xil_pn:name="SCHEDULER9_9.VHD"/>
+      <outfile xil_pn:name="SWITCH_GEN.vhd"/>
+      <outfile xil_pn:name="SWITCH_GENERIQUE.vhd"/>
+      <outfile xil_pn:name="Scheduler.vhd"/>
+      <outfile xil_pn:name="conv.vhd"/>
+      <outfile xil_pn:name="proto_send.vhd"/>
+      <outfile xil_pn:name="stimuli1.vhd"/>
+      <outfile xil_pn:name="test_xbar_8x8.vhd"/>
+    </transform>
+    <transform xil_pn:end_ts="1370435946" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="1086089259624485161" xil_pn:start_ts="1370435946">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1370435946" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-661505819731779733" xil_pn:start_ts="1370435946">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1370435746" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="1089920306747347169" xil_pn:start_ts="1370435746">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1370435746" xil_pn:in_ck="9216248337673135807" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1370435746">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="../CORE_MPI/sim_fifo.vhd"/>
+      <outfile xil_pn:name="Arbiter.vhd"/>
+      <outfile xil_pn:name="C:/RomSwitch/testport5.vhd"/>
+      <outfile xil_pn:name="CoreTypes.vhd"/>
+      <outfile xil_pn:name="Crossbar.vhd"/>
+      <outfile xil_pn:name="Crossbit.vhd"/>
+      <outfile xil_pn:name="FIFO_256_FWFT.vhd"/>
+      <outfile xil_pn:name="FIFO_DP.vhd"/>
+      <outfile xil_pn:name="INPUT_PORT_MODULE.vhd"/>
+      <outfile xil_pn:name="OUTPUT_PORT_MODULE.vhd"/>
+      <outfile xil_pn:name="Proto_receiv.vhd"/>
+      <outfile xil_pn:name="RAM_256.vhd"/>
+      <outfile xil_pn:name="SCHEDULER10_10.VHD"/>
+      <outfile xil_pn:name="SCHEDULER11_11.VHD"/>
+      <outfile xil_pn:name="SCHEDULER12_12.VHD"/>
+      <outfile xil_pn:name="SCHEDULER13_13.VHD"/>
+      <outfile xil_pn:name="SCHEDULER14_14.VHD"/>
+      <outfile xil_pn:name="SCHEDULER15_15.VHD"/>
+      <outfile xil_pn:name="SCHEDULER16_16.VHD"/>
+      <outfile xil_pn:name="SCHEDULER2_2.VHD"/>
+      <outfile xil_pn:name="SCHEDULER3_3.VHD"/>
+      <outfile xil_pn:name="SCHEDULER4_4.VHD"/>
+      <outfile xil_pn:name="SCHEDULER5_5.VHD"/>
+      <outfile xil_pn:name="SCHEDULER6_6.VHD"/>
+      <outfile xil_pn:name="SCHEDULER7_7.VHD"/>
+      <outfile xil_pn:name="SCHEDULER8_8.VHD"/>
+      <outfile xil_pn:name="SCHEDULER9_9.VHD"/>
+      <outfile xil_pn:name="SWITCH_GEN.vhd"/>
+      <outfile xil_pn:name="SWITCH_GENERIQUE.vhd"/>
+      <outfile xil_pn:name="Scheduler.vhd"/>
+      <outfile xil_pn:name="conv.vhd"/>
+      <outfile xil_pn:name="proto_send.vhd"/>
+      <outfile xil_pn:name="stimuli1.vhd"/>
+      <outfile xil_pn:name="test_xbar_8x8.vhd"/>
+    </transform>
+    <transform xil_pn:end_ts="1370435977" xil_pn:in_ck="9216248337673135807" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-4512714324515926764" xil_pn:start_ts="1370435946">
+      <status xil_pn:value="FailedRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+  </transforms>
 
 </generated_project>
Index: /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/GENERIC_16_16.xise
===================================================================
--- /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/GENERIC_16_16.xise	(revision 68)
+++ /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/GENERIC_16_16.xise	(revision 69)
@@ -364,4 +364,5 @@
     <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
     <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -400,6 +401,6 @@
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/test_xbar_8x8" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.test_xbar_8x8" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.test_xbar_8x8" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
@@ -421,5 +422,5 @@
     <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.test_xbar_8x8" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.test_xbar_8x8" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -482,5 +483,5 @@
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|test_xbar_8x8|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="GENERIC_16_16" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
Index: /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/OUTPUT_PORT_MODULE.vhd
===================================================================
--- /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/OUTPUT_PORT_MODULE.vhd	(revision 68)
+++ /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/OUTPUT_PORT_MODULE.vhd	(revision 69)
@@ -15,13 +15,15 @@
 -- Dependencies: 
 --
--- Revision: 
+-- Revision: 07-08-2013
 -- Revision 0.01 - File Created
--- Additional Comments: 
+-- Additional Comments: Ajout d'un délai pour ignorer les paquets qui sont là depuis
+-- longtemps
 --
 ----------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+--use IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE ieee.numeric_std.ALL;
 Library NocLib;
 use NocLib.CoreTypes.all;
@@ -51,10 +53,23 @@
 	srst: IN std_logic;
 	wr_en: IN std_logic;
-	dout: OUT std_logic_VECTOR(Word-1 downto 0);
+	dout: out std_logic_VECTOR(Word-1 downto 0);
 	empty: OUT std_logic;
 	full: OUT std_logic);
 end component;
 --definition du type etat pour les fsm
-signal empty_signal : std_logic;	
+type typ_outfsm is (Idle,waiting,dropping,reading);
+type typ_receiv is (r_wait,r_head,r_len,r_glen,r_data,r_pulse,r_end);
+
+signal EtRec : typ_receiv;
+signal Et_out_fsm : typ_outfsm;
+signal fifo_empty : std_logic;	
+signal sw : std_logic:='0'; -- permet de positionner le mux sur les signaux internes
+signal tlimit : natural:=0; --permet de compter les impulsions de temps
+signal n : natural:=0; --utiliser pour la mae du tampon de sortie
+signal rcv_start :  std_logic; --début de la réception
+signal  rcv_ack : std_logic;   -- acquittement de la réception
+signal  rcv_comp :  std_logic; -- fin de la réception
+signal   spop,pop,rd_en,dat_avail :  std_logic:='0';
+signal  mem,fifo_out :  std_logic_vector(Word-1 downto 0); --variable tampon sans intérêt réel
 begin
 -- instantiation du FIFO_64
@@ -63,12 +78,169 @@
 			clk => clk,
 			din => data_in,
-			rd_en => rd_out_en,
+			rd_en => rd_en,
 			srst => reset,
 			wr_en => wr_en,
-			dout => data_out,
-			empty => empty_signal,
+			dout => fifo_out,
+			empty => fifo_empty,
 			full => fifo_full);
 			
-data_avalaible <= not empty_signal;
+
+outport_proc : process(clk,reset,fifo_empty)
+begin
+if rising_edge(clk) then
+if reset='1' then
+n<=0;
+Et_out_fsm<=Idle;
+else
+case(Et_out_fsm) is 
+
+when Idle => --idle
+	if fifo_empty = '0' then
+		Et_Out_fsm<=waiting;
+	end if;
+	tlimit<=0;
+	sw<='0';
+when reading =>
+if rd_out_en='0' then
+	Et_out_fsm<=Idle;
+end if;
+sw<='0';
+when waiting =>  --counting
+if rd_out_en='1' then
+	Et_out_fsm<=reading;
+elsif tlimit=350 then
+	Et_out_fsm<=dropping;
+	tlimit<=0;
+else
+	tlimit<=tlimit+1;
+end if;
+sw<='0';
+when dropping => --dropping packet
+	if n=0 then
+		rcv_start<='1';
+		n<=1;
+		sw<='1';
+	elsif n=1 then
+		if rcv_comp='1' then
+			rcv_ack<='1';
+			rcv_start<='0';
+			n<=2;
+		end if;
+		sw<='1';
+	elsif n=2 then
+		sw<='0';
+		Et_out_fsm<=Idle;
+		n<=0;
+	end if;
+
+end case;
+end if;
+end if;
+end process outport_proc;
+data_out<=fifo_out;
+mux_proc : process (sw,rd_out_en,pop,fifo_empty)
+begin
+if sw='1' then --mode drop
+	rd_en<=pop;
+	data_avalaible <='0'; --plus de données dans le tampon !
+else
+	rd_en<=rd_out_en;
+	data_avalaible <= not fifo_empty;
+end if;
+end process mux_proc;
+proc_receiv : process (clk,reset)
+variable dlen,i: natural range 0 to 255 :=0;
+
+	begin
+	if reset='1' then 
+				 etrec<=r_wait;
+				 
+				else  
+						if rising_edge(clk) then -- le process s'exécute sur chaque front 
+															-- montant de l'horloge
+						case etrec is
+						when r_wait  =>
+							
+							i:=0;
+							if fifo_empty='0' and rcv_start='1' then
+							
+							etrec<=r_head;
+							mem<=fifo_out;
+							
+							end if;
+						when r_head  =>
+							mem<=fifo_out;  --l'en-tête
+							
+							etrec<=r_len;
+						when r_len =>
+								dlen:=to_integer(unsigned(fifo_out));
+								mem<=fifo_out; -- la longueur
+								
+								if dlen>2 then
+									etrec<=r_data;
+								else
+									etrec<=r_end;
+								end if;
+								i:=1;
+								
+						when r_data  =>
+								if fifo_empty='0' then
+									if i<dlen-2 then
+										i:=i+1;
+										mem<=fifo_out;
+										
+										
+									else
+										etrec<=r_pulse;
+										
+										mem<=fifo_out;
+									end if;
+									-- time out à prévoir ici
+								end if;
+						when r_pulse =>
+								etrec<=r_end;
+								
+						when r_end  =>
+								if rcv_ack='1' then
+									etrec<=r_wait;
+								end if;
+								
+						when others =>
+								
+								
+								etrec<=r_wait;
+						end case;
+						end if;
+				end if;
+	end process;
+	
+	pop<=spop;
+	
+rec_value : process (etrec)
+begin
+case etrec is
+					when r_wait  =>
+						spop<='0';
+						rcv_comp<='0';
+					when r_head  =>
+							
+							spop<='1';
+							rcv_comp<='0';
+
+					when r_len =>
+							spop<='1';
+					when r_data =>
+							spop<='1';
+					when r_pulse =>
+								spop<='0';
+								rcv_comp<='1';
+					when r_end =>
+							spop<='0';
+							rcv_comp<='1';
+					when others =>
+							spop<='0';
+							rcv_comp<='0';
+				end case;
+	end process;
 
 end Behavioral_description;
Index: /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/iseconfig/GENERIC_16_16.projectmgr
===================================================================
--- /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/iseconfig/GENERIC_16_16.projectmgr	(revision 68)
+++ /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/iseconfig/GENERIC_16_16.projectmgr	(revision 69)
@@ -145,5 +145,5 @@
          <SelectedItem>Scheduler11_11 - Scheduler - Behavioral (C:/Core MPI/SWITCH_GENERIC_16_16/Scheduler.vhd)</SelectedItem>
       </SelectedItems>
-      <ScrollbarPosition orientation="vertical" >293</ScrollbarPosition>
+      <ScrollbarPosition orientation="vertical" >283</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
       <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000044e000000020000000000000000000000000000000064ffffffff0000008100000000000000020000044e0000000100000000000000000000000100000000</ViewHeaderState>
@@ -166,5 +166,5 @@
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000010d000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010d0000000100000000</ViewHeaderState>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
       <CurrentItem></CurrentItem>
@@ -276,5 +276,4 @@
          <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar8_8 - Crossbar - Behavioral</ClosedNode>
          <ClosedNode>/SWITCH_GEN - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GEN.vhd/Switch_Crossbar9_9 - Crossbar - Behavioral</ClosedNode>
-         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd</ClosedNode>
          <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
          <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/PORT10_OUTPUT_PORT_MODULE - OUTPUT_PORT_MODULE - Behavioral_description</ClosedNode>
@@ -316,4 +315,5 @@
          <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler15_15 - Scheduler - Behavioral</ClosedNode>
          <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler16_16 - Scheduler - Behavioral</ClosedNode>
+         <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral</ClosedNode>
          <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler10_10 - Scheduler10_10 - Behavioral</ClosedNode>
          <ClosedNode>/SWITCH_GENERIQUE - Behavioral C:|Core MPI|SWITCH_GENERIC_16_16|SWITCH_GENERIQUE.vhd/Scheduler2_2 - Scheduler - Behavioral/Inst_Scheduler11_11 - Scheduler11_11 - Behavioral</ClosedNode>
@@ -452,5 +452,5 @@
          <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar8_8 - Crossbar - Behavioral</ClosedNode>
          <ClosedNode>/test_xbar_16x16 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral/Switch_Crossbar9_9 - Crossbar - Behavioral</ClosedNode>
-         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd</ClosedNode>
+         <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GEN - Behavioral</ClosedNode>
          <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral</ClosedNode>
          <ClosedNode>/test_xbar_8x8 - behavior C:|Core MPI|SWITCH_GENERIC_16_16|test_xbar_8x8.vhd/uut - SWITCH_GENERIQUE - Behavioral/PORT10_INPUT_PORT_MODULE - INPUT_PORT_MODULE - Behavioral</ClosedNode>
@@ -518,11 +518,11 @@
       </ClosedNodes>
       <SelectedItems>
-         <SelectedItem>testbench - behavior (C:/Core MPI/CORE_MPI/sim_fifo.vhd)</SelectedItem>
-      </SelectedItems>
-      <ScrollbarPosition orientation="vertical" >3</ScrollbarPosition>
+         <SelectedItem>test_xbar_8x8 - behavior (C:/Core MPI/SWITCH_GENERIC_16_16/test_xbar_8x8.vhd)</SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >306</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
       <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000014d000000020000000000000000000000000000000064ffffffff0000008100000000000000020000014d0000000100000000000000000000000100000000</ViewHeaderState>
       <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
-      <CurrentItem>testbench - behavior (C:/Core MPI/CORE_MPI/sim_fifo.vhd)</CurrentItem>
+      <CurrentItem>test_xbar_8x8 - behavior (C:/Core MPI/SWITCH_GENERIC_16_16/test_xbar_8x8.vhd)</CurrentItem>
    </ItemView>
    <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
@@ -549,5 +549,5 @@
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000010d000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010d0000000100000000</ViewHeaderState>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
       <CurrentItem>Simulate Behavioral Model</CurrentItem>
@@ -568,5 +568,5 @@
    </ItemView>
    <SourceProcessView>000000ff0000000000000002000000eb0000009c01000000050100000002</SourceProcessView>
-   <CurrentView>Implementation</CurrentView>
+   <CurrentView>Behavioral Simulation</CurrentView>
    <ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_PACKAGE_BODY" guiview="Process" >
       <ClosedNodes>
Index: /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/iseconfig/testbench.xreport
===================================================================
--- /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/iseconfig/testbench.xreport	(revision 68)
+++ /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/iseconfig/testbench.xreport	(revision 69)
@@ -2,5 +2,5 @@
 <report-views version="2.0" >
  <header>
-  <DateModified>2012-11-29T18:08:12</DateModified>
+  <DateModified>2013-06-15T12:57:53</DateModified>
   <ModuleName>testbench</ModuleName>
   <SummaryTimeStamp>Unknown</SummaryTimeStamp>
Index: /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/proto_send.vhd
===================================================================
--- /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/proto_send.vhd	(revision 68)
+++ /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/proto_send.vhd	(revision 69)
@@ -21,5 +21,5 @@
 use IEEE.STD_LOGIC_1164.ALL;
 USE ieee.numeric_std.ALL;
-use work.CoreTypes.all;
+use CoreTypes.all;
 -- Uncomment the following library declaration if using
 -- arithmetic functions with Signed or Unsigned values
Index: /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/test_xbar_8x8.vhd
===================================================================
--- /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/test_xbar_8x8.vhd	(revision 68)
+++ /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/test_xbar_8x8.vhd	(revision 69)
@@ -431,6 +431,6 @@
 				origport:=to_integer(unsigned(portout(destport)(3 downto 0)));
 				rdata_out_en(destport)<='1';
-				if ptype=5 then 
-						etrec<=r_Dlen; --identification de la signature d'en tête valide
+				if ptype=5 then -- 
+						etrec<=r_Dlen;--identification de la signature d'en tête valide
 					else
 						etrec<=r_wait;
Index: /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/test_xbar_8x8_beh.prj
===================================================================
--- /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/test_xbar_8x8_beh.prj	(revision 68)
+++ /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/test_xbar_8x8_beh.prj	(revision 69)
@@ -1,4 +1,3 @@
 vhdl work "CoreTypes.vhd"
-vhdl work "RAM_256.vhd"
 vhdl work "Arbiter.vhd"
 vhdl work "SCHEDULER9_9.VHD"
Index: /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/testbench_summary.html
===================================================================
--- /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/testbench_summary.html	(revision 68)
+++ /PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/testbench_summary.html	(revision 69)
@@ -8,4 +8,5 @@
 <TD>GENERIC_16_16.xise</TD>
 <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+<TD> No Errors </TD>
 </TR>
 <TR ALIGN=LEFT>
@@ -75,4 +76,4 @@
 
 
-<br><center><b>Date Generated:</b> 11/29/2012 - 18:08:12</center>
+<br><center><b>Date Generated:</b> 06/15/2013 - 12:57:53</center>
 </BODY></HTML>