Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.gise
===================================================================
--- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.gise	(revision 68)
+++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/MPI_CORE_COMPONENTS.gise	(revision 70)
@@ -86,4 +86,5 @@
     <file xil_pn:fileType="FILE_NCD" xil_pn:name="EX4_FSM_guide.ncd" xil_pn:origination="imported"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="FIFO_256_FWFT_isim_beh.exe"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Hold_FSM_isim_beh.exe"/>
     <file xil_pn:fileType="FILE_NCD" xil_pn:name="MPICORETEST_guide.ncd" xil_pn:origination="imported"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="MPI_CORE_SCHEDULER.bld"/>
@@ -113,4 +114,5 @@
     <file xil_pn:fileType="FILE_HTML" xil_pn:name="MPI_CORE_SCHEDULER_summary.html"/>
     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="MPI_CORE_SCHEDULER_xst.xrpt"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="MPI_NOC.fdo"/>
     <file xil_pn:fileType="FILE_SPL" xil_pn:name="MPI_NOC.spl"/>
     <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="MPI_NOC.sym" xil_pn:origination="imported"/>
@@ -118,4 +120,5 @@
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="MultiMPITest.bld"/>
     <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="MultiMPITest.cmd_log"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="MultiMPITest.fdo"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="MultiMPITest.lso"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="MultiMPITest.ncd" xil_pn:subbranch="Par"/>
@@ -160,4 +163,5 @@
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="PE.bld"/>
     <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="PE.cmd_log"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="PE.fdo"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="PE.lso"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="PE.ncd" xil_pn:subbranch="Par"/>
@@ -220,13 +224,10 @@
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="SWITCH_GEN_map.ncd" xil_pn:subbranch="Map"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="SWITCH_GEN_map.ngm" xil_pn:subbranch="Map"/>
-    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_map.xrpt"/>
-    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_ngdbuild.xrpt"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="SWITCH_GEN_pad.csv" xil_pn:subbranch="Par"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="SWITCH_GEN_pad.txt" xil_pn:subbranch="Par"/>
     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_par.xrpt"/>
     <file xil_pn:fileType="FILE_HTML" xil_pn:name="SWITCH_GEN_summary.html"/>
-    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="SWITCH_GEN_summary.xml"/>
-    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="SWITCH_GEN_usage.xml"/>
     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="SWITCH_GEN_xst.xrpt"/>
+    <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="SetBit.vhi"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@@ -266,4 +267,5 @@
     <file xil_pn:fileType="FILE_HTML" xil_pn:name="load_instr_summary.html"/>
     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="load_instr_xst.xrpt"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="mpi_test.fdo"/>
     <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="mpi_test_beh.prj"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="mpi_test_isim_beh.exe"/>
@@ -276,9 +278,12 @@
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_DMA_isim_beh.exe"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="test_xbar_8x8.fdo"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_xbar_8x8_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testbench_isim_beh.exe"/>
     <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_LOG" xil_pn:name="vsim.wlf"/>
     <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
     <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="work"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
@@ -290,12 +295,17 @@
       <status xil_pn:value="FailedRun"/>
       <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1366390106" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1366390106">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1366622930" xil_pn:in_ck="-6687518003772672403" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1366622930">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForProperties"/>
+    </transform>
+    <transform xil_pn:end_ts="1367007171" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1367007171">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1387380771" xil_pn:in_ck="-2724970427296384327" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1387380771">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd"/>
       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd"/>
@@ -336,7 +346,9 @@
       <outfile xil_pn:name="EX4_FSM.vhd"/>
       <outfile xil_pn:name="Ex0_Fsm.vhd"/>
+      <outfile xil_pn:name="Ex5_FSM.vhd"/>
       <outfile xil_pn:name="FIFO_64_FWFT.vhd"/>
       <outfile xil_pn:name="FIfo_mem.vhd"/>
       <outfile xil_pn:name="FIfo_proc.vhd"/>
+      <outfile xil_pn:name="HT_process.vhd"/>
       <outfile xil_pn:name="Hold_FSM.vhd"/>
       <outfile xil_pn:name="MPICORETEST.vhd"/>
@@ -351,4 +363,5 @@
       <outfile xil_pn:name="RAM_32_32.vhd"/>
       <outfile xil_pn:name="RAM_64.vhd"/>
+      <outfile xil_pn:name="SetBit.vhd"/>
       <outfile xil_pn:name="image_pkg.vhd"/>
       <outfile xil_pn:name="load_instr.vhd"/>
@@ -358,19 +371,24 @@
       <outfile xil_pn:name="test_DMA.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1366610992" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8801908244967488165" xil_pn:start_ts="1366610992">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1366610993" xil_pn:in_ck="-4314534165031354162" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="3275490455063375833" xil_pn:start_ts="1366610992">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1366390108" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="2807353887341256342" xil_pn:start_ts="1366390108">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1366622930" xil_pn:in_ck="-6687518003772672403" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1366622930">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
+    <transform xil_pn:end_ts="1384950666" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8801908244967488165" xil_pn:start_ts="1384950666">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1384950668" xil_pn:in_ck="-4314534165031354162" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="3275490455063375833" xil_pn:start_ts="1384950666">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1375733793" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2670075927112038592" xil_pn:start_ts="1375733793">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1387380771" xil_pn:in_ck="-2724970427296384327" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1387380771">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/Arbiter.vhd"/>
       <outfile xil_pn:name="../SWITCH_GENERIC_16_16/CoreTypes.vhd"/>
@@ -411,7 +429,9 @@
       <outfile xil_pn:name="EX4_FSM.vhd"/>
       <outfile xil_pn:name="Ex0_Fsm.vhd"/>
+      <outfile xil_pn:name="Ex5_FSM.vhd"/>
       <outfile xil_pn:name="FIFO_64_FWFT.vhd"/>
       <outfile xil_pn:name="FIfo_mem.vhd"/>
       <outfile xil_pn:name="FIfo_proc.vhd"/>
+      <outfile xil_pn:name="HT_process.vhd"/>
       <outfile xil_pn:name="Hold_FSM.vhd"/>
       <outfile xil_pn:name="MPICORETEST.vhd"/>
@@ -426,4 +446,5 @@
       <outfile xil_pn:name="RAM_32_32.vhd"/>
       <outfile xil_pn:name="RAM_64.vhd"/>
+      <outfile xil_pn:name="SetBit.vhd"/>
       <outfile xil_pn:name="image_pkg.vhd"/>
       <outfile xil_pn:name="load_instr.vhd"/>
@@ -433,65 +454,49 @@
       <outfile xil_pn:name="test_DMA.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1366622969" xil_pn:in_ck="-6687518003772672403" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-471607606114857674" xil_pn:start_ts="1366622930">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="fuse.log"/>
-      <outfile xil_pn:name="isim"/>
-      <outfile xil_pn:name="isim.log"/>
-      <outfile xil_pn:name="mpi_test_beh.prj"/>
-      <outfile xil_pn:name="mpi_test_isim_beh.exe"/>
-      <outfile xil_pn:name="xilinxsim.ini"/>
-    </transform>
-    <transform xil_pn:end_ts="1366622969" xil_pn:in_ck="2617743916491253678" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="810398370776000169" xil_pn:start_ts="1366622969">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="isim.cmd"/>
-      <outfile xil_pn:name="isim.log"/>
-      <outfile xil_pn:name="mpi_test_isim_beh.wdb"/>
-    </transform>
-    <transform xil_pn:end_ts="1354901662" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1354901662">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1582102620978348987" xil_pn:start_ts="1364403007">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForInputs"/>
-      <status xil_pn:value="InputAdded"/>
-      <status xil_pn:value="InputChanged"/>
-    </transform>
-    <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="2807353887341256342" xil_pn:start_ts="1364403007">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1364403007">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8804766714685316537" xil_pn:start_ts="1364403007">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1364403007">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
-    </transform>
-    <transform xil_pn:end_ts="1364403007" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4624523187203829856" xil_pn:start_ts="1364403007">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
-    </transform>
-    <transform xil_pn:end_ts="1365597033" xil_pn:in_ck="-7317970075764060686" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-1458878356683843968" xil_pn:start_ts="1365596908">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="WarningsGenerated"/>
+    <transform xil_pn:end_ts="1387380806" xil_pn:in_ck="-2724970427296384327" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="-6667380628693525942" xil_pn:start_ts="1387380771">
+      <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
       <status xil_pn:value="OutOfDateForPredecessor"/>
-      <status xil_pn:value="InputAdded"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="OutputChanged"/>
+      <outfile xil_pn:name="mpi_test.fdo"/>
+      <outfile xil_pn:name="vsim.wlf"/>
+      <outfile xil_pn:name="work"/>
+    </transform>
+    <transform xil_pn:end_ts="1354901662" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1354901662">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1383365892" xil_pn:in_ck="-4314534165031354162" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1582102620978348987" xil_pn:start_ts="1383365882">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1375422910" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2670075927112038592" xil_pn:start_ts="1375422910">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1375399240" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1375399240">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1375399240" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8804766714685316537" xil_pn:start_ts="1375399240">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1375422910" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="6952878091308752832" xil_pn:start_ts="1375422910">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1375422910" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8344791072052426826" xil_pn:start_ts="1375422910">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1385740019" xil_pn:in_ck="-8697612743778259046" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="4800614739687910250" xil_pn:start_ts="1385739753">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
       <status xil_pn:value="InputChanged"/>
       <outfile xil_pn:name="Crossbar.ngr"/>
@@ -515,10 +520,9 @@
       <outfile xil_pn:name="xst"/>
     </transform>
-    <transform xil_pn:end_ts="1365008714" xil_pn:in_ck="6885079285025204965" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4542759591300251492" xil_pn:start_ts="1365008714">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
-    </transform>
-    <transform xil_pn:end_ts="1365597048" xil_pn:in_ck="3099115937148329492" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-5155457213437603231" xil_pn:start_ts="1365597033">
+    <transform xil_pn:end_ts="1383365919" xil_pn:in_ck="6885079285025204965" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4542759591300251492" xil_pn:start_ts="1383365918">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1385740045" xil_pn:in_ck="3099115937148329492" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1241333572523989429" xil_pn:start_ts="1385740019">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
@@ -531,6 +535,6 @@
       <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
     </transform>
-    <transform xil_pn:end_ts="1365597494" xil_pn:in_ck="4998795473985982555" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4079613270754646221" xil_pn:start_ts="1365597048">
-      <status xil_pn:value="SuccessfullyRun"/>
+    <transform xil_pn:end_ts="1385740175" xil_pn:in_ck="4998795473985982555" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2137179975354236087" xil_pn:start_ts="1385740045">
+      <status xil_pn:value="FailedRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -539,5 +543,4 @@
       <outfile xil_pn:name="MultiMPITest_map.map"/>
       <outfile xil_pn:name="MultiMPITest_map.mrp"/>
-      <outfile xil_pn:name="MultiMPITest_map.ncd"/>
       <outfile xil_pn:name="MultiMPITest_map.ngm"/>
       <outfile xil_pn:name="MultiMPITest_map.xrpt"/>
@@ -546,27 +549,25 @@
       <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
     </transform>
-    <transform xil_pn:end_ts="1365598174" xil_pn:in_ck="-2175087184199880886" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1365597494">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="WarningsGenerated"/>
-      <status xil_pn:value="ReadyToRun"/>
+    <transform xil_pn:end_ts="1375723360" xil_pn:in_ck="-2175087184199880886" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="832869163894192598" xil_pn:start_ts="1375723309">
+      <status xil_pn:value="AbortedRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
       <status xil_pn:value="OutOfDateForPredecessor"/>
-      <outfile xil_pn:name="MultiMPITest.ncd"/>
-      <outfile xil_pn:name="MultiMPITest.pad"/>
-      <outfile xil_pn:name="MultiMPITest.par"/>
-      <outfile xil_pn:name="MultiMPITest.ptwx"/>
-      <outfile xil_pn:name="MultiMPITest.unroutes"/>
-      <outfile xil_pn:name="MultiMPITest.xpi"/>
-      <outfile xil_pn:name="MultiMPITest_pad.csv"/>
-      <outfile xil_pn:name="MultiMPITest_pad.txt"/>
-      <outfile xil_pn:name="MultiMPITest_par.xrpt"/>
-      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
-    </transform>
-    <transform xil_pn:end_ts="1365598174" xil_pn:in_ck="-5951230430360050753" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1365598146">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="InputRemoved"/>
+      <status xil_pn:value="OutputChanged"/>
+      <status xil_pn:value="OutputRemoved"/>
+    </transform>
+    <transform xil_pn:end_ts="1375521689" xil_pn:in_ck="-8422061398529632623" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1375521634">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
       <status xil_pn:value="OutOfDateForPredecessor"/>
-      <outfile xil_pn:name="MultiMPITest.twr"/>
-      <outfile xil_pn:name="MultiMPITest.twx"/>
-      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="InputRemoved"/>
+      <status xil_pn:value="OutputChanged"/>
+      <status xil_pn:value="OutputRemoved"/>
     </transform>
   </transforms>
