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Changeset 70 for PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/PE.vhd
- Timestamp:
- Dec 20, 2013, 7:55:55 PM (11 years ago)
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- 1 edited
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PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/PE.vhd (modified) (12 diffs)
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PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/PE.vhd
r64 r70 1 1 ---------------------------------------------------------------------------------- 2 2 -- Company: 3 -- Engineer: 3 -- Engineer: GAMOM Roland Christian 4 4 -- 5 5 -- Create Date: 21:20:54 07/16/2012 … … 9 9 -- Target Devices: 10 10 -- Tool versions: 11 -- Description: 12 -- 11 -- Description: Ce module permet d'encapsuler une tâche matérielle 12 -- et lui donne la possiblité de communiquer à l'aide des fonctions MPI-2 RMA 13 13 -- Dependencies: 14 14 -- … … 40 40 clk : in STD_LOGIC; 41 41 reset : in STD_LOGIC; 42 CE : in STD_LOGIC; -- Active le PE après sa synthèse 42 43 Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); 43 44 Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); … … 66 67 ); 67 68 END COMPONENT; 69 COMPONENT HT_process is 70 generic (Task_Id : natural); 71 Port ( clk : in STD_LOGIC; 72 reset : in STD_LOGIC; 73 en : in std_logic; -- active la tâche 74 Interf_i : in core_i; --signaux pour l'interface I 75 Interf_o : out core_o; --signaux pour l'interface IO 76 mem_i : in typ_dpram_i; -- signaux pour l'accès à la mémoire 77 mem_o : out typ_dpram_o -- signaux pour l'accès à la mémoire 78 ); 79 end COMPONENT HT_process; 68 80 COMPONENT Hold_FSM is 81 69 82 Port ( Hold_Req : in STD_LOGIC; 70 83 Ram_busy : in STD_LOGIC; … … 76 89 --données du programme PE 77 90 --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); 78 signal ram_we ,ram_ena,ram_enb,ramsel : std_logic:='0';91 signal ram_we ,ram_ena,ram_enb,ramsel_i: std_logic:='0'; 79 92 signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic; 80 93 signal pe_instr_en,pe_hold_ack: std_logic:='0'; … … 84 97 signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); 85 98 signal sram : typ_dpram; 99 signal clk_ht : std_logic; 86 100 signal MyGroup:mpi_group; 87 101 signal MyWin : mpi_win; … … 93 107 signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO 94 108 signal Lib_Init : std_logic; -- l'initialisation est terminée 109 signal Lib_Enable : std_logic; 95 110 signal Hold_Ack : std_logic; 111 signal en_task : std_logic; 96 112 --signaux pour la gestion de la MAE 97 113 type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinStart, putdata,getdata,WinCompleted,finalize,st_timeout); … … 107 123 Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN) 108 124 PORT MAP( 109 clka =>clk ,110 clkb => clk ,125 clka =>clk , 126 clkb => clk , 111 127 wea => ram_we, 112 128 ena => ram_ena, … … 117 133 dob => ram_do 118 134 ); 135 HT_task:HT_process generic map(Task_id =>DestId) 136 port map ( 137 clk=>clk_ht, 138 reset=>reset, 139 en=>en_task, 140 Interf_i =>Libr.i, 141 Interf_o=>Libr.o, 142 mem_i =>sram.i, 143 mem_o =>sram.o ); 144 119 145 --================================================================ 120 146 --MUX de la RAM 121 147 122 Ram_mux: process ( ramsel,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr,148 Ram_mux: process (clk,ramsel_i,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr, 123 149 Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do, 124 150 Pe_ram_din,Pe_ram_we ) 125 151 begin 126 case ramsel is152 case ramsel_i is 127 153 128 154 when '1' => … … 133 159 ram_we<= Core_ram_we; 134 160 ram_din <= Core_ram_data_in; 135 pe_ram_do<=(others=>' Z');161 pe_ram_do<=(others=>'-'); 136 162 Core_ram_data_out<=ram_do; 137 163 … … 143 169 ram_we<= pe_ram_we; 144 170 ram_din <=pe_ram_din; 145 Core_ram_data_out<=(others=>' Z');171 Core_ram_data_out<=(others=>'-'); 146 172 pe_ram_do<=ram_do; 147 173 end case ; … … 153 179 --=== !!!!! attention la suppression de la ligne ci-dessous empêche ce 154 180 -- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!! 155 instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8));181 --instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8)); 156 182 157 183 dpid<=dpid_i; 158 184 en_task<= CE or Lib_enable; --l'activation d'une HT peut être directe ou commandée 159 185 Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié 160 186 Lib_init<=Core_Pushout(4); -- Initialized 187 Lib_Enable<=Core_Pushout(6);-- HT activée par la Librairie. 188 189 horloge_ht:process (reset,ce,lib_enable,clk) 190 begin 191 if reset='1' then 192 clk_ht<='0'; 193 else 194 if ce='1' then 195 clk_ht<=clk; 196 elsif lib_enable='1' then 197 clk_ht<=clk; 198 else 199 clk_ht<='0'; 200 end if; 201 end if; 202 end process horloge_ht; 161 203 162 204 Hold1: Hold_fsm port map ( 163 clk=>clk ,205 clk=>clk , 164 206 reset =>reset, 165 Ram_Busy=>Libr. membusy,207 Ram_Busy=>Libr.O.membusy, 166 208 Hold_Ack=>Hold_Ack, 167 209 Hold_req =>Core_Hold_Req, 168 RamSel => RamSel );210 RamSel => RamSel_i); 169 211 Core_Hold_Ack<=Hold_Ack; 170 212 171 213 --================RAM signals ====================== 214 sram.I.data_out<=PE_ram_do; 215 pe_Ram_addra<=sram.O.addr_wr; 216 pe_Ram_addrb<=sram.O.addr_rd ; 217 PE_Ram_we<=sram.O.we; 218 PE_Ram_ena<=sram.O.ena; 219 PE_Ram_enb<=sram.O.enb; 220 PE_ram_din<=sram.O.data_in; 221 --==========MPI HCL signals ============================ 222 223 affect:process (clk,Core_hold_req,RamSel_i,Core_pushout,Libr) 224 begin 225 --if (clk'event and clk='1') then 226 Instruction<=Libr.O.Instruction; 227 Ram_busy<=Libr.O.membusy; 228 PE_Instr_EN<=Libr.O.instr_en; 229 Libr.I.Instr_ack<=Core_pushout(0); 230 Libr.I.InitOk<=Core_pushout(4); 231 Libr.I.Spawned<=Core_pushout(6); 232 Libr.I.Hold_Req<=Core_Hold_req; 233 --Libr.I.Hold_Ack<=Hold_Ack; 234 Libr.I.RamSel<=RamSel_i; 235 --end if; 236 end process affect; 172 237 --======================================================================= 173 238 --MAE du PE 174 239 --======================================================================= 175 240 176 pPutGet:process(clk,Core_Pushout,Core_Hold_req,PE_hold_Ack,RamSel,PE_Ram_do)177 241 178 constant DATAPTR : natural :=256;179 variable bfill,destrank,pid,mport : natural range 0 to 15;180 variable fsrc,ret : natural range 0 to 15:=0;181 variable timeout,ct,dlen : natural range 0 to 255;182 variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0);183 variable mywin : Mpi_win;184 variable iack : std_logic:='0';185 variable adresse,adresse_rd :natural range 0 to 65536;186 variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0');187 --=======================================================188 --variables pour la création du fichier de résultats189 -- synthesis translate_off190 type char_file is file of character;191 file f: text;192 variable status :file_open_status ;193 variable char_count: integer range 0 to 65536 := 0;194 variable str: string (1 to 79) ;195 variable L: line;196 variable fopened: std_logic:='0';197 -- synthesis translate_on198 --======================================================199 begin200 --=== Partie combinatoire du process ===================================201 202 --=== Fin de la partie combinatoire du process ==========================203 204 205 206 --end loop;207 208 if (clk'event and clk='1') then209 Libr.Instr_ack<=Core_pushout(0);210 Libr.InitOk<=Core_pushout(4);211 Libr.Hold_Req<=Core_Hold_req;212 Libr.Hold_Ack<=Hold_Ack;213 Libr.RamSel<=RamSel;214 sram.data_out<=PE_ram_do;215 216 if reset='1' then217 RunState<=start;218 219 else220 221 Libr.Instr_ack<=Core_pushout(0);222 Libr.InitOk<=Core_pushout(4);223 Libr.Hold_Req<=Core_Hold_req;224 Libr.Hold_Ack<=Hold_Ack;225 Libr.RamSel<=RamSel;226 sram.data_out<=PE_ram_do;227 228 case RunState is229 when start =>230 Dcount<=0;231 if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide232 RunState<=Fillmem;233 end if;234 Ram_busy<='0';235 Libr.MemBusy<='0';236 PE_Instr_En<='0';237 iack:='0';238 adresse:=DATAPTR;239 240 adresse_rd:=0;241 timeout:=0;242 dcount<=0;243 -- synthesis translate_off244 if fopened='0' then245 file_open(status,f, integer'image(destid) & "test_file0.txt", APPEND_MODE);246 --while not endfile(c_file_handle) loop247 --end if;248 249 --write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now)));250 --report l.all;251 -- writeline (f, l) ;252 fopened:='1';253 end if;254 -- synthesis translate_on255 when Fillmem =>256 if Ramsel='0' then257 258 259 260 PE_Ram_din<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f";261 PE_Instr_En<='0';262 dcount<=dcount+1;263 264 if dcount=100 then265 bfill:=bfill+1;266 267 if bfill=4 then268 RunState<=InitApp;269 else270 RunState<=nextfill;271 end if;272 else273 adresse:=adresse+1;274 RunState<=Fillmem;275 end if;276 else -- attente de la libéraion de la mémoire277 timeout:=timeout+1;278 if timeout=100 then279 RunState<=st_timeout;280 end if;281 282 end if;283 when nextfill => --prépare le prochain bloc mémoire qui sera rempli284 adresse:=200*bfill+1;285 dcount<=0;286 ct:=0;287 RunState<=Fillmem;288 PE_Instr_En<='0';289 when InitApp =>290 --code pour Init291 dlen:=139;292 if ct=0 then293 -- synthesis translate_off294 write (l,string'("Dlen; ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & time'image(now)));295 296 report l.all;297 writeline (f, l) ;298 -- synthesis translate_on299 end if;300 pMPI_Init(ct,Libr,Clk,SRam);301 PE_Instr_EN<=Libr.instr_en;302 adresse:=to_integer(unsigned(sram.addr_wr));303 adresse_rd:=to_integer(unsigned(sram.addr_rd));304 PE_ram_din<=sram.data_in;305 Ram_busy<=Libr.membusy;306 --if Libr.InitOk='1' then307 if ct=0 then308 RunState<=GetRank;309 -- synthesis translate_off310 write (l,string'("Dlen; ;INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));311 report l.all;312 writeline (f, l) ;313 -- synthesis translate_on314 end if;315 316 317 318 when GetRank =>319 if ct=0 then320 -- synthesis translate_off321 write (l,string'("Dlen; ;Rank1 " & integer'image(Dlen) & "; ; started ; " & time'image(now)));322 report l.all;323 writeline (f, l) ;324 -- synthesis translate_on325 end if;326 pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank);327 adresse_rd:=to_integer(unsigned(sram.addr_rd));328 Ram_busy<=Libr.membusy;329 330 if ct=0 then331 RunState<=WinStart;332 -- synthesis translate_off333 write (l,string'("Dlen; ;Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));334 report l.all;335 writeline (f, l) ;336 -- synthesis translate_on337 end if;338 339 340 when Wincreate =>341 342 when WinStart =>343 if ct=0 then344 -- synthesis translate_off345 write (l,string'("Dlen; ;WStart1 " & integer'image(Dlen) & "; ; started ; " & time'image(now)));346 report l.all;347 writeline (f, l) ;348 -- synthesis translate_on349 end if;350 pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin);351 adresse:=to_integer(unsigned(sram.addr_wr));352 adresse_rd:=to_integer(unsigned(sram.addr_rd));353 --PE_Instr_EN<=Libr.instr_en;354 PE_ram_din<=sram.data_in;355 Ram_busy<=Libr.membusy;356 dcount<=ct;357 358 if ct=0 then359 RunState<=PutData;360 -- synthesis translate_off361 write (l,string'("Dlen; ;WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));362 report l.all;363 writeline (f, l) ;364 -- synthesis translate_on365 end if;366 367 368 when putdata => --construire le packet pour le Put369 370 --dlen:=251; ---371 if ct=0 then372 -- synthesis translate_off373 write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now)));374 report l.all;375 writeline (f, l) ;376 -- synthesis translate_on377 end if;378 if unsigned(MyRank) = 0 then379 Destrank:=2;380 381 elsif unsigned(MyRank) = 1 then382 Destrank:=0;383 elsif unsigned(MyRank) = 2 then384 Destrank:=1;385 elsif unsigned(MyRank) = 3 then386 Destrank:=2;387 else388 DestRank:=0;389 end if;390 391 SrcAdr:=std_logic_vector(to_unsigned(DATAPTR,ADRLEN));392 DestAdr:=X"0340";393 pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);394 395 adresse:=to_integer(unsigned(sram.addr_wr));396 adresse_rd:=to_integer(unsigned(sram.addr_rd));397 PE_Instr_EN<=Libr.instr_en;398 PE_ram_din<=sram.data_in;399 Ram_busy<=Libr.membusy;400 dcount<=ct;401 402 if ct=0 then403 RunState<=GetData;404 -- synthesis translate_off405 report "Put of Process n°; " & image(MyRank) & "; ended at ; " & time'image(now);406 write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & time'image(now)));407 report l.all;408 writeline (f, l) ;409 -- synthesis translate_on410 end if;411 412 413 when getdata => --positionnement du mot de longueur des données414 --dlen:=251; ---415 if ct=0 then416 -- synthesis translate_off417 write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & time'image(now)));418 report l.all;419 writeline (f, l) ;420 -- synthesis translate_on421 end if;422 423 SrcAdr:=X"0120";424 DestAdr:=X"1400";425 if unsigned(MyRank) /= 2 then426 pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);427 else428 RunState<=wincompleted;429 end if;430 adresse:=to_integer(unsigned(sram.addr_wr));431 adresse_rd:=to_integer(unsigned(sram.addr_rd));432 PE_Instr_EN<=Libr.instr_en;433 PE_ram_din<=sram.data_in;434 Ram_busy<=Libr.membusy;435 dcount<=ct;436 437 if ct=0 then438 RunState<=wincompleted;439 -- synthesis translate_off440 assert ct/=0 report "GET_END " & integer'image(destrank)441 severity Warning ;442 write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));443 report l.all;444 445 writeline (f, l) ;446 -- synthesis translate_on447 end if;448 449 when WinCompleted =>450 if ct=0 then451 -- synthesis translate_off452 write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now)));453 report l.all;454 writeline (f, l) ;455 -- synthesis translate_on456 end if;457 pMPI_Win_wait(ct,Libr,sram,MyWin );458 adresse:=to_integer(unsigned(sram.addr_wr));459 adresse_rd:=to_integer(unsigned(sram.addr_rd));460 Ram_busy<=Libr.membusy;461 if ct=0 then462 RunState<=finalize;463 -- synthesis translate_off464 write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));465 report l.all;466 writeline (f, l) ;467 -- synthesis translate_on468 469 end if;470 471 472 when finalize =>473 if ct=0 then474 -- synthesis translate_off475 write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & time'image(now)));476 report l.all;477 writeline (f, l) ;478 -- synthesis translate_on479 end if;480 481 if ct=0 then482 RunState<=start;483 -- synthesis translate_off484 write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & time'image(now)));485 report l.all;486 writeline (f, l) ;487 file_close(f);488 -- synthesis translate_on489 end if;490 491 when st_timeout =>492 493 --if ram_busy='1' then494 RunState<=start;495 --end if496 497 RunState<=start;498 end case;499 pe_Ram_addra<=STD_LOGIC_VECTOR(to_unsigned(adresse,16));500 pe_Ram_addrb<=STD_LOGIC_VECTOR(to_unsigned(adresse_rd,16));501 end if;502 end if;503 504 end process pPutGet;505 506 majPutGet:process (RunState,pe_ram_do,sram,Lib_Init)507 508 begin509 case RunState is510 when start =>511 512 PE_Ram_we<='0';513 PE_Ram_ena<='0';514 PE_Ram_enb<='0';515 --PE_Instr_En<='0';516 517 when fillmem =>518 PE_Ram_we<='1';519 PE_Ram_ena<='1';520 521 PE_Ram_enb<='0';522 --PE_Instr_En<='0';523 when nextfill =>524 PE_Ram_we<='1';525 PE_Ram_ena<='1';526 PE_Ram_enb<='0';527 528 when InitApp =>529 -- PE_Ram_we<='1';530 -- PE_Ram_ena<='1';531 -- PE_Ram_enb<='0';532 PE_Ram_we<=sram.we;533 PE_Ram_ena<=sram.ena;534 PE_Ram_enb<=sram.enb;535 536 537 when GetRank =>538 539 PE_Ram_we<=sram.we;540 PE_Ram_ena<=sram.ena;541 PE_Ram_enb<=sram.enb;542 when WinCreate =>543 544 PE_Ram_we<=sram.we;545 PE_Ram_ena<=sram.ena;546 PE_Ram_enb<=sram.enb;547 548 when WinStart =>549 550 PE_Ram_we<=sram.we;551 PE_Ram_ena<=sram.ena;552 PE_Ram_enb<=sram.enb;553 --positionnement du mot de longueur des données554 555 556 when putdata =>557 srcadr0<=X"00";558 srcadr1<=X"01";559 destadr0<=X"00";560 destadr1<=X"02";561 PE_Ram_we<=sram.we;562 PE_Ram_ena<=sram.ena;563 PE_Ram_enb<=sram.enb;564 565 when getdata =>566 PE_Ram_we<=sram.we;567 PE_Ram_ena<=sram.ena;568 PE_Ram_enb<=sram.enb;569 570 when Wincompleted =>571 PE_Ram_we<=sram.we;572 PE_Ram_ena<=sram.ena;573 PE_Ram_enb<=sram.enb;574 575 when finalize =>576 577 PE_Ram_we<='0';578 PE_Ram_ena<='0';579 PE_Ram_enb<='0';580 581 582 when st_timeout =>583 PE_Ram_we<='0';584 PE_Ram_ena<='0';585 PE_Ram_enb<='0';586 587 588 end case;589 590 end process majPutGet ;591 242 end Behavioral; 592 243
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