Ignore:
Timestamp:
Dec 20, 2013, 7:55:55 PM (11 years ago)
Author:
rolagamo
Message:
 
Location:
PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MPI_CORE_COMPONENTS.projectmgr

    r64 r70  
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  • PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/iseconfig/MultiMPITest.xreport

    r64 r70  
    22<report-views version="2.0" >
    33 <header>
    4   <DateModified>2013-04-22T08:02:07</DateModified>
    5   <ModuleName>DMA_ARBITER</ModuleName>
    6   <SummaryTimeStamp>2013-04-10T14:49:35</SummaryTimeStamp>
     4  <DateModified>2013-12-10T20:37:28</DateModified>
     5  <ModuleName>SWITCH_GEN</ModuleName>
     6  <SummaryTimeStamp>2013-11-29T16:49:35</SummaryTimeStamp>
    77  <SavedFilePath>C:/Core MPI/CORE_MPI/iseconfig/MultiMPITest.xreport</SavedFilePath>
    88  <ImplementationReportsDirectory>C:/Core MPI/CORE_MPI\</ImplementationReportsDirectory>
    9   <DateInitialized>2013-03-19T19:44:50</DateInitialized>
     9  <DateInitialized>2013-06-15T13:06:16</DateInitialized>
    1010  <EnableMessageFiltering>false</EnableMessageFiltering>
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    1616    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
    … …  
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    9595    <toc-item title="Command Line" target="Command Line:" />
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    9797    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
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    100100    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    101101    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
    … …  
    113113    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
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    117117    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
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    122122    <toc-item title="Final Summary" target="Peak Memory Usage:" />
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     135   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.rpt" label="CPLD Fitter Report (Text)" >
    136136    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
    137137    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
    … …  
    139139    <toc-item title="Global Resources" target="** Global Control Resources **" />
    140140   </view>
    141    <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="DMA_ARBITER.tim" label="CPLD Timing Report (Text)" >
     141   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.tim" label="CPLD Timing Report (Text)" >
    142142    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
    143143    <toc-item title="Performance Summary" target="Performance Summary:" />
    144144   </view>
    145    <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="DMA_ARBITER.pwr" label="Power Report" >
     145   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="SWITCH_GEN.pwr" label="Power Report" >
    146146    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    147147    <toc-item title="Power summary" target="Power summary" />
    148148    <toc-item title="Thermal summary" target="Thermal summary" />
    149149   </view>
    150    <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="DMA_ARBITER.bgn" label="Bitgen Report" >
     150   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.bgn" label="Bitgen Report" >
    151151    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    152152    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
    … …  
    156156  <viewgroup label="Secondary Reports" >
    157157   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
    158    <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/DMA_ARBITER_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
    159     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    160    </view>
    161    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/DMA_ARBITER_translate.nlf" label="Post-Translate Simulation Model Report" >
    162     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    163    </view>
    164    <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
    165    <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="DMA_ARBITER_map.map" label="Map Log File" >
     158   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/SWITCH_GEN_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
     159    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     160   </view>
     161   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/SWITCH_GEN_translate.nlf" label="Post-Translate Simulation Model Report" >
     162    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     163   </view>
     164   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
     165   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN_map.map" label="Map Log File" >
    166166    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    167167    <toc-item title="Design Information" target="Design Information" />
    … …  
    169169   </view>
    170170   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
    171    <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_preroute.twr" label="Post-Map Static Timing Report" >
     171   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.twr" label="Post-Map Static Timing Report" >
    172172    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    173173    <toc-item title="Timing Report Description" target="Device,package,speed:" />
    … …  
    180180    <toc-item title="Trace Settings" target="Trace Settings:" />
    181181   </view>
    182    <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/DMA_ARBITER_map.nlf" label="Post-Map Simulation Model Report" />
    183    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_map.psr" label="Physical Synthesis Report" >
    184     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    185    </view>
    186    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="DMA_ARBITER_pad.txt" label="Pad Report" >
    187     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    188    </view>
    189    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="DMA_ARBITER.unroutes" label="Unroutes Report" >
    190     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    191    </view>
    192    <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_preroute.tsi" label="Post-Map Constraints Interaction Report" >
    193     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    194    </view>
    195    <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.grf" label="Guide Results Report" />
    196    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.dly" label="Asynchronous Delay Report" />
    197    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.clk_rgn" label="Clock Region Report" />
    198    <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.tsi" label="Post-Place and Route Constraints Interaction Report" >
    199     <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
    200    </view>
    201    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
    202    <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/DMA_ARBITER_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
    203    <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER_sta.nlf" label="Primetime Netlist Report" >
    204     <toc-item title="Top of Report" target="Release" searchDir="Forward" />
    205    </view>
    206    <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.ibs" label="IBIS Model" >
     182   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/SWITCH_GEN_map.nlf" label="Post-Map Simulation Model Report" />
     183   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_map.psr" label="Physical Synthesis Report" >
     184    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     185   </view>
     186   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="SWITCH_GEN_pad.txt" label="Pad Report" >
     187    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     188   </view>
     189   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN.unroutes" label="Unroutes Report" >
     190    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     191   </view>
     192   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.tsi" label="Post-Map Constraints Interaction Report" >
     193    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     194   </view>
     195   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.grf" label="Guide Results Report" />
     196   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.dly" label="Asynchronous Delay Report" />
     197   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.clk_rgn" label="Clock Region Report" />
     198   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.tsi" label="Post-Place and Route Constraints Interaction Report" >
     199    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
     200   </view>
     201   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
     202   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/SWITCH_GEN_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
     203   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_sta.nlf" label="Primetime Netlist Report" >
     204    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
     205   </view>
     206   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.ibs" label="IBIS Model" >
    207207    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
    208208    <toc-item title="Component" target="Component " />
    209209   </view>
    210    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.lck" label="Back-annotate Pin Report" >
     210   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lck" label="Back-annotate Pin Report" >
    211211    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
    212212    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
    213213   </view>
    214    <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DMA_ARBITER.lpc" label="Locked Pin Constraints" >
     214   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lpc" label="Locked Pin Constraints" >
    215215    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
    216216    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
    217217   </view>
    218    <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/DMA_ARBITER_timesim.nlf" label="Post-Fit Simulation Model Report" />
     218   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/SWITCH_GEN_timesim.nlf" label="Post-Fit Simulation Model Report" />
    219219   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
    220220   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
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