Index: PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX2_FSM.vhd
===================================================================
--- PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX2_FSM.vhd	(revision 70)
+++ PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/EX2_FSM.vhd	(revision 72)
@@ -114,8 +114,9 @@
 type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2, 
 fetch_addresses,ex2_spawn,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4,
-ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack,
- ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4,
-  ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2);
+ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack1,ex2_ack2,ex2_ack3,
+ Ex2_WSync,Ex2_WComp,ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4,
+  ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2,Ex2_Set_Busy);
 type fsm_ack is(ack0,ack1,ack2,ack3,ack4,ack5,ack6);
+type mem32 is array (natural range <>) of std_logic_vector (31 downto 0);
 signal Next_Ex2_state,ex2_state :fsm_states;
 signal ack_state,next_ack_state : fsm_ack;
@@ -126,5 +127,5 @@
 signal pading_data,data_to_ram :  std_logic_vector(Word-1 downto 0):=(others=>'0');
 signal n,n_i : natural range 0 to 15;
-signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0):=(others=>'-');
+signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0');
 signal data_to_write_fifo :  std_logic_vector(Word-1 downto 0);
 --*******************************************
@@ -139,4 +140,25 @@
 signal		sb_ram_address : std_logic_vector(15 downto 0):=(others=>'0');
 signal		sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0');
+-- deuxième module pour set busy bit
+signal		bu_BitMask : std_logic_vector(7 downto 0):=(others=>'0');
+signal		bu_BitVal,bu_start,bu_done : std_logic:='0';
+signal		bu_Ram_data_in : std_logic_vector(7 downto 0);          
+signal		bu_dma_wr_request :  std_logic;
+signal		bu_dma_rd_request :  std_logic;
+signal		bu_ram_rd : std_logic;
+signal		bu_ram_wr : std_logic;
+signal		bu_ram_address : std_logic_vector(15 downto 0):=(others=>'0');
+signal		bu_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0');
+signal Set_Wbusy : std_logic:='0'; --choix du Mux
+signal		b_BitMask : std_logic_vector(7 downto 0):=(others=>'0');
+signal		b_BitVal,b_start,b_done : std_logic:='0';
+signal		b_Ram_data_in : std_logic_vector(7 downto 0);          
+signal		b_dma_wr_request :  std_logic;
+signal		b_dma_rd_request :  std_logic;
+signal		b_ram_rd : std_logic;
+signal		b_ram_wr : std_logic;
+signal		b_ram_address : std_logic_vector(15 downto 0):=(others=>'0');
+signal		b_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0');
+
 --*********************************************
 signal Ex2_on : std_logic:='0';
@@ -151,4 +173,15 @@
 signal rpop:std_logic;
 --signal mem:memory(0 to Msize-1));
+--jusqu'à 16 Get peuvent être attendus!
+signal Wcomp : std_logic:='0'; --indique que tous les transferts sont terminés
+signal WStart,WPost,WBUSY ,RGET: std_logic:='0'; --
+signal Rec_WPost, GPost_i,GPost: std_logic_vector(15 downto 0):=(others=>'0');
+signal Waited_Get : mem32(0 to 15);
+Signal Rec_Data_i : Typ_PortIO(0 to 3);
+signal Get_Instr,Put_instr :memory(0 to 8);
+signal Put_Id : std_logic_vector(31 downto 0):=(others=>'0');
+signal P_G: natural range 0 to 3:=0; --Msg Ack : 1 -> Put, 2-->Get
+signal Ptr_Get,Ptr_Get_i : natural range 0 to 15:=0;
+signal Received_get : std_logic_vector(15 downto 0):=(others=>'0');--sera remis à 0 lorsque Wstart/WPost est reçu
 begin
 ram_address <= dest_address;
@@ -199,12 +232,18 @@
 		done =>sb_done
 		);
-		
+--b_BitVal<=bu_Bitval when Set_Wbusy='1' else Sb_BitVal;
+--b_BitMask<=bu_BitMask when Set_Wbusy='1' else Sb_BitVal;
+--b_start<= bu_start when Set_wBusy='1' else sb_start;
+--b_ram_rd<=bu_ram_rd when Set_Wbusy='1' else Sb_ram_rd;
+--b_ram_wr<=bu_ram_wr when Set_Wbusy='1' else Sb_ram_wr;
+--b_dma_ram_request_rd<=bu__dma_ram_request_rd when Set_Wbusy='1' else Sb_dma_ram_request_rd;
+--b_dma_ram_request_wr<=bu_dma_ram_request_wr when Set_Wbusy='1' else Sb_dma_ram_request_wr;
 -- processus de transistion entre les etats 
 ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized,
  switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len,
- sent_ack,wr_ack,to_fifo_ack,dest_address)
+ sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy)
 variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée
 variable tempval : std_logic_vector(Word-1 downto 0);
-variable n_e:natural range 0 to 15 :=0;
+variable n_e,i:natural range 0 to 15 :=0;
 procedure read_nocdat_fsm(sdata_avail: std_logic;
 signal rd,wr:out std_logic;
@@ -256,5 +295,5 @@
 											      packet_type<=switch_port_out_data(7 downto 4);
 											      Dest_ack<=switch_port_out_data(3 downto 0);
-											      Rec_Data(0)<=switch_port_out_data; --récupérer la première donnée reçue !
+											      Rec_Data_i(0)<=switch_port_out_data; --récupérer la première donnée reçue !
 											      rd_ok<='1';
 									         else
@@ -268,7 +307,9 @@
 												else
 												    rd_ok<='1';
+												    Rec_Data_i(1)<=switch_port_out_data-2;
 													 if packet_type = MPI_PUT then
 													    P_len_i <= switch_port_out_data - 2;
 														  n_i<=0;
+														  
 														 Next_Ex2_state <= decode_packet_type2;
 													  elsif packet_type = MPI_GET then
@@ -284,5 +325,5 @@
 													   --rd_ok<='1';
 														P_len_i <= switch_port_out_data-2;
-														Rec_Data(1)<=switch_port_out_data;
+														Rec_Data_i(1)<=switch_port_out_data;
 														Next_Ex2_state <= ex2_init1;
 														 elsif packet_type = MPI_ACK then
@@ -291,5 +332,11 @@
 													   rd_ok<='0';
 														P_len_i <= switch_port_out_data-2;
-														Next_Ex2_state <= ex2_ack;
+														Next_Ex2_state <= ex2_ack1;
+														elsif packet_type = MPI_WIN_SYNC then
+													   n_i<=0;
+													   wr_ok<='0';
+													   rd_ok<='0';
+														P_len_i <= switch_port_out_data-2;
+														Next_Ex2_state <= ex2_Wsync;
 													  elsif packet_type = MPI_SPAWN  then
 													    Next_Ex2_state <= ex2_spawn;
@@ -307,4 +354,5 @@
                                if switch_data_available = '1'  then
 												            dest_address_i(15 downto 8) <= switch_port_out_data;
+												            Rec_data_i(2)<=switch_port_out_data;												             
 												              n_i <= n + 1;
 												                  rd_ok<='1';
@@ -315,4 +363,5 @@
 												            if switch_data_available = '1'  then
 												              dest_address_i(Word-1 downto 0) <= switch_port_out_data;
+												                Rec_data_i(3)<=switch_port_out_data;
 												                P_len_i <= P_len - 2;	
 												                Next_Ex2_state <= ex2_put1;
@@ -324,6 +373,46 @@
 								                        end if;	
 								               end if;			
-
-    when ex2_ack =>  rd_ok<='0';
+            when Ex2_ack2 =>if unsigned(p_len)>0 then
+                        If Dma_rd_grant='1' then
+			                  if n=0  then
+												  n_i<=n+1; --cycle d'attente pour la RAM
+												elsif n=1 then 
+												  dest_address_i <= dest_address+1; 
+												  n_i<=2;
+												elsif n>=2 then
+											
+													    --creer un délai sur ces signaux par rapport à src_adress
+													     
+                          n_i<=n+1;
+                          rd_ok<='1';
+--                          if n>1 then
+													dest_address_i <= dest_address+1; 
+													p_len_i <= p_len - 1;
+													--end if;
+													Get_Instr(n-2)<=Ram_data_out; --deux cycles de retard
+													Next_ex2_state <= ex2_ack2;
+												end if;	
+												end if;
+												dma_rd<='1';
+												rd_ok<='1';	
+												else
+												  if P_G=1 then
+												    dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16));
+												  else
+												    dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16));
+													Waited_get(ptr_get)(7 downto 0)<=Get_instr(0); --id
+													Waited_get(ptr_get)(15 downto 8)<=Get_instr(1); --longueur
+													Waited_get(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas
+													Waited_get(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut
+													RGET<='1';									
+													
+													Ptr_Get_i<=Ptr_Get+1; --prochain Get à traiter
+													end if;
+													Next_ex2_state <= ex2_ack3;
+													n_i<=0; --suite du process ack
+													rd_ok<='0';
+													dma_rd<='0';
+												end if;
+    when ex2_ack1 =>  rd_ok<='0';
                   if n<2 then --réception de l'acquittement.
                     n_e:=n_i;
@@ -340,13 +429,17 @@
               	     
               elsif n=3 then
-              	     n_i<=n+1;
+              	     n_i<=n+1;P_G<=0;
                     if data_to_ram(7 downto 4)=MPI_PUT then
 														Result_i<=data_to_ram;
-														dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16));
-														wr_ok<='1'; 
+														dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr,16));
+														wr_ok<='1';
+														P_G<=1; --put ou get
+														P_len_i<=x"06"; --longueur de l'entête à parcourir
 												elsif	data_to_ram(7 downto 4)=MPI_GET then
 														Result_i<=data_to_ram;
 														wr_ok<='1'; --
-														dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16));
+														P_G<=2; --put get
+														P_len_i<=x"06";--taille de l'instruction en mémoire
+														dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr,16));
 												elsif data_to_ram(7 downto 4)=MPI_SPAWN then
 														Result_i<=data_to_ram;
@@ -361,18 +454,103 @@
 														Result_i<="00000000";
 														wr_ok<='0'; --
-												end if;
-          elsif n=4 then --set acknowlege bit of the instruction
+														n_i<=n; --code inconnu !
+												end if;
+										elsif n=4 then
+										  if P_G=1 or P_G=2 then
+										    Next_ex2_state<=ex2_ack2;
+										   else
+										      Next_ex2_state<=ex2_ack3;
+										   end if;
+										   n_i<=0;
+										end if;
+          
+when ex2_ack3 => if n=0 then --set acknowlege bit of the instruction
             	     sb_start<='1';
             	     sb_bitMask<=x"20";--cinquième bit à un
             	     sb_bitval<='1';
             	     if sb_done='1' then
-            	       n_i<=5;
+            	       n_i<=1;
             	       sb_start<='0';
             	       sb_bitval<='0';
         	       end if;
-	       elsif n=5 then
+	       elsif n=1 then
 	             Next_Ex2_state<=Ex2_Ready;
 	             n_i<=0;
             end if;
+            
+    when ex2_Wsync =>  rd_ok<='0';
+                  if n<2 then --réception de la synchronisation.
+                    n_e:=n_i;
+                	   read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n);
+                	   n_i<=n_e;
+              	   elsif n=2  then
+              	     	if switch_data_available='1' then
+												n_i<=n+1;
+												rd_ok<='1';
+												
+												data_to_ram<=switch_port_out_data;
+												Result_i<=switch_port_out_data;	
+											end if;
+              	     
+              elsif n=3 then
+              	     n_i<=n+1;P_G<=0;
+                    if data_to_ram(7 downto 4)=SYNC_WSTART then
+														Result_i<=data_to_ram;
+														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16));
+														wr_ok<='1';
+														P_G<=1; --put ou get
+														P_len_i<=x"06"; --longueur de l'entête à parcourir
+												elsif	data_to_ram(7 downto 4)=SYNC_WPOST then
+														Result_i<=data_to_ram;
+														wr_ok<='1'; --
+														P_G<=2; --put get
+														P_len_i<=x"06";--taille de l'instruction en mémoire
+														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16));
+												elsif data_to_ram(7 downto 4)=SYNC_WWAIT then
+														Result_i<=data_to_ram;
+														wr_ok<='1'; --
+														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+7,16));
+												elsif data_to_ram(7 downto 4)=SYNC_WCOMP then
+														Result_i<=data_to_ram;
+														dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16));		
+														wr_ok<='1'; --
+														Next_Ex2_State<=Ex2_WCOMP;
+														n_i<=0;
+												else 
+														Result_i<="00000000";
+														wr_ok<='0'; --
+														n_i<=n; --code inconnu !
+												end if;
+										
+										end if;  
+          when Ex2_Wcomp => dma_rd<='1';
+                        rd_ok<='1';	
+                        If Dma_rd_grant='1' then
+			                  if n=0  then
+												  n_i<=n+1; --cycle d'attente pour la RAM
+												elsif n=1 then 
+												  dest_address_i <= dest_address+1; 
+												  n_i<=2;
+												elsif n=2 then
+											
+													    --creer un délai sur ces signaux par rapport à dest_adress							     
+                          n_i<=n+1;
+                          rd_ok<='1';
+													dest_address_i <= dest_address; 
+													 GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard
+													elsif n=3 then
+													  GPost_i(15 downto 8)<=Ram_data_out;
+													 n_i<=n+1;
+													 rd_ok<='1';
+													 dma_rd<='1';
+													elsif n=4 then
+													  GPost_i(15 downto 8)<=Ram_data_out;
+													 rd_ok<='0';
+													 dma_rd<='1';													 
+													n_i<=0;
+													Next_ex2_state <= ex2_set_busy;
+												end if;	
+												end if;
+												          
 			when ex2_init1 => if n<2 then 	-- execution du mpi Init
 			                 wr_ok<='0';
@@ -381,5 +559,5 @@
 												rd_ok<='1';
 												P_len_i <=P_len-1;
-												Rec_Data(n+2)<=switch_port_out_data;
+												Rec_Data_i(n+2)<=switch_port_out_data;
 												data_to_ram<=switch_port_out_data;
 												Result_i<=switch_port_out_data;
@@ -457,5 +635,5 @@
   										          Next_Ex2_state <= ex2_put2;
   										          data_to_ram<=switch_port_out_data;
-  										          rd_ok<='1';
+  										          rd_ok<='0';
   										          n_i<=0;
   										          delai:=0;
@@ -464,37 +642,41 @@
 								          end if;
 								          end if;	
-			when ex2_put2 =>	if unsigned( P_len) > 1  then 
+			when ex2_put2 =>	rd_ok<='0';
+			                 n_i<=1;
+			                 i:=to_integer(unsigned(Rec_Data_i(0)(3 downto 0)));
+			                 Rec_WPost(i)<='1'; --indiquer que ce port a emis des données !
+			               if unsigned( P_len) > 0  then 
 												
-											if switch_data_available = '1' and dma_wr_grant='1'  then
-													 
+											if switch_data_available = '1' and delai=0  then
+													   delai:=1; --une donné lue
 														 P_len_i <= P_len - 1;
-														 dest_address_i <= dest_address + 1;
 														 Next_Ex2_state <= ex2_put2;
 														 rd_ok<='1';
-														 wr_ok<='1';
 														 data_to_ram<=switch_port_out_data;
-											else
-													if switch_data_available = '1' and dma_wr_grant='0' then
-														if delai=0 then 
-														data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch
-														end if;
-														delai:=1;--indique qu'un temps supplémentaire est
-														--nécessaire pour écrire la donnée en RAM 
-													end if;
+											end if;
+											if  dma_wr_grant='1' and delai=1 then
+											 -- if n=1 then
+													  wr_ok<='1';
+													  dest_address_i <= dest_address + 1;
+													  delai:=0;--une donnée écrite
+											--	else
+											--	    dest_address_i <= dest_address ;
+											--	end if;
+														--if delai=1 then 
+														--data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch
+														--end if;
+														 
+												else
+												  dest_address_i<=dest_address;
+												  wr_ok<='0';
+												  n_i<=0;
+												end if;
+											
 													Next_Ex2_state <= ex2_put2;
-													rd_ok<='0'; --bloaque la lecture du switch pour ne pas perdre les données
-											end if;
+										
 										else 
+										  rd_ok<='0';
 										  
-											if switch_data_available = '1' and n=0 then 
-												--la dernière donnée à écrire en RAM
-												data_to_ram<=switch_port_out_data;
-												rd_ok<='0';
-												wr_ok<='1';
-												n_i<=n+1;
-											else
-												rd_ok<='1';
-												wr_ok<='0';
-											end if;
+
 											if dma_wr_grant='1' and n=1 then 
 
@@ -504,5 +686,5 @@
 											 end if;
 									    end if;
-									
+									 
 			when ex2_put3 =>			if dma_rd_grant='1' then 
 													dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
@@ -513,5 +695,5 @@
 												end if;
 			
-			when ex2_put4 => if n<=4 then     
+			when ex2_put4 => if n<=4 and n>0 then     
 			
 												dma_wr<='1';  --demander un accès exclusif au bus
@@ -522,12 +704,36 @@
 											end if;
 										if n=0 then
-											if dma_rd_grant='1' then 
-												n_i<=n+1;
-											else
+										  if RGET='1' then
+										  for i in 1 to Ptr_get loop
+										  if waited_get(i-1)(3 downto 0)=rec_data_i(0)(3 downto 0) and
+										    waited_get(i-1)(15 downto 8)=(rec_data_i(1)-2) and
+										    waited_get(i-1)(23 downto 16)=rec_data_i(2) and
+											   waited_get(i-1)(31 downto 24)=rec_data_i(3) then
+                          if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data_i(0)(7 downto 4)=MPI_PUT) then
+                          received_get(i-1)<='1';
+             													dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
+                        end if;
+                        else
+                      
+										  end if;
+										end loop;
+										end if;
+											
+											n_i<=n+1;
 											rd_ok<='1';
 											wr_ok<='0';
-											end if;
+											
 											elsif n=1 then
+											  
 												if dma_rd_grant='1' then 
+												if RGET='1' then --si on est en mode attente d'un Get
+												RGET<='0';  --Supposons tous les Gets reçus !
+                        test_wcomp:for i in 1 to Ptr_get loop --Tous les Get reçus ?
+                          if received_get(i-1)='0' then
+                            RGET<='1';    --Non !
+                        end if;
+                        end loop;
+                       
+                      end if;
 													n_i<=n+1;
 												else
@@ -536,9 +742,10 @@
 												end if;
 											elsif n=2 then
-												if dma_rd_grant='1' then 
+												if dma_rd_grant='1' and dma_wr_grant='1' then 
 													n_i<=n+1;
 													tempval:=Ram_data_out;
 													tempval(4):='1';			--SET du bit DReceived
-													tempval(1):='0';        --reset du bit DRING !!
+												                      --si get ack est détecté
+													--tempval(6):=WBusy or RGET;  -- Bit 6  Busy=0 si dernier get reçu !!
 													data_to_ram<=tempval;
 													rd_ok<='0';
@@ -547,5 +754,5 @@
 												rd_ok<='1';
 												wr_ok<='0';
-												n_i<=n-1;
+												n_i<=0;
 												end if;
 											elsif n=3 then
@@ -559,12 +766,17 @@
 													rd_ok<='0';
 													wr_ok<='1';
-													Next_Ex2_state <= ex2_put5;
-													n_i<=0;
-												end if;
+													
+													n_i<=5;
+												end if;
+										 elsif n=5 then
+										     Next_Ex2_state <= ex2_set_busy;
+										     n_i<=0;
+										     rd_ok<='0';
+													wr_ok<='0';
 											end if;
 											
 										 
 								  
-										dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction
+									--	dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction
 			when ex2_put5 => 
 										   Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put
@@ -684,4 +896,9 @@
 											rd_ok<='0';
 								    end if;
+								    i:=to_integer(unsigned(Rec_Data_i(0)(3 downto 0)));
+			               Rec_WPost(i)<='1'; --indiquer que ce port a emis des données !
+
+								    --préparer en avance l'adresse de lecture/écriture
+								    dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
 		   when ex2_get3 => wr_ok<='0';
 		                    if dma_rd_grant='1' then -- fin du mpi_get
@@ -721,12 +938,13 @@
 														n_i<=n+1;
 														tempval:=Ram_data_out;
-														tempval(2):='1';  	--mise à 1 du Bit Dreceiving
+														tempval(2):='1';  	--mise à 1 du Bit DSending
 														--tempval(5):='0'; 		--Mise à 0 du Bit Sent
 														data_to_ram<=tempval;
-														rd_ok<='0';
-														wr_ok<='1';
+														rd_ok<='1';
+														wr_ok<='0';
 													else
 													rd_ok<='1';
 													wr_ok<='0';
+													n_i<=0;
 												end if;
 											
@@ -750,4 +968,32 @@
 										 
 										dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
+					when ex2_Set_Busy => if n=0 then --set busy bit of the instruction
+            	             dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
+                          n_i<=1;
+                              if Gpost>0 then
+                                if  (rec_wpost=gpost) and RGET='0' then
+                                    Wbusy<='0';
+                                else
+                                    Wbusy<='1';
+                                end if;
+                            else
+                                n_i<=2;
+                              end if;
+                              if RGET='1' then 
+                                  WBusy<='1';
+                             end if;
+          	     elsif n=1 then
+            	     sb_start<='1';
+            	     sb_bitMask<=x"40";--6e bit à 1
+            	     sb_bitval<=WBusy;
+            	     if sb_done='1' then
+            	       n_i<=2;
+            	       sb_start<='0';
+            	       sb_bitval<='0';
+        	       end if;
+	       elsif n=2 then
+	             Next_Ex2_state<=Ex2_Ready;
+	             n_i<=0;
+            end if;
 								-- execution du barrier
 			when ex2_barrier1 => if switch_data_available = '1' then
@@ -796,11 +1042,11 @@
 			when others => Next_Ex2_state <= Ex2_Ready;
 		   end case;
- 
+        
  end process;
  
  -- sortie de la machine à etat
 --
- ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,
- switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_dma_rd_request,n)
+ ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram,
+ switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request,n)
   variable transact : std_logic_vector(Word-1 downto 0);
   begin   
@@ -813,5 +1059,5 @@
 										  dma_rd_request <= '0';
 										  barrier_completed <= '0';
-										  Ram_data_in<=(others=>'-');
+										  Ram_data_in<=(others=>'0');
 										  Ram_rd<='0';
 										  Ram_wr<='0';
@@ -824,5 +1070,5 @@
 										  dma_rd_request <= '0';
 										  barrier_completed <= '0';
-										  Ram_data_in<=(others=>'-');
+										  Ram_data_in<=(others=>'0');
 										  Ram_rd<='0';
 										  Ram_wr<='0';
@@ -838,5 +1084,5 @@
 										  Ram_rd<='0';
 										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'-');
+										  Ram_data_in<=(others=>'0');
 										  barrier_completed <= '0';
 										  AppInitReq<='0';	
@@ -850,5 +1096,5 @@
 										    Ram_rd<='0';
 											Ram_wr<='0';
-											Ram_data_in<=(others=>'-');
+											Ram_data_in<=(others=>'0');
 										    barrier_completed <= '0';
 										    AppInitReq<='0';	
@@ -861,9 +1107,9 @@
 										  Ram_rd<='0';
 										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'-');
+										  Ram_data_in<=(others=>'0');
 										  barrier_completed <= '0';
 										  AppInitReq<='0';	
 											Ready<='0';
-		when ex2_ack =>		  
+		when ex2_ack1 |ex2_Wsync =>		  
 										Ready<='0';
 										switch_port_out_rd_en<=rd_ok;
@@ -878,4 +1124,28 @@
 										sb_ram_data_out<=Ram_data_out;
 										Ram_data_in<=sb_ram_data_in;
+				when ex2_ack2|Ex2_WCOMP =>		  
+										Ready<='0';
+										switch_port_out_rd_en<='0';
+										fifo_wr_en <= '0';
+								    packet_received <= '0';
+								    AppInitReq<='0';
+								    barrier_completed <= '0';
+								    dma_rd_request <= dma_rd;
+										dma_wr_request <= '0';
+										Ram_rd<=rd_ok;
+										Ram_wr<='0';
+			when ex2_ack3 =>		  
+										Ready<='0';
+										switch_port_out_rd_en<=rd_ok;
+										fifo_wr_en <= '0';
+								    packet_received <= '0';
+								    AppInitReq<='0';
+								    barrier_completed <= '0';
+								    dma_rd_request <= sb_dma_rd_request;
+										dma_wr_request <= sb_dma_wr_request;
+										Ram_rd<=sb_ram_rd;
+										Ram_wr<=sb_ram_wr;
+										sb_ram_data_out<=Ram_data_out;
+										Ram_data_in<=sb_ram_data_in;							
 		when ex2_put1 =>  fifo_wr_en <= wr_ok;
 										  switch_port_out_rd_en <= '0';
@@ -885,5 +1155,5 @@
 										  Ram_rd<='0';
 										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'-');
+										  Ram_data_in<=(others=>'0');
 										  barrier_completed <= '0';
 										  AppInitReq<='0';	
@@ -900,5 +1170,5 @@
 											Ram_data_in<=data_to_ram;
 										end if;
-										Ram_wr<='1';
+										Ram_wr<=wr_ok;
 										Ram_rd<='0';
 										packet_received <= '0';
@@ -909,5 +1179,5 @@
 		when  ex2_put3 => 	 Ready<='0';
 										fifo_wr_en <= '0';
-									   switch_port_out_rd_en <=rd_ok;	
+									   switch_port_out_rd_en <='0';	
 										--ne pas corrompre le contenu de la RAM
 										--Ram_data_in<=data_to_ram; 					
@@ -954,5 +1224,5 @@
 										  Ram_rd<='0';
 										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'-');
+										  Ram_data_in<=(others=>'0');
 										  barrier_completed <= '0';
 										  AppInitReq<='0';	
@@ -968,5 +1238,5 @@
 										  Ram_rd<='0';
 										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'-');
+										  Ram_data_in<=(others=>'0');
 										  barrier_completed <= '0'; 
 										  AppInitReq<='0';	
@@ -1005,5 +1275,5 @@
 										  Ram_rd<='0';
 											Ram_wr<='0';
-											Ram_data_in<=(others=>'-');
+											Ram_data_in<=(others=>'0');
 										  barrier_completed <= '0'; 
 											Ready<='0';
@@ -1018,5 +1288,5 @@
 										  Ram_rd<='0';
 											Ram_wr<='0';
-											Ram_data_in<=(others=>'-');
+											Ram_data_in<=(others=>'0');
 										  barrier_completed <= '0';    
 										  AppInitReq<='0';	
@@ -1030,5 +1300,5 @@
 										  Ram_rd<='0';
 											Ram_wr<='0';
-											Ram_data_in<=(others=>'-');
+											Ram_data_in<=(others=>'0');
 										  barrier_completed <= '1';	 
 											AppInitReq<='0';	
@@ -1041,5 +1311,5 @@
 										  Ram_rd<='0';
 											Ram_wr<='0';
-											Ram_data_in<=(others=>'-');
+											Ram_data_in<=(others=>'0');
 										  barrier_completed <= '0';
 										  AppInitReq<='0';	
@@ -1054,5 +1324,5 @@
 										  Ram_rd<='0';
 											Ram_wr<='0';
-											Ram_data_in<=(others=>'-');
+											Ram_data_in<=(others=>'0');
 										  barrier_completed <= '0';										  
 										  AppInitReq<='0';	
@@ -1066,5 +1336,5 @@
 										  Ram_rd<='0';
 										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'-');
+										  Ram_data_in<=(others=>'0');
 										  barrier_completed <= '0';
 										  AppInitReq<='0';
@@ -1078,5 +1348,5 @@
 										  Ram_rd<='0';
 										  Ram_wr<='0';
-										  Ram_data_in<=(others=>'-');
+										  Ram_data_in<=(others=>'0');
 										  barrier_completed <= '0';
 										  AppInitReq<='0';	
@@ -1092,5 +1362,5 @@
 										   barrier_completed <= '0';
 										   Ready<='0';
-											Ram_data_in<=(others =>'-');
+											Ram_data_in<=(others =>'0');
 											AppInitReq<=wr_ok;
 	  when ex2_init1 =>    	fifo_wr_en <= '0'; 
@@ -1103,5 +1373,5 @@
 										   barrier_completed <= '0';
 										   Ready<='0';
-											Ram_data_in<=(others =>'-');
+											Ram_data_in<=(others =>'0');
 											AppInitReq<=wr_ok;
 											
@@ -1115,8 +1385,22 @@
 											Ram_wr<='0';
 										   barrier_completed <= '0';
-											Ram_data_in<=(others =>'-');
+											Ram_data_in<=(others =>'0');
 											AppInitReq<= not(AppInitAck);
 											Ready<='0';
-								
+
+            
+		when ex2_Set_Busy =>		  
+										Ready<='0';
+										switch_port_out_rd_en<='0';
+										fifo_wr_en <= '0';
+								    packet_received <= '0';
+								    AppInitReq<='0';
+								    barrier_completed <= '0';
+								    dma_rd_request <= sb_dma_rd_request;
+										dma_wr_request <= sb_dma_wr_request;
+										Ram_rd<=sb_ram_rd;
+										Ram_wr<=sb_ram_wr;
+										sb_ram_data_out<=Ram_data_out;
+										Ram_data_in<=sb_ram_data_in;				
 		when others => 			 Ready<='1';   -- le module est à nouveau libre
 									fifo_wr_en <= '0';
@@ -1126,5 +1410,5 @@
 										  dma_rd_request <= '0';
 										  barrier_completed <= '0';
-										  Ram_data_in<=(others=>'-');
+										  Ram_data_in<=(others=>'0');
 										  Ram_rd<='0';
 										  Ram_wr<='0';
@@ -1144,4 +1428,5 @@
 	n<=0;
 	P_len<=(others=>'0');
+	GPost<=(others =>'0');
 	else
 	  ex2_state<=next_ex2_state;
@@ -1152,4 +1437,9 @@
 	  Sent_ack<=sent_ack_i;
 	  Instr_ack<=Instr_ack_i;
+	  Ptr_Get<=Ptr_Get_i;
+	  GPost<=GPost_i;
+	  for i in 0 to 3 loop 
+	  Rec_Data(i)<=Rec_Data_i(i); 
+	  end loop;
 	 end if;
 	end if;
@@ -1233,5 +1523,19 @@
 end if;
 --end if;
-end process;		    
+end process;	
+Win_busy:process(Rec_wpost,GPost,RGET)
+begin
+  -- if Gpost>0 then
+--      if rec_wpost=gpost and RGET='0' then
+--          Wbusy<='0';
+--      else
+--         Wbusy<='1';
+--      end if;
+--    end if;
+--   if RGET='1' then 
+--     WBusy<='1';
+-- end if;
+end process Win_busy;
+	    
 end Behavioral;
 
