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Changeset 74 for PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/pa.fromHdl.tcl
- Timestamp:
- Jan 15, 2014, 2:40:01 AM (11 years ago)
- File:
-
- 1 edited
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PROJECT_CORE_MPI/CORE_MPI/BRANCHES/v1.00/pa.fromHdl.tcl
r15 r74 2 2 # PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator 3 3 4 create_project -name MPI_CORE_COMPONENTS -dir "C:/Core MPI/CORE_MPI/planAhead_run_1" -part xc6slx 100fgg484-34 create_project -name MPI_CORE_COMPONENTS -dir "C:/Core MPI/CORE_MPI/planAhead_run_1" -part xc6slx75csg484-3 5 5 set_param project.pinAheadLayout yes 6 6 set srcset [get_property srcset [current_run -impl]] … … 10 10 set_property file_type VHDL $hdlfile 11 11 set_property library NocLib $hdlfile 12 set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/ RAM_256.vhd}]]12 set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Arbiter.vhd}]] 13 13 set_property file_type VHDL $hdlfile 14 14 set_property library NocLib $hdlfile 15 set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Arbiter.vhd}]] 15 set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/proto_send.vhd}]] 16 set_property file_type VHDL $hdlfile 17 set_property library NocLib $hdlfile 18 set hdlfile [add_files [list {../SWITCH_GENERIC_16_16/Proto_receiv.vhd}]] 16 19 set_property file_type VHDL $hdlfile 17 20 set_property library NocLib $hdlfile … … 22 25 set_property file_type VHDL $hdlfile 23 26 set_property library NocLib $hdlfile 24 set hdlfile [add_files [list { round_robbin_machine.vhd}]]27 set hdlfile [add_files [list {SetBit.vhd}]] 25 28 set_property file_type VHDL $hdlfile 26 29 set_property library work $hdlfile 27 set hdlfile [add_files [list { RAM_64.vhd}]]30 set hdlfile [add_files [list {round_robbin_machine.vhd}]] 28 31 set_property file_type VHDL $hdlfile 29 32 set_property library work $hdlfile … … 52 55 set_property file_type VHDL $hdlfile 53 56 set_property library NocLib $hdlfile 57 set hdlfile [add_files [list {MPI_RMA.vhd}]] 58 set_property file_type VHDL $hdlfile 59 set_property library work $hdlfile 54 60 set hdlfile [add_files [list {MPI_CORE_SCHEDULER.vhd}]] 55 61 set_property file_type VHDL $hdlfile … … 85 91 set_property file_type VHDL $hdlfile 86 92 set_property library work $hdlfile 93 set hdlfile [add_files [list {HT_process.vhd}]] 94 set_property file_type VHDL $hdlfile 95 set_property library work $hdlfile 96 set hdlfile [add_files [list {Hold_FSM.vhd}]] 97 set_property file_type VHDL $hdlfile 98 set_property library work $hdlfile 87 99 set hdlfile [add_files [list {CORE_MPI.vhd}]] 88 100 set_property file_type VHDL $hdlfile … … 99 111 add_files "MultiMPITest.ucf" -fileset [get_property constrset [current_run]] 100 112 add_files -norecurse { {C:/Core MPI/CORE_MPI} } 101 open_rtl_design -part xc6slx 100fgg484-3113 open_rtl_design -part xc6slx75csg484-3
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